935312939557_技术文档

Document Number T1042

Rev. 2, 06/2015

Freescale Semiconductor

Data Sheet: Technical Data

T1042

QorIQ T1042, T1022 Data

Sheet

Features

• Additional peripheral interfaces

– Two high-speed USB 2.0 controllers with integrated

PHY

– Enhanced secure digital host controller with support

for high capacity memory card(SD/eSDHC/eMMC)

– Enhanced Serial peripheral interface (eSPI)

– Four I2C controllers

– Two DUARTs

– Integrated flash controller supporting NAND and

NOR flash

• e5500 cores built on Power Architecture® technology,

– T1042 has four cores and T1022 has two cores

– Each core with a private 256KB L2 cache

• 256 KB shared L3 CoreNet platform cache (CPC)

• Hierarchical interconnect fabric

– CoreNet Coherency manager supporting coherent

and non-coherent transactions with prioritization and

bandwidth allocation amongst CoreNet end-points

– 150Gbps coherent read bandwidth

– Display interface unit (DIU) with 12-bit dual data

rate

• One 32-/64-bit DDR3L/DDR4 SDRAM memory

controllers

– TDM Interface

– Four GPIO controllers supporting up to 109 general

purpose I/O signals

– ECC and interleaving support

– Two 8-channel DMA engines

– Multicore programmable interrupt controller (MPIC)

• Data Path Acceleration Architecture (DPAA)

incorporating acceleration for the following functions:

– Packet parsing, classification, and distribution

– Queue management for scheduling, packet

sequencing, and congestion management

– Hardware buffer management for buffer allocation

and de-allocation

• QUICC Engine block

– 32-bit RISC controller for flexible support of the

communications peripherals

– Serial DMA channel for receive and transmit on all

serial channels

– Cryptography Acceleration

– RegEx Pattern Matching Acceleration

– IEEE Std 1588™ support

– Two universal communication controllers,

supporting TDM, HDLC and UART

• 780 FC-PBGA package, 23 mm x 23 mm

• Parallel Ethernet interfaces

– Up to two RGMII interface

– One MII interface

• Eight SerDes lanes for high-speed peripheral interfaces

– Four PCI Express 2.0 controllers

– Two Serial ATA (SATA 3Gb/s) controllers

– Up to five SGMII interface supporting 1000 Mbps

– Up to two SGMII interface with maximum speed of

2500 Mbps

– Supports 1000Base-KX

Table of Contents

1 Overview.............................................................................................. 3

3.18 I2C interface.............................................................................. 127

3.19 GPIO interface...........................................................................131

3.20 Display interface unit................................................................ 133

3.21 TDM interface........................................................................... 135

3.22 High-speed serial interfaces (HSSI).......................................... 137

4 Hardware design considerations...........................................................160

4.1 System clocking........................................................................ 160

4.2 Power supply design..................................................................170

4.3 Decoupling recommendations...................................................175

4.4 SerDes block power supply decoupling recommendations.......175

4.5 Connection recommendations................................................... 176

4.6 Thermal......................................................................................187

4.7 Recommended thermal model...................................................188

4.8 Temperature diode.....................................................................188

4.9 Thermal management information............................................ 189

5 Package information.............................................................................192

5.1 Package parameters for the FC-PBGA......................................192

5.2 Mechanical dimensions of the FC-PBGA................................. 192

6 Security fuse processor.........................................................................194

7 Ordering information............................................................................194

7.1 Part numbering nomenclature....................................................194

7.2 Part marking.............................................................................. 195

8 Revision history....................................................................................196

2 Pin assignments....................................................................................4

2.1 780 ball layout diagrams........................................................... 4

2.2 Pinout list...................................................................................10

3 Electrical characteristics.......................................................................46

3.1 Overall DC electrical characteristics.........................................46

3.2 Power sequencing......................................................................53

3.3 Power-down requirements.........................................................56

3.4 Power-on ramp rate................................................................... 57

3.5 Power characteristics.................................................................57

3.6 Input clocks............................................................................... 61

3.7 RESET initialization..................................................................67

3.8 DDR4 and DDR3L SDRAM controller.................................... 68

3.9 eSPI interface.............................................................................75

3.10 DUART interface...................................................................... 78

3.11 Ethernet interface, Ethernet management interface, IEEE Std

1588........................................................................................... 80

3.12 QUICC Engine Specifications...................................................99

3.13 USB interface............................................................................ 104

3.14 Integrated flash controller..........................................................105

3.15 Enhanced secure digital host controller (eSDHC).....................113

3.16 Multicore programmable interrupt controller (MPIC).............. 122

3.17 JTAG controller.........................................................................124

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

2

Freescale Semiconductor, Inc.

Overview

1 Overview

The T1042 QorIQ advanced multicore processor combines with high-performance data

path acceleration and network and peripheral bus interfaces required for networking,

telecom/datacom, wireless infrastructure, and military/aerospace applications.

This chip can be used for combined control, data path, and application layer processing in

routers, switches, gateways, and general-purpose embedded computing systems. Its high

level of integration offers significant performance benefits compared to multiple discrete

devices, while also simplifying board design.

This figure shows the block diagram of the chip.

Power Architecture

e5500

256 KB

backside

L2 cache

32/64-bit

DDR3L/4

memory controller

256 KB

platform cache

32 KB

I-Cache

D-Cache

Security fuse processor

Security Monitor

CoreNet TM Coherency Manager

(Peripheral access

IFC

management unit)

PAMU

Power managment

QUICC

Engine

Parse, classify,

distribute

Security

5.4

Real-time

debug

eSDHC

Queue

Mgr.

(XoR,

CRC)

2x DUART

2xDMA

Watchpoint

cross

2.5G

1G 1G 1G

2.5G

4x I2C

trigger

Pattern

match

engine

2.2

eSPI, 4x GPIO

CoreNet

trace

Perf

Monitor

Buffer

Mgr.

2 x USB2.0 w/PHY

DIU

Aurora

8-lane, 5 GHz SerDes

Figure 1. T1042 Block diagram

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

3

Pin assignments

Power Architecture

e5500

256 KB

backside

L2 cache

32/64-bit

DDR3L/4

memory controller

256 KB

platform cache

32 KB

D-Cache

I-Cache

Security fuse processor

CoreNet TM Coherency Manager

Security Monitor

(Peripheral access

management unit)

IFC

PAMU

Power managment

QUICC

Engine

Parse, classify,

distribute

Security

5.4

Real-time

debug

eSDHC

Queue

Mgr.

(XoR,

CRC)

2x DUART

2xDMA

Watchpoint

cross

2.5G

2.5G 1G 1G 1G 1G

4x I2C

trigger

Pattern

match

engine

2.2

eSPI, 4x GPIO

CoreNet

trace

Perf

Monitor

Buffer

Mgr.

2 x USB2.0 w/PHY

DIU

Aurora

8-lane, 5 GHz SerDes

Figure 2. T1022 Block diagram

2 Pin assignments

2.1 780 ball layout diagrams

This figure shows the complete view of the T1040 ball map diagram. Figure 4, Figure 5,

Figure 6, and Figure 7 show quadrant views.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

4

Freescale Semiconductor, Inc.

Pin assignments

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

A

B

C

D

E

F

SEE DETAIL A

SEE DETAIL B

G

H

J

K

L

M

N

M

N

P

R

T

U

V

W

Y

W

Y

SEE DETAIL C

SEE DETAIL D

AA

AB

AC

AD

AE

AF

AG

AH

AA

AB

AC

AD

AE

AF

AG

AH

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

DDR Interface 1

MPIC

IFC

DUART

I2C

eSPI

Trust

System Control

Debug

ASLEEP

DFT

SYSCLK

DDR Clocking

Analog Signals

Ethernet Cont. 1

QE TDM

RTC

JTAG

Serdes 1

USB PHY 1 and 2

DIFF_SYSCLK

Power

IEEE1588

USB CLK

Ground

Ethernet MI 1

DMA Starlite TDM

No Connects

Ethernet Cont. 2

eSDHC

Figure 3. Complete BGA Map for the T1040

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

5

Pin assignments

1

2

3

4

5

6

7

8

9

10

11

12

13

14

IRQ_

IFC_

GND001

IFC_BCTL

A

B

C

D

E

F

OUT_B

AD00

AD02

AD04

AD05

AD07

AD09

AD10

AD12

AD14

AD15

RESET_

REQ_B

IFC_

AD01

IFC_

AD03

IFC_

AD06

IFC_

AD08

IFC_

AD11

IFC_

AD13

IFC_

TE

GND004

ASLEEP

EVT3_B

GND016

GND005

GND006

GND007

GND008

B

IFC_

A16

IFC_

A17

IFC_

A19

IFC_

A21

IFC_

A23

IFC_

A25

IFC_

A27

IFC_

A29

IFC_

CS_B0

IFC_

PAR1

EVT2_B

EVT4_B

IRQ01

EVT1_B

IRQ04

C

IFC_

NDDDR_

CLK

IFC_

A18

IFC_

A20

IFC_

A22

IFC_

A24

IFC_

A28

IFC_

A30

IFC_

WE0_B

IRQ03

IRQ05

EVT0_B

D

USB1_

VBUS

CLMP

USB_

E

USB_

AGND02

USB_

AGND03

CLK_

OUT

HRESET_

B

IFC_

A26

IFC_

A31

IFC_

PERR_B

GND020

GND021

IRQ00

IRQ02

GND022

GND023

AGND01

USB1_

PWR

FAULT

USB1_

DRV

VBUS

USB1_

UDP

USB1_

UDM

USB_

AGND04

USB1_

UID

SCAN_

MODE_B

TH_

TPA

PROG_

MTR

PROG_

SFP

PORESET_

B

DIFF_

SYSCLK_B

USBCLK

F

USB_

IBIAS_

REXT

USB_

G

USB_

TEST_

SEL_B

TH_

AVDD_

PLAT

AVDD_

CGA1

AVDD_

CGA2

DIFF_

SPARE1

SPARE2

SPARE3

GND055

NC02

GND030

GND035

GND050

GND056

GND063

GND072

GND082

GND031

GND041

O1VDD3

VDDC02

GND066

VDD09

G

H

J

AGND05

AGND06

AGND07

AGND08

VDD

SYSCLK

USB2_

PWR

FAULT

USB2_

UDP

USB2_

UDM

USB_

AGND09

USB2_

UID

GND036

GND037

GND038

GND039

O1VDD1

VDDC01

GND065

VDDC04

GND084

GND040

O1VDD2

GND057

VDD04

GND042

OVDD1

GND058

VDD05

H

USB2_

VBUS

CLMP

USB2_

DRV

VBUS

USB_

AGND10

USB_

AGND11

USB_

AGND12

USB_

HVDD1

USB_

OVDD1

USB_

OVDD2

J

SDHC_

CLK

SDHC_

CMD

SDHC_

DAT1

USB_

HVDD2

USB_

SVDD1

USB_

SVDD2

GND053

GND054

K

L

SDHC_

DAT3

SDHC_

DAT0

SDHC_

DAT2

SDHC_

CD_B

IRQ10

CLK12

CLK11

EVDD

CVDD

DVDD1

GND064

NC04

VDDC03

GND073

VDDC05

L

SPI_

M

SPI_

CS_B1

SPI_

CS_B2

SDHC_

WP

NC03

GND074

VDD13

GND075

VDD14

M

N

P

CS_B0

SPI_

CLK

SPI_

CS_B3

GND080

GND081

NC05

GND083

GND085

N

DMA1_

DREQ0_

B

SPI_

MISO

SPI_

MOSI

CLK10

CLK09

NC06

GND091

DVDD2

NC07

GND092

VDD18

GND093

VDD19

GND094

P

1

2

3

4

5

6

7

8

9

10

11

12

13

14

DDR Interface 1

MPIC

IFC

DUART

I2C

eSPI

Trust

System Control

Debug

ASLEEP

DFT

SYSCLK

DDR Clocking

Analog Signals

Ethernet Cont. 1

QE TDM

RTC

JTAG

Serdes 1

USB PHY 1 and 2

DIFF_SYSCLK

Power

IEEE1588

USB CLK

Ground

Ethernet MI 1

Ethernet Cont. 2

eSDHC

DMA Starlite TDM

No Connects

Figure 4. Detail A

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

6

Freescale Semiconductor, Inc.

Pin assignments

15

16

17

18

19

20

21

22

23

24

25

26

27

28

IFC_

D1_

TDI

GND002

GND003

A

B

C

D

E

F

A

RB_B1

NDDQS

CLK0

CLK1

MDQ05

MDQ01

MDQS_B0

MDQS0

MDQ07

MDQ02

FA_

ANALOG_

IFC_

RB_B0

D1_

MDQ04

D1_

MDM0

D1_

MDQ06

D1_

MDQ03

D1_

MDQ14

GND009

RTC

TMS

TDO

GND010

GND011

GND012

GND013

B

C

D

E

F

FA_

ANALOG_

G_V

IFC_

PAR0

IFC_

CS_B3

IFC_

CS_B5

IFC_

CS_B7

D1_

MDQ00

D1_

MDQ08

D1_

MDQ09

D1_

MDM1

D1_

MCKE0

D1_

MCKE1

GND014

GND015

IFC_

OE_B

IFC_

CS_B2

IFC_

AVD

IFC_

CS_B6

D1_

MDQ12

D1_

MDQ13

D1_

MDQS_B1

D1_

MDQS1

D1_

MA15

TRST_B

GND025

GND017

GND018

GND019

G1VDD01

IFC_

CS_B1

IFC_

CS_B4

AVDD_

D1

TD1_

ANODE

D1_

MDQ16

D1_

MDQ17

D1_

MDQ15

D1_

MA14

D1_

MBA2

GND024

TCK

GND026

GND027

D1_

MAPAR_

ERR_B

IFC_

CLE

IFC_

WP0_B

CKSTP_

OUT_B

TMP_

DETECT_B

D1_

MVREF

TEST_

OUT1

D1_

MDQ20

D1_

MDM2

D1_

MDQ10

D1_

MDQ11

GND028

SYSCLK

GND043

OVDD2

VDD01

GND029

G1VDD02

FA_

VL

SENSE

VDD

SENSE

GND

TD1_

CATHODE

D1_

MDQS_B2

D1_

MDQS2

D1_

MDQ28

D1_

MA09

D1_

MA12

GND032

GND044

OVDD3

GND059

VDD06

NC01

GND033

GND034

G

H

J

G

H

J

TEST_

OUT0

D1_

MDQ21

D1_

MDQ22

D1_

MDQ29

D1_

MDQ24

D1_

MA11

GND045

OVDD4

VDD02

GND068

VDD11

GND046

OVDD5

GND060

VDD07

GND047

OVDD6

VDD03

GND048

GND049

G1VDD03

D1_

TPA

D1_

MDQ18

D1_

MDQ23

D1_

MDQ25

D1_

MA08

D1_

MA07

DDRCLK

G1VDD04

G1VDD06

G1VDD07

G1VDD09

GND051

GND052

TEST_

OUT4

D1_

MDQ19

D1_

MDQS_B3

D1_

MDM3

D1_

MA06

GND061

VDD08

GND062

G1VDD05

K

L

K

L

D1_

MECC4

D1_

MECC0

D1_

MDQS3

D1_

MA04

D1_

MA05

GND067

VDD10

GND069

VDD12

GND070

GND071

TEST_

OUT5

D1_

MECC5

D1_

MDQ31

D1_

MDQ30

D1_

MA03

GND076

VDD15

GND077

VDD16

GND078

VDD17

GND079

G1VDD08

M

N

P

M

N

P

D1_

MECC1

D1_

MDM8

D1_

MDQ27

D1_

MA02

D1_

MA01

GND086

GND087

GND088

GND089

GND090

TEST_

OUT7

D1_

MDQS_B8

D1_

MDQ36

D1_

MDQ26

D1_

MDIC0

VDD20

GND095

VDD21

GND096

VDD22

GND097

G1VDD10

GND098

G1VDD11

15

16

17

18

19

20

21

22

23

24

25

26

27

28

DDR Interface 1

MPIC

IFC

DUART

I2C

eSPI

Trust

RTC

System Control

Debug

ASLEEP

DFT

SYSCLK

JTAG

DDR Clocking

Analog Signals

Serdes 1

USB PHY 1 and 2

DIFF_SYSCLK

Power

IEEE1588

USB CLK

Ground

Ethernet MI 1

Ethernet Cont. 1

QE TDM

Ethernet Cont. 2

eSDHC

DMA Starlite TDM

No Connects

Figure 5. Detail B

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

7

Pin assignments

1

2

3

4

5

6

7

8

9

10

11

12

13

14

DMA1_

DDONE0_

B

TDMA_

TSYNC

TDMA_

RQ

TDMB_

TSYNC

TDMB_

RQ

NC08

GND099

DVDD3

GND100

VDDC06

GND101

VDD23

GND102

VDD24

R

TDMA_

TXD

TDMB_

RSYNC

TDMB_

TXD

GND108

GND109

NC09

NC11

NC12

NC14

NC15

NC19

GND110

GND119

GND127

GND138

GND143

NC20

L1VDD1

L1VDD2

LVDD1

LVDD2

NC16

NC10

GND120

NC13

GND111

VDDC08

GND128

VDDC11

GND144

NC23

VDDC07

GND121

VDDC10

GND140

NC18

GND112

VDDC09

GND129

VDDC12

GND145

VDD28

GND122

VDD36

GND113

VDD32

T

DMA1_

DACK0_

B

TDMA_

RSYNC

TDMA_

RXD

TDMB_

RXD

IRQ11

U

DMA2_

DREQ0_

B

IIC1_

SDA

IIC3_

SCL

IIC2_

SCL

UART2_

RTS_B

GND130

VDD40

V

IIC1_

SCL

IIC3_

SDA

UART2_

SIN

GND136

GND137

GND139

NC17

GND141

S1VDD7

S1GND05

S1GND10

W

DMA2_

DDONE0_

B

UART1_

RTS_B

UART1_

CTS_B

IIC2_

SDA

UART2_

CTS_B

S1GND01

Y

DMA2_

DACK0_

B

SD1_

IMP_

CAL_RX

SD1_

REF_

CLK1_N

UART1_

SIN

UART1_

SOUT

IIC4_

SCL

UART2_

SOUT

NC21

NC22

GND148

NC25

AA

AB

AC

AD

AE

AF

AG

AH

TSEC_

TRIG_IN

1

SD1_

REF_

CLK1_P

IIC4_

SDA

SENSE

VDDC

SENSE

GNDC

IRQ08

GND150

IRQ06

GND151

IRQ09

GND152

NC24

NC26

AB

EC1_

RX_

ER

EC1_

TX_

ER

EC2_

GTX_

CLK125

TSEC_

ALARM_OUT

2

TSEC_

CLK_

IN

EC1_

COL

EC1_

TXD3

X1VDD1

X1GND01 X1GND02

X1VDD2

X1GND10

X1GND15

X1GND03 X1GND04

AC

EC1_

RX_

CLK

TSEC_

CLK_

OUT

TSEC_

PULSE_OUT X1GND09

2

SD1_

TX0_

P

SD1_

TX1_

P

SD1_

TX2_

P

SD1_

TX3_

P

EC1_

RXD3

EC1_

TXD2

GND157

IRQ07

GND158

TSEC_

AD

TSEC_

EC2_

GTX_

CLK

SD1_

TX0_

N

SD1_

TX1_

N

SD1_

TX2_

N

SD1_

TX3_

N

EC1_

RXD2

EC1_

TXD0

EC1_

TXD1

EC2_

TXD0

GND160

TRIG_IN PULSE_OUT

X1GND14

GND163

2

1

AE

EC1_

GTX_

CLK

EC1_

TX_

CTL

TSEC_

ALARM_OUT

1

EC2_

TX_

CTL

EC1_

RXD1

EC1_

RXD0

EC2_

TXD2

EC2_

TXD1

S1GND13 S1GND14 S1GND15 S1GND16 S1GND17

AF

EC1_

RX_

CTL

EC1_

GTX_

EC2_

RX_

CTL

SD1_

RX0_

N

SD1_

RX1_

N

SD1_

RX2_

N

SD1_

RX3_

N

EC2_

TXD3

EC2_

RXD1

GND165

GND166

GND167

S1GND24

S1GND29

S1GND25

S1GND30

CLK125

AG

EC2_

RX_

CLK

SD1_

RX0_

P

SD1_

RX1_

P

SD1_

RX2_

P

SD1_

RX3_

P

EMI1_

MDC

EMI1_

MDIO

EC2_

RXD3

EC2_

RXD2

EC2_

RXD0

GND171

AH

1

2

3

4

5

6

7

8

9

10

11

12

13

14

DDR Interface 1

MPIC

IFC

DUART

I2C

eSPI

Trust

System Control

Debug

ASLEEP

DFT

SYSCLK

DDR Clocking

Analog Signals

Ethernet Cont. 1

QE TDM

RTC

JTAG

Serdes 1

USB PHY 1 and 2

DIFF_SYSCLK

Power

IEEE1588

USB CLK

Ground

Ethernet MI 1

DMA Starlite TDM

No Connects

Ethernet Cont. 2

eSDHC

Figure 6. Detail C

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

8

Freescale Semiconductor, Inc.

Pin assignments

15

16

17

18

19

20

21

22

23

24

25

26

27

28

D1_

MDQS8

D1_

MECC6

D1_

MDQ37

D1_

MCK1

D1_

MCK_B1

GND103

VDD25

GND104

VDD26

GND105

VDD27

G1VDD12

GND106

GND107

R

D1_

VDD29

GND123

VDD37

GND114

VDD33

VDD30

GND124

VDD38

GND115

VDD34

VDD31

GND125

VDD39

GND116

VDD35

G1VDD13

G1VDD14

GND117

GND118

MECC2

MECC7

MDQ32

MCK0

MCK_B0

T

TEST_

OUT6

D1_

MECC3

D1_

MDQ33

D1_

MDM4

D1_

MDIC1

GND126

G1VDD15

U

D1_

MAPAR_

OUT

TEST_

OUT3

D1_

MDQ45

D1_

MDQ40

D1_

MDQS_B4

D1_

MA00

GND131

S1VDD2

GND132

S1VDD4

GND133

S1VDD6

GND134

GND135

V

TEST_

OUT2

D1_

MDQ44

D1_

MDQ41

D1_

MDQS4

D1_

MDQ38

D1_

MBA1

S1VDD1

S1VDD3

S1VDD5

GND142

G1VDD16

W

SD1_

PLL1_

TPA

SD1_

PLL2_

TPA

SD1_

IMP_

CAL_TX

TEST_

OUT8

D1_

MDQS_B5

D1_

MDM5

D1_

MDQ39

D1_

MA10

D1_

MBA0

S1GND02 S1GND03 S1GND04

GND146

GND147

Y

AGND_

SD1_PLL

1

SD1_

REF_

AGND_

SD1_PLL

2

D1_

S1GND06

S1GND07

S1GND11

S1GND08

S1GND09

S1GND12

X1VDD5

GND149

G1VDD17

MDQ42

MDQS5

MDQ35

MDQ34

MRAS_B

CLK2_N

AA

AB

AC

AD

AE

AF

AG

AH

AA

AB

AC

AD

AE

AF

AG

AH

SD1_

PLL1_

TPD

AVDD_

SD1_

PLL1

SD1_

REF_

CLK2_P

SD1_

PLL2_

TPD

AVDD_

SD1_

PLL2

D1_

MDQ47

D1_

MDQ46

D1_

MDQ52

D1_

MWE_B

D1_

MCS_B0

GND153

GND154

GND156

D1_

MDQ43

D1_

MDQ54

D1_

MDQ53

D1_

MCS_B1

D1_

MCAS_B

X1VDD3

X1GND11

X1GND16

X1GND05 X1GND06

X1VDD4

X1GND12

X1GND17

X1GND07 X1GND08

GND155

SD1_

TX4_

P

SD1_

TX5_

P

SD1_

TX6_

P

SD1_

TX7_

P

D1_

MDQ50

D1_

MDM6

D1_

MDQ49

D1_

MDQ48

D1_

MODT0

X1GND13

X1GND18

GND164

GND159

G1VDD18

SD1_

TX4_

N

SD1_

TX5_

N

SD1_

TX6_

N

SD1_

TX7_

N

D1_

MDQ51

D1_

MDQ55

D1_

MDQS6

D1_

MODT1

D1_

MA13

GND161

GND162

D1_

MDQ59

D1_

MDQ63

D1_

MDM7

D1_

MDQS_B6

D1_

MDQ60

D1_

MCS_B3

S1GND18 S1GND19 S1GND20 S1GND21 S1GND22 S1GND23

G1VDD19

SD1_

RX4_

N

SD1_

RX5_

N

SD1_

RX6_

N

SD1_

RX7_

N

D1_

NC_

DET

S1GND26

S1GND31

S1GND27

S1GND32

S1GND28

S1GND33

GND168

GND169

GND170

MDQS7

MDQ56

MCS_B2

SD1_

RX4_

P

SD1_

RX5_

P

SD1_

RX6_

P

SD1_

RX7_

P

D1_

MDQ58

D1_

MDQ62

D1_

MDQS_B7

D1_

MDQ57

D1_

MDQ61

NC_

1040

15

16

17

18

19

20

21

22

23

24

25

26

27

28

DDR Interface 1

MPIC

IFC

DUART

I2C

eSPI

Trust

RTC

System Control

Debug

ASLEEP

DFT

SYSCLK

JTAG

DDR Clocking

Analog Signals

Ethernet Cont. 1

QE TDM

Serdes 1

USB PHY 1 and 2

DIFF_SYSCLK

Power

IEEE1588

USB CLK

Ground

Ethernet MI 1

Ethernet Cont. 2

eSDHC

DMA Starlite TDM

No Connects

Figure 7. Detail D

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

9

Pin assignments

2.2 Pinout list

This table provides the pinout listing for the T1040 by bus. Primary functions are bolded

in the table.

Table 1. Pinout list by bus

Signal

Signal description

Package

type

Power supply

Notes

number

DDR SDRAM Memory Interface 1

D1_MA00

D1_MA01

D1_MA02

D1_MA03

D1_MA04

D1_MA05

D1_MA06

D1_MA07

D1_MA08

D1_MA09

D1_MA10

D1_MA11

D1_MA12

D1_MA13

D1_MA14

D1_MA15

Address

V28

N28

N27

M28

L27

O

I

G1V_DD

---

G1V_DD

---

25

1, 6, 25

25

---

25

---

2

L28

K28

J28

J27

G27

Y27

H28

G28

AE28

E27

D28

D1_MAPAR_ERR_B

D1_MAPAR_OUT

D1_MBA0

Address Parity Error

Address Parity Out

Bank Select

F28

V27

O

Y28

D1_MBA1

Bank Select

W28

E28

D1_MBA2

Bank Select

D1_MCAS_B

D1_MCK0

Column Address Strobe

Clock

AC28

T27

D1_MCK1

Clock

R27

D1_MCKE0

D1_MCKE1

D1_MCK0_B

D1_MCK1_B

D1_MCS0_B

D1_MCS1_B

D1_MCS2_B

Clock Enable

Clock Complement

Chip Select

C27

C28

2

T28

---

R28

AB28

AC27

AG27

Chip Select

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

10

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

D1_MCS3_B

Chip Select

AF28

P28

U28

B22

C25

F23

K26

U26

Y24

AD24

AF24

N24

C21

A22

A26

B26

B21

A21

B24

A25

C23

C24

F25

F26

D22

D23

B27

E25

E23

E24

J23

O

IO

O

G1V_DD

---

D1_MDIC0

D1_MDIC1

D1_MDM0

D1_MDM1

D1_MDM2

D1_MDM3

D1_MDM4

D1_MDM5

D1_MDM6

D1_MDM7

D1_MDM8

D1_MDQ00

D1_MDQ01

D1_MDQ02

D1_MDQ03

D1_MDQ04

D1_MDQ05

D1_MDQ06

D1_MDQ07

D1_MDQ08

D1_MDQ09

D1_MDQ10

D1_MDQ11

D1_MDQ12

D1_MDQ13

D1_MDQ14

D1_MDQ15

D1_MDQ16

D1_MDQ17

D1_MDQ18

D1_MDQ19

D1_MDQ20

D1_MDQ21

D1_MDQ22

D1_MDQ23

D1_MDQ24

D1_MDQ25

Driver Impedence Calibration

G1V_DD

3

Driver Impedence Calibration

3

Data Mask

Data

1, 25

---

O

IO

Data

---

Data

---

Data

---

Data

---

Data

---

Data

---

Data

---

Data

---

Data

---

Data

---

Data

---

Data

---

Data

---

Data

---

Data

---

Data

---

Data

---

Data

---

Data

K23

F22

H22

H23

J24

---

Data

---

Data

---

Data

---

Data

---

Data

H26

J25

---

Data

---

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

11

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

D1_MDQ26

D1_MDQ27

D1_MDQ28

D1_MDQ29

D1_MDQ30

D1_MDQ31

D1_MDQ32

D1_MDQ33

D1_MDQ34

D1_MDQ35

D1_MDQ36

D1_MDQ37

D1_MDQ38

D1_MDQ39

D1_MDQ40

D1_MDQ41

D1_MDQ42

D1_MDQ43

D1_MDQ44

D1_MDQ45

D1_MDQ46

D1_MDQ47

D1_MDQ48

D1_MDQ49

D1_MDQ50

D1_MDQ51

D1_MDQ52

D1_MDQ53

D1_MDQ54

D1_MDQ55

D1_MDQ56

D1_MDQ57

D1_MDQ58

D1_MDQ59

D1_MDQ60

D1_MDQ61

D1_MDQ62

D1_MDQ63

Data

P26

N25

IO

G1V_DD

---

G1V_DD

---

G25

H25

M26

M25

T25

U25

AA26

AA25

P25

R25

W26

Y25

V24

W23

AA22

AC22

W22

V23

AB24

AB23

AD26

AD25

AD23

AE22

AB25

AC25

AC23

AE23

AG25

AH25

AH22

AF22

AF26

AH26

AH23

AF23

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

12

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

D1_MDQS0

D1_MDQS1

D1_MDQS2

D1_MDQS3

D1_MDQS4

D1_MDQS5

D1_MDQS6

D1_MDQS7

D1_MDQS8

Data Strobe

A24

D26

G24

L25

IO

O

G1V_DD

---

2

Data Strobe

G1V_DD

Data Strobe

W25

AA23

AE25

AG24

R23

A23

Data Strobe

D1_MDQS0_B

D1_MDQS1_B

D1_MDQS2_B

D1_MDQS3_B

D1_MDQS4_B

D1_MDQS5_B

D1_MDQS6_B

D1_MDQS7_B

D1_MDQS8_B

D1_MECC0

Data Strobe

D25

G23

K25

Data Strobe

V25

Data Strobe

Y23

Data Strobe

AF25

AH24

P23

Data Strobe

Error Correcting Code

On Die Termination

Row Address Strobe

Write Enable

L24

D1_MECC1

N23

T23

D1_MECC2

D1_MECC3

U23

L23

D1_MECC4

D1_MECC5

M23

R24

T24

D1_MECC6

D1_MECC7

D1_MODT0

AD28

AE27

AA28

AB27

H21

F21

D1_MODT1

O

2

D1_MRAS_B

D1_MWE_B

TEST_OUT0

TEST_OUT1

TEST_OUT2

TEST_OUT3

TEST_OUT4

TEST_OUT5

TEST_OUT6

TEST_OUT7

O

25

12

O

Test Signal

O

Test Signal

O

Test Signal

W21

V21

O

Test Signal

O

Test Signal

K22

O

Test Signal

M22

U22

P22

O

Test Signal

O

Test Signal

O

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

13

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

TEST_OUT8

Test Signal

Y21

O

G1V_DD

12

Integrated Flash Controller

IFC_A16

IFC Address

C5

C6

O

OV_DD

1, 5

1, 4

1

IFC_A17

IFC_A18

D7

IFC_A19

C7

IFC_A20

D8

IFC_A21/cfg_dram_type

IFC_A22

C8

D9

IFC_A23

C9

1

IFC_A24

D10

C10

1

IFC_A25/GPIO2_25/

1

IFC_WP1_B

IFC_A26/GPIO2_26/

IFC_WP2_B

IFC Address

E11

C11

O

OV_DD

1

IFC_A27/GPIO2_27/

IFC_WP3_B

IFC_A28/GPIO2_28

IFC Address

D11

C12

O

OV_DD

1

IFC_A29/GPIO2_29/

IFC_RB2_B

IFC_A30/GPIO2_30/

IFC_RB3_B

IFC Address

D12

E12

O

OV_DD

1

IFC_A31/GPIO2_31/

IFC_RB4_B

IFC_AD00/cfg_gpinput0

IFC_AD01/cfg_gpinput1

IFC_AD02/cfg_gpinput2

IFC_AD03/cfg_gpinput3

IFC_AD04/cfg_gpinput4

IFC_AD05/cfg_gpinput5

IFC_AD06/cfg_gpinput6

IFC_AD07/cfg_gpinput7

IFC_AD08/cfg_rcw_src0

IFC_AD09/cfg_rcw_src1

IFC_AD10/cfg_rcw_src2

IFC_AD11/cfg_rcw_src3

IFC_AD12/cfg_rcw_src4

IFC_AD13/cfg_rcw_src5

IFC_AD14/cfg_rcw_src6

IFC_AD15/cfg_rcw_src7

IFC Address / Data

A4

B5

IO

OV_DD

4

A5

B6

A6

A7

B8

A8

B9

A9

A10

B11

A11

B12

A12

A13

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

14

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

IFC_AVD

IFC Address Valid

D17

A14

F16

A17

A19

C13

E15

D16

C16

E17

C17

D18

C19

D14

A16

D15

C15

C14

E14

C12

O

IO

O

IO

I

OV_DD

1, 5

1

IFC_BCTL

IFC Buffer control

IFC Command Latch Enable

IFC Clock

OV_DD

IFC_CLE/cfg_rcw_src8

IFC_CLK0

1, 4

1

IFC_CLK1

IFC Clock

1

IFC_CS0_B

IFC Chip Select

1, 6

1

IFC_CS1_B/GPIO2_10

IFC_CS2_B/GPIO2_11

IFC_CS3_B/GPIO2_12

IFC_CS4_B/GPIO1_09

IFC_CS5_B/GPIO1_10

IFC_CS6_B/GPIO1_11

IFC_CS7_B/GPIO1_12

IFC_NDDDR_CLK

IFC_NDDQS

IFC Chip Select

IFC NAND DDR Clock

IFC DQS Strobe

IFC Output Enable

IFC Address & Data Parity

IFC Parity Error

---

IFC_OE_B/cfg_eng_use1

IFC_PAR0/GPIO2_13

IFC_PAR1/GPIO2_14

IFC_PERR_B/GPIO2_15

1, 21

---

1, 6

1

IFC_RB2_B/IFC_A29/

IFC Ready / Busy CS 2

I

GPIO2_29

IFC_RB3_B/IFC_A30/

GPIO2_30

IFC Ready / Busy CS 3

IFC Ready / Busy CS 4

D12

E12

I

OV_DD

1

IFC_RB4_B/IFC_A31/

GPIO2_31

IFC_RB0_B

IFC Ready / Busy CS0

IFC Ready / Busy CS1

B15

A15

B14

I

OV_DD

6

IFC_RB1_B

6

IFC_TE/cfg_ifc_te

IFC External Transceiver

Enable

O

1, 4

IFC_WE0_B/cfg_eng_use0

IFC Write Enable

IFC Write Protect

D13

C10

O

OV_DD

1, 21

1

IFC_WP1_B/IFC_A25/

GPIO2_25

IFC_WP2_B/IFC_A26/

GPIO2_26

IFC Write Protect

E11

C11

F17

O

OV_DD

1

IFC_WP3_B/IFC_A27/

GPIO2_27

1

IFC_WP0_B/cfg_eng_use2

1, 21

DUART

UART1_CTS_B/GPIO1_21/

Clear To Send

Y2

I

DV_DD

1

UART3_SIN

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

15

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

UART1_RTS_B/GPIO1_19/

Ready to Send

Y1

O

DV_DD

1

UART3_SOUT

UART1_SIN/GPIO1_17

Receive Data

Transmit Data

Clear To Send

AA1

AA2

Y4

I

O

I

DV_DD

1

UART1_SOUT/GPIO1_15

UART2_CTS_B/GPIO1_22/

UART4_SIN

UART2_RTS_B/GPIO1_20/

Ready to Send

V4

O

DV_DD

1

UART4_SOUT

UART2_SIN/GPIO1_18

Receive Data

Transmit Data

W4

AA4

Y2

I

O

I

DV_DD

1

UART2_SOUT/GPIO1_16

UART3_SIN/UART1_CTS_B/ Receive Data

GPIO1_21

UART3_SOUT/

UART1_RTS_B/GPIO1_19

Transmit Data

Y1

Y4

V4

O

I

DV_DD

1

UART4_SIN/UART2_CTS_B/ Receive Data

GPIO1_22

UART4_SOUT/

Transmit Data

O

UART2_RTS_B/GPIO1_20

I2C

IIC1_SCL

IIC1_SDA

IIC2_SCL

IIC2_SDA

Serial Clock (supports PBL)

Serial Data (supports PBL)

Serial Clock

W1

V1

V3

Y3

IO

DV_DD

7, 8

Serial Data

eSPI Interface

SPI_CLK

SPI Clock

N1

M1

O

CV_DD

1

SPI_CS0_B/GPIO2_00/

SPI Chip Select

SDHC_DAT4

SPI_CS1_B/GPIO2_01/

SDHC_DAT5/

SDHC_CMD_DIR

SPI Chip Select

M2

M3

N3

O

CV_DD

1

SPI_CS2_B/GPIO2_02/

SDHC_DAT6/

SDHC_DAT0_DIR

SPI_CS3_B/GPIO2_03/

SDHC_DAT7/

SDHC_DAT123_DIR/

SDHC_CLK_SYNC_OUT

SPI_MISO

SPI_MOSI

Master In Slave Out

Master Out Slave In

P1

P2

I

CV_DD

1

IO

---

Programmable Interrupt Controller

IRQ00

IRQ01

External Interrupt

F7

D3

I

O1V_DD

1

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

16

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

IRQ02

External Interrupt

E9

D1

I

O1V_DD

1

IRQ03/GPIO1_23/SDHC_VS

IRQ04/GPIO1_24

IRQ05/GPIO1_25

IRQ06/GPIO1_26

IRQ07/GPIO1_27

IRQ08/GPIO1_28

IRQ09/GPIO1_29

External Interrupt

O1V_DD

L1V_DD

CV_DD

D4

D5

AB4

AD5

AB1

AC5

L4

IRQ10/GPIO1_30/

SDHC_CLK_SYNC_IN

IRQ11/GPIO1_31

External Interrupt

Interrupt Output

U3

A3

I

DV_DD

1

IRQ_OUT_B/EVT9_B

O

O1V_DD

1, 6, 7

Trust

TMP_DETECT_B

Tamper Detect

F19

I

OV_DD

1

System Control

HRESET_B

Hard Reset

E8

F13

B3

IO

I

O1V_DD

7, 27

26

PORESET_B

RESET_REQ_B

Power On Reset

Reset Request (POR or Hard)

O

1, 5

Power Management

ASLEEP/GPO1_13

SYSCLK

Asleep

B2

G15

J21

B17

O

I

O1V_DD

OV_DD

1

SYSCLK

System Clock

DDR Clocking

DDR Controller Clock

RTC

17

1

DDRCLK

I

RTC/GPIO1_14

Real Time Clock

Debug

I

OV_DD

CKSTP_OUT_B

CLK_OUT

Checkstop Out

Clock Out

F18

E6

O

OV_DD

O1V_DD

DV_DD

1, 6, 7

---

EVT5_B/IIC4_SCL/GPIO4_02/ Event 5

AA3

IO

---

DIU_HSYNC

EVT6_B/IIC4_SDA/GPIO4_03/ Event 6

DIU_VSYNC

AB3

AA5

Y5

IO

DV_DD

---

EVT7_B/DMA2_DACK0_B/

Event 7

GPIO4_08/TDM_RFS

EVT8_B/DMA2_DDONE0_B/ Event 8

GPIO4_09/TDM_RCK

EVT9_B/IRQ_OUT_B

Event 9

Event 0

A3

D6

IO

O1V_DD

---

9

EVT0_B

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

17

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

EVT1_B

EVT2_B

EVT3_B

EVT4_B

Event 1

C4

C1

C2

C3

IO

O1V_DD

---

Event 2

Event 3

Event 4

O1V_DD

6, 22

---

DFT

SCAN_MODE_B

TEST_SEL_B

Reserved

F9

I

O1V_DD

10

23

G8

JTAG

TCK

Test Clock

E18

A18

C18

B18

D19

I

OV_DD

---

9

TDI

Test Data In

Test Data Out

Test Mode Select

Test Reset

TDO

O

I

---

9

TMS

TRST_B

I

9

Analog Signals

D1_MVREF

D1_TPA

SSTL Reference Voltage

Reserved for internal use only

Thermal diode anode

F20

J20

C20

B20

G6

IO

-

G1V_DD/2

---

-

12

15

12

19

12

FA_ANALOG_G_V

FA_ANALOG_PIN

SPARE1

SPARE2

H6

-

SPARE3

J6

-

TD1_ANODE

TD1_CATHODE

TH_TPA

E21

G21

F10

IO

-

Thermal diode cathode

Reserved for internal use only

Serdes 1

-

SD1_IMP_CAL_RX

SD1_IMP_CAL_TX

SerDes Receive Impedence

Calibration

AA12

Y20

I

S1V_DD

X1V_DD

11

16

SerDes Transmit Impedance

Calibration

SD1_PLL1_TPA

SD1_PLL1_TPD

SD1_PLL2_TPA

SD1_PLL2_TPD

SD1_REF_CLK1_N

Reserved for internal use only

Y15

AB15

Y19

O

I

AVDD_SD1_PLL1

X1V_DD

12

---

AVDD_SD1_PLL2

X1V_DD

AB19

AA14

SerDes PLL 1 Reference Clock

Complement

S1V_DD

SD1_REF_CLK1_P

SD1_REF_CLK2_N

SerDes PLL 1 Reference Clock

AB14

AA18

I

S1V_DD

---

SerDes PLL 2 Reference Clock

Complement

SD1_REF_CLK2_P

SerDes PLL 2 Reference Clock

AB18

I

S1V_DD

---

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

18

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

SD1_RX0_N

SerDes Receive Data

(negative)

AG10

AH10

AG11

AH11

AG13

AH13

AG14

AH14

AG16

AH16

AG17

AH17

AG19

AH19

AG20

AH20

AE10

AD10

AE11

AD11

AE13

AD13

I

S1V_DD

---

SD1_RX0_P

SD1_RX1_N

SD1_RX1_P

SD1_RX2_N

SD1_RX2_P

SD1_RX3_N

SD1_RX3_P

SD1_RX4_N

SD1_RX4_P

SD1_RX5_N

SD1_RX5_P

SD1_RX6_N

SD1_RX6_P

SD1_RX7_N

SD1_RX7_P

SD1_TX0_N

SD1_TX0_P

SD1_TX1_N

SD1_TX1_P

SD1_TX2_N

SD1_TX2_P

SerDes Receive Data

(positive)

S1V_DD

X1V_DD

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SerDes Transmit Data

(negative)

O

SerDes Transmit Data

(positive)

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

19

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

SD1_TX3_N

SD1_TX3_P

SD1_TX4_N

SD1_TX4_P

SD1_TX5_N

SD1_TX5_P

SD1_TX6_N

SD1_TX6_P

SD1_TX7_N

SD1_TX7_P

SerDes Transmit Data

(negative)

AE14

AD14

AE16

AD16

AE17

AD17

AE19

AD19

AE20

AD20

O

X1V_DD

---

SerDes Transmit Data

(positive)

X1V_DD

---

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

USB PHY 1 & 2

USB1_DRVVBUS

USB1_PWRFAULT

USB PHY Digital signal - Drive

VBUS

F6

F5

O

I

USB_HV_DD

---

USB PHY Digital signal -

Power Fault

USB1_UDM

USB PHY Data Minus

USB PHY Data Plus

USB PHY ID Detect

USB PHY VBUS

F2

F1

F4

E4

J5

IO

I

USB_HV_DD

USB_OV_DD

USB_HV_DD

---

USB1_UDP

USB1_UID

USB1_VBUSCLMP

USB2_DRVVBUS

I

USB PHY Digital signal - Drive

VBUS

O

USB2_PWRFAULT

USB PHY Digital signal -

Power Fault

H5

I

USB_HV_DD

---

USB2_UDM

USB PHY Data Minus

USB PHY Data Plus

USB PHY ID Detect

USB PHY VBUS

H2

H1

H4

J4

IO

I

USB_HV_DD

USB_OV_DD

USB_HV_DD

USB_OV_DD

---

20

USB2_UDP

USB2_UID

USB2_VBUSCLMP

USB_IBIAS_REXT

I

USB PHY Impedance

Calibration

G4

IO

IEEE1588

TSEC_1588_ALARM_OUT1/ Alarm Out 1

AF5

O

LV_DD

1

GPIO3_03

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

20

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

TSEC_1588_ALARM_OUT2/ Alarm Out 2

GPIO3_04/EMI1_MDC

AC7

AC8

AD7

AE6

AD8

AB6

AE5

O

I

LV_DD

1

TSEC_1588_CLK_IN/

Clock In

LV_DD

GPIO3_00

TSEC_1588_CLK_OUT/

GPIO3_05

Clock Out

Pulse Out 1

Pulse Out 2

Trigger In 1

Trigger In 2

O

I

TSEC_1588_PULSE_OUT1/

GPIO3_06

TSEC_1588_PULSE_OUT2/

GPIO3_07

TSEC_1588_TRIG_IN1/

GPIO3_01

TSEC_1588_TRIG_IN2/

I

GPIO3_02/EMI1_MDIO

Ethernet Management Interface 1

EMI1_MDC

Management Data Clock

AH3

AC7

O

L1V_DD

LV_DD

---

1

EMI1_MDC/

Management Data Clock

TSEC_1588_ALARM_OUT2/

GPIO3_04

EMI1_MDIO

Management Data In/Out

AH4

AE5

IO

L1V_DD

LV_DD

---

EMI1_MDIO/

TSEC_1588_TRIG_IN2/

GPIO3_02

Ethernet controller 1 and GPIO

EC1_COL/GPIO3_10/

MII_COL/MAC2_MII_COL

Collison Detect

AC1

IO

O

L1V_DD

---

1

EC1_GTX_CLK/GPIO3_16/

MII_TX_CLK/

MAC2_GTX_CLK/

MAC2_MII_TX_CLK

Transmit Clock Out

Reference Clock

AF3

EC1_GTX_CLK125/

GPIO3_17/MII_CRS/

MAC2_GTX_CLK125/

MAC2_MII_CRS

AG3

I

L1V_DD

1

EC1_RXD0/GPIO3_21/

MII_RXD0/MAC2_RXD0/

MAC2_MII_RXD0

Receive Data

AF2

AF1

AE1

I

L1V_DD

1

EC1_RXD1/GPIO3_20/

MII_RXD1/MAC2_RXD1/

MAC2_MII_RXD1

EC1_RXD2/GPIO3_19/

MII_RXD2/MAC2_RXD2/

MAC2_MII_RXD2

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

21

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

EC1_RXD3/GPIO3_18/

MII_RXD3/MAC2_RXD3/

MAC2_MII_RXD3

Receive Data

AD2

AD1

AG2

AC2

AE3

AE4

AD3

AC3

AF4

AC4

I

L1V_DD

1

EC1_RX_CLK/GPIO3_23/

MII_RX_CLK/MAC2_RX_CLK/

MAC2_MII_RX_CLK

Receive Clock

Receive Data Valid

Receive Error

Transmit Data

Transmit Enable

Transmit Error

L1V_DD

EC1_RX_CTL/GPIO3_22/

MII_RX_DV/MAC2_RX_CTL/

MAC2_MII_RX_DV

I

EC1_RX_ER/GPIO3_09/

MII_RX_ER/

MAC2_MII_RX_ER

IO

O

IO

---

1

EC1_TXD0/GPIO3_14/

MII_TXD0/MAC2_TXD0/

MAC2_MII_TXD0

EC1_TXD1/GPIO3_13/

MII_TXD1/MAC2_TXD1/

MAC2_MII_TXD1

1

EC1_TXD2/GPIO3_12/

MII_TXD2/MAC2_TXD2/

MAC2_MII_TXD2

1

EC1_TXD3/GPIO3_11/

MII_TXD3/MAC2_TXD3/

MAC2_MII_TXD3

1

EC1_TX_CTL/GPIO3_15/

MII_TX_EN/MAC2_TX_CTL/

MAC2_MII_TX_EN

1, 14

14

EC1_TX_ER/GPIO3_08/

MII_TX_ER/

MAC2_MII_TX_ER

Ethernet controller 2 and GPIO

EC2_GTX_CLK/GPIO4_28

Transmit Clock Out

AE8

AC6

AH8

AG7

AH7

AH6

AH5

AG8

AE7

AF7

AF6

AG5

AF8

O

I

LV_DD

1

EC2_GTX_CLK125/GPIO4_29 Reference Clock

1

EC2_RXD0/GPIO3_31

EC2_RXD1/GPIO3_30

EC2_RXD2/GPIO3_29

EC2_RXD3/GPIO3_28

EC2_RX_CLK/GPIO4_31

EC2_RX_CTL/GPIO4_30

EC2_TXD0/GPIO3_27

EC2_TXD1/GPIO3_26

EC2_TXD2/GPIO3_25

EC2_TXD3/GPIO3_24

EC2_TX_CTL/GPIO4_27

Receive Data

Receive Clock

Receive Data Valid

Transmit Data

Transmit Enable

I

1

I

1

I

1

I

1

I

1

I

1

O

1

1, 14

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

22

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

DSYSCLK

DIFF_SYSCLK

"Single Oscillator Source"

Reference Clock Differential

(positive)

G14

F14

I

O1V_DD

18

DIFF_SYSCLK_B

"Single Oscillator Source"

Reference Clock Differential

(negative)

O1V_DD

USB Clocking

USBCLK

USB PHY Clock In

F8

I

O1V_DD

17

I2C 3 & 4

IIC3_SCL/GPIO4_00

IIC3_SDA/GPIO4_01

Serial Clock

Serial Data

V2

W3

AA3

IO

DV_DD

7, 8

IIC4_SCL/GPIO4_02/EVT5_B/ Serial Clock

DIU_HSYNC

IIC4_SDA/GPIO4_03/EVT6_B/ Serial Data

AB3

IO

DV_DD

7, 8

DIU_VSYNC

DMA

DMA1_DACK0_B/GPIO4_05/ DMA1 channel 0 acknowledge

TDM_TFS

U5

R5

P5

O

I

DV_DD

1

DMA1_DDONE0_B/

DMA1 channel 0 done

GPIO4_06/TDM_TCK

DMA1_DREQ0_B/GPIO4_04/ DMA1 channel 0 request

TDM_TXD

DMA2_DACK0_B/GPIO4_08/ DMA2 channel 0 acknowledge

EVT7_B/TDM_RFS

AA5

Y5

O

I

DMA2_DDONE0_B/

DMA2 channel 0 done

GPIO4_09/EVT8_B/TDM_RCK

DMA2_DREQ0_B/GPIO4_07/ DMA2 channel 0 request

V5

TDM_RXD

QE_TDM

CLK09/GPIO4_15/BRGO2/

DIU_D10

External Clock

Request

P4

P3

N4

M4

R2

U1

I

DV_DD

1

CLK10/GPIO4_22/BRGO3/

DIU_D11

1

CLK11/GPIO4_16/BRGO4/

DIU_DE

I

1

CLK12/GPIO4_23/BRGO1/

DIU_CLK_OUT

I

1, 24

TDMA_RQ/GPIO4_14/

UC1_CDB_RXER/DIU_D4

O

I

1

TDMA_RSYNC/GPIO4_11/

Receive Sync

UC1_CTSB_RXDV/DIU_D1

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

23

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

TDMA_RXD/GPIO4_10/

UC1_RXD7/DIU_D0/

TDMA_TXD

Receive Data

U2

I

DV_DD

1

TDMA_TSYNC/GPIO4_13/

UC1_RTSB_TXEN/DIU_D3

Transmit Sync

Transmit Data

R1

T1

I

DV_DD

1

TDMA_TXD/GPIO4_12/

UC1_TXD7/DIU_D2/

TDMA_RXD_EXC

O

TDMB_RQ/GPIO4_21/

UC3_CDB_RXER/DIU_D9

Request

R4

T3

U4

O

I

DV_DD

1

TDMB_RSYNC/GPIO4_18/

UC3_CTSB_RXDV/DIU_D6

Receive Sync

Receive Data

TDMB_RXD/GPIO4_17/

UC3_RXD7/DIU_D5/

TDMB_TXD

I

TDMB_TSYNC/GPIO4_20/

UC3_RTSB_TXEN/DIU_D8

Transmit Sync

Transmit Data

R3

T4

I

DV_DD

1

TDMB_TXD/GPIO4_19/

UC3_TXD7/DIU_D7/

TDMB_RXD_EXC

O

eSDHC

SDHC_CD_B/GPIO4_24

SDHC_CLK/GPIO2_09

SDHC Card Detect

Host to Card Clock

L5

K1

L4

I

IO

I

CV_DD

EV_DD

CV_DD

1

---

1

SDHC_CLK_SYNC_IN/IRQ10/ Clock Sync

GPIO1_30

SDHC_CLK_SYNC_OUT/

SPI_CS3_B/GPIO2_03/

SDHC_DAT7/

Clock Sync

N3

O

CV_DD

1

SDHC_DAT123_DIR

SDHC_CMD/GPIO2_04

Command/Response

K3

IO

O

EV_DD

CV_DD

---

1

SDHC_CMD_DIR/SPI_CS1_B/ CMD direction control

M2

GPIO2_01/SDHC_DAT5

SDHC_DAT0/GPIO2_05

Data

L2

IO

O

EV_DD

CV_DD

---

1

SDHC_DAT0_DIR/

SPI_CS2_B/GPIO2_02/

SDHC_DAT6

M3

SDHC_DAT1/GPIO2_06

Data

K4

N3

IO

O

EV_DD

CV_DD

---

1

SDHC_DAT123_DIR/

SPI_CS3_B/GPIO2_03/

SDHC_DAT7/

SDHC_CLK_SYNC_OUT

SDHC_DAT2/GPIO2_07

SDHC_DAT3/GPIO2_08

Data

L3

L1

IO

EV_DD

CV_DD

---

SDHC_DAT4/SPI_CS0_B/

M1

GPIO2_00

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

24

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

SDHC_DAT5/SPI_CS1_B/

GPIO2_01/SDHC_CMD_DIR

Data

M2

M3

N3

IO

CV_DD

---

SDHC_DAT6/SPI_CS2_B/

GPIO2_02/SDHC_DAT0_DIR

CV_DD

SDHC_DAT7/SPI_CS3_B/

GPIO2_03/

SDHC_DAT123_DIR/

SDHC_CLK_SYNC_OUT

SDHC_VS/IRQ03/GPIO1_23

SDHC_WP/GPIO4_25

Voltage Select

D1

M5

IO

I

O1V_DD

CV_DD

---

1

SDHC Write Protect

Power-On-Reset Configuration

cfg_dram_type/IFC_A21

cfg_eng_use0/IFC_WE0_B

cfg_eng_use1/IFC_OE_B

cfg_eng_use2/IFC_WP0_B

cfg_gpinput0/IFC_AD00

cfg_gpinput1/IFC_AD01

cfg_gpinput2/IFC_AD02

cfg_gpinput3/IFC_AD03

cfg_gpinput4/IFC_AD04

cfg_gpinput5/IFC_AD05

cfg_gpinput6/IFC_AD06

cfg_gpinput7/IFC_AD07

cfg_ifc_te/IFC_TE

Power-On-Reset Configuration

Signal

C8

D13

D15

F17

A4

I

OV_DD

1, 4

1, 21

1

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

1, 4

Power-On-Reset Configuration

Signal

B5

Power-On-Reset Configuration

Signal

A5

Power-On-Reset Configuration

Signal

B6

Power-On-Reset Configuration

Signal

A6

Power-On-Reset Configuration

Signal

A7

Power-On-Reset Configuration

Signal

B8

Power-On-Reset Configuration

Signal

A8

Power-On-Reset Configuration

Signal

B14

B9

cfg_rcw_src0/IFC_AD08

cfg_rcw_src1/IFC_AD09

cfg_rcw_src2/IFC_AD10

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

A9

Power-On-Reset Configuration

Signal

A10

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

25

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

cfg_rcw_src3/IFC_AD11

cfg_rcw_src4/IFC_AD12

cfg_rcw_src5/IFC_AD13

cfg_rcw_src6/IFC_AD14

cfg_rcw_src7/IFC_AD15

cfg_rcw_src8/IFC_CLE

Power-On-Reset Configuration

Signal

B11

A11

B12

A12

A13

F16

I

OV_DD

1, 4

Power-On-Reset Configuration

Signal

OV_DD

1, 4

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

General Purpose Input/Output

GPIO1_09/IFC_CS4_B

GPIO1_10/IFC_CS5_B

GPIO1_11/IFC_CS6_B

GPIO1_12/IFC_CS7_B

GPO1_13/ASLEEP

General Purpose Input/Output

E17

C17

D18

C19

B2

IO

O

OV_DD

O1V_DD

OV_DD

DV_DD

---

1

General Purpose Input/Output

GPIO1_14/RTC

B17

AA2

AA4

AA1

W4

IO

---

GPIO1_15/UART1_SOUT

GPIO1_16/UART2_SOUT

GPIO1_17/UART1_SIN

GPIO1_18/UART2_SIN

GPIO1_19/UART1_RTS_B/

Y1

UART3_SOUT

GPIO1_20/UART2_RTS_B/

UART4_SOUT

General Purpose Input/Output

V4

Y2

Y4

IO

DV_DD

---

GPIO1_21/UART1_CTS_B/

UART3_SIN

GPIO1_22/UART2_CTS_B/

UART4_SIN

GPIO1_23/IRQ03/SDHC_VS

GPIO1_24/IRQ04

GPIO1_25/IRQ05

GPIO1_26/IRQ06

GPIO1_27/IRQ07

GPIO1_28/IRQ08

GPIO1_29/IRQ09

General Purpose Input/Output

D1

D4

IO

O1V_DD

L1V_DD

CV_DD

---

D5

AB4

AD5

AB1

AC5

L4

GPIO1_30/IRQ10/

SDHC_CLK_SYNC_IN

GPIO1_31/IRQ11

General Purpose Input/Output

U3

IO

DV_DD

---

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

26

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

GPIO2_00/SPI_CS0_B/

SDHC_DAT4

General Purpose Input/Output

M1

IO

CV_DD

---

GPIO2_01/SPI_CS1_B/

SDHC_DAT5/

SDHC_CMD_DIR

M2

CV_DD

GPIO2_02/SPI_CS2_B/

SDHC_DAT6/

SDHC_DAT0_DIR

General Purpose Input/Output

M3

N3

IO

---

GPIO2_03/SPI_CS3_B/

SDHC_DAT7/

SDHC_DAT123_DIR/

SDHC_CLK_SYNC_OUT

GPIO2_04/SDHC_CMD

GPIO2_05/SDHC_DAT0

GPIO2_06/SDHC_DAT1

GPIO2_07/SDHC_DAT2

GPIO2_08/SDHC_DAT3

GPIO2_09/SDHC_CLK

GPIO2_10/IFC_CS1_B

GPIO2_11/IFC_CS2_B

GPIO2_12/IFC_CS3_B

GPIO2_13/IFC_PAR0

GPIO2_14/IFC_PAR1

GPIO2_15/IFC_PERR_B

General Purpose Input/Output

K3

L2

IO

EV_DD

OV_DD

---

K4

L3

L1

K1

E15

D16

C16

C15

C14

E14

C10

GPIO2_25/IFC_A25/

IFC_WP1_B

GPIO2_26/IFC_A26/

IFC_WP2_B

General Purpose Input/Output

E11

C11

IO

OV_DD

---

GPIO2_27/IFC_A27/

IFC_WP3_B

GPIO2_28/IFC_A28

General Purpose Input/Output

D11

C12

IO

OV_DD

---

GPIO2_29/IFC_A29/

IFC_RB2_B

GPIO2_30/IFC_A30/

IFC_RB3_B

General Purpose Input/Output

D12

E12

AC8

AB6

IO

OV_DD

LV_DD

---

GPIO2_31/IFC_A31/

IFC_RB4_B

GPIO3_00/

TSEC_1588_CLK_IN

GPIO3_01/

TSEC_1588_TRIG_IN1

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

27

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

GPIO3_02/

General Purpose Input/Output

AE5

IO

LV_DD

---

TSEC_1588_TRIG_IN2/

EMI1_MDIO

GPIO3_03/

TSEC_1588_ALARM_OUT1

General Purpose Input/Output

AF5

AC7

IO

LV_DD

---

GPIO3_04/

TSEC_1588_ALARM_OUT2/

EMI1_MDC

GPIO3_05/

TSEC_1588_CLK_OUT

General Purpose Input/Output

AD7

AE6

AD8

AC4

IO

LV_DD

L1V_DD

---

GPIO3_06/

TSEC_1588_PULSE_OUT1

GPIO3_07/

TSEC_1588_PULSE_OUT2

GPIO3_08/EC1_TX_ER/

MII_TX_ER/

MAC2_MII_TX_ER

GPIO3_09/EC1_RX_ER/

MII_RX_ER/

General Purpose Input/Output

AC2

IO

L1V_DD

---

MAC2_MII_RX_ER

GPIO3_10/EC1_COL/

MII_COL/MAC2_MII_COL

General Purpose Input/Output

AC1

AC3

IO

L1V_DD

---

GPIO3_11/EC1_TXD3/

MII_TXD3/MAC2_TXD3/

MAC2_MII_TXD3

GPIO3_12/EC1_TXD2/

MII_TXD2/MAC2_TXD2/

MAC2_MII_TXD2

General Purpose Input/Output

AD3

AE4

AE3

AF4

AF3

IO

L1V_DD

---

GPIO3_13/EC1_TXD1/

MII_TXD1/MAC2_TXD1/

MAC2_MII_TXD1

GPIO3_14/EC1_TXD0/

MII_TXD0/MAC2_TXD0/

MAC2_MII_TXD0

GPIO3_15/EC1_TX_CTL/

MII_TX_EN/MAC2_TX_CTL/

MAC2_MII_TX_EN

GPIO3_16/EC1_GTX_CLK/

MII_TX_CLK/

MAC2_GTX_CLK/

MAC2_MII_TX_CLK

GPIO3_17/

General Purpose Input/Output

AG3

IO

L1V_DD

---

EC1_GTX_CLK125/MII_CRS/

MAC2_GTX_CLK125/

MAC2_MII_CRS

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

28

Freescale Semiconductor, Inc.

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

GPIO3_18/EC1_RXD3/

MII_RXD3/MAC2_RXD3/

MAC2_MII_RXD3

General Purpose Input/Output

AD2

AE1

AF1

AF2

AG2

AD1

IO

L1V_DD

---

GPIO3_19/EC1_RXD2/

MII_RXD2/MAC2_RXD2/

MAC2_MII_RXD2

L1V_DD

GPIO3_20/EC1_RXD1/

MII_RXD1/MAC2_RXD1/

MAC2_MII_RXD1

GPIO3_21/EC1_RXD0/

MII_RXD0/MAC2_RXD0/

MAC2_MII_RXD0

GPIO3_22/EC1_RX_CTL/

MII_RX_DV/MAC2_RX_CTL/

MAC2_MII_RX_DV

GPIO3_23/EC1_RX_CLK/

MII_RX_CLK/MAC2_RX_CLK/

MAC2_MII_RX_CLK

GPIO3_24/EC2_TXD3

GPIO3_25/EC2_TXD2

GPIO3_26/EC2_TXD1

GPIO3_27/EC2_TXD0

GPIO3_28/EC2_RXD3

GPIO3_29/EC2_RXD2

GPIO3_30/EC2_RXD1

GPIO3_31/EC2_RXD0

GPIO4_00/IIC3_SCL

GPIO4_01/IIC3_SDA

General Purpose Input/Output

AG5

AF6

AF7

AE7

AH6

AH7

AG7

AH8

V2

IO

LV_DD

DV_DD

---

W3

GPIO4_02/IIC4_SCL/EVT5_B/ General Purpose Input/Output

AA3

DIU_HSYNC

GPIO4_03/IIC4_SDA/EVT6_B/ General Purpose Input/Output

DIU_VSYNC

AB3

P5

IO

DV_DD

---

GPIO4_04/DMA1_DREQ0_B/ General Purpose Input/Output

TDM_TXD

GPIO4_05/DMA1_DACK0_B/ General Purpose Input/Output

TDM_TFS

U5

GPIO4_06/

General Purpose Input/Output

R5

DMA1_DDONE0_B/TDM_TCK

GPIO4_07/DMA2_DREQ0_B/ General Purpose Input/Output

TDM_RXD

V5

GPIO4_08/DMA2_DACK0_B/ General Purpose Input/Output

AA5

EVT7_B/TDM_RFS

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

29

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

GPIO4_09/

General Purpose Input/Output

Y5

IO

DV_DD

---

DMA2_DDONE0_B/EVT8_B/

TDM_RCK

GPIO4_10/TDMA_RXD/

UC1_RXD7/DIU_D0

General Purpose Input/Output

U2

U1

T1

R1

R2

P4

N4

U4

T3

T4

R3

R4

P3

M4

IO

DV_DD

---

GPIO4_11/TDMA_RSYNC/

UC1_CTSB_RXDV/DIU_D1

GPIO4_12/TDMA_TXD/

UC1_TXD7/DIU_D2

GPIO4_13/TDMA_TSYNC/

UC1_RTSB_TXEN/DIU_D3

GPIO4_14/TDMA_RQ/

UC1_CDB_RXER/DIU_D4

GPIO4_15/CLK09/BRGO2/

DIU_D10

GPIO4_16/CLK11/BRGO4/

DIU_DE

GPIO4_17/TDMB_RXD/

UC3_RXD7/DIU_D5

GPIO4_18/TDMB_RSYNC/

UC3_CTSB_RXDV/DIU_D6

GPIO4_19/TDMB_TXD/

UC3_TXD7/DIU_D7

GPIO4_20/TDMB_TSYNC/

UC3_RTSB_TXEN/DIU_D8

GPIO4_21/TDMB_RQ/

UC3_CDB_RXER/DIU_D9

GPIO4_22/CLK10/BRGO3/

DIU_D11

GPIO4_23/CLK12/BRGO1/

DIU_CLK_OUT

GPIO4_24/SDHC_CD_B

GPIO4_25/SDHC_WP

General Purpose Input/Output

L5

IO

CV_DD

LV_DD

---

M5

GPIO4_27/EC2_TX_CTL

GPIO4_28/EC2_GTX_CLK

AF8

AE8

AC6

AG8

AH5

GPIO4_29/EC2_GTX_CLK125 General Purpose Input/Output

GPIO4_30/EC2_RX_CTL

GPIO4_31/EC2_RX_CLK

General Purpose Input/Output

DIU

DIU_CLK_OUT/CLK12/

GPIO4_23/BRGO1

Pixel Clock

M4

U2

O

DV_DD

1

DIU_D0/TDMA_RXD/

DIU Data

GPIO4_10/UC1_RXD7

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

30

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

DIU_D1/TDMA_RSYNC/

GPIO4_11/UC1_CTSB_RXDV

DIU Data

U1

O

DV_DD

1

DIU_D10/CLK09/GPIO4_15/

BRGO2

DIU Data

P4

DV_DD

DIU_D11/CLK10/GPIO4_22/

BRGO3

DIU Data

P3

DIU_D2/TDMA_TXD/

GPIO4_12/UC1_TXD7

DIU Data

T1

DIU_D3/TDMA_TSYNC/

GPIO4_13/UC1_RTSB_TXEN

DIU Data

R1

R2

U4

T3

DIU_D4/TDMA_RQ/

GPIO4_14/UC1_CDB_RXER

DIU Data

DIU_D5/TDMB_RXD/

GPIO4_17/UC3_RXD7

DIU Data

DIU_D6/TDMB_RSYNC/

GPIO4_18/UC3_CTSB_RXDV

DIU Data

DIU_D7/TDMB_TXD/

GPIO4_19/UC3_TXD7

DIU Data

T4

DIU_D8/TDMB_TSYNC/

GPIO4_20/UC3_RTSB_TXEN

DIU Data

R3

R4

N4

AA3

AB3

DIU_D9/TDMB_RQ/

GPIO4_21/UC3_CDB_RXER

DIU Data

DIU_DE/CLK11/GPIO4_16/

BRGO4

Data Enable

Horizontal sync

Vertical sync

DIU_HSYNC/IIC4_SCL/

GPIO4_02/EVT5_B

DIU_VSYNC/IIC4_SDA/

GPIO4_03/EVT6_B

TDM

TDM_RCK/

Receive clock

Y5

IO

DV_DD

---

DMA2_DDONE0_B/

GPIO4_09/EVT8_B

TDM_RFS/DMA2_DACK0_B/ Receive frame sync

GPIO4_08/EVT7_B

AA5

V5

IO

I

DV_DD

---

1

TDM_RXD/DMA2_DREQ0_B/ Receive data

GPIO4_07

TDM_TCK/

Transmit clock

R5

U5

P5

IO

O

---

1

DMA1_DDONE0_B/GPIO4_06

TDM_TFS/DMA1_DACK0_B/ Transmit frame sync

GPIO4_05

TDM_TXD/DMA1_DREQ0_B/ Transmit data

GPIO4_04

QE

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

31

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

BRGO1/CLK12/GPIO4_23/

DIU_CLK_OUT

Baud rate generator

M4

P4

P3

N4

R2

U1

O

I

DV_DD

1

BRGO2/CLK09/GPIO4_15/

DIU_D10

Baud rate generator

DV_DD

BRGO3/CLK10/GPIO4_22/

DIU_D11

BRGO4/CLK11/GPIO4_16/

DIU_DE

UC1_CDB_RXER/TDMA_RQ/ Receive Error

GPIO4_14/DIU_D4

UC1_CTSB_RXDV/

TDMA_RSYNC/GPIO4_11/

DIU_D1

Receive DV

I

UC1_RTSB_TXEN/

TDMA_TSYNC/GPIO4_13/

DIU_D3

Transmit Enable

R1

O

DV_DD

1

UC1_RXD7/TDMA_RXD/

GPIO4_10/DIU_D0

Receive Data

Transmit Data

U2

T1

R4

T3

I

O

I

DV_DD

1

UC1_TXD7/TDMA_TXD/

GPIO4_12/DIU_D2

UC3_CDB_RXER/TDMB_RQ/ Receive Error

GPIO4_21/DIU_D9

UC3_CTSB_RXDV/

TDMB_RSYNC/GPIO4_18/

DIU_D6

Receive DV

I

UC3_RTSB_TXEN/

TDMB_TSYNC/GPIO4_20/

DIU_D8

Transmit Enable

R3

O

DV_DD

1

UC3_RXD7/TDMB_RXD/

GPIO4_17/DIU_D5

Receive Data

Transmit Data

U4

T4

I

DV_DD

1

UC3_TXD7/TDMB_TXD/

O

GPIO4_19/DIU_D7

Power and Ground Signals

GND001

GND002

GND003

GND004

GND005

GND006

GND007

GND008

GND009

GND010

GND

A2

A20

A27

B1

---

B4

B7

B10

B13

B16

B19

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

32

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

GND011

GND012

GND013

GND014

GND015

GND016

GND017

GND018

GND019

GND020

GND021

GND022

GND023

GND024

GND025

GND026

GND027

GND028

GND029

GND030

GND031

GND032

GND033

GND034

GND035

GND036

GND037

GND038

GND039

GND040

GND041

GND042

GND043

GND044

GND045

GND046

GND047

GND048

GND

B23

B25

B28

C22

C26

D2

---

D20

D21

D24

E5

E7

E10

E13

E16

E19

E22

E26

F15

F24

G7

G13

G16

G22

G26

H7

H8

H9

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

33

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

GND049

GND050

GND051

GND052

GND053

GND054

GND055

GND056

GND057

GND058

GND059

GND060

GND061

GND062

GND063

GND064

GND065

GND066

GND067

GND068

GND069

GND070

GND071

GND072

GND073

GND074

GND075

GND076

GND077

GND078

GND079

GND080

GND081

GND082

GND083

GND084

GND085

GND086

GND

H24

J7

---

J22

J26

K2

K5

K6

K7

K12

K14

K16

K18

K20

K24

L7

L9

L11

L13

L15

L17

L19

L22

L26

M7

M10

M12

M14

M16

M18

M20

M24

N2

N5

N7

N9

N11

N13

N15

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

34

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

GND087

GND088

GND089

GND090

GND091

GND092

GND093

GND094

GND095

GND096

GND097

GND098

GND099

GND100

GND101

GND102

GND103

GND104

GND105

GND106

GND107

GND108

GND109

GND110

GND111

GND112

GND113

GND114

GND115

GND116

GND117

GND118

GND119

GND120

GND121

GND122

GND123

GND124

GND

N17

N19

N22

N26

P7

---

P10

P12

P14

P16

P18

P20

P24

R7

R9

R11

R13

R15

R17

R19

R22

R26

T2

T5

T7

T10

T12

T14

T16

T18

T20

T22

T26

U7

U9

U11

U13

U15

U17

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

35

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

GND125

GND126

GND127

GND128

GND129

GND130

GND131

GND132

GND133

GND134

GND135

GND136

GND137

GND138

GND139

GND140

GND141

GND142

GND143

GND144

GND145

GND146

GND147

GND148

GND149

GND150

GND151

GND152

GND153

GND154

GND155

GND156

GND157

GND158

GND159

GND160

GND161

GND162

GND

U19

U24

V7

---

V10

V12

V14

V16

V18

V20

V22

V26

W2

W5

W7

W9

W11

W13

W24

Y7

Y10

Y12

Y22

Y26

AA11

AA24

AB2

AB5

AB7

AB22

AB26

AC24

AC26

AD4

AD6

AD22

AE2

AE24

AE26

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

36

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

GND163

GND164

GND165

GND166

GND167

GND168

GND169

GND170

GND171

GND

AF9

AF21

AG1

AG4

AG6

AG22

AG23

AG26

AH2

E1

---

USB_AGND01

USB_AGND02

USB_AGND03

USB_AGND04

USB_AGND05

USB_AGND06

USB_AGND07

USB_AGND08

USB_AGND09

USB_AGND10

USB_AGND11

USB_AGND12

X1GND01

USB PHY Transceiver GND

Serdes 1 transceiver GND

E2

E3

F3

G1

G2

G3

G5

H3

J1

J2

J3

AC10

AC11

AC13

AC14

AC16

AC17

AC19

AC20

AD9

AD12

AD15

AD18

AD21

AE9

AE12

AE15

AE18

X1GND02

X1GND03

X1GND04

X1GND05

X1GND06

X1GND07

X1GND08

X1GND09

X1GND10

X1GND11

X1GND12

X1GND13

X1GND14

X1GND15

X1GND16

X1GND17

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

37

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

X1GND18

S1GND01

S1GND02

S1GND03

S1GND04

S1GND05

S1GND06

S1GND07

S1GND08

S1GND09

S1GND10

S1GND11

S1GND12

S1GND13

S1GND14

S1GND15

S1GND16

S1GND17

S1GND18

S1GND19

S1GND20

S1GND21

S1GND22

S1GND23

S1GND24

S1GND25

S1GND26

S1GND27

S1GND28

S1GND29

S1GND30

S1GND31

S1GND32

S1GND33

AGND_SD1_PLL1

AGND_SD1_PLL2

SENSEGND

Serdes 1 transceiver GND

Serdes 1 core logic GND

Serdes 1 PLL 1 GND

AE21

Y14

---

Y16

Y17

Y18

AA13

AA15

AA17

AA19

AA21

AB13

AB17

AB21

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AG9

AG12

AG15

AG18

AG21

AH9

AH12

AH15

AH18

AH21

AA16

AA20

G20

Serdes 1 PLL 2 GND

GND Sense pin

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

38

Freescale Semiconductor, Inc.

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

SENSEGNDC

GND Sense pin for VDDC

domain

AB10

---

O1VDD1

O1VDD2

O1VDD3

OVDD1

General I/O supply - Always on

J11

J12

J13

J14

---

O1V_DD

OV_DD

---

General I/O supply -

Switchable

OVDD2

OVDD3

OVDD4

OVDD5

OVDD6

DVDD1

DVDD2

DVDD3

General I/O supply -

Switchable

J15

J16

J17

J18

J19

N8

---

OV_DD

DV_DD

---

General I/O supply -

Switchable

General I/O supply -

Switchable

General I/O supply -

Switchable

General I/O supply -

Switchable

UART/I2C/DMA/TDM supply -

Switchable

UART/I2C/DMA/TDM supply -

Switchable

P8

UART/I2C/DMA/TDM supply -

Switchable

R8

CVDD

SPI supply - Switchable

M8

L8

T8

---

CV_DD

EV_DD

L1V_DD

---

EVDD

eSDHC supply - Switchable

L1VDD1

Ethernet controller 1 and GPIO

supply- Always ON

L1VDD2

LVDD1

Ethernet controller 1 and GPIO

supply- Always ON

U8

V8

---

L1V_DD

LV_DD

---

Ethernet controller 2, 1588 and

GPIO supply- Switchable

LVDD2

Ethernet controller 2, 1588 and

GPIO supply- Switchable

W8

LV_DD

G1VDD01

G1VDD02

G1VDD03

G1VDD04

G1VDD05

DDR supply for port 1 -

Switchable

D27

F27

H27

K21

K27

G1V_DD

DDR supply for port 1 -

Switchable

DDR supply for port 1 -

Switchable

DDR supply for port 1 -

Switchable

DDR supply for port 1 -

Switchable

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

39

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

G1VDD06

G1VDD07

G1VDD08

G1VDD09

G1VDD10

G1VDD11

G1VDD12

G1VDD13

G1VDD14

G1VDD15

G1VDD16

G1VDD17

G1VDD18

G1VDD19

S1VDD1

DDR supply for port 1 -

Switchable

L21

M21

M27

N21

P21

---

G1V_DD

---

DDR supply for port 1 -

Switchable

---

G1V_DD

S1V_DD

X1V_DD

---

DDR supply for port 1 -

Switchable

DDR supply for port 1 -

Switchable

DDR supply for port 1 -

Switchable

DDR supply for port 1 -

Switchable

P27

DDR supply for port 1 -

Switchable

R21

T21

DDR supply for port 1 -

Switchable

DDR supply for port 1 -

Switchable

U21

U27

W27

AA27

AD27

AF27

W15

W16

W17

W18

W19

W20

Y13

DDR supply for port 1 -

Switchable

DDR supply for port 1 -

Switchable

DDR supply for port 1 -

Switchable

DDR supply for port 1 -

Switchable

DDR supply for port 1 -

Switchable

SerDes 1 core logic supply -

Switchable

S1VDD2

SerDes 1 core logic supply -

Switchable

S1VDD3

SerDes 1 core logic supply -

Switchable

S1VDD4

SerDes 1 core logic supply -

Switchable

S1VDD5

SerDes 1 core logic supply -

Switchable

S1VDD6

SerDes 1 core logic supply -

Switchable

S1VDD7

SerDes 1 core logic supply -

Switchable

X1VDD1

SerDes 1 transceiver supply -

Switchable

AC9

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

40

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

X1VDD2

X1VDD3

X1VDD4

X1VDD5

SerDes 1 transceiver supply -

Switchable

AC12

AC15

AC18

AC21

---

X1V_DD

---

SerDes 1 transceiver supply -

Switchable

---

X1V_DD

SerDes 1 transceiver supply -

Switchable

SerDes 1 transceiver supply -

Switchable

PROG_SFP

PROG_MTR

FA_VL

SFP Fuse Programming supply

Reserved for Internal Use Only

F12

F11

G18

G9

---

PROG_SFP

PROG_MTR

FA_VL

---

15

---

TH_VDD

Thermal Monitor Unit supply --

Switchable

TH_V_DD

VDD01

VDD02

VDD03

VDD04

VDD05

VDD06

VDD07

VDD08

VDD09

VDD10

VDD11

VDD12

VDD13

VDD14

VDD15

Supply for cores and platform -

Switchable

K15

K17

K19

L12

L14

L16

L18

L20

M13

M15

M17

M19

N12

N14

N16

---

V_DD

---

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

41

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

VDD16

VDD17

VDD18

VDD19

VDD20

VDD21

VDD22

VDD23

VDD24

VDD25

VDD26

VDD27

VDD28

VDD29

VDD30

VDD31

VDD32

VDD33

VDD34

VDD35

VDD36

VDD37

Supply for cores and platform -

Switchable

N18

N20

P11

P13

P15

P17

P19

R12

R14

R16

R18

R20

T13

T15

T17

T19

U14

U16

U18

U20

V13

V15

---

V_DD

---

Supply for cores and platform -

Switchable

---

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Supply for cores and platform -

Switchable

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

42

Freescale Semiconductor, Inc.

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

VDD38

VDD39

VDD40

Supply for cores and platform -

Switchable

V17

V19

W14

---

V_DD

---

Supply for cores and platform -

Switchable

---

Supply for cores and platform -

Switchable

VDDC01

VDDC02

VDDC03

VDDC04

VDDC05

VDDC06

VDDC07

VDDC08

VDDC09

VDDC10

VDDC11

VDDC12

Always ON supply

K11

K13

L10

---

V_DDC

---

V_DDC

M11

N10

R10

T11

U10

U12

V11

W10

W12

G11

V_DDC

AVDD_CGA1

AVDD_CGA2

AVDD_PLAT

e5500 Cluster Group A PLL1

supply (SDHC /Cores fed

through this) - Switchable

AVDD_CGA1

e5500 Cluster Group A PLL2

supply (Cores are fed through

this) - Switchable

G12

G10

---

AVDD_CGA2

AVDD_PLAT

---

Platform PLL supply - Always

ON

AVDD_D1

DDR1 PLL supply - Switchable

E20

---

AVDD_D1

---

AVDD_SD1_PLL1

SerDes1 PLL 1 supply -

Switchable

AB16

AVDD_SD1_PLL1

AVDD_SD1_PLL2

SerDes1 PLL 2 supply -

Switchable

AB20

---

AVDD_SD1_PLL2

---

SENSEVDD

SENSEVDDC

USB_HVDD1

Vdd Sense pin - Switchable

Vddc Sense pin - Always ON

G19

AB9

J8

---

SENSEVDD

SENSEVDDC

USB_HV_DD

---

USB PHY Transceiver 3.3V

Supply - "Optionally Switchable

or Always ON"

USB_HVDD2

USB_OVDD1

USB PHY Transceiver 3.3V

Supply - "Optionally Switchable

or Always ON"

K8

J9

---

USB_HV_DD

USB_OV_DD

---

USB PHY Transceiver 1.8V

Supply - "Optionally Switchable

or Always ON"

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

43

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

USB_OVDD2

USB_SVDD1

USB_SVDD2

USB PHY Transceiver 1.8V

Supply - "Optionally Switchable

or Always ON"

J10

---

USB_OV_DD

---

USB PHY Analog 1.0V Supply

- "Optionally Switchable or

Always ON"

K9

---

USB_SV_DD

---

USB PHY Analog 1.0V Supply

- "Optionally Switchable or

Always ON"

K10

No Connection Pins

NC01

NC02

NC03

NC04

NC05

NC06

NC07

NC08

NC09

NC10

NC11

NC12

NC13

NC14

NC15

NC16

NC17

NC18

NC19

NC20

NC21

NC22

NC23

NC24

NC25

NC26

NC_DET

NC_1040

No Connection

G17

L6

---

M6

M9

N6

P6

P9

R6

T6

T9

U6

V6

V9

W6

Y6

Y8

Y9

Y11

AA6

AA7

AA8

AA9

AA10

AB8

AB11

AB12

AG28

AH27

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

44

Freescale Semiconductor, Inc.

Pin assignments

1. Functionally, this pin is an output or an input, but structurally it is an I/O because it

either sample configuration input during reset, is a muxed pin, or has other manufacturing

test functions. This pin is therefore be described as an I/O for boundary scan.

2. During reset this output signal is actively driven rather than being tri-stated.

3. MDIC[0] is grounded through a 162Ω precision 1% resistor and MDIC[1] is connected

to GV1_DDthrough a 162Ω precision 1% resistor. For either full or half driver strength

calibration of DDR IOs, use the same MDIC resistor value of 162Ω. Memory controller

register setting can be used to determine automatic calibration is done to full or half drive

strength. These pins are used for automatic calibration of the DDR3L/DDR4 IOs. The

MDIC[0:1] pins must be connected to 162Ω precision 1% resistors.

4. This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that

is enabled only when the processor is in its reset state. This pull-up is designed such that

it can be overpowered by an external 4.7 kΩ resistor. However, if the signal is intended to

be high after reset, and if there is any device on the net that might pull down the value of

the net at reset, a pull-up or active driver is needed.

5. Pin must NOT be pulled down during power-on reset. This pin may be pulled up,

driven high, or if there are any externally connected devices, left in tristate. If this pin is

connected to a device that pulls down during reset, an external pull-up is required to drive

this pin to a safe state during reset.

6. Recommend that a weak pull-up resistor (2-10 kΩ) be placed on this pin to the

respective power supply.

7. This pin is an open-drain signal.

8. Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective

power supply.

9. This pin has a weak (~20 kΩ) internal pull-up P-FET that is always enabled.

10. These are test signals for factory use only and must be pulled up (100Ω to 1-kΩ) to

the respective power supply for normal operation.

11. This pin requires a 200Ω pull-up to respective power-supply.

12. Do not connect. These pins should be left floating.

14. This pin requires an external 1-kΩ pull-down resistor to prevent PHY from seeing a

valid Transmit Enable before it is actively driven.

15. These pins must be pulled to ground (GND).

16. This pin requires a 698Ω pull-up to respective power-supply.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

45

Electrical characteristics

17. This pin should be connected to ground through 2-10kΩ resistor when not used.

18. This pin should be connected to ground through 2-10kΩ resistor when SYSCLK input

is used as system clock.

19. This pin should be tied to ground if the diode is not utilized for temperature

monitoring.

20. This pin should be connected to GND through a 10kΩ 1% resistor with a low

temperature coefficient of ≤ 25ppm/°C for bias generation

21. This pin has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the

processor is in its reset state. This pin should have an optional pull down resistor on

board. This is required to support DIFF_SYSCLK/DIFF_SYSCLK_B

22. This pin should not be sampled until PORESET_B gets deasserted.

23. This pin must be pulled to O1VDD through a 100-ohm to 1k-ohm resistor for a 4 core

T1042 and tied to ground for a 2 core T1022 device.

24. External “CLK12” pin is connected internally to both CLK12 and CLK8 pins of QE.

25.

26. PORESET_B should be asserted zero during the JTAG Boundary scan operation, and

is required to be controllable on board.

27. This pin requires a pull-up to the respective power supply so as to meet the timing

requirements in Table 21.

Warning

See "Connection Recommendations" for additional details on

properly connecting these pins for specific applications.

3 Electrical characteristics

This section provides the AC and DC electrical specifications for the chip. The chip is

currently targeted to these specifications, some of which are independent of the I/O cell

but are included for a more complete reference. These are not purely I/O buffer design

specifications.

3.1 Overall DC electrical characteristics

This section describes the ratings, conditions, and other characteristics.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

46

Freescale Semiconductor, Inc.

Electrical characteristics

3.1.1 Absolute maximum ratings

This table provides the absolute maximum ratings.

Table 2. Absolute maximum ratings¹

Characteristic

Core and platform supply voltage

Symbol

Max Value

Unit Notes

V_DD

-0.3 to 1.1

-0.3 to 1.98

V

9

Always ON supply voltage

V_DDC

V

-

PLL supply voltage (core PLL/eSDHC, platform, DDR)

AV_DD_CGA1

AV_DD_CGA2

AV_DD_PLAT

AV_DD_D1

10

PLL supply voltage (SerDes, filtered from X1V_DD

)

AVDD_SD1_PLL1

AVDD_SD1_PLL2

PROG_SFP

TH_V_DD

-0.3 to 1.48

V

-

SFP fuse programming

-0.3 to 1.98

V

-

Thermal monitor unit supply

MPIC, GPIO, system control and power management, clocking, OV_DD

debug, IFC, DDRCLK supply, and JTAG I/O voltage

O1V_DD

DUART, I²C, DMA, TDM, QE, MPIC, DIU

DV_DD

-0.3 to 2.75

-0.3 to 1.98

-0.3 to 3.63

-0.3 to 1.98

-0.3 to 3.63

-0.3 to 1.98

-0.3 to 3.63

-0.3 to 1.32

-0.3 to 1.48

V

-

eSPI, SDHC_WP, SDHC_CD, SDHC_DAT[4:7]

eSDHC

CV_DD

EV_DD

G1V_DD

V

-

DDR4 and

DDR4

DDR3L DRAM

I/O voltage

DDR3L

Main power supply for internal circuitry of SerDes and pad power S1V_DD

supply for SerDes receivers

-0.3 to 1.1

V

-

Pad power supply for SerDes transmitter

Ethernet interface 2, 1588, GPIO

X1V_DD

LV_DD

-0.3 to 1.48

-0.3 to 1.98

-0.3 to 2.75

-0.3 to 3.63

-0.3 to 1.98

-0.3 to 2.75

-0.3 to 3.63

-0.3 to 1.98

-0.3 to 1.1

V

-

Ethernet interface 1, Ethernet management interface 1 (EMI1),

GPIO

L1V_DD

V

-

USB PHY Transceiver supply voltage

USB PHY Analog supply voltage

USB_HV_DD

USB_OV_DD

USB_SV_DD

V

-

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

47

Electrical characteristics

Table 2. Absolute maximum ratings¹(continued)

Characteristic

Symbol

Max Value

Unit Notes

Input voltage

DDR4 and DDR3L DRAM signals

DDR4 and DDR3L DRAM reference

Ethernet signals

MV_IN

-0.3 to (G1V_DD

0.3)

+

V

2

D1_MV_REF

-0.3 to (G1V_DD/2+

0.3)

V

5

LV_IN

-0.3 to (LnV_DD

0.3)

+

4, 5

LV1_IN

OV_IN

O1V_IN

MPIC, GPIO, system control and power

management, clocking, debug, IFC, DDRCLK

supply, and JTAG I/O voltage

-0.3 to (OnV_DD

0.3)

+

V

3, 5

eSDHC signals

EV_IN

CV_IN

DV_IN

S1V_IN

-0.3 to (EV_DD+ 0.3) V

-0.3 to (CV_DD+ 0.3) V

-0.3 to (DV_DD+ 0.3) V

7, 5

8, 5

5, 6

5

eSPI signals

DUART, I²C, DMA, TDM, QE, MPIC, DIU

SerDes signals

-0.4 to (S1V_DD

0.3)

+

V

USB PHY Transceiver signals

USB_HV_IN

USB_OV_IN

T_STG

-0.3 to (USB_HV_DD

+ 0.3)

V

5

-

-0.3 to (USB_OV_DD

+ 0.3)

V

Storage temperature range

-55 to 150

°C

Notes:

1. Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional

operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent

damage to the device.

2. Caution: MV_INmust not exceed G1V_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

3. Caution: OV_INmust not exceed OV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

4. Caution: LV_INmust not exceed LV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

5. (S,G,L,O,D,E,C)V_IN, USBn_V_IN_3P3, USBn_V_IN_1P8 and Dn_MV_REFmay overshoot/undershoot to a voltage and for a

maximum duration as shown in Figure 8.

6. Caution: DV_INmust not exceed DV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

7. Caution: EV_INmust not exceed EV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

8. Caution: CV_INmust not exceed CV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

9. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the

sense pin.

10. AVDD_PLAT, AVDD_CGA1, AVDD_CGA2 and AVDD_D1 are measured at the input to the filter (as shown in AN4825)

and not at the pin of the device.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

48

Freescale Semiconductor, Inc.

Electrical characteristics

3.1.2 Recommended operating conditions

This table provides the recommended operating conditions for this chip.

NOTE

The values shown are the recommended operating conditions

and proper device operation outside these conditions is not

guaranteed.

Table 3. Recommended operating conditions

Characteristic

Symbol

Recommended Value Unit

Status

in Deep

Sleep⁷

Notes

Core and platform supply voltage

V_DD

1.0 30 mV

1.8 V 90 mV

V

OFF

ON

3, 4, 5

-

Always ON Core and Platform supply

V_DDC

PLL supply voltage (core PLL/eSDHC,

platform, DDR)

AV_DD_CGA1

AV_DD_CGA2

AV_DD_PLAT

AV_DD_D1

OFF

ON

OFF

PLL supply voltage (SerDes, filtered from

AV_DD_SD1_PLL1

AV_DD_SD1_PLL2

PROG_SFP

TH_V_DD

1.35 V 67 mV

V

-

X1V_DD

)

SFP fuse programming

1.8 V 90 mV

V

ON

2

-

Thermal monitor unit supply

OFF

IFC, GPIO, Trust, DDRCLK supply, RTC and OV_DD

JTAG I/O voltage

-

MPIC, GPIO, system control, debug and

SYSCLK supply

DUART, I²C, DMA, MPIC, QE, TDM, DIU

O1V_DD

1.8 V 90 mV

V

ON

-

DV_DD

2.5 V 125 mV

1.8 V 90 mV

3.3 V 165 mV

3.3 V 165mV

1.8 V 90mV

3.3 V 165 mV

1.8 V 90 mV

1.2V 60 mV

1.35 V 67 mV

1.0 V + 50 mV

1.0 V - 30 mV

OFF

eSPI, SDHC_WP, SDHC_CD,

SDHC_DAT[4:7]

CV_DD

V

OFF

-

eSDHC

EV_DD

DDR DRAM I/O

voltage

DDR4

G1V_DD

S1V_DD

DDR3L

Main power supply for internal circuitry of

SerDes and pad power supply for SerDes

receivers

Pad power supply for SerDes transmitters

Ethernet interface 2, 1588, GPIO

X1V_DD

LV_DD

1.35 V 67 mV

1.8 V 90 mV

2.5 V 125 mV

3.3 V 165 mV

V

OFF

-

1

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

49

Electrical characteristics

Table 3. Recommended operating conditions (continued)

Characteristic

Symbol

Recommended Value Unit

Status

in Deep

Sleep⁷

Notes

Ethernet interface 1, Ethernet management L1V_DD

interface 1 (EMI1), GPIO

1.8 V 90 mV

2.5 V 125 mV

3.3 V 165 mV

V

ON

1

USB PHY Transceiver supply voltage

USB_HV_DD

USB_OV_DD

V

Optionall

y OFF

-

1.8 V 90 mV

1.0 50mV

Optionall

y OFF

-

USB PHY Analog supply voltage

USB_SV_DD

MV_IN

Optionall

y OFF

3

-

Input voltage

DDR4 and DDR3L

DRAM signals

GND to G1V_DD

G1V_DD/2 1ꢀ

-

DDR4 and DDR3L

DRAM reference

D1_MV_REF

-

Ethernet interface,

EMI1, 1588, GPIO

LV_IN

GND to LV_DD

GND to L1V_DD

GND to OnV_DD

-

L1V_IN

MPIC, GPIO, system OV_IN

V

-

control and power

management,

O1V_IN

clocking, debug, IFC,

DDRCLK supply, and

JTAG I/O voltage

DUART, I²C, DMA,

DV_IN

GND to DV_DD

V

-

TDM, QE, MPIC, DIU

eSDHC, eSPI

SerDes signals

CV_IN, EV_IN

GND to CV_DD/EV_DD

GND to S1V_DD

GND to USB_HV_DD

GND to USB_OV_DD

T_A= 0 (min) to

V

-

SV_IN

V

USB PHY

Transceiver signals

USB_HV_IN

V

USB_OV_IN

V

Operating

temperature range

Normal operation

T_A,

T_J

°C

T_J= 105(max)

Extended

Temperature

T_A,

T_J

T_A= -40 (min) to

T_J= 105(max)

°C

-

Secure boot fuse

programming

T_A,

T_J

T_A= 0 (min) to

2

T_J= 70 (max)

1. Selecting RGMII limits L1V_DDand LV_DD= 1.8 V or 2.5 V. L1V_DDand LV_DDshould be configured at same voltage.

2. PROG_SFP must be supplied 1.8 V and the chip must operate in the specified fuse programming temperature range only

during secure boot fuse programming. For all other operating conditions, PROG_SFP must be tied to GND, subject to the

power sequencing constraints shown in Power sequencing.

3. Refer to Core and platform supply voltage filtering for additional information.

4. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the

sense pin.

5. Operation at 1.1V is allowable for up to 25ms at initial power on.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

50

Freescale Semiconductor, Inc.

Electrical characteristics

Table 3. Recommended operating conditions

Characteristic

Symbol

Recommended Value Unit

Status

in Deep

Sleep⁷

Notes

7. The Power supplies designated as OFF in this column should be switched OFF during Deep Sleep and those designated

as ON should not be switched OFF. There are few power supplies which can be optionally switched OFF, for more details

refer T1040 QorIQ Integrated Multicore Communications Processor Reference Manual.

Warning

When the device is in Deep Sleep mode, all external voltage

supplies applied to any I/O pins, with the exception of wake-up

pins, must be turned off. Applying external voltage to any I/O

pins, except the wake up pins, while the device is in Deep Sleep

mode may cause permanent damage to the device.

This figure shows the undershoot and overshoot voltages at the interfaces of the chip.

Nominal D/S/G/L/OVDD + 20ꢀ

D/S/G/L/OVDD + 5ꢀ

D/S/G/L/OVDD

V

IH

GND

GND - 0.3 V

V

IL

GND - 0.7 V

Note: GND - 0.6 V

for SerDes

Not to exceed 10ꢀ

of t

1

CLOCK

receiver inputs

Notes:

t

refers to the clock period associated with the respective interface:

2

CLOCK

For I C OV , t

references SYSCLK.

DD CLOCK

For DDR GV , t

references Dn_MCLK.

references SPI_CLK.

references TCK.

DD CLOCK

For eSPI OV , t

DD CLOCK

For JTAG OV , t

DD CLOCK

For SerDes SVDD, tCLOCK references SD_REF_CLK.

For Ethernet LV , t references ECn_GTX_CLK125.

DD CLOCK

Figure 8. Overshoot/Undershoot voltage for G1V_DD/L1V_DD/OV_DD/SV_DD/DV_DD/CV_DD/

LV_DD/EV_DD

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

51

Electrical characteristics

See Table 3 for actual recommended core voltage. Voltage to the processor interface I/Os

are provided through separate sets of supply pins and must be provided at the voltages

shown in Table 3. The input voltage threshold scales with respect to the associated I/O

supply voltage. DV_DD, OV_DDand LV_DDbased receivers are simple CMOS I/O circuits

and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses

differential receivers referenced by the externally supplied Dn_MV_REFsignal (nominally

set to G1V_DD/2) as is appropriate for the SSTL_1.35/SSTL_1.2 electrical signaling

standard. The DDR MDQS receivers cannot be operated in single-ended fashion. The

complement signal must be properly driven and cannot be grounded.

3.1.3 Output driver characteristics

This chip provides information on the characteristics of the output driver strengths.

NOTE

These values are preliminary estimates.

Table 4. Output drive capability

Driver type

Output impedance (Ω)

Typical

Supply Voltage Notes

Minimum²

Maximum³

DDR4 signal

-

18(full-strength

mode)

-

G1V_DD= 1.2 V

1

-

27(half-strength

mode)

DDR3L signal

Ethernet signals

18(full-strength

mode)

-

G1V_DD= 1.35 V

27(half-strength

mode)

45

40

23

-

90

75

51

L1V_DD/ LV_DD

3.3V

=

L1V_DD/ LV_DD

2.5V

L1V_DD/ LV_DD

1.8VV

MPIC, GPIO, system control and power

management, clocking, debug, IFC,DDRCLK

supply, and JTAG I/O voltage

DUART, DMA, MPIC, QE, TDM, I²C, DIU

OV_DD, O1V_DD

1.8 V

=

-

45

40

45

40

45

-

90

75

90

75

90

DV_DD= 3.3V

DV_DD= 2.5V

DV_DD= 1.8V

CV_DD= 3.3V

CV_DD= 1.8V

EV_DD= 3.3V

eSPI, SDHC_WP, SDHC_CD

eSDHC

-

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

52

Freescale Semiconductor, Inc.

Electrical characteristics

Table 4. Output drive capability (continued)

Driver type

Output impedance (Ω)

Supply Voltage Notes

Minimum²

Typical

Maximum³

40

-

75

EV_DD= 1.8V

1. The drive strength of the DDR4 or DDR3L interface in half-strength mode is at T_j= 105 °C and at G1V_DD(min).

2. Estimated number based on best case processed device.

3. Estimated number based on worst case processed device.

3.1.4 General AC timing specifications

This table provides AC timing specifications for the sections not covered under the

specific interface sections.

Table 5. AC Timing specifications

Parameter

Symbol

Min

Max

Unit

ns

Notes

Input signal rise and fall times

t_R/t_F

-

5

1

1. Rise time refers to signal transitions from 10ꢀ to 90ꢀ of Supply; fall time refers to transitions from 90ꢀ to 10ꢀ of supply

3.2 Power sequencing

The chip requires that its power rails be applied in a specific sequence in order to ensure

proper device operation.

Power up sequence when DDR3L is used

1. O1V_DD, OV_DD, DV_DD, CV_DD, EV_DD, L1V_DD, LV_DD, TH_V_DD, USB_HV_DD,

USB_OV_DD, AV_DD_CGA1, AV_DD_CGA2, AV_DD_PLAT, AV_DD_D1. Drive

PROG_SFP = GND

a. PORESET_B should be driven asserted and held during this step.

2. V_DDC, V_DD, USB_SV_DD, S1V_DD

a. When Deep Sleep is not used, it is recommended to source V_DDand V_DDCfrom

same power supply.

b. When Deep Sleep is used, V_DDCshould ramp up before V_DD. Alternatively V_DD

may ramp up together with V_DDCprovided that the relative timing between

V_DDCand V_DDramp up conforms to Figure 9

3. G1V_DD, X1V_DD, AV_DD_SD1_PLL1, AV_DD_SD1_PLL2

a. All supplies in Step 3 may be sourced from same supply

Power up sequence when DDR4 is used

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

53

Electrical characteristics

1. O1V_DD, OV_DD, DV_DD, CV_DD, EV_DD, L1V_DD, LV_DD, TH_V_DD, USB_HV_DD,

USB_OV_DD, AV_DD_CGA1, AV_DD_CGA2, AV_DD_PLAT, AV_DD_D1, X1V_DD,

AV_DD_SD1_PLL1, AV_DD_SD1_PLL2. Drive PROG_SFP = GND

a. PORESET_B should be driven asserted and held during this step.

2. V_DDC, V_DD, USB_SV_DD, S1V_DD

a. When Deep Sleep is not used, it is recommended to source V_DDand V_DDCfrom

same power supply.

b. When Deep Sleep is used, V_DDCshould ramp up before V_DD. Alternatively V_DD

may ramp up together with V_DDCprovided that the relative timing between

V_DDCand V_DDramp up conforms to Figure 9

3. G1V_DD

The supplies mentioned as OFF in "Status in Deep Sleep" column of Table 3 are

switched ON while exit from Deep sleep power management mode. These supplies

should also follow the same power up sequence as mentioned above.

Items on the same line have no ordering requirement with respect to one another. Items

on separate lines must be ordered sequentially such that voltage rails on a previous step

must reach 90% of their value before the voltage rails on the current step reach 10% of

theirs.

All supplies must be at their stable values within 75 ms.

Negate PORESET_B input when the required assertion/hold time has been met per Table

21.

NOTE

• EVT2_B may be unstable when PORESET_B is asserted.

The signal should not be used to enable switchable power

supplies during this period.

• Ramp rate requirements should be met per Table 7

Warning

Only 300,000 POR cycles are permitted per lifetime of a

device. Note that this value is based on design estimates and is

preliminary.

This figure provides the V_DDCand V_DDramp up diagram.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

54

Freescale Semiconductor, Inc.

Electrical characteristics

90ꢀ

10ꢀ

V

DD

90ꢀ

10ꢀ

V

DDC

T2 <= 1 us

T1 <= 1 us

Figure 9. V_DDCand V_DDramp up diagram

For secure boot fuse programming, use the following steps:

1. After negation of PORESET_B, drive PROG_SFP = 1.8 V after a required minimum

delay per Table 6.

2. After fuse programming is completed, it is required to return PROG_SFP = GND

before the system is power cycled (PORESET_B assertion) or powered down (V_DD

ramp down) per the required timing specified in Table 6. See Security fuse processor,

for additional details.

Warning

No activity other than that required for secure boot fuse

programming is permitted while PROG_SFP is driven to

any voltage above GND, including the reading of the fuse

block. The reading of the fuse block may only occur while

PROG_SFP = GND.

This figure provides the PROG_SFP timing diagram.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

55

Electrical characteristics

Fuse programming

10ꢀ PROG_SFP

PROG_SFP

90ꢀ V_DD

t

PROG_SFP_VDD

V

DD

t_{PROG_SFP_PROG}

t_{PROG_SFP_DELAY}

90ꢀ OV_DD

t_{PROG_SFP_RST}

90ꢀ OV_DD

PORESET_B

NOTE: PROG_SFP must be stable at 1.8 V prior to initiating fuse programming.

Figure 10. PROG_SFP timing diagram

This table provides information on the power-down and power-up sequence parameters

for PROG_SFP.

Table 6. PROG_SFP timing ⁵

Driver type

Min

Max

Unit

SYSCLKs

Notes

t_{PROG_SFP_DELAY}

t_{PROG_SFP_PROG}

t_{PROG_SFP_VDD}

t_{PROG_SFP_RST}

100

0

-

1

2

3

4

μs

0

1. Delay required from the deassertion of PORESET_B to driving PROG_SFP ramp up. Delay measured from PORESET_B

deassertion at 90ꢀ OV_DDto 10ꢀ PROG_SFP ramp up.

2. Delay required from fuse programming finished to PROG_SFP ramp down start. Fuse programming must complete while

PROG_SFP is stable at 1.8 V. No activity other than that required for secure boot fuse programming is permitted while

PROG_SFP driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may

only occur while PROG_SFP = GND. After fuse programming is completed, it is required to return PROG_SFP = GND.

3. Delay required from PROG_SFP ramp down complete to V_DDramp down start. PROG_SFP must be grounded to

minimum 10ꢀ PROG_SFP before V_DDis at 90ꢀ V_DD

4. Delay required from PROG_SFP ramp down complete to PORESET_B assertion. PROG_SFP must be grounded to

minimum 10ꢀ PROG_SFP before PORESET_B assertion reaches 90ꢀ OV_DD

.

5. Only two secure boot fuse programming events are permitted per lifetime of a device.

3.3 Power-down requirements

The power-down cycle must complete such that power supply values are below 0.4 V

before a new power-up cycle can be started.

If performing secure boot fuse programming per Power sequencing, it is required that

PROG_SFP = GND before the system is power cycled (PORESET_B assertion) or

powered down (V_DDramp down) per the required timing specified in Table 6.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

56

Freescale Semiconductor, Inc.

Electrical characteristics

3.4 Power-on ramp rate

This section describes the AC electrical specifications for the power-on ramp rate

requirements. Controlling the maximum power-on ramp rate is required to avoid excess

in-rush current.

This table provides the power supply ramp rate specifications.

Table 7. Power supply ramp rate

Parameter

Min

Max

Unit

V/ms

Notes

1, 2

Required ramp rate for all voltage supplies (including OV_DD/O1V_DD/DV_DD

G1V_DD/S1V_DD/X1V_DD/LV_DD/L1V_DD/EV_DD/CV_DDall core and platform V_DDsupplies,

D1_MV_REFand all AV_DDsupplies.)

/

-

25

Required ramp rate for PROG_SFP

Required ramp rate for USB_HV_DD

Note:

-

V/ms

1, 2

26.7

1. Ramp rate is specified as a linear ramp from 10ꢀ to 90ꢀ. If non-linear (for example, exponential), the maximum rate of

change from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.

2. Over full recommended operating temperature range (see Table 3).

3.5 Power characteristics

This table shows the power dissipations of the V_DDand V_DDCsupply for various

operating platform clock frequencies versus the core and DDR clock frequencies.

Table 8. T1042 core power dissipation

Core

freq

(MHz)

Platfo DDR

V_DD

V_DDC

(V)

,

S1V_DD(V) Junction

temp. (ºC)

Power

mode

Power (W)

V_DDCS1V_DD

Total Core Notes

and

platform

power

rm

freq

data

rate

V_DD

(MHz) (MT/s)

(W)¹

1500

600

1600

1.0

65

Typical

5.44

0.63

0.91

0.63

0.69

0.57

0.63

0.41

0.47

0.41

6.47

8.89

9.64

6.34

6.93

7.66

5.53

6.15

6.75

2, 3

105

Thermal

Maximum

Typical

7.51

8.26

5.31

5.83

6.56

4.55

5.10

5.71

5, 7

4, 6, 7

2, 3

1400

1200

600

500

1.0

65

105

Thermal

Maximum

Typical

5, 7

4, 6, 7

2, 3

65

105

Thermal

Maximum

5, 7

4, 6, 7

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

57

Electrical characteristics

Table 8. T1042 core power dissipation (continued)

Core

freq

(MHz)

Platfo DDR

V_DD

V_DDC

(V)

,

S1V_DD(V) Junction

temp. (ºC)

Power

mode

Power (W)

V_DDCS1V_DD

Total Core Notes

and

platform

power

rm

freq

data

rate

V_DD

(MHz) (MT/s)

(W)¹

1. Combined power of V_DDC, V_DDand S1V_DDwith platform at power-on reset default state, DDR controller and all SerDes

banks active. Does not include I/O power.

2. Typical power assumes Dhrystone running with activity factor of 70ꢀ (on all cores) and is executing DMA on the platform

with 100ꢀ activity factor.

3. Typical power based on nominal, processed device.

4. Maximum power assumes Dhrystone running with activity factor at 100ꢀ (on all cores) and is executing DMA on the

platform at 115ꢀ activity factor.

5. Thermal power assumes Dhrystone running with activity factor of 70ꢀ (on all cores) and executing DMA on the platform at

100ꢀ activity factor.

6. Maximum power is provided for power supply design sizing.

7. Thermal and maximum power are based on worst case processed device.

Table 9. T1022 core power dissipation

Core

freq

(MHz)

Platfo DDR

V_DD

V_DDC

(V)

,

S1V_DD(V) Junction

temp. (ºC)

Power

mode

Power (W)

V_DDCS1V_DD

Total Core Notes

and

platform

power

rm

freq

data

rate

V_DD

(MHz) (MT/s)

(W)¹

1500

600

1600

1.0

65

Typical

4.27

0.63

0.91

0.63

0.69

0.57

0.63

0.41

0.47

0.41

5.31

7.38

7.96

5.25

5.73

6.30

4.57

5.05

5.52

2, 3

105

Thermal

Maximum

Typical

6.00

6.58

4.21

4.63

5.20

3.59

4.01

4.48

5, 7

4, 6, 7

2, 3

1400

1200

600

500

1.0

65

105

Thermal

Maximum

Typical

5, 7

4, 6, 7

2, 3

65

105

Thermal

Maximum

5, 7

4, 6, 7

1. Combined power of V_DDC, V_DDand S1V_DDwith platform at power-on reset default state, DDR controller and all SerDes

banks active. Does not include I/O power.

2. Typical power assumes Dhrystone running with activity factor of 80ꢀ (on all cores) and is executing DMA on the platform

with 100ꢀ activity factor.

3. Typical power based on nominal, processed device.

4. Maximum power assumes Dhrystone running with activity factor at 100ꢀ (on all cores) and is executing DMA on the

platform at 115ꢀ activity factor.

5. Thermal power assumes Dhrystone running with activity factor of 80ꢀ (on all cores) and executing DMA on the platform at

100ꢀ activity factor.

6. Maximum power is provided for power supply design sizing.

7. Thermal and maximum power are based on worst case processed device.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

58

Freescale Semiconductor, Inc.

Electrical characteristics

This table shows the power dissipation in deep sleep mode.

Table 10. Deep sleep power dissipation, 1.0V, 35⁰C

Power (W)

Total Core and platform

power

V_DD

V_DDC

S1V_DD

(W)

-

0.4

-

0.4

Note: V_DDand S1V_DDare switched off during deep sleep mode.

This table provides low power mode saving estimation.

Table 11. Single core, Single cluster low power mode power savings, 1.0V

65⁰C^1,2,3

Mode

Core

Frequency = Frequency = Frequency = Frequency =

1.0 GHz 1.2 GHz 1.4 GHz 1.5 GHz

Core

Units

Comment

Note

s

PH10 0.19

0.23 0.27 0.29

Watts Saving realized moving from PH00 to

PH10 state, single core.

4

PH15 0.19

0.23

0.38

0.27

0.45

0.29

0.48

Watts Saving realized moving from PH10

state to PH15 state, single core.

4

LPM2 0.32

0

Watts Saving realized moving from PH15 to

LPM20, single core

4, 5

Notes:

1. Power for V_DDonly.

2. Typical power assumes Dhrystone running ( PH00 state) with activity factor of 70ꢀ.

3. Typical power based on nominal process distribution for this device.

4. PH10, PH15, LPM20 power savings with 1 core. Maximum savings would be N times, where N is the number of used

cores.

5. LPM20 has all platform clocks disabled.

3.5.1 I/O DC power supply recommendation

This table provides the estimated I/O power numbers for each block: DDR, PCI Express,

eLBC, eTSEC, SGMII, eSDHC, USB, eSPI, DUART, IIC, DIU, SATA and GPIO. Note

that these numbers are based on design estimates only

Table 12. I/O power supply estimated values

Interface

Parameter

Symbol

Typical

Maximum

Deep

Sleep

Unit

mW

Note

1, 2, 6

DDR3L

1600MT/s data rate

G1VDD(1.35V)

860

1760

-

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

59

Electrical characteristics

Table 12. I/O power supply estimated values (continued)

Interface

DDR4

Parameter

Symbol

Typical

Maximum

Deep

Sleep

Unit

Note

1600MT/s data rate

1x, 2.5 GT/s

2x, 2.5 GT/s

4x, 2.5 GT/s

8x, 2.5 GT/s

1x, 5 GT/s

G1VDD(1.2V)

X1VDD(1.35V)

660

1000

62

-

mW

1, 8, 9

1, 4, 7

PCI

Express

50

81

94

145

274

50

158

287

70

2x, 5 GT/s

90

100

160

290

60

4x, 5 GT/s

150

280

50

8x, 5 GT/s

SGMII

1x, 1.25 G-baud

2x, 1.25 G-baud

4x, 1.25 G-baud

1x, 3.125 G-baud

2x, 3.125 G-baud

1x, 3.0 Gbps

2x, 3.0 Gbps

16-bit, 100MHz

RGMII

X1VDD(1.35V)

-

mW

1, 4, 7

70

90

130

50

140

60

SGMII

SATA

X1VDD(1.35V)

-

mW

1, 4, 7

80

90

50

60

70

80

IFC

OVDD(1.8V)

L1VDD(2.5V)

L1VDD(1.8V)

L1VDD(3.3V)

LVDD(2.5V)

LVDD(1.8V)

EVDD(3.3V)

EVDD(1.8V)

USB_HVDD(3.3V)

USB_OVDD(1.8V)

CVDD(3.3V)

CVDD(1.8V)

DVDD(3.3V)

DVDD(2.5V)

DVDD(3.3V)

DVDD(2.5V)

DVDD(1.8V)

DVDD(3.3V)

DVDD(2.5V)

DVDD(1.8V)

DVDD(3.3V)

LVDD(2.5V)

35

61

-

mW

1, 3, 7

EC1

155

115

155

115

11

220

180

220

180

17

13

11

18

-

RGMII

MII

EC2

RGMII

-

eSDHC

-

mW

1, 3, 7

7

10

-

USB1,

USB2

40

60

100

14

110

22

100

eSPI

-

11

16

DIU

QE

70

90

mW

1, 3, 7

15

21

11

17

I2C

14

22

mW

1, 3, 7

10

16

8

13

DUART

14

22

10

15

8

12

TDM

10

14

mW

1, 3, 7

IEEE1588

16

21

Table continues on the next page...

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

60

Freescale Semiconductor, Inc.

Electrical characteristics

Table 12. I/O power supply estimated values (continued)

Interface

GPIO

Parameter

Symbol

Typical

Maximum

Deep

Sleep

Unit

mW

Note

x8

3.3V

2.5V

1.8V

5

4

3

8

-

1, 3, 5, 7

7

-

5

-

System

Control

O1VDD(1.8V)

45

70

9

mW

1, 3, 7

PLL core

and system

AVDD_CGA1 (1.8 V)

AVDD_CGA2 (1.8V)

AVDD_PLAT(1.8 V)

AVDD_D1(1.8V)

20

-

2

-

PLL DDR

30

50

40

50

mW

1, 3, 7

PLL

SerDes

AVDD_SD1_PLL1,

AVDD_SD1_PLL2(1.35

V)

-

PROG_SF

P

PROG_SFP (1.8 V)

173

1

-

mW

-

TH_VDD

TH_VDD(1.8 V)

1. The typical values are estimates based on simulations 65ºC junction temperature.

2. Typical DDR power numbers are based on 2 Rank DIMM with 40ꢀ utilization.

3. Assuming 15 pF total capacitance load per pin.

4. The total power numbers of X1VDD is dependent on customer application use case. This table lists all the SerDes

configurations possible for the device. To get the X1VDD power numbers, the user should add the combined lanes to match

to the total SerDes Lanes used, not simply multiply the power numbers by the number of lanes.

5. GPIO are supported on OV_DD, O1V_DD, L1V_DD, LV_DD, DV_DD, CV_DDand EV_DDpower rails.

6. Maximum DDR power numbers are based on 2 Ranks DIMM with 100ꢀ utilization.

7. The maximum values are dependent on actual use case such as what application, external components used,

environmental conditions such as temperature voltage and frequency. This is not intended to be the maximum guaranteed

power. Expect different results depending on the use case.The maximum values are estimated and they are based on

simulations at 105ºC junction temperature.

8. Typical DDR4 power numbers are based on single Rank DIMM with 40ꢀ utilization.

9. Maximum DDR4 power numbers are based on single Rank DIMM with 100ꢀ utilization.

3.6 Input clocks

3.6.1 System clock (SYSCLK) timing specifications

This section provides the system clock DC and AC timing specifications.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

61

Electrical characteristics

3.6.1.1 System clock DC timing specifications

This table provides the system clock (SYSCLK) DC specifications.

Table 13. SYSCLK DC electrical characteristics³

Parameter

Input high voltage

Symbol

Min

Typical

Max

Unit

Notes

V_IH

V_IL

C_IN

1.2

-

V

1

-

Input low voltage

Input capacitance

-

0.6

12

V

7

pF

Input current (O1V_IN= 0 V or O1V_IN

O1V_DD)

=

I_IN

-

50

µA

2

Note:

1. The min V_ILand max V_IHvalues are based on the respective min and max O1V_INvalues found in Table 3.

2. The symbol OV_IN, in this case, represents the O1V_INsymbol referenced in Recommended operating conditions.

3. At recommended operating conditions with O1V_DD= 1.8 V, see Table 3.

3.6.1.2 System clock AC timing specifications

This table provides the system clock (SYSCLK) AC timing specifications.

Table 14. SYSCLK AC timing specifications¹

Parameter/condition

SYSCLK frequency

Symbol

f_SYSCLK

Min

Typ

Max

Unit

MHz

Notes

64.0

7.5

40

1

-

133.3

15.6

60

2, 6

SYSCLK cycle time

SYSCLK duty cycle

SYSCLK slew rate

t_SYSCLK

ns

1, 2

t_KHK/t_SYSCLK

ꢀ

2

3

-

4

V/ns

ps

SYSCLK peak period jitter

-

150

500

1.8

SYSCLK jitter phase noise at -56 dBc -

-

KHz

V

4

-

AC Input Swing Limits at 1.8 V

O1V_DD

ΔV_AC

1.08

Notes:

1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency does not exceed

their respective maximum or minimum operating frequencies.

2. Measured at the rising edge and/or the falling edge at O1V_DD/2.

3. Slew rate as measured from 0.35 x O1V_DDto 0.65 x O1V_DD

4. Phase noise is calculated as FFT of TIE jitter.

.

5. At recommended operating conditions with O1V_DD= 1.8V, see Table 3.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

62

Freescale Semiconductor, Inc.

Electrical characteristics

3.6.2 Spread-spectrum sources

Spread-spectrum clock sources are an increasingly popular way to control

electromagnetic interference emissions (EMI) by spreading the emitted noise to a wider

spectrum and reducing the peak noise magnitude in order to meet industry and

government requirements. These clock sources intentionally add long-term jitter to

diffuse the EMI spectral content. The jitter specification given in Table 14 considers

short-term (cycle-to-cycle) jitter only. The clock generator's cycle-to-cycle output jitter

should meet the chip's input cycle-to-cycle jitter requirement. Frequency modulation and

spread are separate concerns; the chip is compatible with spread-spectrum sources if the

recommendations listed in Table 14 are observed.

Table 15. Spread-spectrum clock source recommendations³

Parameter

Frequency modulation

Min

Max

Unit

Notes

-

60

kHz

ꢀ

-

Frequency spread

1.0

1, 2

Notes:

1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and

maximum specifications given in Table 14.

2. Maximum spread-spectrum frequency may not result in exceeding any maximum operating frequency of the device.

3. At recommended operating conditions with O1VDD = 1.8 V, see Table 3.

CAUTION

The processor's minimum and maximum SYSCLK and core/

platform/DDR frequencies must not be exceeded regardless of

the type of clock source. Therefore, systems in which the

processor is operated at its maximum rated core/platform/DDR

frequency should avoid violating the stated limits by using

down-spreading only.

3.6.3 Real-time clock timing

The real-time clock timing (RTC) input is sampled by the platform clock. The output of

the sampling latch is then used as an input to the counters of the MPIC and the time base

unit of the core; there is no need for jitter specification. The minimum period of the RTC

signal should be greater than or equal to 16x the period of the platform clock with a 50%

duty cycle. There is no minimum RTC frequency; RTC may be grounded if not needed.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

63

Electrical characteristics

3.6.4 Gigabit Ethernet reference clock timing

This table provides the Ethernet gigabit reference clock DC specifications.

Table 16. ECn_GTX_CLK125 DC electrical characteristics (L1VDD/LVDD=1.8V)

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Input high

voltage

V_IH

V_IL

C_IN

I_IN

0.7 * VDD

-

V

2, 4

-

Input low

voltage

-

0.2 * VDD

V

Input

capacitance

6

pF

µA

Input current

50

3

(V_IN= 0 V or V_IN

= L1V_DD)/LV_DD

1. At recommended operating conditions with L1V_DD/LV_DD= 1.8 V

2. The min V_ILand max V_IHvalues are based on the respective min and max V_INvalues found in Table 3.

)

3. The symbol V_IN, in this case, represents the L1V_IN/LV_INsymbol referenced in Recommended operating conditions.

4. ECn_GTX_CLK125 is powered by L1V_DDand LV_DD. VDD should be replaced by the respective IO power supply.

This table provides the Ethernet gigabit reference clock DC specifications.

Table 17. ECn_GTX_CLK125 DC electrical characteristics ((L1VDD/LVDD=2.5V)

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Input high

voltage

V_IH

V_IL

C_IN

I_IN

0.7 * VDD

-

V

2, 4

-

Input low

voltage

-

0.2 * VDD

V

Input

capacitance

6

pF

µA

Input current

50

3

(V_IN= 0 V or V_IN

= L1V_DD)/LV_DD

1. At recommended operating conditions with L1V_DD/LV_DD= 2.5 V

2. The min V_ILand max V_IHvalues are based on the respective min and max V_INvalues found in Table 3.

)

3. The symbol V_IN, in this case, represents the L1V_IN/LV_INsymbol referenced in Recommended operating conditions.

4. ECn_GTX_CLK125 is powered by L1V_DDand LV_DD. VDD should be replaced by the respective IO power supply.

This table provides the Ethernet gigabit reference clocks AC timing specifications.

Table 18. ECn_GTX_CLK125 AC timing specifications ¹

Parameter/Condition

Symbol

t_G125

Min

Typical

Max

Unit

Notes

ECn_GTX_CLK125 frequency

125 - 100 ppm 125

125 + 100 ppm MHz

-

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Electrical characteristics

Table 18. ECn_GTX_CLK125 AC timing specifications ¹(continued)

Parameter/Condition

ECn_GTX_CLK125 cycle time

ECn_GTX_CLK125 rise and fall time

L1/LV_DD= 1.8 V

Symbol

t_G125

Min

Typical

Max

Unit

Notes

-

8

-

ns

-

t_G125R/t_G125F

2

0.54

0.75

L1/LV_DD= 2.5 V

ECn_GTX_CLK125 duty cycle

1000Base-T for RGMII

t_G125H/t_G125

40

-

60

ꢀ

3

ECn_GTX_CLK125 jitter

-

150

ps

1. At recommended operating conditions with L1/LV_DD= 1.8 V 90mV / 2.5 V 125 mV.

2. Rise and fall times for ECn_GTX_CLK125 are measured from 0.5 and 2.0 V for L1/LV_DD= 2.5 V.

3. ECn_GTX_CLK125 is used to generate the GTX clock for the Ethernet transmitter. See RGMII AC timing specifications for

duty cycle for 10Base-T and 100Base-T reference clock.

3.6.5 DDR clock timing

This section provides the DDR clock DC and AC timing specifications.

3.6.5.1 DDR clock DC timing specifications

This table provides the DDR clock (DDRCLK) DC specifications.

Table 19. DDRCLK DC electrical characteristics³

Parameter

Input high voltage

Symbol

Min

Typical

Max

Unit

Notes

V_IH

V_IL

C_IN

1.25

-

V

1

-

Input low voltage

Input capacitance

-

0.6

12

V

7

pF

Input current (OV_IN= 0 V or OV_IN

OV_DD)

=

I_IN

-

50

μA

2

Note:

1. The min V_ILand max V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2. The symbol OV_IN, in this case, represents the OV_INsymbol referenced in Recommended operating conditions.

3. At recommended operating conditions with OV_DD= 1.8 V, see Table 3.

3.6.5.2 DDR clock AC timing specifications

This table provides the DDR clock (DDRCLK) AC timing specifications.

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Electrical characteristics

Table 20. DDRCLK AC timing specifications⁵

Parameter/Condition

DDRCLK frequency

Symbol

f_DDRCLK

Min

Typ

Max

Unit

MHz

Notes

1, 2

64.0

7.5

40

1

-

133.3

15.6

60

DDRCLK cycle time

t_DDRCLK

ns

1, 2

DDRCLK duty cycle

t_KHK/t_DDRCLK

ꢀ

2

3

-

DDRCLK slew rate

-

4

V/ns

ps

DDRCLK peak period jitter

-

150

500

1.8

DDRCLK jitter phase noise at -56 dBc -

AC Input Swing Limits at 1.8 V OV_DDΔV_AC

Notes:

-

KHz

V

4

-

1.08

1. Caution: The relevant clock ratio settings must be chosen such that the resulting DDRCLK frequency does not exceed

their respective maximum or minimum operating frequencies.

2. Measured at the rising edge and/or the falling edge at OV_DD/2.

3. Slew rate as measured from 0.35 x OV_DDto 0.65 x OV_DD

.

4. Phase noise is calculated as FFT of TIE jitter.

5. At recommended operating conditions with OV_DD= 1.8V, see Table 3.

3.6.6 Differential System clock (DIFF_SYSCLK/DIFF_SYSCLK_B)

timing specifications

"Single Oscillator Source" clocking mode requires single onboard oscillator to provide

reference clock input to Differential System clock pair (DIFF_SYSCLK/

DIFF_SYSCLK_B).

This Differential clock pair can be configured to provide clock to Core, Platform, DDR

and USB PLL's

This figure shows a receiver reference diagram of the Differential System clock.

DIFF_SYSCLK

LVDS

RX

100 Ohm

DIFF_SYSCLK_B

Figure 11. LVDS receiver

This section provides the differential system clock DC and AC timing specifications.

3.6.6.1 Differential System clock DC timing specifications

For DC timing specification, see DC-level requirement for SerDes reference clocks

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Electrical characteristics

The Differential System clock receivers core power supply voltage requirements

(O1V_DD) are as specified in Recommended operating conditions.

The Differential system clock can also be single-ended. For this DIFF_SYSCLK_B

should be connected to O1V_DD/2.

3.6.6.2 Differential System clock AC timing specifications

Differential System clock(DIFF_SYSCLK/DIFF_SYSCLK_B) input pair supports input

clock frequency of 100MHz

For AC timing specification, see AC requirements for SerDes reference clocks

Spread Spectrum clocking is not supported on Differential System clock pair input.

3.6.7 Other input clocks

A description of the overall clocking of this device is available in the chip reference

manual in the form of a clock subsystem block diagram. For information about the input

clock requirements of functional modules sourced external of the chip, such as SerDes,

Ethernet management, eSDHC, IFC, see the specific interface section.

3.7 RESET initialization

This section describes the AC electrical specifications for the RESET initialization timing

requirements. This table describes the AC electrical specifications for the RESET

initialization timing.

Table 21. RESET Initialization timing specifications

Parameter/Condition

Required assertion time of PORESET_B

Min

Max

Unit

Notes

1

32

-

ms

1

Required input assertion time of HRESET_B

Maximum rise/fall time of HRESET_B

Maximum rise/fall time of PORESET_B

-

SYSCLKs

SYSCLK

μs

2, 3

4

10

1

-

4

PLL input setup time with stable SYSCLK before HRESET_B negation 100

-

Input setup time for POR configs with respect to negation of

PORESET_B

4

2

-

SYSCLKs

2

Input hold time for all POR configs with respect to negation of

PORESET_B

-

SYSCLKs

2

Maximum valid-to-high impedance time for actively driven POR

configs with respect to negation of PORESET_B

5

1. PORESET_B must be driven asserted before the core and platform power supplies are powered up.

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Electrical characteristics

Table 21. RESET Initialization timing specifications

Parameter/Condition

2. SYSCLK is the primary clock input for the chip.

Min

Max

Unit

Notes

3. The device asserts HRESET_B as an output when PORESET_B is asserted to initiate the power-on reset process. The

device releases HRESET_B sometime after PORESET_B is deasserted. The exact sequencing of HRESET_B deassertion is

documented in section "Power-On Reset Sequence" in the chip reference manual.

4. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

This table provides the PLL lock times.

Table 22. PLL lock times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times (Core, platform, DDR only)

-

100

μs

-

3.8 DDR4 and DDR3L SDRAM controller

This section describes the DC and AC electrical specifications for the DDR4 and DDR3L

SDRAM controller interface. Note that the required G1V_DD(typ) voltage is 1.2 V when

interfacing to DDR4 SDRAM and the G1V_DD(typ) voltage is 1.35 V when interfacing to

DDR3L SDRAM.

3.8.1 DDR4 and DDR3L SDRAM interface DC electrical

characteristics

This table provides the recommended operating conditions for the DDR SDRAM

controller when interfacing to DDR3L SDRAM.

Table 23. DDR3L SDRAM interface DC electrical characteristics (G1V_DD

1.35 V)^{1, 9}

=

Parameter

I/O reference voltage

Symbol

Min

Max

Unit

Note

2, 3, 4

D1_MV_REF

0.49 x G1V_DD

0.51 x G1V_DD

V

Input high voltage

V_IH

V_IL

I_OZ

I_OH

I_OL

D1_MV_REF+ 0.090 G1V_DD

V

5

Input low voltage

GND

-100

-

D1_MV_REF- 0.090

V

5

I/O leakage current

100

-23.3

-

μA

6

Output high current (V_OUT= 0.641V)

Output low current (V_OUT=0.641 V)

mA

7, 8

23.3

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Electrical characteristics

Table 23. DDR3L SDRAM interface DC electrical characteristics (G1V_DD= 1.35 V)^{1, 9}

(continued)

Parameter

Symbol

Min

Max

Unit

Note

Notes:

1. G1V_DDis expected to be within 50 mV of the DRAM's voltage supply at all times. The voltage supply of DRAM and

memory controller may or may not be from the same source.

2. D1_MV_REFis expected to be equal to 0.5 x G1V_DDand to track G1V_DDDC variations as measured at the receiver. Peak-

to-peak noise on D1_MV_REFmay not exceed the D1_MV_REFDC level by more than 1ꢀ of G1V_DD(that is, 13.5mV).

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be

equal to D1_MV_REFwith a min value of D1_MV_REF- 0.04 and a max value of D1_MV_REF+ 0.04. V_TTshould track variations

in the DC level of D1_MV_REF

.

4. The voltage regulator for D1_MV_REFmust meet the specifications stated in Table 25.

5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.

6. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ G1V_DD

7. See the IBIS model for the complete output IV curve characteristics.

8. I_OHand I_OLare measured at G1V_DD= 1.283 V.

.

9. For recommended operating conditions, see Table 3.

This table provides the recommended operating conditions for the DDR SDRAM

controller when interfacing to DDR4 SDRAM.

Table 24. DDR4 SDRAM interface DC electrical characteristics (G1V_DD= 1.2

V)^{1, 8}

Parameter

Symbol

V_IL

Min

Max

Unit

Note

3, 7

Input low

Input high

-

0.7 x G1V_DD- 0.175 V

V_IH

0.7 x G1V_DD

0.175

+

-

V

3, 7

Output high current (V_OUT= 0.57V)

Output low current (V_OUT=0.57V)

I/O leakage current

I_OH

I_OL

I_OZ

-

-20.7

-

mA

μA

4, 5

6

20.7

-100

100

Notes:

1. G1V_DDis expected to be within 60 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's

voltage supply may or may not be from the same source.

2. VTT and VREFCA are applied directly to the DRAM device. Both VTT and VREFCA voltages must track G1VDD/2.

3. Input capacitance load for MDQ, MDQS, and MDQS_B are available in the IBIS models.

4. I_OHand I_OLare measured at G1V_DD= 1.14 V.

5. Refer to the IBIS model for the complete output IV curve characteristics.

6. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ G1V_DD

7. Internal Vref for data bus must be set to 0.7 x G1VDD.

.

8. For recommended operating conditions, see Table 3.

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Electrical characteristics

This table provides the current draw characteristics for D1_MV_REF

.

1

Table 25. Current draw characteristics for D1_MV_REF

Parameter

Symbol

Min

Max

Unit

Notes

Current draw for DDR3L SDRAM for

D1_MV_REF

I_{D1_MVREF}

-

500

μA

-

Note:

1. For recommended operating conditions, see Table 3.

3.8.2 DDR4 and DDR3L SDRAM interface AC timing specifications

This section provides the AC timing specifications for the DDR SDRAM controller

interface. The DDR controller supports DDR4 and DDR3L memories. Note that the

required G1V_DD(typ) voltage is 1.35 V or 1.2V when interfacing to DDR3L or DDR4

SDRAM respectively.

3.8.2.1 DDR4 and DDR3L SDRAM interface input AC timing specifications

This table provides the input AC timing specifications for the DDR controller when

interfacing to DDR3L SDRAM.

Table 26. DDR3L SDRAM interface input AC timing specifications¹

Parameter

Symbol

Min

Max

D1_MVREF- 0.135

D1_MVREF- 0.160

-

Unit

Notes

AC input low voltage

AC input high voltage

Notes:

> 1200 MT/s data rate V_ILAC

-

V

-

≤ 1200 MT/s data rate

> 1200 MT/s data rate V_IHAC

≤ 1200 MT/s data rate

D1_MVREF+ 0.135

D1_MVREF+ 0.160

V

1. For recommended operating conditions, see Table 3.

This table provides the input AC timing specifications for the DDR controller when

interfacing to DDR4 SDRAM.

Table 27. DDR4 SDRAM interface input AC timing specifications¹

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage ≤ 1600 MT/s data rate V_ILAC

-

0.7 x G1VDD -

0.175

V

-

AC input high voltage

≤ 1600 MT/s data rate V_IHAC

0.7 x G1VDD +

0.175

-

V

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Electrical characteristics

Table 27. DDR4 SDRAM interface input AC timing specifications¹(continued)

Parameter

Symbol

Min

Max

Unit

Notes

Notes:

1. For recommended operating conditions, see Table 3.

This table provides the input AC timing specifications for the DDR controller when

interfacing to DDR3L and DDR4 SDRAM.

Table 28. DDR4 and DDR3L SDRAM interface input AC timing

specifications³

Parameter

Controller Skew for MDQS-MDQ/MECC

1600 MT/s data rate

Symbol

t_CISKEW

Min

Max

Unit

Notes

ps

-112

-125

-142

-170

112

125

142

170

1

1300 MT/s data rate

1200 MT/s data rate

1, 4

1000 MT/s data rate

Tolerated Skew for MDQS-MDQ/MECC

1600 MT/s data rate

t_DISKEW

-200

-250

-275

-300

200

250

275

300

2

1300 MT/s data rate

2

1200 MT/s data rate

2, 4

1000 MT/s data rate

1. t_CISKEWrepresents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

is captured with MDQS[n]. This must be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t_DISKEW.This can be

determined by the following equation: t_DISKEW= (T ꢁ 4 - abs(t_CISKEW)) where T is the clock period and abs(t_CISKEW) is the

absolute value of t_CISKEW

.

3. For recommended operating conditions, see Table 3.

4. DDR3L only

This figure shows the DDR4 and DDR3L SDRAM interface input timing diagram.

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Electrical characteristics

MCK[n]_B

MCK[n]

t_MCK

MDQS[n]

MDQ[x]

t_DISKEW

D0

D1

t_DISKEW

Figure 12. DDR4 and DDR3L SDRAM Interface Input Timing Diagram

3.8.2.2 DDR4 and DDR3L SDRAM interface output AC timing

specifications

This table contains the output AC timing targets for the DDR4 SDRAM interface.

Table 29. DDR4 and DDR3L SDRAM interface output AC timing

specifications⁸

Parameter

MCK[n] cycle time

Symbol¹

Min

Max

Unit

Notes

t_MCK

1250

1876

ps

2

ADDR/CMD output setup with respect to MCK t_DDKHAS

1600 MT/s data rate

495

606

675

744

-

3

1300 MT/s data rate

1200 MT/s data rate

3, 6

1000 MT/s data rate

ADDR/CMD output hold with respect to MCK t_DDKHAX

1600 MT/s data rate

ps

495

606

675

744

-

3

1300 MT/s data rate

3

1200 MT/s data rate

3, 6

4

1000 MT/s data rate

MCK to MDQS Skew

t_DDKHMH

ps

> 1000 MT/s data rate, ≤ 1600 MT/s data rate

MDQ/MECC/MDM output Data eye

-245

245

7

t_DDKXDEYE

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Electrical characteristics

Table 29. DDR4 and DDR3L SDRAM interface output AC timing specifications⁸(continued)

Parameter

1600 MT/s data rate

Symbol¹

Min

Max

Unit

Notes

400

500

550

600

-

5

1300 MT/s data rate

1200 MT/s data rate

1000 MT/s data rate

MDQS preamble

5, 6

t_DDKHMP

t_DDKHME

900 x t_MCK

400 x t_MCK

ps

-

MDQS postamble

600 x t_MCK

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. Output hold time can be read as DDR timing (DD)

from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, t_DDKHAS

symbolizes DDR timing (DD) for the time t_MCKmemory clock reference (K) goes from the high (H) state until outputs (A) are

setup (S) or output valid time. Also, t_DDKLDXsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference (K) goes

low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals.

3. ADDR/CMD/CNTL includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS.

4. Note that t_DDKHMHfollows the symbol conventions described in note 1. For example, t_DDKHMHdescribes the DDR timing

(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t_DDKHMHcan be modified through

control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the

same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two

parameters have been set to the same adjustment value. See the chip reference manual for a description and explanation of

the timing modifications enabled by the use of these bits.

5. Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller

will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization.

6. DDR3L only

7. Note that it is required to program the start value of the MDQS adjust for write leveling.

8. For recommended operating conditions, see Table 3.

NOTE

For the ADDR/CMD/CNTL setup and hold specifications in

Table 29, it is assumed that the clock control register is set to

adjust the memory clocks by ½ applied cycle.

This figure shows the DDR4 and DDR3L SDRAM interface output timing for the MCK

to MDQS skew measurement (t_DDKHMH).

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73

Electrical characteristics

MCK[n]_B

MCK[n]

t

MCK

t

DDKHMH(max)

MDQS

t

DDKHMH(min)

Figure 13. t_DDKHMHtiming diagram

This figure shows the DDR4 and DDR3L SDRAM output timing diagram.

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Electrical characteristics

MCK_B

MCK

t_MCK

t_DDKHAS

t_DDKHAX

NOOP

ADDR/CMD

Write A0

tDDKHMP

t_DDKHMH

MDQS[n]

MDQ[x]

t_DDKHME

D0

D1

tDDKXDEYE

Figure 14. DDR4 and DDR3L output timing diagram

3.9 eSPI interface

This section describes the DC and AC electrical specifications for the eSPI interface.

3.9.1 eSPI DC electrical characteristics

This table provides the DC electrical characteristics for the eSPI interface operating at

CV_DD= 1.8 V.

Table 30. eSPI DC electrical characteristics (1.8 V)¹

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

Input low voltage

V_IH

V_IL

I_IN

0.7 * CVDD

-

V

2

3

-

0.2 * CVDD

V

Input current (V_IN= 0 V or V_IN= CV_DD

)

-

50

-

µA

V

Output high voltage

V_OH

1.35

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Electrical characteristics

Table 30. eSPI DC electrical characteristics (1.8 V)¹(continued)

Parameter

Symbol

Min

Max

Unit

Notes

(CV_DD= min, I_OH= -0.5 mA)

Output low voltage

(CV_DD= min, I_OL= 0.5 mA)

Notes:

V_OL

-

0.4

V

-

1. For recommended operating conditions, see Table 3.

2. The min V_ILand max V_IHvalues are based on the respective min and max CV_INvalues found in Table 3.

3. The symbol V_IN, in this case, represents the CV_INsymbol referenced in Recommended operating conditions.

This table provides the DC electrical characteristics for the eSPI interface operating at

CV_DD= 3.3 V.

Table 31. eSPI DC electrical characteristics (3.3 V)¹

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 * CVDD

-

V

2

-

V_IL

I_IN

-

0.2 * CVDD

V

Input current (V_IN= 0 V or V_IN= CV_DD

)

-

50

-

µA

V

Output high voltage

V_OH

2.4

-

(CV_DD= min, I_OH= -2.0 mA)

Output low voltage

V_OL

-

0.4

V

-

(CV_DD= min, I_OL= 2.0 mA)

Notes:

1. For recommended operating conditions, see Table 3.

2. The min V_ILand max V_IHvalues are based on the respective min and max CV_INvalues found in Table 3.

3.9.2 eSPI AC timing specifications

This table provides the eSPI input and output AC timing specifications.

Table 32. eSPI AC timing specifications³

Parameter/Condition

Symbol ²

Min

Max

Unit Notes

SPI_MOSI output-Master data (internal t_NIKHOX

clock) hold time

-0.49 + (t_{PLATFORM_CLK/2}* -

SPMODE[HO_ADJ])

ns

1, 2

1

SPI_MOSI output-Master data (internal t_NIKHOV

clock) delay

-

0.89 + (t_{PLATFORM_CLK/2 *}ns

SPMODE[HO_ADJ])

SPI_CS outputs-Master data (internal t_NIKHOX2

clock) hold time

-100

-

ps

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Electrical characteristics

Table 32. eSPI AC timing specifications³(continued)

Parameter/Condition

Symbol ²

Min

Max

Unit Notes

SPI_CS outputs-Master data (internal t_NIKHOV2

clock) delay

-

6.0

ns

1

SPI inputs-Master data (internal clock) t_NIIVKH

input setup time

6.6

0

-

ns

-

SPI inputs-Master data (internal clock) t_NIIXKH

input hold time

-

Clock-high time

Clock-low time

Notes:

t_NIKCKH

t_NIKCKL

4

-

ns

-

1. See the chip reference manual for details about the SPMODE register.

2. Output specifications are measured from the 50ꢀ level of the rising edge of CLKIN to the 50ꢀ level of the signal. Timings

are measured at the pin.

3. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_NIKHOVsymbolizes the NMSI outputs

internal timing (NI) for the time t_SPImemory clock reference (K) goes from the high state (H) until outputs (O) are valid (V).

4. Refer AN4375 to calculate maximum achievable eSPI interface frequency on a system.

This figure provides the AC test load for the eSPI.

Output

CV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 15. eSPI AC test load

This figure provides the eSPI clock output timing diagram.

t

NIKCKH

V

OH

V

OL

t

NIKCKL

eSPI clock

Figure 16. eSPI clock output timing diagram

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Electrical characteristics

This figure represents the AC timing from Table 32 in master mode (internal clock). Note

that although the specifications generally reference the rising edge of the clock, these AC

timing diagrams also apply when the falling edge is the active edge. Also, note that the

clock edge is selectable on eSPI.

1

SPICLK (output)

t_NIIXKH

t_NIIVKH

Input Signals:

t_NIKHOX

t_NIKHOV

Output Signals:

t_NIKHOX2

t_NIKHOV2

Output Signals:

1

SPI_CS[0:3]

Note 1: SPICLK appears on the interface only after CS assertion.

Figure 17. eSPI AC timing in master mode (internal clock) diagram

3.10 DUART interface

This section describes the DC and AC electrical specifications for the DUART interface.

3.10.1 DUART DC electrical characteristics

This table provides the DC electrical characteristics for the DUART interface at DV_DD

3.3 V.

=

Table 33. DUART DC electrical characteristics (3.3 V)³

Parameter

Input high voltage

Symbol

Min

0.7*VDD

Max

Unit

Notes

V_IH

V_IL

I_IN

-

V

1, 4

3

Input low voltage

-

0.2*VDD

50

V

Input current (V_IN= 0 V or V_IN

=

µA

DV_DD

)

Output high voltage

V_OH

2.4

-

V

-

(DV_DD= min, I_OH= -2.0 mA)

Output low voltage

V_OL

0.4

(DV_DD= min, I_OL= 2.0 mA)

Table continues on the next page...

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Electrical characteristics

Table 33. DUART DC electrical characteristics (3.3 V)³(continued)

Parameter

Symbol

Min

Max

Unit

Notes

Notes:

1. The min V_ILand max V_IHvalues are based on the min and max DV_INrespective values found in Table 3.

2. The symbol DV_INrepresents the input voltage of the supply. It is referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

4. VDD should be replaced by the respective IO power supply.

This table provides the DC electrical characteristics for the DUART interface at DV_DD

2.5 V.

=

Table 34. DUART DC electrical characteristics(2.5 V)³

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

Input low voltage

V_IH

V_IL

I_IN

0.7*VDD

-

V

1, 4

-

0.2*VDD

V

1, 4

Input current (DV_IN= 0 V or DV_IN= DV_DD

)

-

50

-

µA

V

2

-

Output high voltage (DV_DD= min, I_OH= -1 mA)

Output low voltage (DV_DD= min, I_OL= 1 mA)

Notes:

V_OH

V_OL

2.0

-

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the min and max DV_INrespective values found in Table 3.

2. The symbol DV_INrepresents the input voltage of the supply. It is referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

4. VDD should be replaced by the respective IO power supply.

This table provides the DC electrical characteristics for the DUART interface at DV_DD

1.8 V.

=

Table 35. DUART DC electrical characteristics(1.8 V)³

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

Input low voltage

V_IH

V_IL

I_IN

0.7*VDD

-

V

1, 4

-

0.2*VDD

V

1, 4

Input current (DV_IN= 0 V or DV_IN= DV_DD

)

-

50

-

µA

V

2

-

Output high voltage (DV_DD= min, I_OH= -0.5 mA)

Output low voltage (DV_DD= min, I_OL= 0.5 mA)

Notes:

V_OH

V_OL

1.35

-

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the min and max DV_INrespective values found in Table 3.

2.The symbol DV_INrepresents the input voltage of the supply.It is referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

4. VDD should be replaced by the respective IO power supply.

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Electrical characteristics

3.10.2 DUART AC electrical specifications

This table provides the AC timing parameters for the DUART interface.

Table 36. DUART AC timing specifications

Parameter

Value

f_PLAT/(2 x 1,048,576)

f_PLAT/(2 x 16)

Unit

Notes

Minimum baud rate

Maximum baud rate

Notes:

baud

1, 3

1, 2

1. f_PLATrefers to the internal platform clock.

2. The actual attainable baud rate is limited by the latency of interrupt processing.

3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values

are sampled each 16^thsample.

3.11 Ethernet interface, Ethernet management interface, IEEE

Std 1588^™

This section provides the AC and DC electrical characteristics for the Ethernet controller

and the Ethernet management interface.

3.11.1 SGMII interface

Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of

the chip, as shown in Figure 18, where C_TXis the external (on board) AC-coupled

capacitor. Each SerDes transmitter differential pair features 100-Ω output impedance.

Each input of the SerDes receiver differential pair features 50-Ω on-die termination to

XGNDn. The reference circuit of the SerDes transmitter and receiver is shown in Figure

69.

3.11.1.1 SGMII clocking requirements for SD1_REF_CLKn_P and

SD1_REF_CLKn_N

When operating in SGMII mode, the ECn_GTX_CLK125 clock is not required for this

port. Instead, a SerDes reference clock is required on SD1_REF_CLK[1:2]_P and

SD1_REF_CLK[1:2]_N pins. SerDes lanes may be used for SerDes SGMII

configurations based on the RCW Configuration field SRDS_PRTCL.

For more information on these specifications, see SerDes reference clocks.

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Electrical characteristics

3.11.1.2 SGMII DC electrical characteristics

This section discusses the electrical characteristics for the SGMII interface.

3.11.1.2.1 SGMII and SGMII 2.5G transmit DC specifications

This table describes the SGMII SerDes transmitter AC-coupled DC electrical

characteristics. Transmitter DC characteristics are measured at the transmitter outputs

(SD1_TXn_P and SD1_TXn_N)as shown in Figure 19.

Table 37. SGMII DC transmitter electrical characteristics (X1V_DD= 1.35 V)⁴

Parameter

Output high voltage

Symbol

V_OH

Min

Typ

Max

Unit

mV

Notes

-

1.5 x │V_OD

│

1

-max

Output low voltage

Output differential voltage^{2, 3, 5}

V_OL

│V_OD

320

│

_-min/2

-

mV

│V_OD

│

500.0

459.0

417.0

376.0

333.0

292.0

250.0

100

725.0

TECR0[AMP

_RED]=0b00

0000

(XV_DD-Typat 1.35 V)

293.8

266.9

240.6

213.1

186.9

160.0

80

665.6

604.7

545.2

482.9

423.4

362.5

120

TECR0[AMP

_RED]=0b00

0001

TECR0[AMP

_RED]=0b00

0011

TECR0[AMP

_RED]=0b00

0010

TECR0[AMP

_RED]=0b00

0110

TECR0[AMP

_RED]=0b00

0111

TECR0[AMP

_RED]=0b01

0000

Output impedance (differential)

R_O

Ω

-

Notes:

1. This does not align to DC-coupled SGMII.

2. │V_OD│ = │V_{SD_TXn_P}- V_{SD_TXn_N}│. │V_OD│ is also referred to as output differential peak voltage. V_TX-DIFFp-p= 2 x │V_OD

│

.

3. The │V_OD│ value shown in the Typ column is based on the condition of XVDD_SRDSn-Typ = 1.35 V, no common mode

offset variation. SerDes transmitter is terminated with 100-Ω differential load between SDn _TXn_P and SDn_TXn_N.

4. For recommended operating conditions, see Table 3.

5. Example amplitude reduction setting for SGMII on SerDes1 lane E: SRDS1LN4TECR0[AMP_RED] = 0b000001 for an

output differential voltage of 459 mV typical.

This figure shows an example of a 4-wire AC-coupled SGMII serial link connection.

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Electrical characteristics

SDn_RXn_P

SDn_TXn_P

C_TX

50 Ω

Transmitter

Receiver

100 Ω

C_TX

SDn_TXn_N

SDn_RXn_N

50 Ω

SGMII

SerDes Interface

SDn_RXn_P

SDn_TXn_P

C_TX

50 Ω

Receiver

Transmitter

100 Ω

C_TX

SDn_RXn_N

SDn_TXn_N

50 Ω

Figure 18. 4-wire AC-coupled SGMII serial link connection example

This figure shows the SGMII transmitter DC measurement circuit.

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Electrical characteristics

SGMII

SerDes Interface

SDn_TXn_P

50 Ω

Transmitter

V_OD

100 Ω

50 Ω

SDn_TXn_N

Figure 19. SGMII transmitter DC measurement circuit

This table defines the SGMII 2.5G transmitter DC electrical characteristics for 3.125

GBaud.

Table 38. SGMII 2.5G transmitter DC electrical characteristics (X1V_DD= 1.35

V)¹

Parameter

Symbol

│V_OD

R_O

Min

Typical

Max

Unit

Notes

Output differential voltage

│

400

80

-

600

120

mV

Ω

-

Output impedance (differential)

100

Notes:

1. For recommended operating conditions, see Table 3.

3.11.1.2.2 SGMII and SGMII 2.5G DC receiver electrical characteristics

This table lists the SGMII DC receiver electrical characteristics. Source synchronous

clocking is not supported. Clock is recovered from the data.

Table 39. SGMII DC receiver electrical characteristics (S1V_DD= 1.0V)⁴

Parameter

DC input voltage range

Symbol

Min

Typ

Max

Unit Notes

-

N/A

100

175

30

-

1

Input differential voltage

REIDL_TH = 001

REIDL_TH = 100

REIDL_TH = 001

V_{RX_DIFFp-p}

-

1200

mV

2, 5

Loss of signal threshold

V_LOS

100

mV

3, 5

Table continues on the next page...

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Electrical characteristics

Table 39. SGMII DC receiver electrical characteristics (S1V_DD= 1.0V)⁴(continued)

Parameter

REIDL_TH = 100

Symbol

Min

Typ

Max

Unit Notes

65

80

-

175

120

Receiver differential input impedance

Notes:

Z_{RX_DIFF}

Ω

-

1. Input must be externally AC coupled.

2. V_{RX_DIFFp-p}is also referred to as peak-to-peak input differential voltage.

3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See PCI

Express DC physical layer receiver specifications, and PCI Express AC physical layer receiver specifications, for further

explanation.

4. For recommended operating conditions, see Table 3.

5. The REIDL_TH shown in the table refers to the chip's SRDSxLNmGCR1[REIDL_TH] bit field.

This table defines the SGMII 2.5G receiver DC electrical characteristics for 3.125

GBaud.

Table 40. SGMII 2.5G receiver DC timing specifications (S1V_DD= 1.0V)¹

Parameter

Input differential voltage

Loss of signal threshold

Receiver differential input impedance

Notes:

Symbol

Min

Typical

Max

Unit

Notes

V_{RX_DIFFp-p}200

-

1200

200

mV

Ω

-

V_LOS

75

80

Z_{RX_DIFF}

120

1. For recommended operating conditions, see Table 3.

3.11.1.3 SGMII AC timing specifications

This section discusses the AC timing specifications for the SGMII interface.

3.11.1.3.1 SGMII and SGMII 2.5G transmit AC timing specifications

This table provides the SGMII and SGMII 2.5G transmit AC timing specifications. A

source synchronous clock is not supported. The AC timing specifications do not include

RefClk jitter.

Table 41. SGMII transmit AC timing specifications⁴

Parameter

Deterministic jitter

Symbol

JD

Min

Typ

Max

Unit

UI p-p

Notes

-

0.17

0.35

-

Total jitter

JT

UI

2

1

Unit Interval: 1.25 GBaud (SGMII)

800 - 100 ppm 800

320 - 100 ppm 320

800 + 100 ppm ps

320 + 100 ppm ps

Unit Interval: 3.125 GBaud (2.5G SGMII]) UI

Table continues on the next page...

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Electrical characteristics

Table 41. SGMII transmit AC timing specifications⁴(continued)

Parameter

AC coupling capacitor

Symbol

C_TX

Min

Typ

Max

Unit

Notes

10

-

200

nF

3

Notes:

1. Each UI is 800 ps 100 ppm or 320 ps 100 ppm.

2. See Figure 21 for single frequency sinusoidal jitter measurements.

3. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter output.

4. For recommended operating conditions, see Table 3.

3.11.1.3.2 SGMII AC measurement details

Transmitter and receiver AC characteristics are measured at the transmitter outputs

(SD1_TXn_P and SD1_TXn_N) or at the receiver inputs (SD1_RXn_P and

SD1_RXn_N) respectively, as depicted in this figure.

D + package pin

C = C_TX

Transmitter

silicon

+ package

C = C_TX

D - package pin

R = 50 Ω

Figure 20. SGMII AC test/measurement load

3.11.1.3.3 SGMII and SGMII 2.5G receiver AC timing Specification

This table provides the SGMII and SGMII 2.5G receiver AC timing specifications. The

AC timing specifications do not include RefClk jitter. Source synchronous clocking is not

supported. Clock is recovered from the data.

Table 42. SGMII Receive AC timing specifications³

Parameter

Deterministic jitter tolerance

Symbol

J_D

Min

Typ

Max

Unit

Notes

-

0.37

0.55

UI p-p

1

Combined deterministic and random jitter tolerance J_DR

UI p-p

Table continues on the next page...

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Electrical characteristics

Table 42. SGMII Receive AC timing specifications³(continued)

Parameter

Symbol

J_T

Min

Typ

Max

Unit

Notes

1, 2

Total jitter tolerance

-

0.65

UI p-p

Bit error ratio

BER

UI

10^-12

-

Unit Interval: 1.25 GBaud (SGMII)

Unit Interval: 3.125 GBaud (2.5G SGMII])

Notes:

800 - 100 ppm 800

320 - 100 ppm 320

800 + 100 ppm ps

320 + 100 ppm ps

1

UI

1. Measured at receiver

2.Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 21. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

3. For recommended operating conditions, see Table 3.

The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in

the unshaded region of this figure.

8.5 UI p-p

Sinuosidal

Jitter

20 dB/dec

Amplitude

0.10 UI p-p

20 MHz

baud/142000

baud/1667

Frequency

Figure 21. Single-frequency sinusoidal jitter limits

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Electrical characteristics

3.11.2 1000Base-KX interface

This section discusses the electrical characteristics for the 1000Base-KX. Only AC-

coupled operation is supported.

3.11.2.1 1000Base-KX DC electrical characteristics

3.11.2.1.1 1000Base-KX Transmitter DC Specifications

This table describes the 1000Base-KX SerDes transmitter DC specification at TP1 per

IEEE Std 802.3ap-2007. Transmitter DC characteristics are measured at the transmitter

outputs (SD1_TXn_P and SD1_TXn_N).

Table 43. 1000Base-KX Transmitter DC Specifications

Parameter

Symbols

V_TX-DIFFp-p

Min

Typ

Max

1600

Units

Notes

Output differential

voltage

800

80

-

mV

1

-

Differential

resistance

T_RD

100

120

ohm

Notes:

1. SRDSxLNmTECR0[AMP_RED]=00_0000.

2. For recommended operating conditions, see Table 3.

3.11.2.1.2 1000Base-KX Receiver DC Specifications

Table below provides the 1000Base-KX receiver DC timing specifications.

Table 44. 1000Base-KX Receiver DC Specifications

Parameter

Symbols

V_RX-DIFFp-p

Min

Typical

Max

1600

Units

Notes

Input differential

voltage

-

mV

1

-

Differential

resistance

T_RDIN

80

120

ohm

Notes:

1. For recommended operating conditions, see Table 3.

3.11.2.2 1000Base-KX AC electrical characteristics

3.11.2.2.1 1000Base-KX Transmitter AC Specifications

Table below provides the 1000Base-KX transmitter AC specification.

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Electrical characteristics

Table 45. 1000Base-KX Transmitter AC Specifications

Parameter

Baud Rate

Symbols

T_BAUD

Min

Typical

Max

Units

Notes

1.25-100ppm

1.25

-

1.25+100pp Gb/s

m

-

Uncorrelated High

Probability Jitter/

Random Jitter

T_UHPJT_RJ

-

0.15

UI p-p

Deterministic Jitter

Total Jitter

T_DJ

T_TJ

-

0.10

0.25

UI p-p

-

1

Notes:

1. Total jitter is specified at a BER of 10^-12

2. For recommended operating conditions, Table 3.

.

3.11.2.2.2 1000Base-KX Receiver AC Specifications

Table below provides the 1000Base-KX receiver AC specification with parameters

guided by IEEE Std 802.3ap-2007.

Table 46. 1000Base-KX Receiver AC Specifications

Parameter

Symbols

Min

Typical

Max

Units

Notes

Receiver Baud Rate T_BAUD

1.25-100ppm

1.25

1.25+100pp Gb/s

m

-

Random Jitter

R_RJ

-

0.15

0.10

UI p-p

1

2

Sinusoidal Jitter,

maximum

R_SJ-max

Total Jitter

Notes:

R_TJ

-

See Note 3 UI p-p

2

1. Random jitter is specified at a BER of 10^-12

.

2. The receiver interference tolerance level of this parameter shall be measured as described in Annex 69A of the IEEE Std

802.3ap-2007.

3. Per IEEE 802.3ap-clause 70.

4. The AC specifications do not include Refclk jitter.

5. For recommended operating conditions, Table 3.

3.11.3 RGMII electrical specifications

This section discusses the electrical characteristics for the RGMII interface.

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Electrical characteristics

3.11.3.1 RGMII DC electrical characteristics

This table shows the DC electrical characteristics for the RGMII interface.

Table 47. RGMII DC electrical characteristics(LV_DD, L1V_DD= 2.5 V)⁴

Parameters

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 * LVDD

-

V

1

V_IL

-

0.2 * LVDD

V

Input current (LV_IN=0 V or LV_IN= LV_DD

)

I_IH

-

50

-

µA

V

2, 3

3

Output high voltage (LV_DD= min,I_OH= -1.0 mA)

Output low voltage (LV_DD= min, I_OL= 1.0 mA)

V_OH

V_OL

2.00

-

0.4

V

3

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. The symbol LV_IN, in this case, represents the LV_INand L1V_INsymbol referenced in Recommended operating conditions.

3. The symbol LV_DD, in this case, represents the LV_DDand L1V_DDsymbol referenced in Recommended operating conditions.

4. For recommended operating conditions, see Table 3.

This table provides the DC electrical characteristics for the RGMII interface at

L1V_DD/LV_DD= 1.8 V.

Table 48. RGMII DC electrical characteristics(1.8 V)⁴

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

Input low voltage

V_IH

V_IL

I_IN

0.7 * LVDD

-

V

1

-

0.2 * LVDD

V

1

Input current (LV_IN= 0 V or L1V_IN= LV_DD

)

-

50

-

µA

V

2, 3

3

Output high voltage (LV_DD= min, I_OH= -0.5 mA)

Output low voltage (LV_DD= min, I_OL= 0.5 mA)

Notes:

V_OH

V_OL

1.35

-

0.4

V

3

1. The min V_ILand max V_IHvalues are based on the min and max LV_INvalues found in Table 3.

2. The symbol LV_IN, in this case, represents the LV_INand L1V_INsymbol referenced in Recommended operating conditions.

3. The symbol LV_DD, in this case, represents the LV_DDand L1V_DDsymbol referenced in Recommended operating conditions.

4. For recommended operating conditions, see Table 3.

3.11.3.2 RGMII AC timing specifications

This table presents the RGMII AC timing specifications.

Table 49. RGMII AC timing specifications (LV_DD= 2.5 /1.8 V)⁸

Parameter/Condition

Data to clock output skew (at transmitter)

Data to clock input skew (at receiver)

Symbol¹

t_{SKRGT_TX}

t_{SKRGT_RX}

Min

-620

2.0

Typ

Max

Unit

Notes

0

-

520

3.0

ps

ns

7

2

Table continues on the next page...

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Electrical characteristics

Table 49. RGMII AC timing specifications (LV_DD= 2.5 /1.8 V)⁸(continued)

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

Notes

Clock period duration

Duty cycle for 10BASE-T and 100BASE-TX

Duty cycle for Gigabit

Rise time (20ꢀ-80ꢀ)

L1/LV_DD= 2.5V

t_RGT

7.2

40

45

-

8.0

50

-

8.8

60

55

-

ns

ꢀ

ns

3

t_RGTH/t_RGT

t_RGTR

3, 4

-

5, 6

0.75

0.54

-

L1/LV_DD= 1.8V

Fall time (20ꢀ-80ꢀ)

L1/LV_DD= 2.5V

t_RGTF

-

ns

5, 6

0.75

0.54

L1/LV_DD= 1.8V

Notes:

1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII

timing. Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols

representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 2.5 ns

is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their device. If so,

additional PCB delay is probably not needed.

3. For 10 and 100 Mbps, t_RGTscales to 400 ns 40 ns and 40 ns 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as

long as the minimum duty cycle is not violated and stretching occurs for no more than three t_RGTof the lowest speed

transitioned between.

5. Applies to inputs and outputs.

6. System/board must be designed to ensure this input requirement to the chip is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

7. The frequency of ECn_RX_CLK (input) should not exceed the frequency of ECn_GTX_CLK (output) by more than 300

ppm.

8. For recommended operating conditions, see Table 3.

This figure shows the RGMII AC timing and multiplexing diagrams.

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Electrical characteristics

t

RGT

t

RGTH

GTX_CLK

(At MAC, output)

t

SKRGT_TX

TXDS[8:5][3:0]

TXD[7:4][3:0]

TXD[8:5]

TXD[7:4]

TXD[3:0]

(At MAC, output)

TXD[9]

TXERR

TXD[4]

TXEN

TX_CTL

(At MAC, output)

PHY equivalent to t

SKRGT_RX

PHY equivalent to t

SKRGT_RX

TX_CLK

(At PHY, input)

t

RGT

t

RGTH

RX_CLK

(At PHY, output)

RXD[8:5][3:0]

RXD[7:4][3:0]

RXD[8:5]

RXD[7:4]

RXD[3:0]

PHY equivalent to t

(At PHY, output)

SKRGT_TX

PHY equivalent to t

SKRGT_TX

RXD[9]

RXERR

RXD[4]

RXDV

RX_CTL

(At PHY, output)

t

SKRGT_RX

RX_CLK

(At MAC, input)

Figure 22. RGMII AC timing and multiplexing diagrams

Warning

Freescale guarantees timings generated from the MAC. Board

designers must ensure delays needed at the PHY or the MAC.

3.11.4 MII electrical specifications

This section discusses the electrical characteristics for the MII interface.

3.11.4.1 MII DC electrical characteristics

This table shows the MII DC electrical characteristics when operating from a 3.3 V

supply.

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91

Electrical characteristics

Table 50. MII DC electrical characteristics

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

0.7 * L1VDD

-

V

1

2

-

Input low voltage

V_IL

I_IH

-

0.2 * L1VDD

V

Input high current (VIN= L1V_DD

Input low current (VIN= GND)

)

-

50

µA

V

I_IL

-50

2.4

-

Output high voltage (L1V_DD= min, I_OH= -2.0 mA)

Output low voltage (L1V_DD= min, I_OL= 2.0 mA)

V_OH

V_OL

-

0.40

V

-

1. The min VILand max VIH values are based on the respective min and max L1V_INvalues found in Table 3

2. The symbol VIN, in this case, represents the L1VIN symbols referenced in Table for "Absolute Maximum Ratings"

This table shows the MII DC electrical characteristics when operating from a 2.5 V

supply.

Table 51. MII DC electrical characteristics

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 * L1VDD

-

V

1

2

-

V_IL

I_IH

-

0.2 * L1VDD

V

Input high current (VIN= L1V_DD

Input low current (VIN= GND)

)

-

50

µA

V

I_IL

-50

2.0

-

Output high voltage (L1V_DD= min, I_OH= -1.0 mA)

Output low voltage (L1V_DD= min, I_OL= 1.0 mA)

V_OH

V_OL

-

0.40

V

-

1. The min VILand max VIH values are based on the respective min and max L1V_INvalues found in Table 3

2. The symbol VIN, in this case, represents the L1VIN symbols referenced in Table for "Absolute Maximum Ratings"

3.11.4.2 MII AC timing specifications

This section describes the MII transmit and receive AC timing specifications.

Table 52. MII transmit AC timing specifications

Parameter

TX_CLK clock period 10 Mbps

Symbol

t_MTX

Min

Typ

Max

Unit

-

400

-

ns

ꢀ

TX_CLK clock period 100 Mbps

TX_CLK duty cycle

40

-

tMTXH/tMTX 35

65

25

4.0

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

TX_CLK data clock rise (20ꢀ-80ꢀ)

TX_CLK data clock fall (80ꢀ-20ꢀ)

t_MTKHDX

t_MTXR

0

-

ns

1.0

-

t_MTXF

-

This figure shows the MII transmit AC timing diagram.

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Freescale Semiconductor, Inc.

Electrical characteristics

t_MTX

t_MTXR

TX_CLK

t_MTXH

t_MTXF

TXD[3:0]

TX_EN

TX_ER

t_MTKHDX

Figure 23. MII transmit AC timing diagram

This table provides the MII receive AC timing specifications.

Table 53. MII receive AC timing specifications

Parameter

RX_CLK clock period 10 Mbps

Symbol

t_MRX

Min

Typ

Max

Unit

-

400

-

ns

ꢀ

RX_CLK clock period 100 Mbps

t_MRX

-

40

-

RX_CLK duty cycle

t_MRXH/t_MRX

t_MRDVKH

t_MRDXKH

t_MRXR

35

65

-

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise (20ꢀ-80ꢀ)

10.0

1.0

-

ns

-

4.0

RX_CLK clock fall time (80ꢀ-20ꢀ)

t_MRXF

1.0

-

1.The frequency of RX_CLK (input) should not exceed the frequency of TX_CLK (input) by more than 300 ppm.

2.For recommended operating conditions, see Table 3

This figure provides the AC test load for the Ethernet controller.

Ʊ

/2

DD

LV

Output

Z = 50

Ʊ

0

R

= 50

L

Figure 24. Ethernet controller AC test load

This figure shows the MII receive AC timing diagram.

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Freescale Semiconductor, Inc.

93

Electrical characteristics

t_MRX

t_MRXR

RX_CLK

t_MRXF

Valid Data

t_MRXH

RXD[3:0]

RX_DV

RX_ER

t_MRDVKH

t_MRDXKL

Figure 25. MII receive AC timing diagram

3.11.5 Ethernet management interface (EMI)

This section discusses the electrical characteristics for the EMI1 interface.

The EMI1 interface timing is compatible with IEEE Std 802.3^™clause 22.

3.11.5.1 Ethernet management interface 1 DC electrical characteristics

The DC electrical characteristics for EMI1_MDIO and EMI1_MDC are provided in this

section. The pins are available on LV_DDand L1V_DD. Refer to Table 3 for operating

voltages.

Table 54. Ethernet management interface 1 DC electrical characteristics

(L1V_DD= 3.3 V) ³

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

Input low voltage

V_IH

V_IL

I_IN

0.7 * L1VDD

-

V

1

2

-

0.2 * L1VDD

V

Input current (LV_IN= 0 V or LV_IN= LV_DD

)

-

50

-

µA

V

Output high voltage (L1V_DD= min, I_OH= -2 mA)

Output low voltage (L1V_DD= min, I_OL= 2 mA)

Notes:

V_OH

V_OL

2.4

-

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max L1V_INvalues found in Table 3.

2. The symbol LV_IN, in this case, represents the L1V_INsymbol referenced in Recommended operating conditions

3. For recommended operating conditions, see Table 3

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Electrical characteristics

Table 55. Ethernet management interface 1 DC electrical characteristics

(LV_DD= 2.5 V)^{3, 4}

Parameters

Symbol

V_IH

Min

Max

Unit

Notes

1, 4

Input high voltage

Input low voltage

0.7 * LVDD

-

V

V_IL

I_IH

-

0.2 * LVDD

V

1, 4

Input high current (V_IN= LV_DD

)

-

50

µA

V

2, 4

Input low current (V_IN= GND)

I_IL

-50

2.00

-

Output high voltage (LV_DD= min, I_OH= -1.0 mA)

Output low voltage (LV_DD= min, I_OL= 1.0 mA)

Notes:

V_OH

V_OL

-

0.40

V

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_IN/L1V_INvalues found in Table 3.

2. The symbol VIN, in this case, represents the LV_IN/L1V_INsymbols referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

4. The symbol LV_DD, in this case, represents the LV_DD/L1V_DDsymbols referenced in Recommended operating conditions.

Table 56. Ethernet management interface 1 DC electrical characteristics(1.8

V)³

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

Input low voltage

V_IH

V_IL

0.7 * LVDD

-

V

1, 4

0.2 *

LVDD

Input current (LV_IN= 0 V or LV_IN= LV_DD

)

I_IN

-

50

-

µA

V

2, 4

4

Output high voltage (LV_DD= min, I_OH= -0.5 mA)

Output low voltage (LV_DD= min, I_OL= 0.5 mA)

Notes:

V_OH

V_OL

1.35

-

0.4

V

4

1. The min V_ILand max V_IHvalues are based on the min and max LV_IN/L1V_INrespective values found in Table 3.

2. The symbol LV_INrepresents the LV_IN/L1V_INsymbols referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

4. The symbol LV_DD, in this case, represents the LV_DDand L1V_DDsymbols referenced in Recommended operating

conditions.

3.11.5.2 Ethernet management interface 1 AC electrical specifications

This table provides the Ethernet management interface 1 AC timing specifications.

Table 57. Ethernet management interface 1 AC timing specifications⁵

Parameter/Condition

MDC frequency

Symbol¹

f_MDC

t_MDCH

Min

Typ

Max

Unit

MHz

ns

Notes

-

2.5

-

2

-

MDC clock pulse width high

160

Table continues on the next page...

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Electrical characteristics

Table 57. Ethernet management interface 1 AC timing specifications⁵(continued)

Parameter/Condition

MDC to MDIO delay

Symbol¹

t_MDKHDX

t_MDDVKH

t_MDDXKH

Min

Typ

Max

Unit

Notes

3, 4

(5 x t_{enet_clk}) - 3

-

(5 x t_{enet_clk}) + 3

ns

MDIO to MDC setup time

MDIO to MDC hold time

Notes:

8

0

-

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MDKHDXsymbolizes management

data timing (MD) for the time t_MDCfrom clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.

Also, t_MDDVKHsymbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state

(V) relative to the t_MDCclock reference (K) going to the high (H) state or setup time.

2. This parameter is dependent on the Ethernet clock frequency (MDIO_CFG [MDIO_CLK_DIV] field determines the clock

frequency of the MgmtClk Clock EC_MDC).

3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to 5 Ethernet clock periods 3 ns. For

example, with an Ethernet clock of 400 MHz, the min/max delay is 12.5 ns 3 ns.

4. t_{enet_clk}is the Ethernet clock period (Frame Manager clock period x 2).

5. For recommended operating conditions, see Table 3.

3.11.6 IEEE 1588 electrical specifications

3.11.6.1 IEEE 1588 DC electrical characteristics

This table shows IEEE 1588 DC electrical characteristics when operating at LV_DD= 3.3

V supply.

Table 58. IEEE 1588 DC electrical characteristics(LV_DD= 3.3 V)³

Parameters

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 * LVDD

-

V

1

2

-

V_IL

-

0.2 * LVDD

V

Input current (LV_IN= 0 V or LV_IN= LV_DD

)

I_IH

-

50

-

µA

V

Output high voltage (LV_DD= min, I_OH= -2.0 mA)

Output low voltage (LV_DD= min, I_OL= 2.0 mA)

V_OH

V_OL

2.4

-

0.40

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. The symbol LV_IN, in this case, represents the LV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

This table shows IEEE 1588 DC electrical characteristics when operating at LV_DD= 2.5

V supply.

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Electrical characteristics

Table 59. IEEE 1588 DC electrical characteristics(LV_DD= 2.5 V)³

Parameters

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 * LVDD

-

V

1

2

-

V_IL

-

0.2 * LVDD

V

Input current (LV_IN= 0 V or LV_IN= LV_DD

)

I_IH

-

50

-

µA

V

Output high voltage (LV_DD= min, I_OH= -1.0 mA)

Output low voltage (LV_DD= min, I_OL= 1.0 mA)

V_OH

V_OL

2.00

-

0.40

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. The symbol LV_IN, in this case, represents the LV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

This table shows IEEE 1588 DC electrical characteristics when operating at LV_DD= 1.8

V supply.

Table 60. IEEE 1588 DC electrical characteristics(LV_DD= 1.8 V)³

Parameters

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 * LVDD

-

V

1

2

-

V_IL

-

0.2 * LVDD

V

Input current (LV_IN= 0 V or LV_IN= LV_DD

)

I_IH

-

50

-

µA

V

Output high voltage (LV_DD= min, I_OH= -0.5 mA)

Output low voltage (LV_DD= min, I_OL= 0.5 mA)

V_OH

V_OL

1.35

-

0.40

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. The symbol LV_IN, in this case, represents the LV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

3.11.6.2 IEEE 1588 AC specifications

This table provides the IEEE 1588 AC timing specifications.

Table 61. IEEE 1588 AC timing specifications⁵

Parameter/Condition

TSEC_1588_CLK_IN clock period

TSEC_1588_CLK_IN duty cycle

Symbol

t_T1588CLK

t_T1588CLKH

t_T1588CLK

TSEC_1588_CLK_IN peak-to-peak jitter t_T1588CLKINJ

Min

FM_CLK/2

Typ

Max

Unit

Notes

1, 3, 6

2

-

T_{RX_CLK}x 7 ns

/

40

50

60

ꢀ

-

250

2.0

ps

ns

-

Rise time TSEC_1588_CLK_IN

(20ꢀ-80ꢀ)

t_T1588CLKINR

t_T1588CLKINF

t_T1588CLKOUT

1.0

Fall time TSEC_1588_CLK_IN

(80ꢀ-20ꢀ)

1.0

5.0

-

2.0

-

ns

-

TSEC_1588_CLK_OUT clock period

4

Table continues on the next page...

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Electrical characteristics

Table 61. IEEE 1588 AC timing specifications⁵(continued)

Parameter/Condition

Symbol

t_T1588CLKOTH

t_T1588CLKOUT

Min

Typ

Max

Unit

Notes

TSEC_1588_CLK_OUT duty cycle

/

30

50

-

70

ꢀ

-

TSEC_1588_PULSE_OUT1/2,

TSEC_1588_ALARM_OUT1/2

TSEC_1588_TRIG_IN1/2 pulse width

Notes:

t_T1588OV

0.5

3.0

ns

t_T1588TRIGH

2 x t_{T1588CLK_MAX}

-

3

1.T_{RX_CLK}is the maximum clock period of ethernet receiving clock selected by TMR_CTRL[CKSEL]. See the chip reference

manual for a description of TMR_CTRL registers.

2. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the chip reference

manual for a description of TMR_CTRL registers.

3. The maximum value of t_T1588CLKis not only defined by the value of T_{RX_CLK}, but also defined by the recovered clock. For

example, for 10/100/1000 Mbps modes, the maximum value of t_T1588CLKwill be 2800, 280, and 56 ns, respectively.

4. There are 3 input clock sources for 1588 that is, TSEC_1588_CLK_IN, RTC and MAC clock / 2. When using

TSEC_1588_CLK_IN, the minimum clock period is 2 x t_T1588CLK

5. For recommended operating conditions, see Table 3.

6. FM_CLK = platform clock

.

This figure shows the data and command output AC timing diagram.

t_T1588CLKOUT

t_T1588CLKOUTH

TSEC_1588_CLK_OUT

t_T1588OV

TSEC_1588_PULSE_OUT1/2

TSEC_1588_ALARM_OUT1/2

Note: The output delay is counted starting at the rising edge if t_T1588CLKOUTis non-inverting.

Otherwise, it is counted starting at the falling edge.

Figure 26. IEEE 1588 output AC timing

This figure shows the data and command input AC timing diagram.

t_T1588CLK

TSEC_1588_CLK_IN

t_T1588CLKH

TSEC_1588_TRIG_IN1/2

t_T1588TRIGH

Figure 27. IEEE 1588 input AC timing

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Electrical characteristics

3.12 QUICC Engine Specifications

3.12.1 HDLC, Transparent, and Synchronous UART interfaces

This section describes the DC and AC electrical specifications for the high level data link

control HDLC, transparent and synchronous UART.

3.12.1.1 HDLC, Transparent and Synchronous UART DC electrical

characteristics

This table provides the DC electrical characteristics for the HDLC, Transparent and

Synchronous UART protocols.

Table 62. HDLC, Transparent and Synchronous UART DC electrical

characteristics (DVDD=3.3V)³

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 * DVDD

-

V

1

2

-

V_IL

-

0.2 * DVDD

V

Input current (V_IN= 0 V or V_IN= DV_DD

)

I_IN

-

50

-

μA

V

Output high voltage (DV_DD= min, I_OH= -2 mA)

Output low voltage (DV_DD= min, I_OH= 2 mA)

V_OH

V_OL

2.4

-

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max DV_INvalues found in Table 3

2. The symbol V_IN, in this case, represents the input voltage of the supply. It is referenced in Recommended operating

conditions.

3. For recommended operating conditions, see Table 3.

This table provides the DC electrical characteristics for the HDLC, Transparent and

Synchronous UART protocols.

Table 63. HDLC, Transparent and Synchronous UART DC electrical

characteristics (DVDD=2.5V)³

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 * DVDD

-

V

1

2

-

V_IL

-

0.2 * DVDD

V

Input current (V_IN= 0 V or V_IN= DV_DD

)

I_IN

-

50

-

μA

V

Output high voltage (DV_DD= min, I_OH= -1 mA)

Output low voltage (DV_DD= min, I_OH= 1 mA)

V_OH

V_OL

2.0

-

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max DV_INvalues found in Table 3

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Electrical characteristics

Table 63. HDLC, Transparent and Synchronous UART DC electrical

characteristics (DVDD=2.5V)³

Parameter

Symbol

Min

Max

Unit

Notes

2. The symbol V_IN, in this case, represents the input voltage of the supply. It is referenced in Recommended operating

conditions.

3. For recommended operating conditions, see Table 3.

3.12.1.2 HDLC, Transparent and Synchronous UART AC timing

specifications

This table provides the input and output AC timing specifications for HDLC, and

Transparent and Synchronous UART protocols.

Table 64. HDLC, Transparent AC timing specifications

Parameter

Outputs-Internal clock delay

Symbol

t_HIKHOV

Min

Max

Unit

Notes

0

5.5

8.5

5.5

8.2

-

ns

1

-

Outputs-External clock delay

t_HEKHOV

t_HIKHOX

t_HEKHOX

t_HIIVKH

1

Outputs-Internal clock High Impedance

Outputs-External clock High Impedance

Inputs-Internal clock input setup time

Inputs-External clock input setup time

Inputs-Internal clock input Hold time

Inputs-External clock input hold time

Notes:

0

1

8.0

4

t_HEIVKH

t_HIIXKH

-

0

-

t_HEIXKH

1

-

1. Output specifications are measured from the 50ꢀ level of the rising edge of CLKIN to the 50ꢀ level of the signal. Timings

are measured at the pin.

2. For recommended operating conditions, see Table 3.

3. The Maximum frequency of operation is 50MHz

This table provides the input and output AC timing specifications for the synchronous

UART protocols.

Table 65. Synchronous UART AC timing specifications

Parameter

Outputs-Internal clock delay

Symbol

t_HIKHOV

Min

Max

Unit

Notes

0

1

0

1

11

14

11

14

-

ns

1

-

Outputs-External clock delay

t_HEKHOV

t_HIKHOX

t_HEKHOX

t_HIIVKH

Outputs-Internal clock High Impedance

Outputs-External clock High Impedance

Inputs-Internal clock input setup time

Inputs-External clock input setup time

10

8

t_HEIVKH

-

Table continues on the next page...

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Electrical characteristics

Table 65. Synchronous UART AC timing specifications

(continued)

Parameter

Inputs-Internal clock input Hold time

Inputs-External clock input hold time

Notes:

Symbol

t_HIIXKH

t_HEIXKH

Min

Max

Unit

Notes

0

1

-

ns

-

1. Output specifications are measured from the 50ꢀ level of the rising edge of CLKIN to the 50ꢀ level of the signal. Timings

are measured at the pin.

2. For recommended operating conditions, see Table 3.

This figure provides the AC test load.

Ʊ

/2

DV

DD

Output

Z = 50

Ʊ

0

R

= 50

L

Figure 28. AC test load

These figures represent the AC timing from Table 64 and Table 65. Note that although

the specifications generally reference the rising edge of the clock, these AC timing

diagrams also apply when the falling edge is the active edge. This figure shows the

timing with external clock.

Serial CLK (input)

t

HEIXKH

t

HEIVKH

Input Signals:

(See Note)

t

HEKHOV

Output Signals:

(See Note)

t

HEKHOX

Note: The clock edge is selectable

Figure 29. AC timing (external clock) diagram

This figure shows the timing with internal clock.

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101

Electrical characteristics

Serial CLK (output)

t

HIIXKH

t

HIIVKH

Input Signals:

(See Note)

t

HIKHOV

Output Signals:

(See Note)

t

HIKHOX

Note: The clock edge is selectable

Figure 30. AC timing (internal clock) diagram

3.12.2 TDM/SI

This section describes the DC and AC electrical specifications for the time-division-

multiplexed and serial interface (TDM/SI).

3.12.2.1 TDM/SI DC electrical characteristics

This table provides the TDM/SI DC electrical characteristics.

Table 66. TDM/SI DC electrical characteristics (DVDD=3.3V)³

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 * DVDD

-

V

1

2

-

V_IL

-

0.2 * DVDD

V

Input current (V_IN= 0 V or V_IN= DV_DD

)

I_IN

-

50

-

μA

V

Output high voltage (DV_DD= min, I_OH= -2 mA)

Output low voltage (DV_DD= min, I_OH= 2 mA)

V_OH

V_OL

2.4

-

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max DV_INvalues found in Table 3

2. The symbol V_IN, in this case, represents the input voltage of the supply. It is referenced in Recommended operating

conditions.

3. For recommended operating conditions, see Table 3.

Table 67. TDM/SI DC electrical characteristics (DVDD=2.5V)³

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 * DVDD

-

V

1

2

V_IL

I_IN

-

0.2 * DVDD

50

V

Input current (V_IN= 0 V or V_IN= DV_DD

)

μA

Table continues on the next page...

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Electrical characteristics

Table 67. TDM/SI DC electrical characteristics (DVDD=2.5V)³(continued)

Parameter

Symbol

V_OH

V_OL

Min

Max

Unit

Notes

Output high voltage (DV_DD= min, I_OH= -1 mA)

Output low voltage (DV_DD= min, I_OH= 1 mA)

2.0

-

V

-

0.4

1. The min V_ILand max V_IHvalues are based on the respective min and max DV_INvalues found in Table 3

2. The symbol V_IN, in this case, represents the input voltage of the supply. It is referenced in Recommended operating

conditions.

3. For recommended operating conditions, see Table 3.

3.12.2.2 TDM/SI AC timing specifications

This table provides the TDM/SI input and output AC timing specifications.

Table 68. TDM/SI AC timing specifications ¹

Parameter

TDM/SI outputs-External clock delay

TDM/SI outputs-External clock High Impedance

TDM/SI inputs-External clock input setup time

TDM/SI inputs-External clock input hold time

Notes:

Symbol ¹

Min

Max

Unit

t_SEKHOV

2

5

2

11

10

-

ns

t_SEKHOX

t_SEIVKH

t_SEIXKH

-

1. Output specifications are measured from the 50ꢀ level of the rising edge of CLKIN to the 50ꢀ level of the signal. Timings

are measured at the pin.

2. For recommended operating conditions, see Table 3.

NOTE

The rise/fall time on QUICC Engine block input pins should

not exceed 5 ns. This should be enforced especially on clock

signals. Rise time refers to signal transitions from 10% to 90%

of DV_DD; fall time refers to transitions from 90% to 10% of

DV_DD

This figure provides the AC test load for the TDM/SI.

Ʊ

/2

DV

DD

Output

Z = 50

Ʊ

0

R

= 50

L

Figure 31. TDM/SI AC test load

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Electrical characteristics

This figure represents the AC timing from Table 68. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply

when the falling edge is the active edge. This figure shows the TDM/SI timing with

external clock.

TDM/SICLK (input)

t

SEIXKH

t

SEIVKH

Input Signals:

TDM/SI

(See Note)

t

SEKHOV

Output Signals:

TDM/SI

(See Note)

t

SEKHOX

Note: The clock edge is selectable on TDM/SI

Figure 32. TDM/SI AC timing (external clock) diagram

3.13 USB interface

This section provides the AC and DC electrical specifications for the USB interface.

3.13.1 USB DC electrical characteristics

This table provides the DC electrical characteristics for the USB interface at USB_HV_DD

= 3.3 V.

Table 69. USB DC electrical characteristics (USB_HV_DD= 3.3 V) ³

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

Input low voltage

V_IH

V_IL

I_IN

2.0

-

V

1

2

-

0.8

Input current (USB_HV_IN= 0 V or USB_HV_IN=

USB_HV_DD

50

µA

)

Output high voltage (USB_HV_DD= min, I_OH= -2 mA)

Output low voltage (USB_HV_DD= min, I_OL= 2 mA)

Notes:

V_OH

V_OL

2.8

-

V

-

0.3

1. The min V_ILand max V_IHvalues are based on the respective min and max USB_HV_INvalues found in Table 3.

2. The symbol USB_HV_IN, in this case, represents the USB_HV_INsymbol referenced in Recommended operating conditions

3. For recommended operating conditions, see Table 3

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Electrical characteristics

This table provides the DC electrical characteristics for the USBCLK at O1V_DD= 1.8 V.

Table 70. USBCLK DC electrical characteristics (1.8 V)³

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage V_IH

1.25

-

V

1

2

Input low voltage

Input current (V_IN= I_IN

0 V or V_IN

O1V_DD

Notes:

V_IL

-

0.6

V

50

µA

=

)

1. The min V_ILand max V_IHvalues are based on the respective min and max O1V_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the O1V_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

3.13.2 USB AC timing specifications

This section describes the AC timing specifications for the on-chip USB PHY. See

Chapter 7 in the Universal Serial Bus Revision 2.0 Specification for more information.

This table provides the USB clock input (USBCLK) AC timing specifications.

Table 71. USBCLK AC timing specifications¹

Parameter

Frequency range

Rise/Fall time

Condition

Symbol

f_{USB_CLK_IN}

t_USRF

Min Typ Max

Unit

MHz

Notes

-

24

-

Measured between 10ꢀ and 90ꢀ

-

6

ns

ꢀ

2

-

Clock frequency

tolerance

t_{CLK_TOL}

-0.005 0

0.005

Reference clock duty

cycle

Measured at rising edge and/or failing edge t_{CLK_DUTY}

at O1V_DD/2

40

-

50

60

5

ꢀ

-

Total input jitter/time

interval error

RMS value measured with a second-order, t_{CLK_PJ}

band-pass filter of 500 kHz to 4 MHz

bandwidth at 10^-12BER

-

ps

Notes:

1. For recommended operating conditions, see Table 3

2. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

3.14 Integrated flash controller

This section describes the DC and AC electrical specifications for the integrated flash

controller.

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Electrical characteristics

3.14.1 Integrated flash controller DC electrical characteristics

This table provides the DC electrical characteristics for the integrated flash controller

when operating at OV_DD= 1.8 V.

Table 72. Integrated flash controller DC electrical characteristics (1.8 V)³

Parameter

Input high voltage

Symbol

Min

Max

Unit

Note

V_IH

V_IL

I_IN

1.2

-

V

1

2

Input low voltage

Input current

-

0.6

V

50

µA

(V_IN= 0 V or V_IN= OV_DD

Output high voltage

)

V_OH

1.35

-

V

-

(OV_DD= min, I_OH= -0.5 mA)

Output low voltage

V_OL

0.32

(OV_DD= min, I_OL= 0.5 mA)

1. The min V_ILand max V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the OV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

3.14.2 Integrated flash controller AC timing

This section describes the AC timing specifications for the integrated flash controller.

3.14.2.1 Test condition

This figure provides the AC test load for the integrated flash controller.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 33. Integrated flash controller AC test load

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Electrical characteristics

3.14.2.2 Integrated flash controller Input AC timing specifications

This table describes the input AC timing specifications of the IFC-GPCM and IFC-

GASIC interface.

Table 73. Integrated Flash Controller input timing specifications for GPCM

and GASIC mode (OV_DD= 1.8 V)

Parameter

Symbol

t_IBIVKH1

t_IBIXKH1

Min

Max

Unit

Notes

Input setup

Input hold

4

1

-

ns

-

This figure shows the input AC timing diagram for IFC-GPCM, IFC-GASIC interface.

IFC_CLK[0]

t_IBIXKH1

t_{IBIVKH 1}

Input Signals

(IFC_AD, IFCTA_B)

Figure 34. IFC-GPCM, IFC-GASIC input AC timings

This table describes the input timing specifications of the IFC-NOR interface.

Table 74. Integrated Flash Controller Input timing specifications for NOR

mode (OV_DD= 1.8 V)

Parameter

Symbol

t_IBIVKH2

Min

Max

Unit

Notes

Input setup

Input hold

(2 x t_{IP_CLK}) + -

2

ns

1

t_IBIXKH2

1 x t_{IP_CLK}

-

1. t_{IP_CLK}is the period of ip clock (not the IFC_CLK) on which IFC is running.

2. For recommended operating conditions, see Table 3

This figure shows the AC input timing diagram for input signals of IFC-NOR interface.

Here TRAD is a programmable delay parameter, refer to IFC section of T1040 QorIQ

Integrated Processor Reference Manual for more information.

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Electrical characteristics

(TRAD+1) x tIP_CLK

OE_B

t_IBIXKH2

t_IBIVKH2

AD (Data Phase, Read)

Figure 35. IFC-NOR Interface input AC timings

IP_CLK is the internal clock on which IFC is running. It is not available on interface

pins.

This table describes the input timing specifications of the IFC-NAND interface.

Table 75. Integrated Flash Controller input timing specifications for NAND

mode (OV_DD= 1.8 V)

Parameter

Symbol

t_IBIVKH3

Min

Max

Unit

Notes

Input setup

Input hold

(2 x t_{IP_CLK}

+2

)

-

ns

1

t_IBIXKH3

t_IBCH

(1 x t_{IP_CLK}

2

-

1

IFC_RB_B pulse width

t_{IP_CLK}

1. t_{IP_CLK}is the period of ip clock on which IFC is running.

2. For recommended operating conditions, see Table 3

This figure shows the AC input timing diagram for input signals of IFC-NAND interface.

Here TRAD is a programmable delay parameter, refer to IFC section of T1040 QorIQ

Integrated Processor Reference Manual for more information.

RE_B

(TRAD +1 ) x tIP_CLK

t_IBIXKH3

t_IBIVKH3

AD [0:15]

Figure 36. IFC-NAND Interface input AC timings

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Electrical characteristics

t_{IP_CLK}is the period of ip clock (not the IFC_CLK) on which IFC is running.

3.14.2.3 Integrated flash controller output AC timing specifications

This table describes the output AC timing specifications of IFC-GPCM and IFC-GASIC

interface .

Table 76. Integrated Flash Controller IFC-GPCM and IFC-GASIC interface

output timing specifications (OV_DD= 1.8 V)

Parameter

IFC_CLK cycle time

Symbol

Min

Max

Unit

Notes

t_IBK

10

45

-

ns

ꢀ

-

IFC_CLK duty cycle

Output delay

t_IBKH/ t_IBK

t_IBKLOV1

t_IBKLOX

55

1.5

-2

-

ns

ps

-

Output hold

-

1

-

IFC_CLK[0] to IFC_CLK[m] skew

t_IBKSKEW

0

75

1. Output hold is negative. This means that output transition happens earlier than the falling edge of IFC_CLK.

2. For recommended operating conditions, see Table 3

This figure shows the output AC timing diagram for IFC-GPCM, IFC-GASIC interface.

IFC_CLK_0

t_IBKLOV1

t_IBKLOX

Output Signals

(IFC_AD, IFC_A, IFC_CS,

GPWE, BCTL, GPOE_B,

RW_L_B)

Figure 37. IFC-GPCM, IFC-GASIC Signals

Table 77. Integrated Flash Controller IFC-NOR Interface output timing

specifications (OV_DD= 1.8 V)

Parameter

Symbol

t_IBKLOV2

Min

Max

Unit

Notes

Output delay

-

1.5

ns

1

1) This effectively means that a signal change may appear anywhere within t_IBKLOV2(max) duration, from the point where it's

expected to change.

For recommended operating conditions, see Table 3

This figure shows the AC timing diagram for output signals of IFC-NOR interface. The

timing specs have been illustrated here by taking timings between two signals, CS_B and

OE_B as an example. OE_B is suppose to change TACO (a programmable delay, refer to

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Electrical characteristics

IFC section of T1040 QorIQ Integrated Processor Reference Manual for more

information) time after CS_B. Because of skew between the signals, OE_B may change

anywhere within time window t_IBKLOV2(min) and t_IBKLOV2(max). This concept applies

to other output signals of IFC-NOR interface as well. The diagram is an example to show

the skew between any two chronological toggling signals as per the protocol. Here is the

list of IFC-NOR output signals NRALE, NRAVD_B, NRWE_B, NROE_B, CS_B,

AD(Address phase).

CS_B

TACO

t_IBKLOV2

OE_B

Figure 38. IFC-NOR Interface Output AC Timings

Table 78. Integrated Flash Controller IFC-NAND Interface output timing

specifications (OV_DD= 1.8 V)

Parameter

Symbol

t_IBKLOV3

Min

Max

Unit

Notes

Output delay

-

1.5

ns

1

1. This effectively means that a signal change may appear anywhere within t_IBKLOV3(min) to t_IBKLOV3(max) duration, from

the point where it's expected to change.

2. For recommended operating conditions, see Table 3

This figure shows the AC timing diagram for output signals of IFC-NAND interface.The

timing specs have been illustrated here by taking timings between two signals, CS_B and

CLE as an example. CLE is suppose to change TCCST (a programmable delay, refer to

IFC section of T1040 QorIQ Integrated Processor Reference Manual for more

information) time after CS_B. Because of skew between the signals CLE may change

anywhere within time window t_IBKLOV3(min) and t_IBKLOV3(max). This concept applies

to other output signals of IFC-NAND interface as well. The diagram is an example to

show the skew between any two chronological toggling signals as per the protocol. Here

is the list of output signals NDWE_B, NDRE_B, NDALE, WP_B, NDCLE, CS_B, AD.

CS_B

TCCST

t_IBKLOV3

CLE

Figure 39. IFC-NAND Interface Output AC Timings

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Electrical characteristics

3.14.2.4 Integrated flash controller NAND Source Synchronous Interface

AC timing specifications

This table describes the AC timing specifications of IFC-NAND Source Synchronous

interface.

Table 79. Integrated Flash Controller IFC-NAND Source Synchronous

Interface AC Timing Specifications (OV_DD= 1.8 V)

Parameter

Command/address DQ hold time

CLE and ALE hold time

CLE and ALE setup time

Command/address DQ setup time

CE# hold time

Symbol

t_CAH

I/O

Min

Max

Unit

Notes

O

2.5

1

-

ns

-

1

t_CALH

t_CALS

t_CAS

t_CH

Data DQ setup time

t_DS

Data DQ hold time

t_DH

1

Average clock cycle time

t_CK(avg) or

t_CK

10

Absolute clock period

Clock cycle high

t_CK(abs)

t_CKH(abs)

t_CKL(abs)

t_DQSH

O

I

9.5

10.5

0.56

0.57

1

ns

-

0.44

0.43

-

t_CK

ns

2

-

Clock cycle low

DQS output high pulse width

DQS output low pulse width

3

-

t_DQSL

DQS-DQ skew, DQS to last DQ valid, per

access

t_DQSQ

Data output to first DQS latching transition

t_DQSS

O

0.75+150(ps 1.15

)

t_CK

DQS cycle time

t_DSC

t_DSH

O

I

10

-

ns

t_CK

ns

-

DQS falling edge to CLK rising – hold time

0.228

0.3

-

DQS falling edge to CLK rising – setup time t_DSS

-

Input data valid window

Half-clock period

t_DVW

2.1

-

t_HP

O

4.4

-

The deviation of a given t_CK(abs) from

t_CK(avg)

t_JIT(per)

-0.5

0.5

DQ-DQS hold, DQS to first DQ to go non-

valid, per access

t_QH

I

3.1

-

ns

-

1. t_CK(avg) is the average clock period over any consecutive 200 cycle window.

2. t_CKH(abs) and t_CKL(abs) include static off set and duty cycle jitter.

3. t_DQSLand t_DQSHare relative to t_CKwhen CLK is running . If CLK is stopped during data input, then t_DQSLand t_DQSHare

relative to t_DSC

.

4. For recommended operating conditions, see Table 3

These figures show the AC timing diagram for IFC-NAND source synchronous interface.

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Electrical characteristics

tCH

CE_B

tCALS

CLE

ALE

CLK

tCALS tCALH

tCKL tCKH

tCK

tCALS

tCALH

W/R_B

DQS

tDQSHZ

tCAS

Command

tCAH

DQ[7:0]

Figure 40. Command Cycle

tCH

CE#

tCALS

CLE

ALE

CLK

tCALH

tCALS

tCKL tCKH

tCK

tCALS

tCALH

tCAH

W/R#

DQS

tDQSHZ

tCAS

DQ[7:0]

Address

Figure 41. Address Cycle

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Electrical characteristics

tCH

CE#

CLE

ALE

CLK

tCALS

tCAD

tCALH

tCKH

tCKL

tCK

W/R#

DQS

tDSH tDSS tDSH

tDQSHtDQSL tDQSH

tDSH tDSS tDSH tDSS

tDQSL tDQSH

tDQSS

DQ[7:0]

D

N-2

3

N-1

0

1

2

N

tDS

tDH

Figure 42. Write Cycle

tCH

CE_B

CLE

ALE

CLK

tCALH

tCALS

tCALH

tHP

tCKH tCKL

tCK

tHP

tCALS

tDSC

W/R_B

tCALS

tDQSHZ

tDQSD

DQS

tDVW

tDVW tDVW tDVW

DQ[7:0]

D

0

D

2

D

0

D

0

1

3

0

tDQSQ

tQH

Device Driving

tQH tQH

Don't Care

Data Transitioning

Figure 43. Read Cycle

3.15 Enhanced secure digital host controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC interface.

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113

Electrical characteristics

3.15.1 eSDHC DC electrical characteristics

This table provides the DC electrical characteristics for the eSDHC interface.

Table 80. eSDHC interface DC electrical characteristics (dual-voltage

cards)³

Characteristic

Input high voltage

Input low voltage

Input/Output leakage current I_IN/I_OZ

Symbol

V_IH

V_IL

Condition

Min

0.7 x V_DD

-

Max

Unit

Notes

-

V

1

-

0.2 x V_DD

-50

50

-

μA

V

Output high voltage

V_OH

I_OH= -100 μA at V_DD

min

V_DD- 0.2 V

-

Output low voltage

V_OL

I_OL= 100 μA at V_DD

min

-

0.2

V

-

Output high voltage

Output low voltage

V_OH

V_OL

I_OH= -100 μA

I_OL= 2 mA

V_DD- 0.2

-

V

2

0.3

1. The min V_ILand V_IHvalues are based on the respective min and max V_INvalues found in Table 3.

2. Open-drain mode is for MMC cards only.

3. For recommended operating conditions, see Table 3.

4. SDHC interface is powered by EV_DDand CV_DD. The V_DDand V_INin the table above should be replaced by the respective

IO power supply.

3.15.2 eSDHC AC timing specifications

This table provides the eSDHC AC timing specifications as defined in Figure 44 and

Figure 45 (EV_DD/CV_DD= 1.8V or 3.3V).

Table 81. eSDHC AC timing specifications (High Speed/Full Speed)⁶

Parameter

Symbol¹

Min

Max

25/50

Unit

MHz

Notes

2, 4

SDHC_CLK clock frequency

SD/SDIO (full-speed/high-speed f_SCK

0

mode)

MMC full-speed/high-speed mode

20/52

—

SDHC_CLK clock low time (full-speed/high-speed mode)

SDHC_CLK clock high time (full-speed/high-speed mode)

SDHC_CLK clock rise and fall times

t_SCKL

10/7

—

ns

4

t_SCKH

—

t_SCKR/

t_SCKF

3

Input setup times: SDHC_CMD, SDHC_DATx to SDHC_CLK

Input hold times: SDHC_CMD, SDHC_DATx to SDHC_CLK

Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid

Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid

Notes:

t_NIIVKH

t_NIIXKH

t_NIKHOX

t_NIKHOV

2.5

-3

—

3

ns

3, 4, 5

4, 5

—

4, 5

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Electrical characteristics

Table 81. eSDHC AC timing specifications (High Speed/Full Speed)⁶

Parameter

Symbol¹

Min

Max

Unit

Notes

1. The symbols used for timing specifications herein follow the pattern of t_{(first three letters of functional block)(signal)(state) (reference)(state)}

for inputs and _{(first three letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_FHSKHOVsymbolizes eSDHC

high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching

the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing

the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F

(fall).

2. In full-speed mode, the clock frequency value can be 0-25 MHz for an SD/SDIO card and 0-20 MHz for an MMC card. In

high-speed mode, the clock frequency value can be 0-50 MHz for an SD/SDIO card and 0-52 MHz for an MMC card.

3. To satisfy setup timing, one-way board-routing delay between Host and Card, on SDHC_CLK, SDHC_CMD, and

SDHC_DATx should not exceed 1 ns for any high speed MMC card. For any high speed or default speed mode SD card, the

one way board routing delay between Host and Card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx should not exceed

1.5ns.

4. C_CARD≤ 10 pF, (1 card), and C_L= C_BUS+ C_HOST+ C_CARD≤ 40 pF.

5. The parameter values apply to both full-speed and high-speed modes.

6. For recommended operating conditions, see Table 3.

This figure provides the eSDHC clock input timing diagram.

eSDHC

external clock

VM

t_SCKL

t_SCKH

t_SCK

t_SCKR

t_SCKF

VM = Midpoint voltage (OV_DD/2)

Figure 44. eSDHC clock input timing diagram

This figure provides the data and command input/output timing diagram.

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Electrical characteristics

VM

SDHC_CLK

external clock

tNIIVKH

tNIIXKH

SDHC_DAT/CMD inputs

SDHC_DAT/CMD outputs

tNIKHOX

t^NIKHOV

VM = Midpoint voltage (OV_DD/2)

Figure 45. eSDHC data and command input/output timing diagram referenced to clock

This table provides the eSDHC AC timing specifications for SDR50 mode (EV_DD/CV_DD

= 1.8V).

Table 82. eSDHC AC timing (SDR50)²

Parameter

Symbol

f_SCK

Min

Max

100

Unit

MHz

Notes

SDHC_CLK clock frequency:

SDHC_CLK duty cycle

47

-

53

2

ꢀ

SDHC_CLK clock rise and fall times

t_SCKR/

t_SCKF

—

ns

1

Skew between SDHC_CLK_SYNC_OUT and SDHC_CLK

-0.1

2.1

0.1

-

ns

—

Input setup times: SDHC_CMD, SDHC_DATx to

SDHC_CLK_SYNC_IN

t_NIIVKH

Input hold times: SDHC_CMD, SDHC_DATx to

SDHC_CLK_SYNC_IN

t_NIIXKH

0.9

2.4

-

ns

Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid,

SDHC_DATx_DIR, SDHC_CMD_DIR

t_NIKHOX

-

Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid, t_NIKHOV

SDHC_DATx_DIR, SDHC_CMD_DIR

6.3

Notes:

1. C_CARD≤ 10 pF, (1 card), and C_L= C_BUS+ C_HOST+ C_CARD≤ 30 pF.

2. For recommended operating conditions, see Table 3.

This figure provides the eSDHC clock input timing diagram for SDR50 mode.

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Electrical characteristics

VM

eSDHC

external clock

t_SCK

t_SCKR

t_SCKF

VM = Midpoint voltage (EV_DD/2)

Figure 46. eSDHC SDR50 mode clock input timing diagram

This figure shows the eSDHC input AC timing diagram for SDR50 mode.

T

CLK

SDHC_CLK_SYNC_IN

T

NIIXKH

NIIVKH

SDHC_CMD/

SDHC_DAT

input

Figure 47. eSDHC SDR50 mode input AC timing diagram

This figure shows the eSDHC output AC timing diagram for SDR50 mode.

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Electrical characteristics

T

CLK

SDHC_CLK

T

NIKHOV

SDHC_CMD/SDHC_CMD_DIR

SDHC_DAT/SDHC_DATn_DIR

output

T

NIKHOX

Figure 48. eSDHC SDR50 mode output AC timing diagram

This table provides the eSDHC AC timing specifications for DDR50/eMMC DDR mode

(EV_DD/CV_DD= 1.8V).

Table 83. eSDHC AC timing (DDR50/eMMC DDR)³

Parameter

SD/SDIO DDR50 mode

eMMC DDR mode

Symbol

f_SCK

Min

Max

Units

MHz

Notes

SDHC_CLK clock frequency

SDHC_CLK duty cycle

—

50

53

0.1

4

—

47

ꢀ

—

1

Skew between SDHC_CLK_SYNC_OUT and SDHC_CLK

—

-0.1

—

ns

SDHC_CLK clock rise and fall

times

SD/SDIO DDR50 mode

eMMC DDR mode

t_SCKR

t_SCKF

t_NDIVKH

/

2

Input setup times: SDHC_DATx SD/SDIO DDR50 mode

0.5

—

ns

—

to SDHC_CLK_SYNC_IN

eMMC DDR mode

0.6

Input hold times: SDHC_DATx to SD/SDIO DDR50 mode

t_NDIXKH

0.98

—

SDHC_CLK_SYNC_IN

eMMC DDR mode

Output hold time: SDHC_CLK to SD/SDIO DDR50 mode

t_NDKHOX2.2

3.9

SDHC_DATx valid,

SDHC_DATx_DIR

eMMC DDR mode

Output delay time: SDHC_CLK to SD/SDIO DDR50 mode

t_NDKHOV

—

5.7

6.3

ns

—

SDHC_DATx valid,

eMMC DDR mode

SDHC_DATx_DIR

Input setup times: SDHC_CMD to SD/SDIO DDR50 mode

t_NIIVKH

t_NIIXKH

t_NIKHOX

3.3

2.7

0.4

2.2

4.4

—

ns

—

SDHC_CLK_SYNC_IN

eMMC DDR mode

Input hold times: SDHC_CMD to SD/SDIO DDR50 mode

SDHC_CLK_SYNC_IN

eMMC DDR mode

Output hold time: SDHC_CLK to SD/SDIO DDR50 mode

SDHC_CMD valid,

SDHC_CMD_DIR

eMMC DDR mode

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Electrical characteristics

Table 83. eSDHC AC timing (DDR50/eMMC DDR)³(continued)

Parameter

Symbol

Min

Max

12.2

14.6

Units

Notes

Output delay time: SDHC_CLK to SD/SDIO DDR50 mode

t_NIKHOV

—

ns

—

SDHC_CMD valid,

SDHC_CMD_DIR

eMMC DDR mode

Notes:

1. C_CARD≤ 10 pF, (1 card).

2. C_L= C_BUS+ C_HOST+ C_CARD≤ 20 pF for MMC. 40pF for SD.

3. For recommended operating conditions, see Table 3.

This table provides the eSDHC AC timing specifications for eMMC DDR mode

(EV_DD/CV_DD= 3.3V).

Table 84. eSDHC AC timing (eMMC DDR)³

Parameter

eMMC DDR mode

Symbol

f_SCK

Min

Max

Units

MHz

Notes

SDHC_CLK clock frequency

SDHC_CLK duty cycle

—

49

53

0.1

2

—

2

—

47

ꢀ

Skew between SDHC_CLK_SYNC_OUT and SDHC_CLK

—

-0.1

—

ns

SDHC_CLK clock rise and fall

times

eMMC DDR mode

t_SCKR

t_SCKF

t_NDIVKH

/

Input setup times: SDHC_DATx eMMC DDR mode

to SDHC_CLK_SYNC_IN

1.33

1.32

—

ns

—

4

Input hold times: SDHC_DATx to eMMC DDR mode

SDHC_CLK_SYNC_IN

t_NDIXKH

Output hold time: SDHC_CLK to eMMC DDR mode

SDHC_DATx valid,

t_NDKHOX3.9

—

SDHC_DATx_DIR

Output delay time: SDHC_CLK to eMMC DDR mode

SDHC_DATx valid,

t_NDKHOV

—

6.3

ns

—

SDHC_DATx_DIR

Input setup times: SDHC_CMD to eMMC DDR mode

SDHC_CLK_SYNC_IN

t_NIIVKH

t_NIIXKH

t_NIKHOX

2.7

0.4

4.4

—

ns

—

Input hold times: SDHC_CMD to eMMC DDR mode

SDHC_CLK_SYNC_IN

Output hold time: SDHC_CLK to eMMC DDR mode

SDHC_CMD valid,

SDHC_CMD_DIR

Output delay time: SDHC_CLK to eMMC DDR mode

SDHC_CMD valid,

t_NIKHOV

—

14.6

ns

—

SDHC_CMD_DIR

Notes:

1. C_CARD≤ 10 pF, (1 card).

2. C_L= C_BUS+ C_HOST+ C_CARD≤ 20 pF for MMC. 40pF for SD.

3. For recommended operating conditions, see Table 3.

4. Refer eSDHC A-008936

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Electrical characteristics

This figure shows the eSDHC DDR50/eMMC DDR mode input AC timing diagram.

T

CLK

SDHC_CLK_SYNC_IN

T

NDIXKH

NDIVKH

SDHC_DAT

input

T

NIIXKH

NIIVKH

SDHC_CMD

input

Figure 49. eSDHC DDR50/DDR mode input AC timing diagram

This figure shows the DDR50/eMMC DDR mode output AC timing diagram.

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Electrical characteristics

T

CLK

SDHC_CLK

T

NDKHOV

SDHC_DAT/

SDHC_DATn_DIR

output

T

NDKHOX

T

NIKHOV

SDHC_CMD/

SD_CMD_DIR

output

T

NIKHOX

Figure 50. eSDHC DDR50/DDR mode output AC timing diagram

This table provides the eSDHC AC timing specifications for SDR104/eMMC HS200

mode as defined in Figure 51 (EV_DD/CV_DD= 1.8V).

Table 85. eSDHC AC timing (SDR104/eMMC HS200)

Parameter

SD/SDIO SDR104 mode

eMMC HS200 mode

Symbol

f_SCK

Min

Max

165

Units

MHz

Notes

SDHC_CLK clock frequency

—

175

53

1

SDHC_CLK duty cycle

—

47

—

ꢀ

—

1

SDHC_CLK clock rise and fall times

t_SCKR

t_SCKF

/

ns

Output hold time: SDHC_CLK to SD/SDIO SDR104 mode

t_NIKHOX

t_NIKHOV

t_IDV

1.58

1.6

—

ns

—

SDHC_CMD, SDHC DATx valid,

SDHC_CMD_DIR,

SDHC_DATx_DIR

eMMC HS200 mode

Output delay time: SDHC_CLK to SD/SDIO SDR104

—

4.15

3.9

SDHC_CMD, SDHC DATx valid,

SDHC_CMD_DIR,

SDHC_DATx_DIR

eMMC HS200 mode

Input data window (UI)

SD/SDIO SDR104 mode

eMMC HS200 mode

0.5

—

Unit

interval

0.475

Notes:

1. C_L= C_BUS+ C_HOST+ C_CARD≤ 10 pF.

2. For recommended operating conditions, see Table 3.

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Electrical characteristics

This figure provides the SDR104/HS200 mode timing diagram.

Tclk

SDHC_CLK

T _IDV

SDHC_CMD/

DATA

SDHC_DAT input

T_NIKHOV

SDHC_CMD/SDHC_CMD_DIR

SDHC_DAT/SDHC_DATn_DIR

output

DATA

T_NIKHOX

Figure 51. SDR104/eMMC HS200 mode timing diagram

3.16 Multicore programmable interrupt controller (MPIC)

This section describes the DC and AC electrical specifications for the multicore

programmable interrupt controller.

3.16.1 MPIC DC specifications

These tables provides the DC electrical characteristics for the MPIC interface.

IRQ's pins are on L1VDD, O1VDD, DVDD and CVDD power supplies.

Table 86. MPIC DC electrical characteristics (O1V_DD= 1.8 V)³

Parameter

Symbol

V_IH

V_IL

Min

Max

Unit

Notes

Input high voltage

Input low voltage

1.2

-

V

1

0.6

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Electrical characteristics

Table 86. MPIC DC electrical characteristics (O1V_DD= 1.8 V)³(continued)

Parameter

Symbol

Min

Max

Unit

Notes

Input current (O1V_IN= 0 V or O1V_IN= O1V_DD

)

I_IN

-

50

µA

V

2

-

Output high voltage (O1V_DD= min, I_OH= -0.5 mA)

Output low voltage (O1V_DD= min, I_OL= 0.5 mA)

Note:

V_OH

V_OL

1.35

-

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the min and max DV_INrespective values found in Table 3.

2. The symbol O1V_IN, in this case, represents the O1V_INsymbol referenced in Table 3.

3. For recommended operating conditions, see Table 3.

Table 87. MPIC DC electrical characteristics (DV_DD= 1.8 V)³

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 * DVDD

-

V

1, 4

V_IL

-

0.2 * DVDD

V

1, 4

Input current (DV_IN= 0 V or DV_IN= DV_DD

)

I_IN

-

50

-

µA

V

2

-

Output high voltage (DV_DD= min, I_OH= -0.5 mA)

Output low voltage (DV_DD= min, I_OL= 0.5 mA)

Note:

V_OH

V_OL

1.35

-

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the min and max DV_INrespective values found in Table 3.

2. The symbol DV_IN, in this case, represents the DV_INsymbol referenced in Table 3.

3. For recommended operating conditions, see Table 3.

4. DVDD should be replaced by the respective IO power supply i.e. L1VDD, DVDD or CVDD.

Table 88. MPIC DC electrical characteristics (DV_DD= 2.5 V)³

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 * DVDD

-

V

1, 4

V_IL

-

0.2 * DVDD

V

1, 4

Input current (DV_IN= 0 V or DV_IN= DV_DD

)

I_IN

-

50

-

µA

V

2

-

Output high voltage (DV_DD= min, I_OH= -1 mA)

Output low voltage (DV_DD= min, I_OL= 1 mA)

Note:

V_OH

V_OL

2.0

-

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the min and max DV_INrespective values found in Table 3.

2. The symbol DV_IN, in this case, represents the DV_INsymbol referenced in Table 3.

3. For recommended operating conditions, see Table 3.

4. DVDD should be replaced by the respective IO power supply i.e. L1VDD, DVDD or CVDD.

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Electrical characteristics

Table 89. MPIC DC electrical characteristics (DV_DD= 3.3 V)³

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

0.7 * DVDD

-

V

1, 4

Input low voltage

V_IL

-

0.2 * DVDD

V

1, 4

Input current (DV_IN= 0 V or DV_IN= DV_DD

)

I_IN

-

40

-

µA

V

2

-

Output high voltage (DV_DD= min, I_OH= -2 mA)

Output low voltage (DV_DD= min, I_OL= 2 mA)

Note:

V_OH

V_OL

2.4

-

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the min and max DV_INrespective values found in Table 3.

2. The symbol DV_IN, in this case, represents the DV_INsymbol referenced in Table 3.

3. For recommended operating conditions, see Table 3.

4. DVDD should be replaced by the respective IO power supply i.e. L1VDD, DVDD or CVDD.

3.16.2 MPIC AC timing specifications

This table provides the MPIC input and output AC timing specifications.

Table 90. MPIC Input AC timing specifications²

Characteristic

Symbol

t_PIWID

Min

Max

Unit

Notes

MPIC inputs-minimum pulse width

3

-

SYSCLKs

1, 3

1. MPIC inputs and outputs are asynchronous to any visible clock. MPIC outputs must be synchronized before use by any

external synchronous logic. MPIC inputs are required to be valid for at least t_PIWIDns to ensure proper operation when

working in edge triggered mode.

2. For recommended operating conditions, see Table 3.

3. Entry and exit from deep sleep respectively require a minimum pulse width t_PIWIDof 25 SYSCLK. See the Reference

Manual for details on Entry and Exit from deep sleep.

3.17 JTAG controller

This section describes the DC and AC electrical specifications for the IEEE 1149.1

(JTAG) interface.

3.17.1 JTAG DC electrical characteristics

This table provides the JTAG DC electrical characteristics.

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Electrical characteristics

Table 91. JTAG DC electrical characteristics (OV_DD= 1.8V)³

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

1.2

-

V

1

2

-

V_IL

-

0.6

V

Input current (OV_IN= 0 V or OV_IN= OV_DD

)

I_IN

-

50

µA

V

Output high voltage (OV_DD= min, I_OH= -0.5 mA)

Output low voltage (OV_DD= min, I_OL= 0.5 mA)

Notes:

V_OH

V_OL

1.35

-

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the OV_INsymbol found in Table 3.

3. For recommended operating conditions, see Table 3.

3.17.2 JTAG AC timing specifications

This table provides the JTAG AC timing specifications as defined in Figure 52 through

Figure 55.

Table 92. JTAG AC timing specifications⁴

Parameter

Symbol¹

Min

Max

Unit

MHz

Notes

JTAG external clock frequency of

operation

f_JTG

t_JTG

0

25

-

JTAG external clock cycle time

40

15

-

ns

-

JTAG external clock pulse width

measured at 1.4 V

t_JTKHKL

JTAG external clock rise and fall

times

t_JTGR/t_JTGF

0

2

ns

-

TRST_B assert time

Input setup times

Input hold times

Output valid times

Boundary-scan data

TDO

t_TRST

25

7.5

10

-

ns

2

-

t_JTDVKH

t_JTDXKH

-

3

t_JTKLDV

-

15

10

-

Output hold times

Notes:

t_JTKLDX

0

ns

3

1. The symbols used for timing specifications follow the pattern t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_JTDVKHsymbolizes JTAG device timing (JT)

with respect to the time data input signals (D) reaching the valid state (V) relative to the t_JTGclock reference (K) going to the

high (H) state or setup time. Also, t_JTDXKHsymbolizes JTAG timing (JT) with respect to the time data input signals (D)

reaching the invalid state (X) relative to the t_JTGclock reference (K) going to the high (H) state. Note that in general, the clock

reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2.TRST_B is an asynchronous level sensitive signal. The setup time is for test purposes only.

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Electrical characteristics

Parameter

Table 92. JTAG AC timing specifications⁴

Symbol¹

Min

Max

Unit

Notes

3. All outputs are measured from the midpoint voltage of the falling edge of t_TCLKto the midpoint of the signal in question. The

output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be

added for trace lengths, vias, and connectors in the system.

4. For recommended operating conditions, see Table 3.

This figure provides the AC test load for TDO and the boundary-scan outputs of the

device.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 52. AC test load for the JTAG interface

This figure provides the JTAG clock input timing diagram.

VM

JTAG external clock

t_JTGR

t_JTKHKL

t_JTGF

t_JTG

VM = Midpoint voltage (OV_DD/2)

Figure 53. JTAG clock input timing diagram

This figure provides the TRST_B timing diagram.

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Electrical characteristics

TRST_B

VM

t_TRST

VM = Midpoint voltage (OV_DD/2)

Figure 54. TRST_B timing diagram

This figure provides the boundary-scan timing diagram.

JTAG External Clock

VM

tJTDVKH

tJTDXKH

Boundary Data Inputs

Input Data Valid

tJTKLDV

tJTKLDX

Boundary Data Outputs

Output Data Valid

VM = Midpoint Voltage (OV^DD/2)

Figure 55. Boundary-scan timing diagram

3.18 I²C interface

This section describes the DC and AC electrical characteristics for the I²C interface.

3.18.1 I²C DC electrical characteristics

This table provides the DC electrical characteristics for the I²C interfaces operating at

3.3V.

Table 93. I²C DC electrical characteristics (DV_DD= 3.3V)⁵

Parameter

Symbol

V_IH

Min

0.7 *

DVDD

Max

Unit

Notes

Input high voltage

-

V

1

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Electrical characteristics

Table 93. I²C DC electrical characteristics (DV_DD= 3.3V)⁵(continued)

Parameter

Symbol

V_IL

Min

Max

Unit

Notes

Input low voltage

-

0.2 *

V

1

-

DVDD

0.4

Output low voltage

(I_OL= 3.0 mA)

V_OL

Pulse width of spikes which must be suppressed by the input filter

t_I2KHKL

0

50

ns

3

4

Input current each I/O pin (input voltage is between 0.1 x DV_DDand 0.9 I_I

x DV_DD(max)

-50

µA

Capacitance for each I/O pin

C_I

-

10

pF

-

Notes:

1. The min V_ILand max V_IHvalues are based on the respective min and max DV_INvalues found in Table 3.

3. See the chip reference manual for information about the digital filter used.

4. I/O pins obstruct the SDA and SCL lines if DV_DDis switched off.

5. For recommended operating conditions, see Table 3.

This table provides the DC electrical characteristics for the I²C interfaces operating at

2.5V.

Table 94. I²C DC electrical characteristics (DV_DD= 2.5V)⁵

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 *

DVDD

-

V

1

V_IL

0.2 *

DVDD

Output low voltage (DV_DD= min, I_OL= 3 mA)

V_OL

0

0.4

50

V

-

Pulse width of spikes which must be suppressed by the input filter

t_I2KHKL

0

ns

3

4

Input current each I/O pin (input voltage is between 0.1 x DV_DDand 0.9 I_I

x DV_DD(max)

-50

µA

Capacitance for each I/O pin

C_I

-

10

pF

-

Notes:

1. The min V_ILand max V_IHvalues are based on the respective min and max DV_INvalues found in Table 3.

3. See the chip reference manual for information about the digital filter used.

4. I/O pins obstruct the SDA and SCL lines if DV_DDis switched off.

5. For recommended operating conditions, see Table 3.

This table provides the DC electrical characteristics for the I²C interfaces operating at

1.8V.

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Electrical characteristics

Table 95. I²C DC electrical characteristics (DV_DD= 1.8V)⁵

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 *

DVDD

-

V

1

-

V_IL

0.2 *

DVDD

Output low voltage (DV_DD= min, I_OL= 3 mA)

V_OL

0

0.36

V

Pulse width of spikes which must be suppressed by the input filter

t_I2KHKL

0

50

ns

3

4

Input current each I/O pin (input voltage is between 0.1 x DV_DDand 0.9 I_I

x DV_DD(max)

-50

µA

Capacitance for each I/O pin

C_I

-

10

pF

-

Notes:

1. The min V_ILand max V_IHvalues are based on the respective min and max DV_INvalues found in Table 3.

3. See the chip reference manual for information about the digital filter used.

4. I/O pins obstruct the SDA and SCL lines if DV_DDis switched off.

5. For recommended operating conditions, see Table 3.

3.18.2 I²C AC timing specifications

This table provides the AC timing parameters for the I²C interfaces.

Table 96. I²C AC timing specifications⁵

Parameter

Symbol¹

Min

Max

Unit

kHz

Notes

SCL clock frequency

f_I2C

0

400

2

Low period of the SCL clock

t_I2CL

1.3

0.6

-

μs

-

High period of the SCL clock

t_I2CH

Setup time for a repeated START condition

t_I2SVKH

Hold time (repeated) START condition (after this period, the first t_I2SXKL

clock pulse is generated)

Data setup time

t_I2DVKH

t_I2DXKL

100

-

ns

μs

-

Data input hold time:

3

CBUS compatible masters

I²C bus devices

-

0

-

Data output delay time

t_I2OVKL

t_I2PVKH

t_I2KHDX

V_NL

-

0.9

μs

V

4

-

Setup time for STOP condition

0.6

1.3

-

Bus free time between a STOP and START condition

-

Noise margin at the LOW level for each connected device

(including hysteresis)

0.1 x OV_DD

-

Noise margin at the HIGH level for each connected device

(including hysteresis)

V_NH

0.2 x OV_DD

-

V

-

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Electrical characteristics

Table 96. I²C AC timing specifications⁵(continued)

Parameter

Symbol¹

Min

Max

Unit

pF

Notes

Capacitive load for each bus line

Cb

-

400

-

Notes:

1. The symbols used for timing specifications herein follow the pattern t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_I2DVKHsymbolizes I²C timing (I2) with

respect to the time data input signals (D) reaching the valid state (V) relative to the t_I2Cclock reference (K) going to the high

(H) state or setup time. Also, t_I2SXKLsymbolizes I²C timing (I2) for the time that the data with respect to the START condition

(S) went invalid (X) relative to the t_I2Cclock reference (K) going to the low (L) state or hold time. Also, t_I2PVKHsymbolizes I²C

timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative to the t_I2Cclock

reference (K) going to the high (H) state or setup time.

2. The requirements for I²C frequency calculation must be followed. See Determining the I²C Frequency Divider Ratio for

SCL (AN2919).

3. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the V_IHminof the SCL

signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP

condition. When the chip acts as the I²C bus master while transmitting, it drives both SCL and SDA. As long as the load on

SCL and SDA are balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns

SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the

chip as transmitter, see Determining the I²C Frequency Divider Ratio for SCL (AN2919).

4. The maximum t_I2OVKLhas to be met only if the device does not stretch the LOW period (t_I2CL) of the SCL signal.

5. For recommended operating conditions, see Table 3.

This figure provides the AC test load for the I²C.

Output

DV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 56. I²C AC test load

This figure shows the AC timing diagram for the I²C bus.

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Electrical characteristics

SDA

SCL

t_I2KHKL

t_I2DVKH

t_I2KHDX

t_I2SXKL

t_I2CL

t_I2CH

t_I2DXKL, t_I2OVKL

t_I2SVKH

t_I2PVKH

t_I2SXKL

P

S

Sr

Figure 57. I²C Bus AC timing diagram

3.19 GPIO interface

This section describes the DC and AC electrical characteristics for the GPIO interface.

GPIO pins are on OVDD, O1VDD, DVDD, CVDD, EVDD, L1VDD and LVDD power

supplies.

3.19.1 GPIO DC electrical characteristics

This table provides the DC electrical characteristics for GPIO pins operating at 3.3V.

GPIO pins on DVDD, CVDD, EVDD, L1VDD and LVDD power supplies.

Table 97. GPIO DC electrical characteristics (3.3 V)³

Parameter

Input high voltage

Symbol

Min

Max

Unit

Notes

V_IH

V_IL

I_IN

0.7 * DVDD

-

V

1, 4

2

Input low voltage

-

0.2 * DVDD

V

Input current (V_IN= 0 V or V_IN= DV_DD)

Output high voltage

-

50

-

μA

V

V_OH

2.4

-

(DV_DD= min, I_OH= -2 mA)

Output low voltage

V_OL

-

0.4

V

-

(DV_DD= min, I_OL= 2 mA)

1. The min V_ILand max V_IHvalues are based on the respective min and max DV_INvalues found in Table 3

2. The symbol V_IN, in this case, represents the DV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

4. DVDD should be replaced by the respective IO power supply i.e. L1VDD, LVDD, EVDD or CVDD.

This table provides the DC electrical characteristics for GPIO pins operating at 2.5V.

GPIO pins on DVDD, CVDD, EVDD, L1VDD and LVDD power supplies.

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Electrical characteristics

Table 98. GPIO DC electrical characteristics (2.5 V)³

Parameter

Input high voltage

Symbol

Min

Max

Unit

Notes

V_IH

V_IL

I_IN

0.7 * DVDD

-

V

1, 4

2

Input low voltage

-

0.2 * DVDD

V

Input current (V_IN= 0 V or V_IN= DV_DD)

Output high voltage

-

50

-

μA

V

V_OH

2.0

-

(DV_DD= min, I_OH= -1 mA)

Output low voltage

V_OL

-

0.4

V

-

(DV_DD= min, I_OL= 1 mA)

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3

2. The symbol V_IN, in this case, represents the LV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

4. DVDD should be replaced by the respective IO power supply i.e. L1VDD, LVDD, EVDD or CVDD.

This table provides the DC electrical characteristics for GPIO pins operating at 1.8V.

GPIO pins on DVDD, CVDD, EVDD, L1VDD and LVDD power supplies.

Table 99. GPIO DC electrical characteristics (1.8 V)³

Parameter

Input high voltage

Symbol

Min

Max

Unit

Notes

V_IH

V_IL

I_IN

0.7 * DVDD

-

V

1, 4

2

Input low voltage

-

0.2 * DVDD

V

Input current (V_IN= 0 V or V_IN= DV_DD

)

-

50

-

μA

V

Output high voltage

V_OH

1.35

-

(DV_DD= min, I_OH= -0.5 mA)

Output low voltage

V_OL

-

0.4

V

-

(DV_DD= min, I_OL= 0.5 mA)

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the LV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

4. DVDD should be replaced by the respective IO power supply i.e. L1VDD, LVDD, EVDD or CVDD.

This table provides the DC electrical characteristics for GPIO pins operating at

O1V_DD/OV_DD= 1.8 V.

Table 100. GPIO DC electrical characteristics (OVDD/O1VDD = 1.8 V)³

Parameter

Input high voltage

Symbol

Min

Max

Unit

Notes

V_IH

V_IL

I_IN

1.2

-

V

1

2

Input low voltage

-

0.6

V

Input current (V_IN= 0 V or V_IN= OV_DD

)

50

μA

Table continues on the next page...

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Electrical characteristics

Table 100. GPIO DC electrical characteristics (OVDD/O1VDD = 1.8 V)³(continued)

Parameter

Output high voltage

Symbol

Min

Max

Unit

Notes

V_OH

1.35

-

V

-

(OV_DD/O1V_DD= min, I_OH= -0.5 mA)

Output low voltage

V_OL

0.4

(OV_DD/O1V_DD= min, I_OL= 0.5 mA)

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the OV_IN/O1V_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

3.19.2 GPIO AC timing specifications

This table provides the GPIO input and output AC timing specifications.

Table 101. GPIO input AC timing specifications²

Parameter

GPIO inputs—minimum pulse width

Symbol

t_PIWID

Min

Unit

Notes

1, 3

20

ns

Notes:

1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any

external synchronous logic. GPIO inputs are required to be valid for at least t_PIWIDto ensure proper operation.

2. For recommended operating conditions, see Table 3.

3. Entry and exit from deep sleep respectively require a minimum pulse width t_PIWIDof 35 SYSCLK. See the Reference

Manual for details on Entry and Exit from deep sleep.

This figure provides the AC test load for the GPIO.

Output

(L/O) V_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 58. GPIO AC test load

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Electrical characteristics

3.20 Display interface unit

This section describes the DIU DC and AC electrical characteristics.

3.20.1 DIU DC electrical characteristics

This table provides the DIU DC electrical characteristics.

Table 102. DIU DC electrical characteristics (3.3V)¹

Parameter

Output high voltage

Symbol

V_OH

Min

Max

Unit

Notes

2.4

-

V

-

(DV_DD= min, I_OH= -2 mA)

Output low voltage

(DV_DD= min, I_OL= 2 mA)

.

V_OL

0.4

1. For recommended operating conditions, see Table 3.

3.20.2 DIU AC timing specifications

The table provides the output AC timing specifications for DIU interface.

Table 103. DIU interface timing parameters

Parameter

Display pixel clock period

Symbol

Min

Typ

Max

Unit

t_pcp

6.67

-

ns

Display pixel clock high time

t_CKH

t_CKL

0.45 x t_PCP

1.2

0.5 x t_PCP

-

0.55 x t_PCP

-

LCD interface pixel clock low time

Pixel data output setup with respect to pixel

clock

t_DIUKHDS

t_DIUKLDS

t_DIUKHDX

t_DIUKLDX

Pixel data output hold with respect to pixel

clock

1.2

-

ns

VSYNC/ HSYNC/ DE output setup respect to t_DIUKHSS

pixel clock

1.2

3.8

-

ns

VSYNC/ HSYNC/ DE output hold respect to

pixel clock

t_DIUKHSX

Note:

1. Display pixel clock frequency must be less than or equal to 1/4 of the platform clock.

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Electrical characteristics

tDIUKHSX

DIU_VSYNC/

DIU_HSYNC/

DIU_DE

tDIUKHSS

DIU_LD

tDIUKLDX

tDIUKHDX

tPCP

DIU_CLK_OUT

tCKL

tCKH

tDIUKLDS

tDIUKHDS

Figure 59. DIU interface AC timing diagram

3.21 TDM interface

This section describes the DC and AC electrical specifications for the TDM interface.

3.21.1 TDM DC Timing Specifications

This table provides the DC electrical characteristics for the TDM interface.

Table 104. TDM DC Electrical Characteristics(DV_DD= 3.3 V)³

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.7 * DVDD

-

V

1

2

-

V_IL

-

0.2 * DVDD

V

Input current (DV_IN= 0 V or DV_IN= DV_DD

)

I_IN

-

50

-

μA

V

Output high voltage (DV_DD= min, I_OH= -2 mA)

Output low voltage (DV_DD= min, I_OL= 2 mA)

Note:

V_OH

V_OL

2.4

-

0.4

V

-

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max DV_INvalues found in Table 3

2. Note that the symbol DV_INrepresents the input voltage of the supply. It is referenced in Recommended operating

conditions

3. For recommended operating conditions, see Table 3

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Electrical characteristics

3.21.2 TDM AC Timing Specifications

This table provides the input and output AC timing specifications for the TDM interface.

Table 105. TDM AC Timing Specifications for 50 MHz¹

Characteristic

TDM_RXCLK/TDM_TXCLK

Symbol²

t_DM

t_{DM_HIGH}

t_{DM_LOW}

Min

Max

Unit

Notes

20.0

8.0

3.0

3.5

2.0

4.0

-

ns

-

TDM_RXCLK/TDM_TXCLK high pulse width

TDM_RXCLK/TDM_TXCLK low pulse width

TDM all input setup time

-

t_DMIVKH

-

2

TDM_RXD hold time

t_DMRDIXKH

t_DMFSIXKH

t_{DM_OUTAC}

t_DMTKHOV

t_DMTKHOX

t_{DM_OUTHI}

-

TDM_TFS/TDM_RFS input hold time

TDM_TXCLK high to TDM_TXD output active

TDM_TXCLK high to TDM_TXD output valid

TDM_TXD hold time

-

2

-

2, 3

14.0

-

2, 3

2.0

-

TDM_TXCLK high to TDM_TXD output high

impedance

10.0

TDM_TFS/TDM_RFS output valid

TDM_TFS/TDM_RFS output hold time

Notes:

t_DMFSKHOV

t_DMFSKHOX

-

13.5

-

ns

2

2.5

1. All values are based on a maximum TDM interface frequency of 50 MHz.

2. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)

(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX

symbolizes the outputs internal timing (HI) for the time t_serialmemory clock reference (K) goes from the high state (H) until

outputs (O) are invalid (X).

3. Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming

edge they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. T_DMxTCKand

T_DMxRCKare shown using the rising edge.

4. Output values are based on 30 pF capacitive load.

This figure shows the TDM receive signal timing.

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Electrical characteristics

t _DM

t

DM_HIGH

DM_LOW

TDMxRCK

t

DMRDIXKH

DMFSIXKH

DMIVKH

TDMxRD

t

DMIVKH

TDMxRFS

t

DMFSKHOV

DMFSKHOX

TDMxRFS (output)

Figure 60. TDM Receive Signals

This figure shows the TDM transmit signal timing.

t _DM

t

DM_HIGH

DM_LOW

t

TDMx TCK

DM_OUTHI

t

DMTKHOV

t

DMTKHOX

t

DM_OUTAC

TDMxTD

TDMxRCK

t

DMFSKHOV

t

DMFSKHOX

TDMxTFS (output)

t

DMFSIXKH

DMIVKH

TDMxTFS (input)

Figure 61. TDM Transmit Signals

3.22 High-speed serial interfaces (HSSI)

The chip features a serializer/deserializer (SerDes) interface to be used for high-speed

serial interconnect applications. The SerDes interface can be used for PCI Express,

SATA, SGMII data transfers.

This section describes the common portion of SerDes DC electrical specifications: the

DC requirement for SerDes reference clocks. The SerDes data lane's transmitter (Tx) and

receiver (Rx) reference circuits are also shown.

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Electrical characteristics

3.22.1 Signal terms definition

The SerDes utilizes differential signaling to transfer data across the serial link. This

section defines the terms that are used in the description and specification of differential

signals.

This figure shows how the signals are defined. For illustration purposes only, one SerDes

lane is used in the description. This figure shows the waveform for either a transmitter

output (SD_TXn_P and SD_TXn_N) or a receiver input (SD_RXn_P and SD_RXn_N).

Each signal swings between A volts and B volts where A > B.

SD_TXn_P or

SD_RXn_P

A Volts

V_cm= (A + B)/2

SD_TXn_N or

SD_RXn_N

B Volts

Differential swing, V_IDorV_OD= A - B

Differential peak voltage, V_DIFFp= |A - B|

Differential peak-to-peak voltage, V_DIFFpp=2 x V_DIFFp(not shown)

Figure 62. Differential voltage definitions for transmitter or receiver

Using this waveform, the definitions are as shown in the following list. To simplify the

illustration, the definitions assume that the SerDes transmitter and receiver operate in a

fully symmetrical differential signaling environment:

Single-Ended Swing

The transmitter output signals and the receiver input signals SD_TXn_P, SD_TXn_N,

SD_RXn_P and SD_RXn_N each have a peak-to-peak swing of A - B volts. This is

also referred as each signal wire's single-ended swing.

Differential Output Voltage, V_OD(or Differential Output Swing)

The differential output voltage (or swing) of the transmitter, V_OD, is defined as the

difference of the two complimentary output voltages: V_{SD_TXn_P}- V_{SD_TXn_N.}The V_OD

value can be either positive or negative.

Differential Input Voltage, V_ID(or Differential Input Swing)

The differential input voltage (or swing) of the receiver, V_ID, is defined as the

difference of the two complimentary input voltages: V_{SD_RXn_P}- V_{SD_RXn_N.}The V_ID

value can be either positive or negative.

Differential Peak Voltage, V_DIFFp

The peak value of the differential transmitter output signal or the differential receiver

input signal is defined as the differential peak voltage, V_DIFFp= |A - B| volts.

Differential Peak-to-Peak, V_DIFFp-p

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Electrical characteristics

Since the differential output signal of the transmitter and the differential input signal of

the receiver each range from A - B to -(A - B) volts, the peak-to-peak value of the

differential transmitter output signal or the differential receiver input signal is defined

as differential peak-to-peak voltage, V_DIFFp-p= 2 x V_DIFFp= 2 x |(A - B)| volts, which

is twice the differential swing in amplitude, or twice of the differential peak. For

example, the output differential peak-to-peak voltage can also be calculated as V_TX-

_DIFFp-p= 2 x |V_OD|.

Differential Waveform

The differential waveform is constructed by subtracting the inverting signal

(SD_TXn_N, for example) from the non-inverting signal (SD_TXn_P, for example)

within a differential pair. There is only one signal trace curve in a differential

waveform. The voltage represented in the differential waveform is not referenced to

ground. See Figure 67 as an example for differential waveform.

Common Mode Voltage, V_cm

The common mode voltage is equal to half of the sum of the voltages between each

conductor of a balanced interchange circuit and ground. In this example, for SerDes

output, V_{cm_out}= (V_{SD_TXn}+ V_{SD_TXn_B}) ÷ 2 = (A + B) ÷ 2, which is the arithmetic

mean of the two complimentary output voltages within a differential pair. In a system,

the common mode voltage may often differ from one component's output to the other's

input. It may be different between the receiver input and driver output circuits within

the same component. It is also referred to as the DC offset on some occasions.

To illustrate these definitions using real values, consider the example of a current mode

logic (CML) transmitter that has a common mode voltage of 2.25 V and outputs, TD and

TD_B. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak voltage swing

of each signal (TD or TD_B) is 500 mV p-p, which is referred to as the single-ended

swing for each signal. Because the differential signaling environment is fully symmetrical

in this example, the transmitter output's differential swing (V_OD) has the same amplitude

as each signal's single-ended swing. The differential output signal ranges between 500

mV and -500 mV. In other words, V_ODis 500 mV in one phase and -500 mV in the other

phase. The peak differential voltage (V_DIFFp) is 500 mV. The peak-to-peak differential

voltage (V_DIFFp-p) is 1000 mV p-p.

3.22.2 SerDes reference clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates

the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are

SD1_REF_CLK[1:2]_P and SD1_REF_CLK[1:2]_N.

SerDes may be used for various combinations of the following IP blocks based on the

RCW Configuration field SRDS_PRTCLn:

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Electrical characteristics

• SGMII (1.25 and 3.125 Gbaud)

• PEX1/2/3/4 (2.5 and 5Gbps)

• Aurora (2.5 and 5 Gbps)

• SATA1/2 (1.5 and 3.0 Gbps)

The following sections describe the SerDes reference clock requirements and provide

application information.

3.22.2.1 SerDes spread-spectrum clock source recommendations

SDn_REF_CLKn_P/SDn_REF_CLKn_N are designed to work with spread-spectrum

clock for PCI Express protocol only with the spreading specification defined in Table

106. When using spread-spectrum clocking for PCI Express, both ends of the link

partners should use the same reference clock. For best results, a source without

significant unintended modulation must be used.

For SATA protocol, the SerDes transmitter does not support spread-spectrum clocking.

The SerDes receiver does support spread-spectrum clocking on receive, which means the

SerDes receiver can receive data correctly from a SATA serial link partner using spread-

spectrum clocking

The spread-spectrum clocking cannot be used if the same SerDes reference clock is

shared with other non-spread-spectrum supported protocols. For example, if the spread-

spectrum clocking is desired on a SerDes reference clock for PCI Express and the same

reference clock is used for any other protocol such as SATA/SGMII due to the SerDes

lane usage mapping option, spread-spectrum clocking cannot be used at all.

Table 106. SerDes spread-spectrum clock source recommendations ¹

Parameter

Min

Max

Unit

Notes

Frequency modulation

Frequency spread

30

+0

33

kHz

ꢀ

-

-0.5

2

1. At recommended operating conditions. See Table 3.

2. Only down-spreading is allowed.

3.22.2.2 SerDes reference clock receiver characteristics

This figure shows a receiver reference diagram of the SerDes reference clocks.

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Freescale Semiconductor, Inc.

Electrical characteristics

50 Ω

SD1_REF_CLKn_P

SD1_REF_CLKn_N

Input

amp

50 Ω

Figure 63. Receiver of SerDes reference clocks

The characteristics of the clock signals are as follows:

• The SerDes transceivers core power supply voltage requirements (S1V_DD) are as

specified in Recommended operating conditions.

• The SerDes reference clock receiver reference circuit structure is as follows:

• The SD1_REF_CLKn_P and SD1_REF_CLKn_N are internally AC-coupled

differential inputs as shown in Figure 63. Each differential clock input

(SD1_REF_CLKn_P or SD1_REF_CLKn_N) has on-chip 50-Ω termination to

SGNDn followed by on-chip AC-coupling.

• The external reference clock driver must be able to drive this termination.

• The SerDes reference clock input can be either differential or single-ended. See

the differential mode and single-ended mode descriptions below for detailed

requirements.

• The maximum average current requirement also determines the common mode

voltage range.

• When the SerDes reference clock differential inputs are DC coupled externally

with the clock driver chip, the maximum average current allowed for each input

pin is 8 mA. In this case, the exact common mode input voltage is not critical as

long as it is within the range allowed by the maximum average current of 8 mA

because the input is AC-coupled on-chip.

• This current limitation sets the maximum common mode input voltage to be less

than 0.4 V (0.4 V ÷ 50 = 8 mA) while the minimum common mode input level is

0.1 V above SGNDn. For example, a clock with a 50/50 duty cycle can be

produced by a clock driver with output driven by its current source from 0 mA to

16 mA (0-0.8 V), such that each phase of the differential input has a single-

ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.

• If the device driving the SD1_REF_CLKn_P and SD1_REF_CLKn_N inputs

cannot drive 50 Ω to SGNDn DC or the drive strength of the clock driver chip

exceeds the maximum input current limitations, it must be AC-coupled off-chip.

• The input amplitude requirement is described in detail in the following sections.

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Electrical characteristics

3.22.2.3 DC-level requirement for SerDes reference clocks

The DC level requirement for the SerDes reference clock inputs is different depending on

the signaling mode used to connect the clock driver chip and SerDes reference clock

inputs, as described below:

• Differential Mode

• The input amplitude of the differential clock must be between 400 mV and 1600

mV differential peak-to-peak (or between 200 mV and 800 mV differential

peak). In other words, each signal wire of the differential pair must have a

single-ended swing of less than 800 mV and greater than 200 mV. This

requirement is the same for both external DC-coupled or AC-coupled

connection.

• For an external DC-coupled connection, as described in SerDes reference clock

receiver characteristics, the maximum average current requirements sets the

requirement for average voltage (common mode voltage) as between 100 mV

and 400 mV. Figure 64 shows the SerDes reference clock input requirement for

DC-coupled connection scheme.

200 mV < Input amplitude or differential peak < 800 mV

SD1_REF_CLKn_P

Vmax < 800mV

100 mV < Vcm < 400 mV

Vmin > 0 V

SD1_REF_CLKn_N

Figure 64. Differential reference clock input DC requirements (external DC-coupled)

• For an external AC-coupled connection, there is no common mode voltage

requirement for the clock driver. Because the external AC-coupling capacitor

blocks the DC level, the clock driver and the SerDes reference clock receiver

operate in different common mode voltages. The SerDes reference clock receiver

in this connection scheme has its common mode voltage set to SGNDn. Each

signal wire of the differential inputs is allowed to swing below and above the

common mode voltage (SGNDn). Figure 65 shows the SerDes reference clock

input requirement for AC-coupled connection scheme.

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Electrical characteristics

200 mV < Input amplitude or differential peak < 800 mV

SD1_REF_CLKn_P

Vmax < Vcm + 400 mV

Vcm

Vmin > Vcm - 400 mV

SD1_REF_CLK_N

Figure 65. Differential reference clock input DC requirements (external AC-coupled)

• Single-Ended Mode

• The reference clock can also be single-ended. The SD1_REF_CLKn_P input

amplitude (single-ended swing) must be between 400 mV and 800 mV peak-to-

peak (from V_MINto V_MAX) with SD1_REF_CLKn_N either left unconnected or

tied to ground.

• The SD1_REF_CLKn input average voltage must be between 200 and 400 mV.

Figure 66 shows the SerDes reference clock input requirement for single-ended

signaling mode.

• To meet the input amplitude requirement, the reference clock inputs may need to

be DC- or AC-coupled externally. For the best noise performance, the reference

of the clock could be DC- or AC-coupled into the unused phase

(SD1_REF_CLKn_N) through the same source impedance as the clock input

(SD1_REF_CLKn) in use.

400 mV < SD_REF_CLKn input amplitude < 800 mV

SD1_REF_CLKn_P

0 V

SD1_REF_CLKn_N

Figure 66. Single-ended reference clock input DC requirements

3.22.2.4 AC requirements for SerDes reference clocks

This table lists the AC requirements for SerDes reference clocks for protocols running at

data rates up to 5 Gb/s.

This includes PCI Express (2.5, 5 GT/s), SGMII (1.25Gbps), 2.5G SGMII (3.125Gbps).

SerDes reference clocks to be guaranteed by the customer's application design.

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143

Electrical characteristics

Table 107. SD1_REF_CLKn_P and SD1_REF_CLKn_N input

clock requirements (S1V_DDn = 1.0 V) ¹

Parameter

Symbol

Min

Typ

100/125

Max

Unit

MHz

Notes

SD1_REF_CLKn_P/SD1_REF_CLKn_N frequency t_{CLK_REF}

range

-

2

3

4

5

-

SD1_REF_CLKn_P/SD1_REF_CLKn_N clock

frequency tolerance

t_{CLK_TOL}

t_{CLK_DUTY}

t_{CLK_DJ}

-300

-100

40

-

300

100

60

ppm

ꢀ

SD1_REF_CLKn_P/SD1_REF_CLKn_N clock

frequency tolerance

-

SD1_REF_CLKn_P/SD1_REF_CLKn_N reference

clock duty cycle

50

-

SD1_REF_CLKn_P/SD1_REF_CLKn_N max

deterministic peak-to-peak jitter at 10^-6BER

42

ps

SD1_REF_CLKn_P/SD1_REF_CLKn_N total

reference clock jitter at 10^-6BER (peak-to-peak jitter

at refClk input)

t_{CLK_TJ}

-

86

ps

6

SD1_REF_CLKn_P/SD1_REF_CLKn_N 10 kHz to

1.5 MHz RMS jitter

t_{REFCLK-LF-RMS}

-

3

ps

RMS

7

9

SD1_REF_CLKn_P/SD1_REF_CLKn_N > 1.5 MHz t_{REFCLK-HF-RMS}

to Nyquist RMS jitter

-

3.1

4

ps

RMS

SD1_REF_CLKn_P/SD1_REF_CLKn_N rising/falling t_{CLKRR/ CLKFR}

t

0.6

V/ns

edge rate

Differential input high voltage

Differential input low voltage

V_IH

V_IL

150

-

mV

ꢀ

5

-

-150

20

Rising edge rate (SD1REF_CLKn_P) to falling edge Rise-Fall

rate (SD1_REF_CLKn_N) matching Matching

10, 11

1. For recommended operating conditions, see Table 3.

2. Caution: Only 100 and 125 have been tested.In-between values do not work correctly with the rest of the system.

3. For PCI Express(2.5, 5 GT/s)

4. For SGMII, 2.5G SGMII

5. Measurement taken from differential waveform

6. Limits from PCI Express CEM Rev 2.0

7. For PCI Express-5 GT/s, per PCI Express base specification rev 3.0

9. Measured from -150 mV to +150 mV on the differential waveform (derived from SD1_REF_CLKn_P minus

SD1_REF_CLKn_N). The signal must be monotonic through the measurement region for rise and fall time. The 300 mV

measurement window is centered on the differential zero crossing. See Figure 67.

10. Measurement taken from single-ended waveform

11. Matching applies to rising edge for SD1_REF_CLKn_P and falling edge rate for SD1_REF_CLKn_N. It is measured using

a 75 mV window centered on the median cross point where SD1_REF_CLKn_P rising meets SD1_REF_CLKn_N falling.

The median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations.

The rise edge rate of SD1_REF_CLKn_P must be compared to the fall edge rate of SD1_REF_CLKn_N, the maximum

allowed difference should not exceed 20ꢀ of the slowest edge rate. See Figure 68.

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Electrical characteristics

Rise-edge rate

Fall-edge rate

V^IH= +150 mV

0.0 V

VIL = -150 mV

SD1_REF_CLKn_P -

SD1_REF_CLKn_N

Figure 67. Differential measurement points for rise and fall time

SD1_REF_CLKn_N

T

RISE

FALL

V_{CROSS MEDIAN}+75 mV

V_{CROSS MEDIAN}

V_{CROSS MEDIAN}-75 mV

SD1_REF_CLKn_P

Figure 68. Single-ended measurement points for rise and fall time matching

3.22.3 SerDes transmitter and receiver reference circuits

This figure shows the reference circuits for SerDes data lane's transmitter and receiver.

SDn_TXn_P

SDn_RXn_P

50 Ω

Transmitter

100 Ω

Receiver

SDn_TXn_N

SDn_RXn_N

Figure 69. SerDes transmitter and receiver reference circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol

section below based on the application usage:

• PCI Express

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Electrical characteristics

• Aurora interface

• Serial ATA (SATA) interface

• SGMII interface

Note that external AC-coupling capacitor is required for the above serial transmission

protocols with the capacitor value defined in the specification of each protocol section.

3.22.4 PCI Express

This section describes the clocking dependencies, DC and AC electrical specifications for

the PCI Express bus.

3.22.4.1 Clocking dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per

million (ppm) of each other at all times. This is specified to allow bit rate clock sources

with a 300 ppm tolerance.

3.22.4.2 PCI Express DC physical layer specifications

This section contains the DC specifications for the physical layer of PCI Express on this

chip.

3.22.4.2.1 PCI Express DC physical layer transmitter specifications

This section discusses the PCI Express DC physical layer transmitter specifications for

2.5 GT/s and 5 GT/s.

This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential

output at all transmitters. The parameters are specified at the component pins.

Table 108. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC

specifications (X1V_DD= 1.35 V)¹

Parameter

Symbol

Min Typical Max Units

Notes

Differential peak-to-peak

output voltage

V_TX-DIFFp-p

800

1000

1200 mV

V_TX-DIFFp-p= 2 x │ V_TX-D+- V_TX-D-│

De-emphasized differential V_TX-DE-RATIO3.0

output voltage (ratio)

3.5

4.0

dB

Ratio of the V_TX-DIFFp-pof the second and

following bits after a transition divided by the V_TX-

_DIFFp-pof the first bit after a transition.

DC differential transmitter Z_TX-DIFF-DC80

impedance

100

50

120

60

Ω

Transmitter DC differential mode low Impedance

Transmitter DC impedance Z_TX-DC

40

Required transmitter D+ as well as D- DC

Impedance during all states

Table continues on the next page...

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Table 108. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications

(X1V_DD= 1.35 V)¹(continued)

Parameter

Symbol

Min Typical Max Units

Notes

Notes:

1. For recommended operating conditions, see Table 3.

This table defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential

output at all transmitters. The parameters are specified at the component pins.

Table 109. PCI Express 2.0 (5 GT/s) differential transmitter output DC

specifications (X1V_DD= 1.35 V)¹

Parameter

Symbol

V_TX-DIFFp-p

Min Typical Max Units

Notes

Differential peak-to-peak

output voltage

800

1000

1200 mV

V_TX-DIFFp-p= 2 x │ V_TX-D+- V_TX-D-

│

Low power differential

peak-to-peak output

voltage

V_{TX-DIFFp-p_low}

400

500

1200 mV

V_TX-DIFFp-p= 2 x │ V_TX-D+- V_TX-D-

De-emphasized differential V_{TX-DE-RATIO-3.5dB}3.0

output voltage (ratio)

3.5

6.0

4.0

6.5

dB

Ratio of the V_TX-DIFFp-pof the second and

following bits after a transition divided by the

V_TX-DIFFp-pof the first bit after a transition.

De-emphasized differential V_{TX-DE-RATIO-6.0dB}5.5

output voltage (ratio)

Ratio of the V_TX-DIFFp-pof the second and

following bits after a transition divided by the

V_TX-DIFFp-pof the first bit after a transition.

DC differential transmitter Z_TX-DIFF-DC

impedance

80

40

100

50

120

60

Ω

Transmitter DC differential mode low

impedance

Transmitter DC

Impedance

Z_TX-DC

Required transmitter D+ as well as D- DC

impedance during all states

Notes:

1. For recommended operating conditions, see Table 3.

3.22.4.3 PCI Express DC physical layer receiver specifications

This section discusses the PCI Express DC physical layer receiver specifications for 2.5

GT/s and 5 GT/s.

This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential

input at all receivers. The parameters are specified at the component pins.

Table 110. PCI Express 2.0 (2.5 GT/s) differential receiver input DC

specifications (SV_DD= 1.0 V)⁴

Parameter

Symbol

V_RX-DIFFp-p

Min

Typ

Max Units

Notes

Differential input peak-to-peak

voltage

120 1000

1200 mV

V_RX-DIFFp-p= 2 x |V_RX-D+- V_RX-D-| See

Note 1.

Table continues on the next page...

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Electrical characteristics

Table 110. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (SV_DD

1.0 V)⁴(continued)

=

Parameter

Symbol

Min

80

Typ

100

Max Units

Notes

DC differential input impedance

Z_RX-DIFF-DC

120

Ω

Receiver DC differential mode

impedance. See Note 2

DC input impedance

Z_RX-DC

40

50

-

60

Ω

Required receiver D+ as well as D- DC

Impedance (50 20ꢀ tolerance). See

Notes 1 and 2.

Powered down DC input impedance Z_{RX-HIGH-IMP-DC}50

-

kΩ

Required receiver D+ as well as D- DC

Impedance when the receiver

terminations do not have power. See

Note 3.

Electrical idle detect threshold

V_RX-IDLE-DET-

65

-

175 mV

V_{RX-IDLE-DET-DIFFp-p}= 2 x |V_RX-D+-V_RX-

|

DIFFp-p

D-

Measured at the package pins of the

receiver

Notes:

1. Measured at the package pins with a test load of 50Ω to GND on each pin.

2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)

there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.

3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This

helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must

be measured at 300 mV above the receiver ground.

4. For recommended operating conditions, see Table 3.

This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential

input at all receivers. The parameters are specified at the component pins.

Table 111. PCI Express 2.0 (5 GT/s) differential receiver input DC

specifications (SV_DD= 1.0 V)⁴

Parameter

Symbol

Min

Typ

Max Units

Notes

Differential input peak-to-peak voltage V_RX-DIFFp-p

120 1000

1200 mV

V_RX-DIFFp-p= 2 x |V_RX-D+- V_RX-D-

See Note 1.

|

DC differential input impedance

DC input impedance

Z_RX-DIFF-DC

Z_RX-DC

80

40

100

50

120

60

Ω

Receiver DC differential mode

impedance. See Note 2

Required receiver D+ as well as D-

DC Impedance (50 20ꢀ

tolerance). See Notes 1 and 2.

Powered down DC input impedance

Electrical idle detect threshold

Z_{RX-HIGH-IMP-DC}50

-

kΩ

Required receiver D+ as well as D-

DC Impedance when the receiver

terminations do not have power.

See Note 3.

V_RX-IDLE-DET-

65

175 mV

V_{RX-IDLE-DET-DIFFp-p}= 2 x |V_RX-D+

V_RX-D-

-

|

DIFFp-p

Measured at the package pins of

the receiver

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Table 111. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (SV_DD= 1.0

V)⁴(continued)

Parameter

Symbol

Min

Typ

Max Units

Notes

Notes:

1. Measured at the package pins with a test load of 50 Ω to GND on each pin.

2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)

there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.

3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This

helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must

be measured at 300 mV above the receiver ground.

4. For recommended operating conditions, see Table 3.

3.22.4.4 PCI Express AC physical layer specifications

This section contains the AC specifications for the physical layer of PCI Express on this

device.

3.22.4.4.1 PCI Express AC physical layer transmitter specifications

This section discusses the PCI Express AC physical layer transmitter specifications for

2.5 GT/s and 5 GT/s.

This table defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential

output at all transmitters. The parameters are specified at the component pins. The AC

timing specifications do not include RefClk jitter.

Table 112. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC

specifications⁴

Parameter

Unit interval

Symbol

Min

Typ

Max

Units

Notes

UI

399.88 400 400.12 ps

Each UI is 400 ps 300 ppm. UI does not

account for spread-spectrum clock dictated

variations.

Minimum transmitter eye

width

T_TX-EYE

0.75

-

UI

The maximum transmitter jitter can be

derived as T_{TX-MAX-JITTER}= 1 - T_TX-EYE

=

0.25 UI. Does not include spread-spectrum

or RefCLK jitter. Includes device random

jitter at 10^-12

.

See Notes 1 and 2.

Maximum time between the T_{TX-EYE-MEDIAN-}

-

0.125 UI

Jitter is defined as the measurement

jitter median and maximum

deviation from the median

variation of the crossing points (V_TX-DIFFp-p

0 V) in relation to a recovered transmitter

UI. A recovered transmitter UI is calculated

over 3500 consecutive unit intervals of

sample data. Jitter is measured using all

=

to- MAX-JITTER

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Table 112. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC specifications⁴

(continued)

Parameter

Symbol

Min

Typ

Max

Units

Notes

edges of the 250 consecutive UI in the

center of the 3500 UI used for calculating

the transmitter UI. See Notes 1 and 2.

AC coupling capacitor

C_TX

75

-

200

nF

All transmitters must be AC coupled. The

AC coupling is required either within the

media or within the transmitting component

itself. See Note 3.

Notes:

1. Specified at the measurement point into a timing and voltage test load as shown in Figure 71 and measured over any 250

consecutive transmitter UIs.

2. A T_TX-EYE= 0.75 UI provides for a total sum of deterministic and random jitter budget of T_{TX-JITTER-MAX}= 0.25 UI for the

transmitter collected over any 250 consecutive transmitter UIs. The T_{TX-EYE-MEDIAN-to-MAX-JITTER}median is less than half of the

total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the

same as the mean. The jitter median describes the point in time where the number of jitter points on either side is

approximately equal as opposed to the averaged time value.

3. The chip's SerDes transmitter does not have C_TXbuilt-in. An external AC coupling capacitor is required.

4. For recommended operating conditions, see Table 3.

This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential

output at all transmitters. The parameters are specified at the component pins. The AC

timing specifications do not include RefClk jitter.

Table 113. PCI Express 2.0 (5 GT/s) differential transmitter output AC

specifications³

Parameter

Unit Interval

Symbol

Min

Typ

Max Units

Notes

UI

199.94 200.00 200.06 ps

Each UI is 200 ps 300 ppm. UI does not

account for spread-spectrum clock dictated

variations.

Minimum transmitter eye width T_TX-EYE

0.75

-

UI

The maximum transmitter jitter can be

derived as: T_{TX-MAX-JITTER}= 1 - T_TX-EYE

0.25 UI.

=

See Note 1.

-

Transmitter RMS deterministic T_TX-HF-DJ-DD

jitter > 1.5 MHz

-

0.15

-

ps

nF

Transmitter RMS deterministic T_TX-LF-RMS

jitter < 1.5 MHz

-

3.0

-

Reference input clock RMS jitter (< 1.5

MHz) at pin < 1 ps

AC coupling capacitor

C_TX

75

200

All transmitters must be AC coupled. The

AC coupling is required either within the

media or within the transmitting component

itself. See Note 2.

Notes:

1. Specified at the measurement point into a timing and voltage test load as shown in Figure 71 and measured over any 250

consecutive transmitter UIs.

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Electrical characteristics

Table 113. PCI Express 2.0 (5 GT/s) differential transmitter output AC

specifications³

Parameter

Symbol

Min

Typ

Max Units

Notes

2. The chip's SerDes transmitter does not have C_TXbuilt-in. An external AC coupling capacitor is required.

3. For recommended operating conditions, see Table 3.

3.22.4.4.2 PCI Express AC physical layer receiver specifications

This section discusses the PCI Express AC physical layer receiver specifications for 2.5

GT/s and 5 GT/s.

This table defines the AC specifications for the PCI Express 2.0 (2.5 GT/s) differential

input at all receivers. The parameters are specified at the component pins. The AC timing

specifications do not include RefClk jitter.

Table 114. PCI Express 2.0 (2.5 GT/s) differential receiver input AC

specifications⁴

Parameter

Unit Interval

Symbol

Min

Typ

Max

Units

Notes

UI

399.88 400.00 400.12 ps

Each UI is 400 ps 300 ppm. UI does not

account for spread-spectrum clock

dictated variations.

Minimum receiver eye width T_RX-EYE

0.4

-

UI

The maximum interconnect media and

transmitter jitter that can be tolerated by

the receiver can be derived as T_RX-MAX-

_JITTER= 1 - T_RX-EYE= 0.6 UI.

See Notes 1 and 2.

Maximum time between the T_{RX-EYE-MEDIAN-}

-

0.3

Jitter is defined as the measurement

variation of the crossing points (V_RX-DIFFp-p

= 0 V) in relation to a recovered

jitter median and maximum

deviation from the median.

to-MAX-JITTER

transmitter UI. A recovered transmitter UI

is calculated over 3500 consecutive unit

intervals of sample data. Jitter is

measured using all edges of the 250

consecutive UI in the center of the 3500

UI used for calculating the transmitter UI.

See Notes 1, 2 and 3.

Notes:

1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 71 must be used

as the receiver device when taking measurements. If the clocks to the receiver and transmitter are not derived from the same

reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.

2. A T_RX-EYE= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and

interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter

distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget

collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same as the mean. The jitter

median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the

averaged time value. If the clocks to the receiver and transmitter are not derived from the same reference clock, the

transmitter UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram.

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Electrical characteristics

Table 114. PCI Express 2.0 (2.5 GT/s) differential receiver input AC

specifications⁴

Parameter

Symbol

Min

Typ

Max

Units

Notes

3. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a

fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental

and simulated data.

4. For recommended operating conditions, see Table 3.

This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential

input at all receivers. The parameters are specified at the component pins. The AC timing

specifications do not include RefClk jitter.

Table 115. PCI Express 2.0 (5 GT/s) differential receiver input AC

specifications¹

Parameter

Unit Interval

Symbol

Min

Typ

Max

Units

Notes

UI

199.40 200.00 200.06 ps

Each UI is 200 ps 300 ppm. UI does

not account for spread-spectrum clock

dictated variations.

Max receiver inherent timing T_RX-TJ-CC

error

-

0.4

UI

The maximum inherent total timing error

for common RefClk receiver architecture

Max receiver inherent

T_RX-DJ-DD-CC

0.30

The maximum inherent deterministic

timing error for common RefClk receiver

architecture

deterministic timing error

Note:

1. For recommended operating conditions, see Table 3.

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Electrical characteristics

0.03 MHz

100 MHz

Sj sweep range

1.0 UI

0.1 UI

20 dB

decade

Sj

Rj

~ 3.0 ps RMS

0.01 MHz

0.1 MHz

1.0 MHz

10 MHz

100 MHz

1000 MHz

Figure 70. Swept sinusoidal jitter mask

3.22.4.5 Test and measurement load

The AC timing and voltage parameters must be verified at the measurement point. The

package pins of the device must be connected to the test/measurement load within 0.2

inches of that load, as shown in the following figure.

NOTE

The allowance of the measurement point to be within 0.2 inches

of the package pins is meant to acknowledge that package/

board routing may benefit from D+ and D- not being exactly

matched in length at the package pin boundary. If the vendor

does not explicitly state where the measurement point is

located, the measurement point is assumed to be the D+ and D-

package pins.

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Electrical characteristics

D + package pin

C = C_TX

Transmitter

silicon

+ package

C = C_TX

D - package pin

R = 50 Ω

Figure 71. Test/measurement load

3.22.5 Aurora interface

This section describes the Aurora clocking requirements and its DC and AC electrical

characteristics.

3.22.5.1 Aurora clocking requirements for SD1_REF_CLKn_P and

SD1_REF_CLKn_N

For more information on these specifications, see SerDes reference clocks.

3.22.5.2 Aurora DC electrical characteristics

This section describes the DC electrical characteristics for the Aurora interface.

3.22.5.2.1 Aurora transmitter DC electrical characteristics

This table defines the Aurora transmitter DC electrical characteristics.

Table 116. Aurora transmitter DC electrical characteristics (XV_DD= 1.35 V) ¹

Parameter

Symbol

V_DIFFPP

Min

Typical

1000

Max

Unit

mV p-p

Differential output voltage

800

80

1600

120

DC Differential transmitter impedance

Z_TX-DIFF-DC

100

Ω

1. For recommended operating conditions, see Table 3.

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Electrical characteristics

3.22.5.2.2 Aurora receiver DC electrical characteristics

This table defines the Aurora receiver DC electrical characteristics for the Aurora

interface.

Table 117. Aurora receiver DC electrical characteristics (SV_DD= 1.0V)¹

Parameter

Symbol

V_IN

Z_RX-DIFF-DC80

Min

Typical

Max

1600

120

Unit

mV p-p

Ω

Notes

Differential input voltage

200

-

2

3

DC Differential receiver impedance

100

Notes:

1. For recommended operating conditions, see Table 3.

2. Measured at receiver

3. DC Differential receiver impedance

3.22.5.3 Aurora AC timing specifications

This section describes the AC timing specifications for Aurora.

3.22.5.3.1 Aurora transmitter AC timing specifications

This table defines the Aurora transmitter AC timing specifications. RefClk jitter is not

included.

Table 118. Aurora transmitter AC timing specifications¹

Parameter

Deterministic jitter

Symbol

Min

Typical

Max

Unit

UI p-p

J_D

J_T

UI

-

0.17

0.35

Total jitter

Unit interval: 2.5 GBaud

Unit interval: 5.0 GBaud

Notes:

400 - 100 ppm

200 - 100 ppm

400

200

400 + 100 ppm ps

200 + 100 ppm ps

1. For recommended operating conditions, see Table 3.

3.22.5.3.2 Aurora receiver AC timing specifications

This table defines the Aurora receiver AC timing specifications. RefClk jitter is not

included.

Table 119. Aurora receiver AC timing specifications³

Parameter

Symbol

J_D

Min

Typical

Max

Unit

UI p-p

Notes

Deterministic jitter tolerance

-

0.37

1

Table continues on the next page...

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Electrical characteristics

Table 119. Aurora receiver AC timing specifications³(continued)

Parameter

Symbol

J_DR

Min

Typical

Max

Unit

UI p-p

Notes

Combined deterministic and random

jitter tolerance

-

0.55

1

Total jitter tolerance

J_T

-

0.65

UI p-p

-

1, 2

Bit error rate

BER

UI

10^-12

-

Unit Interval: 2.5 GBaud

Unit Interval: 5.0 GBaud

Notes:

400 - 100 ppm 400

200 - 100 ppm 200

400 + 100 ppm ps

200 + 100 ppm ps

UI

1. Measured at receiver

2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 21. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

3. For recommended operating conditions, see Table 3.

3.22.6 Serial ATA (SATA) interface

This section describes the DC and AC electrical specifications for the serial ATA

(SATA) interface.

3.22.6.1 SATA DC electrical characteristics

This section describes the DC electrical characteristics for SATA.

3.22.6.1.1 SATA DC transmitter output characteristics

This table provides the differential transmitter output DC characteristics for the SATA

interface at Gen1i/1m or 1.5 Gbits/s transmission.

Table 120. Gen1i/1m 1.5G transmitter DC specifications (X1V_DD= 1.35 V)³

Parameter

Symbol

Min

Typ

Max

Units

Notes

Tx differential output voltage

V_{SATA_TXDIFF}

400

85

500

100

600

115

mV p-p

1

2

Tx differential pair impedance

Notes:

Z_{SATA_TXDIFFIM}

Ω

1. Terminated by 50 Ω load

2. DC impedance

3. For recommended operating conditions, see Table 3.

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Electrical characteristics

This table provides the differential transmitter output DC characteristics for the SATA

interface at Gen2i/2m or 3.0 Gbits/s transmission.

Table 121. Gen 2i/2m 3G transmitter DC specifications (X1V_DD= 1.35 V)²

Parameter

Symbol

Min

Typ

Max

Units

Notes

Transmitter differential output voltage

V_{SATA_TXDIFF}

400

85

-

700

115

mV p-p

1

-

Transmitter differential pair impedance

Notes:

Z_{SATA_TXDIFFIM}

100

Ω

1. Terminated by 50 Ω load.

2. For recommended operating conditions, see Table 3.

3.22.6.1.2 SATA DC receiver input characteristics

This table provides the Gen1i/1m or 1.5 Gbits/s differential receiver input DC

characteristics for the SATA interface.

Table 122. Gen1i/1m 1.5 G receiver input DC specifications (SV_DD= 1.0 V)³

Parameter

Symbol

Min

Typical

Max

Units

mV p-p

Ω

Notes

Differential input voltage

V_{SATA_RXDIFF}

240

85

500

100

120

600

115

240

1

2

-

Differential receiver input impedance Z_{SATA_RXSEIM}

OOB signal detection threshold

V_{SATA_OOB}

50

mV p-p

Notes:

1. Voltage relative to common of either signal comprising a differential pair

2. DC impedance

3. For recommended operating conditions, see Table 3.

This table provides the Gen2i/2m or 3 Gbits/s differential receiver input DC

characteristics for the SATA interface.

Table 123. Gen2i/2m 3 G receiver input DC specifications (SV_DD= 1.0 V)³

Parameter

Differential input voltage

Differential receiver input impedance

OOB signal detection threshold

Notes:

Symbol

V_{SATA_RXDIFF}

Z_{SATA_RXSEIM}

V_{SATA_OOB}

Min

Typical

Max

Units

mV p-p

Notes

240

85

-

750

115

240

1

2

100

120

Ω

75

mV p-p

1. Voltage relative to common of either signal comprising a differential pair

2. DC impedance

3. For recommended operating conditions, see Table 3.

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157

Electrical characteristics

3.22.6.2 SATA AC timing specifications

This section discusses the SATA AC timing specifications.

3.22.6.2.1 AC requirements for SATA REF_CLK

The AC requirements for the SATA reference clock listed in this table are to be

guaranteed by the customer's application design.

Table 124. SATA reference clock input requirements⁶

Parameter

Symbol

Min

Typ

Max

Unit

MHz

Notes

SD1_REF_CLKn_P/SD1_REF_CLKn_N

frequency range

t_{CLK_REF}

-

100/125

-

1

-

SD1_REF_CLKn_P/SD1_REF_CLKn_N clock t_{CLK_TOL}

frequency tolerance

-350

40

-

+350

60

ppm

ꢀ

SD1_REF_CLKn_P/SD1_REF_CLKn_N

reference clock duty cycle

t_{CLK_DUTY}

50

-

5

2

SD1_REF_CLKn_P/SD1_REF_CLKn_N cycle- t_{CLK_CJ}

to-cycle clock jitter (period jitter)

100

+50

ps

SD1_REF_CLKn_P/SD1_REF_CLKn_N total

reference clock jitter, phase jitter (peak-to-peak)

t_{CLK_PJ}

-50

-

ps

2, 3, 4

Notes:

1. Caution:Only 100 and 125MHz have been tested. In-between values do not work correctly with the rest of the system.

2. At RefClk input

3. In a frequency band from 150 kHz to 15 MHz at BER of 10^-12

4. Total peak-to-peak deterministic jitter must be less than or equal to 50 ps.

5. Measurement taken from differential waveform

6. For recommended operating conditions, see Table 3.

3.22.6.3 AC transmitter output characteristics

This table provides the differential transmitter output AC characteristics for the SATA

interface at Gen1i/1m or 1.5 Gbits/s transmission. The AC timing specifications do not

include RefClk jitter.

Table 125. Gen1i/1m 1.5 G transmitter AC specifications²

Parameter

Channel speed

Symbol

t_{CH_SPEED}

Min

Typ

Max

Units

Gbps

Notes

-

1.5

-

Unit Interval

T_UI

666.4333

666.6667

670.2333

0.355

ps

Total jitter data-data 5 UI

Total jitter, data-data 250 UI

Deterministic jitter, data-data 5 UI

U_{SATA_TXTJ5UI}

U_{SATA_TXTJ250UI}

U_{SATA_TXDJ5UI}

-

UI p-p

1

0.47

0.175

Table continues on the next page...

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Electrical characteristics

Table 125. Gen1i/1m 1.5 G transmitter AC specifications²(continued)

Parameter

Deterministic jitter, data-data 250 UI

Notes:

Symbol

Min

Typ

Max

Units

UI p-p

Notes

U_{SATA_TXDJ250UI}

-

0.22

1

1. Measured at transmitter output pins peak to peak phase variation, random data pattern

2. For recommended operating conditions, see Table 3.

This table provides the differential transmitter output AC characteristics for the SATA

interface at Gen2i/2m or 3.0 Gbits/s transmission. The AC timing specifications do not

include RefClk jitter.

Table 126. Gen 2i/2m 3 G transmitter AC specifications²

Parameter

Channel speed

Symbol

t_{CH_SPEED}

Min

Typ

Max

Units

Gbps

Notes

-

3.0

-

Unit Interval

T_UI

333.2167

333.3333

335.1167

0.37

ps

Total jitter f_C3dB= f_BAUDꢁ 500

Total jitter f_C3dB= f_BAUDꢁ 1667

U_{SATA_TXTJfB/500}

U_{SATA_TXTJfB/1667}

-

UI p-p

1

0.55

Deterministic jitter, f_C3dB= f_BAUDꢁ 500 U_{SATA_TXDJfB/500}

0.19

Deterministic jitter, f_C3dB= f_BAUD

1667

ꢁ

U_{SATA_TXDJfB/1667}

0.35

Notes:

1. Measured at transmitter output pins peak-to-peak phase variation, random data pattern

2. For recommended operating conditions, see Table 3.

3.22.6.4 AC differential receiver input characteristics

This table provides the Gen1i/1m or 1.5 Gbits/s differential receiver input AC

characteristics for the SATA interface. The AC timing specifications do not include

RefClk jitter.

Table 127. Gen 1i/1m 1.5G receiver AC specifications²

Parameter

Symbol

Min

Typical

Max

670.2333

0.43

Units

ps

Notes

Unit Interval

T_UI

666.4333

666.6667

-

Total jitter data-data 5 UI

U_{SATA_RXTJ5UI}

U_{SATA_RXTJ250UI}

U_{SATA_RXDJ5UI}

-

UI p-p

1

Total jitter, data-data 250 UI

Deterministic jitter, data-data 5 UI

0.60

0.25

Deterministic jitter, data-data 250 UI U_{SATA_RXDJ250UI}

Notes:

0.35

1. Measured at receiver.

2. For recommended operating conditions, see Table 3.

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159

Hardware design considerations

This table provides the differential receiver input AC characteristics for the SATA

interface at Gen2i/2m or 3.0 Gbits/s transmission. The AC timing specifications do not

include RefClk jitter.

Table 128. Gen 2i/2m 3G receiver AC specifications²

Parameter

Symbol

Min

Typical

Max

335.1167

0.60

Units

ps

Notes

Unit Interval

T_UI

U_{SATA_RXTJfB/500}

U_{SATA_RXTJfB/1667}

333.2167

333.3333

-

Total jitter f_C3dB= f_BAUDꢁ 500

Total jitter f_C3dB= f_BAUDꢁ 1667

-

UI p-p

1

0.65

Deterministic jitter, f_C3dB= f_BAUDꢁ 500 U_{SATA_RXDJfB/500}

Deterministic jitter, f_C3dB= f_BAUDꢁ 1667 U_{SATA_RXDJfB/1667}

Notes:

0.42

0.35

1. Measured at receiver

2. For recommended operating conditions, see Table 3.

4 Hardware design considerations

4.1 System clocking

This section describes the PLL configuration of the chip.

4.1.1 PLL characteristics

Characteristics of the chip's PLLs include the following:

• There are two core cluster PLLs which generate a clock for each core cluster from

the externally supplied SYSCLK input.

• Core cluster Group A PLL 1 and Core cluster group A PLL 2

• The frequency ratio between each of the core cluster PLLs and SYSCLK is

selected using the configuration bits as described in Core cluster to SYSCLK

PLL ratio. The frequency for each core cluster is selected using the configuration

bits as described in Table 133.

• The platform PLL generates the platform clock from the externally supplied

SYSCLK input. The frequency ratio between the platform and SYSCLK is selected

using the platform PLL ratio configuration bits as described in Platform to SYSCLK

PLL ratio.

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Hardware design considerations

• Cluster group A generates an asynchronous clock for eSDHC SDR mode from CGA

PLL1 or CGA PLL2. Described in eSDHC SDR mode clock select.

• The DDR block PLL generates an asynchronous DDR clock from the externally

supplied DDRCLK input. The frequency ratio is selected using the Memory

Controller Complex PLL multiplier/ratio configuration bits as described in DDR

controller PLL ratios.

• SerDes block has 2 PLLs which generate a core clock from their respective

externally supplied SD1_REF_CLKn_P/SD1_REF_CLKn_N inputs. The frequency

ratio is selected using the SerDes PLL RCW configuration bits as described in

SerDes PLL ratio.

• When using Single Oscillator Source clocking mode, a single onboard oscillator can

provide the reference clock (100MHz) to all the PLL's that is, Platform PLL, Core

Cluster PLL's, DDR PLL, USB PLL and Serdes PLL's.

4.1.2 Clock ranges

This table provides the clocking specifications for the processor core, platform, memory,

and integrated flash controller.

Table 129. Processor, platform, and memory clocking specifications

Characteristic

Maximum processor core frequency

1200 MHz 1400 MHz 1500 MHz

Min Max Min Max Min Max

800 1200 800 1500

Unit

Notes

Core cluster group PLL frequency

Core cluster frequency

800

400

300

500

625

-

1400

600

800

100

600

MHz

1, 2

400

300

1200

500

800

100

500

400

300

500

625

-

1500

600

800

100

600

MHz

2

Platform clock frequency

1, 7

1, 3, 4

5

Memory bus clock frequency (DDR3L) 500

Memory bus clock frequency (DDR4) 625

IFC clock frequency

FMAN

-

300

6

1. Caution:The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting

SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum

operating frequencies

2. The core cluster can run at cluster group PLL/1 and PLL/2. For the PLL/1 case, the minimum frequency is 800 MHz. With a

minimum cluster group PLL frequency of 800 MHz, this results in a minimum allowable core cluster frequency of 400 MHz for

PLL/2. Frequency provided to the e5500 cluster after any dividers must always be greater than or equal to the platform

frequency. For the case of the minimum platform frequency = 400 MHz, the minimum core cluster frequency is 400 MHz.

3. The memory bus clock speed is half the DDR3L/DDR4 data rate.

4. The memory bus clock speed is dictated by its own PLL.

5. The integrated flash controller (IFC) clock speed on IFC_CLK[0:1] is determined by the IFC module input clock (platform

clock / 2) divided by the IFC ratio programmed in CCR[CLKDIV]. See the chip reference manual for more information.

6. The FMan minimum frequency is 333 MHz for 2.5G SGMII. FMan maximum frequency is 600MHz.

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Freescale Semiconductor, Inc.

161

Hardware design considerations

Table 129. Processor, platform, and memory clocking specifications

Characteristic

Maximum processor core frequency

1200 MHz 1400 MHz 1500 MHz

Min Max Min Max Min Max

Unit

Notes

7. 1200MHz bin cannot support Gen2, x4 PCIe. The minimum platform frequency should meet the requirements in Minimum

platform frequency requirements for high-speed interfaces.

8. "Single Oscillator Source" Reference clock mode supports differential reference clock pair frequency of 100MHz.

4.1.2.1 DDR clock ranges

The DDR memory controller can run only in asynchronous mode, where the memory bus

is clocked with the clock provided on the DDRCLK input pin, which has its own

dedicated PLL.

This table provides the clocking specifications for the memory bus.

Table 130. Memory bus clocking specifications

Characteristic

Memory bus clock frequency

Min

Max

Unit

MHz

Notes

DDR3L

DDR4

500

625

800

1, 2, 3, 4

Notes:

1. Caution: The platform clock to SYSCLK ratio and core to SYSCLK clock ratio settings must be chosen such that the

resulting SYSCLK frequency, core frequency, and platform frequency do not exceed their respective maximum or minimum

operating frequencies. See Platform to SYSCLK PLL ratio, and Core cluster to SYSCLK PLL ratio, and DDR controller PLL

ratios, for ratio settings.

2. The memory bus clock refers to the chip's memory controllers' D1_MCK[0:1] and D1_MCK[0:1]_B output clocks, running at

half of the DDR data rate.

3. The memory bus clock speed is dictated by its own PLL. See DDR controller PLL ratios.

4. Minimum Frequency supported by DDR4 is 1250MT/s

4.1.3 Platform to SYSCLK PLL ratio

This table lists the allowed platform clock to SYSCLK ratios.

Because the DDR operates asynchronously, the memory-bus clock-frequency is

decoupled from the platform bus frequency.

For all valid platform frequencies supported on this chip, set the RCW Configuration

field SYS_PLL_CFG = 0b00.

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Hardware design considerations

Table 131. Platform to SYSCLK PLL ratios

Binary Value of SYS_PLL_RAT

Platform:SYSCLK Ratio

0_0011

0_0100

0_0101

0_0110

0_0111

0_1000

0_1001

All Others

3:1

4:1

5:1

6:1

7:1

8:1

9:1

Reserved

4.1.4 Core cluster to SYSCLK PLL ratio

The clock ratio between SYSCLK and each of the core cluster PLLs is determined by the

binary value of the RCW Configuration field CGA_PLLn_RAT. This table describes the

supported ratios. For all valid core cluster frequencies supported on this chip, set the

RCW Configuration field CGA_PLLn_CFG = 0b00.

This table lists the supported asynchronous core cluster to SYSCLK ratios.

Table 132. Core cluster PLL to SYSCLK ratios

Binary value of CGA_PLLn_RAT(n=1 or 2)

00_0110

Core cluster:SYSCLK Ratio

6:1

00_0111

00_1000

00_1001

00_1010

00_1011

00_1100

00_1101

00_1110

00_1111

01_0000

01_0010

01_0100

01_0110

01_1001

01_1010

01_1011

All others

7:1

8:1

9:1

10:1

11:1

12:1

13:1

14:1

15:1

16:1

18:1

20:1

22:1

25:1

26:1

27:1

Reserved

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163

Hardware design considerations

4.1.5 Core complex PLL select

The clock frequency of each core cluster is determined by the binary value of the RCW

Configuration field Cn_PLL_SEL. These tables describe the selections available to each

core cluster, where each individual core cluster can select a frequency from their

respective tables.

NOTE

There is a restriction that requires that the frequency provided

to the e5500 core cluster after any dividers must always be

greater than half of the platform frequency. Special care must

be used when selecting the /2 outputs of a cluster PLL in which

this restriction is observed.

Table 133. Core cluster PLL select

Binary Value of Cn_PLL_SEL for n=1-4

Core cluster ratio

0000

CGA PLL1 /1

CGA PLL1 /2

CGA PLL2 /1

CGA PLL2 /2

Reserved

0001

0100

0101

All Others

4.1.6 DDR controller PLL ratios

The DDR memory controller operates asynchronous to the platform.

In asynchronous DDR mode, the DDR data rate to DDRCLK ratios supported are listed

in the following table. This ratio is determined by the binary value of the RCW

Configuration field MEM_PLL_RAT (bits 10-15).

The RCW Configuration field MEM_PLL_CFG (bits 8-9) must be set to

MEM_PLL_CFG = 0b00 for all valid DDR PLL reference clock frequencies supported

on this chip.

Table 134. DDR clock ratio

Binary value of MEM_PLL_RAT

00_1000

DDR data-rate:DDRCLK ratio

Maximum supported DDR data-rate

(MT/s)

8:1

1066

00_1010

00_1011

10:1

11:1

1333

1465

Table continues on the next page...

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Hardware design considerations

Table 134. DDR clock ratio (continued)

Binary value of MEM_PLL_RAT

DDR data-rate:DDRCLK ratio

Maximum supported DDR data-rate

(MT/s)

00_1100

12:1

13:1

14:1

15:1

16:1

20:1

24:1

1600

00_1101

00_1110

00_1111

01_0000

1_0100

1300

1400

1500

1600

1333

1600

-

1_1000

All Others

Reserved

4.1.7 SerDes PLL ratio

The clock ratio between each of the two SerDes PLLs and their respective externally

supplied SD1_REF_CLKn_P/SD1_REF_CLKn_N inputs is determined by a set of RCW

Configuration fields-SRDS_PRTCL_S1, SRDS_PLL_REF_CLK_SEL_S1, and

SRDS_DIV_*_S1 as shown in this table.

Table 135. Valid SerDes RCW encodings and reference clocks

SerDes protocol (given

lane)

Valid reference

clock

Legal setting for

SRDS_PRTCL_S1

Legal setting

for

Legal setting for Notes

SRDS_DIV_*_S1

frequency

SRDS_PLL_RE

F_CLK_SEL_S1

High-speed serial interfaces

PCI Express 2.5 Gbps

(doesn't negotiate upwards)

PCI Express 5 Gbps

100 MHz

125 MHz

100 MHz

125 MHz

100 MHz

125 MHz

100 MHz

125 MHz

100 MHz

125 MHz

Any PCIe

0b0: 100 MHz

0b1: 125 MHz

0b0: 100 MHz

0b1: 125 MHz

0b0: 100 MHz

0b1: 125 MHz

0b0: 100 MHz

0b1: 125 MHz

0b0: 100 MHz

0b1: 125 MHz

2b10: 2.5 G

2b01: 5.0 G

Don't care

0b1: 2.5 G

0b0: 5.0 G

1

2

Any PCIe

(can negotiate up to 5 Gbps)

SATA (1.5 or 3 Gbps)

Any SATA

Debug (2.5 Gbps)

Debug (5 Gbps)

Aurora @ 2.5/5 Gbps

-

Networking interfaces

SGMII (1.25 Gbps)

100 MHz

125 MHz

SGMII @ 1.25 Gbps

0b0: 100 MHz

0b1: 125 MHz

Don't care

-

1000Base-KX @ 1.25

Gbps

2.5G SGMII (3.125 Gbps)

125 MHz

SGMII @ 3.125 Gbps

0b0: 125 MHz

-

Table continues on the next page...

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165

Hardware design considerations

Table 135. Valid SerDes RCW encodings and reference clocks (continued)

SerDes protocol (given

lane)

Valid reference

clock

Legal setting for

SRDS_PRTCL_S1

Legal setting

for

Legal setting for Notes

SRDS_DIV_*_S1

frequency

SRDS_PLL_RE

F_CLK_SEL_S1

1. A spread-spectrum reference clock is permitted for PCI Express. However, if any other high-speed interface such as

SATA, SGMII, SGMII 2.5G, 1000Base-KX, is used concurrently on the same SerDes PLL, spread-spectrum clocking is not

permitted.

2. SerDes lanes configured as SATA initially operate at 3.0 Gbps. 1.5 Gbps operation may later be enabled through the

SATA IP itself. It is possible for software to set each SATA at different rate.

4.1.8 eSDHC SDR mode clock select

The eSDHC SDR mode is asynchronous to the platform.

This table describes the clocking options that may be applied to the eSDHC SDR mode.

The clock selection is determined by the binary value of the RCW Clocking

Configuration field HWA_CGA_M1_CLK_SEL.

Table 136. eSDHC SDR mode clock select

Binary value of HWA_CGA_M1_CLK_SEL

eSDHC SDR mode frequency¹

0b000

0b001

0b010

0b011

0b100

0b101

0b110

0b111

Notes:

Reserved

Cluster group A PLL 1/1

Cluster group A PLL 1/2

Cluster group A PLL 1/3

Cluster group A PLL 1/4

Reserved

Cluster group A PLL 2/2

Cluster group A PLL 2/3

1. For asynchronous mode, max frequency, see table "Processor clocking specifications" in the chip reference manual.

2. For SDR104 and HS200 modes, CGA1 PLL should be set to provide a minimum of 1200MHz.

3. For SDR50 mode, Cluster PLL should be set to provide a minimum of 600MHz

4.1.9 Frequency options

This section discusses interface frequency options.

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Hardware design considerations

4.1.9.1 SYSCLK and core cluster frequency options

This table shows the expected frequency options for SYSCLK and core cluster

frequencies.

Table 137. SYSCLK and core cluster frequency options

Core cluster:

SYSCLK (MHz)

SYSCLK Ratio

64.00

66.67

100.00

125.00

133.33

Core cluster Frequency (MHz)¹

6:1

800

7:1

875

933

8:1

800

1000

1125

1250

1375

1500

1067

1200

1333

1463

9:1

900

10:1

11:1

12:1

13:1

14:1

15:1

16:1

18:1

20:1

21:1

22:1

23:1

1000

1100

1200

1300

1400

1500

800

832

867

896

933

960

1000

1067

1200

1333

1400

1467

1024

1152

1280

1344

1408

1472

Notes:

1. Core cluster frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed)

2. When using Single Source clocking only 100MHz input is available.

4.1.9.2 SYSCLK and platform frequency options

This table shows the expected frequency options for SYSCLK and platform frequencies.

Table 138. SYSCLK and platform frequency options

Platform: SYSCLK Ratio

SYSCLK (MHz)

64.00

66.67

100.00

125.00

133.33

Platform Frequency (MHz)¹

3:1

300

400

500

600

375

500

400

533

4:1

5:1

6:1

320

384

333

400

Table continues on the next page...

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167

Hardware design considerations

Table 138. SYSCLK and platform frequency options (continued)

Platform: SYSCLK Ratio

SYSCLK (MHz)

64.00

66.67

100.00

125.00

133.33

Platform Frequency (MHz)¹

7:1

448

512

576

467

533

600

8:1

9:1

Notes:

1. Platform frequency values are shown rounded down to the nearest whole number (decimal place accuracy removed)

2. When using Single source clocking, only 100MHz options are valid

4.1.9.3 DDRCLK and DDR data rate frequency options

This table shows the expected frequency options for DDRCLK and DDR data rate

frequencies.

Table 139. DDRCLK and DDR data rate frequency options

DDR data rate:

DDRCLK Ratio

DDRCLK (MHz)

64.00

66.67

100.00

125.00

133.33

DDR Data Rate (MT/s)¹

8:1

1000

1066

1333

1465

1600

10:1

11:1

12:1

13:1

14:1

15:1

16:1

20:1

24:1

1000

1100

1200

1300

1400

1500

1600

1250

1375

1500

1000

1067

1333

1600

1024

1280

1536

Notes:

1. DDR data rate values are shown rounded up to the nearest whole number (decimal place accuracy removed)

2. When using Single Source clocking, only 100MHz options are available.

3. Minimum Frequency supported by DDR4 is 1250MT/s

4.1.9.4 SYSCLK and eSDHC High Speed modes frequency options

These table shows the expected frequency options for SYSCLK and eSDHC High Speed

modes.

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Freescale Semiconductor, Inc.

Hardware design considerations

Table 140. SYSCLK and eSDHC High Speed mode frequency options

(clocked by CGA PLL1 / 1)

Core cluster:

SYSCLK (MHz)

SYSCLK Ratio

64.00

66.67

100.00

125.00

133.33

Resultant Frequency (MHz)¹

1200

9:1

12:1

18:1

1200

1152

1200

Notes:

1. Resultant frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed)

2. For Low speed operation, eSDHC is clocked from Platform PLL and does not use CGA PLL.

4.1.9.5 Minimum platform frequency requirements for high-speed

interfaces

The platform clock frequency must be considered for proper operation of high-speed

interfaces as described below.

For proper PCI Express operation, the platform clock frequency must be greater than or

equal to:

527 MHz x (PCI Express link width)

8

Figure 72. Gen 1 PEX minimum platform frequency

527 MHz x (PCI Express link width)

4

Figure 73. Gen 2 PEX minimum platform frequency

See section "Link Width," in the chip reference manual for PCI Express interface width

details. Note that "PCI Express link width" in the above equation refers to the negotiated

link width as the result of PCI Express link training, which may or may not be the same

as the link width POR selection. It refers to the widest port in use, not the combined

width of the number ports in use. For instance, if two x4 PCIe Gen2 ports are in use,

527MHz platform frequency is needed to support by using Gen 2 equation (527 x 4 / 4,

not 527 x 4 x 2 / 4).

NOTE

1. Platform needs to run at a minimum frequency of 527MHz

for PEX in Gen2 speed with x4 link width.

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169

Hardware design considerations

2. Platform needs to run at a minimum frequency of 400MHz

for PEX in Gen2 speed.

4.2 Power supply design

4.2.1 Core and platform supply voltage filtering

The V_DD, V_DDCsupply is normally derived from a high current capacity linear or

switching power supply which can regulate its output voltage very accurately despite

changes in current demand from the chip within the regulator's relatively low bandwidth.

Several bulk decoupling capacitors must be distributed around the PCB to supply

transient current demand above the bandwidth of the voltage regulator.

These bulk capacitors should have a low ESR (equivalent series resistance) rating to

ensure the quick response time necessary. They should also be connected to the power

and ground planes through two vias to minimize inductance. However, customers should

work directly with their power regulator vendor for best values and types of bulk

capacitors.

As a guideline for customers and their power regulator vendors, Freescale recommends

that these bulk capacitors be chosen to maintain the positive transient power surges to

less than 1.0V+50 mV (negative transient undershoot should comply with specification

of 1.0V-30mV) for current steps of up to 10A with a slew rate of 12 A/us.

These bulk decoupling capacitors will ideally supply a stable voltage for current

transients into the megahertz range. Above that, see Decoupling recommendations for

further decoupling recommendations.

4.2.2 PLL power supply filtering

Each of the PLLs described in System clocking is provided with power through

independent power supply pins (AV_DD_PLAT, A_VDD_CGA1, A_VDD_CGA2, AV_DD_D1

and AV_DD_SD1_PLLn). AV_DD_PLAT, A_VDD_CGA1, A_VDD_CGA2 and AV_DD_D1

voltages must be derived directly from a 1.8 V voltage source through a low frequency

filter scheme. AV_DD_SD1_PLLn voltages must be derived directly from the X1V_DD

source through a low frequency filter scheme. The recommended solution for PLL

filtering is to provide independent filter circuits per PLL power supply, as illustrated in

Figure 74, one for each of the AV_DDpins. By providing independent filters to each PLL,

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

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Freescale Semiconductor, Inc.

Hardware design considerations

the opportunity to cause noise injection from one PLL to the other is reduced. This circuit

is intended to filter noise in the PLL's resonant frequency range from a 500 kHz to 10

MHz range.

Each circuit should be placed as close as possible to the specific AV_DDpin being

supplied to minimize noise coupled from nearby circuits. It should be possible to route

directly from the capacitors to the AV_DDpin, which is on the periphery of the footprint,

without the inductance of vias.

This figure shows the PLL power supply filter circuit.

Where:

• R = 5 Ω 5%

• C1 = 10 μF 10%, 0603, X5R, with ESL ≤ 0.5 nH

• C2 = 1.0 μF 10%, 0402, X5R, with ESL ≤ 0.5 nH

NOTE

A higher capacitance value for C2 may be used to improve

the filter as long as the other C2 parameters do not change

(0402 body, X5R, ESL ≤ 0.5 nH).

NOTE

Voltage for AV_DDis defined at the input of the PLL supply

filter and not the pin of AV_DD.

R

1.8 V source

AVDD_PLAT, AVDD_CGA1, AVDD_CGA2, AVDD_D1

C1

C2

Low-ESL surface-mount capacitors

GND

Figure 74. PLL power supply filter circuit

The AV_DD_SD1_PLLn signals provides power for the analog portions of the SerDes

PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered

using a circuit similar to the one shown in following Figure 75. For maximum

effectiveness, the filter circuit is placed as closely as possible to the AV_DD_SD1_PLLn

balls to ensure it filters out as much noise as possible. The ground connection should be

near the AV_DD_SD1_PLLn balls. The 0.003-µF capacitors closest to the balls, followed

by a 4.7-µF and 47-µF capacitor, and finally the 0.33 Ω resistor to the board supply plane.

The capacitors are connected from AV_DD_SD1_PLLn to the ground plane. Use ceramic

chip capacitors with the highest possible self-resonant frequency. All traces should be

kept short, wide, and direct.

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171

Hardware design considerations

0.33 Ω

AVDD_SD1_PLLn

X1VDD

47 µF

4.7 µF

0.003 µF

AGND_SD1_PLLn

Figure 75. SerDes PLL power supply filter circuit

Note the following:

• AV_DD_SDn_PLLn should be a filtered version of XnV_DD.

• Signals on the SerDes interface are fed from the X1V_DDpower plane.

• Voltage for AV_DD_SD1_PLLn is defined at the PLL supply filter and not the pin of

AV_DD_SD1_PLLn.

• A 47-µF 0805 XR5 or XR7, 4.7-µF 0603, and 0.003-µF 0402 capacitor are

recommended. The size and material type are important. A 0.33-Ω 1% resistor is

recommended.

• There needs to be dedicated analog ground, AGND_SD1_PLLn for each

AV_DD_SD1_PLLn pin up to the physical local of the filters themselves.

4.2.3 S1V_DDpower supply filtering

S1V_DDshould be supplied by a linear regulator.

An example solution for S1V_DDfiltering, is illustrated in Figure 76. The component

values in this example filter are system dependent and are still under characterization,

component values may need adjustment based on the system or environment noise.

Where:

• C1 = 0.003 μF 10%, X5R, with ESL ≤ 0.5 nH

• C2 and C3 = 2.2 μF 10%, X5R, with ESL ≤ 0.5 nH

• F1 and F2 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata

BLM18PG121SH1)

• Bulk and decoupling capacitors are added, as needed, per power supply design.

F1

F2

Bulk and

decoupling

capacitors

S1V_DD

Linear regulator output

C1

C2

C3

GND

Figure 76. SV_DDpower supply filter circuit

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Freescale Semiconductor, Inc.

Hardware design considerations

Note the following:

• Refer to Power-on ramp rate, for maximum S1V_DDpower-up ramp rate.

• There needs to be enough output capacitance or a soft start feature to assure ramp

rate requirement is met.

• The ferrite beads should be placed in parallel to reduce voltage droop.

• Besides a linear regulator, a low noise dedicated switching regulator can also be

used. 10 mVp-p, 50kHz - 500MHz is the noise goal.

4.2.4 X1V_DDpower supply filtering

X1V_DDmay be supplied by a linear regulator or sourced by a filtered G1V_DD. Systems

may design in both options to allow flexibility to address system noise dependencies.

However, for initial system bring-up, the linear regulator option is highly recommended.

An example solution for X1V_DDfiltering, where X1V_DDis sourced from a linear

regulator, is illustrated in Figure 77. The component values in this example filter are

system dependent and are still under characterization, component values may need

adjustment based on the system or environment noise.

Where:

• C1 = 0.003 μF 10%, X5R, with ESL ≤ 0.5 nH

• C2 and C3 = 2.2 μF 10%, X5R, with ESL ≤ 0.5 nH

• F1 and F2 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata

BLM18PG121SH1)

• Bulk and decoupling capacitors are added, as needed, per power supply design.

F1

F2

Bulk and

decoupling

capacitors

X1V_DD

Linear regulator

output

C1

C2

C3

GND

Figure 77. X1V_DDpower supply filter circuit

Note the following:

• See Power-on ramp rate for maximum X1V_DDpower-up ramp rate.

• There needs to be enough output capacitance or a soft-start feature to assure ramp

rate requirement is met.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

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173

Hardware design considerations

• The ferrite beads should be placed in parallel to reduce voltage droop.

• Besides a linear regulator, a low-noise, dedicated switching regulator can be used. 10

mVp-p, 50 kHz - 500 MHz is the noise goal.

4.2.5 USB_HV_DDand USB_OV_DDpower supply filtering

USB_HV_DDand USB_OV_DDmust be sourced by a filtered 3.3 V and 1.8 V voltage

source using a star connection. An example solution for USB_HV_DDand USB_OV_DD

filtering, where USB_HV_DDand USB_OV_DDare sourced from a 3.3 V and 1.8 V voltage

source, is illustrated in the following figure. The component values in this example filter

is system dependent and are still under characterization, component values may need

adjustment based on the system or environment noise.

Where:

• C1 = 0.003 μF 10%, X5R, with ESL ≤ 0.5 nH

• C2 and C3 = 2.2 μF 10%, X5R, with ESL ≤ 0.5 nH

• F1 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata

BLM18PG121SH1)

• Bulk and decoupling capacitors are added, as needed, per power supply design.

Bulk and

decoupling

capacitors

F1

3.3 V or

1.8 V source

USB_HV_DDor

USB_OV_DD

C1

C2

C3

GND

Figure 78. USB_HV_DDand USB_OV_DDpower supply filter circuit

4.2.6 USB_SV_DDpower supply filtering

USB_SV_DDmust be sourced by a filtered V_DDor V_DDCusing a star connection. An

example solution for USB_SV_DDfiltering, where USB_SV_DDis sourced from V_DD, is

illustrated in the following figure. The component values in this example filter is system

dependent and are still under characterization, component values may need adjustment

based on the system or environment noise.

Where:

• C1 = 2.2 μF 20%, X5R, with Low ESL (for example, Panasonic ECJ0EB0J225M)

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

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Freescale Semiconductor, Inc.

Hardware design considerations

• F1 = 120 Ω at 100-MHz 2A 25% Ferrite (for example, Murata BLM18PG121SH1)

• Bulk and decoupling capacitors are added, as needed, per power supply design.

F1

Bu^Bulk^{lk a}aⁿn^dd

USB_SV_DD

de^dc^eco^ou^upp^lilⁿi^gng

V^DD/ VDDC

ca^cp^apa^ac^cii^toto^rsrs

C1

GND

Figure 79. USB_SV_DDpower supply filter circuit

4.3 Decoupling recommendations

Due to large address and data buses, and high operating frequencies, the device can

generate transient power surges and high frequency noise in its power supply, especially

while driving large capacitive loads. This noise must be prevented from reaching other

components in the chip system, and the chip itself requires a clean, tightly regulated

source of power. Therefore, it is recommended that the system designer place at least one

decoupling capacitor at each V_DD, V_DDC, CV_DD, OnV_DD, DV_DD, EV_DD, GnV_DD, and

LnV_DDpin of the device. These decoupling capacitors should receive their power from

separate V_DD, CV_DD, OnV_DD, DV_DD, EV_DD, GnV_DD, LnV_DD, and GND power planes in

the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly

under the device using a standard escape pattern. Others may surround the part.

These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount

technology) capacitors should be used to minimize lead inductance, preferably 0402 or

0201 sizes.

As presented in Core and platform supply voltage filtering, it is recommended that there

be several bulk storage capacitors distributed around the PCB, feeding the V_DD, V_DDC

and other planes (for example, CV_DD, OnV_DD, DV_DD, EV_DD, GnV_DD, and LnV_DD), to

enable quick recharging of the smaller chip capacitors.

4.4 SerDes block power supply decoupling recommendations

The SerDes block requires a clean, tightly regulated source of power (S1V_DDand

X1V_DD) to ensure low jitter on transmit and reliable recovery of data in the receiver. An

appropriate decoupling scheme is outlined below.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

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175

Hardware design considerations

NOTE

Only SMT capacitors should be used to minimize inductance.

Connections from all capacitors to power and ground should be

done with multiple vias to further reduce inductance.

1. The board should have at least 1 x 0.1-uF SMT ceramic chip capacitor placed as

close as possible to each supply ball of the device. Where the board has blind vias,

these capacitors should be placed directly below the chip supply and ground

connections. Where the board does not have blind vias, these capacitors should be

placed in a ring around the device as close to the supply and ground connections as

possible.

2. Between the device and any SerDes voltage regulator there should be a lower bulk

capacitor for example a 10-uF, low ESR SMT tantalum or ceramic and a higher bulk

capacitor for example a 100uF - 300-uF low ESR SMT tantalum or ceramic

capacitor.

4.5 Connection recommendations

The following is a list of connection recommendations:

• To ensure reliable operation, it is highly recommended to connect unused inputs to

an appropriate signal level. Unless otherwise noted in this document, all unused

active low inputs should be tied to V_DD, OnV_DD, DV_DD, GnV_DD, EV_DD, CV_DDand

LnV_DDas required. All unused active high inputs should be connected to GND. All

NC (no-connect) signals must remain unconnected. Power and ground connections

must be made to all external V_DD, OnV_DD, DV_DD, GnV_DD, LnV_DD, EV_DD, CV_DD

and GND pins of the device.

• The TEST_SEL_B pin must be pulled to O1V_DDthrough a 100-ohm to 1k-ohm

resistor for T1042 and tied to ground for 2 core T1022.

• The chip has temperature diodes on the microprocessor that can be used in

conjunction with other system temperature monitoring devices (such as Analog

Devices, ADT7461A^™). If a temperature diode monitoring device is not connected,

these pins may be connected to test points or grounded.

4.5.1 Legacy JTAG configuration signals

Correct operation of the JTAG interface requires configuration of a group of system

control pins as demonstrated in Figure 81. Care must be taken to ensure that these pins

are maintained at a valid deasserted state under normal operating conditions as most have

asynchronous behavior and spurious assertion will give unpredictable results.

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Freescale Semiconductor, Inc.

Hardware design considerations

Boundary-scan testing is enabled through the JTAG interface signals. The TRST_B

signal is optional in the IEEE Std 1149.1 specification, but it is provided on all processors

built on Power Architecture technology. The device requires TRST_B to be asserted

during power-on reset flow to ensure that the JTAG boundary logic does not interfere

with normal chip operation. While the TAP controller can be forced to the reset state

using only the TCK and TMS signals, generally systems assert TRST_B during the

power-on reset flow. Simply tying TRST_B to PORESET_B is not practical because the

JTAG interface is also used for accessing the common on-chip processor (COP), which

implements the debug interface to the chip.

The COP function of these processors allow a remote computer system (typically, a PC

with dedicated hardware and debugging software) to access and control the internal

operations of the processor. The COP interface connects primarily through the JTAG port

of the processor, with some additional status monitoring signals. The COP port requires

the ability to independently assert PORESET_B or TRST_B in order to fully control the

processor. If the target system has independent reset sources, such as voltage monitors,

watchdog timers, power supply failures, or push-button switches, then the COP reset

signals must be merged into these signals with logic.

The arrangement shown in Figure 81 allows the COP port to independently assert

PORESET_B or TRST_B, while ensuring that the target can drive PORESET_B as well.

The COP interface has a standard header, shown in Figure 80, for connection to the target

system, and is based on the 0.025" square-post, 0.100" centered header assembly (often

called a Berg header). The connector typically has pin 14 removed as a connector key.

The COP header adds many benefits such as breakpoints, watchpoints, register and

memory examination/modification, and other standard debugger features. An inexpensive

option can be to leave the COP header unpopulated until needed.

There is no standardized way to number the COP header; so emulator vendors have

issued many different pin numbering schemes. Some COP headers are numbered top-to-

bottom then left-to-right, while others use left-to-right then top-to-bottom. Still others

number the pins counter-clockwise from pin 1 (as with an IC). Regardless of the

numbering scheme, the signal placement recommended in Figure 80 is common to all

known emulators.

4.5.1.1 Termination of unused signals

If the JTAG interface and COP header will not be used, Freescale recommends the

following connections:

• TRST_B should be tied to PORESET_B through a 0 kΩ isolation resistor so that it is

asserted when the system reset signal (PORESET_B) is asserted, ensuring that the

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

177

Hardware design considerations

JTAG scan chain is initialized during the power-on reset flow. Freescale

recommends that the COP header be designed into the system as shown in Figure 81.

If this is not possible, the isolation resistor will allow future access to TRST_B in

case a JTAG interface may need to be wired onto the system in future debug

situations.

• No pull-up/pull-down is required for TDI, TMS or TDO.

1

3

2

4

NC

COP_TDO

COP_TDI

COP_TRST_B

COP_VDD_SENSE

COP_CHKSTP_IN_B

NC

5

6

COP_TCK

7

8

COP_TMS

9

10

12

COP_SRESET_B

COP_HRESET_B

COP_CHKSTP_OUT_B

11

13

15

NC

KEY

No pin

16

GND

Figure 80. Legacy COP Connector Physical Pinout

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

178

Freescale Semiconductor, Inc.

Hardware design considerations

OV_DD

1 kΩ

10 kΩ

From target

board sources

(if any)

HRESET_B

7

HRESET_B⁶

PORESET_B

10 kΩ

PORESET_B¹

COP_HRESET_B

COP_SRESET_B

13

11

10 kΩ

B

A

10 kΩ

5

1

3

2

4

5

6

COP_TRST_B

TRST_B¹

4

6

5

10 Ω

7

8

COP_VDD_SENSE²

9

10

12

NC

COP_CHKSTP_OUT_B

15

11

13

15

CKSTP_OUT_B

KEY

No pin

14³

10 kΩ

16

COP_CHKSTP_IN_B

COP_TMS

8

9

System logic

COP connector

physical pinout

TMS

TDO

TDI

COP_TDO

1

COP_TDI

3

COP_TCK

TCK

7

2

NC

10 kΩ

10

4

12

16

Notes:

1. The COP port and target board should be able to independently assert PORESET_B and TRST_B to the processor in

order to fully control the processor as shown here.

2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.

3. The KEY location (pin 14) is not physically present on the COP header.

4. Although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity.

5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally

asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to position B.

6. Asserting HRESET_B causes a hard reset on the device

7. This is an open-drain output gate.

Figure 81. Legacy JTAG Interface Connection

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

179

Hardware design considerations

4.5.2 Aurora configuration signals

Correct operation of the Aurora interface requires configuration of a group of system

control pins as demonstrated in the figures below. Care must be taken to ensure that these

pins are maintained at a valid deasserted state under normal operating conditions as most

have asynchronous behavior and spurious assertion will give unpredictable results.

Freescale recommends that the Aurora 34 pin duplex connector be designed into the

system as shown in Figure 84 or the 70 pin duplex connector be designed into the system

as shown in Figure 85.

If the Aurora interface will not be used, Freescale recommends the legacy COP header be

designed into the system as described in .

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

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Freescale Semiconductor, Inc.

Hardware design considerations

1

3

2

4

VIO (VSense)

TCK

TX0_P

TX0_N

GND

5

6

TMS

TDI

TX1_P

TX1_N

GND

7

8

9

10

12

14

TDO

11

13

TRST

Vendor I/O 0

Vendor I/O 1

Vendor I/O 2

Vendor I/O 3

RESET

RX0_P

RX0_N

GND

15

17

16

18

19

21

23

25

27

29

31

33

20

22

24

26

28

30

32

34

RX1_P

RX1_N

GND

CLK_P

TX2_P

TX2_N

GND

CLK_N

GND

Vendor I/O 4

Vendor I/O 5

TX3_P

TX3_N

Figure 82. Aurora 34 pin connector duplex pinout

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

181

Hardware design considerations

1

3

2

4

VIO (VSense)

TCK

TX0_P

TX0_N

GND

5

6

TMS

TDI

TX1_P

TX1_N

GND

7

8

9

10

12

14

TDO

11

13

TRST

Vendor I/O 0

Vendor I/O 1

Vendor I/O 2

Vendor I/O 3

RESET

RX0_P

RX0_N

GND

15

17

16

18

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

RX1_P

RX1_N

GND

CLK_P

TX2_P

TX2_N

GND

CLK_N

GND

Vendor I/O 4

Vendor I/O 5

GND

TX3_P

TX3_N

GND

RX2_P

N/C

RX2_N

GND

N/C

GND

RX3_P

RX3_N

GND

N/C

GND

N/C

GND

N/C

GND

N/C

GND

N/C

TX4_P

TX4_N

GND

49

51

50

52

53

55

57

59

61

63

65

67

69

54

56

58

60

62

64

66

68

70

TX5_P

TX5_N

GND

TX6_P

TX6_N

GND

TX7_P

TX7_N

Figure 83. Aurora 70 pin connector duplex pinout

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

182

Freescale Semiconductor, Inc.

Hardware design considerations

OV_DD

1 kΩ

10 kΩ

HRESET_B

From target

board sources

(if any)

5

HRESET_B⁴

PORESET_B

10 kΩ

PORESET_B¹

RESET

22

20, 25

27, 31

32, 33

NC

B

A

1

2

4

3

10 kΩ

3

5

6

7

8

9

10

12

14

11

13

15

17

19

21

23

25

27

29

31

33

AURORA_TRST_B

TRST_B¹

16

18

20

22

24

26

28

30

32

34

12

2

VIO VSense²

1 kΩ

AURORA_TMS

AURORA_TDO

AURORA_TDI

AURORA_TCK

6

TMS

TDO

TDI

10

8

4

TCK

Vendor I/O 5 (Aurora_HRESET_B)

Vendor I/O 2 (Aurora_Event_Out_B)

Vendor I/O 1 (Aurora_Event_In_B)

Vendor I/O 0 (Aurora_HALT_B)

34

18

16

10 kΩ

EVT[4]

EVT[1]

14

26

EVT[0]

Duplex 34 Connector

Physical Pinout

CLK_P

CLK_N

TX0_P

100 nF

SD1_REF_CLKn_P

SD1_REF_CLKn_N

28

1

SD1_TX4_P

SD1_TX4_N

TX0_N

TX1_P

3

7

TX1_N

RX0_P

RX0_N

RX1_P

RX1_N

9

0.01 uF

13

15

19

SD1_RX4_P

SD1_RX4_N

21

5, 11, 17

6

23, 24

29, 30

REF_CLK1_P

REF_CLK1_N

REF_CLK_P

REF_CLK_N

Notes:

1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor in

order to fully control the processor as shown here.

2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.

3. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally

asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to position B.

4. Asserting HRESET_B causes a hard reset on the device.

5. This is an open-drain output gate.

6. REF_CLK_P/REF_CLK_N and REF_CLK1_P/REFCLK1_N are buffered clocks from the same common source.

7. RX1_P/RX1_N and TX1_P/TX1_N can be left floating at Aurora Header

Figure 84. Aurora 34 pin connector duplex interface connection

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

183

Hardware design considerations

1 kΩ

OV_DD

10 kΩ

From target

board sources

(if any)

HRESET_B

5

HRESET_B⁴

PORESET_B¹

PORESET_B

10 kΩ

1

3

2

4

Reset

22

5

6

20, 25, 27, 31,

32, 33, 37, 38,

39, 40, 43, 44,

45, 46, 49, 50,

51, 52, 55, 56,

57, 58, 61, 62,

63, 64, 67, 68,

69, 70

7

8

9

10

12

14

B

11

13

A

NC

3

15

17

16

18

10 kΩ

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

AURORA_TRST_B

TRST_B¹

12

VIO VSense²

2

6

AURORA_TMS

AURORA_TDO

AURORA_TDI

AURORA_TCK

1 kΩ

TMS

TDO

TDI

10

8

4

TCK

Vendor I/O 5 (Aurora_HRESET_B)

34

26

CLK_P

100 nF

10 kΩ

SD1_REF_CLKn_P

SD1_REF_CLKn_N

CLK_N

28

Vendor I/O 2 (Aurora_Event_Out_B)

Vendor I/O 1 (Aurora_Event_In_B)

Vendor I/O 0 (Aurora_HALT_B)

TX0_P

18

16

14

1

EVT[4]

49

51

50

52

EVT[1]

EVT[0]

53

55

57

59

61

63

65

67

69

54

56

58

60

62

64

66

68

70

SD1_TX4_P

SD1_TX4_N

TX0_N

TX1_P

3

7

9

7

TX1_N

RX0_P

RX0_N

RX1_P

0.01 uF

SD1_RX4_P

SD1_RX4_N

13

15

19

7

RX1_N

21

6

Duplex 70 Connector

Physical Pinout

6

5, 11, 17, 23, 24,

29, 30, 35, 36, 41,

42, 47, 48, 53, 54,

59, 60, 65, 66

REF_CLK1_P

REF_CLK1_N

REF_CLK_P

REF_CLK_N

Notes:

1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor in

order to fully control the processor as shown here.

2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.

3. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally

asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to position B.

4. Asserting HRESET_B causes a hard reset on the device

5. This is an open-drain output gate.

6. REF_CLK_P/REF_CLK_N and REF_CLK1_P/REFCLK1_N are buffered clocks from the same common source.

7. RX1_P/RX1_N and TX1_P/TX1_N can be left floating at Aurora Header

Figure 85. Aurora 70 pin connector duplex interface connection

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

184

Freescale Semiconductor, Inc.

Hardware design considerations

4.5.3 Guidelines for high-speed interface termination

4.5.3.1 SerDes interface entirely unused

If the high-speed SerDes interface is not used at all, the unused pin should be terminated

as described in this section.

Note that S1V_DD, X1V_DDand AVDD_SD1_PLL1 must remain powered.

For AVDD_SD1_PLL1, it must be connected to X1V_DDthrough a zero ohm resistor

(instead of filter circuit shown in Figure 75).

The following pins must be left unconnected:

• SD1_TX[7:0]_P

• SD1_TX[7:0]_N

• SD1_IMP_CAL_RX

• SD1_IMP_CAL_TX

The following pins must be connected to S1GND:

• SD1_REF_CLK1_P, SD1_REF_CLK2_P

• SD1_REF_CLK1_N, SD1_REF_CLK2_N

It is recommended for the following pins to be connected to S1GND:

• SD1_RX[7:0]_P

• SD1_RX[7:0]_N

It is possible to disable SerDes module by disabling all PLLs associated with it.

SerDes is disabled as follows:

• SRDS_PLL_PD_S1 = 2’b11 (both PLLs configured as powered down, all data lanes

selected by the protocols defined in SRDS_PRTCL_S1 associated to the PLLs are

powered down as well)

• SRDS_PLL_REF_CLK_SEL_S1 = 2’b00

• SRDS_PRTCL_S1 = 2 (no other values permitted when both PLLs are powered

down

4.5.3.2 SerDes interface partly unused

If only part of the high speed SerDes interface pins are used, the remaining high-speed

serial I/O pins should be terminated as described in this section.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

185

Hardware design considerations

Note that both S1V_DDand X1V_DDmust remain powered.

If any of the PLLs are un-used, the corresponding AVDD_SD1_PLL1 must be connected

to X1V_DDthrough a zero ohm resistor (instead of filter circuit shown in Figure 75).

The following unused pins must be left unconnected:

• SD1_TX[7:0]_P

• SD1_TX[7:0]_N

The following unused pins must be connected to S1GND:

• SD1_REF_CLK[1:2]_P, SD1_REF_CLK[1:2]_N (If entire SerDes unused)

It is recommended for the following unused pins to be connected to S1GND:

• SD1_RX[7:0]_P

• SD1_RX[7:0]_N

In the RCW configuration field SRDS_PLL_PD_S1, the respective bits for each unused

PLL must be set to power it down. A module is disabled when both its PLLs are turned

off.

Unused lanes must be powered down through the SRDSx Lane m General Control

Register 0 (SRDSxLNmGCR0) as follows:

• SRDSxLNmGCR0[RRST] = 0

• SRDSxLNmGCR0[TRST] = 0

• SRDSxLNmGCR0[RX_PD] = 1

• SRDSxLNmGCR0[TX_PD] = 1

Note that in the case where the SerDes pins are connected to slots , it is acceptable to

have these pins unterminated when unused.

4.5.4 USB controller connections

This section details the hardware connections required for the USB controllers.

4.5.4.1 USB divider network

This figure shows the required divider network for the VBUS interface for the chip.

Additional requirements for the external components are:

• Both resistors require 1% accuracy and a current capability of up to 1 mA. They must

both have the same temperature coefficient and accuracy.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

186

Freescale Semiconductor, Inc.

Hardware design considerations

• The zener diode must have a value of 5 V−5.25 V.

• The 0.6 V diode requires an I_F= 10 mA, I_R< 500 nA and V_F(Max)= 0.8 V. If the

USB PHY does not support OTG mode, this diode can be removed from the

schematic or made a DNP component.

USBn_DRVVBUS

VBUS charge

pump

VBUS

(USB connector)

USBn_PWRFAULT

51.2 k Ω

0.6 V_F

5 V_Z

USBn_VBUSCLMP

18.1 k Ω

Chip

Figure 86. Divider network at VBUS

4.6 Thermal

This table shows the thermal characteristics for the chip. Note that these numbers are

based on design estimates and are preliminary.

Table 141. Package thermal characteristics⁶

Rating

Junction to ambient, natural convection

Junction to ambient (at 200 ft./min.)

Junction to board

Board

Symbol

Value

28

Unit

°C/W

Notes

1, 2

Single-layer board (1s) R_ΘJA

Four-layer board (2s2p) R_ΘJA

Single-layer board (1s) R_ΘJMA

Four-layer board (2s2p) R_ΘJMA

19

22

15

9

°C/W

1, 3

1, 2

3

-

R_ΘJB

Junction to case top

R_ΘJCtop

<0.1

4

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-3 and JESD51-6 with the board (JESD51-9) horizontal.

3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

4. Junction-to-case-top at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature

is used for the case temperature. Reported value includes the thermal resistance of the interface layer.

5. See Thermal management information, for additional details.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

187

Hardware design considerations

This table provides the thermal resistance with heat sink in open flow

Table 142. Thermal Resistance with Heat Sink in Open Flow

Heat Sink with Thermal Grease

Air Flow

Thermal

Resistance(°C/

W)

53 x 53 x 25 mm Pin Fin

Natural Convection

0.5 m/s

6.6

3.9

2.9

2.5

2.2

8.7

5.0

4.2

3.6

3.1

12.1

8.2

6.4

5.0

4.1

8.9

5.4

4.2

3.3

2.7

1 m/s

2 m/s

4 m/s

35x31x23 mm Pin Fin

30x30x9.4 mm Pin Fin

43x41x16.5 mm Pin Fin

Natural Convection

0.5 m/s

1 m/s

2 m/s

4 m/s

Natural Convection

0.5 m/s

1 m/s

2 m/s

4 m/s

Natural Convection

0.5 m/s

1 m/s

2 m/s

4 m/s

1. Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. The thermal interface

material was a typical thermal grease such as Dow Corning 340 or Wakefield 120 grease.

2. Simulation details:

• Substrate metal thicknesses: 0.015, 0.025 mm

• Substrate core thickness: 0.4 mm

4.7 Recommended thermal model

Information about Flotherm models of the package or thermal data not available in this

document can be obtained from your local Freescale sales office.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

188

Freescale Semiconductor, Inc.

Hardware design considerations

4.8 Temperature diode

The chip has a temperature diode on the microprocessor that can be used in conjunction

with other system temperature monitoring devices (such as Analog Devices,

ADT7461A). These devices feature series resistance cancellation using 3 current

measurements, where up to 1.5kΩ of resistance can be automatically cancelled from the

temperature result, allowing noise filtering and a more accurate reading.

The following are the specifications of the chip's on-board temperature diode:

Operating range: 10 - 230μA

Ideality factor over 13.5 - 220 μA; Temperature range 80°C - 105°C: n = 1.004 0.008

4.9 Thermal management information

This section provides thermal management information for the flip-chip, plastic-ball, grid

array (FC-PBGA) package for air-cooled applications. Proper thermal control design is

primarily dependent on the system-level design-the heat sink, airflow, and thermal

interface material.

The recommended attachment method to the heat sink is illustrated in Figure 87. The heat

sink should be attached to the printed-circuit board with the spring force centered over

the die. This spring force should not exceed 15 pounds force (65 Newton).

FC-PBGA package (no lid)

Heat sink

Heat sink clip

Adhesive or

thermal interface material

Die

Printed circuit-board

Figure 87. Package exploded, cross-sectional view-FC-PBGA (no lid)

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

189

Hardware design considerations

The system board designer can choose between several types of heat sinks to place on the

device. There are several commercially-available thermal interfaces to choose from in the

industry. Ultimately, the final selection of an appropriate heat sink depends on many

factors, such as thermal performance at a given air velocity, spatial volume, mass,

attachment method, assembly, and cost.

For additional information regarding thermal management of lid-less flip-chip packages,

refer to application note AN4871, "Assembly Handling and Thermal Solutions for

Lidless Flip Chip Ball Grid Array Packages"

4.9.1 Internal package conduction resistance

For the package, the intrinsic internal conduction thermal resistance paths are as follows:

• The die junction-to-case thermal resistance

• The die junction-to-board thermal resistance

This figure depicts the primary heat transfer path for a package with an attached heat sink

mounted to a printed-circuit board.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

190

Freescale Semiconductor, Inc.

Hardware design considerations

External resistance

Radiation Convection

Heat sink

Thermal interface material

Die/Package

Die junction

Internal resistance

Package/Solder balls

Printed-circuit board

External resistance

(Note the internal versus external package resistance)

Radiation Convection

Figure 88. Package with heat sink mounted to a printed-circuit board

The heat sink removes most of the heat from the device. Heat generated on the active side

of the chip is conducted through the silicon and through the heat sink attach material (or

thermal interface material), and finally to the heat sink. The junction-to-case thermal

resistance is low enough that the heat sink attach material and heat sink thermal

resistance are the dominant terms.

4.9.2 Thermal interface materials

A thermal interface material is required at the package-to-heat sink interface to minimize

the thermal contact resistance. The performance of thermal interface materials improves

with increasing contact pressure; this performance characteristic chart is generally

provided by the thermal interface vendor. The recommended method of mounting heat

sinks on the package is by means of a spring clip attachment to the printed-circuit board

(see Figure 87).

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

191

Package information

The system board designer can choose among several types of commercially-available

thermal interface materials.

5 Package information

5.1 Package parameters for the FC-PBGA

The package parameters are as provided in the following list. The package type is 23 mm

x 23 mm, 780 flip-chip, plastic-ball, grid array (FC-PBGA).

• Package outline - 23 mm x 23 mm

• Interconnects - 780

• Ball Pitch - 0.8 mm

• Ball Diameter (typical) - 0.45 mm

• Solder Balls - 96.5% Sn, 3% Ag, 0.5% Cu

• Module height - 1.77 mm (minimum), 1.92 mm (typical), 2.07 mm (maximum)

5.2 Mechanical dimensions of the FC-PBGA

This figure shows the mechanical dimensions and bottom surface nomenclature of the

chip.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

192

Freescale Semiconductor, Inc.

Package information

2X

0.2

B

23

0.2

780X

A

D

A1 INDEX AREA

C

A

SEATING

PLANE

5

0.2

4

23

0.2

2X

TOP VIEW

D

2X 21.6

27 X 0.8

3MM MAX

UNDERFILL

FROM DIE

EDGE ON

ALL SIDES

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

27X 0.8

R

P

N

M

L

K

J

H

G

F

0.3 + 0.1

0.77

E

D

C

B

A

3

1.62

780X

0.45 +0.05

Ø

0.15

0.08

A

B

C

Ø

M

1.92 + 0.15

ɸ

Ø

1

3

5

7

9 11 13 15 17 19 21 23 25 27

8 10 12 14 16 18 20 22 24 26 28

2

4

6

SOLDER BALLS

VIEW D - D

A1 INDEX AREA

BOTTOM VIEW

NOTES:

1. ALL DIMENSIONS IN MILLIMETERS.

2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M- 1994.

3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.

4. DATUM A, THE SEATING PLANE, IS DETERMINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.

5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE.

Figure 89. Mechanical dimensions of the FC-PBGA

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

193

Security fuse processor

6 Security fuse processor

This chip implements the QorIQ platform's Trust Architecture, supporting capabilities

such as secure boot. Use of the Trust Architecture features is dependent on programming

fuses in the Security Fuse Processor (SFP). The details of the Trust Architecture and SFP

can be found in the chip reference manual.

To program SFP fuses, the user is required to supply 1.8 V to the PROG_SFP pin per

Power sequencing. PROG_SFP should only be powered for the duration of the fuse

programming cycle, with a per device limit of two fuse programming cycles. All other

times PROG_SFP should be connected to GND. The sequencing requirements for raising

and lowering PROG_SFP are shown in Figure 10. To ensure device reliability, fuse

programming must be performed within the recommended fuse programming

temperature range per Table 3.

NOTE

Users not implementing the QorIQ platform's Trust

Architecture features should connect PROG_SFP to GND.

7 Ordering information

Contact your local Freescale sales office or regional marketing team for order

information.

7.1 Part numbering nomenclature

This table provides the Freescale QorIQ platform part numbering nomenclature.

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

194

Freescale Semiconductor, Inc.

Ordering information

Table 143. Part numbering nomenclature

pt or t

n

nn

n

x

t

e

n

c

d

r

PT =

28nm

(Prototype

)

1

04 = 4

cores

2 = First P =

S =

E = SEC 7 = FC- M = 1200

Q= 1600

MT/s

A =

Rev 1.0

product

Prototype Standard

present

PBGA MHz

C4 Pb-

temp

02 = 2

cores

N =

N = SEC

not

P = 1400

B =

Rev 1.1

free

Qualified X =

MHz

T = 28nm

(Productio

n)

to

Extended

present

W = 1500

MHz

industrial temp

tier

7.2 Part marking

Parts are marked as in the example shown in this figure.

T1042

xtencdr

ATWLYYWW

CCCCC

MMMMM

YWWLAZ

FC-PBGA

Legend:

T1042xtencdr is the orderable part number.

ATWLYYWW is the test traceability code.

MMMMM is the mask number.

CCCCC is the country code.

YWWLAZ is the assembly traceability code.

Figure 90. Part marking for FC-PBGA chip

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

Freescale Semiconductor, Inc.

195

Revision history

8 Revision history

This table summarizes revisions to this document.

Table 144. Revision history

Revision

Date

Description

2

06/2015

• Updated side view substrate thickness to 0.77 reference dimension and overall thickness

tolerance to 0.15 in Figure 89

• Updated "this table" with the table reference name in Spread-spectrum sources

• Updated Module height parameters in Package parameters for the FC-PBGA

• Added 1500MHz part information in Part numbering nomenclature

• Added 1500MHz Core frequency typical, thermal, maximum and low power mode power

numbers in Power characteristics

• Added 1500MHz bin information to Table 129

• Added 1500MHz core frequency ratios to Table 137

1

0

03/2015

01/2015

• Part marking

• Updated Figure 90

• Updated platform activity factor in note 2, 4 and 5 below tables in Power characteristics

• Updated USB_HVDD, and USB_OVDD power numbers and added power numbers for

PROG_SFP and TH_VDD in I/O DC power supply recommendation

• Added 2.5 V DC electrical characteristic for MII in MII DC electrical characteristics

• Added Note 10 to PLL supply volatges in Absolute maximum ratings

• Initial public release

QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015

196

Freescale Semiconductor, Inc.

Information in this document is provided solely to enable system and

software implementers to use Freescale products. There are no express

or implied copyright licenses granted hereunder to design or fabricate

any integrated circuits based on the information in this document.

Freescale reserves the right to make changes without further notice to

any products herein.

How to Reach Us:

Home Page:

freescale.com

Web Support:

freescale.com/support

Freescale makes no warranty, representation, or guarantee regarding

the suitability of its products for any particular purpose, nor does

Freescale assume any liability arising out of the application or use of

any product or circuit, and specifically disclaims any and all liability,

including without limitation consequential or incidental damages.

“Typical” parameters that may be provided in Freescale data sheets

and/or specifications can and do vary in different applications, and

actual performance may vary over time. All operating parameters,

including “typicals,” must be validated for each customer application by

customer's technical experts. Freescale does not convey any license

under its patent rights nor the rights of others. Freescale sells products

pursuant to standard terms and conditions of sale, which can be found

at the following address: freescale.com/SalesTermsandConditions.

Freescale, the Freescale logo, and QorIQ are trademarks of Freescale

Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. CoreNet is a trademark

of Freescale Semiconductor, Inc. All other product or service names are

the property of their respective owners. The Power Architecture and

Power.org word marks and the Power and Power.org logos and related

marks are trademarks and service marks licensed by Power.org.

Document Number T1042

Revision 2, 06/2015


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描述：	RISC Microprocessor 外围集成电路
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