935313605557 [NXP]
RISC Microprocessor;型号: | 935313605557 |
厂家: | NXP |
描述: | RISC Microprocessor |
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中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MCF5208EC
Rev. 3, 9/2009
Freescale Semiconductor
Data Sheet: Technical Data
MCF5208 ColdFire®
Microprocessor Data Sheet
Supports MCF5207 & MCF5208
by: Microcontroller Solutions Group
Table of Contents
The MCF5207 and MCF5208 devices are
1
2
3
4
5
6
MCF5207/8 Device Configurations......................2
Ordering Information ...........................................2
Signal Descriptions..............................................3
Mechanicals and Pinouts ....................................8
Electrical Characteristics...................................17
Revision History ................................................43
highly-integrated, 32-bit microprocessors based on the
version 2 ColdFire microarchitecture. Both devices
contain a 16-Kbyte internal SRAM, an 8-Kbyte
configurable cache, a 2-bank SDR/DDR SDRAM
controller, a 16-channel DMA controller, up to three
UARTs, a queued SPI, a low-power management
modeule, and other peripherals that enable the MCF5207
and MCF5208 for use in industrial control and
connectivity applications. The MCF5208 device also
features a 10/100 Mbps fast ethernet controller.
This document provides detailed information on power
considerations, DC/AC electrical characteristics, and AC
timing specifications of the MCF5207 and MCF5208
microprocessors. It was written from the perspective of
the MCF5208 device. See the following section for a
summary of differences between the two devices.
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
MCF5207/8 Device Configurations
1 MCF5207/8 Device Configurations
The following table compares the two devices described in this document:
Table 1. MCF5207 & MCF5208 Configurations
Module
MCF5207
MCF5208
Version 2 ColdFire Core with EMAC
(Enhanced Multiply-Accumulate Unit)
•
•
Core (System) Clock
up to 166.67 MHz
Peripheral and External Bus Clock
up to 83.33 MHz
(Core clock ÷ 2)
Performance (Dhrystone/2.1 MIPS)
Instruction/Data Cache
Static RAM (SRAM)
up to 159
8 Kbytes
16 Kbytes
SDR/DDR SDRAM Controller
Fast Ethernet Controller (FEC)
Low-Power Management Module
UARTs
•
•
•
—
•
•
3
•
3
•
I2C
QSPI
•
•
32-bit DMA Timers
4
•
4
•
Watchdog Timer (WDT)
Periodic Interrupt Timers (PIT)
Edge Port Module (EPORT)
Interrupt Controllers (INTC)
16-channel Direct Memory Access (DMA)
FlexBus External Interface
General Purpose I/O Module (GPIO)
JTAG - IEEE® 1149.1 Test Access Port
Package
4
•
4
•
1
•
1
•
•
•
•
•
•
•
144 LQFP
160 QFP
144 MAPBGA
196 MAPBGA
2 Ordering Information
Table 2. Orderable Part Numbers
Freescale Part
Number
Description
Speed
Temperature
MCF5207CAG166
MCF5207CVM166
MCF5208CAB166
MCF5208CVM166
MCF5207 RISC Microprocessor, 144 LQFP
MCF5207 RISC Microprocessor, 144 MAPBGA
MCF5208 RISC Microprocessor, 160 QFP
MCF5208 RISC Microprocessor, 196 MAPBGA
166.67 MHz
166.67 MHz
166.67 MHz
166.67 MHz
–40° to +85° C
–40° to +85° C
–40° to +85° C
–40° to +85° C
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
2
Freescale Semiconductor
Signal Descriptions
3 Signal Descriptions
The following table lists all the MCF5208 pins grouped by function. The Dir column is the direction for
the primary function of the pin only. Refer to Section 4, “Mechanicals and Pinouts” for package diagrams.
For a more detailed discussion of the MCF5208 signals, consult the MCF5208 Reference Manual
(MCF5208RM).
NOTE
In this table and throughout this document, a single signal within a group is
designated without square brackets (i.e., A23), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO default to their GPIO functionality.
Table 3. MCF5207/8 Signal Information and Muxing
MCF5207
144
MCF5207
144
MCF5208
160
MCF5208
196
Signal Name
GPIO
Alternate 1
Alternate 2
LQFP
MAPBGA
QFP
MAPBGA
Reset
RESET2
RSTOUT
—
—
—
—
—
—
I
82
74
J10
90
82
J14
EVDD
EVDD
O
M12
N14
Clock
EVDD
EVDD
EXTAL
XTAL
—
—
—
—
—
—
—
—
—
I
78
80
34
K12
J12
L1
86
88
40
L14
K14
N1
O
O
SDVDD
FB_CLK
Mode Selection
RCON2
—
—
—
—
—
—
144
79
C4
160
87
C3
EVDD
I
EVDD
DRAMSEL
I
H10
K11
FlexBus
SDVDD
A[23:22]
A[21:16]
—
—
FB_CS[5:4]
—
—
—
O
O
118, 117
B9, A10
126, 125
B11, A11
SDVDD
116–114,
112, 108,
107
C9, A11,
B10, A12,
C11, B11
124, 123,
122, 120,
116, 115
B12, A12,
A13, B13,
B14, C13
SD_BA[1:0]3
SD_A[13:11]3
—
—
O
O
106, 105
104–102
B12, C12
114, 113
C14, D12
SDVDD
SDVDD
A[15:14]
A[13:11]
—
—
D11, E10,
D12
112, 111,
110
D13, D14,
E11
SDVDD
A10
—
—
—
O
101
C10
109
E12
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
3
Signal Descriptions
Table 3. MCF5207/8 Signal Information and Muxing (continued)
MCF5207
144
MCF5207
144
MCF5208
160
MCF5208
196
Signal Name
GPIO
Alternate 1
Alternate 2
LQFP
MAPBGA
QFP
MAPBGA
SDVDD
SDVDD
A[9:0]
—
SD_A[9:0]3
—
O
100–91
E11, D9,
E12, F10,
F11, E9,
F12, G10,
G12, F9
108–99
E13, E14,
F11–F14,
G11–G14
D[31:16]
D[15:0]
—
SD_D[31:16]4
FB_D[31:16]4
SD_DQM[3:0]3
—
—
—
I/O
21–28,
40–47
F1, F2, G1,
G2, G4, G3,
H1, H2, K3,
L2, L3, K2,
M3, J4, M4,
K4
27–34,
46–53
J4–J1,
K4–K1, M3,
N3, M4, N4,
P4, L5, M5,
N5
SDVDD
—
I/O
8–15, 51–58 B2, B1, C2,
C1, D2, D1,
E2, E1, L5,
16–23,
57–64
F3–F1,
G4–G1, H1,
N6, P6, L7,
M7, N7, P7,
N8, P8
K5, L6, J6,
M6, J7, L7,
K7
SDVDD
BE/BWE[3:0]
PBE[3:0]
O
20, 48, 18, F4, L4, E3, 26, 54, 24, H2, P5, H4,
50
60
90
59
4
J5
56
66
98
65
12
M6
M8
H14
L8
SDVDD
SDVDD
SDVDD
SDVDD
OE
TA2
R/W
TS
PBUSCTL3
PBUSCTL2
PBUSCTL1
PBUSCTL0
—
—
—
—
—
—
O
I
J8
G11
K6
—
O
O
DACK0
B3
E3
Chip Selects
SDVDD
FB_CS[3:2]
FB_CS1
PCS[3:2]
PCS1
—
—
SD_CS1
—
—
—
—
O
O
O
119, 120
121
D7, A9
C8
—
C11, A10
B10
SDVDD
SDVDD
127
128
FB_CS0
122
B8
C10
SDRAM Controller
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SD_A10
SD_CKE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
O
O
O
O
O
37
6
M1
C3
43
14
N2
E1
SD_CLK
31
32
7
J1
37
L1
SD_CLK
K1
38
M1
F4
SD_CS0
A1
15
SD_DQS[3:2]
SD_SCAS
SD_SRAS
SD_SDR_DQS
SD_WE
19, 49
38
39
29
5
F3, M5
M2
J2
25, 55
44
H3, L6
P2
45
P3
H3
35
L3
D3
13
E2
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
4
Freescale Semiconductor
Signal Descriptions
Table 3. MCF5207/8 Signal Information and Muxing (continued)
MCF5207
144
MCF5207
144
MCF5208
160
MCF5208
196
Signal Name
GPIO
Alternate 1
Alternate 2
LQFP
MAPBGA
QFP
MAPBGA
External Interrupts Port5
IRQ72
IRQ42
IRQ12
PIRQ72
PIRQ42
PIRQ12
—
DREQ02
—
—
—
—
I
I
I
134
133
132
A5
C6
B6
142
141
140
C7
D7
D8
EVDD
EVDD
EVDD
FEC
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
FEC_MDC
FEC_MDIO
FEC_TXCLK
—
PFECI2C3
PFECI2C2
PFECH7
PFECH6
PFECH6
PFECH5
PFECH4
PFECH3
PFECH2
PFECH1
PFECH0
I2C_SCL2
U2TXD
U2RXD
—
O
I/O
I
—
—
—
—
—
A2
—
—
—
—
—
—
—
—
D5
—
—
B4
—
E4
—
148
147
157
—
D6
C6
I2C_SDA2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B3
U1RTS
U1RTS
—
O
O
O
I
142
—
—
FEC_TXEN
FEC_TXD0
FEC_COL
FEC_RXCLK
FEC_RXDV
FEC_RXD0
FEC_CRS
158
3
A2
—
B1
—
—
7
D3
—
I
—
154
153
152
8
B4
—
I
—
A4
—
I
—
D5
—
I
—
D2
FEC_TXD[3:1] PFECL[7:5]
—
O
O
O
I
—
6–4
—
C1, C2, B2
—
—
PFECL4
PFECL4
U0RTS
U0RTS
—
141
—
FEC_TXER
156
149–150
—
A3
FEC_RXD[3:2] PFECL[3:2]
—
A5, B5
—
—
PFECL1
PFECL1
PFECL0
PFECL0
U1CTS
U1CTS
U0CTS
U0CTS
I
139
—
FEC_RXD1
—
I
151
—
C5
I
140
—
—
FEC_RXER
I
155
C4
Note: The MCF5207 does not contain an FEC module. However, the UART0 and UART1 control signals (as well as their GPIO signals)
are available by setting the appropriate FEC GPIO port registers.
I2C
I2C_SDA2
I2C_SCL2
PFECI2C02
PFECI2C12
U2RXD2
U2TXD2
—
—
I/O
I/O
—
—
—
—
—
—
D1
E4
EVDD
EVDD
DMA
DACK0 and DREQ0 do not have a dedicated bond pads. Please refer to the following pins for muxing:
TS and QSPI_CS2 for DACK0, IRQ4 and QSPI_DIN for DREQ0.
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
5
Signal Descriptions
Table 3. MCF5207/8 Signal Information and Muxing (continued)
MCF5207
144
MCF5207
144
MCF5208
160
MCF5208
196
Signal Name
GPIO
Alternate 1
Alternate 2
LQFP
MAPBGA
QFP
MAPBGA
QSPI
EVDD
EVDD
EVDD
EVDD
QSPI_CS2
QSPI_CLK
QSPI_DOUT
QSPI_DIN
PQSPI3
PQSPI0
PQSPI1
PQSPI2
DACK0
I2C_SCL2
I2C_SDA2
DREQ02
U2RTS
—
O
O
O
I
126
127
128
129
A8
C7
A7
B7
132
133
134
135
D10
A9
—
B9
U2CTS
C9
Note: The QSPI_CS1 and QSPI_CS0 signals are available on the U1CTS, U1RTS, U0CTS, or U0RTS pins for the 196 and 160-pin
packages.
UARTs
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
U1CTS
U1RTS
U1TXD
U1RXD
U0CTS
U0RTS
U0TXD
U0RXD
PUARTL7
PUARTL6
PUARTL5
PUARTL4
PUARTL3
PUARTL2
PUARTL1
PUARTL0
DT1IN
DT1OUT
—
QSPI_CS1
I
O
O
I
—
—
—
—
136
137
139
138
76
D9
C8
QSPI_CS1
—
131
130
—
A6
D6
—
A8
—
—
QSPI_CS0
QSPI_CS0
—
B8
DT0IN
DT0OUT
—
I
N12
P12
P13
N13
O
O
I
—
—
77
71
L10
M10
79
—
—
70
78
Note: The UART2 signals are multiplexed on the DMA Timers, QSPI, FEC, and I2C pins. For the MCF5207 devices, the UART0 and
UART1 control signals are multiplexed internally on the FEC signals.
DMA Timers
EVDD
EVDD
EVDD
EVDD
DT3IN
DT2IN
DT1IN
DT0IN
PTIMER3
PTIMER2
PTIMER1
PTIMER0
DT3OUT
DT2OUT
DT1OUT
DT0OUT
U2CTS
U2RTS
U2RXD
U2TXD
I
I
I
I
135
136
137
138
B5
C5
A4
A3
143
144
145
146
B7
A7
A6
B6
BDM/JTAG6
JTAG_EN7
DSCLK
PSTCLK
BKPT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
83
76
64
75
77
69
—
J11
K11
M7
91
84
70
83
85
75
—
J13
L12
P9
EVDD
TRST2
TCLK2
TMS2
TDI2
TDO
—
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
O
I
L12
H9
M14
K12
M12
DSI
I
DSO
O
O
M9
DDATA[3:0]
K9, L9, M11,
M8
P11, N11,
M11, P10
EVDD
PST[3:0]
—
—
—
O
—
L11, L8,
K10, K8
—
N10, M10,
L10, L9
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
6
Freescale Semiconductor
Signal Descriptions
Table 3. MCF5207/8 Signal Information and Muxing (continued)
MCF5207
144
MCF5207
144
MCF5208
160
MCF5208
196
Signal Name
GPIO
Alternate 1
Alternate 2
LQFP
MAPBGA
QFP
MAPBGA
EVDD
ALLPST
—
—
—
O
67
—
73
—
Test
TEST7
—
—
—
—
—
—
I
I
109
—
—
—
—
—
C12
M13
EVDD
EVDD
PLL_TEST
Power Supplies
EVDD
IVDD
—
—
—
—
—
—
—
—
1, 33, 63, 66, E5–E6, F5, 2, 9, 69, 72, E5–E7, F5,
72, 81, 87,
125
G8–G9,
H7–H8
80, 89, 95, F6, G5, H10,
131
J9, J10,
K8–K10,
K13, M9
—
—
30, 68, 84, D4, D8, H4, 36, 74, 92,
J12, D4,
D11, H11,
L4, L11,
113, 143
H11, J9
121, 159
PLL_VDD
SD_VDD
—
—
—
—
—
—
—
—
—
—
86
H12
94
H13
3, 17, 35, 61, E7–E8, F8, 11, 39, 41, E8–E10, F9,
89, 110, 123 G5, H5–H6, 67, 97, 118, F10, G10,
J3
129
H5, J5, J6,
K5–K7, L2
VSS
—
—
—
—
—
—
—
—
—
2, 16, 36, 62, D10, F6–F7, 1, 10, 42, 68,
A1, A14,
F7–F8,
G6–G9,
H6–H9,
J7–J8, L13,
M2, N9, P1,
P14
65, 73, 88,
111, 124
G6–G7
71, 81, 96,
117, 119,
130
PLL_VSS
—
85
—
93
H12
NOTES:
1
2
3
Refers to pin’s primary function.
Pull-up enabled internally on this signal for this mode.
The SDRAM functions of these signals are not programmable by the user. They are dynamically switched by the processor when
accessing SDRAM memory space and are included here for completeness.
Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating the
DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.
GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions.
If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning
these pins.
4
5
6
7
Pull-down enabled internally on this signal for this mode.
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
7
Mechanicals and Pinouts
4 Mechanicals and Pinouts
Drawings in this section show the pinout and the packaging and mechanical characteristics of the
MCF5207 and MCF5208 devices.
NOTE
The mechanical drawings are the latest revisions at the time of publication
of this document. The most up-to-date mechanical drawings can be found at
the product summary page located at http://www.freescale.com/coldfire.
4.1 Pinout—144 LQFP
Figure 1 shows a pinout of the MCF5207CAG166 device.
•
EVDD
EVSS
SD_VDD
TS
1
108
107
106
105
104
103
102
101
100
99
A17
2
A16
3
A15
4
A14
SD_WE
SD_CKE
SD_CS
D15
5
A13
6
A12
7
A11
8
A10
D14
9
A9
D13
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A8
D12
98
A7
D11
D10
97
A6
96
A5
D9
D8
95
A4
94
A3
EVSS
93
A2
SD_VDD
BE/BWE1
SD_DQS3
BE/BWE3
92
A1
91
A0
90
TA
89
SD_VDD
VSS
D31
D30
88
87
EVDD
PLL_VDD
PLL_VSS
IVDD
JTAG_EN
RESET
EVDD
XTAL
DRAMSEL
EXTAL
TDI/DSI
TRST/DSCLK
TMS/BKPT
RSTOUT
VSS
D29
86
D28
85
D27
84
D26
83
D25
82
D24
81
SD_SDR_DQS
IVDD
80
79
SD_CLK
SD_CLK
SD_VDD
FB_CLK
SD_VDD
VSS
78
77
76
75
74
73
Figure 1. MCF5207CAG166 Pinout Top View (144 LQFP)
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
8
Freescale Semiconductor
Mechanicals and Pinouts
4.2 Package Dimensions—144 LQFP
Figure 2 and Figure 3 show MCF5207CAB166 package dimensions.
Figure 2. MCF5207CAB166 Package Dimensions (Sheet 1 of 2)
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
9
Mechanicals and Pinouts
View A
Section A-A
Rotated 90× CW
144 Places
View B
Figure 3. MCF5207CAB166 Package Dimensions (Sheet 2 of 2)
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
10
Freescale Semiconductor
Mechanicals and Pinouts
4.3 Pinout—144 MAPBGA
The pinout of the MCF5207CVM166 device is shown below.
1
2
3
4
5
6
7
8
9
10
11
12
QSPI_
DOUT
A
B
C
D
E
F
SD_CS
U1RTS
DT0IN
DT1IN
IRQ7
U1TXD
QSPI_CS2 FB_CS2
A22
A20
A18
A
B
C
D
E
F
QSPI_
DIN
D14
D12
D15
D13
D11
D9
TS
U1CTS
RCON
IVDD
DT3IN
DT2IN
IRQ1
IRQ4
U1RXD
EVDD
VSS
FB_CS0
FB_CS1
IVDD
A23
A21
A19
A10
VSS
A12
A6
A16
A17
A15
A14
QSPI_
CLK
SD_CKE
SD_WE
BE/BWE1
D10
U0RTS
EVDD
FB_CS3
A8
A13
A11
D8
U0CTS
SD_VDD SD_VDD
A4
A9
A7
D31
D30
D28
D24
SD_DQS3 BE/BWE3
EVDD
VSS
VSS
EVDD
D2
SD_VDD
EVDD
EVDD
OE
A0
A5
A3
G
H
J
D29
D26
D27
IVDD
SD_VDD
VSS
EVDD
TDI/DSI
IVDD
DDATA3
DDATA2
A2
TA
A1
G
H
J
SD_SDR_
DQS
DRAM
SEL
D25
SD_VDD SD_VDD
IVDD
JTAG_EN
PLL_VDD
XTAL
EXTAL
SD_CLK
SD_CLK
FB_CLK
SD_RAS SD_VDD
D18
BE/BWE0
D6
D4
R/W
D5
RESET
PST1
TRST/
DSCLK
K
L
D20
D22
D23
D21
D16
D0
PST0
PST2
K
L
TMS/
BKPT
BE/BWE2
D7
D1
U0TXD
PST3
TCLK/
PSTCLK
M
SD_A10
1
SD_CAS
2
D19
3
D17
4
SD_DQS2
5
D3
6
DDATA0 TDO/DSO
U0RXD
10
DDATA1
11
RSTOUT
12
M
7
8
9
Figure 4. MCF5207CVM166 Pinout Top View (144 MAPBGA)
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
11
Mechanicals and Pinouts
4.4 Package Dimensions—144 MAPBGA
Figure 5 shows the MCF5207CAB166 package dimensions.
Figure 5. MCF5207CAB166 Package Dimensions (144 MAPBGA)
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
12
Freescale Semiconductor
Mechanicals and Pinouts
4.5 Pinout—160 QFP
Figure 6 shows a pinout of the MCF5208CAB166 device.
•
VSS
EVDD
1
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
A18
2
VSS
FEC_TXD0
FEC_TXD1
FEC_TXD2
FEC_TXD3
FEC_COL
FEC_CRS
EVDD
3
SD_VDD
VSS
4
5
A17
6
A16
7
A15
8
A14
9
A13
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A12
SD_VDD
A11
TS
A10
SD_WE
A9
SD_CKE
SD_CS
D15
A8
A7
A6
D14
A5
D13
A4
D12
A3
D11
A2
D10
A1
D9
A0
D8
98
TA
BE/BWE1
SD_DQS3
BE/BWE3
D31
97
SD_VDD
VSS
96
95
EVDD
PLL_VDD
PLL_VSS
IVDD
JTAG_EN
RESET
EVDD
XTAL
DRAMSEL
EXTAL
TDI/DSI
TRST/DSCLK
TMS/BKPT
RSTOUT
VSS
94
D30
93
D29
92
D28
91
D27
90
D26
89
D25
88
D24
87
SD_SDR_DQS
IVDD
86
85
SD_CLK
SD_CLK
SD_VDD
FB_CLK
84
83
82
81
Figure 6. MCF5208CAB166 Pinout Top View (160 QFP)
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
13
Mechanicals and Pinouts
4.6 Package Dimensions—160 QFP
The package dimensions of the MCF5208CAB166 device are shown in the figures below.
Top View
Figure 7. MCF5208CAB166 Package Dimensions (Sheet 1 of 2)
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
14
Freescale Semiconductor
Mechanicals and Pinouts
SECTION B-B
DETAIL A
Figure 8. MCF5208CAB166 Package Dimensions (Sheet 2 of 2)
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
15
Mechanicals and Pinouts
4.7 Pinout—196 MAPBGA
Figure 9 shows a pinout of the MCF5208CVM166 device.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FEC_
TXEN
FEC_
TXER
FEC_
RXDV
FEC_
RXD3
QSPI_
CLK
A
B
C
D
E
F
VSS
DT1IN
DT2IN
U1TXD
FB_CS2
A22
A20
A19
VSS
A
B
C
D
E
F
FEC_
TXD0
FEC_
TXD1
FEC_
TXCLK
FEC_
RXCLK
FEC_
RXD2
QSPI_
DOUT
DT0IN
DT3IN
IRQ7
IRQ4
EVDD
VSS
U1RXD
U1RTS
IRQ1
FB_CS1
A23
A21
TEST
A14
A10
A6
A18
A16
A13
A9
A17
A15
FEC_
TXD3
FEC_
TXD2
FEC_
RXER
FEC_
RXD1
FEC_
MDIO
QSPI_
DIN
RCON
FB_CS0 FB_CS3
FEC_
CRS
FEC_
COL
FEC_
RXD0
FEC_
MDC
QSPI_
IVDD
CS2
I2C_SDA
IVDD
I2C_SCL
SD_CS
D12
U1CTS
A12
SD_CKE SD_WE
TS
EVDD
EVDD
EVDD
EVDD
VSS
SD_VDD SD_VDD SD_VDD
A11
A7
A8
D13
D9
D14
D10
D15
D11
VSS
VSS
VSS
VSS
EVDD
R/W
OE
SD_VDD SD_VDD
A5
A4
G
H
J
EVDD
VSS
VSS
VSS
SD_VDD
EVDD
EVDD
EVDD
PST1
A3
A2
A1
A0
G
H
J
BE/
BWE3
SD_
DQS3
BE/
BWE1
PLL_
VSS
PLL_
VDD
D8
SD_VDD
VSS
VSS
IVDD
NC
TA
JTAG_
EN
D28
D24
D29
D25
D30
D26
D31
D27
IVDD
D21
D20
SD_VDD SD_VDD
VSS
EVDD
EVDD
PST0
EVDD
VSS
IVDD
RESET
XTAL
EXTAL
DRAM
SEL
TDI/
DSI
K
L
SD_VDD SD_VDD SD_VDD
EVDD
VSS
K
L
SD_SDR
_DQS
SD_
DQS2
TRST/
DSCLK
SD_CLK SD_VDD
D18
D17
D16
D5
D4
D3
IVDD
BE/
BWE0
TDO/
DSO
PLL_
TEST
TMS/
BKPT
M
N
P
SD_CLK
VSS
D23
D22
PST2
DDATA1
DDATA2
M
N
P
FB_CLK SD_A10
D7
D1
PST3
U0CTS
U0RXD RSTOUT
BE/
BWE2
TCLK/
PSTCLK
VSS
1
SD_CAS SD_RAS
D19
4
D6
6
D2
7
D0
8
DDATA0 DDATA3
U0RTS
12
U0TXD
13
VSS
14
2
3
5
9
10
11
Figure 9. MCF5208CVM166 Pinout Top View (196 MAPBGA)
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
16
Freescale Semiconductor
Electrical Characteristics
4.8 Package Dimensions—196 MAPBGA
The package dimensions for the MCF5208CVM166 device is shown below.
Top View
Bottom View
Figure 10. MCF5208CVM166 Package Dimensions (196 MAPBGA)
5 Electrical Characteristics
5.1 Maximum Ratings
1, 2
Table 4. Absolute Maximum Ratings
Rating
Core Supply Voltage
Symbol
Value
Unit
IVDD
EVDD
SDVDD
PLLVDD
VIN
– 0.5 to +2.0
– 0.3 to +4.0
– 0.3 to +4.0
– 0.3 to +2.0
– 0.3 to +3.6
25
V
V
CMOS Pad Supply Voltage
DDR/Memory Pad Supply Voltage
PLL Supply Voltage
V
V
Digital Input Voltage 3
V
Instantaneous Maximum Current
ID
mA
Single pin limit (applies to all pins) 3, 4, 5
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
17
Electrical Characteristics
1, 2
Table 4. Absolute Maximum Ratings
Operating Temperature Range (Packaged) TA
(continued)
– 40 to 85
°C
°C
(TL - TH)
Storage Temperature Range
NOTES:
Tstg
– 55 to 150
1
Functional operating conditions are given in Section 5.4, “DC Electrical Specifications”.
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is
not guaranteed. Continued operation at these levels may affect device reliability or cause
permanent damage to the device.
2
3
This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid application of
any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate logic voltage level (VSS or
EVDD).
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages,
then use the larger of the two values.
4
5
All functional non-supply pins are internally clamped to VSS and EVDD
.
Power supply must maintain regulation within operating EVDD range during instantaneous
and operating maximum current conditions. If positive injection current (Vin > EVDD) is greater
than IDD, the injection current may flow out of EVDD and could result in external power supply
going out of regulation. Ensure external EVDD load shunts current greater than maximum
injection current. This is the greatest risk when the MCU is not consuming power (ex; no
clock). Power supply must maintain regulation within operating EVDD range during
instantaneous and operating maximum current conditions.
5.2 Thermal Characteristics
Table 5 lists thermal resistance values
Table 5. Thermal Characteristics
Characteristic
Symbol 196MBGA 144MBGA 160QFP 144LQFP Unit
Junction to ambient, natural convection
Four layer board
(2s2p)
θJMA
471,2
431,2
471,2
431,2
491,2
441,2
651,2
581,2
°C/W
°C/W
Junction to ambient (@200 ft/min)
Four layer board
(2s2p)
θJMA
Junction to board
θJB
θJC
Ψjt
Tj
363
224
61,5
105
363
224
61,5
105
403
394
503
194
51,7
105
°C/W
°C/W
°C/W
oC
Junction to case
Junction to top of package
Maximum operating junction temperature
121,6
105
NOTES:
1
θ
JMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of θJmA and power dissipation specifications in the system design to prevent device junction temperatures
from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly
influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be
verified by physical measurement in the customer’s system using the Ψjt parameter, the device power dissipation, and the
method described in EIA/JESD Standard 51-2.
2
Per JEDEC JESD51-6 with the board horizontal.
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
18
Freescale Semiconductor
Electrical Characteristics
3
4
5
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance
with Psi-JT.
6
7
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance
with Psi-JT.
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance
with Psi-JT.
The average chip-junction temperature (T ) in °C can be obtained from:
J
TJ = TA + (PD × ΘJMA
)
Eqn. 1
Where:
T
= Ambient Temperature, °C
= Package Thermal Resistance, Junction-to-Ambient, ×C/W
= P + P
A
Q
JMA
P
D
INT
I/O
P
= I × IV , Watts - Chip Internal Power
DD DD
INT
P
= Power Dissipation on Input and Output Pins — User Determined
I/O
For most applications P < P
and can be ignored. An approximate relationship between P and T (if
I/O
INT
D
J
P
is neglected) is:
I/O
K
--------------------------------
PD
=
Eqn. 2
(TJ + 273°C)
Solving equations 1 and 2 for K gives:
K = PD × (TA × 273°C) + QJMA × P2D
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by
D
A
D
J
solving Equation 1 and Equation 2 iteratively for any value of T .
A
5.3 ESD Protection
1, 2
Table 6. ESD Protection Characteristics
Characteristics
Symbol
Value
Unit
ESD Target for Human Body Model
HBM
2000
V
NOTES:
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for
Automotive Grade Integrated Circuits.
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
19
Electrical Characteristics
2
A device is defined as a failure if, after exposure to ESD pulses, the device no longer
meets the device specification requirements. Complete DC parametric and functional
testing is performed per applicable device specification at room temperature followed by
hot temperature, unless specified otherwise in the device specification.
5.4 DC Electrical Specifications
Table 7. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Unit
Core Supply Voltage
PLL Supply Voltage
IVDD
PLLVDD
EVDD
1.4
1.4
3.0
1.6
1.6
3.6
V
V
V
V
CMOS Pad Supply Voltage
SDRAM and FlexBus Supply Voltage
SDVDD
Mobile DDR/Bus Pad Supply Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
1.70
2.25
3.0
1.95
2.75
3.6
CMOS Input High Voltage
CMOS Input Low Voltage
EVIH
EVIL
2
EVDD + 0.3
V
V
V
VSS - 0.3
EVDD - 0.4
0.8
—
CMOS Output High Voltage
IOH = –5.0 mA
EVOH
CMOS Output Low Voltage
IOL = 5.0 mA
EVOL
—
0.4
V
V
SDRAM and FlexBus Input High Voltage
SDVIH
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
1.35
1.7
2
SDVDD + 0.3
SDVDD + 0.3
SDVDD + 0.3
SDRAM and FlexBus Input Low Voltage
SDVIL
V
V
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
VSS - 0.3
VSS - 0.3
VSS - 0.3
0.45
0.8
0.8
SDRAM and FlexBus Output High Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
IOH = –5.0 mA for all modes
SDVOH
SDVDD - 0.35
—
—
—
2.1
2.4
SDRAM and FlexBus Output Low Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
SDVOL
V
—
—
—
0.3
0.3
0.5
I
OL = 5.0 mA for all modes
Input Leakage Current
Iin
–1.0
1.0
μA
Vin = IVDD or VSS, Input-only pins
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
20
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
Weak Internal Pull Up Device Current, tested at VIL Max.1
IAPU
Cin
-10
- 130
μA
Input Capacitance 2
pF
All input-only pins
All input/output (three-state) pins
—
—
7
7
NOTES:
1
Refer to the signals section for pins having weak internal pull-up devices.
This parameter is characterized before qualification rather than 100% tested.
2
5.4.1 PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog V pins.
DD
The filter shown in Figure 11 should be connected between the board V and the PLLV pins. The
DD
DD
resistor and capacitors should be placed as close to the dedicated PLLV pin as possible.
DD
10 Ω
Board VDD
PLL VDD Pin
10 µF
0.1 µF
GND
Figure 11. System PLL V Power Filter
DD
5.4.2 Supply Voltage Sequencing and Separation Cautions
The relationship between SDV and EV is non-critical during power-up and power-down sequences.
DD
DD
SDV (2.5V or 3.3V) and EV are specified relative to IV .
DD
DD
DD
5.4.2.1 Power Up Sequence
If EV /SDV are powered up with IV at 0 V, the sense circuits in the I/O pads cause all pad output
DD
DD
DD
drivers connected to the EV /SDV to be in a high impedance state. There is no limit on how long after
DD
DD
EV /SDV powers up before IV must power up. IV should not lead the EV , SDV , or
DD
DD
DD
DD
DD
DD
PLLV by more than 0.4 V during power ramp-up or there will be high current in the internal ESD
DD
protection diodes. The rise times on the power supplies should be slower than 500 us to avoid turning on
the internal ESD protection clamp diodes.
5.4.2.2 Power Down Sequence
If IV /PLLV are powered down first, sense circuits in the I/O pads cause all output drivers to be in a
DD
DD
high impedance state. There is no limit on how long after IV and PLLV power down before EV
DD
DD
DD
or SDV must power down. IV should not lag EV , SDV , or PLLV going low by more than
DD
DD
DD
DD
DD
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
21
Electrical Characteristics
0.4 V during power down or there is an undesired high current in the ESD protection diodes. There are no
requirements for the fall times of the power supplies.
The recommended power down sequence is:
1. Drop IV /PLLV to 0 V.
DD
DD
2. Drop EV /SDV supplies.
DD
DD
5.5 Current Consumption
All of the below current consumption data is lab data measured on a single device using an evaluation
board. Table 8 shows the typical current consumption in low-power modes at various f
Current measurements are taken after executing a STOP instruction.
frequencies.
sys/2
1,2
Table 8. Current Consumption in Low-Power Mode
Typical3 (mA)
Peak4 (mA)
83.33 MHz
Voltage
Mode
(V)
44 MHz
56 MHz
64 MHz
72 MHz
83.33 MHz
3.3
2.5
1.5
3.3
2.5
1.5
3.3
2.5
1.5
3.3
2.5
1.5
3.3
2.5
1.5
3.3
2.5
1.5
1.33
15.19
0.519
1.93
Stop Mode 3
(Stop 11)5
Stop Mode 2
(Stop 10)5
15.19
1.25
1.83
Stop Mode 1
(Stop 01)5
15.23
8.24
2.23
16.2
8.32
2.23
16.2
11.53
6.79
16.17
16.29
10.22
2.33
9.55
2.41
10.61
2.5
12.1
2.61
12.1
2.61
Stop Mode 0
(Stop 00)5
16.47
10.32
2.33
16.62
9.66
16.91
10.73
2..5
17.24
12.25
2.6
17.24
12.25
4.07
2.41
Wait/Doze
Run
16.48
14.36
9.02
16.62
14.29
14.56
16.64
21.13
16.91
15.92
19.54
16.89
23.57
17.24
18.21
29.12
17.23
27.0
18.77
35.45
30.43
18.76
44.1
16.48
20.36
NOTES:
1
2
3
4
All values are measured with a 3.30V EVDD, 2.50V SDVDD, and 1.5V IVDD power supplies. Tests performed at
room temperature with pins configured for high drive strength.
Refer to the Power Management chapter in the MCF5208 Reference Manual for more information on low-power
modes.
All peripheral clocks except UART0, FlexBus, INTC, reset controller, PLL, and Edge Port off before entering
low-power mode. All code executed from flash.
Peak current measured while running a while(1) loop with all modules active.
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
22
Freescale Semiconductor
Electrical Characteristics
5
See the description of the low-power control register (LCPR) in the MCF5208 Reference Manual for more
information on stop modes 0–3.
The figure below illustrates the power consumption in a graphical format.
250
Stop 0 - Flash
Stop 1 - Flash
Stop 2 - Flash
Stop 3 - Flash
Wait/Doze - Flash
Run - Flash
200
150
100
50
0
44
48
56
64
72
83.33
83.33(peak)
fsys/2 (MHz)
Figure 12. Current Consumption in Low-Power Modes
1
Table 9. Typical Active Current Consumption Specifications
Typical2 Active (mA)
Voltage
(V)
Peak3 Active
fsys/2 Frequency
(mA)
SRAM
Flash
3.3
2.5
1.5
3.3
2.5
1.5
3.3
2.5
1.5
3.3
2.5
1.5
3.3
2.5
1.5
2.04
15.24
1.30
2.12
15.32
1.41
2.28
15.24
1.49
1 MHz
2.23
2.40
3.57
2 MHz
4 MHz
15.26
1.71
15.42
1.92
15.26
2.09
2.60
2.95
3.58
15.30
2.49
15.61
2.95
15.30
3.29
7.61
17.67
19.49
28.72
26.21
20.06
31.13
25.34
16.95
39.02
34.45
17.17
42.30
44 MHz
48 MHz
16.13
24.04
8.16
16.28
26.05
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
23
Electrical Characteristics
1
Table 9. Typical Active Current Consumption Specifications (continued)
Typical2 Active (mA)
Voltage
(V)
Peak3 Active
(mA)
fsys/2 Frequency
SRAM
Flash
3.3
2.5
1.5
3.3
2.5
1.5
3.3
2.5
1.5
3.3
2.5
1.5
10.09
16.43
30.07
15.72
16.56
32.19
20.97
16.87
35.90
31.37
17.21
41.10
30.71
20.71
35.90
31.37
21.08
38.72
31.40
21.70
43.20
25.83
22.80
49.40
38.97
17.65
47.90
42.10
17.95
53.50
48.80
18.20
59.50
48.60
18.83
67.50
56 MHz
64 MHz
72 MHz
83.33 MHz
NOTES:
1
All values are measured with a 3.30V EVDD, 2.50V SDVDD, and 1.5V IVDD power
supplies. Tests performed at room temperature with pins configured for high drive
strength.
CPU polling a status register. All peripheral clocks except UART0, FlexBus, INTC,
reset controller, PLL, and edge port disabled.
2
3
Peak current measured while running a while(1) loop with all modules active.
5.6 Oscillator and PLL Electrical Characteristics
Table 10. PLL Electrical Characteristics
Min.
Value
Max.
Value
Num
Characteristic
Symbol
Unit
1
PLL Reference Frequency Range
Crystal reference
fref_crystal
fref_ext
12
12
251
401
MHz
MHz
External reference
2
Core frequency
fsys
fsys/2
488 x 10-6
244 x 10-6
166.66
83.33
MHz
MHz
CLKOUT Frequency2
3
4
Crystal Start-up Time3, 4
tcst
—
10
ms
EXTAL Input High Voltage
Crystal Mode5
All other modes (External, Limp)
VIHEXT
VIHEXT
VXTAL + 0.4
EVDD/2 + 0.4
—
—
V
V
5
EXTAL Input Low Voltage
Crystal Mode5
VILEXT
VILEXT
—
—
VXTAL - 0.4
EVDD/2 - 0.4
V
V
All other modes (External, Limp)
7
8
PLL Lock Time 3, 6
tlpll
tdc
—
50000
60
CLKIN
%
Duty Cycle of reference 3
40
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
24
Freescale Semiconductor
Electrical Characteristics
Table 10. PLL Electrical Characteristics (continued)
Min.
Max.
Unit
Num
Characteristic
Symbol
Value
Value
9
XTAL Current
IXTAL
CS_XTAL
CS_EXTAL
CL
1
3
mA
pF
pF
10
11
12
Total on-chip stray capacitance on XTAL
Total on-chip stray capacitance on EXTAL
Crystal capacitive load
1.5
1.5
See crystal
spec
13
14
17
Discrete load capacitance for XTAL
Discrete load capacitance for EXTAL
CL_XTAL
CL_EXTAL
Cjitter
2*CL -
CS_XTAL
CPCB_XTAL
pF
pF
-
7
2*CL -
CS_EXTAL
CPCB_EXTAL
-
7
CLKOUT Period Jitter, 3, 4, 7, 8, 9 Measured at fSYS Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
—
—
10
TBD
% fsys/2
% fsys/2
18
19
Frequency Modulation Range Limit 3, 10, 11
(fsysMax must not be exceeded)
Cmod
fvco
0.8
2.2
%fsys/2
VCO Frequency. fvco = (fref * PFD)/4
350
540
MHz
NOTES:
1
The maximum allowable input clock frequency when booting with the PLL enabled is 24 MHz. For higher input clock
frequencies, the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.
All internal registers retain data at 0 Hz.
2
3
4
5
6
7
8
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
This parameter is guaranteed by design rather than 100% tested.
This specification is the PLL lock time only and does not include oscillator start-up time.
CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
.
Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.
Modulation percentage applies over an interval of 10μs, or equivalently the modulation rate is 100KHz.
Modulation range determined by hardware design.
9
10
11
5.7 External Interface Timing Characteristics
Table 11 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the FB_CLK output.
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
25
Electrical Characteristics
All other timing relationships can be derived from these values. Timings
listed in Table 11 are shown in Figure 14 and Figure 15.
* The timings are also valid for inputs sampled on the negative clock edge.
1.5V
FB_CLK(75MHz)
TSETUP
THOLD
Invalid
1.5V Valid 1.5V
Invalid
Input Setup And Hold
Input Rise Time
trise
Vh = VIH
V = V
l
IL
tfall
Vh = VIH
Vl = VIL
Input Fall Time
FB_CLK
Inputs
FB4
FB5
Figure 13. General Input Timing Requirements
5.7.1 FlexBus
FlexBus is a multi-function external bus interface provided to interface to slave-only devices up to a
maximum bus frequency of 83.33 MHz. It can be directly connected to asynchronous or synchronous
devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave)
devices with little or no additional circuitry. For asynchronous devices, a simple chip-select based interface
can be used. The FlexBus interface has six general purpose chip-selects (FB_CS[5:0]) that can be
configured to be distributed between the FlexBus or SDRAM memory interfaces. Chip-select FB_CS[0]
can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or
longword (32 bits) wide. Control signal timing is compatible with common ROM/flash memories.
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
26
Freescale Semiconductor
Electrical Characteristics
5.7.1.1 FlexBus AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the system clock.
Table 11. FlexBus AC Timing Specifications
Num
Characteristic
Frequency of Operation
Symbol
Min
Max
Unit
Notes
83.33
Mhz
ns
fsys/2
FB1
FB2
Clock Period (FB_CLK)
tFBCK
12
—
tcyc
1
Data, and Control Output Valid (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)
tFBCHDCV
7.0
—
ns
1, 2
FB3
Data, and Control Output Hold ((A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)
tFBCHDCI
1
ns
FB4
FB5
FB6
FB7
Data Input Setup
tDVFBCH
tDIFBCH
tCVFBCH
tCIFBCH
3.5
0
—
—
—
—
ns
ns
ns
ns
Data Input Hold
Transfer Acknowledge (TA) Input Setup
Transfer Acknowledge (TA) Input Hold
4
0
NOTES:
1
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.8, “SDRAM Bus” for SD_CS[1:0]
timing.
2
The FlexBus supports programming an extension of the address hold. Please consult the device reference manual for
more information.
NOTE
The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM
controller. At the end of the read and write bus cycles the address signals are
indeterminate.
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
27
Electrical Characteristics
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[23:0]
FB_A[23:0]
FB2
FB5
FB_D[31:X]
ADDR[31:X]
DATA
FB4
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB6
FB7
FB_TA
Figure 14. FlexBus Read Timing
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[23:0]
FB_A[23:0]
FB2
ADDR[31:X]
FB_D[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB6
FB7
FB_TA
Figure 15. Flexbus Write Timing
5.8 SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports
standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time. The
SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable for
Class I or Class II drive strength.
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
28
Freescale Semiconductor
Electrical Characteristics
5.8.1 SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read
cycles. The SDRAM controller is a DDR controller with an SDR mode. Because it is designed to support
DDR, a DQS pulse must remain supplied to the device for each data beat of an SDR read. The ColdFire
processor accomplishes this by asserting a signal called SD_SDR_DQS during read cycles. Take care
during board design to adhere to the following guidelines and specs with regard to the SD_SDR_DQS
signal and its usage.
Table 12. SDR Timing Specifications
Symbol
Characteristic
Frequency of Operation
Clock Period (tCK
Pulse Width High (tCKH
Pulse Width Low (tCKL
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
Symbol
Min
Max
Unit
Notes
1
60
12
83.33
16.67
0.55
MHz
ns
2
3
3
SD1
SD3
SD4
SD5
)
tSDCK
tSDCKH
tSDCKL
)
0.45
0.45
—
SD_CLK
SD_CLK
ns
)
0.55
tSDCHACV
0.5 × SD_CLK
SD_BA, SD_CS[1:0] - Output Valid (tCMV
)
+ 1.0
SD6
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
tSDCHACI
tDQSOV
2.0
—
—
ns
SD_BA, SD_CS[1:0] - Output Hold (tCMH
)
4
5
6
7
SD7
SD8
SD_SDR_DQS Output Valid (tDQSOV
)
Self timed
ns
ns
SD_DQS[3:2] input setup relative to SD_CLK (tDQSIS) tDQVSDCH 0.25 × SD_CLK 0.40 × SD_CLK
SD9
SD_DQS[3:2] input hold relative to SD_CLK (tDQSIH
)
tDQISDCH Does not apply. 0.5 SD_CLK fixed width.
SD10
Data (D[31:0]) Input Setup relative to SD_CLK
tDVSDCH 0.25 × SD_CLK
—
ns
ns
ns
ns
(reference only) (tDIS
)
SD11
SD12
SD13
Data Input Hold relative to SD_CLK (reference only)
tDISDCH
1.0
—
—
(tDIH
)
Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output tSDCHDMV
0.75 × SD_CLK
Valid (tDV
)
+ 0.5
Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output tSDCHDMI
1.5
—
Hold (tDH
)
NOTES:
1
The device supports the same frequency of operation for FlexBus and SDRAM as that of the internal bus clock. Please see the
PLL chapter of the MCF5208 Reference Manual for more information on setting the SDRAM clock rate.
2
3
4
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from
this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat.
5
6
7
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.
Because a read cycle in SDR mode continues using the DQS circuit within the device, it is most critical that the data valid window
be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup spec
is provided as guidance.
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
29
Electrical Characteristics
SD2
SD1
SD_CLK
SD3
SD5
SD_CSn
SD_RAS
SD_CAS
CMD
ROW
SD_WE
SD4
A[23:0]
SD_BA[1:0]
COL
SD11
SDDM
D[31:0]
SD12
WD1
WD2
WD3
WD4
Figure 16. SDR Write Timing
SD2
SD1
SD_CLK
SD5
SD_CSn,
SD_RAS,
SD_CAS,
SD_WE
SD3
CMD
3/4 MCLK
Reference
SD4
A[23:0],
SD_BA[1:0]
ROW
COL
tDQS
SDDM
SD6
SD_SDR_DQS (Measured at Output Pin)
SD_DQS[3:2] (Measured at Input Pin)
Board Delay
SD8
Board Delay
SD7
Delayed
SD_CLK
SD9
D[31:0]
from
WD1
WD2
WD3
WD4
Memories
NOTE: Data driven from memories relative
to delayed memory clock.
SD10
Figure 17. SDR Read Timing
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
30
Freescale Semiconductor
Electrical Characteristics
5.8.2 DDR SDRAM AC Timing Characteristics
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to
properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte
lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early
board design. Please contact your local Freescale representative if questions develop.
Table 13. DDR Timing Specifications
Num
Characteristic
Frequency of Operation
Symbol
Min
Max
Unit
Notes
1
—
—
60
12
83.33
16.67
0.55
Mhz
ns
2
3
3
4
DD1
DD2
DD3
DD4
Clock Period (SD_CLK)
Pulse Width High
tDDCK
tDDCKH
tDDCKL
tSDCHACV
0.45
0.45
—
SD_CLK
SD_CLK
ns
Pulse Width Low
0.55
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid
0.5 × SD_CLK
+ 1.0
DD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
tSDCHACI
2.0
—
ns
—
—
DD6
DD7
Write Command to first DQS Latching Transition
tCMDVDQ
tDQDMV
1.25
—
SD_CLK
ns
5
6
Data and Data Mask Output Setup (DQ-->DQS)
Relative to DQS (DDR Write Mode)
1.5
1.0
—
7
DD8
DD9
Data and Data Mask Output Hold (DQS-->DQ)
Relative to DQS (DDR Write Mode)
tDQDMI
—
ns
8
9
Input Data Skew Relative to DQS (Input Setup)
tDVDQ
tDIDQ
1
ns
ns
DD10 Input Data Hold Relative to DQS.
0.25 × SD_CLK
—
+ 0.5ns
DD11 DQS falling edge from SDCLK rising (output hold time) tDQLSDCH
0.5
0.9
—
1.1
0.6
—
ns
—
—
—
—
—
DD12 DQS input read preamble width (tRPRE
DD13 DQS input read postamble width (tRPST
DD14 DQS output write preamble width (tWPRE
DD15 DQS output write postamble width (tWPST
)
tDQRPRE
tDQRPST
tDQWPRE
tDQWPST
SD_CLK
SD_CLK
SD_CLK
SD_CLK
)
0.4
)
0.25
0.4
)
0.6
NOTES:
1
The frequency of operation is 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the same
frequency as the internal bus clock.
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature, and
voltage variations.
2
3
4
5
This specification relates to the required input setup time of today’s DDR memories. The device’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, the input setup on the memory is in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].
The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid
for each subsequent DQS edge.
6
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
31
Electrical Characteristics
7
This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative
MEM_DQS[0].
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes
valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors).
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
8
9
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
SD_CSn, SD_WE,
SD_RAS, SD_CAS
CMD
ROW
DD4
DD6
A[13:0]
COL
DD7
DM3/DM2
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
DD8
DD7
WD1 WD2 WD3 WD4
DD8
Figure 18. DDR Write Timing
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
32
Freescale Semiconductor
Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
CL=2
SD_CSn, SD_WE,
SD_RAS, SD_CAS
CMD
ROW
DD4
CL=2.5
A[13:0]
COL
DD9
DQS Read
Postamble
DQS Read
Preamble
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
DD10
WD1 WD2 WD3 WD4
DQS Read DQS Read
Preamble Postamble
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
Figure 19. DDR Read Timing
5.9 General Purpose I/O Timing
1
Table 14. GPIO Timing
Num
Characteristic
FB_CLK High to GPIO Output Valid
Symbol
Min
Max
Unit
G1
G2
G3
G4
tCHPOV
tCHPOI
tPVCH
tCHPI
—
1.5
8
8
ns
ns
ns
ns
FB_CLK High to GPIO Output Invalid
GPIO Input Valid to FB_CLK High
FB_CLK High to GPIO Input Invalid
—
—
—
1.5
NOTES:
1
GPIO spec cover: IRQn, UART and Timer pins.
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
33
Electrical Characteristics
FB_CLK
G2
G1
GPIO Outputs
G3
G4
GPIO Inputs
Figure 20. GPIO Timing
5.10 Reset and Configuration Override Timing
Table 15. Reset and Configuration Override Timing
Num
Characteristic
Symbol
Min
Max
Unit
R1
R2
R3
R4
R5
R6
R7
R8
RESET Input valid to FB_CLK High
tRVCH
tCHRI
9
1.5
5
—
—
—
10
—
—
—
1
ns
ns
FB_CLK High to RESET Input invalid
RESET Input valid Time 1
tRIVT
tCYC
ns
FB_CLK High to RSTOUT Valid
tCHROV
tROVCV
tCOS
—
0
RSTOUT valid to Config. Overrides valid
Configuration Override Setup Time to RSTOUT invalid
Configuration Override Hold Time after RSTOUT invalid
RSTOUT invalid to Configuration Override High Impedance
ns
20
0
tCYC
ns
tCOH
tROICZ
—
tCYC
NOTES:
1
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to
the system. Thus, RESET must be held a minimum of 100 ns.
FB_CLK
R1
R2
R3
RESET
R4
R4
RSTOUT
R8
R5
R6
R7
Configuration Overrides*:
(RCON, Override pins)
Figure 21. RESET and Configuration Override Timing
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
34
Freescale Semiconductor
Electrical Characteristics
NOTE
Refer to the MCF5208 Reference Manual for more information.
5.11 I2C Input/Output Timing Specifications
2
Table 16 and Table 17 list specifications for the I C input and output timing parameters.
2
Table 16. I C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Start condition hold time
Min
Max
Unit
I1
I2
I3
I4
I5
I6
I7
I8
I9
2
8
—
—
1
tcyc
tcyc
ms
ns
Clock low period
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
Data hold time
—
0
—
1
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
Clock high time
—
4
ms
tcyc
ns
—
—
—
—
Data setup time
0
Start condition setup time (for repeated start condition only)
Stop condition setup time
2
tcyc
tcyc
2
2
Table 17. I C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Start condition hold time
Min
Max
Unit
I11
6
—
—
—
—
3
tcyc
tcyc
µs
1.
I2
Clock low period
10
—
7
I3 2
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
Data hold time
1.
I4
tcyc
ns
I5 3
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
Clock high time
—
10
2
1.
I6
—
—
—
—
tcyc
tcyc
tcyc
tcyc
1.
I7
Data setup time
1.
I8
Start condition setup time (for repeated start condition only)
Stop condition setup time
20
10
1.
I9
NOTES:
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table A-16. The I2C
interface is designed to scale the actual data transition time to move it to the middle of the I2C_SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in Table A-16 are minimum values.
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively
drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal
capacitance and pull-up resistor values.
2
3
Specified at a nominal 50-pF load.
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
35
Electrical Characteristics
I2
I6
I5
I2C_SCL
I1
I3
I4
I8
I9
I7
I2C_SDA
2
Figure 22. I C Input/Output Timings
5.12 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V.
5.12.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RXDV,
FEC_RXER, and FEC_RXCLK)
The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
FEC_RXCLK frequency.
Table 18 lists MII receive channel timings.
Table 18. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK
setup
5
—
ns
M2
M3
M4
FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold
FEC_RXCLK pulse width high
5
—
ns
35%
35%
65% FEC_RXCLK period
65% FEC_RXCLK period
FEC_RXCLK pulse width low
Figure 23 shows MII receive signal timings listed in Table 18.
M3
FEC_RXCLK (input)
M4
FEC_RXD[3:0] (inputs)
FEC_RXDV
FEC_RXER
M1
M2
Figure 23. MII Receive Signal Timing Diagram
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
36
Freescale Semiconductor
Electrical Characteristics
5.12.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN,
FEC_TXER, FEC_TXCLK)
Table 19 lists MII transmit channel timings.
The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. In
addition, the processor clock frequency must exceed twice the FEC_TXCLK frequency.
Table 19. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER
invalid
5
—
ns
M6
M7
M8
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid
FEC_TXCLK pulse width high
—
25
ns
35%
35%
65%
65%
FEC_TXCLK period
FEC_TXCLK period
FEC_TXCLK pulse width low
Figure 24 shows MII transmit signal timings listed in Table 19.
M7
FEC_TXCLK (input)
M5
M8
FEC_TXD[3:0] (outputs)
FEC_TXEN
FEC_TXER
M6
Figure 24. MII Transmit Signal Timing Diagram
5.12.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)
Table 20 lists MII asynchronous inputs signal timing.
Table 20. MII Async Inputs Signal Timing
Num
Characteristic
Min
Max
Unit
M9
FEC_CRS, FEC_COL minimum pulse width
1.5
—
FEC_TXCLK period
Figure 25 shows MII asynchronous input timings listed in Table 20.
FEC_CRS
FEC_COL
M9
Figure 25. MII Async Inputs Timing Diagram
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
37
Electrical Characteristics
5.12.4 MII Serial Management Channel Timing (FEC_MDIO and
FEC_MDC)
Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum
MDC frequency of 2.5 MHz.
Table 21. MII Serial Management Channel Timing
Num
Characteristic
Min Max
Unit
M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum
propagation delay)
0
—
ns
M11 FEC_MDC falling edge to FEC_MDIO output valid (max prop delay)
M12 FEC_MDIO (input) to FEC_MDC rising edge setup
M13 FEC_MDIO (input) to FEC_MDC rising edge hold
M14 FEC_MDC pulse width high
—
10
0
25
—
—
ns
ns
ns
40% 60% FEC_MDC period
40% 60% FEC_MDC period
M15 FEC_MDC pulse width low
Figure 26 shows MII serial management channel timings listed in Table 21.
M14
M15
FEC_MDC (output)
FEC_MDIO (output)
M10
M11
FEC_MDIO (input)
M12
M13
Figure 26. MII Serial Management Channel Timing Diagram
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
38
Freescale Semiconductor
Electrical Characteristics
5.13 32-Bit Timer Module AC Timing Specifications
Table 22 lists timer module AC timings.
Table 22. Timer Module AC Timing Specifications
Name
Characteristic
Unit
Min
Max
T1
T2
DT0IN / DT1IN / DT2IN / DT3IN cycle time
DT0IN / DT1IN / DT2IN / DT3IN pulse width
3
1
—
—
tCYC
tCYC
5.14 QSPI Electrical Specifications
Table 23 lists QSPI timings.
Table 23. QSPI Modules AC Timing Specifications
Name
Characteristic
Min
Max
Unit
QS1
QS2
QS3
QS4
QS5
QSPI_CS[3:0] to QSPI_CLK
1
—
1.5
9
510
10
—
tcyc
ns
QSPI_CLK high to QSPI_DOUT valid.
QSPI_CLK high to QSPI_DOUT invalid. (Output hold)
QSPI_DIN to QSPI_CLK (Input setup)
QSPI_DIN to QSPI_CLK (Input hold)
ns
—
ns
9
—
ns
The values in Table 23 correspond to Figure 27.
QS1
QSPI_CS[3:0]
QSPI_CLK
QS2
QSPI_DOUT
QS3
QS4
QS5
QSPI_DIN
Figure 27. QSPI Timing
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
39
Electrical Characteristics
5.15 JTAG and Boundary Scan Timing
Table 24. JTAG and Boundary Scan Timing
Num
Characteristics1
TCLK Frequency of Operation
Symbol
Min
Max
Unit
J1
J2
J3
J4
J5
J6
J7
J8
J9
fJCYC
tJCYC
DC
4
1/4
—
—
3
fsys/2
tCYC
ns
TCLK Cycle Period
TCLK Clock Pulse Width
tJCW
26
0
TCLK Rise and Fall Times
tJCRF
ns
Boundary Scan Input Data Setup Time to TCLK Rise
Boundary Scan Input Data Hold Time after TCLK Rise
TCLK Low to Boundary Scan Output Data Valid
TCLK Low to Boundary Scan Output High Z
TMS, TDI Input Data Setup Time to TCLK Rise
tBSDST
tBSDHT
tBSDV
4
—
—
33
33
—
—
26
8
ns
26
0
ns
ns
tBSDZ
0
ns
tTAPBST
tTAPBHT
tTDODV
tTDODZ
tTRSTAT
tTRSTST
4
ns
J10 TMS, TDI Input Data Hold Time after TCLK Rise
J11 TCLK Low to TDO Data Valid
10
0
ns
ns
J12 TCLK Low to TDO High Z
0
ns
J13 TRST Assert Time
100
10
—
—
ns
J14 TRST Setup Time (Negation) to TCLK High
ns
NOTES:
1
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
J2
J3
J3
V
IH
TCLK
(input)
V
IL
J4
J4
Figure 28. Test Clock Input Timing
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
40
Freescale Semiconductor
Electrical Characteristics
TCLK
V
V
IH
IL
J5
Input Data Valid
J6
Data Inputs
J7
J8
Data Outputs
Output Data Valid
Data Outputs
Data Outputs
J7
Output Data Valid
Figure 29. Boundary Scan (JTAG) Timing
TCLK
V
V
IL
IH
J9
Input Data Valid
J10
TDI
TMS
J11
TDO
Output Data Valid
J12
J11
TDO
TDO
Output Data Valid
Figure 30. Test Access Port Timing
TCLK
TRST
J14
J13
Figure 31. TRST Timing
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
41
Electrical Characteristics
5.16 Debug AC Timing Specifications
Table 25 lists specifications for the debug AC timing parameters shown in Figure 32.
Table 25. Debug AC Timing Specification
Num
Characteristic
PSTCLK cycle time
Min
Max
Unit
D0
D1
D2
D3
D41
D5
D6
1
—
1.5
1
1
3.0
—
—
—
—
—
tSYS
ns
PSTCLK rising to PSTDDATA valid
PSTCLK rising to PSTDDATA invalid
DSI-to-DSCLK setup
ns
PSTCLK
PSTCLK
PSTCLK
PSTCLK
DSCLK-to-DSO hold
4
DSCLK cycle time
5
BKPT assertion time
1
NOTES:
1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized
DSCLK input relative to the rising edge of PSTCLK.
D0
PSTCLK
D2
D1
PSTDDATA[7:0]
Figure 32. Real-Time Trace AC Timing
D5
DSCLK
DSI
D3
Current
D4
Next
DSO
Past
Current
Figure 33. BDM Serial Port AC Timing
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
42
Freescale Semiconductor
Revision History
6 Revision History
Table 26. Revision History
Revision
Number
Date
Substantive Changes
0
5/23/2005
6/16/2005
• Initial Release
0.1
• Corrected 144QFP pinout in Figure 1. Pins 139-142 incorrectly showed
FEC functionality, which are actually UART 0/1 clear-to-send and
request-to-send signals.
• Changed maximum core frequency in Table 10, spec #2, from 240MHz to
166.67MHz. Also, changed symbols in table: fcore -> fsys and fsys -> fsys/2
for consistency throughout document and reference manual.
0.2
8/26/2005
• Changed ball M9 from SD_VDD to EVDD in Figure 9.
• Table 3: Pin 33 for 144 LQFP package should be EVDD instead of
SD_VDD. BE/BWE[3:0] for 144 LQFP should be “20, 48, 18, 50“ instead
of “18, 20, 48, 50”
Cleaned up various electrical specifications:
• Table 4: Added DDR/Memory pad supply voltage spec, changed “clock
synthesizer supply voltage” to “PLL supply voltage”, changed min PLLVDD
from -0.5 to -0.3, changed max VIN from 4.0 to 3.6, changed minimum Tstg
from -65 to -55,
• Table 5: Changed TBD values in Tj entry to 105°C.
• Table 7: Changed minimum core supply voltage from 1.35 to 1.4 and
maximum from 1.65 to 1.6, added PLL supply voltage entry, added pad
supply entries for mobile-DDR, DDR, and SDR, changed minimum input
high voltage from 0.7xEVDD to 2 and maximum from 3.65 to EVDD+0.05,
changed minimum input low voltage from VSS-0.3 to -0.05 and maximum
from 0.35xEVDDto 0.8, added input high/low voltage entries for DDR and
mobile-DDR, removed high impedance leakage current entry, changed
minimum output high voltage from EVDD-0.5 to EVDD-0.4, added DDR/bus
output high/low voltage entries, removed load capacitance and DC
injection current entries.
• Added filtering circuits and voltage sequencing sections: Section 5.4.1,
“PLL Power Filtering,” and Section 5.4.2, “Supply Voltage Sequencing and
Separation Cautions.”
• Removed “Operating Conditions” table from Section 5.6, “Oscillator and
PLL Electrical Characteristics,” because it is redundant with Table 7.
• Table 11: Changed minimum core frequency to TBD, removed external
reference and on-chip PLL frequency specs to have only a CLKOUT
frequency spec of TBD to 83.33MHz, removed loss of reference frequency
and self-clocked mode frequency entries, in EXTAL input high/low voltage
entries changed “All other modes (Dual controller (1:1), Bypass, External)”
to “All other modes (External, Limp)”, removed XTAL output high/low
voltage entries, removed power-up to lock time entry, removed last 5
entries (frequency un-lock range, frequency lock range, CLKOUT period
jitter, frequency modulation range limit, and ICO frequency)
0.3
9/07/2005
• Corrected DRAMSEL footnote #3 in Table 3.
• Updated Table 3 with 144MAPBGA pin locations.
• Added 144MAPBGA ballmap to Section 4.3, “Pinout—144 MAPBGA.”
• Changed J12 from PLL_VDD to IVDD in Figure 9.
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
43
Revision History
Table 26. Revision History (continued)
Substantive Changes
Revision
Number
Date
0.4
0.5
0.6
10/10/2005
• Figure 1 and Table 3: Changed pin 33 from EVDD to SD_VDD
• Figure 4 and Table 3: Changed ball D10 from TEST to VSS
• Figure 6 and Table 3: Changed pin 39 from EVDD to SD_VDD and pin 117
from TEST to VSS
3/29/2006
7/21/2006
• Added “top view” and “bottom view” labels where appropriate to
mechanical drawings and pinouts.
• Updated mechanical drawings to latest available, and added note to
Section 4, “Mechanicals and Pinouts.”
• Corrected cross-reference to Figure 9 in Section 4.7, “Pinout—196
MAPBGA.”
• Corrected L3 label in Figure 9 from SD_DR_DQS to SD_SDR_DQS.
• Corrected L6 label in Figure 9 from SD_DQS0 to SD_DQS2 and H3 from
SD_DQS1 to SD_DQS3.
• Removed second sentence from Section 5.12.2, “MII Transmit Signal
Timing (FEC_TXD[3:0], FEC_TXEN, FEC_TXER, FEC_TXCLK),”
regarding no minimum frequency requirement for TXCLK.
• Removed third and fourth paragraphs from Section 5.12.2, “MII Transmit
Signal Timing (FEC_TXD[3:0], FEC_TXEN, FEC_TXER, FEC_TXCLK),”
as this feature is not supported on this device.
1
3/28/2007
• Removed preliminary designation from Section 5, “Electrical
Characteristics.”
• Updated Section 5.2, “Thermal Characteristics.”
• Updated Section 5.4, “DC Electrical Specifications.”
• Added Section 5.5, “Current Consumption.”
• Updated Section 5.6, “Oscillator and PLL Electrical Characteristics.”
• Made some corrections to the drawings in Section 5.8, “SDRAM Bus.”
• Edited for grammar, punctuation, spelling, style, and format. - JD
2
3
12/4/2008
9/1/2009
• Updated FlexBus read and write timing diagrams in Figure 14 and
Figure 15.
Changed the following specs in Table 12 and Table 13:
• Minimum frequency of operation from TBD to 60MHz
• Maximum clock period from TBD to 16.67 ns
• Changed doc type from Advance Information to Technical Data
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
44
Freescale Semiconductor
Revision History
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
45
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MCF5208EC
Rev. 3
9/2009
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