935314082528_技术文档

56F8037/56F8027

Data Sheet

Technical Data

56F8000

16-bit Digital Signal Controllers

MC56F8037

Rev. 8

04/2012

freescale.com

Document Revision History

Version History

Rev. 0

Description of Change

Initial public release.

Rev. 1

• In Table 10-4, added an entry for flash data retention with less than 100 program/erase

cycles (minimum 20 years).

• In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz.

• In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode

from 400kHz to 200kHz.

• Changed input propagation delay values in Table 10-21 as follows:

Old values: 1 s typical, 2 s maximum

New values: 35 ns typical, 45 ns maximum

Rev. 2

Rev. 3

In Table 10-20, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz.

• Added the following note to the description of the TMS signal in Table 2-3:

Note: Always tie the TMS pin to V_DDthrough a 2.2K resistor.

• Changed the description of the GPIOC4 signal in Table 2-3 (was “...the signal goes to both

the ANA0 and CMPAI3”, is “...the signal goes to both ANB0 and CMPB13”).

Rev. 4

• Changed the ITCN_BASE address In Table 5-3 (was $00 F060, is $00 F0E0).

• In Figure 5-10, moved the footnote marker (superscript 1) from bit 4 to “RESET”.

• Changed the STANDBY > STOP I_DDvalues in Table 10-6 as follows:

Typical: was 290A, is 540A

Maximum: was 390A, is 650A

• Changed the POWERDOWN I_DDvalues in Table 10-6 as follows:

Typical: was 190A, is 440A

Maximum: was 250A, is 550A

• Changed footnote 1 in Table 10-12 (was “Output frequency after application of 8MHz trim

value, at 125°C.”, is “Output frequency after application of factory trim”).

• Deleted the text “at 125°C” from Figure 10-5.

• Changed the maximum input offset voltage in Table 10-21 (was +/- 20 mV, is ±35 mV).

Rev. 5

• In Table 2-3, changed V_CAPvalue from 4.7F to 2.2F.

• Revised Section 7, Security Features.

• Added information for 56F8027 device throughout document.

• Fixed miscellaneous typos.

56F8037/56F8027 Data Sheet, Rev. 8

2

FreescaleSemiconductor

Document Revision History

Version History

Rev. 6

Description of Change

In the table Recommended Operating Conditions, removed the line “XTAL not driven by an

external clock“ from the characteristic:

“Oscillator Input Voltage High

XTAL not driven by an external clock

XTAL driven by an external clock source”

In the table 56F8037/56F8027 Ordering Information, changed “MC56F8027VLD“ to

“MC56F8027VLH“

Removed “Preliminary” from data sheet

In the Select Peripheral Input Source for PWM2/PWM3 Pair Source Bits, fixed typos

Added new part number to ordering information: MC56F8027MLH

Rev. 7

Rev. 8

Added MC56F8037MLH to the part ordering table.

• In section Section 5.6.18, changed bit15 from “PENDING” to reserved.

• Added section Section 5.6.18.2 to describe the reserved bit.

Please see http://www.freescale.com for the most current data sheet revision.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

3

56F8037/56F8027 General Description

• Up to 32 MIPS at 32MHz core frequency

• Three Programmable Interval Timers (PITs)

• DSP and MCU functionality in a unified,

C-efficient architecture

• Two Queued Serial Communication Interfaces (QSCIs)

with LIN slave functionality

• 56F8037 offers 64KB (32K x 16) Program Flash

• 56F8027 offers 32KB (16K x 16) Program Flash

• Two Queued Serial Peripheral Interfaces (QSPIs)

• Freescale’s scalable controller area network (MSCAN)

2.0 A/B Module

• 56F8037 offers 8KB (4K x 16) Unified Data/Program

RAM

• Two 16-bit Quad Timers

2

• 56F8027 offers 4KB (2K x 16) Unified Data/Program

RAM

• One Inter-Integrated Circuit (I C) port

• Computer Operating Properly (COP)/Watchdog

• On-Chip Relaxation Oscillator

• One 6-channel PWM module

• Two 8-channel 12-bit Analog-to-Digital Converters

(ADCs)

• Integrated Power-On Reset (POR) and Low-Voltage

Interrupt (LVI) module

• Two 12-bit Digital-to-Analog Converters (DACs)

• Two Analog Comparators

• JTAG/Enhanced On-Chip Emulation (OnCE™) for

unobtrusive, real-time debugging

RESET or

GPIOA

V

2

V

3

V

SSA

CAP

DD

SS

DDA

4

JTAG/EOnCE

Port or

GPIOD

PWM

or TMRA or TMRB

or CMP or QSPI1

or GPIOA

Digital Reg

Low-Voltage

Supervisor

Analog Reg

14

16-Bit

56800E Core

Data ALU

Program Controller

and Hardware

Looping Unit

Address

Generation Unit

Bit

Manipulation

Unit

16 x 16 + 36 -> 36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

2

8

DAC

or GPIOD

PAB

PDB

CDBR

CDBW

AD0

Memory

ADC

R/W Control

or CMP

or QSCI1

or GPIOC

XDB2

XAB1

XAB2

Program Memory

32K x 16 Flash

16K x 16 Flash

8

System Bus

Control

AD1

PAB

Unified Data /

Program RAM

4K x 16

PDB

CDBR

CDBW

2K x 16

Programmable

Interval

Timer

IPBus Bridge (IPBB)

QSCI0

or PWM

2

QSPI0

I C

2

or PWM

or I C

or CAN

or TMRB

or CMP

2

or QSPI1

or TMRA

or TMRB

or GPIOB

or I C

XTAL, CLKIN, or

GPIOD

P

O

R

or TMRA

or GPIOB

System

Integration

Module

Interrupt

Controller

COP/

Watchdog

O

S

C

Clock

Generator*

or GPIOB

EXTAL or GPIOD

*Includes On-Chip

Relaxation Oscillator

6

4

56F8037/56F8027 Block Diagram

56F8037/56F8027 Data Sheet, Rev. 8

4

FreescaleSemiconductor

56F8037/56F8027 Data Sheet Table of Contents

7.3

Product Analysis. . . . . . . . . . . . . . . . . . 131

Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 6

1.1

1.2

1.3

56F8037/56F8027 Features . . . . . . . . . . . 6

56F8037/56F8027 Description . . . . . . . . . 8

Award-Winning Development

Part 8 General Purpose Input/Output

(GPIO) . . . . . . . . . . . . . . . . . . . . . . . .131

Environment . . . . . . . . . . . . . . . . . . . 9

Architecture Block Diagram . . . . . . . . . . . 9

Product Documentation . . . . . . . . . . . . . 18

Data Sheet Conventions. . . . . . . . . . . . . 18

8.1

8.2

8.3

Introduction. . . . . . . . . . . . . . . . . . . . . . 131

Configuration . . . . . . . . . . . . . . . . . . . . 131

Reset Values . . . . . . . . . . . . . . . . . . . . 135

1.4

1.5

1.6

Part 9 Joint Test Action Group (JTAG) . . .140

Part 2 Signal/Connection Descriptions . . . 19

9.1

56F8037/56F8027 Information . . . . . . . 140

2.1

2.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . 19

56F8037/56F8027 Signal Pins . . . . . . . . 24

Part 10Specifications. . . . . . . . . . . . . . . . . .140

10.1

10.2

10.3

10.4

10.5

10.6

10.7

10.8

General Characteristics . . . . . . . . . . . . 140

DC Electrical Characteristics . . . . . . . . 144

AC Electrical Characteristics . . . . . . . . 147

Flash Memory Characteristics . . . . . . . 148

External Clock Operation Timing . . . . . 148

Phase Locked Loop Timing . . . . . . . . . 149

Relaxation Oscillator Timing. . . . . . . . . 149

Reset, Stop, Wait, Mode Select, and

Part 3 OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.1

3.2

3.3

3.4

3.5

3.6

3.7

Overview. . . . . . . . . . . . . . . . . . . . . . . . . 40

Features . . . . . . . . . . . . . . . . . . . . . . . . . 41

Operating Modes . . . . . . . . . . . . . . . . . . 41

Internal Clock Source . . . . . . . . . . . . . . . 42

Crystal Oscillator. . . . . . . . . . . . . . . . . . . 42

Ceramic Resonator. . . . . . . . . . . . . . . . . 43

External Clock Input - Crystal Oscillator

Option. . . . . . . . . . . . . . . . . . . . . . . 43

Interrupt Timing . . . . . . . . . . . . . . 151

Serial Peripheral Interface (SPI) Timing152

10.9

3.8

Alternate External Clock Input . . . . . . . . 44

10.10 Quad Timer Timing. . . . . . . . . . . . . . . . 156

10.11 Queued Serial Communication Interface

(QSCI) Timing . . . . . . . . . . . . . . . 158

Part 4 Memory Maps. . . . . . . . . . . . . . . . . . . 44

4.1

4.2

4.3

4.4

4.5

4.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . 44

Interrupt Vector Table . . . . . . . . . . . . . . . 45

Program Map . . . . . . . . . . . . . . . . . . . . . 47

Data Map . . . . . . . . . . . . . . . . . . . . . . . . 48

EOnCE Memory Map . . . . . . . . . . . . . . . 50

Peripheral Memory-Mapped Registers . . 51

10.12 Freescale’s Scalable Controller Area

Network (MSCAN) Timing . . . . . . 159

10.13 Inter-Integrated Circuit Interface (I2C)

Timing . . . . . . . . . . . . . . . . . . . . . 159

10.14 JTAG Timing. . . . . . . . . . . . . . . . . . . . . 161

10.15 Analog-to-Digital Converter (ADC)

Parameters . . . . . . . . . . . . . . . . . 162

Part 5 Interrupt Controller (ITCN) . . . . . . . . 68

10.16 Equivalent Circuit for ADC Inputs. . . . . 163

10.17 Comparator (CMP) Parameters . . . . . . 164

10.18 Digital-to-Analog Converter (DAC)

Parameters . . . . . . . . . . . . . . . . . 164

5.1

5.2

5.3

5.4

5.5

5.6

5.7

Introduction . . . . . . . . . . . . . . . . . . . . . . . 68

Features . . . . . . . . . . . . . . . . . . . . . . . . . 68

Functional Description . . . . . . . . . . . . . . 68

Block Diagram. . . . . . . . . . . . . . . . . . . . . 70

Operating Modes . . . . . . . . . . . . . . . . . . 71

Register Descriptions . . . . . . . . . . . . . . . 71

Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . 92

10.19 Power Consumption . . . . . . . . . . . . . . . 166

Part 11Packaging . . . . . . . . . . . . . . . . . . . . .168

11.1

56F8037/56F8027 Package and

Pin-Out Information . . . . . . . . . . . 168

Part 6 System Integration Module (SIM). . . 93

Part 12Design Considerations . . . . . . . . . .171

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

Introduction . . . . . . . . . . . . . . . . . . . . . . . 93

Features . . . . . . . . . . . . . . . . . . . . . . . . . 94

Register Descriptions . . . . . . . . . . . . . . . 95

Clock Generation Overview . . . . . . . . . 124

Power-Saving Modes . . . . . . . . . . . . . . 124

Resets. . . . . . . . . . . . . . . . . . . . . . . . . . 126

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . 129

12.1

12.2

Thermal Design Considerations . . . . . . 171

Electrical Design Considerations . . . . . 172

Part 13Ordering Information . . . . . . . . . . . .173

Part 14Appendix. . . . . . . . . . . . . . . . . . . . . .174

Part 7 Security Features. . . . . . . . . . . . . . . 129

7.1

7.2

Operation with Security Enabled. . . . . . 129

Flash Access Lock and Unlock Mechanisms130

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

5

Part 1 Overview

1.1 56F8037/56F8027 Features

1.1.1

Digital Signal Controller Core

•

Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture

As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency

Single-cycle 16  16-bit parallel Multiplier-Accumulator (MAC)

Four 36-bit accumulators, including extension bits

32-bit arithmetic and logic multi-bit shifter

Parallel instruction set with unique DSP addressing modes

Hardware DO and REP loops

Three internal address buses

Four internal data buses

Instruction set supports both DSP and controller functions

Controller-style addressing modes and instructions for compact code

Efficient C compiler and local variable support

Software subroutine and interrupt stack with depth limited only by memory

JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time

debugging

1.1.2

Difference Between Devices

Table 1-1 outlines the key differences between the 56F8037 and 56F8027 devices.

Table 1-1 Device Differences

Feature

Program Flash

Unified Data/Program RAM

56F8037 56F8027

64KB

8KB

32KB

4KB

1.1.3

Memory

•

Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory

Flash security and protection that prevent unauthorized users from gaining access to the internal Flash

On-chip memory

— 64KB of Program Flash (56F8037 device)

32KB of Program Flash (56F8027 device)

— 8KB of Unified Data/Program RAM (56F8037 device)

4KB of Unified Data/Program RAM (56F8027 device)

•

EEPROM emulation capability using Flash

56F8037/56F8027 Data Sheet, Rev. 8

6

FreescaleSemiconductor

56F8037/56F8027 Features

1.1.4

Peripheral Circuits for 56F8037/56F8027

One multi-function six-output Pulse Width Modulator (PWM) module

— Up to 96MHz PWM operating clock

•

— 15 bits of resolution

— Center-aligned and Edge-aligned PWM signal mode

— Four programmable fault inputs with programmable digital filter

— Double-buffered PWM registers

— Each complementary PWM signal pair allows selection of a PWM supply source from:

– PWM generator

– External GPIO

– Internal timers

– Analog comparator outputs

– ADC conversion result which compares with values of ADC high- and low-limit registers to set

PWM output

•

Two independent 12-bit Analog-to-Digital Converters (ADCs)

— 2 x 8 channel inputs

— Supports both simultaneous and sequential conversions

— ADC conversions can be synchronized by both PWM and timer modules

— Sampling rate up to 2.67MSPS

— 16-word result buffer registers

•

Two 12-bit Digital-to-Analog Converters (DACs)

— 2 microsecond settling time when output swing from rail to rail

— Automatic waveform generation generates square, triangle and sawtooth waveforms with

programmable period, update rate, and range

Two 16-bit multi-purpose Quad Timer modules (TMRs)

— Up to 96MHz operating clock

— Eight independent 16-bit counter/timers with cascading capability

— Each timer has capture and compare capability

— Up to 12 operating modes

•

Two Queued Serial Communication Interfaces (QSCIs) with LIN Slave functionality

— Full-duplex or single-wire operation

— Two receiver wake-up methods:

– Idle line

– Address mark

— Four-bytes-deep FIFOs are available on both transmitter and receiver

Two Queued Serial Peripheral Interfaces (QSPIs)

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

7

— Full-duplex operation

— Master and slave modes

— Four-words-deep FIFOs available on both transmitter and receiver

— Programmable Length Transactions (2 to 16 bits)

•

One Inter-Integrated Circuit (I²C) port

— Operates up to 400kbps

— Supports both master and slave operation

— Supports both 10-bit address mode and broadcasting mode

One Freescale scalable controller area network (MSCAN) module

— Fully compliant with CAN protocol - Version 2.0 A/B

— Supports standard and extended data frames

— Supports data rate up to 1Mbps

— Five receive buffers and three transmit buffers

•

Three 16-bit Programmable Interval Timers (PITs)

Two analog Comparators (CMPs)

— Selectable input source includes external pins, DACs

— Programmable output polarity

— Output can drive Timer input, PWM fault input, PWM source, external pin output and trigger ADCs

— Output falling and rising edge detection able to generate interrupts

Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources

Up to 53 General-Purpose I/O (GPIO) pins with 5V tolerance

Integrated Power-On Reset and Low-Voltage Interrupt Module

Phase Lock Loop (PLL) to provide high-speed clock to the core and peripherals

Clock sources:

•

— On-chip relaxation oscillator

— External clock: crystal oscillator, ceramic resonator and external clock source

JTAG/EOnCE debug programming interface for real-time debugging

•

1.1.5

Energy Information

•

Fabricated in high-density CMOS with 5V tolerance

On-chip regulators for digital and analog circuitry to lower cost and reduce noise

Wait and Stop modes available

ADC smart power management

Each peripheral can be individually disabled to save power

1.2 56F8037/56F8027 Description

The 56F8037/56F8027 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs).

It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller

with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,

56F8037/56F8027 Data Sheet, Rev. 8

8

FreescaleSemiconductor

Award-Winning Development Environment

configuration flexibility, and compact program code, the 56F8037/56F8027 is well-suited for many

applications. The 56F8037/56F8027 includes many peripherals that are especially useful for industrial

control, motion control, home appliances, general purpose inverters, smart sensors, fire and security

systems, switched-mode power supply, power management, and medical monitoring applications.

The 56800E core is based on a dual Harvard-style architecture consisting of three execution units

operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style

programming model and optimized instruction set allow straightforward generation of efficient, compact

DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The 56F8037/56F8027 supports program execution from internal memories. Two data operands can be

accessed from the on-chip data RAM per instruction cycle. The 56F8037/56F8027 also offers up to 53

General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.

The 56F8037 Digital Signal Controller includes 64KB of Program Flash and 8KB of Unified

Data/Program RAM. The 56F8027 Digital Signal Controller includes 32KB of Program Flash and 4KB of

Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages.

Program Flash page erase size is 512 Bytes (256 Words).

A full set of programmable peripherals—PWM, ADCs, QSCIs, QSPIs, I2C, PITs, Quad Timers, DACs

and analog comparators—supports various applications. Each peripheral can be independently shut down

to save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs).

1.3 Award-Winning Development Environment

TM

Processor Expert

(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use

component-based software application creation with an expert knowledge system.

The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,

compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and

development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs

create a complete, scalable tools solution for easy, fast, and efficient development.

1.4 Architecture Block Diagram

The 56F8037/56F8027’s architecture is shown in Figures 1-1, 1-2, 1-3, 1-4, 1-5, 1-6, and 1-7. Figure 1-1

illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge and

the internal connections between each unit of the 56800E core. Figure 1-2 shows the peripherals and

control blocks connected to the IPBus Bridge. Figures 1-3, 1-4, 1-5, 1-6 and 1-7 detail how the device’s

I/O pins are muxed. The figures do not show the on-board regulator and power and ground signals. Please

see Part 2, Signal/Connection Descriptions, for information about which signals are multiplexed with

those of other peripherals.

1.4.1

PWM, TMR and ADC Connections

Figure 1-6 shows the over-limit and under-limit connections from the ADC to the PWM and the

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

9

connections to the PWM from the TMR and GPIO. These signals can control the PWM outputs in a similar

manner as the PWM generator. See the 56F802x and 56F803x Peripheral Reference Manual for

additional information.

The PWM_reload_sync output can be connected to Timer A’s (TMRA) Channel 3 input; TMRA’s

Channels 2 and 3 outputs are connected to the ADC sync inputs. TMRA Channel 3 output is connected to

SYNC0 and TMRA Channel 2 is connected to SYNC1. SYNC0 is the master ADC sync input that is used

to trigger ADCA and ADCB in sequence and parallel mode. SYNC1 is used to trigger ADCB in parallel

independent mode. These are controlled by bits in the SIM Control Register; see Section 6.3.1.

56F8037/56F8027 Data Sheet, Rev. 8

10

FreescaleSemiconductor

Architecture Block Diagram

DSP56800E Core

Program Control Unit

ALU1

ALU2

Address

PC

LA

LA2

Generation

Unit

Instruction

Decoder

R0

R1

(AGU)

HWS0

HWS1

FIRA

R2

R3

Interrupt

Unit

Program

Memory

M01

N3

OMR

R4

R5

N

SR

LC

LC2

Looping

Unit

SP

FISR

XAB1

XAB2

PAB

Data /

Program

RAM

PDB

CDBW

CDBR

XDB2

A2

B2

C2

D2

A1

B1

C1

D1

Y1

Y0

X0

A0

B0

C0

D0

Bit-

Manipulation

Unit

IPBUS

Interface

Y

Data

Enhanced

OnCE™

Arithmetic

Logic Unit

(ALU)

JTAG TAP

MAC and ALU

Multi-Bit Shifter

Figure 1-1 56800E Core Block Diagram

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

11

To/From IPBus Bridge

OCCS

Interrupt

(ROSC / PLL /

OSC)

Controller

Low-Voltage Interrupt

POR & LVI

System POR

GPIO A

GPIO B

GPIO C

GPIO D

RESET

SIM

(Muxed with GPIOA7)

COP Reset

COP

IPBus

(Continues on Figure 1-3)

Figure 1-2 Peripheral Subsystem

56F8037/56F8027 Data Sheet, Rev. 8

12

FreescaleSemiconductor

Architecture Block Diagram

To/From IPBus Bridge

IPBus

INTC

SYNC

MSTR_CNT_EN

PIT0

3

DAC SYNC on Figure 1-5

MSTR_CNT_EN

SYNC

PIT1

MSTR_CNT_EN

PIT2

2

3

SYNC0, SYNC1 on Figure 1-7

LIMIT on Figure 1-6

Sync0, Over/Under

ANA0

ANA0 on Figure 1-5

Sync1

Limits

GPIOC2

GPIOC3

ANA2 (V_REFHA

)

ANA3 (V_REFLA

ANA4 on Figure 1-4

ANA4

GPIOC1, 9-11

ANA1, 5-7

4

ANA1, 5-7

ADC

ANB0

ANB0 on Figure 1-5

GPIOC6

GPIOC7

ANB2 (V_REFHA

)

ANB3 (V_REFLB

ANB4 on Figure 1-4

ANB4

GPIOC5, 13-15

ANB1, 5-7

4

ANB1, 5-7

Figure 1-3 56F8037/56F8027 I/O Pin-Out Muxing (Part 1/5)

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

13

To/From IPBus Bridge

CLKO

TA0 on Figure 1-7

GPIOB4

SS1

QSPI1

3

TA1-3 on Figure 1-7

SCLK1, MISO1, MOSI1

GPIOA12 - 14

TB0 on Figure 1-5

T0

TB1 on Figure 1-5

T1

1

2

TMRB

TB2, TB3 on Figure 1-5

2

T2, T3

2

GPIOB6 - 7

GPIOB2 - 3

RXD0, TXD0

TA2, TA3 on Figure 1-7

2

QSCI0

MISO0, MOSI0

2

QSPI0

I²C

SCLK0, SS0

SCL, SDA

2

GPIOB0 - 1

GPIOB8 - 9

2

CANTX, CANRX

2

MSCAN

GPIOB12 - 13

GPIOC8 - 12

2

ANA4, ANB4 on Figure 1-3

TXD1, RXD1

2

QSCI1

IPBus

Figure 1-4 56F8037/56F8027 I/O Pin-Out Muxing (Part 2/5)

56F8037/56F8027 Data Sheet, Rev. 8

14

FreescaleSemiconductor

Architecture Block Diagram

To/From IPBus Bridge

FAULT1 on Figure 1-6

TA2 on Figure 1-7

GPIOA8

GPIOC0

CMPAI1

CMPAI3

CMP_IN1

CMP_IN3

CMPA

CMP_OUT

CMPAO on Figure 1-6, Figure 1-7

CMPAI2

CMP_IN2

GPIOA10

Export Import

ANA0 on Figure 1-3

TB2 on Figure 1-4

GPIOB10

GPIOD6

DAC0

TB0 on Figure 1-4

DAC0

2

TA0o, TA1o on Figure 1-7

3

DAC SYNC on Figure 1-3

RELOAD on Figure 1-6

DAC1

GPIOD7

TB1 on Figure 1-4

DAC1

GPIOB11

TB3 on Figure 1-4

GPIOA11

ANB0 on Figure 1-3

Import Export

CMP_IN2

CMPBI2

CMP_OUT

CMPBO on Figure 1-6, Figure 1-7

CMPB

GPIOC4

GPIOA9

CMPBI3

CMPBI1

CMP_IN3

CMP_IN1

TA3 on Figure 1-7

FAULT2 on Figure 1-6

IPBus

Figure 1-5 56F8037/56F8027 I/O Pin-Out Muxing (Part 3/5)

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

15

To/From IPBus Bridge

TA0 on Figure 1-7

GPIOA6

2

TA2 - 3 on Figure 1-7

GPIOA0 - 3

4

PWM0 - 3

FAULT0

GPIOA4 - 5

2

PWMA4 - 5

1

PWM

FAULT1

FAULT1 on Figure 1-5

CMPAO on Figure 1-5

FAULT2

FAULT3

1

RELOAD PSRC0 - 2

FAULT2 on Figure 1-5

CMPBO on Figure 1-5

TA1 on Figure 1-7

GPIOB5

CMPBO on Figure 1-5

CMPAO on Figure 1-5

IPBus

3

GPIOB2 - 4 on Figure 1-4

LIMIT on Figure 1-3

3

TA0o, TA2o, TA3o on Figure 1-3

Figure 1-6 56F8037/56F8027 I/O Pin-Out Muxing (Part 4/5)

56F8037/56F8027 Data Sheet, Rev. 8

16

FreescaleSemiconductor

Architecture Block Diagram

To/From IPBus Bridge

TA0o on Figure 1-6 (PWM)

TA0 on Figure 1-6 (GPIOA6)

TA0 on Figure 1-4 (GPIOB4)

T0o

T0i

TA1 on Figure 1-4(GPIOA12)

T1o

T1i

TA1 on Figure 1-6 (GPIOB5)

CMPAO on Figure 1-6 (CMPA)

SYNC1 on Figure 1-3 (ADC)

TA2o on Figure 1-6 (PWM)

TA2 on Figure 1-6 (GPIOA4)

TMRA

T2o

T2i

TA2 on Figure 1-5 (GPIOA8)

TA2 on Figure 1-4 (GPIOA13)

TA2 on Figure 1-4 (GPIOB2)

CMPBO on Figure 1-6 (CMPB)

SYNC0 on Figure 1-3 (ADC)

TA3o on Figure 1-6 (PWM)

TA3 on Figure 1-6 (GPIOA5)

T3o

T3i

TA3 on Figure 1-5 (GPIOA9)

TA3 on Figure 1-4 (GPIOA14)

TA 3 on Figure 1-4 (GPIOB3)

RELOAD on Figure 1-6 (PWM)

IPBus

Figure 1-7 56F8037/56F8027 I/O Pin-Out Muxing (Part 5/5)

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

17

1.5 Product Documentation

The documents listed in Table 1-2 are required for a complete description and proper design with the

56F8037/56F8027. Documentation is available from local Freescale distributors, Freescale Semiconductor

sales offices, Freescale Literature Distribution Centers, or online at:

http://www.freescale.com

Table 1-2 56F8037/56F8027 Chip Documentation

Topic

DSP56800E

Description

Order Number

DSP56800ERM

Detailed description of the 56800E family architecture,

16-bit Digital Signal Controller core processor, and the

instruction set

Reference Manual

56F802x and 56F803x

Peripheral Reference

Manual

Detailed description of peripherals of the 56F802x and

56F803x family of devices

MC56F80xxRM

56F80xxBLUG

56F802x and 56F803x

Serial Bootloader User

Guide

Detailed description of the Serial Bootloader in the

56F802x and 56F803x family of devices

56F8037/56F8027

Technical Data Sheet

Electrical and timing specifications, pin descriptions,

and package descriptions (this document)

MC56F8037/56F8027

MC56F8037/56F8027E

56F8037/56F8027

Errata

Details any chip issues that might be present

1.6 Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

This is used to indicate a signal that is active when pulled low. For example, the RESET pin is

active when low.

“asserted”

“deasserted”

Examples:

A high true (active high) signal is high or a low true (active low) signal is low.

A high true (active high) signal is low or a low true (active low) signal is high.

Voltage¹

Signal/Symbol

Logic State

True

Signal State

Asserted

V_IL/V_OL

False

Deasserted

Asserted

V_IH/V_OH

V_IL/V_OL

True

False

Deasserted

1. Values for V , V , V , and V are defined by individual product specifications.

IL

OL

IH

OH

56F8037/56F8027 Data Sheet, Rev. 8

18

FreescaleSemiconductor

Introduction

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F8037/56F8027 are organized into functional groups, as detailed in

Table 2-1. Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or

signals present on a pin, sorted by pin number.

Table 2-1 Functional Group Pin Allocations

Functional Group

Power Inputs (V_DD, V_DDA

Number of Pins

)

4

5

Ground (V_SS, V_SSA

Supply Capacitors

Reset¹

)

2

1

Pulse Width Modulator (PWM) Ports¹

Queued Serial Peripheral Interface 0 (QSPI0) Ports¹

Queued Serial Peripheral Interface 1 (QSPI1) Ports¹

Timer Module A (TMRA) Ports¹

13

4

Timer Module B (TMRB) Ports¹

4

Analog-to-Digital Converter (ADC) Ports¹

Digital-to-Analog Converter (DAC) Ports¹

Queued Serial Communications Interface 0 (QSCI0) Ports¹

Queued Serial Communications Interface 1 (QSCI1) Ports¹

Inter-Integrated Circuit Interface (I²C) Ports¹

MSCAN Ports¹

16

2

Oscillator Signals¹

2

JTAG/Enhanced On-Chip Emulation (EOnCE)¹

4

1. Pins may be shared with other peripherals. See Table 2-2.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

19

In Table 2-2, peripheral pins in bold identify reset state.

Table 2-2 56F8037/56F8027 Pins

Peripherals:

#

Quad

Timer

Power&

Ground

Pin Name

GPIOB6

Signal Name

GPIO I2C

QSCI

QSPI

ADC

PWM

DAC

Comp

MSCAN

JTAG Misc.

1

GPIOB6, RXD0, SDA,

CLKIN

B6

SDA RXD0

CLKIN

2

3

4

GPIOB1

GPIOB7

GPIOB5

GPIOB1, SS0, SDA

GPIOB7, TXD0, SCL

B1

B7

B5

SDA

SS0

SCL TXD0

GPIOB5, TA1,

FAULT3, CLKIN

FAULT3 TA1

FAULT2 TA3

TB3

CLKIN

5

6

GPIOA9

GPIOA9, FAULT2,

TA3, CMPBI1

A9

CMPBI1

CMPBI2

GPIOA11 GPIOA11, TB3,

A11

CMPBI2

7

8

9

VDD

VSS

V

DD

SS

V

SS

GPIOC12 GPIOC12, ANB4,

C12

C4

RXD1

ANB4

ANB0

RXD1

10 GPIOC4

11 GPIOC5

GPIOC4, ANB0,

CMPBI3

GPIOC5, ANB1

C5

C13

C6

ANB1

ANB5

ANB2

12 GPIOC13 GPIOC13, ANB5

13 GPIOC6

ANB2, V

REFHB

V

REFHB

14 GPIOC7

GPIOC7, ANB3,

C7

D7

ANB3

V

REFLB

V

REFLB

15 GPIOD7

16 VDDA

GPIOD7, DAC1

DAC1

DAC0

V

DDA

SSA

17 VSSA

V

SSA

18 GPIOD6

19 GPIOC3

GPIOD6, DAC0

GPIOC3, ANA3,

D6

C3

ANA3

V

REFLA

20 GPIOC2

GPIOC2, ANA2,

C2

ANA2

V

REFHA

ANA5

ANA1

ANA6

ANA0

21 GPIOC9

22 GPIOC1

GPIOC9, ANA5

GPIOC1, ANA1

C9

C1

23 GPIOC10 GPIOC10, ANA6

C10

C0

24 GPIOC0

GPIOC0, ANA0,

CMPAI3

25 GPIOC11 GPIOC11, ANA7

C11

C8

ANA7

ANA4

26 GPIOC8

27 VSS

GPIOC8, ANA4, TXD1

TXD1

V

SS

56F8037/56F8027 Data Sheet, Rev. 8

20

FreescaleSemiconductor

Introduction

Table 2-2 56F8037/56F8027 Pins (Continued)

Peripherals:

#

Quad

Timer

Power&

Ground

Pin Name

Signal Name

GPIO I2C

QSCI

QSPI

ADC

PWM

DAC

Comp

MSCAN

JTAG Misc.

28 VCAP

29 TCK

V

CAP

TCK, GPIOD2

D2

TCK

30 GPIOB10 GPIOB10, CMPAO,

B10

TB0

CMPAO

TB0

31 RESET

32 GPIOB3

RESET, GPIOA7

A7

RESET

GPIOB3, MOSI0, TA3,

PSRC1

B3

MOSI0

MISO0

PSRC1

PSRC0

TA3

TA2

33 GPIOB2

34 GPIOA6

GPIOB2, MISO0, TA2,

PSRC0

B2

A6

GPIOA6, FAULT0,

TA0

FAULT0 TA0

TB2

35 GPIOA10 GPIOA10, TB2,

A10

A8

CMPAI2

CMPAI1

CMPAI2

36 GPIOA8

GPIOA8, FAULT1,

TA2, CMPAI1

FAULT1 TA2

37 GPIOA12 GPIOA12, TB1,

A12

B4

SCLK1

SS1

TB1

TA1

SCLK1, TA1

38 GPIOB4

39 GPIOA5

GPIOB4, SS1, TB0,

TA0, PSRC2, CLKO

PSRC2

TA0

TB0

CLKO

GPIOA5, PWM5, TA3,

FAULT2

A5

PWM5

FAULT2

TA3

40 VSS

41 VDD

V

SS

DD

SS

V

DD

42 GPIOB0

43 GPIOA4

GPIOB0, SCLK0, SCL

B0

A4

SCL

SCLK0

GPIOA4, PWM4, TA2,

FAULT1

PWM4

FAULT1

TA2

44 GPIOA13 GPIOA13, TB2,

A13

A14

B9

MISO1

MOSI1

TB2

TA2

MISO1, TA2

45 GPIOA14 GPIOA14, TB3,

TB3

TA3

MOSI1, TA3

46 GPIOB9

GPIOB9, SDA,

CANRX

SDA

CANRX

47 GPIOA2

48 GPIOA3

49 VCAP

GPIOA2, PWM2

GPIOA3, PWM3

A2

A3

PWM2

PWM3

V

CAP

DD

50 VDD

V

DD

51 VSS

V

SS

52 GPIOD5

GPIOD5, XTAL, CLKIN

D5

XTAL

CLKIN

53 GPIOD4

54 GPIOB8

55 GPIOA1

GPIOD4, EXTAL

D4

B8

A1

EXTAL

GPIOB8, SCL, CANTX

GPIOA1, PWM1

SCL

CANTX

PWM1

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

21

Table 2-2 56F8037/56F8027 Pins (Continued)

Peripherals:

#

Quad

Timer

Power&

Ground

Pin Name

Signal Name

GPIO I2C

QSCI

QSPI

ADC

PWM

DAC

Comp

MSCAN

JTAG Misc.

56 GPIOA0

GPIOA0, PWM0

A0

B12

B13

D0

PWM0

57 GPIOB12 GPIOB12, CANTX

58 GPIOB13 GPIOB13, CANRX

CANTX

CANRX

59 TDI

TDI, GPIOD0

TD1

60 GPIOB11 GPIOB11, CMPBO,

B11

TB1

CMPBO

TB1

61 GPIOC15 GPIOC15, ANB7

62 GPIOC14 GPIOC14, ANB6

C15

C14

D3

ANB7

ANB6

63 TMS

64 TDO

TMS, GPIOD3

TDO, GPIOD1

TMS

TDO

D1

56F8037/56F8027 Data Sheet, Rev. 8

22

FreescaleSemiconductor

Introduction

V_DD

V_SS

GPIOA0-3 (PWM0-3)

Power

Ground

Power

4

1

3

4

GPIOA4 (PWM4, TA2, FAULT1)

GPIOA5 (PWM5, TA3, FAULT2)

GPIOA6 (FAULT0, TA0)

V_DDA

1

V_SSA

Ground

56F8037/56F802¹7

PWM

GPIOA8 (FAULT1, TA2, CMPAI1)

Other

Supply

Ports

or TMRA

or TMRB

or CMP

or QSPI1

or GPIOA

V_CAP

1

2

GPIOA9 (FAULT2, TA3, CMPBI1)

GPIOA10 (TB2, CMPAI2)

1

GPIOD4 (EXTAL)

OSC Port

or GPIO

1

GPIOA11 (TB3, CMPBI2)

GPIOD5 (XTAL, CLKIN)

GPIOA12 (SCLK1, TB1, TA1)

GPIOA13 (MISO1, TB2, TA2)

GPIOA14 (MOSI1, TB3, TA3)

RESET

or GPIOA

RESET (GPIOA7)

1

GPIOB0 (SCLK0, SCL)

GPIOB1 (SS0, SDA)

GPIOB8 (SCL, CANTX)

GPIOB9 (SDA, CANRX)

GPIOB10 (TB0, CMPAO)

1

QSPI0

1

or I²C

or PWM

I²C

GPIOB2 (MISO0, TA2, PSRC0)

GPIOB3 (MOSI0, TA3, PSRC1)

or TMRA

or GPIOB

or CAN

or TMRB

or CMP

or GPIOB

1

GPIOB11 (TB1, CMPBO)

GPIOB12 (CANTX)

1

GPIOB4 (SS1, TB0, TA0, PSRC2,

CLKO)

GPIOB13 (CANRX)

QSCI0

or PWM

or I²C

or TMRA

or TMRB

or QSPI1

or GPIOB

1

GPIOB5 (TA1, FAULT3, CLKIN)

GPIOB6 (RXD0, SDA, CLKIN)

GPIOB7 (TXD0, SCL)

GPIOC0 (ANA0 & CMPAI3)

GPIOC1 (ANA1)

1

GPIOC2 (ANA2, V_REFHA

)

1

GPIOC3 (ANA3, V_REFLA

)

DAC

or GPIOD

GPIOD6-7 (DAC0-1)

GPIOC8 (ANA4, TXD1)

GPIOC9-11 (ANA5-7)

ADC

2

1

3

or CMP

or QSCI1

or GPIOC

GPIOC4 (ANB0 & CMPBI3)

GPIOC5 (ANB1)

TDI (GPIOD0)

TDO (GPIOD1)

TCK (GPIOD2)

TMS (GPIOD3)

1

GPIOC6 (ANB2, V_REFHB

GPIOC7 (ANB3, V_REFLB

)

JTAG/ EOnCE

or GPIOD

1

)

GPIOC12 (ANB4, RXD1)

GPIOC13-15 (ANA5-7)

1

3

Figure 2-1 56F8037/56F8027 Signals Identified by Functional Group

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

23

2.2 56F8037/56F8027 Signal Pins

After reset, each pin is configured for its primary function (listed first). Any alternate functionality must

be programmed.

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

V_DD

V_SS

V_DDA

7

Supply

I/O Power — This pin supplies 3.3V power to the chip I/O interface.

41

50

8

Supply

V_SS— These pins provide ground for chip logic and I/O drivers.

27

40

51

16

Supply

ADC Power — This pin supplies 3.3V power to the ADC modules. It

must be connected to a clean analog power supply.

V_SSA

17

ADC Analog Ground — This pin supplies an analog ground to the

ADC modules.

V_CAP

28

49

31

V_CAP— Connect this pin to a 2.2F or greater bypass capacitor in

order to bypass the core voltage regulator, required for proper chip

operation. See Section 10.2.1.

RESET

Input

Input,

internal

pull-up

enabled

Reset — This input is a direct hardware reset on the processor.

When RESET is asserted low, the chip is initialized and placed in the

reset state. A Schmitt trigger input is used for noise immunity. The

internal reset signal will be deasserted synchronous with the internal

clocks after a fixed number of internal clocks.

(GPIOA7)

Input/Open

Drain

Output

Port A GPIO — This GPIO pin can be individually programmed as

an input or open drain output pin. Note that RESET functionality is

disabled in this mode and the chip can only be reset via POR, COP

reset, or software reset.

After reset, the default state is RESET.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

24

FreescaleSemiconductor

56F8037/56F8027 Signal Pins

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOA0

(PWM0)

GPIOA1

(PWM1)

GPIOA2

(PWM2)

GPIOA3

(PWM3)

56

55

47

48

Input/

Output

Input,

internal

pull-up

enabled

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Output

PWM0 — This is one of the six PWM output pins.

After reset, the default state is GPIOA0.

Input/

Output

Input,

internal

pull-up

enabled

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Output

PWM1 — This is one of the six PWM output pins.

After reset, the default state is GPIOA1.

Input/

Output

Input,

internal

pull-up

enabled

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Output

PWM2 — This is one of the six PWM output pins.

After reset, the default state is GPIOA2.

Input/

Output

Input,

internal

pull-up

enabled

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Output

PWM3 — This is one of the six PWM output pins.

After reset, the default state is GPIOA3.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

25

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOA4

43

Input/

Output

Input,

internal

pull-up

enabled

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(PWM4)

(TA2¹)

Output

PWM4 — This is one of the six PWM output pins.

TA2 — Timer A, Channel 2

Input/

Output

(FAULT1²)

Input

Fault1 — This fault input pin is used for disabling selected PWM

outputs in cases where fault conditions originate off-chip.

After reset, the default state is GPIOA4. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

¹The TA2 signal is also brought out on the GPIOA8-9, GPIOA13-14 and GPIOB2-3 pins.

²The Fault1 signal is also brought out on the GPIOA8-9, GPIOB4 and GPIOB10 pins.

GPIOA5

39

Input/

Output

Input,

internal

pull-up

enabled

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(PWM5)

(TA3³)

Output

PWM5 — This is one of the six PWM output pins.

TA3 — Timer A, Channel 3

Input/

Output

Input

Fault2 — This fault input pin is used for disabling selected PWM

outputs in cases where fault conditions originate off-chip.

(FAULT2⁴)

After reset, the default state is GPIOA5. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

³The TA3 signal is also brought out on the GPIOA8-9, GPIOA13-14 and GPIOB2-3 pins.

⁴The Fault2 signal is also brought out on the GPIOA8-9, GPIOB4 and GPIOB10 pins.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

26

FreescaleSemiconductor

56F8037/56F8027 Signal Pins

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOA6

34

Input/

Output

Input,

internal

pull-up

enabled

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(FAULT0)

(TA0⁵)

Input

Fault0 — This fault input pin is used for disabling selected PWM

outputs in cases where fault conditions originate off-chip.

TA0 — Timer A, Channel 0.

After reset, the default state is GPIOA6. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

⁵The TA0 signal is also brought out on the GPIOB4 pin.

GPIOA8

36

Input/

Output

Input,

internal

pull-up

enabled

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(FAULT1)

(TA2)

Input

Fault1 — This fault input pin is used for disabling selected PWM

outputs in cases where fault conditions originate off-chip.

Input/

TA2 — Timer A, Channel 2.

Output

(CMPAI1)

Input

Comparator A, Input 1 — This is an analog input to Comparator A.

After reset, the default state is GPIOA8. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

GPIOA9

5

Input/

Output

Input,

internal

pull-up

enabled

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(FAULT2)

(TA3)

Input

Fault2 — This fault input pin is used for disabling selected PWM

outputs in cases where fault conditions originate off-chip.

Input/

TA2 — Timer A, Channel 3.

Output

(CMPBI1)

Input

Comparator B, Input 1 — This is an analog input to Comparator B.

After reset, the default state is GPIOA9. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

27

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOA10

35

Input/

Output

Input,

internal

pull-up

enabled

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(TB2⁶)

Input/

Output

TB2 — Timer B, Channel 2.

Input

Comparator A, Input 2 — This is an analog input to Comparator A.

(CMPAI2)

After reset, the default state is GPIOA10. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

⁶The TB2 signal is also brought out on the GPIOA13 pin.

GPIOA11

6

Input/

Output

Input,

internal

pull-up

enabled

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(TB3⁷)

Input/

Output

TB3 — Timer B, Channel 3.

Input

Comparator B, Input 2 — This is an analog input to Comparator B.

(CMPBI2)

After reset, the default state is GPIOA11. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

⁷The TB3 signal is also brought out on the GPIOA14 pin.

GPIOA12

37

Input/

Output

Input,

internal

pull-up

enabled

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(SCLK1)

Input/

Output

QSPI1 Serial Clock — In the master mode, this pin serves as an

output, clocking slaved listeners. In slave mode, this pin serves as

the data clock input. A Schmitt trigger input is used for noise

immunity.

(TB1⁸)

(TA1⁹)

Input/

Output

TB1 — Timer B, Channel 1.

TA1 — Timer A, Channel 1.

Input/

Output

After reset, the default state is GPIOA12. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

⁸The TB1 signal is also brought out on the GPIOB11 pin.

⁹The TA1 signal is also brought out on the GPIOB5 pin.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

28

FreescaleSemiconductor

56F8037/56F8027 Signal Pins

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOA13

44

Input/

Output

Input,

internal

pull-up

enabled

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(MISO1)

Input/

Output

QSPI1 Master In/Slave Out— This serial data pin is an input to a

master device and an output from a slave device. The MISO line of a

slave device is placed in the high-impedance state if the slave device

is not selected. The slave device places data on the MISO line a

half-cycle before the clock edge the master devices uses to latch the

data.

(TB2¹⁰

)

Input/

Output

TB2 — Timer B, Channel 2.

TA2 — Timer A, Channel 2.

Input/

Output

(TA2¹¹

After reset, the default state is GPIOA13. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

¹⁰The TB2 signal is also brought out on the GPIOA10 pin.

¹¹The TA2 signal is also brought out on the GPIOA4, GPIOA8 and GPIOB2 pins.

GPIOA14

45

Input/

Output

Input,

internal

pull-up

enabled

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(MOSI1)

Input/

Output

QSPI1 MasterOut/Slave In — This serial data pin is an output from

a master device and an input to a slave device. The master device

places data on the MOSI line a half-cycle before the clock edge the

slave devices uses to latch the data.

TB3 — Timer B, Channel 3.

TA3 — Timer A, Channel 3.

(TB3¹²

)

Input/

Output

Input/

Output

After reset, the default state is GPIOA14. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

(TA3¹³

¹²The TB3 signal is also brought out on the GPIOA11 pin.

¹³The TA3 signal is also brought out on the GPIOA5, GPIOA9, and GPIOB3 pins.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

29

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOB0

42

Input/

Output

Input,

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(SCLK0)

Input/

Output

QSPI0 Serial Clock — In the master mode, this pin serves as an

output, clocking slaved listeners. In slave mode, this pin serves as

the data clock input. A Schmitt trigger input is used for noise

immunity.

(SCL¹⁴

)

Serial Clock — This pin serves as the I²C serial clock.

Input/

Output

After reset, the default state is GPIOB0. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

¹⁴The SCL signal is also brought out on the GPIOB7 and GPIOB8 pins.

GPIOB1

2

Input/

Output

Input,

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(SS0)

Input/

QSPI0 Slave Select — SS is used in slave mode to indicate to the

Output

QSPI0 module that the current transfer is to be received.

(SDA¹⁵

)

Serial Data — This pin serves as the I²C serial data line.

Input

After reset, the default state is GPIOB1. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

¹⁵The SDA signal is also brought out on the GPIOB6 and GPIOB9 pins.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

30

FreescaleSemiconductor

56F8037/56F8027 Signal Pins

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOB2

33

Input/

Output

Input,

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(MISO0)

Input/

Output

QSPI0 Master In/Slave Out — This serial data pin is an input to a

master device and an output from a slave device. The MISO line of a

slave device is placed in the high-impedance state if the slave device

is not selected. The slave device places data on the MISO line a

half-cycle before the clock edge the master device uses to latch the

data.

(TA2¹⁶

)

Input/

Output

TA2 — Timer A, Channel 2

Input

PSRC0 — External PWM signal source input for the complementary

PWM4/PWM5 pair.

(PSRC0)

After reset, the default state is GPIOB2. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

¹⁶The TA2 signal is also brought out on the GPIOA4, GPIOA8 and GPIOA13 pins.

GPIOB3

32

Input/

Output

Input,

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(MOSI0)

Input/

Output

QSPI0 Master Out/Slave In— This serial data pin is an output from

a master device and an input to a slave device. The master device

places data on the MOSI line a half-cycle before the clock edge the

slave device uses to latch the data.

(TA3¹⁷

)

Input/

Output

TA3 — Timer A, Channel 3

Input

PSRC1 — External PWM signal source input for the complementary

PWM2/PWM3 pair.

(PSRC1)

After reset, the default state is GPIOB3. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

¹⁷The TA3 signal is also brought out on the GPIOA5, GPIOA9 and GPIOA14 pins.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

31

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOB4

38

Input/

Output

Input,

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(SS1)

Input/

QSPI1 Slave Select — This is used in slave mode to indicate to the

Output

QSPI1 module that the current transfer is to be received.

(TB0¹⁸

)

Input/

Output

TB0 — Timer B, Channel 0

TA0 — Timer A, Channel 0

Input/

Output

(TA0¹⁹

Input

PSRC2 — External PWM signal source input for the complementary

PWM0/PWM1 pair.

(PSRC2)

(CLKO)

Output

Clock Output — This is a buffered clock output; the clock source is

selected by Clockout Select (CLKOSEL) bits in the Clock Output

Select Register (CLKOUT). See Section 6.3.7.

After reset, the default state is GPIOB4. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

¹⁸The TB0 signal is also brought out on the GPIOB4 and GPIOB10 pins.

¹⁹The TA0 signal is also brought out on the GPIOB4 and GPIOA6 pins.

GPIOB5

4

Input/

Output

Input,

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(TA1²⁰

)

Input/

Output

TA1 — Timer A, Channel 1

Input

FAULT3 — This fault input pin is used for disabling selected PWM

outputs in cases where fault conditions originate off-chip.

(FAULT3)

(CLKIN)

External Clock Input— This pin serves as an external clock input.

After reset, the default state is GPIOB5. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

²⁰The TA1 signal is also brought out on the GPIOA12 pin.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

32

FreescaleSemiconductor

56F8037/56F8027 Signal Pins

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOB6

1

Input/

Output

Input,

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(RXD0)

Input

Receive Data 0 — QSCI0 receive data input.

(SDA²¹

)

Serial Data — This pin serves as the I²C serial data line.

Input/

Output

Input

(CLKIN)

External Clock Input — This pin serves as an optional external

clock input.

After reset, the default state is GPIOB6. The peripheral functionality

is controlled via the SIM (See Section 6.3.16) and the CLKMODE bit

of the OCCS Oscillator Control Register.

²¹The SDA signal is also brought out on the GPIOB1 and GPIOB9 pins.

GPIOB7

3

Input/

Output

Input,

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Transmit Data 0 — QSCI0 transmit data output or transmit / receive

(TXD0)

Input/

in single wire operation.

Output

Serial Clock — This pin serves as the I²C serial clock.

(SCL²²

)

Input/

Output

After reset, the default state is GPIOB7. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

²²The SCL signal is also brought out on the GPIOB0 and GPIOB8 pins.

GPIOB8

54

Input/

Output

Input,

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(SCL²³

)

Serial Clock 1 — This pin serves as the I²C serial clock.

CAN Transmit Data — This is the SCAN interface output.

Input/

Output

Open Drain

Output

(CANTX²⁴

)

After reset, the default state is GPIOB8. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

²³The SCL signal is also brought out on the GPIOB0 and GPIOB7 pins.

²⁴The CANTX signal is also brought out on the GPIOB12 pin.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

33

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOB9

46

Input/

Output

Input,

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(SDA²⁵

)

Serial Data 1 — This pin serves as the I²C serial data line.

CAN Receive Data — This is the MSCAN interface input.

Input/

Output

Input

(CANRX²⁶

)

After reset, the default state is GPIOB9. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

²⁵The SDA signal is also brought out on the GPIOB1 and GPIOB6 pins.

²⁶The CANRX signal is also brought out on the GPIOB13 pin.

GPIOB10

30

Input/

Output

Input,

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(TB0²⁷

)

Input/

Output

TB0— Timer B, Channel 0.

Output

Comparator A Output— This is the output of comparator A.

(CMPAO)

After reset, the default state is GPIOB10. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

²⁷The TB0 signal is also brought out on the GPIOB4 pin.

GPIOB11

60

Input/

Output

Input,

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

(TB1²⁸

)

Input/

Output

TB1— Timer B, Channel 1.

Output

Comparator B Output— This is the output of comparator B.

(CMPBO)

After reset, the default state is GPIOB11. The peripheral functionality

is controlled via the SIM. See Section 6.3.16.

²⁸The TB1 signal is also brought out on the GPIOA12 pin.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

34

FreescaleSemiconductor

56F8037/56F8027 Signal Pins

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOB12

57

Input/

Input

Port B GPIO — This GPIO pin can be individually programmed as

Output

an input or output pin.

(CANTX²⁹

)

Open Drain

Output

CAN Transmit Data — This is the MSCAN interface output.

After reset, the default state is GPIOB12.

²⁹The CANTX signal is also brought out on the GPIOB8 pin.

GPIOB13

58

Input/

Input

Port B GPIO — This GPIO pin can be individually programmed as

Output

an input or output pin.

(CANRX³⁰

)

Input

CAN Receive Data — This is the MSCAN interface input.

After reset, the default state is GPIOB13.

³⁰The CANRX signal is also brought out on the GPIOB9 pin.

GPIOC0

24

Input/

Input

Port C GPIO — This GPIO pin can be individually programmed as

Output

an input or output pin.

(ANA0 &

CMPAI3)

Analog

Input

ANA0 — Analog input to ADC A, Channel 0.

Comparator A, Input 3 — This is an analog input to Comparator A.

When used as an analog input, the signal goes to both ANA0 and

CMPAI3.

After reset, the default state is GPIOC0.

GPIOC1

(ANA1)

22

20

Input/

Output

Input

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

ANA1 — Analog input to ADC A, Channel 1.

After reset, the default state is GPIOC1.

GPIOC2

(ANA2)

Input/

Output

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

ANA2 — Analog input to ADC A, Channel 2.

(V_REFHA

)

Analog

Input

V_REFHA— Analog reference voltage high (ADC A).

After reset, the default state is GPIOC2.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

35

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOC3

(ANA3)

19

Input/

Output

Input

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

ANA3 — Analog input to ADC A, Channel 3.

(V_REFLA

)

Analog

Input

V_REFLA— Analog reference voltage low. (ADC A).

After reset, the default state is GPIOC3.

GPIOC4

10

Input/

Input

Port C GPIO — This GPIO pin can be individually programmed as

Output

an input or output pin.

(ANB0 &

CMPBI3)

Analog

Input

ANB0 — Analog input to ADC B, Channel 0.

Comparator B, Input 3 — This is an analog input to Comparator B.

Analog

Input

When used an analog input, the signal goes to both ANB0 and

CMPB13.

After reset, the default state is GPIOC4.

GPIOC5

(ANB1)

11

13

Input/

Output

Input

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

ANB1 — Analog input to ADC B, Channel 1.

After reset, the default state is GPIOC5.

GPIOC6

(ANB2)

Input/

Output

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

ANB2 — Analog input to ADC B, Channel 2.

(V_REFHB

)

Input

V_REFHx— Analog reference voltage high (ADC B).

After reset, the default state is GPIOC6.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

36

FreescaleSemiconductor

56F8037/56F8027 Signal Pins

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOC7

(ANB3)

14

Input/

Output

Input

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

ANB3 — Analog input to ADC B, Channel 3.

(V_REFLB

)

Input

V_REFLB— Analog reference voltage low (ADC B).

After reset, the default state is GPIOC7.

GPIOC8

(ANA4)

(TXD1)

26

Input/

Output

Input

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

ANA4 — Analog input to ADC A, Channel 4.

Input/

Transmit Data 1 — SCI1 transmit data output.

Output

After reset, the default state is GPIOC8.

GPIOC9

(ANA5)

21

23

25

Input/

Output

Input

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

ANA5 — Analog input to ADC A, Channel 5.

After reset, the default state is GPIOC9.

GPIOC10

(ANA6)

Input/

Output

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

ANA6 — Analog input to ADC A, Channel 6.

After reset, the default state is GPIOC10.

GPIOC11

(ANA7)

Input/

Output

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

ANA7 — Analog input to ADC A, Channel 7.

After reset, the default state is GPIOC11.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

37

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOC12

(ANB4)

(RXD1)

9

Input/

Output

Input

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

ANB4 — Analog input to ADC B, Channel 4.

Input

Receive Data 1 — SCI1 receive data input.

After reset, the default state is GPIOC12.

GPIOC13

(ANB5)

12

62

61

53

Input/

Output

Input

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

ANB5 — Analog input to ADC B, Channel 5.

After reset, the default state is GPIOC13.

GPIOC14

(ANB6)

Input/

Output

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

ANB6 — Analog input to ADC B, Channel 6.

After reset, the default state is GPIOC14.

GPIOC15

(ANB7)

Input/

Output

Port C GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

ANB7 — Analog input to ADC B, Channel 7.

After reset, the default state is GPIOC15.

GPIOD4

(EXTAL)

Input/

Output

Port D GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

External Crystal Oscillator Input — This input can be connected to

an 8MHz external crystal. Tie this pin low if XTAL is being driven by

an external clock source.

After reset, the default state is GPIOD4.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

38

FreescaleSemiconductor

56F8037/56F8027 Signal Pins

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

GPIOD5

(XTAL)

52

Input/

Output

Input

Port D GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input/

External Crystal Oscillator Output — This output connects the

internal crystal oscillator output to an external crystal.

Output

(CLKIN)

Input

External Clock Input — This pin serves as an external clock input.

After reset, the default state is GPIOD5.

GPIOD6

(DAC0)

18

15

59

Input/

Output

Input,

internal

pull-up

enabled

Port D GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

DAC0— Digital-to-Analog Converter output 0.

After reset, the default state is GPIOD6.

GPIOD7

(DAC1)

Input/

Output

Input,

internal

pull-up

enabled

Port D GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Analog

Input

DAC1— Digital-to-Analog Converter output 1.

After reset, the default state is GPIOD7.

TDI

Input

Input,

internal

pull-up

enabled

Test Data Input — This input pin provides a serial input data stream

to the JTAG/EOnCE port. It is sampled on the rising edge of TCK

and has an on-chip pull-up resistor.

(GPIOD0)

Input/

Port D GPIO — This GPIO pin can be individually programmed as

Output

an input or output pin.

After reset, the default state is TDI.

TDO

64

Output

Test Data Output — This tri-stateable output pin provides a serial

tri-stated, output data stream from the JTAG/EOnCE port. It is driven in the

internal

pull-up

shift-IR and shift-DR controller states, and changes on the falling

edge of TCK.

enabled

(GPIOD1)

Input/

Port D GPIO — This GPIO pin can be individually programmed as

Output

an input or output pin.

After reset, the default state is TDO.

Return to Table 2-2

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

39

Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

StateDuring

Reset

Type

Signal Description

TCK

29

Input

Input,

internal

pull-up

enabled

Test Clock Input — This input pin provides a gated clock to

synchronize the test logic and shift serial data to the JTAG/EOnCE

port. The pin is connected internally to a pull-up resistor. A Schmitt

trigger input is used for noise immunity.

(GPIOD2)

Input/

Port D GPIO — This GPIO pin can be individually programmed as

Output

an input or output pin.

After reset, the default state is TCK.

TMS

63

Input

Input,

internal

pull-up

enabled

Test Mode Select Input — This input pin is used to sequence the

JTAG TAP controller’s state machine. It is sampled on the rising

edge of TCK and has an on-chip pull-up resistor.

(GPIOD3)

Input/

Port D GPIO — This GPIO pin can be individually programmed as

Output

an input or output pin.

After reset, the default state is TMS.

Note: Always tie the TMS pin to V_DDthrough a 2.2K resistor.

Return to Table 2-2

Part 3 OCCS

3.1 Overview

The On-Chip Clock Synthesis (OCCS) module allows designers using an internal relaxation oscillator, an

external crystal, or an external clock to run 56F8000 family devices at user-selectable frequencies up to

32MHz. For details, see the OCCS chapter in the 56F802x and 56F803x Peripheral Reference Manual.

56F8037/56F8027 Data Sheet, Rev. 8

40

FreescaleSemiconductor

Features

3.2 Features

The OCCS module interfaces to the oscillator and PLL and offers these features:

•

Internal relaxation oscillator

Ability to power down the internal relaxation oscillator or crystal oscillator

Ability to put the internal relaxation oscillator into Standby mode

3-bit postscaler provides control for the PLL output

Ability to power down the PLL

Provides a 2X system clock which operates at twice the system clock to the System Integration Module

(SIM)

•

Provides a 3X system clock which operates at three times the system clock to PWM and Timer modules

Safety shutdown feature is available if the PLL reference clock is lost

Can be driven from an external clock source

The clock generation module provides the programming interface for the PLL, internal relaxation

oscillator, and crystal oscillator.

3.3 Operating Modes

In 56F8000 family devices, an internal oscillator, an external crystal, or an external clock source can be

used to provide a reference clock to the SIM.

The 2X system clock source output from the OCCS can be described by one of the following equations:

2X system frequency = oscillator frequency

2X system frequency = (oscillator frequency x 8) / (postscaler)

where:

postscaler = 1, 2, 4, 8, 16, or 32

The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle

in the system clock output.

The 56F8000 family devices’ on-chip clock synthesis module has the following registers:

•

Control Register (OCCS_CTRL)

Divide-by Register (OCCS_DIVBY)

Status Register (OCCS_STAT)

Shutdown Register (OCCS_SHUTDN)

Oscillator Control Register (OCCS_OCTRL)

For more information on these registers, please refer to the 56F802x and 56F803x Peripheral Reference

Manual.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

41

3.4 Internal Clock Source

An internal relaxation oscillator can supply the reference frequency when an external frequency source or

crystal is not used. It is optimized for accuracy and programmability while providing several power-saving

configurations which accommodate different operating conditions. The internal relaxation oscillator has

very little temperature and voltage variability. To optimize power, the architecture supports a standby state

and a power-down state.

During a boot or reset sequence, the relaxation oscillator is enabled by default (the PRECS bit in the

PLLCR word is set to 0). Application code can then also switch to the external clock source and power

down the internal oscillator, if desired. If a changeover between internal and external clock sources is

required at power-on, the user must ensure that the clock source is not switched until the desired external

clock source is enabled and stable.

To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator

can be incrementally adjusted to within + 0.078% of 8MHz by trimming an internal capacitor. Bits 0-9 of

the OSCTL (oscillator control) register allow the user to set in an additional offset (trim) to this preset

value to increase or decrease capacitance. Each unit added or subtracted changes the output frequency by

about 0.078% of 8MHz, allowing incremental adjustment until the desired frequency accuracy is achieved.

The center frequency of the internal oscillator is calibrated at the factory to 8MHz and the TRIM value is

stored in the Flash information block and loaded to the FMOPT1 register at reset. When using the

relaxation oscillator, the boot code should read the FMOPT1 register and set this value as OSCTL TRIM.

For further information, see the 56F802x and 56F803x Peripheral Reference Manual.

3.5 Crystal Oscillator

The internal crystal oscillator circuit is designed to interface with a parallel-resonant crystal resonator in a

frequency range of 4-8MHz, specified for the external crystal. Figure 3-1 shows a typical crystal oscillator

circuit. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal parameters

determine the component values required to provide maximum stability and reliable start-up. The load

capacitance values used in the oscillator circuit design should include all stray layout capacitances. The

crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins

to minimize output distortion and start-up stabilization time.

56F8037/56F8027 Data Sheet, Rev. 8

42

FreescaleSemiconductor

Ceramic Resonator

Crystal Frequency = 4 - 8MHz (optimized for 8MHz)

EXTAL XTAL

R_z

EXTAL XTAL

R_z

Sample External Crystal Parameters:

R_z= 750 K

Note: If the operating temperature range is limited to

below 85^oC (105^oC junction), then R_z= 10 Meg 

CL1

CL2

Figure 3-1 External Crystal Oscillator Circuit

3.6 Ceramic Resonator

The internal crystal oscillator circuit is also designed to interface with a ceramic resonator in the frequency

range of 4-8MHz. Figure 3-2 shows the typical 2 and 3 terminal ceramic resonators and their circuits.

Follow the resonator supplier’s recommendations when selecting a resonator, since their parameters

determine the component values required to provide maximum stability and reliable start up. The load

capacitance values used in the resonator circuit design should include all stray layout capacitances. The

resonator and associated components should be mounted as near as possible to the EXTAL and XTAL pins

to minimize output distortion and start-up stabilization time.

Resonator Frequency = 4 - 8MHz (optimized for 8MHz)

3 Terminal

2 Terminal

EXTAL XTAL

R_z

Sample External Ceramic Resonator Parameters:

R_z= 750 K

EXTAL XTAL

R_z

CL1

CL2

C1

C2

Figure 3-2 External Ceramic Resonator Circuit

3.7 External Clock Input - Crystal Oscillator Option

The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock

source is connected to XTAL and the EXTAL pin is grounded. The external clock input must be generated

using a relatively low impedance driver.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

43

56F8037/56F8027

CLKMODE = 1

XTAL

EXTAL

External

Clock

GND or

GPIO

Figure 3-3 Connecting an External Clock Signal using XTAL

3.8 Alternate External Clock Input

The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock

source is connected to GPIO6/RXD (primary) or GPIOB5/TA1/FAULT3/XTAL/EXTAL (secondary).

The user has the option of using GPIO6/RXD/CLKIN or GPIOB5/TA1/FAULT3/CLKIN as external

clock input.

56F8037/56F8027

GPIO

ExternalClock

Figure 3-4 Connecting an External Clock Signal using GPIO

Part 4 Memory Maps

4.1 Introduction

The 56F8037/56F8027 device is a 16-bit motor-control chip based on the 56800E core. It uses a

Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM is

shared by both spaces and Flash memory is used only in Program space.

This section provides memory maps for:

•

Program Address Space, including the Interrupt Vector Table

Data Address Space, including the EOnCE Memory and Peripheral Memory Maps

On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are

identified in the “Use Restrictions” column of Table 4-1.

56F8037/56F8027 Data Sheet, Rev. 8

44

FreescaleSemiconductor

Interrupt Vector Table

Table 4-1 Chip Memory Configurations

On-Chip Memory

56F8037

56F8027

Use Restrictions

Erase / Program via Flash interface unit and word writes to CDBW

Program Flash

(PFLASH)

32k x 16

or

16k x 16

or

64KB

32KB

Unified RAM (RAM)

4k x 16

or

2k x 16

or

Usable by both the Program and Data memory spaces

8KB

4KB

4.2 Interrupt Vector Table

Table 4-2 provides the 56F8037/56F8027’s reset and interrupt priority structure, including on-chip

peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts

lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing

some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For

a selected priority level, the lowest vector number has the highest priority.

The location of the vector table is determined by the Vector Base Address (VBA). Please see Section 5.6.8

for the reset value of the VBA.

By default, the chip reset address and COP reset address will correspond to vector 0 and 1 of the interrupt

vector table. In these instances, the first two locations in the vector table must contain branch or JMP

instructions. All other entries must contain JSR instructions.

1

Table 4-2 Interrupt Vector Table Contents

Vector

Number

Priority

Level

Vector Base

Address +

Peripheral

Interrupt Function

Reserved for Reset Overlay²

core

P:$00

core

P:$02

P:$04

P:$06

P:$08

P:$0A

P:$0C

P:$0E

P:$10

P:$12

P:$14

P:$16

P:$18

P:$1A

Reserved for COP Reset Overlay

Illegal Instruction

2

3

4

5

6

7

8

9

3

SW Interrupt 3

HW Stack Overflow

Misaligned Long Word Access

EOnCE Step Counter

EOnCE Breakpoint Unit

EOnCE Trace Buffer

EOnCE Transmit Register Empty

EOnCE Receive Register Full

SW Interrupt 2

1-3

2

10

11

12

13

14

1

SW Interrupt 1

0

SW Interrupt 0

Reserved

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

45

1

Table 4-2 Interrupt Vector Table Contents (Continued)

Vector

Number

Priority

Level

Vector Base

Address +

Peripheral

Interrupt Function

LVI

15

1-3

P:$1E

P:$20

P:$22

P:$24

P:$26

P:$28

P:$2a

P:$2C

P:$2E

P:$30

P:$32

P:$34

P:$36

P:$38

P:$3A

P:$3C

P:$3E

P:$40

P:$42

P:$44

P:$46

P:$48

P:$4A

P:$4C

P:$4E

P:$50

Low-Voltage Detector (Power Sense)

Phase-Locked Loop

FM Access Error Interrupt

FM Command Complete

FM Command, Data, and Address Buffers Empty

MSCAN Error

PLL

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

1-3

0-2

FM

MSCAN

GPIOD

GPIOC

GPIOB

GPIOA

QSPI0

QSPI1

QSCI0

QSCI1

I2C

MSCAN Receive

MSCAN Transmit

MSCAN Wake-Up

GPIOD

GPIOC

GPIOB

GPIOA

QSPI0 Receiver Full

QSPI0 Transmitter Empty

QSPI1 Receiver Full

QSPI1 Transmitter Empty

QSCI0 Transmitter Empty

QSCI0 Transmitter Idle

QSCI0 Receiver Error

QSCI0 Receiver Full

QSCI1 Transmitter Empty

QSCI1 Transmitter Idle

QSCI1 Receiver Error

QSCI1 Receiver Full

I²C Error

I²C General

I²C Receive

I²C Transmit

I2C

41

42

43

44

0-2

P:$52

P:$54

P:$56

P:$58

I²C Status

TMRA

TMRB

45

46

47

48

49

50

51

52

0-2

P:$5A

P:$5C

P:$5E

P:$60

P:$62

P:$64

P:$66

P:$68

Timer A, Channel 0

Timer A, Channel 1

Timer A, Channel 2

Timer A, Channel 3

Timer B, Channel 0

Timer B, Channel 1

Timer B, Channel 2

Timer B, Channel 3

56F8037/56F8027 Data Sheet, Rev. 8

46

FreescaleSemiconductor

Program Map

1

Table 4-2 Interrupt Vector Table Contents (Continued)

Vector

Number

Priority

Level

Vector Base

Address +

Peripheral

Interrupt Function

CMPA

CMPB

PIT0

53

0-2

P:$6A

P:$6C

P:$6E

P:$70

P:$72

P:$74

P:$76

P:$78

P:$7A

P:$7C

P:$7E

Comparator A

Comparator B

Interval Timer 0

Interval Timer 1

Interval Timer 2

54

55

56

57

58

59

60

61

62

63

0-2

-1

PIT1

PIT2

ADC

ADC A Conversion Complete

ADC B Conversion Complete

ADC Zero Crossing or Limit Error

Reload PWM

ADC

PWM

SWILP

PWM Fault

SW Interrupt Low Priority

1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced

from the vector table, providing only 19 bits of address.

2. If the VBA is set to the reset value, the first two locations of the vector table will overlay the chip reset addresses since

the reset address would match the base of this vector table.

4.3 Program Map

The Program Memory map is shown in Table 4-3 and Table 4-4.

1

Table 4-3 Program Memory Map at Reset for 56F8037

Begin/End Address

Memory Allocation

P: $1F FFFF

RESERVED

P: $00 9000

On-Chip RAM²

8KB

P: $00 8FFF

P: $00 8000

P: $00 7FFF

P: $00 0000

Internal Program Flash

64KB

Cop Reset Address = $00 0002

Boot Location = $00 0000

1. All addresses are 16-bit Word addresses.

2. This RAM is shared with Data space starting at address X: $00 0000; see Figure 4-1.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

47

1

Table 4-4 Program Memory Map at Reset for 56F8027

Begin/End Address

Memory Allocation

P: $1F FFFF

RESERVED

P: $00 8800

On-Chip RAM²

4KB

P: $00 87FF

P: $00 8000

P: $00 7FFF

P: $00 4000

Internal Program Flash

32KB

Cop Reset Address = $00 4002

Boot Location = $00 4000

P: $00 3FFF

P: $00 0000

RESERVED

1. All addresses are 16-bit Word addresses.

2. This RAM is shared with Data space starting at address X: $00 0000; see Figure 4-2.

4.4 Data Map

1

Table 4-5 Data Memory Map for 56F8037

Begin/End Address

Memory Allocation

X:$FF FFFF

EOnCE

X:$FF FF00

256 locations allocated

X:$FF FEFF

X:$01 0000

RESERVED

X:$00 FFFF

X:$00 F000

On-Chip Peripherals

4096 locations allocated

X:$00 EFFF

X:$00 9000

RESERVED

X:$00 8FFF

X:$00 8000

X:$00 7FFF

X:$00 1000

X:$00 0FFF

X:$00 0000

On-Chip Data RAM

8KB²

1. All addresses are 16-bit Word addresses.

2. This RAM is shared with Program space starting at P: $00 8000; see Figure 4-1.

56F8037/56F8027 Data Sheet, Rev. 8

48

FreescaleSemiconductor

Data Map

Program

Data

EOnCE

Reserved

RAM

Peripherals

Reserved

RAM

Dual Port RAM

Flash

Figure 4-1 Dual Port RAM for 56F8037

Table 4-6 Data Memory Map for 56F8027

1

Begin/End Address

Memory Allocation

X:$FF FFFF

EOnCE

X:$FF FF00

256 locations allocated

X:$FF FEFF

X:$01 0000

RESERVED

X:$00 FFFF

X:$00 F000

On-Chip Peripherals

4096 locations allocated

X:$00 EFFF

X:$00 9000

RESERVED

X:$00 8FFF

X:$00 8000

X:$00 7FFF

X:$00 0800

X:$00 07FF

X:$00 0000

On-Chip Data RAM

4KB²

1. All addresses are 16-bit Word addresses.

2. This RAM is shared with Program space starting at P: $00 8000; see Figure 4-2.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

49

Program

Data

EOnCE

Reserved

RAM

Flash

Peripherals

Reserved

RAM

Dual Port RAM

Reserved

Figure 4-2 Dual Port RAM for 56F8027

4.5 EOnCE Memory Map

Figure 4-7 lists all EOnCE registers necessary to access or control the EOnCE.

Table 4-7 EOnCE Memory Map

Address

X:$FF FFFF

Register Acronym

Register Name

OTX1 / ORX1

Transmit Register Upper Word

Receive Register Upper Word

X:$FF FFFE

OTX / ORX (32 bits)

Transmit Register

Receive Register

X:$FF FFFD

X:$FF FFFC

X:$FF FFFB - X:$FF FFA1

X:$FF FFA0

X:$FF FF9F

X:$FF FF9E

X:$FF FF9D

X:$FF FF9C

X:$FF FF9B

X:$FF FF9A

X:$FF FF99

X:$FF FF98

X:$FF FF97

X:$FF FF96

X:$FF FF95

X:$FF FF94

X:$FF FF93

OTXRXSR

OCLSR

Transmit and Receive Status and Control Register

Core Lock / Unlock Status Register

Reserved

OCR

Control Register

Instruction Step Counter

OSCNTR (24 bits)

OSR

Instruction Step Counter

Status Register

OBASE

Peripheral Base Address Register

Trace Buffer Control Register

Trace Buffer Pointer Register

Trace Buffer Register Stages

OTBCR

OTBPR

OTB (21 - 24 bits/stage) Trace Buffer Register Stages

Breakpoint Unit Control Register

OBCR (24 bits)

Breakpoint Unit Control Register

Breakpoint Unit Address Register 1

Breakpoint Unit Address Register 2

OBAR1 (24 bits)

56F8037/56F8027 Data Sheet, Rev. 8

50

FreescaleSemiconductor

Peripheral Memory-Mapped Registers

Table 4-7 EOnCE Memory Map (Continued)

Address

X:$FF FF92

Register Acronym

Register Name

Breakpoint Unit Address Register 2

OBAR2 (32 bits)

X:$FF FF91

Breakpoint Unit Mask Register 2

Reserved

X:$FF FF90

OBMSK (32 bits)

OBCNTR

X:$FF FF8F

X:$FF FF8E

EOnCE Breakpoint Unit Counter

Reserved

X:$FF FF8D

X:$FF FF8C

Reserved

X:$FF FF8B

Reserved

X:$FF FF8A

OESCR

External Signal Control Register

Reserved

X:$FF FF89 - X:$FF FF00

4.6 Peripheral Memory-Mapped Registers

On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may

be accessed with the same addressing modes used for ordinary Data memory, except all peripheral

registers should be read or written using word accesses only.

Table 4-8 summarizes base addresses for the set of peripherals on the 56F8037/56F8027 device.

Peripherals are listed in order of the base address.

The following tables list all of the peripheral registers required to control or access the peripherals.

Table 4-8 Data Memory Peripheral Base Address Map Summary

Peripheral

Prefix

Base Address

Table Number

Timer A

Timer B

ADC

TMRA

TMRB

ADC

X:$00 F000

X:$00 F040

X:$00 F080

X:$00 F0C0

X:$00 F0E0

X:$00 F100

X:$00 F120

X:$00 F130

X:$00 F140

X:$00 F150

X:$00 F160

X:$00 F170

X:$00 F180

X:$00 F190

X:$00 F1A0

X:$00 F1B0

4-9

4-10

4-11

4-12

4-13

4-14

4-15

4-16

4-17

4-18

4-19

4-20

4-21

4-22

4-23

4-24

PWM

ITCN

SIM

PWM

ITCN

SIM

COP

CLK, PLL, OSC

Power Supervisor

GPIO Port A

GPIO Port B

GPIO Port C

GPIO Port D

PIT 0

OCCS

PS

GPIOA

GPIOB

GPIOC

GPIOD

PIT0

PIT 1

PIT1

PIT 2

PIT2

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

51

Table 4-8 Data Memory Peripheral Base Address Map Summary (Continued)

Peripheral

Prefix

Base Address

Table Number

DAC 0

DAC 1

DAC0

DAC1

CMPA

CMPB

QSCI0

QSCI1

QSPI0

QSPI1

I2C

X:$00 F1C0

X:$00 F1D0

X:$00 F1E0

X:$00 F1F0

X:$00 F200

X:$00 F210

X:$00 F220

X:$00 F230

X:$00 F280

4-25

4-26

4-27

4-28

4-29

4-30

4-31

4-32

4-33

Comparator A

Comparator B

QSCI 0

QSCI 1

QSPI 0

QSPI 1

I²C

FM

X:$00 F400

X:$00 F800

4-34

4-35

MSCAN

CAN

56F8037/56F8027 Data Sheet, Rev. 8

52

FreescaleSemiconductor

Peripheral Memory-Mapped Registers

Table 4-9 Quad Timer A Registers Address Map

(TMRA_BASE = $00 F000)

Register Acronym

Address Offset

$0

Register Description

Compare Register 1

TMRA0_COMP1

TMRA0_COMP2

TMRA0_CAPT

TMRA0_LOAD

TMRA0_HOLD

TMRA0_CNTR

TMRA0_CTRL

TMRA0_SCTRL

TMRA0_CMPLD1

TMRA0_CMPLD2

TMRA0_CSCTRL

TMRA0_FILT

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

Compare Register 2

Capture Register

Load Register

Hold Register

Counter Register

Control Register

Status and Control Register

Comparator Load Register 1

Comparator Load Register 2

Comparator Status and Control Register

Input Filter Register

Reserved

TMRA0_ENBL

TMRA1_COMP1

TMRA1_COMP2

TMRA1_CAPT

TMRA1_LOAD

TMRA1_HOLD

TMRA1_CNTR

TMRA1_CTRL

TMRA1_SCTRL

TMRA1_CMPLD1

TMRA1_CMPLD2

TMRA1_CSCTRL

TMRA1_FILT

$F

Timer Channel Enable Register

Compare Register 1

Compare Register 2

Capture Register

$10

$11

$12

$13

$14

$15

$16

$17

$18

$19

$1A

$1B

Load Register

Hold Register

Counter Register

Control Register

Status and Control Register

Comparator Load Register 1

Comparator Load Register 2

Comparator Status and Control Register

Input Filter Register

Reserved

TMRA2_COMP1

TMRA2_COMP2

TMRA2_CAPT

TMRA2_LOAD

TMRA2_HOLD

TMRA2_CNTR

TMRA2_CTRL

TMRA2_SCTRL

TMRA2_CMPLD1

$20

$21

$22

$23

$24

$25

$26

$27

$28

Compare Register 1

Compare Register 2

Capture Register

Load Register

Hold Register

Counter Register

Control Register

Status and Control Register

Comparator Load Register 1

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

53

Table 4-9 Quad Timer A Registers Address Map (Continued)

(TMRA_BASE = $00 F000)

Register Acronym

Address Offset

Register Description

Comparator Load Register 2

TMRA2_CMPLD2

TMRA2_CSCTRL

TMRA2_FILT

$29

$2A

$2B

Comparator Status and Control Register

Input Filter Register

Reserved

TMRA3_COMP1

TMRA3_COMP2

TMRA3_CAPT

TMRA3_LOAD

TMRA3_HOLD

TMRA3_CNTR

TMRA3_CTRL

TMRA3_SCTRL

TMRA3_CMPLD1

TMRA3_CMPLD2

TMRA3_CSCTRL

TMRA3_FILT

$30

$31

$32

$33

$34

$35

$36

$37

$38

$39

$3A

$3B

Compare Register 1

Compare Register 2

Capture Register

Load Register

Hold Register

Counter Register

Control Register

Status and Control Register

Comparator Load Register 1

Comparator Load Register 2

Comparator Status and Control Register

Input Filter Register

Reserved

Table 4-10 Quad Timer B Registers Address Map

(TMRB_BASE = $00 F040)

Register Acronym

Address Offset

Register Description

Compare Register 1

TMRB0_COMP1

TMRB0_COMP2

TMRB0_CAPT

TMRB0_LOAD

TMRB0_HOLD

TMRB0_CNTR

TMRB0_CTRL

TMRB0_SCTRL

TMRB0_CMPLD1

TMRB0_CMPLD2

TMRB0_CSCTRL

TMRB0_FILT

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

Compare Register 2

Capture Register

Load Register

Hold Register

Counter Register

Control Register

Status and Control Register

Comparator Load Register 1

Comparator Load Register 2

Comparator Status and Control Register

Input Filter Register

Reserved

TMRB0_ENBL

TMRB1_COMP1

TMRB1_COMP2

TMRB1_CAPT

$F

Timer Channel Enable Register

Compare Register 1

Compare Register 2

Capture Register

$10

$11

$12

56F8037/56F8027 Data Sheet, Rev. 8

54

FreescaleSemiconductor

Peripheral Memory-Mapped Registers

Table 4-10 Quad Timer B Registers Address Map (Continued)

(TMRB_BASE = $00 F040)

Register Acronym

Address Offset

$13

Register Description

TMRB1_LOAD

TMRB1_HOLD

TMRB1_CNTR

TMRB1_CTRL

TMRB1_SCTRL

TMRB1_CMPLD1

TMRB1_CMPLD2

TMRB1_CSCTRL

TMRB1_FILT

Load Register

Hold Register

$14

$15

$16

$17

$18

$19

$1A

$1B

Counter Register

Control Register

Status and Control Register

Comparator Load Register 1

Comparator Load Register 2

Comparator Status and Control Register

Input Filter Register

Reserved

TMRB2_COMP1

TMRB2_COMP2

TMRB2_CAPT

TMRB2_LOAD

TMRB2_HOLD

TMRB2_CNTR

TMRB2_CTRL

TMRB2_SCTRL

TMRB2_CMPLD1

TMRB2_CMPLD2

TMRB2_CSCTRL

TMRB2_FILT

$20

$21

$22

$23

$24

$25

$26

$27

$28

$29

$2A

$2B

Compare Register 1

Compare Register 2

Capture Register

Load Register

Hold Register

Counter Register

Control Register

Status and Control Register

Comparator Load Register 1

Comparator Load Register 2

Comparator Status and Control Register

Input Filter Register

Reserved

TMRB3_COMP1

TMRB3_COMP2

TMRB3_CAPT

TMRB3_LOAD

TMRB3_HOLD

TMRB3_CNTR

TMRB3_CTRL

TMRB3_SCTRL

TMRB3_CMPLD1

TMRB3_CMPLD2

TMRB3_CSCTRL

TMRB3_FILT

$30

$31

$32

$33

$34

$35

$36

$37

$38

$39

$3A

$3B

Compare Register 1

Compare Register 2

Capture Register

Load Register

Hold Register

Counter Register

Control Register

Status and Control Register

Comparator Load Register 1

Comparator Load Register 2

Comparator Status and Control Register

Input Filter Register

Reserved

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

55

Table 4-11 Analog-to-Digital Converter Registers Address Map

(ADC_BASE = $00 F080)

Register Acronym

Address Offset

Register Description

Control Register 1

ADC_CTRL1

ADC_CTRL2

ADC_ZXCTRL

ADC_CLIST 1

ADC_CLIST 2

ADC_CLIST 3

ADC_CLIST 4

ADC_SDIS

$0

$1

Control Register 2

$2

Zero Crossing Control Register

Channel List Register 1

Channel List Register 2

Channel List Register 3

Channel List Register 4

Sample Disable Register

Status Register

$3

$4

$5

$6

$7

ADC_STAT

$8

ADC_RDY

$9

Conversion Ready Register

Limit Status Register

Zero Crossing Status Register

Result Register 0

ADC_LIMSTAT

ADC_ZXSTAT

ADC_RSLT0

ADC_RSLT1

ADC_RSLT2

ADC_RSLT3

ADC_RSLT4

ADC_RSLT5

ADC_RSLT6

ADC_RSLT7

ADC_RSLT8

ADC_RSLT9

ADC_RSLT10

ADC_RSLT11

ADC_RSLT12

ADC_RSLT13

ADC_RSLT14

ADC_RSLT15

ADC_LOLIM0

ADC_LOLIM1

ADC_LOLIM2

ADC_LOLIM3

ADC_LOLIM4

ADC_LOLIM5

ADC_LOLIM6

ADC_LOLIM7

$A

$B

$C

$D

Result Register 1

$E

Result Register 2

$F

Result Register 3

$10

$11

$12

$13

$14

$15

$16

$17

$18

$19

$1A

$1B

$1C

$1D

$1E

$1F

$20

$21

$22

$23

Result Register 4

Result Register 5

Result Register 6

Result Register 7

Result Register 8

Result Register 9

Result Register 10

Result Register 11

Result Register 12

Result Register 13

Result Register 14

Result Register 15

Low Limit Register 0

Low Limit Register 1

Low Limit Register 2

Low Limit Register 3

Low Limit Register 4

Low Limit Register 5

Low Limit Register 6

Low Limit Register 7

56F8037/56F8027 Data Sheet, Rev. 8

56

FreescaleSemiconductor

Peripheral Memory-Mapped Registers

Table 4-11 Analog-to-Digital Converter Registers Address Map (Continued)

(ADC_BASE = $00 F080)

Register Acronym

Address Offset

$24

Register Description

High Limit Register 0

ADC_HILIM0

ADC_HILIM1

ADC_HILIM2

ADC_HILIM3

ADC_HILIM4

ADC_HILIM5

ADC_HILIM6

ADC_HILIM7

ADC_OFFST0

ADC_OFFST1

ADC_OFFST2

ADC_OFFST3

ADC_OFFST4

ADC_OFFST5

ADC_OFFST6

ADC_OFFST7

ADC_PWR

$25

$26

$27

$28

$29

$2A

$2B

$2C

$2D

$2E

$2F

$30

$31

$32

$33

$34

$35

High Limit Register 1

High Limit Register 2

High Limit Register 3

High Limit Register 4

High Limit Register 5

High Limit Register 6

High Limit Register 7

Offset Register 0

Offset Register 1

Offset Register 2

Offset Register 3

Offset Register 4

Offset Register 5

Offset Register 6

Offset Register 7

Power Control Register

Calibration Register

Reserved

ADC_CAL

Table 4-12 Pulse Width Modulator Registers Address Map

(PWM_BASE = $00 F0C0)

Register Acronym

Address Offset

Register Description

PWM_CTRL

PWM_FCTRL

PWM_FLTACK

PWM_OUT

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

$C

Control Register

Fault Control Register

Fault Status Acknowledge Register

Output Control Register

Counter Register

PWM_CNTR

PWM_CMOD

PWM_VAL0

PWM_VAL1

PWM_VAL2

PWM_VAL3

PWM_VAL4

PWM_VAL5

PWM_DTIM0

Counter Modulo Register

Value Register 0

Value Register 1

Value Register 2

Value Register 3

Value Register 4

Value Register 5

Dead Time Register 0

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

57

Table 4-12 Pulse Width Modulator Registers Address Map (Continued)

(PWM_BASE = $00 F0C0)

Register Acronym

Address Offset

Register Description

Dead Time Register 1

PWM_DTIM1

PWM_DMAP1

PWM_DMAP2

PWM_CNFG

PWM_CCTRL

PWM_PORT

PWM_ICCTRL

PWM_SCTRL

PWM_SYNC

PWM_FFILT0

PWM_FFILT1

PWM_FFILT2

PWM_FFILT3

$D

$E

Disable Mapping Register 1

Disable Mapping Register 2

Configure Register

$F

$10

$11

$12

$13

$14

$15

$16

$17

$18

$19

Channel Control Register

Port Register

Internal Correction Control Register

Source Control Register

Synchronization Window Register

Fault0 Filter Register

Fault1 Filter Register

Fault2 Filter Register

Fault3 Filter Register

Table 4-13 Interrupt Control Registers Address Map

(ITCN_BASE = $00 F0E0)

Register Acronym

Address Offset

Register Description

Interrupt Priority Register 0

ITCN_IPR0

ITCN_IPR1

ITCN_IPR2

ITCN_IPR3

ITCN_IPR4

ITCN_IPR5

ITCN_IPR6

ITCN_VBA

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

$C

$D

$E

$F

$10

Interrupt Priority Register 1

Interrupt Priority Register 2

Interrupt Priority Register 3

Interrupt Priority Register 4

Interrupt Priority Register 5

Interrupt Priority Register 6

Vector Base Address Register

Fast Interrupt Match 0 Register

Fast Interrupt Vector Address Low 0 Register

Fast Interrupt Vector Address High 0 Register

Fast Interrupt Match 1 Register

Fast Interrupt Vector Address Low 1 Register

Fast Interrupt Vector Address High 1 Register

IRQ Pending Register 0

ITCN_FIM0

ITCN_FIVAL0

ITCN_FIVAH0

ITCN_FIM1

ITCN_FIVAL1

ITCN_FIVAH1

ITCN_IRQP0

ITCN_IRQP1

ITCN_IRQP2

IRQ Pending Register 1

IRQ Pending Register 2

56F8037/56F8027 Data Sheet, Rev. 8

58

FreescaleSemiconductor

Peripheral Memory-Mapped Registers

Table 4-13 Interrupt Control Registers Address Map (Continued)

(ITCN_BASE = $00 F0E0)

Register Acronym

Address Offset

$11

Register Description

IRQ Pending Register 3

ITCN_IRQP3

Reserved

ITCN_ICTRL

$16

Interrupt Control Register

Reserved

Table 4-14 SIM Registers Address Map

(SIM_BASE = $00 F100)

Register Acronym

Address Offset

Register Description

SIM_CTRL

SIM_RSTAT

SIM_SWC0

SIM_SWC1

SIM_SWC2

SIM_SWC3

SIM_MSHID

SIM_LSHID

SIM_PWR

$0

$1

$2

$3

$4

$5

$6

$7

$8

Control Register

Reset Status Register

Software Control Register 0

Software Control Register 1

Software Control Register 2

Software Control Register 3

Most Significant Half JTAG ID

Least Significant Half JTAG ID

Power Control Register

Reserved

SIM_CLKOUT

SIM_PCR

$A

$B

Clock Out Select Register

Peripheral Clock Rate Register

Peripheral Clock Enable Register 0

Peripheral Clock Enable Register 1

Peripheral STOP Disable Register 0

Peripheral STOP Disable Register 1

I/O Short Address Location High Register

I/O Short Address Location Low Register

Protection Register

SIM_PCE0

SIM_PCE1

SIM_SD0

$C

$D

$E

SIM_SD1

$F

SIM_IOSAHI

SIM_IOSALO

SIM_PROT

SIM_GPSA0

SIM_GPSA1

SIM_GPSB0

SIM_GPSB1

SIM_GPSCD

SIM_IPS0

$10

$11

$12

$13

$14

$15

$16

$17

$18

$19

$1A

GPIO Peripheral Select Register 0 for GPIOA

GPIO Peripheral Select Register 1 for GPIOA

GPIO Peripheral Select Register 0 for GPIOB

GPIO Peripheral Select Register 1 for GPIOB

GPIO Peripheral Select Register for GPIOC and GPIOD

Internal Peripheral Source Select Register 0 for PWM

Internal Peripheral Source Select Register 1 for DACs

Internal Peripheral Source Select Register 2 for TMRA

Reserved

SIM_IPS1

SIM_IPS2

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

59

Table 4-15 Computer Operating Properly Registers Address Map

(COP_BASE = $00 F120)

Register Acronym

Address Offset

Register Description

COP_CTRL

COP_TOUT

COP_CNTR

$0

$1

$2

Control Register

Time-Out Register

Counter Register

Table 4-16 Clock Generation Module Registers Address Map

(OCCS_BASE = $00 F130)

Register Acronym

Address Offset

Register Description

OCCS_CTRL

OCCS_DIVBY

OCCS_STAT

$0

$1

$2

Control Register

Divide-By Register

Status Register

Reserved

OCCS_OCTRL

OCCS_CLKCHK

OCCS_PROT

$5

$6

$7

Oscillator Control Register

Clock Check Register

Protection Register

Table 4-17 Power Supervisor Registers Address Map

(PS_BASE = $00 F140)

Register Acronym

Address Offset

Register Description

PS_CTRL

PS_STAT

$0

$1

Control Register

Status Register

Reserved

Table 4-18 GPIOA Registers Address Map

(GPIOA_BASE = $00 F150)

Address Offset

Register Description

Register Acronym

GPIOA_PUPEN

GPIOA_DATA

$0

$1

$2

$3

$4

$5

$6

Pull-up Enable Register

Data Register

GPIOA_DDIR

Data Direction Register

Peripheral Enable Register

Interrupt Assert Register

Interrupt Enable Register

Interrupt Polarity Register

GPIOA_PEREN

GPIOA_IASSRT

GPIOA_IEN

GPIOA_IPOL

56F8037/56F8027 Data Sheet, Rev. 8

60

FreescaleSemiconductor

Peripheral Memory-Mapped Registers

Table 4-18 GPIOA Registers Address Map (Continued)

(GPIOA_BASE = $00 F150)

Address Offset

Register Description

Register Acronym

GPIOA_IPEND

$7

$8

$9

$A

$B

Interrupt Pending Register

GPIOA_IEDGE

GPIOA_PPOUTM

GPIOA_RDATA

GPIOA_DRIVE

Interrupt Edge-Sensitive Register

Push-Pull Output Mode Control Register

Raw Data Input Register

Output Drive Strength Control Register

Table 4-19 GPIOB Registers Address Map

(GPIOB_BASE = $00 F160)

Register Acronym

Address Offset

Register Description

GPIOB_PUPEN

GPIOB_DATA

GPIOB_DDIR

GPIOB_PEREN

GPIOB_IASSRT

GPIOB_IEN

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

Pull-up Enable Register

Data Register

Data Direction Register

Peripheral Enable Register

Interrupt Assert Register

Interrupt Enable Register

Interrupt Polarity Register

Interrupt Pending Register

Interrupt Edge-Sensitive Register

Push-Pull Output Mode Control Register

Raw Data Input Register

GPIOB_IPOL

GPIOB_IPEND

GPIOB_IEDGE

GPIOB_PPOUTM

GPIOB_RDATA

GPIOB_DRIVE

Output Drive Strength Control Register

Table 4-20 GPIOC Registers Address Map

(GPIOC_BASE = $00 F170)

Register Acronym

Address Offset

Register Description

GPIOC_PUPEN

GPIOC_DATA

GPIOC_DDIR

GPIOC_PEREN

GPIOC_IASSRT

GPIOC_IEN

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

Pull-up Enable Register

Data Register

Data Direction Register

Peripheral Enable Register

Interrupt Assert Register

Interrupt Enable Register

Interrupt Polarity Register

Interrupt Pending Register

Interrupt Edge-Sensitive Register

Push-Pull Output Mode Control Register

Raw Data Input Register

GPIOC_IPOL

GPIOC_IPEND

GPIOC_IEDGE

GPIOC_PPOUTM

GPIOC_RDATA

GPIOC_DRIVE

Output Drive Strength Control Register

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

61

Table 4-21 GPIOD Registers Address Map

(GPIOD_BASE = $00 F180)

Register Acronym

Address Offset

Register Description

GPIOD_PUPEN

GPIOD_DATA

GPIOD_DDIR

GPIOD_PEREN

GPIOD_IASSRT

GPIOD_IEN

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

Pull-up Enable Register

Data Register

Data Direction Register

Peripheral Enable Register

Interrupt Assert Register

Interrupt Enable Register

Interrupt Polarity Register

Interrupt Pending Register

Interrupt Edge-Sensitive Register

Push-Pull Output Mode Control Register

Raw Data Input Register

GPIOD_IPOL

GPIOD_IPEND

GPIOD_IEDGE

GPIOD_PPOUTM

GPIOD_RDATA

GPIOD_DRIVE

Output Drive Strength Control Register

Table 4-22 Programmable Interval Timer 0 Registers Address Map

(PIT0_BASE = $00 F190)

Register Acronym

Address Offset

Register Description

PIT0_CTRL

PIT0_MOD

PIT0_CNTR

$0

$1

$2

Control Register

Modulo Register

Counter Register

Table 4-23 Programmable Interval Timer 1 Registers Address Map

(PIT1_BASE = $00 F1A0)

Register Acronym

Address Offset

Register Description

PIT1_CTRL

PIT1_MOD

PIT1_CNTR

$0

$1

$2

Control Register

Modulo Register

Counter Register

Table 4-24 Programmable Interval Timer 2 Registers Address Map

(PIT2_BASE = $00 F1B0)

Register Acronym

Address Offset

Register Description

PIT2_CTRL

PIT2_MOD

$0

$1

Control Register

Modulo Register

56F8037/56F8027 Data Sheet, Rev. 8

62

FreescaleSemiconductor

Peripheral Memory-Mapped Registers

Table 4-24 Programmable Interval Timer 2 Registers Address Map (Continued)

(PIT2_BASE = $00 F1B0)

Register Acronym

Address Offset

Register Description

Counter Register

PIT2_CNTR

$2

Table 4-25 Digital-to-Analog Converter 0 Registers Address Map

(DAC0_BASE = $00 F1C0)

Register Acronym

Address Offset

Register Description

DAC0_CTRL

DAC0_DATA

DAC0_STEP

DAC0_MINVAL

DAC0_MAXVAL

$0

$1

$2

$3

$4

Control Register

Data Register

Step Register

Minimum Value Register

Maximum Value Register

Table 4-26 Digital-to-Analog Converter 0 Registers Address Map

(DAC1_BASE = $00 F1D0)

Register Acronym

Address Offset

Register Description

DAC1_CTRL

DAC1_DATA

DAC1_STEP

DAC1_MINVAL

DAC1_MAXVAL

$0

$1

$2

$3

$4

Control Register

Data Register

Step Register

Minimum Value Register

Maximum Value Register

Table 4-27 Comparator A Registers Address Map

(CMPA_BASE = $00 F1E0)

Register Acronym

Address Offset

Register Description

CMPA_CTRL

CMPA_STAT

CMPA_FILT

$0

$1

$2

Control Register

Status Register

Filter Register

Table 4-28 Comparator B Registers Address Map

(CMPB_BASE = $00 F1F0)

Register Acronym

Address Offset

Register Description

CMPB_CTRL

CMPB_STAT

CMPB_FILT

$0

$1

$2

Control Register

Status Register

Filter Register

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

63

Table 4-29 Queued Serial Communication Interface 0 Registers Address Map

(QSCI0_BASE = $00 F200)

Register Acronym

Address Offset

Register Description

Baud Rate Register

QSCI0_RATE

QSCI0_CTRL1

QSCI0_CTRL2

QSCI0_STAT

QSCI0_DATA

$0

$1

$2

$3

$4

Control Register 1

Control Register 2

Status Register

Data Register

Table 4-30 Queued Serial Communication Interface 1 Registers Address Map

(QSCI1_BASE = $00 F210)

Register Acronym

Address Offset

Register Description

Baud Rate Register

QSCI1_RATE

QSCI1_CTRL1

QSCI1_CTRL2

QSCI1_STAT

QSCI1_DATA

$0

$1

$2

$3

$4

Control Register 1

Control Register 2

Status Register

Data Register

Table 4-31 Queued Serial Peripheral Interface 0 Registers Address Map

(QSPI0_BASE = $00 F220)

Register Acronym

Address Offset

Register Description

Status and Control Register

QSPI0_SCTRL

QSPI0_DSCTRL

QSPI0_DRCV

QSPI0_DXMIT

QSPI0_FIFO

$0

$1

$2

$3

$4

$5

Data Size and Control Register

Data Receive Register

Data Transmit Register

FIFO Control Register

Delay Register

QSPI0_DELAY

Table 4-32 Queued Serial Peripheral Interface 1 Registers Address Map

(QSPI1_BASE = $00 F230)

Register Acronym

Address Offset

Register Description

Status and Control Register

QSPI1_SCTRL

QSPI1_DSCTRL

QSPI1_DRCV

QSPI1_DXMIT

QSPI1_FIFO

$0

$1

$2

$3

$4

Data Size and Control Register

Data Receive Register

Data Transmit Register

FIFO Control Register

56F8037/56F8027 Data Sheet, Rev. 8

64

FreescaleSemiconductor

Peripheral Memory-Mapped Registers

Table 4-32 Queued Serial Peripheral Interface 1 Registers Address Map

(QSPI1_BASE = $00 F230)

Register Acronym

Address Offset

$5

Register Description

QSPI1_DELAY

Delay Register

2

Table 4-33 I C Registers Address Map

(I2C_BASE = $00 F280)

Register Acronym

Address Offset

Register Description

I2C_CTRL

$0

$2

Control Register

I2C_TAR

Target Address Register

I2C_SAR

$4

Slave Address Register

I2C_DATA

$8

RX/TX Data Buffer and Command Register

Standard Speed Clock SCL High Count Register

Standard Speed Clock SCL Low Count Register

Fast Speed Clock SCL High Count Register

Fast Speed Clock SCL Low Count Register

Interrupt Status Register

I2C_SSHCNT

I2C_SSLCNT

I2C_FSHCNT

I2C_FSLCNT

I2C_ISTAT

$A

$C

$E

$10

$16

$18

$1A

$1C

$1E

$20

$22

$24

$26

$28

$2A

$2C

$2E

$30

$32

$34

$36

$38

$3A

$3C

$40

I2C_IMASK

Interrupt Mask Register

I2C_RISTAT

I2C_RXFT

Raw Interrupt Status Register

Receive FIFO Threshold Register

Transmit FIFO Threshold Register

Clear Combined and Individual Interrupts Register

Clear RX_UNDER Interrupt Register

Clear RX_OVER Interrupt Register

Clear TX_OVER Interrupt Register

Clear RD_REQ Interrupt Register

Clear TX_ABRT Interrupt Register

Clear RX_DONE Interrupt Register

Clear Activity Interrupt Register

Clear STOP_DET Interrupt Register

Clear START_DET Interrupt Register

Clear GEN_CALL Interrupt Register

Enable Register

I2C_TXFT

I2C_CLRINT

I2C_CLRRXUND

I2C_CLRRXOVR

I2C_CLRTXOVR

I2C_CLRRDREQ

I2C_CLRTXABRT

I2C_CLRRXDONE

I2C_CLRACT

I2C_CLRSTPDET

I2C_CLRSTDET

I2C_CLRGC

I2C_ENBL

I2C_STAT

Status Register

I2C_TXFLR

Transmit FIFO Level Register

I2C_RXFLR

Receive FIFO Level Register

I2C_TXABRTSRC

Transmit Abort Status Register

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

65

Table 4-34 Flash Module Registers Address Map

(FM_BASE = $00 F400)

Register Acronym

Address Offset

Register Description

Clock Divider Register

FM_CLKDIV

FM_CNFG

$0

$1

Configuration Register

Reserved

$2

FM_SECHI

FM_SECLO

$3

Security High Half Register

Security Low Half Register

Reserved

$4

$5 - $9

$10

FM_PROT

Protection Register

Reserved

$11 - $12

$13

FM_USTAT

FM_CMD

User Status Register

Command Register

Reserved

$14

$15 - $17

$18

FM_DATA

FM_OPT1

FM_TSTSIG

Data Buffer Register

Reserved

$19 - $A

$1B

Information Option Register 1

Reserved

$1C

$1D

Test Array Signature Register

Table 4-35 MSCAN Registers Address Map

(MSCAN_BASE = $00 F800)

Register Acronym

Address Offset

Register Description

MSCAN_CTRL0

$00

$01

$02

$03

$04

$05

$06

$07

$08

$09

$0A

$0B

Control Register 0

MSCAN_CTRL1

MSCAN_BTR0

MSCAN_BTR1

MSCAN_RFLG

MSCAN_RIER

MSCAN_TFLG

MSCAN_TIER

MSCAN_TARQ

MSCAN_TAAK

MSCAN_TBSEL

MSCAN_IDAC

Control Register 1

Bus Timing Register 0

Bus Timing Register 1

Receiver Flag Register

Receiver Interrupt Enable Register

Transmitter Flag Register

Transmitter Interrupt Enable Register

Transmitter Message Abort Request Register

Transmitter Message Abort Acknowledge Register

Transmitter Buffer Selection Register

Identifier Acceptance Control Register

Reserved

MSCAN_MISC

MSCAN_RXERR

MSCAN_TXERR

$0D

$0E

$0F

Miscellaneous Register

Receive Error Register

Transmit Error Register

56F8037/56F8027 Data Sheet, Rev. 8

66

FreescaleSemiconductor

Peripheral Memory-Mapped Registers

Table 4-35 MSCAN Registers Address Map (Continued)

(MSCAN_BASE = $00 F800)

Register Acronym

MSCAN_IDAR0

Address Offset

Register Description

Identifier Acceptance Register 0

Identifier Acceptance Register 1

$10

$11

$12

$13

$14

$15

$16

$17

$18

$19

$1A

$1B

$1C

$1D

$1E

$1F

$20

$21

$22

$23

$24

$25

$26

$27

$28

$29

$2A

$2B

$2C

$2D

$2E

$2F

$30

$31

$32

$33

MSCAN_IDAR1

MSCAN_IDAR2

MSCAN_IDAR3

MSCAN_IDMR0

MSCAN_IDMR1

MSCAN_IDMR2

MSCAN_IDMR3

MSCAN_IDAR4

MSCAN_IDAR5

MSCAN_IDAR6

MSCAN_IDAR7

MSCAN_IDMR4

MSCAN_IDMR5

MSCAN_IDMR6

MSCAN_IDMR7

MSCAN_RXFG0

MSCAN_RXFG1

MSCAN_RXFG2

MSCAN_RXFG3

MSCAN_RXFG4

MSCAN_RXFG5

MSCAN_RXFG6

MSCAN_RXFG7

MSCAN_RXFG8

MSCAN_RXFG9

MSCAN_RXFG10

MSCAN_RXFG11

MSCAN_RXFG12

MSCAN_RXFG13

MSCAN_RXFG14

MSCAN_RXFG15

MSCAN_TXFG0

MSCAN_TXFG1

MSCAN_TXFG2

MSCAN_TXFG3

Identifier Acceptance Register 2

Identifier Acceptance Register 3

Identifier Mask Register 0

Identifier Mask Register 1

Identifier Mask Register 2

Identifier Mask Register 3

Identifier Acceptance Register 4

Identifier Acceptance Register 5

Identifier Acceptance Register 6

Identifier Acceptance Register 7

Identifier Mask Register 4

Identifier Mask Register 5

Identifier Mask Register 6

Identifier Mask Register 7

Foreground Receive Buffer 0

Foreground Receive Buffer 1

Foreground Receive Buffer 2

Foreground Receive Buffer 3

Foreground Receive Buffer 4

Foreground Receive Buffer 5

Foreground Receive Buffer 6

Foreground Receive Buffer 7

Foreground Receive Buffer 8

Foreground Receive Buffer 9

Foreground Receive Buffer 10

Foreground Receive Buffer 11

Foreground Receive Buffer 12

Foreground Receive Buffer 13

Foreground Receive Buffer 14

Foreground Receive Buffer 15

Foreground Transmit Buffer 0

Foreground Transmit Buffer 1

Foreground Transmit Buffer 2

Foreground Transmit Buffer 3

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

67

Table 4-35 MSCAN Registers Address Map (Continued)

(MSCAN_BASE = $00 F800)

Register Acronym

MSCAN_TXFG4

Address Offset

Register Description

Foreground Transmit Buffer 4

$34

$35

$36

$37

$38

$39

$3A

$3B

$3C

$3D

$3E

$3F

MSCAN_TXFG5

MSCAN_TXFG6

MSCAN_TXFG7

MSCAN_TXFG8

MSCAN_TXFG9

MSCAN_TXFG10

MSCAN_TXFG11

MSCAN_TXFG12

MSCAN_TXFG13

MSCAN_TXFG14

MSCAN_TXFG15

Foreground Transmit Buffer 5

Foreground Transmit Buffer 6

Foreground Transmit Buffer 7

Foreground Transmit Buffer 8

Foreground Transmit Buffer 9

Foreground Transmit Buffer 10

Foreground Transmit Buffer 11

Foreground Transmit Buffer 12

Foreground Transmit Buffer 13

Foreground Transmit Buffer 14

Foreground Transmit Buffer 15

Reserved

Part 5 Interrupt Controller (ITCN)

5.1 Introduction

The Interrupt Controller (ITCN) module arbitrates between various interrupt requests (IRQs), signals to

the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to

service this interrupt.

5.2 Features

The ITCN module design includes these distinctive features:

•

Programmable priority levels for each IRQ

Two programmable Fast Interrupts

Notification to SIM module to restart clocks out of Wait and Stop modes

Ability to drive initial address on the address bus after reset

For further information, see Table 4-2, Interrupt Vector Table Contents.

5.3 Functional Description

The Interrupt Controller is a slave on the IPBus. It contains registers that allow each of the 64 interrupt

sources to be set to one of four priority levels (excluding certain interrupts that are of fixed priority). Next,

all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value

of the active interrupt requests for that level. Within a given priority level, number 0 is the highest priority

and number 63 is the lowest.

56F8037/56F8027 Data Sheet, Rev. 8

68

FreescaleSemiconductor

Functional Description

5.3.1

Normal Interrupt Handling

Once the INTC has determined that an interrupt is to be serviced and which interrupt has the highest

priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base

Address (VBA) and the vector number to determine the vector address, generating an offset into the vector

table for each interrupt.

5.3.2

Interrupt Nesting

Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be

serviced. The 56800E core controls the masking of interrupt priority levels it will accept by setting the I0

and I1 bits in its status register.

Table 5-1 Interrupt Mask Bit Definition

Exceptions Permitted

SR[9] (I1) SR[8] (I0)

Exceptions Masked

0

1

0

1

0

1

Priorities 0, 1, 2, 3

Priorities 1, 2, 3

Priorities 2, 3

Priority 3

None

Priority 0

Priorities 0, 1

Priorities 0, 1, 2

The IPIC bits of the ICTRL register reflect the state of the priority level being presented to the 56800E

core.

Table 5-2 Interrupt Priority Encoding

Current Interrupt

Priority Level

Required Nested

Exception Priority

IPIC_VALUE[1:0]

00

01

10

11

No interrupt or SWILP

Priority 0

Priorities 0, 1, 2, 3

Priorities 1, 2, 3

Priorities 2, 3

Priority 3

Priority 1

Priority 2 or 3

5.3.3

Fast Interrupt Handling

Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes

Fast Interrupts before the core does.

A Fast Interrupt is defined (to the ITCN) by:

1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers

2. Setting the FIMn register to the appropriate vector number

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

69

3. Setting the FIVALn and FIVAHn registers with the address of the code for the Fast Interrupt

When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a

match occurs, and it is a level 2 interrupt, the ITCN handles it as a Fast Interrupt. The ITCN takes the vector

address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an

offset from the VBA.

The core then fetches the instruction from the indicated vector address and if it is not a JSR, the core starts

its Fast Interrupt handling.

5.4 Block Diagram

any0

Priority

Level

Level 0

64 -> 6

Priority

Encoder

6

2 -> 4

Decode

INT1

INT

VAB

IPIC

CONTROL

any3

IACK

SR[9:8]

Level 3

Priority

Level

64 -> 6

Priority

PIC_EN

6

Encoder

2 -> 4

Decode

INT64

Figure 5-1 Interrupt Controller Block Diagram

56F8037/56F8027 Data Sheet, Rev. 8

70

FreescaleSemiconductor

Operating Modes

5.5 Operating Modes

The ITCN module design contains two major modes of operation:

•

Functional Mode

The ITCN is in this mode by default.

Wait and Stop Modes

During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal

a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ

can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode.

5.6 Register Descriptions

A register address is the sum of a base address and an address offset. The base address is defined at the

system level and the address offset is defined at the module level.

Table 5-3 ITCN Register Summary

(ITCN_BASE = $00 F0E0)

Register

Acronym

Base Address +

Register Name

Section Location

IPR0

$0

$1

Interrupt Priority Register 0

5.6.1

5.6.2

IPR1

Interrupt Priority Register 1

Interrupt Priority Register 2

Interrupt Priority Register 3

Interrupt Priority Register 4

Interrupt Priority Register 5

Interrupt Priority Register 6

Vector Base Address Register

Fast Interrupt Match 0 Register

Fast Interrupt 0 Vector Address Low Register

Fast Interrupt 0 Vector Address High 0 Register

Fast Interrupt Match 1 Register

Fast Interrupt 1 Vector Address Low Register

Fast Interrupt 1 Vector Address High Register

IRQ Pending Register 0

IPR2

$2

5.6.3

IPR3

$3

5.6.4

IPR4

$4

5.6.5

IPR5

$5

5.6.6

IPR6

$6

5.6.7

VBA

$7

5.6.8

FIM0

$8

5.6.9

FIVAL0

FIVAH0

FIM1

$9

5.6.10

5.6.11

5.6.12

5.6.13

5.6.14

5.6.15

5.6.16

5.6.17

5.6.18

$A

$B

$C

$D

$E

$F

$10

$11

FIVAL1

FIVAH1

IRQP0

IRQP1

IRQP2

IRQP3

IRQ Pending Register 1

IRQ Pending Register 2

IRQ Pending Register 3

Reserved

ICTRL

$16

Interrupt Control Register

5.6.19

Reserved

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

71

Add.

Offset

Register

Name

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

W

R

0

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

$C

$D

$E

$F

$10

IPR0

IPR1

PLL IPL

LVI IPL

RX_REG IPL TX_REG IPL

MSCAN_RX MSCAN_ERR

TRBUF IPL

FM_CBE IPL

GPIOA IPL

BKPT_U IPL

FM_CC IPL

GPIOB IPL

STPCNT IPL

FM_ERR IPL

GPIOC IPL

MSCAN_WK

UP IPL

MSCAN_TX

IPL

GPIOD IPL

IPL

W

R

QSCI0_XMIT QSPI1_XMIT QSPI1_RCV QSPI0_XMIT QSPI0_RCV

IPR2

IPL

W

R

QSCI1_RCV

IPL

QSCI1_RER

R IPL

QSCI1_TIDL QSCI1_XMIT QSCI0_RCV QSCI0_RERR QSCI0_TIDL

IPR3

I2C_ERR IPL

IPL

W

R

I2C_STAT

IPL

IPR4

TMRA_3 IPL TMRA_2 IPL TMRA_1 IPL TMRA_0 IPL

I2C_TX IPL

I2C_RX IPL

I2C_GEN IPL

W

R

IPR5

PIT1 IPL

PIT0 IPL

COMPB IPL

COMPA IPL

TMRB_3 IPL TMRB_2 IPL

TMRB_1 IPL

TMRB_0 IPL

PIT2 IPL

W

0

ADCB_CC

IPR6

PWM_F IPL PWM_RL IPL ADC_ZC IPL

ADCA_CC IPL

IPL

R

W

R

VBA

VECTOR_BASE_ADDRESS

0

FIM0

FAST INTERRUPT 0

W

R

FIVAL0

FIVAH0

FIM1

FAST INTERRUPT 0 VECTOR ADDRESS LOW

W

R

0

FAST INTERRUPT 0 VECTOR

ADDRESS HIGH

W

R

FAST INTERRUPT 1

W

R

FIVAL1

FIVAH1

IRQP0

IRQP1

IRQP2

FAST INTERRUPT 1 VECTOR ADDRESS LOW

W

R

0

FAST INTERRUPT 1 VECTOR

ADDRESS HIGH

W

R

PENDING[16:2]

PENDING[32:17]

PENDING[48:33]

1

W

R

W

R

W

R

PENDING[63:49]

$11

$16

IRQP3

W

Reserved

ICTRL

R

INT

IPIC

VAB

1

0

INT_

DIS

W

Reserved

= Reserved

Figure 5-2 ITCN Register Map Summary

56F8037/56F8027 Data Sheet, Rev. 8

72

FreescaleSemiconductor

Register Descriptions

5.6.1

Interrupt Priority Register 0 (IPR0)

Base + $0

Read

15

14

0

13

12

0

11

0

10

0

9

8

7

6

5

4

3

2

1

0

PLL IPL

LVI IPL

RX_REG IPL TX_REG IPL

TRBUF IPL

BKPT_U IPL STPCNT IPL

Write

RESET

0

Figure 5-3 Interrupt Priority Register 0 (IPR0)

5.6.1.1

PLL Loss of Reference or Change in Lock Status Interrupt Priority Level

(PLL IPL)—Bits 15–14

This field is used to set the interrupt priority levels for the PLL Loss of Reference or Change in Lock Status

IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.6.1.2

Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 13–12

This field is used to set the interrupt priority levels for the Low Voltage Detector IRQ. This IRQ is limited

to priorities 1 through 3 and is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.6.1.3

Reserved—Bits 11–10

This bit field is reserved. Each bit must be set to 0.

5.6.1.4

EOnCE Receive Register Full Interrupt Priority Level

(RX_REG IPL)— Bits 9–8

This field is used to set the interrupt priority level for the EOnCE Receive Register Full IRQ. This IRQ is

limited to priorities 1 through 3. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

73

5.6.1.5

EOnCE Transmit Register Empty Interrupt Priority Level

(TX_REG IPL)— Bits 7–6

This field is used to set the interrupt priority level for the EOnCE Transmit Register Empty IRQ. This IRQ

is limited to priorities 1 through 3. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.6.1.6

EOnCE Trace Buffer Interrupt Priority Level

(TRBUF IPL)— Bits 5–4

This field is used to set the interrupt priority level for the EOnCE Trace Buffer IRQ. This IRQ is limited

to priorities 1 through 3. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.6.1.7

EOnCE Breakpoint Unit Interrupt Priority Level

(BKPT_U IPL)— Bits 3–2

This field is used to set the interrupt priority level for the EOnCE Breakpoint Unit IRQ. This IRQ is limited

to priorities 1 through 3. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.6.1.8

EOnCE Step Counter Interrupt Priority Level

(STPCNT IPL)— Bits 1–0

This field is used to set the interrupt priority level for the EOnCE Step Counter IRQ. This IRQ is limited

to priorities 1 through 3. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

56F8037/56F8027 Data Sheet, Rev. 8

74

FreescaleSemiconductor

Register Descriptions

5.6.2

Interrupt Priority Register 1 (IPR1)

Base + $1

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MSCAN_WK

UP IPL

MSCAN_TX

IPL

MSCAN_RX

IPL

MSCAN_ERR

IPL

GPIOD IPL

FM_CBE IPL

FM_CC IPL

FM_ERR IPL

Write

RESET

0

Figure 5-4 Interrupt Priority Register 1 (IPR1)

GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14

5.6.2.1

This field is used to set the interrupt priority level for the GPIOD IRQ. This IRQ is limited to priorities 0

through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.2.2

MSCAN Wake Up Interrupt Priority Level

(MSCAN_WKUP IPL)—Bits 13–12

This field is used to set the interrupt priority level for the MSCAN Wake Up IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.2.3

MSCAN Transmit Interrupt Priority Level (MSCAN_TX IPL)—Bits 11–10

This field is used to set the interrupt priority level for the MSCAN Transmit IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.2.4

MSCAN Receive Interrupt Priority Level (MSCAN_RX IPL)—Bits 9–8

This field is used to set the interrupt priority level for MSCAN Receive IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

75

•

11 = IRQ is priority level 2

5.6.2.5

MSCAN Error Interrupt Priority Level (MSCAN_ERR IPL)—Bits 7–6

This field is used to set the interrupt priority level for the MSCAN Error IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.2.6

FM Command, Data, Address Buffers Empty Interrupt Priority Level

(FM_CBE IPL)—Bits 5–4

This field is used to set the interrupt priority level for the FM Command, Data Address Buffers Empty

IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.2.7

FM Command Complete Interrupt Priority Level (FM_CC IPL)—Bits 3–2

This field is used to set the interrupt priority level for the FM Command Complete IRQ. This IRQ is

limited to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.2.8

FM Error Interrupt Priority Level (FM_ERR IPL)—Bits 1–0

This field is used to set the interrupt priority level for the FM Error IRQ. This IRQ is limited to priorities

0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

56F8037/56F8027 Data Sheet, Rev. 8

76

FreescaleSemiconductor

Register Descriptions

5.6.3

Interrupt Priority Register 2 (IPR2)

Base + $2

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

QSCI0_XMIT QSPI1_XMIT

IPL IPL

QSPI1_RCV QSPI0_XMIT

IPL IPL

QSPI0_RCV

IPL

GPIOA IPL

GPIOB IPL

GPIOC IPL

Write

RESET

0

Figure 5-5 Interrupt Priority Register 2 (IPR2)

5.6.3.1

QSCI 0 Transmitter Empty Interrupt Priority Level (QSCI0_XMIT IPL)—

Bits 15–14

This field is used to set the interrupt priority level for the QSCI0 Transmitter Empty IRQ. This IRQ is

limited to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.3.2

QSPI 1 Transmitter Empty Interrupt Priority Level (QSPI1_XMIT IPL)—

Bits 13–12

This field is used to set the interrupt priority level for the QSPI1 Transmitter Empty IRQ. This IRQ is

limited to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.3.3

QSPI 1 Receiver Full Interrupt Priority Level (QSPI1_RCV IPL)—

Bits 11–10

This field is used to set the interrupt priority level for the QSPI1 Receiver Full IRQ. This IRQ is limited

to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.3.4

QSPI 0 Transmitter Empty Interrupt Priority Level (QSPI0_XMIT IPL)—

Bits 9–8

This field is used to set the interrupt priority level for the QSPI0 Transmitter Empty IRQ. This IRQ is

limited to priorities 0 through 2. It is disabled by default.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

77

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.3.5

QSPI 0 Receiver Full Interrupt Priority Level (QSPI0_RCV IPL)—Bits 7–6

This field is used to set the interrupt priority level for the QSPI0 Receiver Full IRQ. This IRQ is limited

to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.3.6

GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4

This field is used to set the interrupt priority level for the GPIOA IRQ. This IRQ is limited to priorities 0

through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.3.7

GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2

This field is used to set the interrupt priority level for the GPIOB IRQ. This IRQ is limited to priorities 0

through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.3.8

GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 1–0

This field is used to set the interrupt priority level for the GPIOC IRQ. This IRQ is limited to priorities 0

through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

56F8037/56F8027 Data Sheet, Rev. 8

78

FreescaleSemiconductor

Register Descriptions

5.6.4

Interrupt Priority Register 3 (IPR3)

Base + $3

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

QSCI1_RCV QSCI1_RER QSCI1_TIDL QSCI1_XMIT QSCI0_RCV QSCI0_RERR QSCI0_TIDL

IPL R IPL IPL IPL IPL IPL IPL

I2C_ERR IPL

Write

RESET

0

Figure 5-6 Interrupt Priority Register 3 (IPR3)

2

5.6.4.1

I C Error Interrupt Priority Level (I2C_ERR IPL)—Bits 15–14

2

This field is used to set the interrupt priority level for the I C Error IRQ. This IRQ is limited to priorities

0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.4.2

QSCI 1 Receiver Full Interrupt Priority Level (QSCI1_RCV IPL)—

Bits 13–12

This field is used to set the interrupt priority level for the QSCI1 Receiver Full IRQ. This IRQ is limited

to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.4.3

QSCI 1 Receiver Error Interrupt Priority Level (QSCI1_RERR IPL)—

Bits 11–10

This field is used to set the interrupt priority level for the QSCI1 Receiver Error IRQ. This IRQ is limited

to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.4.4

QSCI 1 Transmitter Idle Interrupt Priority Level (QSCI1_TIDL IPL)—

Bits 9–8

This field is used to set the interrupt priority level for the QSCI1 Transmitter Idle IRQ. This IRQ is limited

to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

79

•

11 = IRQ is priority level 2

5.6.4.5

QSCI 1 Transmitter Empty Interrupt Priority Level (QSCI1_XMIT IPL)—

Bits 7–6

This field is used to set the interrupt priority level for the QSCI1 Transmitter Empty IRQ. This IRQ is

limited to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.4.6

QSCI 0 Receiver Full Interrupt Priority Level (QSCI0_RCV IPL)—Bits 5–4

This field is used to set the interrupt priority level for the QSCI0 Receiver Full IRQ. This IRQ is limited

to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.4.7

QSCI 0 Receiver Error Interrupt Priority Level (QSCI0_RERR IPL)—

Bits 3–2

This field is used to set the interrupt priority level for the QSCI0 Receiver Error IRQ. This IRQ is limited

to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.4.8

QSCI 0 Transmitter Idle Interrupt Priority Level (QSCI0_TIDL IPL)—

Bits 1–0

This field is used to set the interrupt priority level for the QSCI0 Transmitter Idle IRQ. This IRQ is limited

to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

56F8037/56F8027 Data Sheet, Rev. 8

80

FreescaleSemiconductor

Register Descriptions

5.6.5

Interrupt Priority Register 4 (IPR4)

Base + $4

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TMRA_3 IPL

TMRA_2 IPL

TMRA_1 IPL

TMRA_0 IPL I2C_STAT IPL I2C_TX IPL

I2C_RX IPL I2C_GEN IPL

Write

RESET

0

Figure 5-7 Interrupt Priority Register 4 (IPR4)

5.6.5.1

Timer A, Channel 3 Interrupt Priority Level (TMRA_3 IPL)—

Bits 15–14

This field is used to set the interrupt priority level for the Timer A, Channel 3 IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.5.2

Timer A, Channel 2 Interrupt Priority Level (TMRA_2 IPL)—

Bits 13–12

This field is used to set the interrupt priority level for the Timer A, Channel 2 IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.5.3

Timer A, Channel 1 Interrupt Priority Level (TMRA_1 IPL)—

Bits 11–10

This field is used to set the interrupt priority level for the Timer A, Channel 1 IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

81

5.6.5.4

Timer A, Channel 0 Interrupt Priority Level (TMRA_0 IPL)—

Bits 9–8

This field is used to set the interrupt priority level for the Timer A, Channel 0 IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

2

5.6.5.5

I C Status Interrupt Priority Level (I2C_STAT IPL)—Bits 7–6

2

This field is used to set the interrupt priority level for the I C Status IRQ. This IRQ is limited to priorities

0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

2

5.6.5.6

I C Transmit Interrupt Priority Level (I2C_TX IPL)—Bits 5–4

2

This field is used to set the interrupt priority level for the I C Transmit IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

2

5.6.5.7

I C Receive Interrupt Priority Level (I2C_RX IPL)— Bits 3–2

2

This field is used to set the interrupt priority level for the I C Receiver IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

2

5.6.5.8

I C General Call Interrupt Priority Level (I2C_GEN IPL)—Bits 1–0

2

This field is used to set the interrupt priority level for the I C General Call IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

56F8037/56F8027 Data Sheet, Rev. 8

82

FreescaleSemiconductor

Register Descriptions

•

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.6

Interrupt Priority Register 5 (IPR5)

Base + $5

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PIT1 IPL

PIT0 IPL

COMPB IPL

COMPA IPL

TMRB_3 IPL TMRB_2 IPL TMRB_1 IPL TMRB_0 IPL

Write

0

RESET

Figure 5-8 Interrupt Priority Register 5 (IPR6)

5.6.6.1

Programmable Interval Timer 1 Interrupt Priority Level (PIT1 IPL)—

Bits 15–14

This field is used to set the interrupt priority level for the Programmable Interval Timer 1 IRQ. This IRQ

is limited to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.6.2

Programmable Interval Timer 0 Interrupt Priority Level (PIT0 IPL)—

Bits 13–12

This field is used to set the interrupt priority level for the Programmable Interval Timer 0 IRQ. This IRQ

is limited to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.6.3

Comparator B Interrupt Priority Level (COMPB IPL)—

Bits 11–10

This field is used to set the interrupt priority level for the Comparator B IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

83

5.6.6.4

Comparator A Interrupt Priority Level (COMPA IPL)—

Bits 9–8

This field is used to set the interrupt priority level for the Comparator IRQ. This IRQ is limited to priorities

0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.6.5

Timer B, Channel 3 Interrupt Priority Level (TMRB_3 IPL)—Bits 7–6

This field is used to set the interrupt priority level for the Timer B, Channel 3 IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.6.6

Timer B, Channel 2 Interrupt Priority Level (TMRB_2 IPL)—Bits 5–4

This field is used to set the interrupt priority level for the Timer B, Channel 2 IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.6.7

Timer B, Channel 1 Interrupt Priority Level (TMRB_1 IPL)—Bits 3–2

This field is used to set the interrupt priority level for the Timer B, Channel 1 IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.6.8

Timer B, Channel 0 Interrupt Priority Level (TMRB_0 IPL)—Bits 1–0

This field is used to set the interrupt priority level for the Timer B, Channel 0 IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

56F8037/56F8027 Data Sheet, Rev. 8

84

FreescaleSemiconductor

Register Descriptions

•

11 = IRQ is priority level 2

5.6.7

Interrupt Priority Register 6 (IPR6)

Base + $6

Read

15

0

14

0

13

0

12

0

11

10

9

8

7

6

5

4

3

2

1

0

ADCB_CC

IPL

ADCA_CC

IPL

PWM_F IPL

PWM_RL IPL

ADC_ZC IPL

PIT2 IPL

Write

0

RESET

Figure 5-9 Interrupt Priority Register 6 (IPR6)

5.6.7.1

Reserved—Bits 15–12

This bit field is reserved. Each bit must be set to 0.

5.6.7.2

PWM Fault Interrupt Priority Level (PWM_F IPL)—Bits 11–10

This field is used to set the interrupt priority level for the PWM Fault Interrupt IRQ. This IRQ is limited

to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.7.3

Reload PWM Interrupt Priority Level (PWM_RL IPL)—Bits 9–8

This field is used to set the interrupt priority level for the Reload PWM Interrupt IRQ. This IRQ is limited

to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.7.4

ADC Zero Crossing Interrupt Priority Level (ADC_ZC IPL)—Bits 7–6

This field is used to set the interrupt priority level for the ADC Zero Crossing IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

85

5.6.7.5

ADC B Conversion Complete Interrupt Priority Level

(ADCB_CC IPL)—Bits 5–4

This field is used to set the interrupt priority level for the ADC B Conversion Complete IRQ. This IRQ is

limited to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.7.6

ADC A Conversion Complete Interrupt Priority Level

(ADCA_CC IPL)—Bits 3–2

This field is used to set the interrupt priority level for the ADC A Conversion Complete IRQ. This IRQ is

limited to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.7.7

Programmable Interval Timer 2 Interrupt Priority Level

(PIT2 IPL)—Bits 1–0

This field is used to set the interrupt priority level for the Programmable Interval Timer 2 IRQ. This IRQ

is limited to priorities 0 through 2. It is disabled by default.

•

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.8

Vector Base Address Register (VBA)

Base + $7

Read

15

0

14

0

13

12

11

10

9

8

7

6

5

4

0

3

0

2

0

1

0

VECTOR_BASE_ADDRESS

Write

RESET¹

0

1. The 56F8037 resets to a value of 0x0000. This corresponds to reset addresses of 0x000000.

The 56F8027 resets to a value of 0x0080. This corresponds to reset addresses of 0x004000.

Figure 5-10 Vector Base Address Register (VBA)

5.6.8.1

Reserved—Bits 15–14

This bit field is reserved. Each bit must be set to 0.

56F8037/56F8027 Data Sheet, Rev. 8

86

FreescaleSemiconductor

Register Descriptions

5.6.8.2

Vector Address Bus (VAB) Bits 13–0

The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower 7 bits

are determined based on the highest priority interrupt and are then appended onto VBA before presenting

the full VAB to the Core.

5.6.9

Fast Interrupt Match 0 Register (FIM0)

Base + $8

Read

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

2

1

0

FAST INTERRUPT 0

Write

RESET

0

Figure 5-11 Fast Interrupt Match 0 Register (FIM0)

5.6.9.1

Reserved—Bits 15–6

This bit field is reserved. Each bit must be set to 0.

5.6.9.2

Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 5–0

These values determine which IRQ will be Fast Interrupt 0. Fast Interrupts vector directly to a service

routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table

first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast

Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority

level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt.

Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to

the vector table.

5.6.10 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

Base + $9

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

1

0

FAST INTERRUPT 0 VECTOR ADDRESS LOW

Write

0

RESET

Figure 5-12 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

5.6.10.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0

The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0

to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

87

5.6.11 Fast Interrupt 0 Vector Address High Register (FIVAH0)

Base + $A

Read

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

3

2

1

0

FAST INTERRUPT 0 VECTOR

ADDRESS HIGH

Write

0

RESET

Figure 5-13 Fast Interrupt 0 Vector Address High Register (FIVAH0)

5.6.11.1 Reserved—Bits 15–5

This bit field is reserved. Each bit must be set to 0.

5.6.11.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0

The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0

to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

5.6.12 Fast Interrupt 1 Match Register (FIM1)

Base + $B

Read

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

2

1

0

FAST INTERRUPT 1

Write

0

RESET

Figure 5-14 Fast Interrupt 1 Match Register (FIM1)

5.6.12.1 Reserved—Bits 15–6

This bit field is reserved. Each bit must be set to 0.

5.6.12.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 5–0

These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service

routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table

first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast

Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest priority

level 2 interrupt, regardless of its location in the interrupt table prior to being declared as Fast Interrupt.

Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to

the vector table.

5.6.13 Fast Interrupt 1 Vector Address Low Register (FIVAL1)

Base + $C

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

1

0

FAST INTERRUPT 1 VECTOR ADDRESS LOW

Write

0

RESET

Figure 5-15 Fast Interrupt 1 Vector Address Low Register (FIVAL1)

56F8037/56F8027 Data Sheet, Rev. 8

88

FreescaleSemiconductor

Register Descriptions

5.6.13.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0

The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1

to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.6.14 Fast Interrupt 1 Vector Address High (FIVAH1)

Base + $D

Read

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

2

1

0

FAST INTERRUPT 1 VECTOR

ADDRESS HIGH

Write

0

RESET

Figure 5-16 Fast Interrupt 1 Vector Address High Register (FIVAH1)

5.6.14.1 Reserved—Bits 15–5

This bit field is reserved. Each bit must be set to 0.

5.6.14.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0

The upper five bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAL1

to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.6.15 IRQ Pending Register 0 (IRQP0)

Base + $E

Read

15

14

13

12

11

10

9

8

7

6

1

5

1

4

1

3

1

2

1

0

1

PENDING[16:2]

Write

1

RESET

Figure 5-17 IRQ Pending Register 0 (IRQP0)

5.6.15.1 IRQ Pending (PENDING)—Bits 16–2

This register bit values represent the pending IRQs for interrupt vector numbers 2 through 16. Ascending

IRQ numbers correspond to ascending bit locations.

•

0 = IRQ pending for this vector number

1 = No IRQ pending for this vector number

5.6.15.2 Reserved—Bit 0

This bit field is reserved. It must be set to 0.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

89

5.6.16 IRQ Pending Register 1 (IRQP1)

Base + $F

Read

15

14

13

12

11

10

9

8

7

6

1

5

1

4

1

3

1

2

1

0

1

PENDING[32:17]

Write

1

RESET

Figure 5-18 IRQ Pending Register 1 (IRQP1)

5.6.16.1 IRQ Pending (PENDING)—Bits 32–17

This register bit values represent the pending IRQs for interrupt vector numbers 17 through 32. Ascending

IRQ numbers correspond to ascending bit locations.

•

0 = IRQ pending for this vector number

1 = No IRQ pending for this vector number

5.6.17 IRQ Pending Register 2 (IRQP2)

Base + $10

Read

15

14

13

12

11

10

9

8

7

6

1

5

1

4

1

3

1

2

1

0

1

PENDING[48:33]

Write

RESET

1

Figure 5-19 IRQ Pending Register 2 (IRQP2)

5.6.17.1 IRQ Pending (PENDING)—Bits 48–33

This register bit values represent the pending IRQs for interrupt vector numbers 33 through 48. Ascending

IRQ numbers correspond to ascending bit locations.

•

0 = IRQ pending for this vector number

1 = No IRQ pending for this vector number

5.6.18 IRQ Pending Register 3 (IRQP3)

Base + $11

Read

15

1

14

13

12

11

10

9

8

7

6

5

1

4

1

3

1

2

1

0

1

PENDING[63:49]

Write

RESET

1

Figure 5-20 IRQ Pending Register 3 (IRQP3)

5.6.18.1 IRQ Pending (PENDING)—Bits 63–49

This register bit values represent the pending IRQs for interrupt vector numbers 49 through 63. Ascending

IRQ numbers correspond to ascending bit locations.

•

0 = IRQ pending for this vector number

1 = No IRQ pending for this vector number

56F8037/56F8027 Data Sheet, Rev. 8

90

FreescaleSemiconductor

Register Descriptions

5.6.18.2 Reserved—Bit 15

This bit field is reserved. When it is read, it has a value of 1.

5.6.19 Interrupt Control Register (ICTRL)

$Base + $16

Read

15

14

13

12

11

10

9

8

7

0

6

0

5

4

1

3

1

2

1

0

INT

IPIC

VAB

INT_

DIS

Write

0

1

0

RESET

Figure 5-21 Interrupt Control Register (ICTRL)

5.6.19.1 Interrupt (INT)—Bit 15

This read-only bit reflects the state of the interrupt to the 56800E core.

•

0 = No interrupt is being sent to the 56800E core

1 = An interrupt is being sent to the 56800E core

5.6.19.2 Interrupt Priority Level (IPIC)—Bits 14–13

These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E

core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being

sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service

routine.

Note:

Nested interrupts may cause this field to be updated before the original interrupt service routine can

read it.

•

00 = Required nested exception priority levels are 0, 1, 2, or 3

01 = Required nested exception priority levels are 1, 2, or 3

10 = Required nested exception priority levels are 2 or 3

11 = Required nested exception priority level is 3

Table 5-4 Interrupt Priority Encoding

Current Interrupt

Priority Level

Required Nested

Exception Priority

IPIC_VALUE[1:0]

00

01

10

11

No interrupt or SWILP

Priority 0

Priorities 0, 1, 2, 3

Priorities 1, 2, 3

Priorities 2, 3

Priority 3

Priority 1

Priority 2 or 3

5.6.19.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6

This read-only field shows bits [7:1] of the Vector Address Bus used at the time the last IRQ was taken.

In the case of a Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

91

when the 56800E core jumps to a new interrupt service routine.

Note:

Nested interrupts may cause this field to be updated before the original interrupt service routine can

read it.

5.6.19.4 Interrupt Disable (INT_DIS)—Bit 5

This bit allows all interrupts to be disabled.

•

0 = Normal operation (default)

1 = All interrupts disabled

5.6.19.5 Reserved—Bits 4-2

This bit field is reserved. Each bit must be set to 1.

5.6.19.6 Reserved—Bits 1–0

This bit field is reserved. Each bit must be set to 0.

5.7 Resets

5.7.1

General

Table 5-5 Reset Summary

Source

Characteristics

Reset

Priority

Core Reset

RST

Core reset from the SIM

5.7.2

Description of Reset Operation

Reset Handshake Timing

5.7.2.1

The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is

asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET

is released. The general timing is shown in Figure 5-22.

RES

CLK

RESET_VECTOR_ADR

VAB

PAB

READ_ADR

Figure 5-22 Reset Interface

56F8037/56F8027 Data Sheet, Rev. 8

92

FreescaleSemiconductor

Introduction

5.7.3

ITCN After Reset

After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,

except the core IRQs with fixed priorities:

•

Illegal Instruction

SW Interrupt 3

HW Stack Overflow

Misaligned Long Word Access

SW Interrupt 2

SW Interrupt 1

SW Interrupt 0

SW Interrupt LP

These interrupts are enabled at their fixed priority levels.

Part 6 System Integration Module (SIM)

6.1 Introduction

The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls

distribution of resets and clocks and provides a number of control features. The System Integration

Module’s functions are discussed in more detail in the following sections.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

93

6.2 Features

The SIM has the following features:

•

Chip reset sequencing

Core and peripheral clock control and distribution

Stop/Wait mode control

System status control

Registers containing the JTAG ID of the chip

Controls for programmable peripheral and GPIO connections

Peripheral clocks for TMR and PWM with a high-speed (3X) option

Power-saving clock gating for peripherals

Three power modes (Run, Wait, Stop) to control power utilization

— Stop mode shuts down the 56800E core, system clock, and peripheral clock

— Wait mode shuts down the 56800E core and unnecessary system clock operation

— Run mode supports full device operation

•

Controls the enable/disable functions of the 56800E core WAIT and STOP instructions with write protection

capability

•

Controls the enable/disable functions of Large Regulator Standby mode with write protection capability

Permits selected peripherals to run in Stop mode to generate Stop recovery interrupts

Controls for programmable peripheral and GPIO connections

Software chip reset

I/O short address base location control

Peripheral protection control to provide runaway code protection for safety-critical applications

Controls output of internal clock sources to CLKO pin

Four general-purpose software control registers are reset only at power-on

Peripherals Stop mode clocking control

56F8037/56F8027 Data Sheet, Rev. 8

94

FreescaleSemiconductor

Register Descriptions

6.3 Register Descriptions

A write to an address without an associated register is an NOP. A read from an address without an

associated register returns unknown data.

Table 6-1 SIM Registers (SIM_BASE = $00 F100)

Register

Acronym

Section

Location

Base Address +

Register Name

CTRL

$0

$1

$2

$3

$4

$5

$6

$7

$8

Control Register

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

RSTAT

SWC0

SWC1

SWC2

SWC3

MSHID

LSHID

PWR

Reset Status Register

Software Control Register 0

Software Control Register 1

Software Control Register 2

Software Control Register 3

Most Significant Half of JTAG ID

Least Significant Half of JTAG ID

Power Control Register

Reserved

CLKOUT

PCR

$A

$B

CLKO Select Register

6.3.7

6.3.8

Peripheral Clock Rate Register

PCE0

PCE1

SD0

$C

Peripheral Clock Enable Register 0

Stop Disable Register 0

6.3.9

$D

6.3.10

6.3.11

6.3.12

6.3.13

6.3.14

6.3.15

6.3.16

6.3.17

6.3.18

6.3.19

6.3.20

6.3.21

6.3.22

6.3.23

$E

SD1

$F

Stop Disable Register 1

IOSAHI

IOSALO

PROT

GPSA0

GPSA1

GPSB0

GPSB1

GPSCD

IPS0

$10

$11

$12

$13

$14

$15

$16

$17

$18

$19

$1A

I/O Short Address Location High Register

I/O Short Address Location Low Register

Protection Register

GPIO Peripheral Select Register 0 for GPIOA

GPIO Peripheral Select Register 1 for GPIOA

GPIO Peripheral Select Register 0 for GPIOB

GPIO Peripheral Select Register 1 for GPIOB

GPIO Peripheral Select Register for GPIOC and GPIOD

Internal Peripheral Source Select Register 0 for PWM

Internal Peripheral Source Select Register 1 for DACs

Internal Peripheral Source Select Register 2 for Quad Timer A

Reserved

IPS1

IPS2

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

95

Add.

Address

Offset Acronym

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

0

SIM_

CTRL

ONCE SW

EBL0 RST

STOP_

DISABLE

WAIT_

DISABLE

$0

W

COP_ COP_

R

0

SWR

EXTR POR

0

SIM_

$1

TOR

LOR

RSTAT

W

R

$2

$3

$4

$5

$6

$7

$8

SIM_SWC0

SIM_SWC1

SIM_SWC2

SIM_SWC3

SIM_MSHID

SIM_LSHID

Software Control Data 0

Software Control Data 1

Software Control Data 2

Software Control Data 3

W

R

W

R

W

R

W

R

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

W

R

W

R

SIM_PWR

Reserved

LRSTDBY

W

R

W

R

0

CLKOSEL

0

SIM_

CLKOUT

CLK

DIS

$A

$B

$C

$D

$E

$F

PWM3 PWM2 PWM1 PWM0

0

TMRB_ TMRA_ PWM_C I2C_

CR CR CR

SIM_PCR

SIM_PCE0

SIM_PCE1

SIM_SD0

SIM_SD1

R

W

R

CMPB CMPA DAC1 DAC0

0

ADC

0

I2C QSCI1 QSCI0 QSPI1 QSPI0

PWM

TA0

W

R

PIT2

PIT1

PIT0

TB3

0

TB2

TB1

TB0

TA3

TA2

TA1

0

W

R

CMPB_ CMPA_ DAC1_S DAC0_

SD

ADC_

SD

I2C_ QSCI1 QSCI0 QSPI1 QSPI0

SD _SD _SD _SD _SD

PWM_

SD

D

SD

W

R

0

PIT2_ PIT1_S PIT0_

TB3_ TB2_ TB1_ TB0_ TA3_ TA2_ TA1_ TA0_

SD

0

D

0

SD

0

SD

W

R

0

$10 SIM_IOSAHI

$11 SIM_IOSALO

ISAL[23:22]

W

R

ISAL[21:6]

0

W

R

0

$12

SIM_PROT

PCEP

GIPSP

W

R

0

GPS_

A6

$13 SIM_GPSA0

$14 SIM_GPSA1

$15 SIM_GPSB0

$16 SIM_GPSB1

$17 SIM_GPSCD

GPS_A5

GPS_A4

W

R

GPS_

A11

GPS_

A10

GPS_A14

GPS_A13

GPS_A12

GPS_A9

GPS_A8

W

R

0

GPS_

B1

GPS_

B0

GPS_B6

GPS_B5

GPS_B4

GPS_B3

GPS_B2

W

R

0

GPS_

B11

GPS_

B10

GPS_

B9

GPS_

B8

GPS_

B7

W

R

0

GPS_

D5

GPS_

C12

GPS_

C8

W

R

0

IPS0_

FAULT2

IPS0_

FAULT1

$18

$19

SIM_IPS0

SIM_IPS1

IPS0_PSRC2

0

IPS0_PSRC1

IPS0_PSRC0

W

R

0

IPS1_DSYNC1

IPS1_DSYNC0

W

56F8037/56F8027 Data Sheet, Rev. 8

96

FreescaleSemiconductor

Register Descriptions

R

0

1

0

IPS2_

TA3

IPS2_

TA2

IPS2_

TA1

$1A

SIM_IPS2

Reserved

W

= Read as 0

= Read as 1

= Reserved

Figure 6-1 SIM Register Map Summary

6.3.1

SIM Control Register (SIM_CTRL)

Base + $0

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ONCE SW

STOP_

WAIT_

EBL

RST

DISABLE

Write

0

RESET

Figure 6-2 SIM Control Register (SIM_CTRL)

6.3.1.1

Reserved—Bits 15–6

This bit field is reserved. Each bit must be set to 0.

6.3.1.2

OnCE Enable (ONCEEBL)—Bit 5

•

0 = OnCE clock to 56800E core enabled when core TAP is enabled

1 = OnCE clock to 56800E core is always enabled

Note:

Using default state “0” is recommended.

6.3.1.3

Software Reset (SWRST)—Bit 4

•

Writing 1 to this field will cause the device to reset

Read is zero

6.3.1.4

Stop Disable (STOP_DISABLE)—Bits 3–2

•

00 = Stop mode will be entered when the 56800E core executes a STOP instruction

01 = The 56800E STOP instruction will not cause entry into Stop mode

10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the

STOP_DISABLE field is write-protected until the next reset

•

11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is

write-protected until the next reset

6.3.1.5

Wait Disable (WAIT_DISABLE)—Bits 1–0

•

00 = Wait mode will be entered when the 56800E core executes a WAIT instruction

01 = The 56800E WAIT instruction will not cause entry into Wait mode

10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the

WAIT_DISABLE field is write-protected until the next reset

•

11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is

write-protected until the next reset

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

97

6.3.2

SIM Reset Status Register (SIM_RSTAT)

This read-only register is updated upon any system reset and indicates the cause of the most recent reset.

It indicates whether the COP reset vector or regular reset vector (including Power-On Reset, External

Reset, Software Reset) in the vector table is used. This register is asynchronously reset during Power-On

Reset and subsequently is synchronously updated based on the precedence level of reset inputs. Only the

most recent reset source will be indicated if multiple resets occur. If multiple reset sources assert

simultaneously, the highest-precedence source will be indicated. The precedence from highest to lowest is

Power-On Reset, External Reset, COP Loss of Reference Reset, COP Time-Out Reset, and Software

Reset. Power-On Reset is always set during a Power-On Reset; however, Power-On Reset will be cleared

and External Reset will be set if the external reset pin is asserted or remains asserted after the Power-On

Reset has deasserted.

Base + $1

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

COP_ COP_

TOR

0

SWR

EXTR POR

0

LOR

Write

RESET

0

1

0

Figure 6-3 SIM Reset Status Register (SIM_RSTAT)

6.3.2.1

Reserved—Bits 15–7

This bit field is reserved. Each bit must be set to 0.

6.3.2.2

Software Reset (SWR)—Bit 6

When set, this bit indicates that the previous system reset occurred as a result of a software reset (written

1 to SWRST bit in the SIM_CTRL register).

6.3.2.3

COP Time-Out Reset (COP_TOR)—Bit 5

When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly

(COP) module signaling a COP time-out reset. If COP_TOR is set as code starts executing, the COP reset

vector in the vector table will be used. Otherwise, the normal reset vector is used.

6.3.2.4

COP Loss of Reference Reset (COP_LOR)—Bit 4

When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly

(COP) module signaling a loss of COP reference clock reset. If COP_LOR is set as code starts executing,

the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used.

6.3.2.5

External Reset (EXTR)—Bit 3

When set, this bit indicates that the previous system reset was caused by an external reset.

6.3.2.6

Power-On Reset (POR)—Bit 2

This bit is set during a Power-On Reset.

56F8037/56F8027 Data Sheet, Rev. 8

98

FreescaleSemiconductor

Register Descriptions

6.3.2.7

Reserved—Bits 1–0

This bit field is reserved. Each bit must be set to 0.

6.3.3

SIM Software Control Registers (SIM_SWC0, SIM_SWC1,

SIM_SWC2, and SIM_SWC3)

These registers are general-purpose registers. They are reset only at power-on, so they can monitor

software execution flow.

Base + $2

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Software Control Data 0 - 3

Write

0

RESET

Figure 6-4 SIM Software Control Register 0 (SIM_SWC0 - 3)

Software Control Register 0 - 3 (FIELD)—Bits 15–0

6.3.3.1

This register is reset only by the Power-On Reset (POR). It is intended for use by a software developer to

contain data that will be unaffected by the other reset sources (external reset, software reset, and COP

reset).

6.3.4

Most Significant Half of JTAG ID (SIM_MSHID)

This read-only register displays the most significant half of the JTAG ID for the chip. This register reads

$01F2.

Base + $6

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

Write

RESET

0

1

0

1

0

Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID)

6.3.5

Least Significant Half of JTAG ID (SIM_LSHID)

This read-only register displays the least significant half of the JTAG ID for the chip. This register reads

$801D.

Base + $7

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

Write

RESET

1

0

1

0

1

Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID)

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

99

6.3.6

SIM Power Control Register (SIM_PWR)

This register controls the Standby mode of the large on-chip regulator. The large on-chip regulator derives

the core digital logic power supply from the IO power supply. At a system bus frequency of 200kHz, the

large regulator may be put in a reduced-power standby mode without interfering with device operation to

reduce device power consumption. Refer to the overview of power-down modes and the overview of clock

generation for more information on the use of large regulator standby.

Base + $8

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LRSTDBY

Write

0

RESET

Figure 6-7 SIM Power Control Register (SIM_PWR)

6.3.6.1

Reserved—Bits 15–2

This bit field is reserved. Each bit must be set to 0.

6.3.6.2

Large Regulator Standby Mode[1:0] (LRSTDBY)—Bits 1–0

•

00 = Large regulator is in Normal mode

01 = Large regulator is in Standby (reduced-power) mode

10 = Large regulator is in Normal mode and the LRSTDBY field is write-protected until the next reset

11 = Large regulator is in Standby mode and the LRSTDBY field is write-protected until the next reset

6.3.7

Clock Output Select Register (SIM_CLKOUT)

The Clock Output Select register can be used to multiplex out selected clock sources generated inside the

clock generation and SIM modules onto the muxed clock output pins. All functionality is for test purposes

only. Glitches may be produced when the clock is enabled or switched. The delay from the clock source

to the output is unspecified. The observability of the CLKO clock output signal at an output pad is subject

to the frequency limitations of the associated IO cell.

GPIOA[3:0] can function as GPIO, PWM, or as clock output pins. If GPIOA[3:0] are programmed to

operate as peripheral outputs, then the choice is between PWM and clock outputs. The default state is for

the peripheral function of GPIOA[3:0] to be programmed as PWM (selected by bits [9:6] of the Clock

Output Select register).

GPIOB4 can function as GPIO, or as other peripheral outputs, including clock output (CLKO). If GPIOB4

is programmed to operate as a peripheral output and CLKO is selected in the SIM_GPSB0 register, bits

[4:0] decide if CLKO is enabled or disabled and which clock source is selected if CLKO is enabled. See

Figure 6-8 for details.

56F8037/56F8027 Data Sheet, Rev. 8

100

FreescaleSemiconductor

Register Descriptions

Base + $A

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

CLKOSEL

0

1

0

CLK

DIS

PWM3 PWM2 PWM1 PWM0

Write

0

1

0

RESET

Figure 6-8 CLKO Select Register (SIM_CLKOUT)

6.3.7.1

Reserved—Bits 15–10

This bit field is reserved. Each bit must be set to 0.

6.3.7.2

PWM3—Bit 9

•

0 = Peripheral output function of GPIOA[3] is defined to be PWM3

1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock

6.3.7.3

PWM2—Bit 8

•

0 = Peripheral output function of GPIOA[2] is defined to be PWM2

1 = Peripheral output function of GPIOA[2] is defined to be the system clock

6.3.7.4

PWM1—Bit 7

•

0 = Peripheral output function of GPIOA[1] is defined to be PWM1

1 = Peripheral output function of GPIOA[1] is defined to be 2X system clock

6.3.7.5

PWM0—Bit 6

•

0 = Peripheral output function of GPIOA[0] is defined to be PWM0

1 = Peripheral output function of GPIOA[0] is defined to be 3X system clock

6.3.7.6

Clockout Disable (CLKDIS)—Bit 5

•

0 = CLKOUT output function is enabled and will output the signal indicated by CLKOSEL

1 = CLKOUT output function is disabled

6.3.7.7

Clockout Select (CLKOSEL)—Bits 4–0

CLKOSEL selects clock to be muxed out on the CLKO pin as defined in the following. Internal delay to

CLKO output is unspecified. Signal at the output pad is undefined when CLKO signal frequency exceeds

the rated frequency of the I/O cell. CLKO may not operate as expected when CLKDIS and CLKOSEL

settings are changed.

•

00000 = Continuous system clock

00001 = Continuous peripheral clock

00010 = 3X system clock

00100.....11111 = Reserved for factory test

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

101

6.3.8

Peripheral Clock Rate Register (SIM_PCR)

By default, all peripherals are clocked at the system clock rate, which has a maximum of 32MHz. Selected

peripherals clocks have the option to be clocked at 3X system clock rate, which has a maximum of 96MHz,

if the PLL output clock is selected as the system clock. If PLL is disabled, the 3X system clock will not be

available. This register is used to enable high-speed clocking for those peripherals that support it.

Note:

Operation is unpredictable if peripheral clocks are reconfigured at runtime, so peripherals should be

disabled before a peripheral clock is reconfigured.

Base + $B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Read

Write

TMRB_ TMRA_ PWM_ I2C_

CR

0

RESET

Figure 6-9 Peripheral Clock Rate Register (SIM_PCR)

6.3.8.1

Quad Timer B Clock Rate (TMRB_CR)—Bit 15

This bit selects the clock speed for the Quad Timer B module.

•

0 = Quad Timer B clock rate equals the system clock rate, to a maximum 32MHz (default)

1 = Quad Timer B clock rate equals 3X system clock rate, to a maximum 96MHz

6.3.8.2

Quad Timer A Clock Rate (TMRA_CR)—Bit 14

This bit selects the clock speed for the Quad Timer A module.

•

0 = Quad Timer A clock rate equals the system clock rate, to a maximum 32MHz (default)

1 = Quad Timer A clock rate equals 3X system clock rate, to a maximum 96MHz

6.3.8.3

Pulse Width Modulator Clock Rate (PWM_CR)—Bit 13

This bit selects the clock speed for the PWM module.

•

0 = PWM module clock rate equals the system clock rate, to a maximum 32MHz (default)

1 = PWM module clock rate equals 3X system clock rate, to a maximum 96MHz

6.3.8.4

Inter-Integrated Circuit Run Clock Rate (I2C_CR)—Bit 12

2

This bit selects the clock speed for the I C run clock.

•

0 = I²C module run clock rate equals the system clock rate, to a maximum 32MHz (default)

1 = I²C module run clock rate equals 3X system clock rate, to a maximum 96MHz

6.3.8.5

Reserved—Bits 11–0

This bit field is reserved. Each bit must be set to 0.

56F8037/56F8027 Data Sheet, Rev. 8

102

FreescaleSemiconductor

Register Descriptions

6.3.9

Peripheral Clock Enable Register 0 (SIM_PCE0)

The Peripheral Clock Enable register enables or disables clocks to the peripherals as a power savings

feature. Significant power savings are achieved by enabling only the peripheral clocks that are in use.

When a peripheral’s clock is disabled, that peripheral is in Stop mode. Accesses made to a module that has

its clock disabled will have no effect. The corresponding peripheral should itself be disabled while its clock

is shut off. IPBus writes are not possible.

Setting the PCE bit does not guarantee that the peripheral’s clock is running. Enabled peripheral clocks

will still become disabled in Stop mode, unless the peripheral’s Stop Disable control in the SDn register

is set to 1.

Note:

The MSCAN module supports extended power management capabilities, including Sleep,

Stop-in-Wait, and Disable modes. MSCAN clocks are selected by MSCAN control registers. Refer to

the 56F802x and 56F803x Peripheral Reference Manual for details.

Base + $C

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Read

Write

CMPB CMPA DAC1 DAC0

ADC

I2C

QSCI1 QSCI0 QSPI1 QSPI0

PWM

0

RESET

Figure 6-10 Peripheral Clock Enable Register 0 (SIM_PCE0)

Comparator B Clock Enable (CMPB)—Bit 15

6.3.9.1

•

0 = The clock is not provided to the Comparator B module (the Comparator B module is disabled)

1 = The clock is enabled to the Comparator B module

6.3.9.2

Comparator A Clock Enable (CMPA)—Bit 14

•

0 = The clock is not provided to the Comparator A module (the Comparator A module is disabled)

1 = The clock is enabled to the Comparator A module

6.3.9.3

Digital-to-Analog Clock Enable 1 (DAC1)—Bit 13

•

0 = The clock is not provided to the DAC1 module (the DAC1 module is disabled)

1 = The clock is enabled to the DAC1 module

6.3.9.4

Digital-to-Analog Clock Enable 0 (DAC0)—Bit 12

•

0 = The clock is not provided to the DAC0 module (the DAC0 module is disabled)

1 = The clock is enabled to the DAC0 module

6.3.9.5

Reserved—Bit 11

This bit field is reserved. It must be set to 0.

6.3.9.6

Analog-to-Digital Converter Clock Enable (ADC)—Bit 10

•

0 = The clock is not provided to the ADC module (the ADC module is disabled)

1 = The clock is enabled to the ADC module

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

103

6.3.9.7

Reserved—Bits 9–7

This bit field is reserved. Each bit must be set to 0.

6.3.9.8

Inter-Integrated Circuit IPBus Clock Enable (I2C)—Bit 6

•

0 = The clock is not provided to the I²C module (the I²C module is disabled)

1 = The clock is enabled to the I²C module

6.3.9.9

QSCI 1 Clock Enable (QSCI1)—Bit 5

•

0 = The clock is not provided to the QSCI1 module (the QSCI1 module is disabled)

1 = The clock is enabled to the QSCI1 module

6.3.9.10 QSCI 0 Clock Enable (QSCI0)—Bit 4

•

0 = The clock is not provided to the QSCI0 module (the QSCI0 module is disabled)

1 = The clock is enabled to the QSCI0 module

6.3.9.11 QSPI 1 Clock Enable (QSPI1)—Bit 3

•

0 = The clock is not provided to the QSPI1 module (the QSPI1 module is disabled)

1 = The clock is enabled to the QSPI1 module

6.3.9.12 QSPI 0 Clock Enable (QSPI0)—Bit 2

•

0 = The clock is not provided to the QSPI0 module (the QSPI0 module is disabled)

1 = The clock is enabled to the QSPI0 module

6.3.9.13 Reserved—Bit 1

This bit field is reserved. It must be set to 0.

6.3.9.14 PWM Clock Enable (PWM)—Bit 0

•

0 = The clock is not provided to the PWM module (the PWM module is disabled)

1 = The clock is enabled to the PWM module

6.3.10 Peripheral Clock Enable Register 1 (SIM_PCE1)

See Section 6.3.9 for general information about Peripheral Clock Enable registers.

Base + $D

Read

15

14

PIT2

0

13

PIT1

0

12

PIT0

0

11

10

9

8

7

TB3

0

6

TB2

0

5

TB1

0

4

TB0

0

3

TA3

0

2

TA2

0

1

TA1

0

TA0

0

Write

0

RESET

Figure 6-11 Peripheral Clock Enable Register 1 (SIM_PCE1)

56F8037/56F8027 Data Sheet, Rev. 8

104

FreescaleSemiconductor

Register Descriptions

6.3.10.1 Reserved—Bit 15

This bit field is reserved. It must be set to 0.

6.3.10.2 Programmable Interval Timer 2 Clock Enable (PIT2)—Bit 14

•

0 = The clock is not provided to the PIT2 module (the PIT2 module is disabled)

1 = The clock is enabled to the PIT2 module

6.3.10.3 Programmable Interval Timer 1 Clock Enable (PIT1)—Bit 13

•

0 = The clock is not provided to the PIT1 module (the PIT1 module is disabled)

1 = The clock is enabled to the PIT1 module

6.3.10.4 Programmable Interval Timer 0 Clock Enable (PIT0)—Bit 12

•

0 = The clock is not provided to the PIT0 module (the PIT0 module is disabled)

1 = The clock is enabled to the PIT0 module

6.3.10.5 Reserved—Bits 11–8

This bit field is reserved. Each bit must be set to 0.

6.3.10.6 Quad Timer B, Channel 3 Clock Enable (TB3)—Bit 7

•

0 = The clock is not provided to the Timer B3 module (the Timer B3 module is disabled)

1 = The clock is enabled to the Timer B3 module

6.3.10.7 Quad Timer B, Channel 2 Clock Enable (TB2)—Bit 6

•

0 = The clock is not provided to the Timer B2 module (the Timer B2 module is disabled)

1 = The clock is enabled to the Timer B2 module

6.3.10.8 Quad Timer B, Channel 1 Clock Enable (TB1)—Bit 5

•

0 = The clock is not provided to the Timer B1 module (the Timer B1 module is disabled)

1 = The clock is enabled to the Timer B1 module

6.3.10.9 Quad Timer B, Channel 0 Clock Enable (TB0)—Bit 4

•

0 = The clock is not provided to the Timer B0 module (the Timer B0 module is disabled)

1 = The clock is enabled to the Timer B0 module

6.3.10.10 Quad Timer A, Channel 3 Clock Enable (TA3)—Bit 3

•

0 = The clock is not provided to the Timer A3 module (the Timer A3 module is disabled)

1 = The clock is enabled to the Timer A3 module

6.3.10.11 Quad Timer A, Channel 2 Clock Enable (TA2)—Bit 2

•

0 = The clock is not provided to the Timer A2 module (the Timer A2 module is disabled)

1 = The clock is enabled to the Timer A2 module

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

105

6.3.10.12 Quad Timer A, Channel 1 Clock Enable (TA1)—Bit 1

•

0 = The clock is not provided to the Timer A1 module (the Timer A1 module is disabled)

1 = The clock is enabled to the Timer A1 module

6.3.10.13 Quad Timer A, Channel 0 Clock Enable (TA0)—Bit 0

•

0 = The clock is not provided to the Timer A0 module (the Timer A0 module is disabled)

1 = The clock is enabled to the Timer A0 module

6.3.11 Stop Disable Register 0 (SD0)

By default, peripheral clocks are disabled during Stop mode in order to maximize power savings. This

register will allow an individual peripheral to operate in Stop mode. Since asserting an interrupt causes the

system to return to Run mode, this feature is provided so that selected peripherals can be left operating in

Stop mode for the purpose of generating a wake-up interrupt.

For power-conscious applications, it is recommended that only a minimum set of peripherals be

configured to remain operational during Stop mode.

Peripherals should be put in a non-operating (disabled) configuration prior to entering Stop mode unless

their corresponding Stop Disable control is set to 1. Refer to the 56F802x and 56F803x Peripheral

Reference Manual for further details. Reads and writes cannot be made to a module that has its clock

disabled.

Note:

The MSCAN module supports extended power management capabilities including Sleep,

Stop-in-Wait, and Disable modes. MSCAN clocks are selected by MSCAN control registers. For

details, refer to the 56F802x and 56F803x Peripheral Reference Manual.

Base + $E

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Read

Write

CMPB_ CMPA_ DAC1_ DAC0_

ADC_

SD

I2C_ QSCI1 QSCI0 QSPI1 QSPI0

PWM_

SD

_SD

0

RESET

Figure 6-12 Stop Disable Register 0 (SD0)

6.3.11.1 Comparator B Clock Stop Disable (CMPB_SD)—Bit 15

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

register

6.3.11.2 Comparator A Clock Stop Disable (CMPA_SD)—Bit 14

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

register

56F8037/56F8027 Data Sheet, Rev. 8

106

FreescaleSemiconductor

Register Descriptions

6.3.11.3 Digital-to-Analog Converter 1 Clock Stop Disable (DAC1_SD)—Bit 13

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

register

6.3.11.4 Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)—Bit 12

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

register

6.3.11.5 Reserved—Bit 11

This bit field is reserved. It must be set to 0.

6.3.11.6 Analog-to-Digital Converter Clock Stop Disable (ADC_SD)—Bit 10

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

register

6.3.11.7 Reserved—Bits 9–7

This bit field is reserved. Each bit must be set to 0.

6.3.11.8 Inter-Integrated Circuit Clock Stop Disable (I2C_SD)—Bit 6

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

register

6.3.11.9 QSCI1 Clock Stop Disable (QSCI1_SD)—Bit 5

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

register

6.3.11.10 QSCI0 Clock Stop Disable (QSCI0_SD)—Bit 4

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

register

6.3.11.11 QSPI1 Clock Stop Disable (QSPI1_SD)—Bit 3

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

register

6.3.11.12 QSPI0 Clock Stop Disable (QSPI0_SD)—Bit 2

Each bit controls clocks to the indicated peripheral.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

107

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

register

6.3.11.13 Reserved—Bit 1

This bit field is reserved. It must be set to 0.

6.3.11.14 PWM Clock Stop Disable (PWM_SD)—Bit 0

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

register

6.3.12 Stop Disable Register 1 (SD1)

See Section 6.3.11 for general information about Stop Disable Registers.

Base + $F

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PIT2_ PIT1_

SD

PIT0_

SD

TB3_ TB2_

SD

TB1_

SD

TB0_ TA3_

SD

TA2_ TA1_ TA0_

SD

Write

0

RESET

Figure 6-13 Stop Disable Register 1 (SD1)

6.3.12.1 Reserved—Bit 15

This bit field is reserved. It must be set to 0.

6.3.12.2 Programmable Interval Timer 2 Clock Stop Disable (PIT2_SD)—Bit 14

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

register

6.3.12.3 Programmable Interval Timer 1 Clock Stop Disable (PIT1_SD)—Bit 13

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

register

6.3.12.4 Programmable Interval Timer 0 Clock Stop Disable (PIT0_SD)—Bit 12

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

register

6.3.12.5 Reserved—Bits 11–8

This bit field is reserved. Each bit must be set to 0.

56F8037/56F8027 Data Sheet, Rev. 8

108

FreescaleSemiconductor

Register Descriptions

6.3.12.6 Quad Timer B, Channel 3 Clock Stop Disable (TB3_SD)—Bit 7

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

register

6.3.12.7 Quad Timer B, Channel 2 Clock Stop Disable (TB2_SD)—Bit 6

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

register

6.3.12.8 Quad Timer B, Channel 1 Clock Stop Disable (TB1_SD)—Bit 5

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

register

6.3.12.9 Quad Timer B, Channel 0 Clock Stop Disable (TB0_SD)—Bit 4

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

register

6.3.12.10 Quad Timer A, Channel 3 Clock Stop Disable (TA3_SD)—Bit 3

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

register

6.3.12.11 Quad Timer A, Channel 2 Clock Stop Disable (TA2_SD)—Bit 2

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

register

6.3.12.12 Quad Timer A, Channel 1 Clock Stop Disable (TA1_SD)—Bit 1

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

register

6.3.12.13 Quad Timer A, Channel 0 Clock Stop Disable (TA0_SD)—Bit 0

•

0 = The clock is disabled during Stop mode

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1

register

6.3.13 I/O Short Address Location Register High (SIM_IOSAHI)

In I/O short address mode, the instruction specifies only 6 LSBs of the effective address; the upper 18 bits

are “hard coded” to a specific area of memory. This scheme allows efficient access to a 64-location area

in peripheral space with single word instruction. Short address location registers specify the upper 18 bits

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

109

of I/O address, which are “hard coded”. These registers allow access to peripherals using I/O short address

mode, regardless of the physical location of the peripheral, as shown in Figure 6-14.

Instruction Portion

“Hard Coded” Address Portion

6 Bits from I/O Short Address Mode Instruction

16 Bits from SIM_IOSALO Register

2 bits from SIM_IOSAHI Register

Full 24-Bit for Short I/O Address

Figure 6-14 I/O Short Address Determination

With this register set, software can set the SIM_IOSAHI and SIM_IOSALO registers to point to its

peripheral registers and then use the I/O short addressing mode to access them.

Note:

The default value of this register set points to the EOnCE registers.

The pipeline delay between setting this register set and using short I/O addressing with the new value

is five instruction cycles.

Base + $10

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ISAL[23:22]

Write

0

1

RESET

Figure 6-15 I/O Short Address Location High Register (SIM_IOSAHI)

6.3.13.1 Reserved—Bits 15—2

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.13.2 Input/Output Short Address Location (ISAL[23:22])—Bits 1–0

This field represents the upper two address bits of the “hard coded” I/O short address.

6.3.14 I/O Short Address Location Register Low (SIM_IOSALO)

See Section 6.3.13 for general information about I/O short address location registers.

56F8037/56F8027 Data Sheet, Rev. 8

110

FreescaleSemiconductor

Register Descriptions

Base + $11

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ISAL[21:6]

Write

1

RESET

Figure 6-16 I/O Short Address Location Low Register (SIM_IOSALO)

6.3.14.1 Input/Output Short Address Location (ISAL[21:6])—Bits 15–0

This field represents the lower 16 address bits of the “hard coded” I/O short address.

6.3.15 Protection Register (SIM_PROT)

This register provides write protection of selected control fields for safety-critical applications. The

primary purpose is to prevent unsafe conditions due to the unintentional modification of these fields

between the onset of a code runaway and a reset by the COP watchdog. The GPIO and Internal Peripheral

Select Protection (GIPSP) field protects the contents of registers in the SIM and GPIO modules that control

inter-peripheral signal muxing and GPIO configuration. The Peripheral Clock Enable Protection (PCEP)

field protects the SIM registers’ contents, which contain peripheral clock controls. Some peripherals

provide additional safety features. Refer to the 56F802x and 56F803x Peripheral Reference Manual for

details.

Flexibility is provided so that write protection control values may themselves be optionally locked

(write-protected). Protection controls in this register have two bit values which determine the setting of the

control and whether the value is locked. While a protection control remains unlocked, protection can be

disabled and re-enabled by software. Once a protection control is locked, its value can only be altered by

a chip reset, which restores its default non-locked value.

Base + $12

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PCEP

GIPSP

Write

0

RESET

Figure 6-17 Protection Register (SIM_PROT)

6.3.15.1 Reserved—Bits 15–4

This bit field is reserved. Each bit must be set to 0.

6.3.15.2 Peripheral Clock Enable Protection (PCEP)—Bits 3–2

These bits enable write protection of all fields in the PCEn, SDn, and PCR registers in the SIM module.

•

00 = Write protection off (default)

01 = Write protection on

10 = Write protection off and locked until chip reset

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

111

•

11 = Write protection on and locked until chip reset

6.3.15.3 GPIO and Internal Peripheral Select Protection (GIPSP)—Bits 1–0

These bits enable write protection of GPSn and IPSn registers in the SIM module and write protect all

GPIOx_PEREN, GPIOx_PPOUTM and GPIOx_DRIVE registers in GPIO modules.

•

00 = Write protection off (default)

01 = Write protection on

10 = Write protection off and locked until chip reset

11 = Write protection on and locked until chip reset

Note:

The PWM fields in the CLKOUT register are also write protected by GIPSP. They are reserved for

in-house test only.

6.3.16 SIM GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0)

Most I/O pins have an associated GPIO function. In addition to the GPIO function, I/O can be configured

to be one of several peripheral functions. The GPIOx_PEREN register within the GPIO module controls

the selection between peripheral or GPIO control of the I/O pins. The GPIO function is selected when the

GPIOx_PEREN bit for the I/O is 0. When the GPIOx_PEREN bit of the GPIO is 1, the fields in the GPSn

registers select which peripheral function has control of the I/O. Figure 6-18 illustrates the output path to

an I/O pin when an I/O has two peripheral functions. Similar muxing is required on peripheral function

inputs to receive input from the properly selected I/O pin.

GPIOA6_PEREN

Register

SIM_GPSA0

Register

GPIOA6

0

GPIOA6 pin

PWM

FAULT0

0

1

Timer A0

Figure 6-18 Overall Control of Signal Source Using SIM_GPSnn Control

In some cases, the user can choose peripheral function between several I/O, each of which have the option

to be programmed to control a specific peripheral function. If the user wishes to use that function, only one

of these I/O must be configured to control that peripheral function. If more than one I/O is configured to

control the peripheral function, the peripheral output signal will fan out to each I/O, but the peripheral input

signal will be the logical OR and AND of all the I/O signals.

Complete lists of I/O muxings are provided in Table 2-3.

The GPSn setting can be altered during normal operation, but a delay must be inserted between the time

when one function is disabled and another function is enabled.

56F8037/56F8027 Data Sheet, Rev. 8

112

FreescaleSemiconductor

Register Descriptions

Note:

After reset, all I/O pins are GPIO, except the JTAG pins and the RESET pin.

Base + $13

15

14

13

12

GPS_A6

0

11

10

9

8

7

6

5

4

3

2

1

0

Read

Write

GPS_A5

GPS_A4

RESET

0

Figure 6-19 GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0)

6.3.16.1 Reserved—Bits 15–13

This bit field is reserved. Each bit must be set to 0.

6.3.16.2 Configure GPIOA6 (GPS_A6)—Bit 12

This field selects the alternate function for GPIOA6.

•

0 = FAULT0 - PWM FAULT0 Input (default)

1 = TA0 - Timer A0

6.3.16.3 Configure GPIOA5 (GPS_A5)—Bits 11–10

This field selects the alternate function for GPIOA5.

•

00 = PWM5 - PWM5 (default)

01 = FAULT2 - PWM FAULT2 Input

10 = TA3 - Timer A3

11 = Reserved

6.3.16.4 Configure GPIOA4 (GPS_A4)—Bits 9–8

This field selects the alternate function for GPIOA4.

•

00 = PWM4 - PWM4 (default)

01 = FAULT1 - PWM FAULT1 Input

10 = TA2 - Timer A2

11 = Reserved

6.3.16.5 Reserved—Bits 7–0

This bit field is reserved. Each bit must be set to 0.

6.3.17 SIM GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1)

See Section 6.3.16 for general information about GPIO Peripheral Select Registers.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

113

Base + $14

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

GPS_

A11

GPS_

A10

GPS_A14

GPS_A13

GPS_A12

GPS_A9

GPS_A8

Write

RESET

0

Figure 6-20 GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1)

6.3.17.1 Reserved—Bits 15–14

This bit field is reserved. Each bit must be set to 0.

6.3.17.2 Configure GPIOA14 (GPS_A14)—Bits 13–12

This field selects the alternate function for GPIOA14.

•

00 = TB3 - Timer B3 (default)

01 = MOSI1 - QSPI1 Master Out/Slave In

10 = TA3 - Timer A3

11 = Reserved

6.3.17.3 Configure GPIOA13 (GPS_A13)—Bits 11–10

This field selects the alternate function for GPIOA13.

•

00 = TB2 - Timer B2 (default)

01 = MISO1 - QSPI1 Master In/Slave Out

10 = TA2 - Timer A2

11 = Reserved

6.3.17.4 Configure GPIOA12 (GPS_A12)—Bits 9–8

This field selects the alternate function for GPIOA12.

•

00 = TB1- Timer B1 (default)

01 = SCLK1 - QSPI1 Serial Clock

10 = TA1 - Timer A1

11 = Reserved

6.3.17.5 Reserved—Bit 7

This bit field is reserved. It must be set to 0.

6.3.17.6 Configure GPIOA11 (GPS_A11)—Bit 6

This field selects the alternate function for GPIOA11.

•

0 = CMPBI2 - Comparator B Input 2 (default)

1 = TB3 - Timer B3

56F8037/56F8027 Data Sheet, Rev. 8

114

FreescaleSemiconductor

Register Descriptions

6.3.17.7 Reserved—Bit 5

This bit field is reserved. It must be set to 0.

6.3.17.8 Configure GPIOA10 (GPS_A10)—Bit 4

This field selects the alternate function for GPIOA10.

•

0 = CMPAI2- Comparator A Input 2 (default)

1 = TB2 - Timer B2

6.3.17.9 Configure GPIOA9 (GPS_A9)—Bits 3–2

This field selects the alternate function for GPIOA9.

•

00 = FAULT2 - PWM FAULT2 Input (default)

01 = TA3 - Timer A3

10 = CMPBI1 - Comparator B Input 1

11 = Reserved

6.3.17.10 Configure GPIOA8 (GPS_A8)—Bits 1–0

This field selects the alternate function for GPIOA8.

•

00 = FAULT1 - PWM FAULT1 Input (default)

01 = TA2 - Timer A2

10 = CMPAI1 - Comparator A Input 1

11 = Reserved

6.3.18 SIM GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0)

See Section 6.3.16 for general information about GPIO Peripheral Select Registers.

Base + $15

Read

15

14

13

12

11

10

9

GPS_B4

0

8

7

6

5

4

3

2

1

0

GPS_

B1

GPS_

B0

GPS_B6

GPS_B5

GPS_B3

GPS_B2

Write

0

RESET

Figure 6-21 GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0)

6.3.18.1 Reserved—Bit 15

This bit field is reserved. It must be set to 0.

6.3.18.2 Configure GPIOB6 (GPS_B6)—Bits 14–13

This field selects the alternate function for GPIOB6.

•

00 = RXD0 - QSCI0 Receive Data (default)

01 = SDA - I2C Serial Data

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

115

•

10 = CLKIN - External Clock Input

11 = Reserved

6.3.18.3 Configure GPIOB5 (GPS_B5)—Bits 12–11

This field selects the alternate function for GPIOB5.

•

00 = TA1 - Timer A1 (default)

01 = FAULT3 - PWM FAULT3 Input

10 = CLKIN - External Clock Input

11 = Reserved

6.3.18.4 Configure GPIOB4(GPS_B4)—Bits 10–8

This field selects the alternate function for GPIOB4.

•

000 = TA0 - Timer A0 (default)

001 = CLKO - Clock Output

010 = SS1 - QSPI1 Slave Select

011 = TB0 - Timer B0

100 = PSRC2 - PWM4 / PWM5 Pair External Source

11x = Reserved

1x1 = Reserved

6.3.18.5 Configure GPIOB3 (GPS_B3)—Bits 7–6

This field selects the alternate function for GPIOB3.

•

00 = MOSI0 - QSPI0 Master Out/Slave In (default)

01 = TA3 - Timer A3

10 = PSRC1 - PWM2 / PWM3 Pair External Source

11 = Reserved

6.3.18.6 Configure GPIOB2 (GPS_B2)—Bits 5–4

This field selects the alternate function for GPIOB2.

•

00 = MISO0 QSPI0 Master In/Slave Out (default)

01 = TA2 - Timer A2

10 = PSRC0 - PWM0 / PWM1 Pair External Source

11 = Reserved

6.3.18.7 Reserved—Bit 3

This bit field is reserved. It must be set to 0.

6.3.18.8 Configure GPIOB1 (GPS_B1)—Bit 2

This field selects the alternate function for GPIOB1.

56F8037/56F8027 Data Sheet, Rev. 8

116

FreescaleSemiconductor

Register Descriptions

•

0 = SS0 - QSPI0 Slave Select (default)

1 = SDA - I2C Serial Data

6.3.18.9 Reserved—Bit 1

This bit field is reserved. It must be set to 0.

6.3.18.10 Configure GPIOB0 (GPS_B0)—Bits 0

This field selects the alternate function for GPIOB0.

•

0 = SCLK0 - QSPI0 Serial Clock (default)

1 = SCL - I²C Serial Clock

6.3.19 SIM GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1)

See Section 6.3.16 for general information about GPIO Peripheral Select Registers.

Base + $16

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

GPS_

B11

GPS_

B10

GPS_

B9

GPS_

B8

GPS_

B7

Write

RESET

0

Figure 6-22 GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1)

6.3.19.1 Reserved—Bits 15–9

This bit field is reserved. Each bit must be set to 0.

6.3.19.2 Configure GPIOB11 (GPS_B11)—Bit 8

This field selects the alternate function for GPIOB11.

•

0 = CMPBO - Comparator B Output (default)

1 = TB1 - Timer B1

6.3.19.3 Reserved—Bit 7

This bit field is reserved. It must be set to 0.

6.3.19.4 Configure GPIOB10 (GPS_B10)—Bit 6

This field selects the alternate function for GPIOB10.

•

0 = CMPAO - Comparator A Output (default)

1 = TB0 - Timer B0

6.3.19.5 Reserved—Bit 5

This bit field is reserved. It must be set to 0.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

117

6.3.19.6 Configure GPIOB9 (GPS_B9)—Bit 4

This field selects the alternate function for GPIOB9.

•

0 = SDA - I²C Serial Data (default)

1 = MSCANRX - MSCAN Receive Data

6.3.19.7 Reserved—Bit 3

This bit field is reserved. It must be set to 0.

6.3.19.8 Configure GPIOB8 (GPS_B8)—Bit 2

This field selects the alternate function for GPIOB8.

•

0 = SCL - I2C Serial Clock (default)

1 = MSCANTX - MSCAN Transmit Data

6.3.19.9 Reserved—Bit 1

This bit field is reserved. It must be set to 0.

6.3.19.10 Configure GPIOB7 (GPS_B7)—Bit 0

This field selects the alternate function for GPIOB7.

•

0 = TXD0 - QSCI0 Transmit Data (default)

1 = SCL - I2C Serial Clock

6.3.20 SIM GPIO Peripheral Select Register for GPIOC and GPIOD

(SIM_GPSCD)

See Section 6.3.16 for general information about GPIO Peripheral Select Registers.

Base + $17

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

GPS_

D5

GPS_

C12

GPS_

C8

Write

0

RESET

Figure 6-23 GPIO Peripheral Select Register for GPIOC and GPIOD (SIM_GPSCD)

6.3.20.1 Reserved—Bits 15–13

This bit field is reserved. Each bit must be set to 0.

56F8037/56F8027 Data Sheet, Rev. 8

118

FreescaleSemiconductor

Register Descriptions

6.3.20.2 Configure GPIOD5 (GPS_D5)—Bit 12

This field selects the alternate function for GPIOD5.

•

0 = XTAL - External Crystal Oscillator Output (default)

1 = CLKIN - External Clock Input

6.3.20.3 Reserved—Bits 11–5

This bit field is reserved. Each bit must be set to 0.

6.3.20.4 Configure GPIOC12 (GPS_C12)—Bit 4

This field selects the alternate function for GPIOC12.

•

0 = ANB4 - ADCB, Channel 4 (default)

1 = RXD1 - QSCI1 Receive Data

6.3.20.5 Reserved—Bit 3

This bit field is reserved. It must be set to 0.

6.3.20.6 Configure GPIOC8 (GPS_C8)—Bit 2

This field selects the alternate function for GPIOC8.

•

0 = ANA4 - ADCA, Channel 4 (default)

1 = TXD1 - QSCI1 Transmit Data

6.3.20.7 Reserved—Bits 1—0

This bit field is reserved. Each bit must be set to 0.

6.3.21 Internal Peripheral Source Select Register 0 for Pulse Width

Modulator (SIM_IPS0)

The internal integration of peripherals provides input signal source selection for peripherals where an input

signal to a peripheral can be fed from one of several sources. These registers are organized by peripheral

type and provide a selection list for every peripheral input signal that has more than one alternative source

to indicate which source is selected.

If one of the alternative sources is GPIO, the setting in these registers must be made consistently with the

settings in the GPSn and GPIOx_PEREN registers. Specifically, when an IPSn field is configured to select

an I/O pin as the source, then GPSn register settings must configure only one I/O pin to feed this peripheral

input function. Also, the GPIOx_PEREN bit for that I/O pin must be set to 1 to enable peripheral control

of the I/O.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

119

GPIOA5_PEREN

Register

SIM_GPSA0

Register

GPIOA5

SIM_IPS0

Register

0

PWM5

GPIOA5 pin

00

01

10

1

0

1

PWM

FAULT2

Timer A3

Comparator A

Output (Internal)

Figure 6-24 Overall Control of Signal Source using SIM_IPSn Control

IPSn settings should not be altered while an affected peripheral is in an enabled (operational)

configuration. See the 56F802x and 56F803x Peripheral Reference Manual for details.

Base + $18

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

IPS0_

FAULT2

IPS0_

FAULT1

IPS0_PSRC2

0

IPS0_PSRC1

0

IPS0_PSRC0

0

Write

0

RESET

Figure 6-25 Internal Peripheral Source Select Register for PWM (SIM_IPS0)

6.3.21.1 Reserved—Bits 15–14

This bit field is reserved. Each bit must be set to 0.

6.3.21.2 Select Peripheral Input Source for FAULT2 (IPS0_FAULT2)—Bit 13

This field selects the alternate input source signal to feed PWM input FAULT2.

•

0 = I/O Pin (External) - Use PWM FAULT2 Input Pin (default)

1 = CMPBO (Internal) - Use Comparator B Output

6.3.21.3 Reserved—Bit 12

This bit field is reserved. It must be set to 0.

6.3.21.4 Select Peripheral Input Source for FAULT1 (IPS0_FAULT1)—Bit 11

This field selects the alternate input source signal to feed PWM input FAULT1.

•

0 = I/O pin (External) - Use PWM FAULT2 Input Pin (default)

1 = CMPAO (Internal) - Use Comparator A Output

56F8037/56F8027 Data Sheet, Rev. 8

120

FreescaleSemiconductor

Register Descriptions

6.3.21.5 Reserved—Bits 10–9

This bit field is reserved. Each bit must be set to 0.

6.3.21.6 Select Peripheral Input Source for PWM4/PWM5 Pair Source

(IPS0_PSRC2)—Bits 8–6

This field selects the alternate input source signal to feed PWM input PSRC2 as the PWM4/PWM5 pair

source.

•

000 = I/O Pin (External) - Use a PSRC2 input pin as PWM source (default)

001 = TA3 (Internal) - Use Timer A3 output as PWM source

010 = ADC SAMPLE2 (Internal) - Use ADC SAMPLE2 result as PWM source

— If the ADC conversion result in SAMPLE2 is greater than the value programmed into the High Limit

register HLMT2, then PWM4 is set to 0 and PWM5 is set to 1

— If the ADC conversion result in SAMPLE2 is less than the value programmed into the Low Limit

register LLMT2, then PWM4 is set to 1 and PWM5 is set to 0

•

011 = CMPAO (Internal) - Use Comparator A output as PWM source

100 = CMPBO (Internal) - Use Comparator B output as PWM source

11x = Reserved

1x1 = Reserved

6.3.21.7 Select Peripheral Input Source for PWM2/PWM3 Pair Source

(IPS0_PSRC1)—Bits 5–3

This field selects the alternate input source signal to feed PWM input PSRC1 as the PWM2/PWM3 pair

source.

•

000 = I/O pin (External) - Use a PSRC1 input pin as PWM source (default)

001 = TA2 (Internal) - Use Timer A2 output as PWM source

010 = ADC SAMPLE1 (Internal) - Use ADC SAMPLE1 result as PWM source

— If the ADC conversion result in SAMPLE1 is greater than the value programmed into the High Limit

register HLMT1, then PWM2 is set to 0 and PWM3 is set to 1

— If the ADC conversion result in SAMPLE1 is less than the value programmed into the Low Limit

register LLMT1, then PWM2 is set to 1 and PWM3 is set to 0

•

011 = CMPAO (Internal) - Use Comparator A output as PWM source

100 = CMPBO (Internal) - Use Comparator B output as PWM source

11x = Reserved

1x1 = Reserved

6.3.21.8 Select Peripheral Input Source for PWM0/PWM1 Pair Source

(IPS0_PSRC0)—Bits 2–0

This field selects the alternate input source signal to feed PWM input PSRC0 as the PWM0/PWM1 pair

source.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

121

•

000 = I/O pin (External) - Use a PSRC0 input pin as PWM source (default)

001 = TA0 (Internal) - Use Timer A0 output as PWM source

010 = ADC SAMPLE0 (Internal) - Use ADC SAMPLE0 result as PWM source

— If the ADC conversion result in SAMPLE0 is greater than the value programmed into the High Limit

register HLMT0, then PWM0 is set to 0 and PWM1 is set to 1

— If the ADC conversion result in SAMPLE0 is less than the value programmed into the Low Limit

register LLMT0, then PWM0 is set to 1 and PWM1 is set to 0

•

011 = CMPAO (Internal) - Use Comparator A output as PWM source

100 = CMPBO (Internal) - Use Comparator B output as PWM source

11x = Reserved

1x1 = Reserved

6.3.22 Internal Peripheral Source Select Register 1 for Digital-to-Analog

Converters (SIM_IPS1)

See Section 6.3.21 for general information about Internal Peripheral Source Select registers.

Base + $19

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

IPS1_DSYNC1

0

IPS1_DSYNC0

Write

0

RESET

Figure 6-26 Internal Peripheral Source Select Register for DACs (SIM_IPS1)

6.3.22.1 Reserved—Bits 15–7

This bit field is reserved. Each bit must be set to 0.

6.3.22.2 Select Input Peripheral Source for SYNC Input to DAC 1

(IPS1_DSYNC1)—Bits 6–4

This field selects the alternate input source signal to feed DAC1 SYNC input.

•

000 = PIT0 (Internal) - Use Programmable Interval Timer 0 Output as DAC SYNC input (default)

001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input

010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input

011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input

100 = TA0 (Internal) - Use Timer A0 output as DAC SYNC input

101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input

11x = Reserved

6.3.22.3 Reserved—Bit 3

This bit field is reserved. It must be set to 0.

56F8037/56F8027 Data Sheet, Rev. 8

122

FreescaleSemiconductor

Register Descriptions

6.3.22.4 Select Peripheral Input Source for SYNC Input to DAC 0

(IPS1_DSYNC0)—Bits 2–0

This field selects the alternate input source signal to feed DAC0 SYNC input.

•

000 = PIT0 (Internal) - Use Programmable Interval Timer 0 Output as DAC SYNC input (default)

001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input

010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input

011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input

100 = TA0 (Internal) - Use Timer A0 output as DAC SYNC input

101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input

11x = Reserved

6.3.23 Internal Peripheral Source Select Register 2 for Quad Timer A

(SIM_IPS2)

See Section 6.3.21 for general information about Internal Peripheral Source Select registers.

Base + $1A

Read

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

IPS2_

TA3

IPS2_

TA2

IPS2_

TA1

Write

0

RESET

Figure 6-27 Internal Peripheral Source Select Register for TMRA (SIM_IPS2)

6.3.23.1 Reserved—Bits 15–13

This bit field is reserved. Each bit must be set to 0.

6.3.23.2 Select Peripheral Input Source for TA3 (IPS2_TA3)—Bit 12

This field selects the alternate input source signal to feed Quad Timer A, input 3.

•

0 = I/O pin (External) - Use Timer A3 input/output pin

1 = PWM SYNC (Internal) - Use PWM reload synchronization signal

6.3.23.3 Reserved—Bits 11–9

This bit field is reserved. Each bit must be set to 0.

6.3.23.4 Select Peripheral Input Source for TA2 (IPS2_TA2)—Bit 8

This field selects the alternate input source signal to feed Quad Timer A, input 2.

•

0 = I/O pin (External) - Use Timer A2 input/output pin

1 = CMPBO (Internal) - Use Comparator B output

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

123

6.3.23.5 Reserved—Bits 7–5

This bit field is reserved. Each bit must be set to 0.

6.3.23.6 Select Peripheral Input Source for TA1 (IPS2_TA1)—Bit 4

This field selects the alternate input source signal to feed Quad Timer A, input 1.

•

0 = I/O pin (External) - Use Timer A1 input/output pin

1 = CMPAO (Internal) - Use Comparator A output

6.3.23.7 Reserved—Bits 3–0

This bit field is reserved. Each bit must be set to 0.

For Timer A to detect the PWM SYNC signal, the clock rate of both the PWM module and Timer A

module must be identical, at either the system clock rate or 3X system clock rate.

6.4 Clock Generation Overview

The SIM uses the master clock (2X system clock) at a maximum of 64MHz from the OCCS module to

produce a system clock at a maximum of 32MHz for the peripheral, core and memory. It divides the master

clock by two and gates it with appropriate power mode and clock gating controls. A 3X system high-speed

peripheral clock input from OCCS operates at three times the system clock at a maximum of 96MHz and

2

can be an optional clock for PWM, Timer A, Timer B, and I C modules. These clocks are generated by

gating the 3X system high-speed peripheral clock with appropriate power mode and clock gating controls.

The OCCS configuration controls the operating frequency of the SIM’s master clocks. In the OCCS, either

an external clock (CLKIN), a crystal oscillator, or the relaxation oscillator can be selected as the master

clock source (MSTR_OSC). An external clock can be operated at any frequency up to 64MHz. The crystal

oscillator can be operated only at a maximum of 8MHz. The relaxation oscillator can be operated at full

speed (8MHz), standby speed (200kHz using ROSB), or powered down (using ROPD). An 8MHz

MSTR_OSC can be multiplied to 196MHz using the PLL and postscaled to provide a variety of high-speed

clock rates. Either the postscaled PLL output or MSTR_OSC signal can be selected to produce the master

clocks to the SIM. When the PLL is selected, both the 3X system clock and the 2X system clock are

enabled. If the PLL is not selected, the 3X system clock is disabled and the master clock is MSTR_OSC.

In combination with the OCCS module, the SIM provides power modes (see Section 6.5), clock enables,

and clock rate controls to provide flexible control of clocking and power utilization. The clock rate

controls enable the high-speed clocking option for the two quad timers (TMRA and TMRB) and PWM,

but requires the PLL to be on and selected. Refer to the 56F802x and 56F803x Peripheral Reference

Manual for further details. The peripheral clock enable controls can be used to disable an individual

peripheral clock when it is not used.

6.5 Power-Saving Modes

The 56F8037/56F8027 operates in one of five Power-Saving modes, as shown in Table 6-2.

56F8037/56F8027 Data Sheet, Rev. 8

124

FreescaleSemiconductor

Power-Saving Modes

Table 6-2 Clock Operation in Power-Saving Modes

Mode

Core Clocks

Peripheral Clocks

Description

Device is fully functional

Run

Wait

Core and memory

clocks enabled

Peripheral clocks

enabled

Core and memory

clocks disabled

Peripheral clocks

enabled

Core executes WAIT instruction to enter this

mode.

Typically used for power-conscious applications.

Possible recoveries from Wait mode to Run

mode are:

1. Any interrupt

2. Executing a Debug mode entry command

during the 56800E core JTAG interface

3. Any reset (POR, external, software, COP)

Stop

Master clock generation in the OCCS

remains operational, but the SIM disables

the generation of system and peripheral

clocks.

Core executes STOP instruction to enter this

mode.

Possible recoveries from Stop mode to Run

mode are:

1. Interrupt from any peripheral configured in the

CTRL register to operate in Stop mode (TA0-3,

QSCI0, PIT0-1, CAN, CMPA-B)

2. Low-voltage interrupt

3. Executing a Debug mode entry command

using the 56800E core JTAG interface

4. Any reset (POR, external, software, COP)

Standby

The OCCS generates the master clock at a The user configures the OCCS and SIM to select

reduced frequency (400kHz). The PLL is

disabled and the high-speed peripheral

option is not available. System and

peripheral clocks operate at 200kHz.

the relaxation oscillator clock source (PRECS),

shut down the PLL (PLLPD), put the relaxation

oscillator in Standby mode (ROSB), and put the

large regulator in Standby (LRSTDBY). The

device is fully operational, but operating at a

minimum frequency and power configuration.

Recovery requires reversing the sequence used

to enter this mode (allowing for PLL lock time).

Power-Down

Master clock generation in the OCCS is

completely shut down. All system and

peripheral clocks are disabled.

The user configures the OCCS and SIM to enter

Standby mode as shown in the previous

description, followed by powering down the

oscillator (ROPD). The only possible recoveries

from this mode are:

1. External Reset

2. Power-On Reset

The power-saving modes provide additional power management options by disabling the clock,

reconfiguring the voltage regulator clock generation to manage power utilization, as shown in Table 6-2.

Run, Wait, and Stop modes provide methods of enabling/disabling the peripheral and/or core clocking as

a group. Stop disable controls for an individual peripheral are provided in the SDn registers to override the

default behavior of Stop mode. By asserting a peripheral’s Stop disable bit, the peripheral clock continues

to operate in Stop mode. This is useful to generate interrupts which will recover the device from Stop mode

to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

125

possible to invoke Stop or Wait mode while in Standby mode for even greater levels of power reduction.

A 400kHz external clock can optionally be used in Standby mode to produce the required Standby 200kHz

system clock rate. Power-down mode, which selects the ROSC clock source but shuts it off, fully disables

the device and minimizes its power utilization but is only recoverable via reset.

When the PLL is not selected and the system bus is operating at 200kHz or less, the large regulator can be

put into its Standby mode (LRSTDBY) to reduce the power utilization of that regulator.

All peripherals, except the COP/watchdog timer, run at the system clock frequency or optional 3X system

2

clock for PWM, Timers, and I C. The COP timer runs at OSC_CLK / 1024. The maximum frequency of

operation is 32MHz.

6.6 Resets

The SIM supports five sources of reset, as shown in Figure 6-28. The two asynchronous sources are the

external reset pin and the Power-On Reset (POR). The three synchronous sources are the software reset

(SW reset), which is generated within the SIM itself by writing the SIM_CTRL register in Section 6.3.1,

the COP time-out reset (COP_TOR), and the COP loss-of-reference reset (COP_LOR). The reset

generation module has three reset detectors, which resolve into four primary resets. These are outlined in

Table 6-3. The JTAG circuitry is reset by the Power-On Reset.

Table 6-3 Primary System Resets

Reset Sources

Reset Signal

POR

External

Software

COP

Comments

EXTENDED_POR

X

Stretched version of POR released 64

OSC_CLK cycles after POR deasserts

CLKGEN_RST

X

Released 32 OSC_CLK cycles after all reset

sources, including EXTENDED_POR, have

released

PERIP_RST

CORE_RST

X

Releases 32 SYS_CLK cycles after the

CLKGEN_RST is released

Releases 32 SYS_CLK cycles after

PERIP_RST is released

Figure 6-28 provides a graphic illustration of the details in Table 6-3. Note that the POR_Delay blocks

use the OSC_CLK as their time base, since other system clocks are inactive during this phase of reset.

56F8037/56F8027 Data Sheet, Rev. 8

126

FreescaleSemiconductor

Clocks

EXTENDED_POR

JTAG

POR

pulse shaper

Power-On

Reset

(active low)

Memory

Subsystem

Delay 64

OSC_CLK

Clock

CLKGEN_RST

OCCS

COMBINED_RST

External

RESET IN

(active low)

PERIP_RST

Delay 32

OSC_CLK

Clock

RESET

Peripherals

pulse shaper

Delay 32

COP_TOR

(active low)

sys clocks

SW Reset

56800E

pulse shaper

Delay 32

sys clocks

COP_LOR

(active low)

pulse shaper

Delay blocks assert immediately and

deassert only after the programmed

number of clock cycles.

CORE_RST

Figure 6-28 Sources of RESET Functional Diagram (Test modes not included)

POR resets are extended 64 OSC_CLK clocks to stabilize the power supply and clock source. All resets

are subsequently extended for an additional 32 OSC_CLK clocks and 64 system clocks as the various

internal reset controls are released. Given the normal relaxation oscillator rate of 8MHz, the duration of a

POR reset from when power comes on to when code is running is 28µS. An external reset generation

circuit may also be used. A description of how these resets are used to initialize the clocking system and

system modules is included in Section 6.7.

6.7 Clocks

The memory, peripheral and core clocks all operate at the same frequency (32MHz maximum) with the

exception of the peripheral clocks for quad timers TMRA and TMRB and the PWM, which have the option

to operate at 3X system clock. The SIM is responsible for clock distributions.

While the SIM generates the ADC peripheral clock in the same way it generates all other peripheral clocks,

the ADC standby and conversion clocks are generated by a direct interface between the ADC and the

OCCS module.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

127

The deassertion sequence of internal resets coordinates the device start up, including the clocking system

start up. The sequence is described in the following steps:

1. As power is applied, the Relaxation Oscillator starts to operate. When a valid operating voltage is

reached, the POR reset will release.

2. The release of POR reset permits operation of the POR reset extender. The POR extender generates

an extended POR reset, which is released 64 OSC_CLK cycles after POR reset. This provides an

additional time period for the clock source and power to stabilize.

3. A Combined reset consists of the OR of the extended POR reset, the external reset, the COP reset

and Software reset. The entire device, except for the POR extender, is held reset as long as

Combined reset is asserted. The release of Combined reset permits operation of the CTRL register,

the Synchronous reset generator, and the CLKGEN reset extender.

4. The Synchronous reset generator generates a reset to the Software and COP reset logic. The COP

and Software reset logic is released three OSC_CLK cycles after Combined reset deasserts. This

provides a reasonable minimum duration to the reset for these specialized functions.

5. The CLKGEN reset extender generates the CLKGEN reset used by the clock generation logic. The

CLKGEN reset is released 32 OSC_CLK cycles after Combined reset deasserts. This provides a

window in which the SIM stabilizes the master clock inputs to the clock generator.

6. The release of CLKGEN reset permits operation of the clock generation logic and the Peripheral

reset extender. The Peripheral reset extender generates the Peripheral reset, which is released 32

SYS_CLK cycles after CLKGEN reset. This provides a window in which peripheral and core logic

remain clocked, but in reset, so that synchronous resets can be resolved.

7. The release of Peripheral reset permits operation of the peripheral logic and the Core reset extender.

The Core reset extender generates the Core reset, which is released 32 SYS_CLK cycles after the

Peripheral reset. This provides a window in which critical peripheral start-up functions, such as

Flash Security in the Flash memory, can be implemented.

8. The release of Core reset permits execution of code by the 56800E core and marks the end of the

system start-up sequence.

Figure 6-29 illustrates clock relationships to one another and to the various resets as the device comes out

of reset. RST is assumed to be the logical AND of all active-low system resets (for example, POR, external

reset, COP and Software reset). In the 56F8037/56F8027, this signal will be stretched by the SIM for a

period of time (up to 96 OSC_CLK clock cycles, depending upon the status of the POR) to create the clock

generation reset signal (CLKGEN_RST). The SIM should deassert CLKGEN_RST synchronously with

the negative edge of OSC_CLK in order to avoid skew problems. CLKGEN_RST is delayed 32 SYS_CLK

cycles to create the peripheral reset signal (PERIP_RST). PERIP_RST is then delayed by 32 SYS_CLK

cycles to create CORE_RST. Both PERIP_RST and CORE_RST should be released on the negative edge

of SYS_CLK_D as shown. This phased releasing of system resets is necessary to give some peripherals

(for example, the Flash interface unit) set-up time prior to the 56800E core becoming active.

56F8037/56F8027 Data Sheet, Rev. 8

128

FreescaleSemiconductor

Interrupts

Maximum Delay = 64 OSC_CLK cycles for POR reset extension and 32 OSC_CLK cycles

for Combined reset extension

RST

MSTR_OSC

Switch on falling OSC_CLK

96 MSTR_OSC cycles

CKGEN_RST

2X SYS_CLK

SYS_CLK

SYS_CLK_D

SYS_CLK_DIV2

PERIP_RST

32 SYS_CLK cycles delay

Switch on falling SYS_CLK

32 SYS_CLK cycles delay

CORE_RST

Figure 6-29 Timing Relationships of Reset Signal to Clocks

6.8 Interrupts

The SIM generates no interrupts.

Part 7 Security Features

The 56F8037/56F8027 offers security features intended to prevent unauthorized users from reading the

contents of the flash memory (FM) array. The 56F8037/56F8027’s flash security consists of several

hardware interlocks that prevent unauthorized users from gaining access to the flash array.

After flash security is set, an authorized user is still able to access on-chip memory if a user-defined

software subroutine, which reads and transfers the contents of internal memory via serial communication

peripherals, is included in the application software.

7.1 Operation with Security Enabled

After the user has programmed flash with the application code, the 56F8037/56F8027 can be secured by

programming the security word $0002 into program memory location $00 7FF7. This non-volatile word

will keep the device secured through reset and through power-down of the device. Refer to the flash

memory chapter in the 56F802x and 56F803x Peripheral Reference Manual for the details. When flash

security mode is enabled, the 56F8037/56F8027 will disable the core EOnCE debug capabilities. Normal

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

129

program execution is otherwise unaffected.

7.2 Flash Access Lock and Unlock Mechanisms

There are several methods that effectively lock or unlock the on-chip flash.

7.2.1

Disabling EOnCE Access

On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for

the 56800E CPU. The TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE

port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port) is active

and provides the chip’s boundary scan capability and access to the ID register, but proper implementation

of flash security will block any attempt to access the internal flash memory via the EOnCE port when

security is enabled.

7.2.2

Flash Lockout Recovery Using JTAG

If the device is secured, one lockout recovery mechanism is the complete erasure of the internal flash

contents, including the configuration field, thus disabling security (the protection register is cleared). This

does not compromise security, as the entire contents of the user’s secured code stored in flash are erased

before security is disabled on the device on the next reset or power-up sequence.

To start the lockout recovery sequence via JTAG, the JTAG public instruction

(LOCKOUT_RECOVERY) must first be shifted into the chip-level TAP controller’s instruction register.

Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock

divider value must be shifted into the corresponding 7-bit data register. After the data register has been

updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout

sequence to commence. The controller must remain in this state until the erase sequence is complete. Refer

to the 56F802x and 56F803x Peripheral Reference Manual for more details, or contact Freescale.

Note:

Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller

and device to return to normal unsecured operation. Power-on reset will reset both too.

7.2.3

Flash Lockout Recovery using CodeWarrior

CodeWarrior can unlock a device by selecting the Debug menu, then selecting DSP56800E, followed by

Unlock Flash. Another mechanism is also built into CodeWarrior using the device’s memory

configuration file. The command “Unlock_Flash_on_Connect 1” in the .cfg file accomplishes the same

task as using the Debug menu.

This lockout recovery mechanism is the complete erasure of the internal flash contents, including the

configuration field, thus disabling security (the protection register is cleared).

7.2.4

Flash Lockout Recovery without mass erase

A user can un-secure a secured device by programming the word $0000 into program memory location

$00 7FF7. After completing the programming, both the JTAG TAP controller and the device must be reset

in order to return to normal unsecured operation. Power-on reset will also reset both.

56F8037/56F8027 Data Sheet, Rev. 8

130

FreescaleSemiconductor

Product Analysis

The user is responsible for directing the device to invoke the flash programming subroutine to reprogram

the word $0000 into program memory location $00 7FF7. This is done by, for example, toggling a specific

pin or downloading a user-defined key through serial interfaces.

Note:

Flash contents can only be programmed for 1s to 0s.

7.3 Product Analysis

The recommended method of unsecuring a secured device for product analysis of field failures is via the

method described in section 7.2.4. The customer would need to supply Technical Support with the details

of the protocol to access the subroutines in flash memory. An alternative method for performing analysis

on a secured device would be to mass-erase and reprogram the flash with the original code, but modify the

security word or not program the security word.

Part 8 General Purpose Input/Output (GPIO)

8.1 Introduction

This section is intended to supplement the GPIO information found in the 56F802x and 56F803x

Peripheral Reference Manual and contains only chip-specific information. This information supersedes

the generic information in the 56F802x and 56F803x Peripheral Reference Manual.

8.2 Configuration

There are four GPIO ports defined on the 56F8037/56F8027. The width of each port, the associated

peripheral and reset functions are shown in Table 8-1. The specific mapping of GPIO port pins is shown

in Table 8-2. Additional details are shown in Tables 2-2 and 2-3.

Table 8-1 GPIO Ports Configuration

Available

Pins in

56F8037/56F

8027

GPIO Port

Peripheral Function

Reset Function

PWM, Timer, QSPI, Comparator, Reset

GPIO, RESET

A

B

15

14

QSPI, I²C, PWM, Clock, MSCAN,

Comparator, Timer

GPIO

ADC, Comparator, QSCI

GPIO

C

D

16

8

Clock, Oscillator, DAC, JTAG

GPIO, JTAG

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

131

Table 8-2 GPIO External Signals Map

LQFP

Peripheral Function

Package Pin

Notes

GPIO Function

GPIOA0

GPIOA1

GPIOA2

GPIOA3

GPIOA4

PWM0

56

55

47

48

43

Defaults to A0

Defaults to A1

Defaults to A2

Defaults to A3

PWM1

PWM2

PWM3

PWM4 / TA2 / FAULT1

SIM register SIM_GPS is used to

select between PWM4, TA2, and

FAULT1.

Defaults to A4

GPIOA5

GPIOA6

PWM5 / TA3 / FAULT2

FAULT0 / TA0

39

34

SIM register SIM_GPS is used to

select between PWM5, TA3, and

FAULT2.

Defaults to A5

SIM register SIM_GPS is used to

select between FAULT0 and TA0.

Defaults to A6

GPIOA7

GPIOA8

RESET

31

36

Defaults to RESET

FAULT1 / TA2 / CMPAI1

SIM register SIM_GPS is used to

select between FAULT1, TA2, and

CMPAI1.

Defaults to A8

GPIOA9

FAULT2 / TA3 / CMPBI1

5

SIM register SIM_GPS is used to

select between FAULT2, TA3, and

CMPBI1.

Defaults to A9

GPIOA10

GPIOA11

GPIOA12

GPIOA13

GPIOA14

TB2 / CMPAI2

35

6

SIM register SIM_GPS is used to

select between TB2 and CMPAI2.

Defaults to A10

TB3 / CMPBI2

SIM register SIM_GPS is used to

select between TB3 and CMPBI2.

Defaults to A11

SCLK1 / TB1 / TA1

MISO1 / TB2 / TA2

MOSI1 / TB3 / TA3

37

44

45

SIM register SIM_GPS is used to

select between SCLK1, TB1, and TA1.

Defaults to A12

SIM register SIM_GPS is used to

select between MISO1, TB2, and TA2.

Defaults to A13

SIM register SIM_GPS is used to

select between MOSI1, TB3, and TA3.

Defaults to A14

56F8037/56F8027 Data Sheet, Rev. 8

132

FreescaleSemiconductor

Configuration

Table 8-2 GPIO External Signals Map (Continued)

LQFP

Package Pin

Notes

GPIO Function

Peripheral Function

GPIOB0

SCLK0 / SCL

42

SIM register SIM_GPS is used to

select between SCLK and SCL.

Defaults to B0

GPIOB1

GPIOB2

SS0 / SDA

2

SIM register SIM_GPS is used to

select between SS0 and SDA.

Defaults to B1

MISO0 / TA2 / PSRC0

33

SIM register SIM_GPS is used to

select between MISO0, TA2, and

PSRC0.

Defaults to B2

GPIOB3

GPIOB4

GPIOB5

MOSI0 / TA3 / PSRC1

32

38

4

SIM register SIM_GPS is used to

select between MOSI0, TA3 and

PSRC1.

Defaults to B3

TA0 / CLKO / SS1 / TB0 /

PSRC2

SIM register SIM_GPS is used to

select between TA0, CLKO, SS1, TB0,

and PSRC2.

Defaults to B4

TA1 / FAULT3 / CLKIN

SIM register SIM_GPS is used to

select between TA1, FAULT3, and

CLKIN.

CLKIN functionality is enabled using

the PLL Control Register within the

OCCS block.

Defaults to B5

GPIOB6

RXD0 / SDA / CLKIN

1

SIM register SIM_GPS is used to

select between RXD0, SDA, and

CLKIN.

CLKIN functionality is enabled using

the PLL Control Register within the

OCCS block.

Defaults to B6

GPIOB7

GPIOB8

GPIOB9

GPIOB10

TXD0 / SCL

3

SIM register SIM_GPS is used to

select between TXD0 and SCL.

Defaults to B7

SCL / CANTX

SDA / CANRX

TB0 / CMPAO

54

46

30

SIM register SIM_GPS is used to

select between SCL and CANTX.

Defaults to B8

SIM register SIM_GPS is used to

select between SDA and CANRX.

Defaults to B9

SIM register SIM_GPS is used to

select between TB0 and CMPAO.

Defaults to B10

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

133

Table 8-2 GPIO External Signals Map (Continued)

LQFP

Package Pin

Notes

GPIO Function

Peripheral Function

GPIOB11

TB1 / CMPBO

60

SIM register SIM_GPS is used to

select between TB1 and CMPBO.

Defaults to B11

GPIOB12

GPIOB13

GPIOC0

CANTX

57

58

24

Defaults to B12

Defaults to B13

CANRX

ANA0 / CMPAI3

SIM register SIM_GPS is used to

select between ANA0 and CMPAI3.

Defaults to C0

GPIOC1

GPIOC2

ANA1

22

20

Defaults to C1

ANA2 / V_REFHA

SIM register SIM_GPS is used to

select between ANA2 and V_REFHA

.

Defaults to C2

GPIOC3

GPIOC4

ANA3 / V_REFLA

ANB0 / CMPBI3

19

10

SIM register SIM_GPS is used to

select between ANA3 and V_REFLA

.

Defaults to C3

SIM register SIM_GPS is used to

select between ANB0 and CMPBI3.

Defaults to C4

GPIOC5

GPIOC6

ANB1

11

13

Defaults to C5

ANB2 / V_REFHB

SIM register SIM_GPS is used to

select between ANB2 and V_REFHB

.

Defaults to C6

GPIOC7

GPIOC8

ANB3 / V_REFLB

ANA4 / TXD1

14

26

SIM register SIM_GPS is used to

select between ANB3 and V_REFLB

.

Defaults to C7

SIM register SIM_GPS is used to

select between ANA4 and TXD1.

Defaults to C8

GPIOC9

ANA5

21

23

25

9

Defaults to C9

Defaults to C10

Defaults to C11

GPIOC10

GPIOC11

GPIOC12

ANA6

ANA7

ANB4 / RXD1

SIM register SIM_GPS is used to

select between ANB4 and RXD1.

Defaults to C12

GPIOC13

GPIOC14

GPIOC15

GPIOD0

GPIOD1

ANB5

ANB6

ANB7

TDI

12

62

61

59

64

Defaults to C13

Defaults to C14

Defaults to C15

Defaults to TDI

Defaults to TDO

TDO

56F8037/56F8027 Data Sheet, Rev. 8

134

FreescaleSemiconductor

Reset Values

Table 8-2 GPIO External Signals Map (Continued)

LQFP

Package Pin

Notes

GPIO Function

Peripheral Function

TCK

GPIOD2

GPIOD3

GPIOD4

GPIOD5

29

63

53

52

Defaults to TCK

Defaults to TMS

Defaults to D4

TMS

EXTAL

XTAL / CLKIN

SIM register SIM_GPSCD is used to

select between XTAL and CLKIN.

Defaults to D5

GPIOD6

GPIOD7

DAC0

DAC1

18

15

Defaults to D6

Defaults to D7

8.3 Reset Values

Tables 8-1 and 8-2 detail registers for the 56F8037/56F8027; Figures 8-1 through 8-4 summarize register

maps and reset values.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

135

Add.

Offset

Register Acronym

GPIOA_PUPEN

15

0

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

W

PU[15:0]

1

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

RS

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

R

W

.0

D[15:0]

0

GPIOA_DATA

GPIOA_DDIR

RS

0

1

X

0

R

W

.0.

DD[15:0]

0

RS

0

R

W

PE[15:0]

0

GPIOA_PEREN

GPIOA_IASSRT

GPIOA_IEN

RS

0

R

W

IA[15:0]

0

RS

0

R

W

IEN[15:0]

0

RS

R

W

0

IEPOL[15:0]

GPIOA_IEPOL

GPIOA_IPEND

GPIOA_IEDGE

GPIOA_PPOUTM

GPIOA_RDATA

GPIOA_DRIVE

RS

0

R

W

IPR[15:0]

RS

0

1

0

1

R

W

IES[15:0]

0

RS

0

R

W

OEN[15:0]

1

RS

0

R

W

RAW DATA[15:0]

RS

0

X

R

W

DRIVE[15:0]

RS

0

R

W

Read as 0

Reserved

Reset

RS

Figure 8-1 GPIOA Register Map Summary

56F8037/56F8027 Data Sheet, Rev. 8

136

FreescaleSemiconductor

Reset Values

Add.

Offset

Register Acronym

GPIOB_PUPEN

15

0

14

0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

W

PU[15:0]

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

RS

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

R

W

D[15:0]

GPIOB_DATA

GPIOB_DDIR

RS

0

R

W

DD[15:0]

RS

0

R

W

PE[15:0]

GPIOB_PEREN

GPIOB_IASSRT

GPIOB_IEN

RS

0

R

W

IA[15:0]

RS

0

R

W

IEN[15:0]

RS

0

R

W

IEPOL[15:0]

GPIOB_IEPOL

GPIOB_IPEND

GPIOB_IEDGE

GPIOB_PPOUTM

GPIOB_RDATA

GPIOB_DRIVE

RS

0

R

W

IPR[15:0]

RS

0

R

W

IES[15:0]

RS

0

R

W

OEN[15:0]

RS

0

1

R

W

RAW DATA[15:0]

RS

0

X

0

X

0

R

W

DRIVE[15:0]

RS

0

R

W

Read as 0

Reserved

Reset

RS

Figure 8-2 GPIOB Register Map Summary

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

137

Add.

Offset

Register Acronym

GPIOC_PUPEN

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

W

PU[15:0]

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

RS

1

0

1

X

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

R

W

D[15:0]

GPIOC_DATA

GPIOC_DDIR

RS

0

1

X

0

R

W

DD[15:0]

RS

0

R

W

PE[15:0]

GPIOC_PEREN

GPIOC_IASSRT

GPIOC_IEN

RS

0

R

W

IA[15:0]

RS

0

R

W

IEN[15:0]

RS

0

R

W

IEPOL[15:0]

GPIOC_IEPOL

GPIOC_IPEND

GPIOC_IEDGE

GPIOC_PPOUTM

GPIOC_RDATA

GPIOC_DRIVE

RS

0

R

W

IPR[15:0]

RS

0

R

W

IES[15:0]

RS

0

R

W

OEN[15:0]

RS

1

R

W

RAW DATA[15:0]

RS

X

R

W

DRIVE[15:0]

RS

0

R

W

Read as 0

Reserved

Reset

RS

Figure 8-3 GPIOC Register Map Summary

56F8037/56F8027 Data Sheet, Rev. 8

138

FreescaleSemiconductor

Reset Values

Add.

Offset

Register Acronym

GPIOD_PUPEN

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

W

PU[15:0]

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

RS

0

1

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

0

1

0

1

X

0

R

W

D[15:0]

GPIOD_DATA

GPIOD_DDIR

RS

0

R

W

DD[15:0]

RS

0

R

W

PE[15:0]

GPIOD_PEREN

GPIOD_IASSRT

GPIOD_IEN

RS

0

1

R

W

IA[15:0]

RS

0

R

W

IEN[15:0]

RS

0

R

W

IEPOL[15:0]

GPIOD_IEPOL

GPIOD_IPEND

GPIOD_IEDGE

GPIOD_PPOUTM

GPIOD_RDATA

GPIOD_DRIVE

RS

0

R

W

IPR[15:0]

RS

0

R

W

IES[15:0]

RS

0

R

W

OEN[15:0]

RS

1

R

W

RAW DATA[15:0]

RS

X

0

X

0

R

W

DRIVE[15:0]

RS

0

R

W

Read as 0

Reserved

Reset

RS

Figure 8-4 GPIOD Register Map Summary

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

139

Part 9 Joint Test Action Group (JTAG)

9.1 56F8037/56F8027 Information

Please contact your Freescale sales representative or authorized distributor for device/package-specific

BSDL information.

The TRST pin is not available in this package. The pin is tied to V in the package.

DD

The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high

for five rising edges of TCK, as described in the 56F802x and 56F803x Peripheral Reference Manual.

Part 10 Specifications

10.1 General Characteristics

The 56F8037/56F8027 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital

inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process

technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture

of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and

5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V

 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the

power savings of 3.3V I/O levels, combined with the ability to receive 5V levels without damage.

Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum

is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to

the device.

Unless otherwise stated, all specifications within this chapter apply over the temperature range of -40ºC to

125ºC ambient temperature over the following supply ranges:

V

= V

= 0V, V = V

= 3.0–3.6V, CL < 50pF, f = 32MHz

SS

SSA

DD

DDA

OP

CAUTION

This device contains protective circuitry to guard

against damage due to high static voltage or electrical

fields. However, normal precautions are advised to

avoid application of any voltages higher than

maximum-rated voltages to this high-impedance circuit.

Reliability of operation is enhanced if unused inputs are

tied to an appropriate logic voltage level (either V_DDor

V_SS).

56F8037/56F8027 Data Sheet, Rev. 8

140

FreescaleSemiconductor

General Characteristics

Table 10-1 Absolute Maximum Ratings

(V_SS= 0V, V_SSA= 0V)

Characteristic

Supply Voltage Range

Symbol

V_DD

Notes

Min

-0.3

- 0.3

- 0.4

- 0.3

—

Max

4.0

Unit

V

Analog Supply Voltage Range

ADC High Voltage Reference

Voltage difference V_DDto V_DDA

Voltage difference V_SSto V_SSA

Digital Input Voltage Range

Oscillator Voltage Range

V_DDA

V_REFHx

V_DD

V_SS

V_IN

4.0

V

4.0

V

0.3

V

0.3

V

Pin Groups 1, 2

Pin Group 4

6.0

V

V_OSC

V_INA

4.0

V

Analog Input Voltage Range

Pin Group 3

4.0

V

Input clamp current, per pin (V_IN< 0)¹

Output clamp current, per pin (V_O< 0)¹

V_IC

-20.0

mA

V_OC

—

-20.0

4.0

mA

V

Output Voltage Range

(Normal Push-Pull mode)

Pin Group 1

Pin Group 2

Pin Group 5

V_OUT

- 0.3

Output Voltage Range

(Open Drain mode)

V_OUTOD

- 0.3

6.0

4.0

V

Output Voltage Range (DAC)

V_OUTDAC

Ambient Temperature

Industrial

T_A

- 40

- 55

105

150

°C

Storage Temperature Range

(Extended Industrial)

T_STG

1. Continuous clamp current per pin is -2.0 mA

Default Mode

Pin Group 1: GPIO, TDI, TDO, TMS, TCK

Pin Group 2: RESET, GPIOA7

Pin Group 3: ADC and Comparator Analog Inputs

Pin Group 4: XTAL, EXTAL

Pin Group 5: DAC Analog Outputs

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

141

10.1.1 ElectroStatic Discharge (ESD) Model

Table 10-2 56F8037/56F8027 ESD Protection

Characteristic

Min

Typ

Max

Unit

ESD for Human Body Model (HBM)

ESD for Machine Model (MM)

2000

200

—

V

ESD for Charge Device Model (CDM)

750

6

Table 10-3 LQFP Package Thermal Characteristics

Value

(LQFP)

Characteristic

Symbol

Unit

Notes

Comments

Junction to ambient

Natural convection

Single layer board

(1s)

R_JA

41

34

°C/W

2

Junction to ambient

Natural convection

Four layer board

(2s2p)

R_JMA

1, 2

Junction to ambient

(@200 ft/min)

Single layer board

(1s)

R_JMA

34

29

°C/W

2

Junction to ambient

(@200 ft/min)

Four layer board

(2s2p)

R_JMA

1, 2

Junction to board

R_JB

R_JC

_JT

24

8

°C/W

4

3

5

Junction to case

Junction to package top

Natural Convection

2

1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p

thermal test board.

2. Junction to ambient thermal resistance, Theta-JA (R ), was simulated to be equivalent to the JEDEC specification JESD51-2

JA

in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes

(2s2p, where “s” is the number of signal layers and “p” is the number of planes) per JESD51-6 and JESD51-7. The correct name

for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA.

3. Junction to case thermal resistance, Theta-JC (R ), was simulated to be equivalent to the measured values using the cold plate

JC

technique with the cold plate temperature used as the “case” temperature. The basic cold plate measurement technique is de-

scribed by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the

package is being used with a heat sink.

4. Junction to board thermal resistance, Theta-JB (R ), is a metric of the thermal resistance from the junction to the printed circuit

JB

board determined per JESD51-8. Board temperature is measured on the top surface of the board near the package.

5. Thermal Characterization Parameter, Psi-JT (Y ), is the “resistance” from junction to reference point thermocouple on top center

JT

of case as defined in JESD51-2. Y is a useful value to use to estimate junction temperature in steady state customer

JT

environments.

6. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

56F8037/56F8027 Data Sheet, Rev. 8

142

FreescaleSemiconductor

General Characteristics

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

7. See Section 12.1 for more details on thermal design considerations.

Table 10-4 Recommended Operating Conditions

(V

= 0V, V

= 0V, V = 0V)

REFL x

SSA SS

Characteristic

Supply voltage

Symbol

Notes

Min

Typ

Max

Unit

V_DD,

3

3.3

3.6

V

V_DDA

ADC Reference Voltage High

Voltage difference V_DDto V_DDA

Voltage difference V_SSto V_SSA

V_REFHx

V_DD

3.0

-0.1

V_DDA

0.1

V

0

V_SS

0.1

Device Clock Frequency

Using relaxation oscillator

Using external clock source

FSYSCLK

1

0

32

MHz

Input Voltage High (digital inputs)

Input Voltage Low (digital inputs)

Oscillator Input Voltage High

V_IH

V_IL

Pin Groups 1, 2

Pin Group 4

2.0

-0.3

2.0

5.5

0.8

V

V_IHOSC

V_DDA+ 0.3

XTAL driven by an external clock source

Oscillator Input Voltage Low

V_ILOSC

Pin Group 4

-0.3

0.8

V

DAC Output Load Resistance

DAC Output Load Capacitance

RLD

CLD

I_OH

3K

—

ohms

pF

400

Output Source Current High at V_OHmin.)¹

Pin Group 1

—

-4

-8

mA

When programmed for low drive strength

When programmed for high drive strength

Output Source Current Low (at V_OLmax.)¹

I_OL

Pin Groups 1, 2

—

4

8

When programmed for low drive strength

When programmed for high drive strength

Ambient Operating Temperature

(Extended Industrial)

T_A

N_F

-40

105

—

°C

Flash Endurance

(Program Erase Cycles)

T_A= -40°C to

125°C

10,000

cycles

Flash Data Retention

T_R

T_J<= 85°C avg

15

20

—

years

Flash Data Retention with <100

Program/Erase Cycles

t_FLRET

—

1. Total chip source or sink current cannot exceed 75mA

Note: Pin groups are detailed following Table 10-1

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

143

10.2 DC Electrical Characteristics

Table 10-5 DC Electrical Characteristics

At Recommended Operating Conditions

Test

Conditions

Characteristic

Symbol

Notes

Min

Typ

Max

Unit

Output Voltage High

Output Voltage Low

V_OH

V_OL

I_IH

Pin Group 1

Pin Groups 1, 2

2.4

—

0

—

0.4

V

I_OH= I_OHmax

I_OL= I_OLmax

Digital Input Current High (a)

pull-up enabled or disabled

—

+/- 2.5

A

V_IN= 2.4V

to 5.5V

Comparator Input Current High

Oscillator Input Current High

I_IHC

I_IHOSC

I_IL

Pin Group 3

—

0

+/- 2

A

V_IN= V_DDA

V_IN= 0V

Digital Input Current Low¹

pull-up enabled

pull-up disabled

Pin Groups 1, 2

-15

—

-30

0

-60

+/- 2.5

Comparator Input Current Low

Oscillator Input Current Low

DAC Output Voltage Range

I_ILC

Pin Group 3

Pin Group 5

—

0

+/- 2

A

V

V_IN= 0V

—

I_ILOSC

V_DAC

Typically

—

Typically

V_SSA

+

V_DDA-

40mV

Output Current ¹

High Impedance State

I_OZ

Pin Groups 1, 2

—

0

+/- 2.5

A

—

Schmitt Trigger Input Hysteresis

Input Capacitance

V_HYS

C_IN

—

0.35

10

—

V

—

pF

Output Capacitance

C_OUT

10

1. See Figure 10-1

Note: Pin groups are detailed following Table 10-1

56F8037/56F8027 Data Sheet, Rev. 8

144

FreescaleSemiconductor

DC Electrical Characteristics

2.0

0.0

- 2.0

- 4.0

- 6.0

- 8.0

- 10.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Volt

Figure 10-1 I /I vs. V (Typical; Pull-Up Disabled)

IN OZ

IN

Table 10-6 Current Consumption per Power Supply Pin

Typical @ 3.3V, 25°C

Maximum@ 3.6V, 25°C

Mode

Conditions

1

I_DDA

I_DD

RUN

32MHz Device Clock

48mA

18.8mA

—

Relaxation Oscillator on

PLL powered on

Continuous MAC instructions with fetches from

Program Flash

All peripheral modules enabled. TMR and PWM

using 1X Clock

ADC/DAC powered on and clocked

Comparator powered on

WAIT

STOP

32MHz Device Clock

Relaxation Oscillator on

PLL powered on

Processor Core in WAIT state

All Peripheral modules enabled. TMR and PWM

using 1X Clock

29mA

0A

A

—

ADC/DAC/Comparator powered off

4MHz Device Clock

5.4mA

Relaxation Oscillator on

PLL powered off

Processor Core in STOP state

All peripheral module and core clocks are off

ADC/DAC/Comparator powered off

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

145

Table 10-6 Current Consumption per Power Supply Pin (Continued)

Typical @ 3.3V, 25°C

Maximum@ 3.6V, 25°C

Mode

Conditions

1

I_DDA

I_DD

STANDBY > STOP 100kHz Device Clock

Relaxation Oscillator in Standby mode

540A

0A

650A

1A

PLL powered off

Processor Core in STOP state

All peripheral module and core clocks are off

ADC/DAC/Comparator powered off

Voltage regulator in Standby mode

POWERDOWN

Device Clock is off

440A

0A

550A

1A

Relaxation Oscillator powered off

PLL powered off

Processor Core in STOP state

All peripheral module and core clocks are off

ADC /DAC/Comparator powered off

Voltage Regulator in Standby mode

1. No Output Switching

All ports configured as inputs

All inputs Low

No DC Loads

Table 10-7 Power-On Reset Low-Voltage Parameters

Typ

2.7

Max

—

Unit

Min

2.58

—

Characteristic

Symbol

V_EI3.3

V_E12.5

V_EIH

Low-Voltage Interrupt for 3.3V supply¹

V

Low-Voltage Interrupt for 2.5V supply²

2.15

50

—

Low-Voltage Interrupt Recovery Hysteresis

—

mV

V

Power-On Reset³

POR

—

1.8

1.9

1. When V drops below V

, an interrupt is generated.

DD

EI3.3

2. When V drops below V

, an interrupt is generated.

DD

EI32.5

3. Power-On Reset occurs whenever the internally regulated 2.5V digital supply drops below 1.8V. While

power is ramping up, this signal remains active for as long as the internal 2.5V is below 2.15V or the 3.3V

1/O voltage is below 2.7V, no matter how long the ramp-up rate is. The internally regulated voltage is

typically 100mV less than V during ramp-up until 2.5V is reached, at which time it self-regulates.

DD

10.2.1 Voltage Regulator Specifications

The 56F8037/56F8027 has two on-chip regulators. One supplies the PLL and relaxation oscillator. It has

no external pins and therefore has no external characteristics which must be guaranteed (other than proper

operation of the device). The second regulator supplies approximately 2.5V to the 56F8037/56F8027’s

core logic. This regulator requires an external 4.4F, or greater, capacitor for proper operation. Ceramic

and tantalum capacitors tend to provide better performance tolerances. The output voltage can be

56F8037/56F8027 Data Sheet, Rev. 8

146

FreescaleSemiconductor

AC Electrical Characteristics

measured directly on the V

pin. The specifications for this regulator are shown in Table 10-8.

CAP

Table 10-8. Regulator Parameters

Characteristic

Short Circuit Current

Symbol

I_SS

Min

—

Typical

450

Max

650

30

Unit

mA

Short Circuit Tolerance

(V_CAPshorted to ground)

T_RSC

—

minutes

10.3 AC Electrical Characteristics

Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified,

propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured

between the 10% and 90% points, as shown in Figure 10-2.

Low

V_IL

High

V_IH

90%

50%

10%

Input Signal

Midpoint1

Fall Time

Note: The midpoint is V_IL+ (V_IH– V_IL)/2.

Rise Time

Figure 10-2 Input Signal Measurement References

Figure 10-3 shows the definitions of the following signal states:

•

Active state, when a bus or signal is driven, and enters a low impedance state

Tri-stated, when a bus or signal is placed in a high impedance state

Data Valid state, when a signal level has reached V_OLor V_OH

•

Data Invalid state, when a signal level is in transition between V_OLand V_OH

Data2 Valid

Data2

Data1 Valid

Data1

Data3 Valid

Data3

Data

Tri-stated

Data Invalid State

Data Active

Figure 10-3 Signal States

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

147

10.4 Flash Memory Characteristics

Table 10-9 Flash Timing Parameters

Characteristic

Symbol

Tprog

Terase

Tme

Min

20

Typ

—

Max

40

Unit

s

Program time¹

Erase time ²

20

—

ms

Mass erase time

100

—

1. There is additional overhead which is part of the programming sequence. See the 56F802x and 56F803x Peripheral

Reference Manual for details.

2. Specifies page erase time. There are 512 bytes per page in the Program Flash memory.

10.5 External Clock Operation Timing

1

Table 10-10 External Clock Operation Timing Requirements

Characteristic

Symbol

f_osc

Min

4

Typ

8

Max

8

Unit

MHz

ns

Frequency of operation (external clock driver)²

Clock Pulse Width³

t_PW

6.25

—

3

External Clock Input Rise Time⁴

t_rise

ns

External Clock Input Fall Time⁵

t_fall

—

3

ns

1. Parameters listed are guaranteed by design.

2. See Figure 10-4 for details on using the recommended connection of an external clock driver.

3. The chip may not function if the high or low pulse width is smaller than 6.25ns.

4. External clock input rise time is measured from 10% to 90%.

5. External clock input fall time is measured from 90% to 10%.

V_IH

External

Clock

90%

50%

10%

90%

50%

10%

V_IL

t_fall

t_rise

t_PW

Note: The midpoint is V_IL+ (V_IH– V_IL)/2.

Figure 10-4 External Clock Timing

56F8037/56F8027 Data Sheet, Rev. 8

148

FreescaleSemiconductor

Phase Locked Loop Timing

10.6 Phase Locked Loop Timing

Table 10-11 PLL Timing

Characteristic

Symbol

f_osc

Min

4

Typ

8

Max

—

Unit

MHz

µs

External reference crystal frequency for the PLL¹

Internal reference relaxation oscillator frequency for the PLL

f_rosc

f_op

—

96

—

8

—

PLL output frequency²(24 x reference frequency)

PLL lock time³

192

40

—

t_plls

100

0.37

—

Accumulated jitter using an 8MHz external crystal as the PLL source⁴

Cycle-to-cycle jitter

J_A

%

t_jitterpll

350

ps

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL

is optimized for 8MHz input.

2. The core system clock will operate at 1/6 of the PLL output frequency.

3. This is the time required after the PLL is enabled to ensure reliable operation.

4. This is measured on the CLKO signal (programmed as System clock) over 264 System clocks at 32MHz System clock frequency

and using an 8MHz oscillator frequency.

10.7 Relaxation Oscillator Timing

Table 10-12 Relaxation Oscillator Timing

Characteristic

Symbol

Minimum

Typical

Maximum

Unit

Relaxation Oscillator output frequency¹

Normal Mode

Standby Mode

f_op

—

8.05

200

MHz

kHz

Relaxation Oscillator stabilization time²

t_roscs

—

1

3

ms

ps

Cycle-to-cycle jitter. This is measured on the CLKO

signal (programmed prescaler_clock) over 264 clocks³

t_jitterrosc

400

—

Minimum tuning step size

Maximum tuning step size

—

.08

40

—

%

Variation over temperature -40C to 150ºC⁴

+1.0 to -1.5 +3.0 to -3.0

0 to +1 +2.0 to -2.0

Variation over temperature 0C to 105ºC⁴

—

%

1. Output frequency after factory trim.

2. This is the time required from Standby to Normal mode transition.

3. J_Ais required to meet QSCI requirements.

4. See Figure 10-5

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

149

8.16

8.08

8

7.92

7.84

-50

-25

0

25

50

75

100

125

150

175

Degrees C (Junction)

Figure 10-5 Relaxation Oscillator Temperature Variation (Typical) After Trim

56F8037/56F8027 Data Sheet, Rev. 8

150

FreescaleSemiconductor

Reset, Stop, Wait, Mode Select, and Interrupt Timing

10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Note:

All address and data buses described here are internal.

1,2

Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Characteristic

Symbol

t_RA

Typical Min

Typical Max

Unit

ns

See Figure

Minimum RESET Assertion Duration

4T

—

10-6

—

Minimum GPIO pin Assertion for Interrupt

t_IW

2T

96T_OSC+ 64T

—

97T_OSC+ 65T

6T

ns

RESET deassertion to First Address Fetch³

t_RDA

t_IF

ns

Delay from Interrupt Assertion to Fetch of first

instruction (exiting Stop)

ns

—

1. In the formulas, T = system clock cycle and T = oscillator clock cycle. For an operating frequency of 32MHz, T = 31.25ns. At

osc

8MHz (used during Reset and Stop modes), T = 125ns.

2. Parameters listed are guaranteed by design.

3. During Power-On Reset, it is possible to use the 56F8037/56F8027 internal reset stretching circuitry to extend this period to

2^21T.

GPIO pin

(Input)

T_IW

Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive)

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

151

10.9 Serial Peripheral Interface (SPI) Timing

1

Table 10-14 SPI Timing

Characteristic

Symbol

Min

Max

Unit

See Figure

Cycle time

Master

Slave

t_C

10-7, 10-8,

10-9, 10-10

125

62.5

—

ns

Enable lead time

Master

Slave

t_ELD

t_ELG

t_CH

t_CL

10-10

—

31

—

ns

Enable lag time

Master

Slave

—

125

—

ns

Clock (SCK) high time

Master

Slave

10-7, 10-8,

10-9, 10-10

50

31

—

ns

Clock (SCK) low time

Master

Slave

10-10

50

31

—

ns

Data set-up time required for inputs

Master

Slave

t_DS

t_DH

t_A

10-7, 10-8,

10-9, 10-10

20

0

—

ns

Data hold time required for inputs

Master

Slave

10-7, 10-8,

10-9, 10-10

0

2

—

ns

Access time (time to data active from

high-impedance state)

Slave

10-10

4.8

3.7

15

ns

Disable time (hold time to high-impedance state)

Slave

t_D

15.2

Data Valid for outputs

Master

Slave (after enable edge)

t_DV

10-7, 10-8,

10-9, 10-10

—

4.5

20.4

ns

Data invalid

Master

Slave

t_DI

t_R

t_F

10-7, 10-8,

10-9, 10-10

0

—

ns

Rise time

Master

Slave

10-7, 10-8,

10-9, 10-10

—

11.5

10.0

ns

Fall time

Master

Slave

10-7, 10-8,

10-9, 10-10

—

9.7

9.0

ns

1. Parameters listed are guaranteed by design.

56F8037/56F8027 Data Sheet, Rev. 8

152

FreescaleSemiconductor

Serial Peripheral Interface (SPI) Timing

SS

(Input)

SS is held High on master

t_C

t_R

t_F

t_CL

SCLK (CPOL = 0)

(Output)

t_CH

t_F

t_R

t_CL

SCLK (CPOL = 1)

(Output)

t_DH

t_CH

t_DS

MISO

MSB in

t_DI

Bits 14–1

LSB in

t_DI(ref)

(Input)

t_DV

Bits 14–1

MOSI

(Output)

Master MSB out

t_F

Master LSB out

t_R

Figure 10-7 SPI Master Timing (CPHA = 0)

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

153

SS

(Input)

SS is held High on master

t_F

t_C

t_R

t_CL

SCLK (CPOL = 0)

(Output)

t_CH

t_F

t_CL

SCLK (CPOL = 1)

(Output)

t_CH

t_DS

t_R

t_DH

MISO

MSB in

t_DI

Bits 14–1

LSB in

t_DI(ref)

(Input)

t_DV(ref)

t_DV

Bits 14– 1

MOSI

(Output)

Master MSB out

t_F

Master LSB out

t_R

Figure 10-8 SPI Master Timing (CPHA = 1)

56F8037/56F8027 Data Sheet, Rev. 8

154

FreescaleSemiconductor

Serial Peripheral Interface (SPI) Timing

SS

(Input)

t_C

t_F

t_ELG

t_CL

t_R

SCLK (CPOL = 0)

(Input)

t_CH

t_ELD

t_CL

SCLK (CPOL = 1)

(Input)

t_CH

t_F

t_A

t_R

t_D

MISO

(Output)

Slave MSB out

Bits 14–1

t_DV

Slave LSB out

t_DI

t_DS

t_DI

t_DH

MOSI

(Input)

MSB in

Bits 14–1

LSB in

Figure 10-9 SPI Slave Timing (CPHA = 0)

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

155

SS

(Input)

t_F

t_C

t_R

t_CL

SCLK (CPOL = 0)

(Input)

t_CH

t_ELG

t_ELD

t_CL

SCLK (CPOL = 1)

(Input)

t_DV

t_CH

t_R

t_D

t_A

t_F

MISO

Slave MSB out

MSB in

Bits 14–1

t_DV

Slave LSB out

(Output)

t_DS

t_DI

t_DH

MOSI

(Input)

Bits 14–1

LSB in

Figure 10-10 SPI Slave Timing (CPHA = 1)

10.10 Quad Timer Timing

1, 2

Table 10-15 Timer Timing

Characteristic

Timer input period

Symbol

P_IN

Min

2T + 6

1T + 3

125

Max

—

Unit

ns

See Figure

10-11

Timer input high / low period

Timer output period

P_INHL

P_OUT

—

ns

10-11

—

ns

10-11

Timer output high / low period

P_OUTHL

50

—

ns

10-11

1. In the formulas listed, T = the clock cycle. For 32MHz operation, T = 31.25ns.

2. Parameters listed are guaranteed by design.

56F8037/56F8027 Data Sheet, Rev. 8

156

FreescaleSemiconductor

Quad Timer Timing

Timer Inputs

P_INHL

P_IN

Timer Outputs

P_OUTHL

P_OUT

Figure 10-11 Timer Timing

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

157

10.11 Queued Serial Communication Interface (QSCI) Timing

1

Table 10-16 QSCI Timing

Characteristic

Symbol

Min

—

Max

Unit

See Figure

—

Baud Rate²

BR

(f_MAX/16)

Mbps

RXD³Pulse Width

TXD⁴Pulse Width

RXD_PW

TXD_PW

0.965/BR

1.04/BR

ns

10-12

0.965/BR

10-13

LIN Slave Mode

Deviation of slave node clock from

nominal clock rate before

synchronization

F_{TOL_UNSYNCH}

F_{TOL_SYNCH}

T_BREAK

-14

-2

14

2

%

—

Deviation of slave node clock relative

to the master node clock after

synchronization

—

Minimum break character length

13

11

—

Master

node bit

periods

—

Slavenode

bit periods

—

1. Parameters listed are guaranteed by design.

2. f is the frequency of operation of the system clock in MHz, which is 32MHz for the 56F8037/56F8027 device.

MAX

3. The RXD pin in QSCI0 is named RXD0 and the RXD pin in QSCI1 is named RXD1.

4. The TXD pin in QSCI0 is named TXD0 and the TXD pin in QSCI1 is named TXD1.

RXD

QSCI Receive

data pin

RXD_PW

(Input)

Figure 10-12 RXD Pulse Width

TXD

QSCI Receive

data pin

TXD_PW

(Input)

Figure 10-13 TXD Pulse Width

56F8037/56F8027 Data Sheet, Rev. 8

158

FreescaleSemiconductor

Freescale’s Scalable Controller Area Network (MSCAN) Timing

10.12 Freescale’s Scalable Controller Area Network (MSCAN)

Timing

1

Table 10-17 MSCAN Timing

Characteristic

Baud rate

Bus wake-up detection

Symbol

BR_CAN

Min

—

Max

1

Unit

Mbps

µs

T_WAKEUP

T_IPBUS

—

1. Parameters listed are guaranteed by design

MSCAN_RX

CAN receive

data pin

T_WAKEUP

(Input)

Figure 10-14 Bus Wake-up Detection

2

10.13 Inter-Integrated Circuit Interface (I C) Timing

2

Table 10-18 I C Timing

Standard Mode

Minimum Maximum

Fast Mode

Minimum Maximum

Characteristic

Symbol

Unit

SCL Clock Frequency

f_SCL

0

100

—

0

400

—

kHz

Hold time (repeated)

START condition. After

this period, the first clock

pulse is generated.

t_{HD; STA}

4.0

0.6

s

LOW period of the SCL

clock

t_LOW

4.7

4.0

4.7

—

1.3

0.6

—

s

HIGH period of the SCL

clock

t_HIGH

Set-up time for a repeated

START condition

t_{SU; STA}

Data hold time for I²C bus

devices

0¹

3.45²

0¹

0.9²

t_{HD; DAT}

250³

—

100^{3, 4}

Data set-up time

t_{SU; DAT}

t_r

—

ns

5

Rise time of both SDA and

SCL signals

1000

300

20 +0.1C_b

Fall time of both SDA and

SCL signals

t_f

—

300

ns

20 +0.1C_b

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

159

2

Table 10-18 I C Timing (Continued)

Standard Mode

Minimum Maximum

Fast Mode

Characteristic

Symbol

t_{SU; STO}

t_BUF

Unit

s

Minimum

Maximum

Set-up time for STOP

condition

4.0

4.7

—

0.6

—

Bus free time between

STOP and START

condition

1.3

0

—

s

Pulse width of spikes that

must be suppressed by

the input filter

t_SP

N/A

50

ns

2

1. The master mode I C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves

acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.

2. The maximum t

must be met only if the device does not stretch the LOW period (t

) of the SCL signal.

HD; DAT

LOW

3. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.

2

4. A Fast mode I C bus device can be used in a Standard mode I C bus system, but the requirement t

>= 250ns

SU; DAT

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.

If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line

2

t

+ t

= 1000 + 250 = 1250ns (according to the Standard mode I C bus specification) before the SCL line is

rmax

SU; DAT

released.

5. C = total capacitance of the one bus line in pF

b

SDA

t

f

t

SU; DAT

t

SP

t

r

BUF

f

HD; STA

r

LOW

SCL

t

SU; STA

HD; STA

SU; STO

S

SR

P

S

t

HIGH

HD; DAT

2

Figure 10-15 Timing Definition for Fast and Standard Mode Devices on the I C Bus

56F8037/56F8027 Data Sheet, Rev. 8

160

FreescaleSemiconductor

JTAG Timing

10.14 JTAG Timing

Table 10-19 JTAG Timing

Characteristic

Symbol

Min

DC

50

5

Max

Unit

MHz

ns

See Figure

TCK frequency of operation¹

TCK clock pulse width

f_OP

SYS_CLK/8

10-16

10-17

t_PW

t_DS

t_DH

t_DV

t_TS

—

30

TMS, TDI data set-up time

TMS, TDI data hold time

TCK low to TDO data valid

TCK low to TDO tri-state

ns

5

ns

—

ns

1. TCK frequency of operation must be less than 1/8 the processor rate.

1/f_OP

t_PW

V_IH

V_M

TCK

(Input)

V_IL

V_M= V_IL+ (V_IH– V_IL)/2

Figure 10-16 Test Clock Input Timing Diagram

TCK

(Input)

t_DS

t_DH

TDI

TMS

Input Data Valid

(Input)

t_DV

TDO

(Output)

Output Data Valid

t_TS

TDO

(Output)

Figure 10-17 Test Access Port Timing Diagram

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

161

10.15 Analog-to-Digital Converter (ADC) Parameters

1

Table 10-20 ADC Parameters

Parameter

DC Specifications

Symbol

Min

Typ

Max

Unit

Resolution

R_ES

f_ADIC

R_AD

12

0.1

—

6

12

5.33

V_REFH

13

Bits

MHz

V

ADC internal clock

Conversion range

V_REFL

—

ADC power-up time²

t_AICcycles³

t_ADPU

Recovery from auto standby

t_REC

t_ADC

t_ADS

—

0

6

1

Conversion time

Sample time

Accuracy

—

Integral non-linearity⁴

(Full input signal range)

LSB⁵

INL

—

+/- 3

+/- 5

+/- 1

Differential non-linearity

DNL

+/- .6

Monotonicity

GUARANTEED

+/- 4

Offset Voltage Internal Ref

V_OFFSET

E_GAIN

—

+/- 9

+/- 12

mV

—

Offset Voltage External Ref

Gain Error (transfer gain)

+/- 6

.998 to 1.002

1.01 to .99

ADC Inputs⁶(Pin Group 3)

Input voltage (external reference)

V_ADIN

I_IA

V_REFL

V_SSA

—

V_REFH

V_DDA

+/- 2

—

V

Input voltage (internal reference)

Input leakage

—

0

A

V_REFHcurrent

I_VREFH

I_ADI

—

0

A

Input injection current⁷, per pin

Input capacitance

—

3

mA

pF

C_ADI

X_IN

—

See Figure 10-18

—

Input impedance

—

Ohms

AC Specifications

Signal-to-noise ratio

SNR

THD

60

61

58

—

65

64

66

62

dB

Total Harmonic Distortion

Spurious Free Dynamic Range

Signal-to-noise plus distortion

Effective Number Of Bits

SFDR

SINAD

ENOB

dB

10.0

Bits

1. All measurements were made at V = 3.3V, V

= 3.3V, and V = ground

REFL

DD

REFH

2. Includes power-up of ADC and V

3. ADC clock cycles

REF

4. INL measured from V = V

to V = V

IN REFH

IN

REFL

5. LSB = Least Significant Bit = 0.806mV

6. Pin groups are detailed following Table 10-1.

7. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the

ADC.

56F8037/56F8027 Data Sheet, Rev. 8

162

FreescaleSemiconductor

Equivalent Circuit for ADC Inputs

10.16 Equivalent Circuit for ADC Inputs

Figure 10-18 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed

at the same time that S3 is closed/open. When S1/S2 are closed and S3 is open, one input of the sample

and hold circuit moves to (V

- V

) / 2, while the other charges to the analog input voltage. When

REFHx

REFLx

the switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended

analog input is switched to a differential voltage centered about (V - V ) / 2. The switches

REFHx

REFLx

switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that

there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter

into the S/H output voltage, as S1 provides isolation during the charge-sharing phase.

One aspect of this circuit is that there is an on-going input current, which is a function of the analog input

voltage, V , and the ADC clock frequency.

REF

125 ESD Resistor

8pF noise damping capacitor

4

3

Analog Input

S1

C1

S/H

S3

C2

S2

(V_REFHx- V_REFLx) / 2

2

1

C1 = C2 = 1pF

1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF

2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF

3. Equivalent resistance for the channel select mux; 100 ohms

4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only

connected to it at sampling time; 1.4pF

Figure 10-18 Equivalent Circuit for A/D Loading

10.17 Comparator (CMP) Parameters

Table 10-21 CMP Parameters

Parameter

Conditions/Comments

Symbol

Min

Typ

Max

Unit

Input Offset Voltage¹

Within range of V_DDA- .1V to

V_SSA+ .1V

V_OFFSET

—

±10

±35

mV

Input Propagation Delay

Power-up time

t_PD

—

35

45

ns

t_CPU

TBD

1. No guaranteed specification within 0.1V of V

or V

SSA

DDA

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

163

10.18 Digital-to-Analog Converter (DAC) Parameters

Table 10-22 DAC Parameters

Parameter

Conditions/Comments

Symbol

Min

Typ

Max

Unit

DC Specifications

Resolution

12

TBD

—

12

2

bits

µS

Conversion time

Conversion rate

Power-up time

—

500.000

11

conv/sec

µS

Time from release of PWRDWN

signal until DACOUT signal is

valid

t_DAPU

Accuracy

Integral non-linearity¹

LSB²

Range of input digital words:

410 to 3891 ($19A - $F33)

5% to 95% of full range

INL

—

+/- 3

+/- 8.0

< - 1

Differential non-linearity¹

Range of input digital words:

410 to 3891 ($19A - $F33)

5% to 95% of full range

DNL

+/- .8

Monotonicity

Offset error¹

> 6 sigma monotonicity,

< 3.4 ppm non-monotonicity

guaranteed

+/- 25

—

Range of input digital words:

410 to 3891 ($19A - $F33)

5% to 95% of full range

V_OFFSET

—

+/- 40

mV

Gain error¹

Range of input digital words:

410 to 3891 ($19A - $F33)

5% to 95% of full range

E_GAIN

+/- .5

+/- 1.5

%

DAC Output

Output voltage range

Within 40mV of either V_REFLXor

V_REFHX

V_OUT

V_REFLX

+.04V

—

V_REFHX

- .04V

V

Short circuit current

DACOUT shorted to ground with

input digital word = $FFF

DACOUT shorted to V_DDAwith

I_SC

—

70

50

100

75

mA

input digital word = $000

AC Specifications

Signal-to-noise ratio

SNR

—

TBD

—

dB

Spurious free dynamic

range

SFDR

Effective number of bits

ENOB

9

—

bits

1. No guaranteed specification within 5% of V

2. LSB = 0.806mV

or V

SSA

DDA

56F8037/56F8027 Data Sheet, Rev. 8

164

FreescaleSemiconductor

Power Consumption

10.19 Power Consumption

See Section 10.1 for a list of IDD requirements for the 56F8037/56F8027. This section provides additional

detail which can be used to optimize power consumption for a given application.

Power consumption is given by the following equation:

Total power = A: internal [static component]

+B: internal [state-dependent component]

+C: internal [dynamic component]

+D: external [dynamic component]

+E: external [static component]

A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage currents,

PLL, and voltage references. These sources operate independently of processor state or operating

frequency.

B, the internal [state-dependent component], reflects the supply current required by certain on-chip

resources only when those resources are in use. These include RAM, Flash memory and the ADCs.

2

C, the internal [dynamic component], is classic C*V *F CMOS power dissipation corresponding to the

56800E core and standard cell logic.

D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading

2

on the external pins of the chip. This is also commonly described as C*V *F, although simulations on two

of the I/O cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero

Y-intercept.

Table 10-23 I/O Loading Coefficients at 10MHz

Intercept

Slope

8mA drive

4mA drive

1.3

0.11mW / pF

1.15mW

Power due to capacitive loading on output pins is (first order) a function of the capacitive load and

frequency at which the outputs change. Table 10-23 provides coefficients for calculating power dissipated

in the I/O cells as a function of capacitive load. In these cases:

TotalPower = ((Intercept + Slope*Cload)*frequency/10MHz)

where:

•

Summation is performed over all output pins with capacitive loads

TotalPower is expressed in mW

Cload is expressed in pF

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

165

Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found

to be fairly low when averaged over a period of time.

E, the external [static component], reflects the effects of placing resistive loads on the outputs of the

2

device. Sum the total of all V /R or IV to arrive at the resistive load contribution to power. Assume V = 0.5

for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs driving

10mA into LEDs, then P = 8*.5*.01 = 40mW.

In previous discussions, power consumption due to parasitics associated with pure input pins is ignored,

as it is assumed to be negligible.

56F8037/56F8027 Data Sheet, Rev. 8

166

FreescaleSemiconductor

56F8037/56F8027 Package and Pin-Out Information

Part 11 Packaging

11.1 56F8037/56F8027 Package and Pin-Out Information

This section contains package and pin-out information for the 56F8037/56F8027. This device comes in a

64-pin Low-profile Quad Flat Pack (LQFP). Figure 11-1 shows the package outline, Figure 11-2 shows

the mechanical parameters and Table 11-1 lists the pin-out.

Orientation

Mark

GPIOA3 / PWM3

GPIOB6 / RXD0 / SDA / CLKIN

GPIOB1 / SS0 / SDA

49

GPIOA2 / PWM2

Pin 1

GPIOB7 / TXD0 / SCL

GPIOB9 / SDA / CANRX

GPIOA14 / MOSI1/ TB3 / TA3

GPIOA13 / MISO1/ TB2 / TA2

GPIOA4 / PWM4 / TA2 / FAULT1

GPIOB0 / SCLK0 / SCL

GPIOB5 / TA1 / FAULT3 / CLKIN

GPIOA9 / FAULT2 / TA3 / CMPBI1

GPIOA11 / TB3 / CMPBI2

V

DD

V

SS

DD

GPIOC12 / ANB4 / RXD1

GPIOC4 / ANB0 / CMPBI3

GPIOC5 / ANB1

V

SS

GPIOA5 / PWM5 / TA3 / FAULT2

GPIOB4 / SS1 / TB0 / TA0 / PSRC2 / CLKO

GPIOA12 / SCLK1 / TB1 / TA1

GPIOA8 / FAULT1 / TA2 / CMPAI1

GPIOA10 / TB2 / CMPAI2

GPIOC13 / ANB5

GPIOC6 / ANB2 / V

REFHB

GPIOC7 / ANB3 / V

REFLB

33

GPIOA6 / FAULT0 / TA0

GPIOD7 / DAC1

17

GPIOB2 / MISO0 / TA2 / PSRC0

V

DDA

Figure 11-1 Top View, 56F8037/56F8027 64-Pin LQFP Package

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

167

1

Table 11-1 56F8037/56F8027 64-Pin LQFP Package Identification by Pin Number

#

Signal Name

V_SSA

Signal Name

V_CAP

1

2

3

GPIOB6

RXD0 / SDA / CLKIN

17

18

19

33

34

35

GPIOB2

MISO0 / TA2 / PSRC0

49

50

51

GPIOB1

SS0 / SDA

GPIOD6

DAC0

GPIOA6

FAULT0 / TA0

V_DD

GPIOB7

GPIOC3

GPIOA10

V_SS

TXD0 / SCL

ANA3 / V_REFLA

TB2 / CMPAI2

4

5

6

GPIOB5

TA1 / FAULT3 / CLKIN

20

21

22

GPIOC2

ANA2 / V_REFHA

36

37

38

GPIOA8

FAULT1 / TA2 /

CMPAI1

52

53

54

GPIOD5

XTAL / CLKIN

GPIOA9

FAULT2 / TA3 /

CMPBI1

GPIOC9

ANA5

GPIOA12

SCLK1 / TB1 / TA1

GPIOD4

EXTAL

GPIOA11

GPIOC1

GPIOB4

GPIOB8

TB3 / CMPBI2

ANA1

SS1 / TB0 / TA0 /

PSRC2 / CLKO

SCL / CANTX

7

8

VDD

VSS

23

24

25

26

27

28

29

GPIOC10

ANA6

39

40

41

42

43

44

45

GPIOA5

PWM5 / TA3 / FAULT2

55

56

57

58

59

60

61

GPIOA1

PWM1

GPIOC0

ANA0 & CMPAI3

V_SS

GPIOA0

PWM0

9

GPIOC12

ANB4 / RXD1

GPIOC11

ANA7

V_DD

GPIOB12

CANTX

10

11

12

13

GPIOC4

ANB0 & CMPBI3

GPIOC8

ANA4 / TXD1

GPIOB0

SCLK0 / SCL

GPIOB13

CANRX

GPIOC5

ANB1

V_SS

GPIOA4

PWM4 / TA2 / FAULT1

TDI

GPIOD0

GPIOC13

ANB5

V_CAP

GPIOA13

MISO1 / TB2 / TA2

GPIOB11

TB1 / CMPBO

GPIOC6

TCK

GPIOA14

GPIOC15

ANB2 / V_REFHB

GPIOD2

MOSI1 / TB3 / TA3

ANB7

14

GPIOC7

30

GPIOB10

46

GPIOB9

62

GPIOC14

ANB3 / V_REFLB

TB0 / CMPAO

SDA / CANRX

ANB6

15

16

GPIOD7

DAC1

31

32

RESET

GPIOA7

47

48

GPIOA2

PWM2

63

64

TMS

GPIOD3

V_DDA

GPIOB3

MOSI0 / TA3 /

PSRC1

GPIOA3

PWM3

TDO

GPIOD1

1. Alternate signals are in italic

56F8037/56F8027 Data Sheet, Rev. 8

168

FreescaleSemiconductor

56F8037/56F8027 Package and Pin-Out Information

4X

4X 16 TIPS

0.2

H

A-B

D

0.2

C

A-B D

A2

S

0.05

64

49

(S)

1

48

2X R R1

q 1

0.25

A

B

GAGE PLANE

q

E

E1

(L2)

A1

L

(L1)

3X

E1/2

VIEW Y

E/2

VIEW AA

16

33

17

32

NOTES:

1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M,

1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE DATUM H IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD WHERE

THELEADEXITSTHEPLASTICBODYATTHE BOTTOM

OF THE PARTING LINE.

D

D1/2

D/2

D1

4. DATUMS A, B AND D TO BE DETERMINED AT DATUM

PLANE DATUM C.

D

5. DIMENSIONS D AND E TO BE DETERMINED AT

SEATING PLANE DATUM C.

6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD

PROTRUSION.ALLOWABLEPROTRUSIONIS0.25PER

SIDE.

7. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL NOT

CAUSE THE b DIMENSION TO EXCEED 0.35. MINIMUM

SPACE BETWEEN PROTRUSION AND ADJACENT

LEAD OR PROTRUSION 0.07.

4X (q2)

H

A

0.08 C

MILLIMETERS

4X (q 3)

DIM MIN

MAX

1.60

0.15

1.45

0.27

0.23

0.20

0.16

SEATING

PLANE

C

A

A1

A2

b

b1

c

---

VIEW AA

0.05

1.35

0.17

0.09

c1

D

12.00 BSC

BASE METAL

D1

e

E

E1

L

L1

L2

R1

S

10.00 BSC

0.50 BSC

12.00 BSC

10.00 BSC

b1

X

X=A, B OR D

0.45

0.75

c1

c

1.00 REF

0.50 REF

0.10

0.20

C

L

0.20 REF

q

⁰

⁷

AB

e/2

PLATING

q 1

q 2

q 3

0

---

b



12 REF



60X

e

M

12 REF

0.08

C A-B D



VIEW Y

SECTION AB-AB

ROTATED 90 CLOCKWISE



Figure 11-2 56F8037/56F8027 64-Pin LQFP Mechanical Information

Please see www.freescale.com for the most current case outline.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

169

Part 12 Design Considerations

12.1 Thermal Design Considerations

An estimation of the chip junction temperature, T , can be obtained from the equation:

J

T = T + (R

x P )

D

J

A

J

where:

o

T

R

= Ambient temperature for the package ( C)

A

o

= Junction-to-ambient thermal resistance ( C/W)

J

P

= Power dissipation in the package (W)

D

The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy

estimation of thermal performance. Unfortunately, there are two values in common usage: the value

determined on a single-layer board and the value obtained on a board with two planes. For packages such

as the PBGA, these values can be different by a factor of two. Which value is closer to the application

depends on the power dissipated by other components on the board. The value obtained on a single layer

board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the

internal planes is usually appropriate if the board has low-power dissipation and the components are well

separated.

When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal

resistance and a case-to-ambient thermal resistance:

R

= R

+ R

JA

JC CA

where:

R

=

Package junction-to-ambient thermal resistance (°C/W)

Package junction-to-case thermal resistance (°C/W)

Package case-to-ambient thermal resistance (°C/W)

JA

JC

CA

R

is device related and cannot be influenced by the user. The user controls the thermal environment to

JC

change the case to ambient thermal resistance, R

. For instance, the user can change the size of the heat

CA

sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit

board, or change the thermal dissipation on the printed circuit board surrounding the device.

To determine the junction temperature of the device in the application when heat sinks are not used, the

Thermal Characterization Parameter ( ) can be used to determine the junction temperature with a

JT

measurement of the temperature at the top center of the package case using the following equation:

T = T + ( x P )

J

T

JT

D

where:

o

T



= Thermocouple temperature on top of package ( C)

= Thermal characterization parameter ( C/W)

T

o

JT

P

= Power dissipation in package (W)

D

56F8037/56F8027 Data Sheet, Rev. 8

170

FreescaleSemiconductor

Electrical Design Considerations

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T

thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so

that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire

is placed flat against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the

interface between the case of the package and the interface material. A clearance slot or hole is normally

required in the heat sink. Minimizing the size of the clearance is important to minimize the change in

thermal performance caused by removing part of the thermal interface to the heat sink. Because of the

experimental difficulties with this technique, many engineers measure the heat sink temperature and then

back-calculate the case temperature using a separate measurement of the thermal resistance of the

interface. From this case temperature, the junction temperature is determined from the junction-to-case

thermal resistance.

12.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to guard

against damage due to high static voltage or electrical

fields. However, normal precautions are advised to

avoid application of any voltages higher than

maximum-rated voltages to this high-impedance circuit.

Reliability of operation is enhanced if unused inputs are

tied to an appropriate voltage level.

Use the following list of considerations to assure correct operation of the 56F8037/56F8027:

•

Provide a low-impedance path from the board power supply to each V_DDpin on the 56F8037/56F8027 and

from the board ground to each V_SS(GND) pin

•

The minimum bypass requirement is to place 0.01–0.1µF capacitors positioned as close as possible to the

package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of

the V_DD/V_SSpairs, including V_DDA/V_SSA.Ceramic and tantalum capacitors tend to provide better

tolerances.

•

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V_DDand V_SS(GND)

pins are as short as possible

Bypass the V_DDand V_SSwith approximately 100µF, plus the number of 0.1µF ceramic capacitors

PCB trace lengths should be minimal for high-frequency signals

•

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.

This is especially critical in systems with higher capacitive loads that could create higher transient currents

in the V_DDand V_SScircuits.

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

171

•

Take special care to minimize noise levels on the V_REF, V_DDA, and V_SSApins

Using separate power planes for V_DDand V_DDAand separate ground planes for V_SSand V_SSAare

recommended. Connect the separate analog and digital power and ground planes as close as possible to

power supply outputs. If both analog circuit and digital circuit are powered by the same power supply, it is

advisable to connect a small inductor or ferrite bead in serial with both V_DDAand V_SSAtraces.

•

It is highly desirable to physically separate analog components from noisy digital components by ground

planes. Do not place an analog trace in parallel with digital traces. It is also desirable to place an analog

ground trace around an analog signal trace to isolate it from digital traces.

•

Because the Flash memory is programmed through the JTAG/EOnCE port, QSPI, QSCI, or I²C, the

designer should provide an interface to this port if in-circuit Flash programming is desired

If desired, connect an external RC circuit to the RESET pin. The Resistor value should be in the range of

4.7k—10k; the Capacitor value should be in the range of 0.22µf - 4.7µf.

Add a 3.3k external pull-up on the TMS pin of the JTAG port to keep EOnce in a restate during normal

operation if JTAG converter is not present

During reset and after reset but before I/O initialization, all I/O pins are at input state with internal pull-up

enable. The typical value of internal pull-up is around 110K. These internal pull-ups can be disabled by

software.

•

To eliminate PCB trace impedance effect, each ADC input should have a 33pf-10 ohm RC filter

Device GPIOs have only a down (substrate) diode on the GPIO circuit. Devices do not have a positive clamp

diode because GPIOs use a floating gate structure to tolerate 5V input. The absolute maximum clamp

current is -20mA at V_inless than 0V. The continuous clamp current is -2mA at V_inless than 0V. If positive

voltage spikes are a concern, a positive clamp is recommended.

Part 13 Ordering Information

Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor

sales office or authorized distributor to determine availability and to order devices.

Table 13-1 56F8037/56F8027 Ordering Information

Ambient

Temperature

Range

Supply

Voltage

Count

Frequency

(MHz)

Device

Package Type

Order Number

Low-Profile Quad Flat Pack (LQFP)

MC56F8037

MC56F8027

MC56F8037

MC56F8027

3.0–3.6 V

64

32

-40° to + 105° C

-40° to + 125° C

MC56F8037VLH*

MC56F8027VLH*

MC56F8037MLH*

MC56F8027MLH*

* This package is RoHS compliant.

56F8037/56F8027 Data Sheet, Rev. 8

172

FreescaleSemiconductor

Electrical Design Considerations

Part 14 Appendix

Register acronyms are revised from previous device data sheets to provide a cleaner register description.

A cross reference to legacy and revised acronyms are provided in the following table.

Table 14-1 Legacy and Revised Acronyms

Peripheral Reference

Manual

Memory

Address

Data Sheet

Processor Expert

Acronym

Register Name

New

Legacy

New

Acronym

Legacy

Acronym

Start

End

Acronym

Analog-to-Digital Converter (ADC) Module

Control 1 Register

Control 2 Register

CTRL1

CTRL2

ADCR1

ADCR2

ADZCC

ADC_CTRL1

ADC_CTRL2

ADC_ZXCTRL

ADC_ADCR1

ADC_ADCR2

ADC_ADZCC

ADC_ADCR1

ADC_ADCR2

ADC_ADZCC

0xF080

0xF081

0xF082

Zero Crossing Control

Register

ZXCTRL

Channel List 1

Register

CLIST1

CLIST2

CLIST3

CLIST4

SDIS

ADLST1

ADLST2

ADC_CLIST1

ADC_CLIST2

ADC_CLIST3

ADC_CLIST4

ADC_SDIS

ADC_ADLST1

ADC_ADLST2

ADC_ADCLST3

ADC_ADCLST4

ADC_ADSDIS

ADC_ADLST1

ADC_ADLST2

ADC_ADCLST3

ADC_ADCLST4

ADC_ADSDIS

0xF083

0xF084

0xF085

0xF086

0xF087

Channel List 2

Register

Channel List 3

Register

Channel List 4

Register

Sample Disable

Register

ADSDIS

ADSTAT

Status Register

STAT

RDY

ADC_STAT

ADC_ADSTAT

0xF088

0xF089

Conversion Ready

Register

ADC_CNRDY

ADC_ADCNRDY

Limit Status Register

LIMSTAT

ZXSTAT

ADLSTAT

ADC_LIMSTAT

ADC_ZXSTAT

ADC_ADLSTAT

0xF08A

0xF08B

Zero Crossing Status

Register

ADZCSTAT

ADC_ADZCSTAT

Result 0-7 Registers

Result 8-15 Registers

RSLT0-7

RSLT8-15

LOLIM0-7

ADRSLT0-7

ADC_RSLT0-7

ADC_RSLT8-15

ADC_LOLIM0-7

ADC_ADRSLT0-7

ADC_ADRSLT8-15

ADC_ADLLMT0-7

ADC_ADRSLT0-7

ADC_ADRSLT8-15

ADC_ADLLMT0-7

0xF08C 0XF093

0xF094 0XF09B

0XF09C 0XF0A3

Low Limit 0-7

Registers

ADLLMT0-7

ADHLMT0-7

High Limit 0-7

Registers

HILIM0-7

ADC_HILIM0-7

ADC_ADHLMT0-7

0XF0A4 0XF0AB

Offset 0-7 Registers

OFFST0-7

PWR

ADOFS0-7

ADPOWER

ADC_OFFST0-7

ADC_PWR

ADC_ADOFS0-7

ADC_ADPOWER

ADC_ADOFS0-7

ADC_ADPOWER

0XF0AC 0XF0B3

0XF0B4

Power Control

Register

Calibration Register

CAL

ADC_CAL

ADC_ADCAL

0XF0B5

Computer Operating Properly (COP) Module

Control Register

Timeout Register

Counter Register

CTRL

TOUT

CNTR

COPCTL

COPTO

COP_CTRL

COP_TOUT

COP_CNTR

COPCTL

COPTO

COPCTL

COPTO

0XF120

0XF121

0XF122

COPCTR

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

173

Table 14-1 Legacy and Revised Acronyms (Continued)

Peripheral Reference

Data Sheet

Memory

Address

Manual

Processor Expert

Register Name

Acronym

New

Legacy

New

Legacy

Start

End

Acronym

Inter-Integrated Circuit Interface (I²C) Module

Control Register

CTRL

TAR

IBCR

I2C_CTRL

I2C_TAR

I2C_IBCR

I2CTAR

I2C_IBCR

I2C_TAR

0xF280

0xF282

Target Address

Register

Slave Address

Register

SAR

DATA

I2C_SAR

I2C_DATA

I2CSAR

I2C_SAR

0xF242

0xF288

0xF28A

Data Buffer &

Command Register

I2C_DATACMD

I2C_SS_SCLHCNT

I2C_DATACMD

I2C_SS_SCLHCNT

Standard Speed

Clock SCL High

Count Register

SSHCNT

I2C_SS_SCL_HCNT

Standard Speed

Clock SCL Low Count

Register

SSLCNT

FSHCNT

FSLCNT

I2C_SS_SCL_LCNT

I2C_FS_SCL_HCNT

I2C_FS_SCL_LCNT

I2C_SS_SCLLCNT

I2C_FS_SCLHCNT

I2C_FS_SCLLCNT

I2C_SS_SCLLCNT

I2C_FS_SCLHCNT

I2C_FS_SCLLCNT

0xF28C

0xF28E

0xF290

Fast Speed Clock

SCL High Count

Register

Fast Speed Clock

SCL Low Count

Register

Interrupt Status

Register

ISTAT

IENBL

RISTAT

RXFT

I2C_INTR_STAT

I2C_INTR_MASK

I2C_INTRSTAT

I2C_INTRMASK

I2C_INTRSTAT

I2C_INTRMASK

I2C_RAW_INTRSTAT

I2C_RXTL

0xF296

0xF298

0xF29A

0xF29C

Interrupt Mask

Register

Raw Interrupt Status

Register

I2C_RAW_INTR_ STAT I2C_RAW_INTRSTAT

I2C_RXTL

Receive FIFO

Threshold Level

Register

Transmit FIFO

Threshold Level

Register

TXFT

I2C_TXTL

0xF29E

0xF2A0

Clear Combined &

Individual Interrupts

Register

CLRINT

I2C_CLRINTR

Clear Receive Under

Interrupt Register

CLRRXUND

CLRRXOVR

CLRTXOVR

CLRRDREQ

CLRTXABRT

I2C_CLR_RXUNDER

I2C_CLROVER

I2C_CLR_RXUNDER

I2C_CLROVER

0xF2A2

0xF2A4

0xF2A6

0xF2A8

0xF2AA

Clear Receive Over

Interrupt Register

Clear Transmit Over

Register

I2C_CLR_TXOVER

I2C_CLR_RDREQ

I2C_CLR_TXABRT

I2C_CLR_TXOVER

I2C_CLR_RDREQ

I2C_CLR_TXABRT

Clear Read Required

Interrupt Register

Clear Transmit Abort

Interrupt Register

56F8037/56F8027 Data Sheet, Rev. 8

174

FreescaleSemiconductor

Electrical Design Considerations

Table 14-1 Legacy and Revised Acronyms (Continued)

Peripheral Reference

Manual

Memory

Address

Data Sheet

Processor Expert

Acronym

Register Name

New

Legacy

New

Acronym

Legacy

Acronym

Start

End

Acronym

Clear Receive Done

Interrupt Register

CLRRXDONE

I2C_CLR_RXDONE

I2C_CLRACTIVITY

I2C_CLR_STOPDET

I2C_CLR_STAR_DET

I2C_CLR_GENCALL

I2C_CLR_RXDONE

I2C_CLRACTIVITY

I2C_CLR_STOPDET

I2C_CLR_STAR_DET

I2C_CLR_GENCALL

0xF2AC

0xF2AE

0xF2B0

0xF2B2

0xF2B4

Clear Activity Interrupt

Register

CLRACT

Clear Stop Detect

Interrupt Register

CLRSTPDET

CLRSTDET

CLRGC

Clear Start Detect

Interrupt Register

Clear General Call

Interrupt Register

Enable Register

Status Register

ENBL

STAT

I2C_ENABLE

I2C_STAT

I2C_ENABLE

I2C_STAT

0xF2B6

0xF2B8

0xF2BA

Transmit FIFO Level

Register

TXFLR

I2C_TXFLR

Receive FIFO Level

Register

RXFLR

I2C_RXFLR

I2C_TX_ABRTSRC

I2C_COMPARM1

I2C_COMPARM2

I2C_COMVER1

I2C_COMVER2

I2C_COMTYP1

I2C_COMTYP2

I2C_RXFLR

I2C_TX_ABRTSRC

I2C_COMPARM1

I2C_COMPARM2

I2C_COMVER1

I2C_COMVER2

I2C_COMTYP1

I2C_COMTYP2

0xF2BC

0xF2C0

0xF2FA

0xF2FB

0xF2FC

0xF2FD

0xF2FE

0xF2FF

Transmit Abort

Source Register

TXABRTSRC

COMPARM1

COMPARM2

COMVER1

COMVER2

COMTYP1

COMTYP2

Component

Parameter 1 Register

Component

Parameter 2 Register

Component Version 1

Register

Component Version 2

Register

Component Type 1

Register

Component Type 2

Register

On-Clock Chip Synthesis (OCCS) Module

Control Register

Divide-By Register

Status Register

CTRL

DIVBY

STAT

PLLCR

PLLDB

PLLSR

OSCTL

OCCS_CTRL

OCCS_DIVBY

OCCS_STAT

OCCS_OCTRL

PLLCR

PLLDB

PLLSR

OSCTL

PLLCR

PLLDB

PLLSR

OSCTL

0xF130

0xF131

0xF132

0xF135

Oscillator Control

Register

OCTRL

Clock Check Register

Protection Register

Clock Divider Register

CLKCHK

PROT

OCCS_CLCHK

OCCS_PROT

FM_CLKDIV

FM_CNFG

PLLCLCHK

PLLPROT

FMCLKD

FMCR

OCCS_CLCHK

OCCS_PROT

FMCLKD

0xF136

0xF137

0xF400

0xF401

CLKDIV

CNFG

FMCLKD

FMCR

Configuration

Register

FMCR

Security High Half

Register

SECHI

FMSECH

FM_SECHI

FMSECH

0xF403

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

175

Table 14-1 Legacy and Revised Acronyms (Continued)

Peripheral Reference

Data Sheet

Memory

Address

Manual

Processor Expert

Register Name

Acronym

New

Legacy

New

Legacy

Start

End

Acronym

Security Low Half

Register

SECLO

FMSECL

FM_SECLO

FMSECL

0xF404

Protection Register

User Status Register

Command Register

Data Buffer Register

PROT

USTAT

CMD

FMPROT

FMUSTAT

FMCMD

FM_PROT

FM_USTAT

FM_CMD

FMPROT

FMUSTAT

FMCMD

FMPROT

FMUSTAT

FMCMD

0xF410

0xF413

0xF414

0xF418

0xF41B

DATA

OPT1

FMDATA

FMOPT1

FM_DATA

FM_OPT1

FMDATA

FMOPT1

FMDATA

FMOPT1

Info Optional Data 1

Register

Test Array Signature

Register

TSTSIG

FMTST_SIG

FM_TSTSIG

FMTST_SIG

0xF41D

General Purpose Input/Output (GPIO) Module

x= A (n=0) B (n=1) C (n=2) D (n=3)

Pull-Up Enable

Register

PUPEN

PUR

GPIOx_PUPEN

GPIOx_PUR

GPIO_x_PUR

0xF1n0

Data Register

DATA

DDIR

DR

GPIOx_DATA

GPIOx_DDIR

GPIOx_DR

GPIO_x_DR

0xF1n1

0xF1n2

Data Direction

Register

DDR

GPIOx_DDR

GPIO_x_DDR

Peripheral Enable

Register

PEREN

IASSRT

IEN

PER

IAR

GPIOx_PEREN

GPIOx_IASSRT

GPIOx_IEN

GPIOx_PER

GPIOx_IAR

GPIO_x_PER

GPIO_x_IAR

0xF1n3

0xF1n4

0xF1n5

0xF1n6

0xF1n7

0xF1n8

Interrupt Assert

Register

Interrupt Enable

Register

IENR

IPOLR

IPR

GPIOx_IENR

GPIOx_IPOLR

GPIOx_IPR

GPIO_x_IENR

GPIO_x_IPOLR

GPIO_x_IPR

Interrupt Polarity

Register

IPOL

GPIOx_IPOL

Interrupt Pending

Register

IPEND

IEDGE

GPIOx_IPEND

GPIOx_IEDGE

Interrupt

IESR

GPIOx_IESR

GPIO_x_IESR

Edge-Sensitive

Register

Push-Pull Mode

Registers

PPOUTM

RDATA

DRIVE

PPMODE

RAWDATA

DRIVE

GPIOx_PPOUTM

GPIOx_RDATA

GPIOx_DRIVE

GPIOx_PPMODE

GPIOx_RAWDATA

GPIOx_DRIVE

GPIO_x_PPMODE

GPIO_x_RAWDATA

GPIO_x_DRIVE

0xF1n9

0xF1nA

0xF1nB

Raw Data Input

Register

Output Drive Strength

Register

56F8037/56F8027 Data Sheet, Rev. 8

176

FreescaleSemiconductor

Electrical Design Considerations

Table 14-1 Legacy and Revised Acronyms (Continued)

Peripheral Reference

Manual

Memory

Address

Data Sheet

Processor Expert

Acronym

Register Name

New

Legacy

New

Acronym

Legacy

Acronym

Start

End

Acronym

Pulse Width Modulator (PWM) Module

Control Register

CTRL

FCTRL

FLTACK

PMCTL

PMFCTL

PMFSA

PWM_CTRL

PWM_FCTRL

PWM_FLTACK

PWM_PMCTL

PWM_PMFCTL

PWM_PMFSA

0xF0C0

0xF0C1

0xF0C2

Fault Control Register

PWM_PMFCTL

PWM_PMFSA

Fault

Status/Acknowledge

Regis.

Output Control

Register

OUT

PMOUT

PWM_OUT

PWM_PMOUT

0xF0C3

Counter Register

CNTR

PMCNT

MCM

PWM_CNTR

PWM_CMOD

PWM_PMCNT

PWM_MCM

PWM_PMCNT

PWM_MCM

0xF0C4

0xF0C5

Counter Modulo

Register

CMOD

Value 0-5 Registers

VAL0-5

PMVAL0-5

PWM_VAL0-5

PWM_DTIM0-1

PWM_PMVAL0-5

0xF0C6 0xF0CB

Deadtime 0-1

Registers

DTIM0-1

PMDEADTM0-1

PWM_PMDEADTM0-1 PWM_PMDEADTM0-1 0xF0CC 0xF0CD

Disable Mapping 1-2

Registers

DMAP1-2

PMDISMAP1-2

PWM_DMAP1-2

PWM_PMDISMAP1-2

PWM_PMDISMAP1-2 0xF0CE 0xF0CF

Configure Register

CNFG

PMCFG

PMCCR

PWM_CNFG

PWM_CCTRL

PWM_PMCFG

PWM_PMCCR

PWM_PMCFG

PWM_PMCCR

0xF0D0

0xF0D1

Channel Control

Register

CCTRL

Port Register

PORT

PMPORT

PMICCR

PWM_PORT

PWM_PMPORT

PWM_PMICCR

PWM_PMPORT

PWM_PMICCR

0xF0D2

0xF0D3

Internal Correction

Control Register

ICCTRL

PWM_ICCTRL

Source Control

Register

SCTRL

SYNC

PMSRC

PWM_SCTRL

PWM_SYNC

PWM_PMSRC

PWM_SYNC

PWM_PMSRC

PWM_SYNC

0xF0D4

0xF0D5

Synchronization

Window Register

Fault Filter 0-3

Register

FFILT0-3

PWM_FFILT0-3

0xF0D6 0xF0D9

Multi-Scalable Controller Area Network (MSCAN) Module

Control 0 Register

CTRL0

CTRL1

BTR0

BTR1

RFLG

RIER

CAN_CTRL0

CAN_CTRL1

CAN_BTR0

CAN_BTR1

CAN_RFLG

CAN_RIER

CANCTRL0

CANCTRL1

CANBTR0

CANBTR1

CANRFLG

CANRIER

0XF800

0XF801

0XF802

0XF803

0XF804

0XF805

Control 1 Register

Bus Timing 0 Register

Bus Timing 1 Register

Receive Flag Register

Receiver Interrupt

Enable Register

Transmitter Flag

Register

TFLG

TIER

CAN_TFLG

CAN_TIER

CAN_TARQ

CANTFLG

CANTIER

CANTARQ

0XF806

0XF807

0XF808

Transmitter Interrupt

Enable Register.

Transmitter Msg Abort

Request Register

TARQ

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

177

Table 14-1 Legacy and Revised Acronyms (Continued)

Peripheral Reference

Data Sheet

Memory

Address

Manual

Processor Expert

Register Name

Acronym

New

Legacy

New

Legacy

Start

End

Acronym

Transmitter Message

Abort Acknowledge

Register

TAAK

CAN_TAAK

CANTAAK

0XF809

Transmitter FIFO

Selection Register

TBSEL

IDAC

CAN_TBSEL

CAN_IDAC

CANTBSEL

CANIDAC

0XF80A

0XF80B

Identifier Acceptance

Control Register

Miscellaneous

Register

MISC

CAN_MISC

CANMISC

0XF80D

Receive Error

Register

RXERR

TXERR

IDAR0-3

IDMR0-3

IDAR4-7

IDMR4-7

RXFG

CAN_RXERR

CAN_TXERR

CAN_IDAR0-3

CAN_IDMR0-3

CAN_IDAR4-7

CAN_IDMR4-7

CAN_RXFG

CAN_TXFG

CANRXERR

CANTXERR

CANIDAR0-3

CANIDMR0-3

CANIDAR4-7

CANIDMR4-7

CANRXFG

CANTXFG

0XF80E

Transmit Error

Register

0XF80F

Identifier Acceptance

0-3 Registers

0xF810 0xF813

0xF814 0xF817

0xF818 0xF81B

0xF81C 0xF81F

0xF82F 0xF820

0xF830 0xF83F

Identifier Mask 0-3

Registers

Identifier Acceptance

4-7 Register

Identifier Mask 4-7

Registers

Foreground Receive

FIFO Register

Foreground Transmit

FIFO Register

TXFG

Power Supervisor (PS) Module

Control Register

Status Register

CTRL

STAT

LVICONTROL

LVISTATUS

PS_CTRL

PS_STAT

LVICONTROL

LVISTATUS

LVICTRL

LVISR

0xF140

0xF141

Queued Serial Communications Interface (QSCI) Module

n= 0, 1

Baud Rate Register

Control 1 Register

Control 2 Register

Status Register

RATE

CTRL1

CTRL2

STAT

QSCI_RATE

QSCI_CTRL1

QSCI_CTRL2

QSCI_STAT

QSCI_DATA

QSCI_SCIBR

QSCI_SCICR

QSCI_SCICR2

QSCI_SCISR

QSCI_SCIDR

0xF2n0

0xF2n1

0xF2n2

0xF2n3

0xF2n4

Data Register

DATA

Queued Serial Peripheral Interface (QSPI) Module

Status and Control

Register

SCTRL

DSCTRL

DRCV

QSPI_SCTRL

QSPI_SPSCR

QSPI_SPDSR

QSPI_SPDRR

QSPI_SPDTR

0xF2n0

0xF2n1

0xF2n2

0xF2n3

Data Size and Control

Register

QSPI_DSCTRL

QSPI_DRCV

QSPI_DXMIT

Data Receive

Register

Data Transmit

Register

DXMIT

56F8037/56F8027 Data Sheet, Rev. 8

178

FreescaleSemiconductor

Electrical Design Considerations

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor

179

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

support@freescale.com

USA/Europe or Locations Not Listed:

Freescale Semiconductor

Technical Information Center, CH370

1300 N. Alma School Road

Chandler, Arizona 85224

+1-800-521-6274 or +1-480-768-2130

support@freescale.com

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

support@freescale.com

RoHS-compliant and/or Pb-free versions of Freescale products have the

functionality and electrical characteristics of their non-RoHS-compliant

and/or non-Pb-free counterparts. For further information, see

http://www.freescale.com or contact your Freescale sales representative.

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

For information on Freescale’s Environmental Products program, go to

http://www.freescale.com/epp.

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064, Japan

0120 191014 or +81 3 5437 9125

support.japan@freescale.com

Information in this document is provided solely to enable system and

software implementers to use Freescale Semiconductor products. There are

no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits or integrated circuits based on the

information in this document.

Asia/Pacific:

Freescale Semiconductor China Ltd.

Exchange Building 23F

No. 118 Jianguo Road

Chaoyang District

Beijing 100022

China

Freescale Semiconductor reserves the right to make changes without further

notice to any products herein. Freescale Semiconductor makes no warranty,

representation or guarantee regarding the suitability of its products for any

particular purpose, nor does Freescale Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or

incidental damages. “Typical” parameters that may be provided in Freescale

Semiconductor data sheets and/or specifications can and do vary in different

applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer

application by customer’s technical experts. Freescale Semiconductor does

not convey any license under its patent rights nor the rights of others.

Freescale Semiconductor products are not designed, intended, or authorized

for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other

application in which the failure of the Freescale Semiconductor product could

create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended

or unauthorized application, Buyer shall indemnify and hold Freescale

Semiconductor and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized

use, even if such claim alleges that Freescale Semiconductor was negligent

regarding the design or manufacture of the part.

+86 10 5879 8000

support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center

1-800-441-2447 or 303-675-2140

Fax: 303-675-2150

LDCForFreescaleSemiconductor@hibbertgroup.com

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor,

Inc. All other product or service names are the property of their respective owners.

This product incorporates SuperFlash® technology licensed from SST.

MC56F8037

Rev. 8

04/2012


型号：	935314082528
厂家：	NXP
描述：	Microcontroller 时钟微控制器外围集成电路
文件：	总180页 (文件大小：1801K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935314082528 [NXP]

相关型号：

935314082557

935314087574

935314156557

935314173574

935314192575

935314219557

935314224557

935314228518

935314228574

935314256518

935314325518

935314325574