935314499518 [NXP]
Interface Circuit;
| 型号： | 935314499518 |
| 厂家： | 
NXP |
| 描述： | Interface Circuit 电信 电信集成电路 |
| 文件： | 总13页 (文件大小：475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33790
Rev 13.0, 2/2014
escale Semiconductor
Technical Data
Two Channel Distributed
System Interface (DSI) Physical
Interface Device
33790
The 33790 is a dual channel physical layer interface IC for the
Distributed System Interface (DSI) bus. It is designed to meet
automotive requirements. It can also be used in non automotive
applications. It supports bidirectional communication between slave
and master ICs. Some slave devices derive a regulated 5.0 V from
the bus, which can be used to power sensors, thereby eliminating the
need for additional circuitry and wiring. This device is powered by
SMARTMOS technology.
DISTRIBUTED SYSTEM INTERFACE (DSI)
Features
• Two independent DSI compatible buses
• Wave-shaped bus output voltage
• Independent thermal shutdown and current limit
• Return signalling current detection
• Internal logic input pull-ups and pull-downs
• On-board charge pump
EG SUFFIX (PB-FREE)
98ASB42567B
16-PIN SOICW
• 2.0 kV ESD capability
• Communications rate up to 150 kbps
Applications
• Simple bus for remote control and sensing
• Automotive, aircraft, marine, industrial controls,
and safety systems
• Heating and air-conditioning
33790
+5.0 V
DSI0F
DSI0S
DSI0R
DSI1F
DSI1S
DSI1R
CPCAP
VDD
GND
DSI0O
VSUP
DSI1O
GND
MCU
+25 V
BUS_IN
BUS_OUT
BUS_OUT
33793
33793
DSI
SLAVE
DEVICE
BUS_IN
33793
Figure 1. 33790 Simplified Application Diagram
© Freescale Semiconductor, Inc., 2010 - 2014. All rights reserved.
ERABLE PARTS
ORDERABLE PARTS
Table 1. Orderable Part Variations
Temperature (T )
Part Number
Package
A
MC33790HEG/R2
-40 to 85 C
16 SOICW
33790
Analog Integrated Circuit Device Data
2
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VSUP (IDLE Level)
VDD (+5.0 V)
CPCAP
Internal
Bias
Charge
Pump
Bus Supply
Voltage
+
DSI0O
Bus Current
Sense
Wave-
Shaper
DSI0F
DSI0S
DSI Bus
Transmitter
Driver
DSI0R
GND
+
DSI1O
Bus Current
Sense
DSI1F
DSI1S
Wave-
Shaper
DSI Bus
Transmitter
Driver
DSI1R
Figure 2. 33790 Simplified Internal Block Diagram
33790
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
CONNECTIONS
PIN CONNECTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DSI0F
DSI0S
DSI0R
DSI1F
DSI1S
DSI1R
NC
VDD
GND
DSI0O
VSUP
DSI10
GND
NC
CPCAP
NC
Figure 3. 33790 Pin Connections
Table 2. 33790 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 9.
Pin Number Pin Name
Definition
1
2
DSI0F
DSI0S
DSI0R
DSI1F
DSI1S
DSI1R
NC
This logic input controls the frame output for DSI channel 0 in accordance with Table 6, page 9.
This logic input controls the signalling output for DSI channel 0 in accordance with Table 6, page 9.
3
This logic output provides the return data for DSI channel 0 in accordance with Table 6, page 9.
4
This logic input controls the frame output for DSI channel 1 in accordance with Table 6, page 9.
5
This logic input controls the signalling output for DSI channel 1 in accordance with Table 6, page 9.
6
This logic output provides the return data for DSI channel 1 in accordance with Table 6, page 9.
7
Unused.
8
CPCAP
NC
Used to store and filter charge pump output.
9
Unused.
10
11
12
13
14
15
16
NC
Unused.
GND
Circuit and bus ground return.
DSI1O
VSUP
DSI0O
GND
DSI bus 1 input/output.
Idle level supply input. The voltage supplied to this pin sets the idle level on the DSI bus.
DSI bus 0 input/output.
Circuit and bus ground return.
VDD
5.0 V logic supply input.
33790
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Supply Voltage
V
Continuous
V
-0.5 to 25
40
SUP
Load Dump - t < 300 ms
V
SUP(t)
Maximum Voltage on Input/Output Pins
V
-0.3 to 5.5
V
DD
-0.3 to V +0.3
DSIxS, DSIxF (1)
DSIxO (1)
DD
-0.3 to V
+0.3
SUP
Storage Temperature
T
-55 to 150
-40 to 85
-40 to 150
Note 3
C
C
STG
Operating Ambient Temperature
Operating Junction Temperature
Peak Package Reflow Temperature During Reflow (2)
Continuous Current per Pin
T
A
T
C
J
(3)
°C
,
TPPRT
V
0 to 10
-2.5 to 5.0
500
mA
DD
DSIxR
V
SUP
Thermal Resistance Junction to Ambient
Thermal Shutdown
R
45
C/W
C
JA
T
155 to 190
SD
ESD Voltage (All Pins) (4)
Human Body Model
Machine Model
V
V
2000
200
ESD1
VESD2
Notes
1. R= 0
2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
4. ESD1 performed in accordance with the Human Body Model (CZAP=100 pF, RZAP=1500 ), ESD2 performed in accordance with the
Machine Model (CZAP=200 pF, RZAP=0 ).
33790
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
CTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 4.75 V VDD 5.25 V, 8.0 V VSUP 25.0 V, -40 C TJ 150 C, unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SUPPLY
ISUP Supply Current /Channel (Not Including IOUT
DSIx0 = Idle Voltage, -100 mA IOUT 0 mA
DSIx0 = Output High Voltage, IOUT = 12 mA
)
mA
I
–
–
1.35
5.0
3.25
9.00
SUPI
I
SUPH
IDD Supply Current/Channel
I
–
0.5
1.0
mA
DD
BUS TRANSMITTER
VSUP to DSIxO ON Resistance (During Idle)
IOUT = -100 mA
R
V
V
DS(ON)
–
–
10
Output High Voltage
DSIV
OH
DSIx0 (-15 mA I
1.0 mA)
1.0 mA)
4.175
4.5
4.825
OUT
Output Low Voltage
DSIV
I
OL
DSIx0 (-15 mA I
1.325
-100
110
1.5
–
1.675
-200
220
OUT
Output High Side Current Limit (5)
CLH
mA
mA
A
Output Low Side Current Limit (5)
Input Leakage
CLL
I
–
DSI
IB
DSIxO When DSIxF Is High and DSIxS Is Low (0 V DSIxO Min
(V = 16.5 V))
-200
–
50
SUP
BUS RECEIVER
Return Current Threshold
I
-5.0
1.10
-6.0
-7.0
2.20
mA
RH
MICROCONTROLLER INTERFACE
Logic Input Thresholds DSIxS, DSIxF
V
–
–
V
V
IN(TH)
Output High Voltage
DSIxR Pin = -0.5 mA
V
OH
0.8 V
V
DD
DD
Output Low Voltage
DSIxR Pin = 1.0 mA
V
I
V
OL
0.0
-100
10
–
–
–
0.2 V
DD
Internal Pull-up for DSIxF
-10
A
A
IL
Internal Pull-down for DSIxS
I
100
IH
Notes
5. After 10 s settling time (assured by design).
33790
Analog Integrated Circuit Device Data
6
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V VDD 5.25 V, 8.0 V VSUP 25.0 V, -40 C TJ 150 C, unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
MICROCONTROLLER INTERFACE
Microcontroller Signal Cycle Time
t
6.6
2.0
2.0
30
–
–
1000
667
667
36
s
s
s
%
CYC
Microcontroller Signal Low Time
t
CYCL
CYCH
Microcontroller Signal High Time
t
–
Microcontroller Signal Duty Cycle for Logic Zero
Microcontroller Signal Duty Cycle for Logic One
DC
LO
33
66.7
–
DC
HI
60.0
–
72.0
500
%
Microcontroller Signal Slew Time (6)
Frame Start to Signal Delay Time
Signal End to Frame End Delay Time
SLEW
tDLY1
tDLY2
tRISE
t
ns
t
-0.1
t
t +0.1
cyc
s
s
ns
cyc
cyc
–
1.0
0
–
Rise Time (6)
–
–
100
Fall Time (6)
tFALL
0
100
ns
BUS TRANSMITTER
Idle to Frame and Frame to Idle Slew Rate
tSLEW(FRAME)
V/s
V/s
s
C 5.0 nF
3.0
3.0
6.0
4.5
10.0
8.0
Signal High to Low and Signal Low to High Slew Rate
tSLEW(SIGNAL)
C 5.0 nF
Data Valid (VSUPx = 25 V, CL 5.0 nF)
t
2.44
0.25
0.25
0.25
–
–
–
–
6.56
1.3
DVLD1
DSIxF, V
DSIxS, V
DSIxS, V
DSIxF, V
to DSIxO = 5.3 V
to DSIxO = 2.6 V
to DSIxO = 3.4 V
to DSIxO = 7.0 V
IN(TH)
IN(TH)
IN(TH)
IN(TH)
t
DVLD2
t
t
1.3
DVLD3
DVLD4
1.3
BUS RECEIVER
Receiver Delay Time
ns
t
t
: I = I
to DSIxR = 2.5 V
to DSIxR = 2.5 V
t
–
–
400
400
750
750
DRH
RH
RH
DRH
: I = I
t
DRL
DRL
Notes
6. Slew times and rise and fall times between 10% and 90% of output high and low levels.
33790
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
CTRICAL CHARACTERISTICS
TIMING CHARACTERISTICS
TIMING CHARACTERISTICS
tCYC
t
CYC
tDLY2
t
H
CYC
5.0 V
DSIxS
VIN(TH)
0 V
tRISE
t
L
CYC
tRISE
tDLY1
tFALL
5.0 V
DSIxF
VIN(TH)
0 V
t
DVLD4
t
(FRAME)
SLEW
tDVLD1
25 V
7.0 V
tDVLD3
t
(SIGNAL)
SLEW
DSIxO
5.0 V
tDVLD2
DSIVOH
4.5 V
Note (7)
3.0 V
1.5 V
tTAT
(Note (8)
)
IOUT
I
RH
0 mA
5.0 V
tDRH
tDRL
DSIxR
(Note (9)
)
0 V
Figure 4. Timing Characteristics
Notes
7. Typical BUSIN/BUSOUT logic thresholds (VTHL) from MC33793 datasheet.
8. tTAT (Turnaround Time) is dependent upon wire length, bus loads, and slave response characteristics.
9. DSIxR stable on falling edge of DSIxS or rising edge of DSIxF.
33790
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33790 is designed to provide the interface between logic
and the DSI bus. It accepts signals with a typical 0 V to 5.0 V
logic level to control the state of the bus output (Idle Level,
Logic High Level, Logic Low Level, and High Impedance). It
detects the current drawn from the bus output during
to the bus current being above (Logic [1] out) the bus return
logic [1] current or below (Logic [0] out). The 33790 contains
current limiting of the bus outputs as required by the DSI Bus
specification and thermal shutdown to protect itself from
damage. Two independent DSI bus outputs are provided by
the IC.
signaling and outputs a 0 V to 5.0 V logic level corresponding
FUNCTIONAL TERMINAL DESCRIPTION
250 mA per channel. During idle state, the voltage on the DSI
bus will be very close to the VSUP voltage.
Bus Driver and Receiver
The Wave-Shaper converts the 0 to 5.0 V logic inputs from
DSIxF (frame) and DSIxS (signal) to a wave-shaped signal
on the DSIxO output, as shown in the timing diagrams in
Figure 2, page 3, and the truth table in Table 6. The Bus
Current Sense detects the current being drawn by the
device(s) on the bus during signalling (DSIxF=0). If the
current is above a set level, DSIxR will be high; otherwise, it
is low. Due to the variations in the turnaround time (tTAT) from
Internal thermal shutdown circuitry and current limit
individually protect the DSIxO outputs from shorts to battery
and ground.
Typically, the thermal shutdown occurs between 160 °C and
170 °C. If the junction temperature rises above this
temperature, the internal TxLIM bit is asserted, and the output
drivers for DSIxO are disabled by the thermal shutdown
circuitry. The output drivers remain off until the junction
temperature decreases below approximately 155 °C, at
which time the thermal shutdown circuitry turns off and the
outputs are re-enabled. Each DSIxO output has a unique
thermal sense and shutdown circuit, so a short on one
channel does not affect the other channel.
slave devices and bus delays, DSIxR should be sampled on
the falling edge of DSIxS and on the rising edge of DSIxF (for
the last return bit).
Table 6. DSI Bus Truth Table
TxLIM
DSIxF
DSIxS
DSIxR
Not Defined
Not Defined
Return Data
Return Data
0
DSIxO
Low (1.5 V)
High (4.5 V)
Unchanged
Unchanged
High Impedance
0
0
0
1
1
0
1
X
0
1
0
0
0
0
0
0
Charge Pump
The charge pump uses on-board capacitors to step the input
voltage up to the voltage needed to drive the on-board
transmitter FETs. A filter/storage capacitor is connected to
CPCAP to hold the stepped-up voltage.
0
IdleV
-0.5 V
SUP
Input Pull-ups and Pull-downs
X
X
1
1
High Impedance
Internal current pull-ups are used on the DSIxF pins and
pulldowns on the DSIxS pins. If these pins are left
unconnected, their associated DSI bus will go to the unused
(high-impedance) state.
The current for the idle state is from the supply connected to
SUP and this supply should not be current limited below
V
33790
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
CAL APPLICATIONS
TYPICAL APPLICATIONS
The 33790 is intended for use in a DSI system. This device
supplies the interface between standard logic levels and the
voltage and current required for the DSI bus. Two
independent DSI busses are supported by this part. The
33790 does not form the timing for the DSI bus. This is done
by logic embedded in a microcontroller which interfaces to
the 33790 through the MCU’s 5 V I/O pins.
A capacitor attached to CPCAP serves as a charge reservoir
for the gate drive charge pump. This circuit creates a voltage
that is higher than the source of the N-channel output
transistor. This allows turning on of the transistor enough to
prevent any significant voltage drop across it. The rest of
charge pump electronics are completely self-contained on
the IC.
33790
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
EG SUFFIX (PB-FREE)
98ASB42567B
16-PIN SOICW
33790
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
SION HISTORY
REVISION HISTORY
Revision
Date
Description of Changes
Implemented Revision History page
•
•
7.0
5/2006
Converted to Freescale format
•
•
Updated data sheet format
Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from
Maximum Ratings on page 5. Added note with instructions to obtain this information from
www.freescale.com.
8.0
9.0
11/2006
11/2006
•
•
Minor correction changes to Figure 1 and ordering information
Restated note Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC
standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels
(MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter
the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. on
page 5
10.0
12/2006
•
•
Removed watermark from page 1.
11.0
12.0
3/2008
Removed part numbers MCZ33790EG/R2, MC33790DW/R2 and added part number
MC33790HEG/R2.
Deleted references to MC68HC55.
12/2011
•
•
Updated Freescale form and style.
•
No technical changes. Revised back page. Updated document properties. Added SMARTMOS
sentence to last paragraph on page 1.
13.0
2/2014
33790
Analog Integrated Circuit Device Data
12
Freescale Semiconductor
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© 2014 Freescale Semiconductor, Inc.
Document Number: MC33790
Rev 13.0
2/2014
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