935318609051 [NXP]
RISC Microcontroller;
| 型号： | 935318609051 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 外围集成电路 |
| 文件： | 总92页 (文件大小：1085K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
K26P169M180SF5
Rev. 4, 04/2017
Kinetis K26 Sub-Family
MK26FN2M0VMD18
180 MHz ARM® Cortex®-M4F Microcontroller.
MK26FN2M0VMI18
MK26FN2M0VLQ18
MK26FN2M0CAC18R
The K26 sub-family members provide greater performance,
memory options up to 2 MB total flash and 256 KB of SRAM, as
well as higher peripheral integration with features such as Dual
USB. These devices maintain hardware and software
compatibility with the existing Kinetis family.
144 MAPBGA (MD)
13 mm x 13 mm Pitch 1 20 mm x 20 mm Pitch
144 LQFP (LQ)
This product also offers:
mm
0.5 mm
• Integration of a High Speed USB Physical Transceiver
• Greater performance flexibility with a High Speed Run
mode
• Smarter peripherals with operation in Stop modes
169 MAPBGA (MI)
169 WLCSP (AC)
9 mm x 9 mm Pitch 5.6 mm x 5.5 mm Pitch
0.65 mm 0.4 mm
Performance
• Up to 180 MHz ARM Cortex-M4 based core with DSP
System and Clocks
• Multiple low-power modes to provide power
optimization based on application requirements
• Memory protection unit with multi-master protection
• 3 to 32 MHz main crystal oscillator
instructions and Single Precision Floating Point unit
Memories and memory expansion
• Up to 2 MB program flash memory on non-FlexMemory
devices with 256 KB RAM
• 32 kHz low power crystal oscillator
• 48 MHz internal reference
• Up to 1 MB program flash memory and 256 KB of
FlexNVM on FlexMemory devices
Security
• 4 KB FlexRAM on FlexMemory devices
• FlexBus external bus interface and SDRAM controller
• Hardware random-number generator
• Supports DES, AES, SHA accelerator (CAU)
• Multiple levels of embedded flash security
Analog modules
• Two 16-bit SAR ADCs and two 12-bit DAC
• Four analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
• Voltage reference 1.2V
Timers
• Four Periodic interrupt timers
• 16-bit low-power timer
• Two 16-bit low-power timer PWM modules
• Two 8-channel motor control/general purpose/PWM
timers
Communication interfaces
• USB high-/full-/low-speed On-the-Go with on-chip high
speed transceiver
• Two 2-ch quad decoder/general purpose timers
• Real-time clock
• USB full-/low-speed OTG with on-chip transceiver
• Two CAN, three SPI and four I2C modules
• Low Power Universal Asynchronous Receiver/
Transmitter 0 (LPUART0) and five standard UARTs
• Secure Digital Host Controller (SDHC)
• I2S module
Operating Characteristics
• Voltage/Flash write voltage range:1.71 to 3.6 V
• V-Temperature range (ambient): -40 to 105°C
• C-Temperature range (ambient): -40 to 85°C
Human-machine interface
• Low-power hardware touch sensor interface (TSI)
• General-purpose input/output
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information 1
Memory
Part Number
Maximum number of I\O's
Flash
SRAM
MK26FN2M0VMD18
MK26FN2M0VLQ18
MK26FN2M0CAC18R
MK26FN2M0VMI18
2 MB
2 MB
2 MB
2 MB
256 KB
256 KB
256 KB
256 KB
100
100
116
116
1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.
Related Resources
Type
Selector
Description
Resource
Solution Advisor
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Guide
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K26P169M180SF5RM
This document.
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
Chip Errata
The chip mask set Errata provides additional or corrective information for Kinetis_K_0N65N 1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
MAPBGA 144-pin :
98ASA00222D1
QFP 144-pin: 98ASS23177W1
MAPBGA 169-pin :
98ASA00628D1
WLCSP 169-pin:
98ASA00222D1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Kinetis K26 Sub-Family
ARM® Cortex®-M4
Core
System
Memories and Memory Interfaces
Clocks
Internal
and external
watchdogs
Program
flash
Phase-
locked loop
RAM
Debug
Memory
protection
Frequency-
locked loop
FlexMemory
DSP
Cache
interfaces
Serial
Low/high
frequency
oscillators
Interrupt
Floating-
point unit
External
bus
programming
DMA
controller
interface
Internal
reference
clocks
Low-leakage
wakeup
SDRAM
controller
Security
and Integrity
Communication Interfaces
Human-Machine
Interface (HMI)
Analog
Timers
I2C
x4
16-bit ADC
x2
I2S
x1
Timers
x4 (20ch)
CRC
GPIO
Xtrinsic
touch-sensing
interface
Random
number
generator
Carrier
modulator
transmitter
Analog
comparator
x4
UART
x5
Secure
Digital
Hardware
encryption
Programmable
delay block
SPI
x3
USB LS/FS
OTG
controller
with
6-bit DAC
x4
Periodic
interrupt
timers
CAN
x2
12-bit DAC
x2
transceiver
Voltage
reference
USB LS/FS/HS
OTG
controller
with
Low power
timer
LPUART
Independent
real-time
clock
transceiver
USB DCD/
USBHSDCD
Low power
TPM x 2 (4ch)
USB voltage
regulator
Figure 1. K26 Block Diagram
Kinetis K26 Sub-Family, Rev. 4, 04/2017
3
NXP Semiconductors
Table of Contents
1 Ratings....................................................................................5
3.6 Timers..............................................................................55
3.7 Communication interfaces............................................... 55
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 6
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
3.7.1
USB Voltage Regulator Electrical
Specifications....................................................56
USB Full Speed Transceiver and High Speed
PHY specifications............................................ 57
USB DCD electrical specifications.................... 57
CAN switching specifications............................ 58
DSPI switching specifications (limited voltage
range)................................................................58
DSPI switching specifications (full voltage
3.7.2
3.7.3
3.7.4
3.7.5
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
Voltage and current operating requirements.....7
LVD and POR operating requirements............. 8
Voltage and current operating behaviors.......... 9
Power mode transition operating behaviors......10
Power consumption operating behaviors..........12
EMC radiated emissions operating behaviors...17
Designing with radiated emissions in mind....... 18
Capacitance attributes...................................... 18
3.7.6
range)................................................................60
Inter-Integrated Circuit Interface (I2C) timing....61
UART switching specifications..........................63
Low Power UART switching specifications....... 63
3.7.7
3.7.8
3.7.9
3.7.10 SDHC specifications......................................... 63
3.7.11 I2S switching specifications.............................. 65
3.8 Human-machine interfaces (HMI)....................................71
2.3 Switching specifications...................................................18
2.3.1
2.3.2
Device clock specifications............................... 18
General switching specifications.......................19
3.8.1
TSI electrical specifications...............................71
2.4 Thermal specifications.....................................................20
4 Dimensions............................................................................. 71
4.1 Obtaining package dimensions....................................... 71
5 Pinout......................................................................................72
5.1 MK26 Signal Multiplexing and Pin Assignments..............72
5.2 Recommended connection for unused analog and
2.4.1
2.4.2
Thermal operating requirements.......................20
Thermal attributes............................................. 20
3 Peripheral operating requirements and behaviors.................. 22
3.1 Core modules.................................................................. 22
3.1.1
3.1.2
Debug trace timing specifications..................... 22
JTAG electricals................................................23
digital pins........................................................................81
5.3 MK26 Pinouts.................................................................. 82
6 Ordering parts......................................................................... 86
6.1 Determining valid orderable parts....................................86
7 Part identification.....................................................................87
7.1 Description.......................................................................87
7.2 Format............................................................................. 87
7.3 Fields............................................................................... 87
7.4 Example...........................................................................88
8 Terminology and guidelines.................................................... 88
8.1 Definitions........................................................................88
8.2 Examples.........................................................................89
8.3 Typical-value conditions.................................................. 89
8.4 Relationship between ratings and operating
3.2 System modules.............................................................. 26
3.3 Clock modules................................................................. 26
3.3.1
3.3.2
3.3.3
3.3.4
MCG specifications........................................... 26
IRC48M specifications...................................... 29
Oscillator electrical specifications..................... 30
32 kHz oscillator electrical characteristics.........32
3.4 Memories and memory interfaces................................... 33
3.4.1
3.4.2
3.4.3
3.4.4
Flash (FTFE) electrical specifications............... 33
EzPort switching specifications.........................38
Flexbus switching specifications....................... 38
SDRAM controller specifications.......................41
3.5 Analog............................................................................. 44
3.5.1
3.5.2
3.5.3
3.5.4
ADC electrical specifications.............................44
CMP and 6-bit DAC electrical specifications.....48
12-bit DAC electrical characteristics................. 51
Voltage reference electrical specifications........54
requirements....................................................................90
8.5 Guidelines for ratings and operating requirements..........90
9 Revision History...................................................................... 90
4
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
• For C-
temp
—
1
varian
t: 1
• For V-
temp
varian
t :3
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
VHBM
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
Kinetis K26 Sub-Family, Rev. 4, 04/2017
5
NXP Semiconductors
General
1.4 Voltage and current operating ratings
Symbol
VDD
Description
Min.
–0.3
—
Max.
3.8
Unit
V
Digital supply voltage
IDD
Digital supply current
300
mA
V
VDIO
Digital1 input voltage,including RESET_b
Analog1 input voltage, including EXTAL32 and XTAL32
Maximum current single pin limit (digital output pins)
Analog supply voltage
–0.3
–0.3
–25
VDD + 0.3
VDD + 0.3
25
VAIO
V
ID
mA
V
VDDA
VDD – 0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
VDD + 0.3
3.63
VUSB0_DP
VUSB1_DP
VUSB0_DM
VUSB1_DM
USB0_DP input voltage
V
USB1_DP input voltage
3.63
V
USB0_DM input voltage
3.63
V
USB1_DM input voltage
3.63
V
VUSB1_VBUS USB1_VBUS detect voltage
6.0
V
VREG_IN0, USB regulator input
VREG_IN1
6.0
V
VBAT
RTC battery supply voltage
–0.3
3.8
V
1. Digital pins have a general purpose I/O port assigned (e.g. PTA0). Analog pins do not have an associated general
purpose I/O port.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
6
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
General
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
1.71
Max.
3.6
3.6
0.1
0.1
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
V
V
VBAT
VIH
RTC battery supply voltage
Input high voltage
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.71 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.71 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICDIO
Input hysteresis
Digital1 input pin negative DC injection current
(except RTC_WAKEUP pins) — single pin
0.06 × VDD
-5
—
—
V
2
2
mA
• VIN < VSS-0.3V
IICAIO
Analog1 input pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
mA
mA
-5
—
—
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pin
-25
Table continues on the next page...
Kinetis K26 Sub-Family, Rev. 4, 04/2017
7
NXP Semiconductors
General
Table 1. Voltage and current operating requirements (continued)
Symbol
Description
• Negative current injection
Min.
Max.
Unit
Notes
VODPU
VRAM
Pseudo Open drain pullup voltage level
VDD voltage required to retain RAM
VDD
1.2
VDD
—
V
V
V
3
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT
—
1. Digital pins have a general purpose I/O port assigned (e.g. PTA0). Analog pins do not have an associated general
purpose I/O port.
2. All digital and analog I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VSS-0.3V, a current limiting resistor is required. The minimum negative DC
injection current limiting resistor value is calculated as R=(-0.3-VIN)/|IICDIO| or R=(-0.3-VIN)/|IICAIO|. The actual resistor
should be an order of magnitude higher to tolerate transient voltages.
3. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
8
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
General
Notes
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VOH
Output high voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤VDD ≤ 2.7 V, IOH = -5mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
Output high voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20mA
VDD – 0.5
—
—
—
—
V
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10mA VDD – 0.5
IOHT
Output high current total for all ports
—
—
100
mA
V
VOH_RTC_WAKEUP Output high voltage— normal drive pad
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -5 mA
VBAT – 0.5
VBAT – 0.5
—
—
V
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -2.5
mA
IOH_RTC_WAKEUP Output high current total for
RTC_WAKEUP pins
—
—
100
mA
VOL
Output low voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5 mA
—
—
—
—
0.5
0.5
V
V
Output low voltage — high drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
—
—
—
0.5
0.5
V
V
IOLT
Output low current total for all ports
—
—
100
mA
V
VOL_RTC_WAKEUP Output low voltage— normal drive pad
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 5 mA
—
—
0.5
0.5
V
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 2.5mA
IOL_RTC_WAKEUP Output low current total for
RTC_WAKEUPpins
—
—
—
100
0.5
mA
µA
IIN
Input leakage current, analog and digital
pins
0.002
1
Table continues on the next page...
Kinetis K26 Sub-Family, Rev. 4, 04/2017
9
NXP Semiconductors
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
• VSS ≤ VIN ≤ VDD
Min.
Typ.
Max.
Unit
Notes
IOZ_RTC_WAKEUP Hi-Z (off-state) leakage current (per
RTC_WAKEUP pin)
—
—
0.25
µA
RPU
RPD
Internal pullup resistors
20
20
—
—
50
50
kΩ
kΩ
2
3
Internal pulldown resistors
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx –> RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 100MHz
• Bus clock = 50MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode=FEI
Table 5. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
—
300
µs
—
—
—
—
—
—
—
—
172
172
94
µs
µs
µs
µs
µs
µs
µs
µs
• VLLS0 –> RUN
• VLLS1 –> RUN
• VLLS2 –> RUN
• VLLS3 –> RUN
• LLS2 –> RUN
• LLS3 –> RUN
• VLPS –> RUN
• STOP –> RUN
94
5.8
5.8
5.4
5.4
10
NXP Semiconductors
Kinetis K26 Sub-Family, Rev. 4, 04/2017
General
Table 6. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
1051
IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KH 32 kHz internal reference clock (IRC) adder.
52
52
52
52
52
52
µA
uA
Measured by entering STOP mode with the
z
32 kHz IRC enabled.
IEREFSTEN4MH External 4 MHz crystal clock adder.
206
228
237
245
251
258
Measured by entering STOP or VLPS mode
z
with the crystal enabled.
IEREFSTEN32K External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured by entering all
modes with the crystal enabled.
Hz
nA
440
440
490
490
510
510
511
22
490
490
490
490
560
560
520
22
540
540
540
540
560
560
545
22
560
560
560
560
560
560
556
22
570
570
570
570
610
610
563
22
580
580
680
680
680
680
576
22
VLLS1
VLLS3
LLS2
LLS3
VLPS
STOP
I48MIRC
ICMP
48MHz IRC
µA
µA
CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP
enabled using the 6-bit DAC and a single
external input for compare. Includes 6-bit
DAC power consumption.
IRTC
RTC peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
RTC_CR[OSCE] bit and the RTC ALARM
set for 1 minute. Includes ERCLK32K (32
kHz external crystal) power consumption.
432
357
388
475
532
810
nA
µA
IUART
UART peripheral adder measured by placing
the device in STOP or VLPS mode with
selected clock source waiting for RX data at
115200 baud rate. Includes selected clock
source power consumption.
66
66
66
66
66
66
MCGIRCLK (4 MHz internal reference clock)
OSCERCLK (4 MHz external crystal)
214
45
234
45
246
45
254
45
260
45
268
45
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx
mode.
µA
µA
IADC
ADC peripheral adder combining the
366
366
366
366
366
366
measured values at VDD and VDDA by placing
Kinetis K26 Sub-Family, Rev. 4, 04/2017
11
NXP Semiconductors
General
Table 6. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
50 70
Unit
-40
25
85
1051
the device in STOP or VLPS mode. ADC is
configured for low power mode using the
internal clock and continuous conversions.
1. Applicable to LQFP and BGA packages only
2.2.5 Power consumption operating behaviors
NOTE
The maximum values represent characterized results
equivalent to the mean plus three times the standard deviation
(mean + 3 sigma)
Table 7. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
2
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
—
—
32.3
32.4
71.03
71.81
mA
mA
• @ 1.8V
• @ 3.0V
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
3, 4
—
50.5
89.58
mA
• @ 1.8V
• @ 3.0V
• @ 25°C
—
—
—
50.6
60.5
69.7
55.95
79.20
99.85
mA
mA
mA
• @ 85°C
• @ 105°C
IDD_RUNC Run mode current in compute operation - 120
5
6
—
28.5
67.74
mA
MHz core / 24 MHz flash / bus clock disabled,
O
code of while(1) loop executing from flash
• at 3.0 V
IDD_HSRUN Run mode current — all peripheral clocks
disabled, code executing from flash
—
—
47.2
47.3
91.25
91.62
mA
mA
• @ 1.8V
• @ 3.0V
IDD_HSRUN Run mode current — all peripheral clocks
enabled, code executing from flash
7, 4
—
71.4
103.58
mA
Table continues on the next page...
12
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NXP Semiconductors
General
Notes
Table 7. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
• @ 1.8V
71.5
84.5
93.3
79.13
106.75
115.08
mA
mA
mA
—
—
—
• @ 3.0V
• @ 25°C
• @ 85°C
• @ 105°C
IDD_HSRUN HSRun mode current in compute operation – 168
—
42.9
91.97
mA
5
MHz core/ 28 MHz flash / bus clock disabled,
CO
code of while(1) loop executing from flash at 3.0V
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
—
—
—
16.9
35
45.2
62.81
9.56
mA
mA
mA
mA
8
8
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
all peripheral clocks enabled
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
1.1
2
9
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
9.88
10
11
IDD_VLPRC Very-low-power run mode current in compute
—
986
9.47
μA
operation - 4 MHz core / 1 MHz flash / bus clock
O
disabled, LPTMR running with 4 MHz internal
reference clock
• at 3.0 V
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
—
—
0.690
1.5
9.25
mA
mA
12
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks enabled
10.00
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
—
—
—
—
0.791
3.8
2.39
6.91
mA
mA
mA
mA
• @ 70°C
6.8
11.44
18.91
• @ 85°C
• @ 105°C
13.2
IDD_VLPS Very-low-power stop mode current at 3.0 V
—
—
—
—
202
353.77
2464.54
4642.45
8949.06
μA
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
1400
2700
5100
• @ 85°C
• @ 105°C
IDD_LLS3 Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
—
—
—
—
9.0
76.3
169.1
402
16.5
μA
μA
μA
μA
88.63
• @ 85°C
• @ 105°C
181.46
656.08
Table continues on the next page...
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13
NXP Semiconductors
General
Table 7. Power consumption operating behaviors (continued)
Symbol Description
IDD_LLS2 Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
Min.
Typ.
Max.
Unit
Notes
—
5.7
9.7
μA
μA
• @ 70°C
—
—
—
41.3
92.4
229
55.80
120.01
276.81
• @ 85°C
• @ 105°C
μA
μA
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
—
—
—
—
5.5
46.3
104
249
7.31
μA
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
58.33
196.02
380.77
• @ 85°C
• @ 105°C
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
—
—
—
—
2.7
3.24
18.72
37.49
84.77
μA
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
13.1
29.6
76.6
• @ 85°C
• @ 105°C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
—
—
—
—
0.847
6.5
1.48
11.31
28.31
81.78
μA
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
16.2
46.7
• @ 85°C
• @ 105°C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
—
—
—
—
0.551
6.3
.65
μA
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
7.12
17.1
49.6
20.02
53.68
• @ 85°C
• @ 105°C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
—
—
—
—
0.254
6.3
0.445
10.99
27.58
85.27
μA
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
15.8
48.7
• @ 85°C
• @ 105°C
IDD_VBAT Average current with RTC and 32kHz disabled at
3.0 V
—
—
—
—
0.19
0.49
1.11
2.2
0.22
0.64
1.4
μA
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
• @ 85°C
• @ 105°C
3.2
Table continues on the next page...
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NXP Semiconductors
General
Table 7. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VBAT Average current when CPU is not accessing RTC
registers
13
• @ 1.8V
0.68
1.2
—
—
—
0.8
1.56
5.3
• @ –40 to 25°C
• @ 70°C
μA
μA
μA
3.6
• @ 105°C
• @ 3.0V
• @ –40 to 25°C
• @ 70°C
0.81
1.45
2.5
—
—
—
—
0.96
1.89
3.46
6.33
μA
μA
μA
μA
• @ 85°C
• @ 105°C
4.3
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. MCG configured for PEE mode.
6. 168 MHz core and system clock, 56 MHz bus and FlexBus clock, and 28 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
7. 168 MHz core and system clock, 56 MHz bus and FlexBus clock, and 28 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled.
8. 120 MHz core and system clock, 60MHz bus clock, and FlexBus. MCG configured for PEE mode.
9. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
10. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
11. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high,
optimized for balanced.
12. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
13. Includes 32kHz oscillator current and RTC operation.
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
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15
NXP Semiconductors
General
Figure 3. Run mode supply current vs. core frequency
16
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NXP Semiconductors
General
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
Typ.
Unit
Notes
(MHz)
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
23
27
28
14
K
dBμV
dBμV
dBμV
dBμV
—
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,
150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits -
Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM
Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic
Kinetis K26 Sub-Family, Rev. 4, 04/2017
17
NXP Semiconductors
General
application code. The reported emission level is the value of the maximum measured emission, rounded up to the next
whole number, from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = MHz, fBUS = MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions.
1. Go to nxp.com
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol
fSYS
Description
Min.
Max.
Unit
Notes
High Speed run mode
System and core clock
—
180
MHz
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS
System and core clock
—
120
—
MHz
MHz
System and core clock when Full Speed USB in
operation
20
fSYS_USBHS System and core clock when High Speed USB in
operation
100
—
MHz
fBUS
Bus clock
—
—
—
60
60
28
MHz
MHz
MHz
FB_CLK
fFLASH
FlexBus clock
Flash clock
Table continues on the next page...
18
NXP Semiconductors
Kinetis K26 Sub-Family, Rev. 4, 04/2017
General
Notes
Table 10. Device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
fLPTMR
LPTMR clock
—
25
MHz
VLPR mode1
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
—
—
—
—
4
4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
FB_CLK
fFLASH
FlexBus clock
4
Flash clock
1
fERCLK
fLPTMR_pin
External reference clock
LPTMR clock
16
25
8
fFlexCAN_ERCLK FlexCAN external reference clock
fI2S_MCLK
fI2S_BCLK
I2S master clock
I2S bit clock
12.5
4
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, timers, and I2C signals.
Table 11. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous
path
100
50
—
—
ns
ns
ns
3
3
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous
path
External reset pulse width (digital glitch filter
disabled)
100
2
—
—
Mode select (EZP_CS) hold time after reset
deassertion
Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew enabled
4
• 1.71 ≤ VDD ≤ 2.7V
—
—
25
15
ns
ns
• 2.7 ≤ VDD ≤ 3.6V
• Slew disabled
Table continues on the next page...
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19
NXP Semiconductors
General
Table 11. General switching specifications (continued)
Symbol
Description
• 1.71 ≤ VDD ≤ 2.7V
Min.
Max.
Unit
Notes
—
7
ns
• 2.7 ≤ VDD ≤ 3.6V
—
7
ns
Port rise and fall time (low drive strength)
• Slew enabled
5
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
25
15
ns
ns
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
7
7
ns
ns
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can
be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TJ
Die junction temperature
°C
–40
125
• For BGA and LQFP package
TJ
TA
TA
Die junction temperature
• For CSP package
°C
°C
°C
–40
–40
–40
95
105
85
Ambient temperature
1
1
• For BGA and LQFP package
Ambient temperature
• For CSP package
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RθJA x chip power dissipation.
20
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NXP Semiconductors
General
Notes
2.4.2 Thermal attributes
Board
type
Symbol Descripti 144 LQFP
on
144
169
169
Unit
MAPBGA MAPBGA WLCSP
Single-
layer (1s)
RθJA
Thermal
45
36
36
48
29
38
38
48.3
°C/W
1
1
1
resistance,
junction to
ambient
(natural
convection)
Four-layer RθJA
(2s2p)
Thermal
21.9
30
24
°C/W
°C/W
resistance,
junction to
ambient
(natural
convection)
Single-
layer (1s)
RθJMA
Thermal
resistance,
junction to
ambient
(200 ft./
39.8
min. air
speed)
Four-layer RθJMA
(2s2p)
Thermal
resistance,
junction to
ambient
(200 ft./
30
25
18.6
19.5
°C/W
1
min. air
speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal
resistance,
junction to
board
24
9
16
9
14.4
8.2
21.4
0.1
°C/W
°C/W
°C/W
2
3
4
Thermal
resistance,
junction to
case
Thermal
characteriz
ation
2
2
0.2
0.2
parameter,
junction to
package
top outside
center
(natural
convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
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21
NXP Semiconductors
Peripheral operating requirements and behaviors
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 Debug trace timing specifications
Table 13. Debug trace operating behaviors
Symbol
Tcyc
Twl
Description
Min.
Max.
Unit
MHz
ns
Clock period
Frequency dependent
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
Twh
Tr
ns
—
—
1.5
1.0
ns
Tf
3
ns
Ts
—
—
ns
Th
Data hold
ns
TRACECLK
T
r
T
f
T
wh
T
wl
T
cyc
Figure 5. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 6. Trace data specifications
22
NXP Semiconductors
Kinetis K26 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
3.1.2 JTAG electricals
Table 14. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
25
50
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
20
10
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
J4
J5
TCLK rise and fall times
—
20
2.0
—
—
8
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
—
—
28
25
—
—
19
17
—
—
J6
J7
J8
J9
J10
J11
J12
J13
J14
1
—
—
100
8
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Table 15. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
20
40
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
ns
50
—
Table continues on the next page...
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NXP Semiconductors
Peripheral operating requirements and behaviors
Table 15. JTAG full voltage range electricals (continued)
Symbol
Description
• JTAG and CJTAG
Min.
Max.
Unit
25
—
ns
• Serial Wire Debug
12.5
—
ns
J4
J5
TCLK rise and fall times
—
20
2.0
—
—
8
3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
J6
—
J7
30.6
25
J8
J9
—
J10
J11
J12
J13
J14
1.0
—
—
100
8
—
19.0
17.0
—
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
—
J2
J4
J3
J3
TCLK (input)
J4
Figure 7. Test clock input timing
24
NXP Semiconductors
Kinetis K26 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 8. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 9. Test Access Port timing
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NXP Semiconductors
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 16. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
fints_t
Iints
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
Internal reference (slow clock) current
—
—
20
—
µA
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
0.6
%fdco
1
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
0.2
0.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
0.5
0.3
2
%fdco
%fdco
1
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
1.5
fintf_ft
fintf_t
Iintf
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
3
4
—
5
MHz
MHz
µA
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
—
25
Internal reference (fast clock) current
—
—
Table continues on the next page...
26
NXP Semiconductors
Kinetis K26 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
floc_low Loss of external clock minimum frequency —
(3/5) x
fints_t
—
—
kHz
RANGE = 00
ext clk freq: above (3/5)fint never reset
ext clk freq: between (2/5)fint and (3/5)fint maybe
reset (phase dependency)
ext clk freq: below (2/5)fint always reset
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
ext clk freq: above (16/5)fint never reset
ext clk freq: between (15/5)fint and (16/5)fint
maybe reset (phase dependency)
ext clk freq: below (15/5)fint always reset
FLL
ffll_ref
FLL reference frequency range
31.25
16.0
—
39.0625
26.66
kHz
fdco_ut
DCO output
Low range
23.04
MHz
2
frequency range
— untrimmed
(DRS=00, DMX32=0)
640 × fints_ut
Mid range
32.0
48.0
46.08
69.12
92.16
26.35
52.70
79.09
105.44
53.32
79.99
106.65
30.50
60.99
91.53
122.02
(DRS=01, DMX32=0)
1280 × fints_ut
Mid-high range
(DRS=10, DMX32=0)
1920 × fints_ut
High range
64.0
(DRS=11, DMX32=0)
2560 × fints_ut
Low range
18.3
(DRS=00, DMX32=1)
732 × fints_ut
Mid range
36.6
(DRS=01, DMX32=1)
1464 × fints_ut
Mid-high range
(DRS=10, DMX32=1)
2197 × fints_ut
54.93
73.23
High range
(DRS=11, DMX32=1)
2929 × fints_ut
Table continues on the next page...
Kinetis K26 Sub-Family, Rev. 4, 04/2017
27
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20
20.97
25
MHz
3, 4
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
95.98
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
5, 6
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
—
180
150
—
—
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
7
PLL
fpll_ref
PLL reference frequency range
8
180
90
90
—
—
—
16
360
180
180
—
MHz
MHz
fvcoclk_2x VCO output frequency
fvcoclk
PLL output frequency
—
—
MHz
MHz
fvcoclk_90 PLL quadrature output frequency
Ipll
PLL operating current
8
8
9
2.8
3.6
mA
mA
• VCO @ 184 MHz (fosc_hi_1 = 32 MHz,
fpll_ref = 8 MHz, VDIV multiplier = 23)
Ipll
PLL operating current
—
—
• VCO @ 360 MHz (fosc_hi_1 = 32 MHz,
fpll_ref = 8 MHz, VDIV multiplier = 45)
Jcyc_pll
PLL period jitter (RMS)
• fvco = 180 MHz
—
—
100
75
—
—
ps
ps
• fvco = 360 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
• fvco = 180 MHz
9
—
—
600
300
—
—
ps
ps
• fvco = 360 MHz
Table continues on the next page...
28
NXP Semiconductors
Kinetis K26 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol Description
Min.
4.47
—
Typ.
—
Max.
Unit
%
Notes
Dunl
Lock exit frequency tolerance
Lock detector detection time
5.97
150 × 10-6
+ 1075(1/
tpll_lock
—
s
10
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. This applies when SCTRIM at value (0x80) and SCFTRIM control bit at value (0x0).
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3.3.2 IRC48M specifications
Table 17. IRC48M specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Notes
Supply voltage
IDD48M
firc48m
Supply current
520
48
μA
Internal reference frequency
—
—
MHz
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at
1
low voltage (VDD=1.71V-1.89V) over full
—
—
0.4
0.5
1.0
1.5
%firc48m
temperature
• Regulator disable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=
0)
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=
1)
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over 0—70°C
• Regulator enable
1
1
—
—
0.2
0.4
0.5
1.0
%firc48m
(USB_CLK_RECOVER_IRC_EN[REG_EN]=
1)
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over full
temperature
%firc48m
Table continues on the next page...
Kinetis K26 Sub-Family, Rev. 4, 04/2017
29
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 17. IRC48M specifications (continued)
Symbol
Description
• Regulator enable
Min.
Typ.
Max.
Unit
Notes
(USB_CLK_RECOVER_IRC_EN[REG_EN]=
1)
Δfirc48m_cl Closed loop total deviation of IRC48M frequency
—
—
0.1
%fhost
2
3
over voltage and temperature
Jcyc_irc48m Period Jitter (RMS)
—
—
35
2
150
3
ps
μs
tirc48mst
Startup time
1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard
deviation (mean 3 sigma)
2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It
is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover
function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).
3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
clock by one of the following settings:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1, or
• MCG_C7[OSCSEL]=10, or
• SIM_SOPT2[PLLFLLSEL]=11
3.3.3 Oscillator electrical specifications
3.3.3.1 Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
600
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
7.5
500
650
2.5
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
3.25
Table continues on the next page...
30
NXP Semiconductors
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Peripheral operating requirements and behaviors
Table 18. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
• 24 MHz
—
4
—
mA
• 32 MHz
Cx
Cy
RF
EXTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
XTAL load capacitance
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain
mode (HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C, Internal capacitance = 20 pf
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
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NXP Semiconductors
Peripheral operating requirements and behaviors
3.3.3.2 Oscillator frequency specifications
Table 19. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high-
frequency mode (low range)
3
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal Input clock frequency (external clock mode)
tdc_extal Input clock duty cycle (external clock mode)
—
40
—
—
50
50
60
—
MHz
%
1, 2
3, 4
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.3.4 32 kHz oscillator electrical characteristics
3.3.4.1 32 kHz oscillator DC electrical specifications
Table 20. 32kHz oscillator DC electrical specifications
Symbol
VBAT
RF
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
Internal feedback resistor
100
—
MΩ
Table continues on the next page...
32
NXP Semiconductors
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Peripheral operating requirements and behaviors
Table 20. 32kHz oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
5
7
pF
1
Vpp
Peak-to-peak amplitude of oscillation
—
0.6
—
V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
3.3.4.2 32 kHz oscillator frequency specifications
Table 21. 32 kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
32.768
—
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
1
2
fec_extal32 Externally provided input clock frequency
vec_extal32 Externally provided input clock amplitude
—
—
kHz
mV
700
VBAT
2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VBAT
.
3.4 Memories and memory interfaces
3.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 22. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm8 Program Phrase high-voltage time
thversscr Erase Flash Sector high-voltage time
thversblk256k Erase Flash Block high-voltage time for 256 KB
thversblk512k Erase Flash Block high-voltage time for 512 KB
—
13
113
ms
ms
ms
1
1
1
—
208
416
1808
3616
—
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NXP Semiconductors
Peripheral operating requirements and behaviors
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 23. Flash command timing specifications
Symbol Description
Read 1s Block execution time
Min.
Typ.
Max.
Unit
Notes
trd1blk256k
trd1blk512k
• 256 KB data flash
—
—
—
—
1.0
1.8
ms
ms
• 512 KB program flash
trd1sec4k Read 1s Section execution time (4 KB flash)
—
—
—
—
—
—
—
90
100
95
μs
μs
μs
μs
1
1
1
tpgmchk
trdrsrc
Program Check execution time
Read Resource execution time
Program Phrase execution time
Erase Flash Block execution time
• 256 KB data flash
40
tpgm8
150
2
tersblk256k
tersblk512k
—
—
220
435
1850
3700
ms
ms
• 512 KB program flash
tersscr
Erase Flash Sector execution time
—
—
15
5
115
—
ms
ms
2
tpgmsec1k Program Section execution time (1 KB flash)
Read 1s All Blocks execution time
trd1allx
trd1alln
• FlexNVM devices
—
—
—
—
5.9
6.7
ms
ms
• Program flash only devices
trdonce
Read Once execution time
—
—
—
—
—
90
30
—
μs
μs
ms
μs
1
tpgmonce Program Once execution time
tersall
Erase All Blocks execution time
Verify Backdoor Access Key execution time
Swap Control execution time
• control code 0x01
1750
—
14,800
30
2
1
tvfykey
tswapx01
tswapx02
tswapx04
tswapx08
tswapx10
—
—
—
—
—
200
90
90
—
—
μs
μs
μs
μs
μs
• control code 0x02
150
150
30
• control code 0x04
• control code 0x08
• control code 0x10
90
150
Program Partition for EEPROM execution time
• 32 KB EEPROM backup
tpgmpart32k
tpgmpart256k
—
—
70
78
—
—
ms
ms
• 256 KB EEPROM backup
Set FlexRAM Function execution time:
• Control Code 0xFF
tsetramff
tsetram32k
tsetram64k
—
—
—
70
0.8
1.3
—
μs
ms
ms
• 32 KB EEPROM backup
• 64 KB EEPROM backup
1.2
1.9
Table continues on the next page...
34
NXP Semiconductors
Kinetis K26 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
Table 23. Flash command timing specifications (continued)
Symbol Description
tsetram128k • 128 KB EEPROM backup
tsetram256k
Min.
Typ.
Max.
Unit
Notes
—
2.4
3.1
ms
• 256 KB EEPROM backup
—
4.5
5.5
ms
Byte-write to FlexRAM execution time:
• 32 KB EEPROM backup
teewr8b32k
teewr8b64k
teewr8b128k
teewr8b256k
—
—
—
—
385
475
1700
2000
2350
3250
μs
μs
μs
μs
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
650
1000
16-bit write to FlexRAM execution time:
• 32 KB EEPROM backup
teewr16b32k
teewr16b64k
teewr16b128k
teewr16b256k
—
—
—
—
385
475
1700
2000
2350
3250
μs
μs
μs
μs
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
650
1000
teewr32bers 32-bit write to erased FlexRAM location
execution time
—
360
1500
μs
32-bit write to FlexRAM execution time:
teewr32b32k
teewr32b64k
teewr32b128k
teewr32b256k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
—
630
810
2000
2250
2650
3500
μs
μs
μs
μs
1200
1900
1. Assumes 25MHz or greater flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 24. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage flash
programming operation
—
3.5
7.5
mA
IDD_ERS
Average current adder during high voltage flash
erase operation
—
1.5
4.0
mA
3.4.1.4 Reliability specifications
Table 25. NVM reliability specifications
Symbol Description
Min.
Program Flash
Table continues on the next page...
Typ.1
Max.
Unit
Notes
Kinetis K26 Sub-Family, Rev. 4, 04/2017
35
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 25. NVM reliability specifications (continued)
Symbol Description
Min.
5
Typ.1
Max.
—
Unit
years
years
cycles
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
50
20
100
50 K
—
10 K
—
2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k Data retention after up to 1 K cycles
nnvmcycd Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
nnvmcycee Cycling endurance for EEPROM backup
Write endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
20 K
2
3
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree2k
nnvmwree8k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 2,048
• EEPROM backup to FlexRAM ratio = 8,192
140 K
1.26 M
5 M
400 K
3.2 M
12.8 M
50 M
—
—
—
—
—
writes
writes
writes
writes
writes
20 M
80 M
200 M
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the
cycling endurance of the FlexNVM and the allocated EEPROM backup per subsystem. Minimum and typical values
assume all 16-bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance.
3.4.1.5 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set
size can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFE to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that
can be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout
the entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
36
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Peripheral operating requirements and behaviors
EEPROM – 2 × EEESPLIT × EEESIZE
Writes_subsystem =
× Write_efficiency × nnvmcycee
where
• Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on
DEPART; entered with the Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program
Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycee — EEPROM-backup cycling endurance
16/32-bit
8-bit
Ratio of EEPROM Backup to FlexRAM
Figure 11. EEPROM backup writes to FlexRAM
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NXP Semiconductors
Peripheral operating requirements and behaviors
3.4.2 EzPort switching specifications
Table 26. EzPort full voltage range switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
Unit
V
Operating voltage
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
5
5
—
ns
—
ns
2
—
ns
5
—
ns
—
0
14
—
ns
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
ns
—
12
ns
EZP_CK
EP2
EP3
EP4
EZP_CS
EP9
EP8
EP7
EZP_Q (output)
EZP_D (input)
EP5
EP6
Figure 12. EzPort Timing Diagram
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NXP Semiconductors
Kinetis K26 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
3.4.3 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are
given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK
frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing numbers indicate when data is latched or driven onto the
external bus, relative to the Flexbus output clock (FB_CLK). All other timing
relationships can be derived from these values.
Table 27. Flexbus limited voltage range switching specifications
Num
Description
Min.
2.7
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
—
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
1/FB_CLK
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
11.8
—
ns
1.0
ns
1
2
11.9
0.0
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
FB_ALE, and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 28. Flexbus full voltage range switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
1/FB_CLK
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
12.6
—
ns
1.0
ns
1
2
12.5
0
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
FB_ALE, and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
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NXP Semiconductors
Peripheral operating requirements and behaviors
Read Timing Parameters
S0
S1
S2
S3
S0
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB5
FB3
Address
FB4
FB2
Address
Data
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
S1
S0
S2
S3
S0
Figure 13. FlexBus read timing diagram
40
NXP Semiconductors
Kinetis K26 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
Write Timing Parameters
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB2
FB3
Address
Address
Data
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 14. FlexBus write timing diagram
3.4.4 SDRAM controller specifications
Following figure shows SDRAM read cycle.
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NXP Semiconductors
Peripheral operating requirements and behaviors
0
1
2
3
4
5
6
7
8
9
10
11
12
13
D0
CLKOUT
D3
D1
Row
Column
A[23:0]
D4
SRAS
D2
1
SCAS
D4
DRAMW
D5
2
D[31:0]
SDRAM_CS[1:0]
BS[3:0]
D6
D4
NOP
ACTV
NOP
READ
PRE
1
2
DACR[CASL] = 2
D[31:16] for 144-pin packages
Figure 15. SDRAM read timing diagram
Table 29. SDRAM Timing (Full voltage range)
NUM
Characteristic 1
Symbol
1.71
MIn
Max
Unit
Operating voltage
3.6
V
Frequency of operation
—
CLKOUT
MHz
D0
D1
D2
D3
D4
D5
D6
D73
D83
Clock period
1/CLKOUT
tCHDAV
tCHDCV
tCHDAI
—
-
ns
2
CLKOUT high to SDRAM address valid
CLKOUT high to SDRAM control valid
CLKOUT high to SDRAM address invalid
CLKOUT high to SDRAM control invalid
SDRAM data valid to CLKOUT high
CLKOUT high to SDRAM data invalid
CLKOUT high to SDRAM data valid
CLKOUT high to SDRAM data invalid
11.2
ns
ns
ns
ns
ns
ns
ns
ns
11.1
1.0
1.0
12.0
1.0
-
-
tCHDCI
-
tDDVCH
tCHDDI
tCHDDVW
tCHDDIW
-
-
12.0
-
1.0
1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
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Peripheral operating requirements and behaviors
2. CLKOUT is same as FB_CLK, maximum frequency can be 60 MHz
3. D7 and D8 are for write cycles only.
Table 30. SDRAM Timing (Limited voltage range)
NUM
Characteristic 1
Symbol
2.7
MIn
3.6
Max
Unit
Operating voltage
V
Frequency of operation
—
1/CLKOUT
tCHDAV
tCHDCV
tCHDAI
CLKOUT
MHz
D0
D1
D2
D3
D4
D5
D6
D73
D83
Clock period
—
-
ns
2
CLKOUT high to SDRAM address valid
CLKOUT high to SDRAM control valid
CLKOUT high to SDRAM address invalid
CLKOUT high to SDRAM control invalid
SDRAM data valid to CLKOUT high
CLKOUT high to SDRAM data invalid
CLKOUT high to SDRAM data valid
CLKOUT high to SDRAM data invalid
11.1
ns
ns
ns
ns
ns
ns
ns
ns
11.1
1.0
1.0
11.3
1.0
-
-
tCHDCI
-
tDDVCH
tCHDDI
tCHDDVW
tCHDDIW
-
-
11.1
-
1.0
1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2. CLKOUT is same as FB_CLK, maximum frequency can be 60 MHz
3. D7 and D8 are for write cycles only.
Following figure shows an SDRAM write cycle.
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NXP Semiconductors
Peripheral operating requirements and behaviors
0
1
2
3
4
5
6
7
8
9
10
11
12
D0
CLKOUT
D3
D1
Row
Column
A[23:0]
SRAS
D2
1
SCAS
D4
DRAMW
D7
2
D[31:0]
D8
D4
SDRAM_CS[1:0]
D4
D2
BS[3:0]
D4
ACTV
NOP
WRITE
NOP
PALL
1
2
DACR[CASL]=2
D[31:16] for 144-pin packages
Figure 16. SDRAM write timing diagram
3.5 Analog
3.5.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 31 and Table 32 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
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Peripheral operating requirements and behaviors
3.5.1.1 16-bit ADC operating conditions
Table 31. 16-bit ADC operating conditions
Symbol Description
VDDA Supply voltage
ΔVDDA Supply voltage
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
Absolute
—
—
2
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
ΔVSSA
Ground voltage Delta to VSS (VSS – VSSA
)
0
2
VREFH
ADC reference
voltage high
VDDA
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VREFL
VREFL
—
—
31/32 *
VREFH
—
—
VREFH
CADIN
Input
capacitance
—
—
8
4
10
5
pF
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
—
3
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
24
MHz
MHz
4
4
5
ADC conversion 16-bit mode
clock frequency
12.0
ADC conversion ≤ 13-bit modes
rate
20.000
—
1200
kS/s
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
5
37.037
—
461.467
kS/s
rate
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
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NXP Semiconductors
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 17. ADC input impedance equivalency diagram
3.5.1.2 16-bit ADC electrical characteristics
Table 32. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
mA
Notes
IDDA_ADC Supply current
—
3
ADC asynchronous
clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
4.0
5.2
6.2
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
2.4
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
0.7
0.2
–1.1 to
+1.9
–0.3 to
0.5
INL
Integral non-linearity
• 12-bit modes
—
1.0
–2.7 to
+1.9
LSB4
5
Table continues on the next page...
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NXP Semiconductors
Kinetis K26 Sub-Family, Rev. 4, 04/2017
Peripheral operating requirements and behaviors
Table 32. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
—
0.5
–0.7 to
+0.5
• <12-bit modes
5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4
LSB4
VADIN = VDDA
Quantization error
0.5
ENOB Effective number of 16-bit differential mode
6
bits
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
bits
bits
dB
• Avg = 4
Signal-to-noise plus See ENOB
SINAD
6.02 × ENOB + 1.76
distortion
THD
Total harmonic
distortion
16-bit differential mode
• Avg = 32
7
7
dB
dB
—
-94
-85
—
16-bit single-ended mode
• Avg = 32
—
—
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
—
—
dB
dB
82
78
95
90
16-bit single-ended mode
• Avg = 32
EIL
Input leakage error
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
8
VTEMP25 Temp sensor voltage 25 °C
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
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NXP Semiconductors
Peripheral operating requirements and behaviors
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 18. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
Averaging of 4 samples
Averaging of 32 samples
11.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 19. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
48
NXP Semiconductors
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Peripheral operating requirements and behaviors
3.5.2 CMP and 6-bit DAC electrical specifications
Table 33. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
50
250
—
7
—
0.5
200
600
40
V
V
Output low
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
20
ns
tDLS
80
ns
—
μs
IDAC6b
INL
—
—
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
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Peripheral operating requirements and behaviors
0.08
0.07
0.06
0.05
0.04
0.03
HYSTCTR
Setting
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 20. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 21. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.5.3 12-bit DAC electrical characteristics
3.5.3.1 12-bit DAC operating requirements
Table 34. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
1.13
—
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
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Peripheral operating requirements and behaviors
3.5.3.2 12-bit DAC operating behaviors
Table 35. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
150
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
100
15
700
200
30
μA
μs
μs
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
0.7
1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
AC
Temperature coefficient offset voltage
Temperature coefficient gain error
Offset aging coefficient
3.7
—
μV/C
%FSR/C
μV/yr
Ω
6
0.000421
—
—
100
250
Rop
SR
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
—
V/μs
• High power (SPHP
• Low power (SPLP
)
1.2
1.7
—
—
)
0.05
0.12
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
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6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC
set to 0x800, temperature range is across the full range of the device
8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 22. Typical INL error vs. digital code
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1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 23. Offset at half scale vs. temperature
3.5.4 Voltage reference electrical specifications
Table 36. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Supply voltage
Temperature
Min.
Max.
Unit
Notes
3.6
V
Operating temperature
range of the device
°C
CL
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range
of the device.
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Table 37. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.190
1.195
1.200
V
1
nominal VDDA and temperature=25C
Voltage reference output — factory trim
Voltage reference output — user trim
Voltage reference trim step
Vout
Vout
1.1584
1.193
—
—
—
1.2376
1.197
—
V
V
1
1
1
1
Vstep
Vtdrift
0.5
—
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
80
Ac
Ibg
Aging coefficient
—
—
—
—
400
80
uV/yr
µA
—
1
Bandgap only current
ΔVLOAD Load regulation
• current = 1.0 mA
µV
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
—
100
35
µs
Tchop_osc_st Internal bandgap start-up delay with chop
ms
—
1
oscillator enabled
up
Vvdrift
Voltage drift (Vmax -Vmin across the full
voltage range)
—
2
—
mV
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 38. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
Table 39. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim
1.173
1.225
V
3.6 Timers
See General switching specifications.
3.7 Communication interfaces
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3.7.1 USB Voltage Regulator Electrical Specifications
Table 40. USB VREG electrical specifications
Symbol
Description
Min.
Typ.1
Max.
Unit
Notes
VREG_IN0 Regulator selectable input supply voltages
VREG_IN1
2.7
—
5.5
V
2
IDDon
Quiescent current — Run mode, load current
equal zero, input supply (VREG_IN*) > 3.6 V
μA
μA
—
—
—
—
VREG_IN0
VREG_IN1
157
157
2
IDDstby
Quiescent current — Standby mode, load
current equal zero
—
—
—
—
VREG_IN0
VREG_IN1
IDDoff
2
Quiescent current — Shutdown mode
VREG_IN0
VREG_IN1
• VREG_IN*= 5.0 V and temperature=25 °C
—
—
680
920
—
—
—
nA
ILOADrun
ILOADstby
Maximum load current — Run mode
—
150
1
mA
mA
mV
3
4
Maximum load current — Standby mode
—
—
VDROPOUT Regulator drop-out voltage — Run mode at
maximum load current with inrush current limit
disabled
300
—
—
VREG_OUT Regulator programmable output target voltage
— Selected input supply > programmed output
target voltage + VDROPOUT
3
3.3
2.8
3.6
3.6
V
V
2.1
• Run mode
• Standby mode
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
ILIM
Short circuit current
Inrush current limit
—
350
—
—
mA
mA
5
IINRUSH
40
100
6, 7, 8,
9, 10
1. Typical values assume the selected input supply is 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operation range is 2.7 V to 5.5 V; tolerance voltage is up to 6 V.
3. 150mA is inclusive of the run mode current of the on-chip USB modules. Available load outside of the chip depends on
USB operation and device power dissipation limits.
4. The target voltage for the regulator is programmable, accounting for the range of the max and min values
5. Current limit disabled.
6. Current limit should be disabled after the powers have stabilized to allow full functionality of the regulator.
7. Limited Characterization
8. IINRUSH with VREGINx=4.0 V to 5.5 V
9. The minimum value of IINRUSH is stated for operation when only one of VREG_IN0 / VREG_IN1 is powered, or when
VREG_IN0 and VREG_IN1 both have the same voltage level. When VREG_IN0 and VREG_IN1 are operated at
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different voltage levels with the selected VREG_IN lower than the non-selected VREG_IN, the minumum value of
IINRUSH may decrease to a lower value.
10. Total current load on startup should be less than IINRUSH min over full input voltage range of the regulator.
3.7.2 USB Full Speed Transceiver and High Speed PHY
specifications
This section describes the USB0 port Full Speed/Low Speed transceiver and USB1
port USB-PHY High Speed Phy parameters. The high speed phy is capable of full and
low speed signalling as well.
The USB0 (FS/LS Transceiver) and USB1 ((USB HS/FS/LS) meet the electrical
compliance requirements defined in the Universal Serial Bus Revision 2.0
Specification with the amendments below.
• USB ENGINEERING CHANGE NOTICE
• Title: 5V Short Circuit Withstand Requirement Change
• Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE
• Title: Pull-up/Pull-down resistors
• Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
• Title: Suspend Current Limit Changes
• Applies to: Universal Serial Bus Specification, Revision 2.0
• On-The-Go and Embedded Host Supplement to the USB Revision 2.0
Specification
• Revision 2.0 version 1.1a July 27, 2012
• Battery Charging Specification (available from USB-IF)
• Revision 1.2 (including errata and ECNs through March 15, 2012), March 15,
2012
USB1_VBUS pin is a detector function which is 5v tolerant and complies with the
above specifications without needing any external voltage division components.
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3.7.3 USB DCD electrical specifications
Table 41. USB DCD electrical specifications
Symbol
VDP_SRC
Description
Min.
Typ.
Max.
Unit
,
USB_DP and USB_DM source voltages (up to 250
0.5
—
0.7
V
VDM_SRC μA)
VLGC
IDP_SRC
IDM_SINK
Threshold voltage for logic high
0.8
7
—
10
2.0
13
V
USB_DP source current
μA
μA
,
USB_DM and USB_DP sink currents
50
100
150
IDP_SINK
RDM_DWN D- pulldown resistance for data pin contact detect
VDAT_REF Data detect voltage
14.25
0.25
—
24.8
0.4
kΩ
V
0.33
3.7.4 CAN switching specifications
See General switching specifications.
3.7.5 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to
the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 42. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
30
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
1.0
15.8
0
15.0
—
ns
ns
ns
ns
—
—
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1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 24. DSPI classic SPI timing — master mode
Table 43. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
Frequency of operation
15 1
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
23.0
—
ns
ns
2.7
7.0
—
—
—
ns
—
ns
13
13
ns
ns
1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with
continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example,
when bus clock is 60MHz, SPI clock should not be greater than 10MHz.
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DSPI_SS
DS10
DS9
DSPI_SCK
DS15
DS12
DS16
DS11
(CPOL=0)
First data
Last data
DSPI_SOUT
Data
Data
DS13
DS14
First data
Last data
DSPI_SIN
Figure 25. DSPI classic SPI timing — slave mode
3.7.6 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 44. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
15
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
—
(tSCK/2) - 4 (tSCK/2) + 4
ns
(tBUS x 2) −
4
—
ns
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
1.0
15.8
0
15
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
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DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 26. DSPI classic SPI timing — master mode
Table 45. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
1.71
Frequency of operation
—
7.5
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
23.1
—
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
ns
ns
2.6
7.0
—
—
—
ns
—
ns
13.0
13.0
ns
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 27. DSPI classic SPI timing — slave mode
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3.7.7 Inter-Integrated Circuit Interface (I2C) timing
Table 46. I 2C timing
Characteristic
Symbol
Standard Mode
Minimum Maximum
100
Fast Mode
Unit
Minimum
Maximum
400
SCL Clock Frequency
fSCL
0
0
kHz
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.25
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
0.6
Data hold time for I2C bus devices
tHD; DAT
tSU; DAT
tr
01
2504
—
3.452
—
03
1002, 5
20 +0.1Cb
20 +0.1Cb
0.6
0.91
—
µs
ns
ns
ns
µs
µs
Data set-up time
6
5
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
1000
300
—
300
300
—
tf
—
tSU; STO
tBUF
4
Bus free time between STOP and
START condition
4.7
—
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
6. Cb = total capacitance of the one bus line in pF.
Table 47. I 2C 1 Mbps timing
Characteristic
Symbol
fSCL
Minimum
Maximum
Unit
MHz
µs
SCL Clock Frequency
0
11
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time for I2C bus devices
Data set-up time
tLOW
tHIGH
0.5
0.26
0.26
0
—
—
µs
µs
µs
µs
ns
ns
tSU; STA
tHD; DAT
tSU; DAT
tr
—
—
50
—
, 2
Rise time of SDA and SCL signals
20 +0.1Cb
120
Table continues on the next page...
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Table 47. I 2C 1 Mbps timing (continued)
Characteristic
Symbol
tf
Minimum
Maximum
Unit
ns
2
Fall time of SDA and SCL signals
20 +0.1Cb
120
—
Set-up time for STOP condition
tSU; STO
tBUF
0.26
0.5
0
µs
Bus free time between STOP and START condition
—
µs
Pulse width of spikes that must be suppressed by
the input filter
tSP
50
ns
1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins
across the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tSU; STO
HD; STA
S
SR
P
S
tHD; DAT
tHIGH
Figure 28. Timing definition for devices on the I2C bus
3.7.8 UART switching specifications
See General switching specifications.
3.7.9 Low Power UART switching specifications
See General switching specifications.
3.7.10 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 48. SDHC full voltage range switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Table continues on the next page...
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Table 48. SDHC full voltage range switching specifications
(continued)
Num
Symbol
Description
Min.
Max.
Unit
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
0
0
400
25\50
20\50
400
—
kHz
MHz
MHz
kHz
ns
Clock frequency (SD\SDIO full speed\high speed)
Clock frequency (MMC full speed\high speed)
Clock frequency (identification mode)
Clock low time
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
—
ns
Clock rise time
—
—
3
ns
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid) -5 8.6 8.3
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
ns
SD7
SD8
tISU
tIH
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
Table 49. SDHC limited voltage range switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
0
0
400
25\50
20\50
400
—
kHz
MHz
MHz
kHz
ns
Clock frequency (SD\SDIO full speed\high speed)
Clock frequency (MMC full speed\high speed)
Clock frequency (identification mode)
Clock low time
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
—
ns
Clock rise time
—
—
3
ns
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid) -5 7.6 8.3
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
ns
SD7
SD8
tISU
tIH
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
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SD3
SD6
SD2
SD1
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
SD7
SD8
Figure 29. SDHC timing
3.7.11 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] =
0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or
the frame sync (I2S_FS) shown in the figures below.
Table 50. I2S master mode timing (limited voltage range)
Num
Description
Min.
2.7
40
45%
80
45%
—
Max.
3.6
—
Unit
Operating voltage
V
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
55%
—
MCLK period
ns
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
I2S_BCLK to I2S_TXD invalid
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
55%
15
BCLK period
ns
ns
ns
ns
ns
ns
0
—
—
15
0
—
15
0
—
—
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S1
S2
S2
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S3
S4
S4
S5
S7
S6
S10
S9
S7
S8
S8
S9
S10
I2S_RXD
Figure 30. I2S timing — master mode
Table 51. I2S slave mode timing (limited voltage range)
Num
Description
Operating voltage
Min.
2.7
80
45%
4.5
2
Max.
Unit
3.6
—
V
S11
S12
S13
S14
S15
S16
S17
S18
S19
I2S_BCLK cycle time (input)
ns
I2S_BCLK pulse width high/low (input)
I2S_FS input setup before I2S_BCLK
I2S_FS input hold after I2S_BCLK
55%
—
MCLK period
ns
ns
ns
ns
ns
ns
ns
—
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
I2S_RXD setup before I2S_BCLK
—
20
—
0
4.5
2
—
I2S_RXD hold after I2S_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
25
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
66
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Peripheral operating requirements and behaviors
S11
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S12
S15
S16
S13
S14
S19
S15
S16
S15
S16
S17
S18
I2S_RXD
Figure 31. I2S timing — slave modes
3.7.11.1 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 52. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK (as an input) pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
45%
80
55%
—
MCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
15
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
Kinetis K26 Sub-Family, Rev. 4, 04/2017
67
NXP Semiconductors
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 32. I2S/SAI timing — master modes
Table 53. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
80
3.6
—
V
S11
S12
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
S14
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5
2
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
23.1
—
ns
ns
ns
ns
ns
4.5
2
—
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
—
25
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
68
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 33. I2S/SAI timing — slave modes
3.7.11.2 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 54. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
62.5
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
45%
250
55%
—
MCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
55%
45
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
45
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
Kinetis K26 Sub-Family, Rev. 4, 04/2017
69
NXP Semiconductors
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 34. I2S/SAI timing — master modes
Table 55. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
250
3.6
—
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
S12
S13
S14
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
5
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
56.5
—
ns
ns
ns
ns
ns
30
5
—
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
—
72
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
70
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Dimensions
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 35. I2S/SAI timing — slave modes
3.8 Human-machine interfaces (HMI)
3.8.1 TSI electrical specifications
Table 56. TSI electrical specifications
Symbol
TSI_RUNF
TSI_RUNV
Description
Min.
—
Typ.
100
—
Max.
Unit
µA
Fixed power consumption in run mode
—
Variable power consumption in run mode
(depends on oscillator's current selection)
1.0
128
µA
TSI_EN
TSI_DIS
Power consumption in enable mode
Power consumption in disable mode
TSI analog enable time
—
—
100
1.2
66
—
—
µA
µA
µs
pF
V
TSI_TEN
—
—
TSI_CREF
TSI_DVOLT
TSI reference capacitor
—
1.0
—
—
Voltage variation of VP & VM around nominal
values
0.19
1.03
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
Kinetis K26 Sub-Family, Rev. 4, 04/2017
71
NXP Semiconductors
Pinout
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
144-pin LQFP
Then use this document number
98ASS23177W
144-pin MAPBGA
169-pin MAPBGA
169-pin WLCSP
98ASA00222D
98ASA00628D
98ASA00640D
5 Pinout
5.1 MK26 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
The pin functions SDRAM_D12, SDRAM_D13,
SDRAM_D14, and SDRAM_D15 don't exist on 144 LQFP
and 144 MAPBGA packages.
169
169
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EZPORT
CSP
BGA LQFP BGA
C11
A13
B12
B13
—
A1
B1
—
1
2
D3
D2
—
PTE0
ADC1_
SE4a
ADC1_
SE4a
PTE0
SPI1_PCS1 UART1_TX SDHC0_D1 TRACE_
CLKOUT
I2C1_SDA
RTC_
CLKOUT
PTE1/
LLWU_P0
ADC1_
SE5a
ADC1_
SE5a
PTE1/
LLWU_P0
SPI1_
SOUT
UART1_RX SDHC0_D0 TRACE_D3 I2C1_SCL
SPI1_SIN
—
—
3
PTE2/
LLWU_P1
ADC1_
SE6a
ADC1_
SE6a
PTE2/
LLWU_P1
SPI1_SCK
SPI1_SIN
SPI1_SCK
SPI1_SIN
UART1_
CTS_b
SDHC0_
DCLK
TRACE_D2
TRACE_D1
TRACE_D2
TRACE_D1
—
—
PTE3
ADC1_
SE7a
ADC1_
SE7a
PTE3
UART1_
RTS_b
SDHC0_
CMD
SPI1_
SOUT
C1
D1
D1
E4
PTE2/
LLWU_P1
ADC1_
SE6a
ADC1_
SE6a
PTE2/
LLWU_P1
UART1_
CTS_b
SDHC0_
DCLK
—
4
PTE3
ADC1_
SE7a
ADC1_
SE7a
PTE3
UART1_
RTS_b
SDHC0_
CMD
SPI1_
SOUT
F9
—
G5
C3
E1
5
6
7
E5
H3
E3
VDD
VSS
VDD
VDD
VSS
VSS
C12
PTE4/
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX SDHC0_D3 TRACE_D0
SPI1_PCS2 UART3_RX SDHC0_D2
LLWU_P2
D11
D2
8
E2
PTE5
DISABLED
PTE5
FTM3_CH0
72
NXP Semiconductors
Kinetis K26 Sub-Family, Rev. 4, 04/2017
Pinout
169
169
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EZPORT
CSP
BGA LQFP BGA
C13
E10
D12
D13
F10
E11
E12
E2
E3
E4
F3
F4
G4
H4
9
E1
F4
F3
F2
F1
G4
G3
PTE6/
LLWU_P16
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTE6/
LLWU_P16
SPI1_PCS3 UART3_
CTS_b
I2S0_MCLK
I2S0_RXD0
FTM3_CH1 USB0_
SOF_OUT
10
11
12
13
14
15
PTE7
PTE7
UART3_
RTS_b
FTM3_CH2
PTE8
PTE8
I2S0_RXD1
I2S0_TXD1
I2C3_SDA
I2C3_SCL
I2S0_RX_
FS
LPUART0_
TX
FTM3_CH3
PTE9/
LLWU_P17
PTE9/
LLWU_P17
I2S0_RX_
BCLK
LPUART0_
RX
FTM3_CH4
PTE10/
LLWU_P18
PTE10/
LLWU_P18
I2S0_TXD0 LPUART0_
CTS_b
FTM3_CH5 USB1_ID
FTM3_CH6
PTE11
PTE11
I2S0_TX_
FS
LPUART0_
RTS_b
PTE12
PTE12
I2S0_TX_
BCLK
FTM3_CH7
E13
G8
G6
G8
H3
16
17
—
E6
F7
—
VDD
VDD
VSS
VDD
VSS
VSS
G9
PTE16
ADC0_
SE4a
ADC0_
SE4a
PTE16
SPI0_PCS0 UART2_TX FTM_
CLKIN0
FTM0_
FLT3
TPM_
CLKIN0
F11
G10
F12
F5
F6
F7
—
—
—
—
—
—
PTE17/
ADC0_
ADC0_
SE5a
PTE17/
LLWU_P19
SPI0_SCK
UART2_RX FTM_
LPTMR0_
ALT3
TPM_
CLKIN1
LLWU_P19 SE5a
PTE18/ ADC0_
LLWU_P20 SE6a
CLKIN1
ADC0_
SE6a
PTE18/
LLWU_P20 SOUT
SPI0_
UART2_
CTS_b
I2C0_SDA
PTE19
ADC0_
SE7a
ADC0_
SE7a
PTE19 SPI0_SIN
UART2_
RTS_b
I2C0_SCL
CMP3_OUT
F13
G13
H13
G11
G3
G1
F1
18
19
20
21
F6
H1
H2
G1
VSS
VSS
VSS
USB0_DP
USB0_DM
USB0_DP
USB0_DM
USB0_DP
USB0_DM
G2
VREG_
OUT
VREG_
OUT
VREG_
OUT
G12
H12
J12
J13
K13
K12
F2
H2
K1
J1
22
23
24
25
26
27
G2
J2
VREG_IN0
VREG_IN1
VREG_IN0
DISABLED
VREG_IN0
VREG_IN1
USB1_VSS
USB1_DP
USB1_DM
K2
J1
USB1_VSS DISABLED
USB1_DP
USB1_DM
DISABLED
DISABLED
DISABLED
H1
J2
K1
L1
USB1_
VBUS
USB1_
VBUS
J11
K11
L13
L1
M1
M2
—
—
—
—
—
—
ADC1_DP1 ADC1_DP1 ADC1_DP1
ADC1_DM1 ADC1_DM1 ADC1_DM1
ADC0_DP0/ ADC0_DP0/ ADC0_DP0/
ADC1_DP3 ADC1_DP3 ADC1_DP3
M13
L12
L2
28
29
L2
ADC0_
DM0/
ADC0_
DM0/
ADC0_
DM0/
ADC1_DM3 ADC1_DM3 ADC1_DM3
N1
M1
ADC1_DP0/ ADC1_DP0/ ADC1_DP0/
ADC0_DP3 ADC0_DP3 ADC0_DP3
Kinetis K26 Sub-Family, Rev. 4, 04/2017
73
NXP Semiconductors
Pinout
169
169
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EZPORT
CSP
BGA LQFP BGA
M12
N2
30
M2
ADC1_
DM0/
ADC1_
DM0/
ADC1_
DM0/
ADC0_DM3 ADC0_DM3 ADC0_DM3
L11
M11
N12
N13
H11
J3
K3
K4
J4
31
32
33
34
35
H5
G5
G6
H6
K3
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
M3
ADC1_
SE16/
ADC1_
SE16/
ADC1_
SE16/
CMP2_IN2/ CMP2_IN2/ CMP2_IN2/
ADC0_
SE22
ADC0_
SE22
ADC0_
SE22
K10
L10
L3
36
37
J3
ADC0_
SE16/
ADC0_
SE16/
ADC0_
SE16/
CMP1_IN2/ CMP1_IN2/ CMP1_IN2/
ADC0_
SE21
ADC0_
SE21
ADC0_
SE21
N3
M3
VREF_
OUT/
VREF_
OUT/
VREF_
OUT/
CMP1_IN5/ CMP1_IN5/ CMP1_IN5/
CMP0_IN5/ CMP0_IN5/ CMP0_IN5/
ADC1_
SE18
ADC1_
SE18
ADC1_
SE18
M10
N11
M4
N4
38
39
L3
L4
DAC0_
OUT/
DAC0_
OUT/
DAC0_
OUT/
CMP1_IN3/ CMP1_IN3/ CMP1_IN3/
ADC0_
SE23
ADC0_
SE23
ADC0_
SE23
DAC1_
OUT/
DAC1_
OUT/
DAC1_
OUT/
CMP0_IN4/ CMP0_IN4/ CMP0_IN4/
CMP2_IN3/ CMP2_IN3/ CMP2_IN3/
ADC1_
SE23
ADC1_
SE23
ADC1_
SE23
J10
M5
—
L5
RTC_
WAKEUP_
B
RTC_
WAKEUP_
B
RTC_
WAKEUP_
B
H10
H9
J9
L4
L5
K5
L6
K6
N5
N6
M6
J6
—
—
—
—
—
40
41
42
—
—
—
—
NC
NC
NC
NC
NC
NC
—
NC
NC
NC
N10
K9
M9
N9
L9
—
NC
NC
NC
—
NC
NC
NC
M7
M6
L6
—
XTAL32
EXTAL32
VBAT
NC
XTAL32
EXTAL32
VBAT
NC
XTAL32
EXTAL32
VBAT
NC
H8
J8
J5
—
NC
NC
NC
74
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Pinout
169
169
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EZPORT
CSP
BGA LQFP BGA
K8
H7
N8
G7
N7
L7
43
44
45
—
—
VDD
VDD
VDD
VSS
VSS
VSS
M4
PTE24
ADC0_
SE17
ADC0_
SE17
PTE24
CAN1_TX
CAN1_RX
UART4_TX
UART4_RX
I2C0_SCL
I2C0_SDA
EWM_
OUT_b
M8
L8
K7
K8
46
47
K5
K4
PTE25/
LLWU_P21 SE18
ADC0_
ADC0_
SE18
PTE25/
LLWU_P21
EWM_IN
PTE26/
CLKOUT32
K
DISABLED
PTE26/
CLKOUT32
K
UART4_
CTS_b
RTC_
CLKOUT
USB0_
CLKIN
J7
L8
48
J4
PTE27
DISABLED
DISABLED
PTE27
UART4_
RTS_b
K7
N7
M7
N8
49
50
H4
J5
PTE28
PTA0
PTE28
PTA0
JTAG_
TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1
UART0_
CTS_b/
UART0_
COL_b
FTM0_CH5
LPUART0_
CTS_b
JTAG_
TCLK/
EZP_CLK
SWD_CLK
M7
L7
N9
M9
51
52
J6
PTA1
PTA2
JTAG_TDI/
EZP_DI
TSI0_CH2
TSI0_CH3
PTA1
PTA2
UART0_RX FTM0_CH6 I2C3_SDA
LPUART0_
RX
JTAG_TDI
EZP_DI
K6
JTAG_
TDO/
UART0_TX FTM0_CH7 I2C3_SCL
LPUART0_
TX
JTAG_
TDO/
EZP_DO
TRACE_
SWO/
TRACE_
SWO
EZP_DO
J6
M8
53
K7
PTA3
JTAG_
TMS/
SWD_DIO
TSI0_CH4
TSI0_CH5
PTA3
UART0_
RTS_b
FTM0_CH0
LPUART0_
RTS_b
JTAG_
TMS/
SWD_DIO
K6
N6
L9
54
55
L7
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
FTM0_CH1
FTM0_CH2
NMI_b
EZP_CS_b
N10
M8
PTA5
DISABLED
PTA5
USB0_
CLKIN
CMP2_OUT I2S0_TX_
BCLK
JTAG_
TRST_b
M6
H6
N5
H5
H8
56
57
58
E7
G7
J7
VDD
VSS
VDD
VDD
VSS
VSS
M10
PTA6
DISABLED
PTA6
PTA7
PTA8
FTM0_CH3
FTM0_CH4
FTM1_CH0
CLKOUT
TRACE_
CLKOUT
L6
L10
K9
59
60
J8
PTA7
PTA8
ADC0_
SE10
ADC0_
SE10
TRACE_D3
M5
K8
ADC0_
SE11
ADC0_
SE11
FTM1_QD_ TRACE_D2
PHA/
TPM1_CH0
J5
K10
N11
61
62
L8
PTA9
DISABLED
DISABLED
PTA9
FTM1_CH1
FTM2_CH0
FTM1_QD_ TRACE_D1
PHB/
TPM1_CH1
K5
M9
PTA10/
LLWU_P22
PTA10/
LLWU_P22
FTM2_QD_ TRACE_D0
PHA/
TPM2_CH0
Kinetis K26 Sub-Family, Rev. 4, 04/2017
75
NXP Semiconductors
Pinout
169
169
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EZPORT
CSP
BGA LQFP BGA
N4
M4
L5
M11
L12
L11
K13
63
64
65
66
L9
K9
J9
PTA11/
LLWU_P23
DISABLED
PTA11/
LLWU_P23
FTM2_CH1
I2C2_SDA
FTM2_QD_
PHB/
TPM2_CH1
PTA12
CMP2_IN0
CMP2_IN1
DISABLED
CMP2_IN0
CMP2_IN1
PTA12
CAN0_TX
CAN0_RX
FTM1_CH0
FTM1_CH1
I2C2_SCL
I2C2_SDA
I2C2_SCL
I2S0_TXD0 FTM1_QD_
PHA/
TPM1_CH0
PTA13/
LLWU_P4
PTA13/
LLWU_P4
I2S0_TX_
FS
FTM1_QD_
PHB/
TPM1_CH1
N3
L10
PTA14
PTA14
SPI0_PCS0 UART0_TX
I2S0_RX_
BCLK
I2S0_TXD1
L4
K4
K12
J13
67
68
L11
K10
PTA15
PTA16
CMP3_IN1
CMP3_IN2
CMP3_IN1
CMP3_IN2
PTA15
PTA16
SPI0_SCK
UART0_RX
I2S0_RXD0
SPI0_
SOUT
UART0_
CTS_b/
UART0_
COL_b
I2S0_RX_
FS
I2S0_RXD1
L3
J12
69
K11
PTA17
ADC1_
SE17
ADC1_
SE17
PTA17
SPI0_SIN
UART0_
RTS_b
I2S0_MCLK
M3
M2
N1
N12
M12
N13
70
71
72
E8
G8
VDD
VDD
VDD
VSS
VSS
VSS
M12
PTA18
EXTAL0
EXTAL0
PTA18
PTA19
FTM0_
FLT2
FTM_
CLKIN0
TPM_
CLKIN0
N2
M13
73
M11
PTA19
XTAL0
XTAL0
FTM1_
FLT0
FTM_
CLKIN1
LPTMR0_
ALT1
TPM_
CLKIN1
M1
K3
L13
K11
74
75
L12
K12
RESET_b
PTA24
RESET_b
CMP3_IN4
RESET_b
CMP3_IN4
PTA24
PTA25
PTA26
PTA27
FB_A15/
SDRAM_
D15
FB_A29
FB_A28
FB_A27
FB_A26
J4
J3
L2
J11
J10
H13
76
77
78
J12
J11
J10
PTA25
PTA26
PTA27
CMP3_IN5
DISABLED
DISABLED
CMP3_IN5
FB_A14/
SDRAM_
D14
FB_A13/
SDRAM_
D13
FB_A12/
SDRAM_
D12
L1
K2
K1
H12
H11
H10
79
80
—
H12
H11
—
PTA28
PTA29
PTA30
DISABLED
DISABLED
DISABLED
PTA28
PTA29
PTA30
FB_A25
FB_A24
CAN0_TX
CAN0_RX
FB_A11/
SDRAM_
D11
H5
J9
—
—
PTA31
DISABLED
PTA31
FB_A10/
SDRAM_
D10
76
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Pinout
169
169
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EZPORT
CSP
BGA LQFP BGA
H4
G13
G12
G11
G10
81
82
83
84
H10
H9
PTB0/
LLWU_P5
ADC0_SE8/ ADC0_SE8/ PTB0/
ADC1_SE8/ ADC1_SE8/ LLWU_P5
I2C0_SCL
FTM1_CH0
SDRAM_
CAS_b
FTM1_QD_
PHA/
TPM1_CH0
TSI0_CH0
TSI0_CH0
J2
PTB1
PTB2
PTB3
ADC0_SE9/ ADC0_SE9/ PTB1
ADC1_SE9/ ADC1_SE9/
I2C0_SDA
I2C0_SCL
I2C0_SDA
FTM1_CH1
SDRAM_
RAS_b
FTM1_QD_
PHB/
TPM1_CH1
TSI0_CH6
TSI0_CH6
J1
G12
G11
ADC0_
SE12/
TSI0_CH7
ADC0_
SE12/
TSI0_CH7
PTB2
PTB3
UART0_
RTS_b
SDRAM_
WE
FTM0_
FLT3
H3
ADC0_
SE13/
ADC0_
SE13/
UART0_
CTS_b/
UART0_
COL_b
SDRAM_
CS0_b
FTM0_
FLT0
TSI0_CH8
TSI0_CH8
G7
G6
H2
—
—
—
—
85
—
—
VSS
VSS
VDD
VSS
VDD
VDD
PTB4
H9
G10
ADC1_
SE10
ADC1_
SE10
PTB4
PTB5
PTB6
SDRAM_
CS1_b
FTM1_
FLT0
H1
G5
F13
F12
86
87
G9
PTB5
PTB6
ADC1_
SE11
ADC1_
SE11
FTM2_
FLT0
F12
ADC1_
SE12
ADC1_
SE12
FB_AD23/
SDRAM_
D23
G4
G3
G2
G1
F5
F4
F3
F11
F10
F9
88
89
90
91
92
—
—
F11
F10
F9
PTB7
ADC1_
SE13
ADC1_
SE13
PTB7
FB_AD22/
SDRAM_
D22
PTB8
DISABLED
DISABLED
PTB8
UART3_
RTS_b
FB_AD21/
SDRAM_
D21
PTB9
PTB9
SPI1_PCS1 UART3_
CTS_b
FB_AD20/
SDRAM_
D20
G9
E12
E11
—
PTB10
PTB11
PTB12
PTB13
ADC1_
SE14
ADC1_
SE14
PTB10
PTB11
PTB12
PTB13
SPI1_PCS0 UART3_RX
FB_AD19/
SDRAM_
D19
FTM0_
FLT1
E13
E12
E11
ADC1_
SE15
ADC1_
SE15
SPI1_SCK
UART3_TX
FB_AD18/
SDRAM_
D18
FTM0_
FLT2
DISABLED
DISABLED
UART3_
RTS_b
FTM1_CH0 FTM0_CH4 FB_A9/
FTM1_CH1 FTM0_CH5 FB_A8/
FB_A7/
FTM1_QD_
SDRAM_D9 PHA/
TPM1_CH0
—
UART3_
CTS_b
FTM1_QD_
SDRAM_D8 PHB/
TPM1_CH1
F2
F1
—
E10
E9
—
—
—
93
—
—
PTB14
PTB15
VSS
DISABLED
DISABLED
VSS
PTB14
PTB15
CAN1_TX
CAN1_RX
SDRAM_D7
FB_A6/
SDRAM_D6
H7
VSS
Kinetis K26 Sub-Family, Rev. 4, 04/2017
77
NXP Semiconductors
Pinout
169
169
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EZPORT
CSP
BGA LQFP BGA
—
—
94
95
F5
VDD
VDD
TSI0_CH9
VDD
TSI0_CH9
E1
F8
E10
PTB16
PTB16
SPI1_
SOUT
UART0_RX FTM_
CLKIN0
FB_AD17/
SDRAM_
D17
EWM_IN
TPM_
CLKIN0
E2
E3
E4
E5
D1
D2
D3
C1
C2
D4
D13
D12
D11
D10
D9
96
97
E9
PTB17
PTB18
PTB19
PTB20
PTB21
PTB22
PTB23
PTC0
TSI0_CH10 TSI0_CH10 PTB17
TSI0_CH11 TSI0_CH11 PTB18
TSI0_CH12 TSI0_CH12 PTB19
SPI1_SIN
UART0_TX FTM_
CLKIN1
FB_AD16/
SDRAM_
D16
EWM_
OUT_b
TPM_
CLKIN1
D12
D11
D10
D9
CAN0_TX
CAN0_RX
SPI2_PCS0
SPI2_SCK
FTM2_CH0 I2S0_TX_
BCLK
FB_AD15/
SDRAM_
A23
FTM2_QD_
PHA/
TPM2_CH0
98
FTM2_CH1 I2S0_TX_
FS
FB_OE_b
FTM2_QD_
PHB/
TPM2_CH1
99
DISABLED
DISABLED
DISABLED
DISABLED
PTB20
PTB21
PTB22
PTB23
PTC0
FB_AD31/
SDRAM_
D31
CMP0_OUT
CMP1_OUT
CMP2_OUT
CMP3_OUT
I2S0_TXD1
I2S0_TXD0
100
101
102
103
104
105
FB_AD30/
SDRAM_
D30
C13
C12
B13
B12
A13
C12
C11
B12
B11
A12
SPI2_
SOUT
FB_AD29/
SDRAM_
D29
SPI2_SIN
SPI0_PCS5
FB_AD28/
SDRAM_
D28
ADC0_
SE14/
ADC0_
SE14/
SPI0_PCS4 PDB0_
EXTRG
USB0_
SOF_OUT
FB_AD14/
SDRAM_
A22
TSI0_CH13 TSI0_CH13
PTC1/
LLWU_P6
ADC0_
SE15/
ADC0_
SE15/
PTC1/
LLWU_P6
SPI0_PCS3 UART1_
RTS_b
FTM0_CH0 FB_AD13/
SDRAM_
A21
TSI0_CH14 TSI0_CH14
PTC2
ADC0_
SE4b/
ADC0_
SE4b/
PTC2
SPI0_PCS2 UART1_
CTS_b
FTM0_CH1 FB_AD12/
I2S0_TX_
FS
SDRAM_
A20
CMP1_IN0/ CMP1_IN0/
TSI0_CH15 TSI0_CH15
B1
A12
106
A11
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT
I2S0_TX_
BCLK
F6
E6
A1
C11
H6
107
108
109
H8
—
VSS
VDD
VSS
VSS
VDD
VDD
B11
A9
PTC4/
DISABLED
PTC4/
SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11/
CMP1_OUT
LLWU_P8
LLWU_P8
SDRAM_
A19
B2
C3
A11
A10
110
111
D8
C8
PTC5/
LLWU_P9
DISABLED
CMP0_IN0
PTC5/
LLWU_P9
SPI0_SCK
SPI0_
LPTMR0_
ALT2
I2S0_RXD0 FB_AD10/
CMP0_OUT FTM0_CH2
I2S0_MCLK
SDRAM_
A18
PTC6/
LLWU_P10
CMP0_IN0
PTC6/
LLWU_P10 SOUT
PDB0_
EXTRG
I2S0_RX_
BCLK
FB_AD9/
SDRAM_
A17
78
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Pinout
169
169
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EZPORT
CSP
BGA LQFP BGA
D5
C4
A2
B3
B10
C10
C9
112
113
114
115
B8
A8
D7
C7
PTC7
CMP0_IN1
CMP0_IN1
PTC7
SPI0_SIN
USB0_
SOF_OUT
I2S0_RX_
FS
FB_AD8/
SDRAM_
A16
PTC8
ADC1_
SE4b/
CMP0_IN2
ADC1_
SE4b/
CMP0_IN2
PTC8
PTC9
PTC10
FTM3_CH4 I2S0_MCLK FB_AD7/
SDRAM_
A15
PTC9
ADC1_
SE5b/
CMP0_IN3
ADC1_
SE5b/
CMP0_IN3
FTM3_CH5 I2S0_RX_
BCLK
FB_AD6/
SDRAM_
A14
FTM2_
FLT0
A8
PTC10
PTC11/
ADC1_
SE6b
ADC1_
SE6b
I2C1_SCL
I2C1_SDA
FTM3_CH6 I2S0_RX_
FS
FB_AD5/
SDRAM_
A13
D6
C5
A9
B9
116
117
B7
A7
ADC1_
ADC1_
SE7b
PTC11/
LLWU_P11
FTM3_CH7 I2S0_RXD1 FB_RW_b
LLWU_P11 SE7b
PTC12
PTC13
PTC14
PTC15
DISABLED
PTC12
PTC13
PTC14
PTC15
UART4_
RTS_b
FTM_
CLKIN0
FB_AD27/
SDRAM_
D27
FTM3_
FLT0
TPM_
CLKIN0
A3
B4
A4
B8
C8
D8
118
119
120
D6
C6
B6
DISABLED
DISABLED
DISABLED
UART4_
CTS_b
FTM_
CLKIN1
FB_AD26/
SDRAM_
D26
TPM_
CLKIN1
UART4_RX
UART4_TX
FB_AD25/
SDRAM_
D25
FB_AD24/
SDRAM_
D24
F7
E7
A5
—
—
121
122
123
—
—
VSS
VSS
VSS
VDD
VDD
VDD
E8
A6
PTC16
DISABLED
PTC16
PTC17
PTC18
CAN1_RX
CAN1_TX
UART3_RX
UART3_TX
FB_CS5_b/
FB_TSIZ1/
FB_BE23_
16_BLS15_
8_b/
SDRAM_
DQM2
B5
C6
E7
D7
124
125
D5
C5
PTC17
PTC18
DISABLED
DISABLED
FB_CS4_b/
FB_TSIZ0/
FB_BE31_
24_BLS7_
0_b/
SDRAM_
DQM3
UART3_
RTS_b
FB_TBST_
b/
FB_CS2_b/
FB_BE15_
8_BLS23_
16_b/
SDRAM_
DQM1
Kinetis K26 Sub-Family, Rev. 4, 04/2017
79
NXP Semiconductors
Pinout
169
169
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EZPORT
CSP
BGA LQFP BGA
B6
C7
126
B5
PTC19
DISABLED
PTC19
UART3_
CTS_b
FB_CS3_b/ FB_TA_b
FB_BE7_0_
BLS31_24_
b/
SDRAM_
DQM0
A6
D7
E8
A7
B7
C7
D8
B7
A7
E6
D6
C6
B6
A6
—
—
—
—
—
—
—
—
A5
PTC24
PTC25
PTC26
PTC27
PTC28
PTC29
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTC24
PTC25
PTC26
PTC27
PTC28
PTC29
LPUART0_
TX
FB_A5/
SDRAM_D5
LPUART0_
RX
FB_A4/
SDRAM_D4
—
LPUART0_
CTS_b
FB_A3/
SDRAM_D3
—
LPUART0_
RTS_b
FB_A2/
SDRAM_D2
—
I2C3_SDA
I2C3_SCL
FB_A1/
SDRAM_D1
—
FB_A0/
SDRAM_D0
127
PTD0/
LLWU_P12
PTD0/
LLWU_P12
SPI0_PCS0 UART2_
RTS_b
FTM3_CH0 FB_ALE/
FB_CS1_b/
FB_TS_b
A8
B8
A5
A4
128
129
D4
C4
PTD1
ADC0_
SE5b
ADC0_
SE5b
PTD1
SPI0_SCK
UART2_
CTS_b
FTM3_CH1 FB_CS0_b
PTD2/
LLWU_P13
DISABLED
DISABLED
DISABLED
PTD2/
LLWU_P13 SOUT
SPI0_
UART2_RX FTM3_CH2 FB_AD4/
I2C0_SCL
I2C0_SDA
SPI1_PCS0
SPI1_SCK
SDRAM_
A12
C8
F8
A9
B4
B5
C4
130
131
132
B4
A4
A3
PTD3
PTD3
SPI0_SIN
UART2_TX FTM3_CH3 FB_AD3/
SDRAM_
A11
PTD4/
LLWU_P14
PTD4/
LLWU_P14
SPI0_PCS1 UART0_
FTM0_CH4 FB_AD2/
EWM_IN
EWM_
RTS_b
SDRAM_
A10
PTD5
ADC0_
SE6b
ADC0_
SE6b
PTD5
SPI0_PCS2 UART0_
CTS_b/
FTM0_CH5 FB_AD1/
SDRAM_A9 OUT_b
UART0_
COL_b
B9
C5
133
A2
PTD6/
LLWU_P15 SE7b
ADC0_
ADC0_
SE7b
PTD6/
LLWU_P15
SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0
FTM0_
FLT0
SPI1_
SOUT
—
E9
J8
H7
E5
134
135
136
M10
F8
VSS
VSS
VSS
VDD
VDD
PTD7
VDD
A10
A1
DISABLED
PTD7
CMT_IRO
I2C0_SCL
I2C0_SDA
UART0_TX FTM0_CH7 SDRAM_
CKE
FTM0_
FLT1
SPI1_SIN
C9
D5
D4
D3
137
138
139
C9
B9
B3
PTD8/
LLWU_P24
DISABLED
DISABLED
DISABLED
PTD8/
LLWU_P24
LPUART0_
RX
FB_A16
FB_A17
FB_A18
B10
A11
PTD9
PTD9
LPUART0_
TX
PTD10
PTD10
LPUART0_
RTS_b
80
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Pinout
169
CSP
169
144
144
Pin Name
Default
DISABLED
DISABLED
DISABLED
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
FB_A19
FB_A20
FB_A21
ALT7
EZPORT
BGA LQFP BGA
D9
C2
B2
B3
140
141
142
B2
B1
C3
PTD11/
LLWU_P25
PTD11/
LLWU_P25
SPI2_PCS0
SPI2_SCK
SDHC0_
CLKIN
LPUART0_
CTS_b
C10
A12
PTD12
PTD12
FTM3_
FLT0
SDHC0_D4
PTD13
PTD13
SPI2_
SOUT
SDHC0_D5
B11
D10
—
A2
A3
K2
J7
—
143
144
—
C2
C1
PTD14
PTD15
NC
DISABLED
DISABLED
NC
PTD14
PTD15
SPI2_SIN
SDHC0_D6
SDHC0_D7
FB_A22
FB_A23
SPI2_PCS1
—
NC
NC
NC
NC
NC
—
—
M5
A10
B10
C10
NC
NC
—
—
NC
NC
—
—
—
NC
NC
—
—
—
NC
NC
5.2 Recommended connection for unused analog and digital
pins
Table 57 shows the recommended connections for analog interface pins if those
analog interfaces are not used in the customer's application
Table 57. Recommended connection for unused analog interfaces
Pin Type
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
GPIO/Analog
K26
Short recommendation
Float
Detailed recommendation
Analog input - Float
ADCx/CMPx
VREF_OUT
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Analog output - Float
DAC0_OUT, DAC1_OUT
RTC_WAKEUP_B
XTAL32
Analog output - Float
Analog output - Float
Analog output - Float
EXTAL32
Analog input - Float
PTA18/EXTAL0
PTA19/XTAL0
PTx/ADCx
Analog input - Float
GPIO/Analog
Analog output - Float
GPIO/Analog
Float (default is analog input)
Float (default is analog input)
Float (default is analog input)
GPIO/Analog
PTx/CMPx
GPIO/Analog
PTx/TSIOx
GPIO/Digital
PTA0/JTAG_TCLK
Float (default is JTAG with
pulldown)
GPIO/Digital
GPIO/Digital
PTA1/JTAG_TDI
PTA2/JTAG_TDO
Float
Float
Float (default is JTAG with
pullup)
Float (default is JTAG with
pullup)
Table continues on the next page...
Kinetis K26 Sub-Family, Rev. 4, 04/2017
81
NXP Semiconductors
Pinout
Table 57. Recommended connection for unused analog interfaces (continued)
Pin Type
K26
Short recommendation
Float
Detailed recommendation
GPIO/Digital
PTA3/JTAG_TMS
Float (default is JTAG with
pullup)
GPIO/Digital
PTA4/NMI_b
10kΩ pullup or disable and
float
Pull high or disable in PCR &
FOPT and float
GPIO/Digital
USB
PTx
Float
Float
Float
Float (default is disabled)
USB0_DP
USB0_DM
VREG_OUT
Float
Float
USB
USB
Tie to input and ground
through 10kΩ
Tie to input and ground
through 10kΩ
USB
USB
VREG_IN0
VREG_IN1
Tie to output and ground
through 10kΩ
Tie to output and ground
through 10kΩ
Tie to output and ground
through 10kΩ
Tie to output and ground
through 10kΩ
USB
USB1_VSS
USB1_DP
USB1_DM
USB1_VBUS
VBAT
Always connect to VSS
Always connect to VSS
USB
Float
Float
Float
Float
Float
Float
Float
Float
USB
USB
VBAT
VDDA
VDDA
Always connect to VDD
potential
Always connect to VDD
potential
VREFH
VREFL
VSSA
VREFH
VREFL
VSSA
Always connect to VDD
potential
Always connect to VDD
potential
Always connect to VSS
potential
Always connect to VSS
potential
Always connect to VSS
potential
Always connect to VSS
potential
5.3 MK26 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
82
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Pinout
PTE0
1
108
107
106
105
104
103
102
101
100
99
VDD
VSS
PTE1/LLWU_P0
2
PTE2/LLWU_P1
3
PTC3/LLWU_P7
PTC2
PTE3
4
VDD
5
PTC1/LLWU_P6
PTC0
VSS
6
PTE4/LLWU_P2
7
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
PTB16
VDD
PTE5
8
PTE6/LLWU_P16
9
PTE7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PTE8
98
PTE9/LLWU_P17
97
PTE10/LLWU_P18
96
PTE11
95
PTE12
94
VDD
VSS
93
VSS
PTB11
PTB10
PTB9
92
VSS
USB0_DP
91
90
USB0_DM
PTB8
89
VREG_OUT
PTB7
88
VREG_IN0
PTB6
87
VREG_IN1
PTB5
86
USB1_VSS
PTB4
85
USB1_DP
PTB3
84
USB1_DM
PTB2
83
USB1_VBUS
PTB1
82
ADC0_DM0/ADC1_DM3
ADC1_DP0/ADC0_DP3
ADC1_DM0/ADC0_DM3
VDDA
PTB0/LLWU_P5
PTA29
PTA28
PTA27
PTA26
PTA25
PTA24
RESET_b
PTA19
81
80
79
78
VREFH
77
VREFL
76
VSSA
75
ADC1_SE16/CMP2_IN2/ADC0_SE22
ADC0_SE16/CMP1_IN2/ADC0_SE21
74
73
Figure 36. MK26 144 LQFP Pinout Diagram
Kinetis K26 Sub-Family, Rev. 4, 04/2017
83
NXP Semiconductors
Pinout
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
PTC8
PTC4/
NC
PTC3/
PTC2
A
B
C
D
E
F
PTD7
PTD6/
LLWU_P15
PTD5
PTD4/
LLWU_P14
PTD0/
PTC16
PTC12
LLWU_P8
LLWU_P7
LLWU_P12
PTC11/
PTD12
PTD15
PTD11/
LLWU_P25
PTD10
PTD13
PTE0
PTD3
PTC19
PTC18
PTC17
VDD
PTC15
PTC14
PTC13
VDD
PTC7
PTD9
NC
NC
PTC1/
LLWU_P6
PTC0
PTB22
PTB18
PTB10
PTB6
LLWU_P11
PTD14
PTD2/
LLWU_P13
PTC10
PTC9
VDD
VSS
PTC6/
LLWU_P10
PTD8/
LLWU_P24
PTB23
PTB19
PTB11
PTB7
PTE2/
LLWU_P1
PTE1/
LLWU_P0
PTD1
PTE3
PTC5/
LLWU_P9
PTB21
PTB17
PTB9
PTB5
PTB1
PTB20
PTB16
PTB8
PTB4
PTE6/
LLWU_P16
PTE5
PTE4/
LLWU_P2
VDD
VDD
VSS
F
G
H
J
PTE10/
LLWU_P18
PTE9/
PTE8
PTE7
VDD
VSS
LLWU_P17
G
H
J
VREG_OUT
USB0_DP
VREG_IN0
USB0_DM
VREG_IN1
USB1_VSS
PTE12
PTE11
PTE28
PTE27
VREFH
VDDA
PTA0
VREFL
VSSA
PTA1
VSS
PTB3
PTB2
PTB0/
LLWU_P5
VSS
VSS
VSS
PTA29
PTA26
PTA17
PTA15
PTA28
PTA25
PTA24
RESET_b
ADC0_SE16/
PTA13/
LLWU_P4
CMP1_IN2/
ADC0_SE21
USB1_DP
PTA6
PTA3
PTA7
PTA8
PTA9
PTA27
PTA16
PTA14
ADC1_SE16/
PTE26/
CMP2_IN2/
ADC0_SE22
CLKOUT32K
K
L
K
L
USB1_DM
USB1_VBUS
PTE25/
LLWU_P21
PTA2
PTA12
DAC0_OUT/ DAC1_OUT/
CMP1_IN3/
CMP2_IN3/
ADC0_SE23
ADC0_DM0/
ADC1_DM3
CMP0_IN4/
RTC_
WAKEUP_B
VBAT
PTA4/
LLWU_P3
PTA11/
LLWU_P23
ADC1_SE23
VREF_OUT/
PTA10/
LLWU_P22
ADC1_DM0/
ADC0_DM3
ADC1_DP0/
ADC0_DP3
CMP1_IN5/
PTE24
M
M
NC
EXTAL32
XTAL32
PTA5
VSS
PTA19
PTA18
CMP0_IN5/
ADC1_SE18
1
2
3
4
5
6
7
8
9
10
11
12
Figure 37. MK26 144 BGA Pinout Diagram
84
NXP Semiconductors
Kinetis K26 Sub-Family, Rev. 4, 04/2017
Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
A
B
C
D
E
F
PTE0
PTD14
PTD15
PTD2/
LLWU_P13
PTD1
PTD0/
LLWU_P12
PTC25
PTC10
PTC11/
PTC6/
PTC5/
PTC3/
PTC2
A
B
C
D
E
F
LLWU_P11 LLWU_P10 LLWU_P9 LLWU_P7
PTE1/
LLWU_P0
PTD12
PTD13
VSS
PTD3
PTD5
PTD9
PTE8
PTD4/
LLWU_P14
PTC29
PTC28
PTC27
PTC26
PTE18/
PTC24
PTC19
PTC18
PTC17
PTE19
VDD
PTC13
PTC14
PTC15
PTC16
PTB16
VSS
PTC12
PTC9
PTB21
PTB15
PTB9
PTC7
PTC8
PTB20
PTB14
PTB8
PTB3
PTA30
PTA26
PTA9
PTC4/
LLWU_P8 LLWU_P6
PTC1/
PTC0
PTB22
PTB17
PTB11
PTB5
PTE2/
LLWU_P1 LLWU_P25
PTD11/
PTD6/
LLWU_P15
VSS
PTB23
PTB18
PTB12
PTB6
PTE3
PTE5
PTD10
PTE7
PTE9/
PTD8/
LLWU_P24
PTB19
PTB13
PTB7
PTE4/
LLWU_P2 LLWU_P16
PTE6/
PTD7
USB0_DM VREG_IN0
PTE10/
PTE17/
LLWU_P17 LLWU_P18 LLWU_P19 LLWU_P20
G
H
J
USB0_DP VREG_OUT
USB1_DM VREG_IN1
VSS
PTE16
VDDA
VREFH
PTE11
PTE12
VSSA
VREFL
NC
VDD
VDD
NC
VDD
VDD
NC
PTB10
PTB4
PTB2
PTB1
PTB0/
LLWU_P5
G
H
J
VDD
VSS
PTA29
PTA25
PTA24
PTA28
PTA17
PTA15
PTA12
VSS
PTA27
PTA16
USB1_VBUS
NC
USB1_DP
USB1_VSS
ADC1_DP1
ADC1_DM1
NC
VSS
PTA31
PTA8
PTE25/
LLWU_P21 CLKOUT32K
PTE26/
K
L
NC
NC
PTA14
K
L
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
PTA4/
LLWU_P3
ADC0_DM0/
ADC1_DM3
NC
NC
PTE24
PTE28
PTE27
PTA3
PTA7
PTA13/
LLWU_P4
RESET_b
PTA19
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
PTA11/
LLWU_P23
ADC0_DP0/
ADC1_DP3
RTC_
WAKEUP_B
M
N
VBAT
PTA2
PTA6
M
N
VREF_OUT/ DAC1_OUT/
CMP1_IN5/ CMP0_IN4/
PTA10/
LLWU_P22
ADC1_DM0/
ADC0_DM3 CMP0_IN5/
ADC1_SE18
ADC1_DP0/
ADC0_DP3
XTAL32
5
EXTAL32
6
VSS
7
PTA0
8
PTA1
9
PTA5
10
VDD
12
PTA18
13
CMP2_IN3/
ADC1_SE23
1
2
3
4
11
Figure 38. MK26 169 BGA Pinout Diagram
Kinetis K26 Sub-Family, Rev. 4, 04/2017
85
NXP Semiconductors
Ordering parts
1
2
3
4
5
6
7
8
9
10
11
12
13
A
B
C
D
E
F
PTC4/
LLWU_P8
PTC9
PTC13
PTC15
PTC16
PTC24
PTC27
PTD1
PTD5
PTD7
PTD10
PTD13
PTE1/
LLWU_P0
A
B
C
D
E
F
PTC3/
LLWU_P7 LLWU_P9
PTC5/
PTC10
PTC6
PTC14
PTC8
PTC2
PTB19
PTB12
PTB7
PTC17
PTC12
PTC7
PTC19
PTC18
PTC28
PTC29
PTC25
VDD
PTD2/
LLWU_P13 LLWU_P15
PTD6/
PTD9
PTD12
PTD15
PTE7
PTD14
PTE0
PTE2/
LLWU_P1
PTE3
PTC0
PTB21
PTB16
PTB15
PTB10
PTB5
PTC1/
LLWU_P6 /LLWU_P10
PTD3
PTD8/
LLWU_P24
PTE4/
LLWU_P2 LLWU_P16
PTE6/
PTB22
PTB17
PTB14
PTB9
PTB4
PTB1
PTA29
PTA27
VSS
PTB23
PTB18
PTB13
PTB8
PTC11/
LLWU_P11
PTD0/
LLWU_P12 LLWU_P25
PTD11/
PTE5
PTE8
PTE12
PTE19
PTE9/
LLWU_P17
PTB20
PTB11
PTB6
VDD
VSS
VDD
VSS
PTA3
PTC26
VDD
VDD
PTE16
NC
PTE11
PTE17/
VDD
VSS
VSS
PTD4/
LLWU_P14
PTE10/
LLWU_P18 LLWU_P19
G
H
J
VSS
VSS
NC
PTE18/ VREG_OUT VREG_IN0 USB0_DP
LLWU_P20
G
H
J
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
PTB0/
LLWU_P5
PTB3
PTA31
PTA9
VSS
NC
VREG_IN1 USB0_DM
RTC_
WAKEUP_B
PTB2
PTA26
PTA24
PTA17
VDD
PTA25
PTA16
PTA15
PTA12
PTE27
PTE28
PTA2
PTA1
NC
NC
ADC1_DP1 USB1_VSS USB1_DP
ADC1_DM1 USB1_VBUS USB1_DM
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
PTA10/
LLWU_P22
PTA4/
LLWU_P3
K
L
PTA30
PTA28
RESET_b
VDD
NC
K
L
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
PTE26/
CLKOUT32K
PTA13/
LLWU_P4
PTA7
VDD
VBAT
XTAL32
VDDA
ADC1_DP0/ ADC0_DP0/
ADC0_DP3 ADC1_DP3
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
ADC0_DM0/
ADC1_DM0/
ADC1_DM3
ADC0_DM3
PTE25/
LLWU_P21
M
N
PTA8
VREFH
M
N
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
PTA11/
LLWU_P23
PTA18
1
PTA19
2
PTA14
3
PTA6
5
PTA5
6
PTA0
7
PTE24
8
EXTAL32
9
NC
10
VREFL
12
VSSA
13
4
11
Figure 39. MK26 169 CSP Pinout Diagram
6 Ordering parts
86
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Part identification
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: MK26
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
A
Kinetis family
Key attribute
• K26
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
• 2M0 = 2 MB
Table continues on the next page...
Kinetis K26 Sub-Family, Rev. 4, 04/2017
87
NXP Semiconductors
Terminology and guidelines
Field
Description
Values
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
• C = –40 to 85
PP
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
CC
Maximum CPU frequency (MHz)
• 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
• 16 = 168 MHz
• 18 = 180 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
MK26FN2M0CAC18R
8 Terminology and guidelines
8.1 Definitions
Key terms are defined in the following table:
Term
Definition
Rating
A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
Table continues on the next page...
88
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Terminology and guidelines
Term
Definition
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.
8.2 Examples
Operating rating:
EXAMPLE
EXAMPLE
Operating requirement:
Operating behavior that includes a typical value:
8.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Kinetis K26 Sub-Family, Rev. 4, 04/2017
89
NXP Semiconductors
Revision History
Symbol
Description
Ambient temperature
Supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
8.4 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
8.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
9 Revision History
The following table provides a revision history for this document.
90
Kinetis K26 Sub-Family, Rev. 4, 04/2017
NXP Semiconductors
Revision History
Table 58. Revision History
Rev. No.
Date
Substantial Changes
Initial Release
• Editorial change
0
1
02/2015
04/2015
• Updated OTG/EH and BC rev. 1.2 specification references in USB Full Speed
Transceiver and High Speed PHY specifications section
• Updated USBDCD electrical specifications table
• Updated the typical values and maximum values of specs in Power consumption
operating behaviors table
• Removed PSTOP2 current from Power consumption operating behaviors table
• Updated the values of DS5 and DS7 in Master mode DSPI timing (full voltage
range) table
• Updated the footnote and description of VDIO, VAIO and ID in Voltage and current
operating ratings table
• Updated the values and description of specs in Voltage and current operating
requirements table
• Updated the leakage current specs in Voltage and current operating behaviors table
• Added Notes column in Thermal operating requirements
• Updated the values of 48 MHz IRC in Low power mode peripheral adders table
2
3
4
05/2015
01/2016
03/2017
• Added new footnotes for IINRUSH in USB VREG electrical specifications table to
better document operation.
• Added a footnote to the figures, "SDRAM write timing diagram" and "SDRAM read
timing diagram," for 144-pin packages, in the section "SDRAM controller
specifications."
• Added a note to the section "Pinouts" for pin functions not available in 144-pin
packages.
• Updated the symbol in footnote of Thermal operating spec
• Updated description of PLL operating current in MCG specification table.
• Added the USB FS and USB HS logo in front matter
• Updated IRC48M specifications
• Updated Terminology and guidelines section
• Updated the maximum values of IDD_LLS2 and IDD_LLS3 in Power consumption
operating behaviors table
• Removed the verbiage of "except RTC_WAKEUP pins" from the description for RPU
and RPD in Voltage and current operating behaviors table
• Updated the unit of ADC conversion rate from "Kbps" to "kS/s" in 16-bit ADC
operating conditions table
• Updated I2C switching specifications section
• Updated the minimum and maximum value of Voltage reference output with factory
trim in VREF full-range operating requirements table in Voltage reference electrical
specifications section
Kinetis K26 Sub-Family, Rev. 4, 04/2017
91
NXP Semiconductors
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
How to Reach Us:
Home Page:
nxp.com
Web Support:
nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customer's technical experts. NXP
does not convey any license under its patent rights nor the rights of others. NXP
sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/SalesTermsandConditions.
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Document Number K26P169M180SF5
Revision 4, 04/2017
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