935324175528 [NXP]
Microcontroller;
| 型号： | 935324175528 |
| 厂家： | 
NXP |
| 描述： | Microcontroller 微控制器 外围集成电路 |
| 文件： | 总14页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCS12BFAMILYPP
Rev. 2.8, 7/2005
Freescale Semiconductor
Product Brief
MC9S12B Family
16-bit Microcontroller
1 Introduction
Designed for automotive multiplexing applications, members of the MC9S12B-Family of 16 bit
Flash-based microcontrollers are fully pin compatible and enable users to choose between different
memory and peripheral options for scalable designs. All MC9S12B-Family members are composed of
standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 256K bytes of Flash
EEPROM, 8K bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces
(SCI), serial peripheral interface (SPI), an input capture/output compare timer (TIM), 16-channel, 10-bit
analog-to-digital converter (ADC), an 8-channel pulse-width modulator (PWM), one CAN 2.0 A, B
software compatible module (MSCAN12) and an Inter-IC Bus. System resource mapping, clock
generation, interrupt control and bus interfacing are managed by the lite integration module (LIM). The
MC9S12B-Family has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit
narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a
PLL circuit allows power consumption and performance to be adjusted to suit operational requirements.
In addition to the I/O ports available in each module, up to 22 I/O ports are available with Wake-Up
capability from STOP or WAIT mode.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Features
2 Features
NOTE
Not all features listed here are available in all configurations.
Additional information about D and B family inter-operability is given in:
EB386 “HCS12 D-Family Compatibility Considerations” and
EB388 “Using the HCS12 D_Family as a development platform for the
HCS12 B family”
•
16-bit CPU12
— Upward compatible with M68HC11 instruction set
— Interrupt stacking and programmer’s model identical to M68HC11
— 20-bit ALU
— Instruction queue
— Enhanced indexed addressing
•
•
•
Multiplexed bus
— Single chip or expanded
— 16 address/16 data wide or 16 address/8 data narrow modes
— External address space 1MByte for Data and Program space (112 pin package only)
Wake-up interrupt inputs depending on the package option
— 8-bit port H
— 4-bit port J
— 8-bit port P shared with PWM
Memory options
— 64K, 128K, 256K Byte Flash EEPROM
— 1K, 2K Byte EEPROM
— 2K, 4K and 8K Byte RAM
•
•
Analog-to-Digital Converter
— 16-channels for 112 Pin Package, 8 channels for 80 Pin package options, 10-bit resolution
— External conversion trigger capability
1M bit per second, CAN 2.0 A, B software compatible module
— Five receive and three transmit buffers
— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
— Four separate interrupt channels for Rx, Tx, error and wake-up
— Low-pass filter wake-up function
— Loop-back for self test operation
•
Input Capture/Output Compare Timer (TIM)
MC9S12B Family, Rev. 2.8
2
Freescale Semiconductor
Features
— 16-bit Counter with 7-bit Prescaler
— 8 programmable input capture or output compare channels
— Simple PWM Mode
— Modulo Reset of Timer Counter
— 16-bit Pulse Accumulator
— External Event Counting
— Gated Time Accumulation
•
8 PWM channels with programmable period and duty cycle (7 channels on 80 Pin Packages)
— 8-bit 8-channel or 16-bit 4-channel
— Separate control for each pulse width and duty cycle
— Center- or left-aligned outputs
— Programmable clock select logic with a wide range of frequencies
Serial interfaces
•
•
— Two asynchronous serial communications interfaces (SCI)
— synchronous serial peripheral interface (SPI)
Inter-IC Bus (IIC)
— Compatible with I2C Bus standard
— Multi-master operation
— Software programmable for one of 256 different serial clock frequencies
SIM (System Integration Module)
•
— CRG (windowed COP watchdog, real time interrupt, clock monitor, clock generation and
reset)
— MEBI (multiplexed external bus interface)
— MMC (memory map and interface)
— INT (interrupt control)
— BKP (breakpoints)
— BDM (background debug mode)
Clock generation
•
•
— Phase-locked loop clock frequency multiplier
— Limp home mode in absence of external clock
— Clock Monitor
— Low power 0.5 to 16 MHz crystal oscillator reference clock
Operation frequency
— 50MHz equivalent to 25MHz Bus Speed for single chip
— 50MHz equivalent to 25MHz Bus Speed in expanded bus modes
MC9S12B Family, Rev. 2.8
Freescale Semiconductor
3
Features
•
•
Internal 5V to 2.5V Regulator
112-Pin or 80-Pin LQFP package
— I/O lines with 5V input and drive capability
— 5VA/D converter inputs
— Dual supply - 5V for I/O and A/D, 2.5V logic
Development support
•
— Single-wire background debug™ mode (BDM)
— On-chip hardware breakpoints
Table 1. List of MC9S12B-Family members
Flash
RAM
EEPROM Package
Device
CAN SCI
SPI
IIC
A/D PWM TIM
I/O
256K
128K
64K
8K
2K
1K
1K
112LQFP MC9S12B256
80QFP MC9S12B256
112LQFP MC9S12B128
80QFP MC9S12B128
112LQFP MC9S12B64
1
1
1
1
1
1
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
16ch 8ch
8ch 7ch
16ch 8ch
8ch 7ch
16ch 8ch
8ch 7ch
8ch
8ch
8ch
8ch
8ch
8ch
91
59
91
59
91
59
4K
2K
80QFP
MC9S12B64
•
Pin out explanations:
— I/O is the sum of ports capable to act as digital input or output
For 112 Pin Versions:
Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 7, M = 8, P = 8, S = 8, T = 8,
PAD = 16 input only.
22 inputs provide Interrupt capability (H =8, P= 8, J = 4, IRQ, XIRQ
For 80 Pin Versions:
Port A = 8, B = 8, E = 6 + 2 input only, J = 2, M = 6, P = 7, S = 4, T = 8, PAD = 8 input only.
11 inputs provide Interrupt capability (P= 7, J = 2, IRQ, XIRQ)
MC9S12B Family, Rev. 2.8
4
Freescale Semiconductor
Features
VRH
VRL
VDDA
VSSA
VRH
VRL
VDDA
VSSA
64K, 128K, 256K Byte Flash EEPROM
2K, 4K, 8K Byte RAM
ATD
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
PAD0
PAD1
PAD2
PAD3
PAD4
PAD5
PAD6
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
1K, 2K Byte EEPROM
VDDR
VSSR
VREGEN
VDD1,2
VSS1,2
Voltage Regulator
PAD7
PAD15
PIX0
PK0 XADDR14
PK1 XADDR15
Single-wire Background
BKGD
PIX1
PIX2
PIX3
PIX4
PIX5
ECS
CPU12
Debug Module
PPAGE
PK2
XADDR16
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
PK3 XADDR17
PK4 XADDR18
PK5 XADDR19
Clock and
Reset
Generation
Module
PLL
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
PK7
ECS
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
PT0
PT1
PT2
PT3
PT4
PT5
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
XIRQ
IRQ
R/W
LSTRB
ECLK
MODA
MODB
Input Capture
Output Compare
Timer
System
Integration
Module
(SIM)
PT6
PT7
NOACC/XCLKS
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
PP0
PP1
PP2
PP3
PP4
PP5
TEST
Multiplexed Address/Data Bus
PWM6
PWM7
PP6
PP7
PWM
DDRA
PTA
DDRB
PTB
RXD
TXD
RXD
TXD
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
SCI0
SCI1
MISO
MOSI
SCK
SS
SPI0
RxCAN
CAN0
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
TxCAN
Multiplexed
Wide Bus
Multiplexed
Narrow Bus
Internal Logic 2.5V
VDD1,2
VSS1,2
I/O Driver 5V
KWJ0
KWJ1
PJ0
PJ1
VDDX
VSSX
KWJ6
KWJ7
PJ6
PJ7
SDA
SCL
IIC
A/D Converter 5V &
PLL 2.5V
Voltage Regulator Reference
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
PH0
PH1
PH2
PH3
PH4
PH5
VDDPLL
VSSPLL
VDDA
VSSA
Pin
Interrupt
Logic
Voltage Regulator 5V & I/O
VDDR
VSSR
PH6
PH7
Not all functionality shown in this
Block diagram is available in all Versions!
MC9S12B Family, Rev. 2.8
Freescale Semiconductor
5
Features
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
PWM3/KWP3/PP3
PWM2/KWP2/PP2
PWM1/KWP1/PP1
PWM0/KWP0/PP0
XADDR17/PK3
XADDR16/PK2
XADDR15/PK1
XADDR14/PK0
IOC0/PT0
1
VRH
VDDA
2
3
PAD15/AN15
PAD07/AN07
4
5
PAD14/AN14
PAD06/AN06
6
7
PAD13/AN13
PAD05/AN05
8
9
PAD12/AN12
PAD04/AN04
IOC1/PT1
IOC2/PT2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PAD11/AN11
PAD03/AN03
IOC3/PT3
VDD1
PAD10/AN10
PAD02/AN02
VSS1
IOC4/PT4
MC9S12B-Family
112LQFP
PAD09/AN09
PAD01/AN01
IOC5/PT5
IOC6/PT6
IOC7/PT7
PAD08/AN08
PAD00/AN00
VSS2
XADDR19/PK5
XADDR18/PK4
KWJ1/PJ1
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
KWJ0/PJ0
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
Signals shown in Bold are not available on the 80 Pin Package
Figure 1. Pin assignments 112 QFP for MC9S12B-Family
MC9S12B Family, Rev. 2.8
6
Freescale Semiconductor
Features
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PWM3/KWP3/PP3
PWM2/KWP2/PP2
PWM1/KWP1/PP1
PWM0/KWP0/PP0
IOC0/PT0
1
VRH
VDDA
2
3
PAD07/AN07
PAD06/AN06
4
5
PAD05/AN05
PAD04/AN04
IOC1/PT1
IOC2/PT2
6
7
PAD03/AN03
PAD02/AN02
IOC3/PT3
VDD1
8
9
PAD01/AN01
PAD00/AN00
VSS1
IOC4/PT4
10
11
12
13
14
15
16
17
18
19
20
MC9S12B-Family
80 QFP
VSS2
VDD2
IOC5/PT5
IOC6/PT6
IOC7/PT7
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
Figure 2. Pin Assignments in 80 QFP for MC9S12B-Family
MC9S12B Family, Rev. 2.8
Freescale Semiconductor
7
Features
$0000
1K Register Space
$03FF
$0800
Mappable to any 2K Boundary
2K Bytes EEPROM
$0000
$0400
$0800
$1000
$0FFF
$2000
Mappable to any 2K Boundary
8K Bytes RAM
$2000
$3FFF
$4000
Mappable to any 8K Boundary
$4000
$8000
$C000
1K, 2K, 4K or 8K Protected Sector
16K Fixed Flash EEPROM
$7FFF
$8000
16K Page Window
sixteen * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $1FFF: 8K RAM (only 7K visible $0400 - $1FFF)
$0000 - $07FF: 2K EEPROM (not visible)
$2000 - $3FFF: 8K Flash
Figure 3. MC9S12Bx256 User Configurable Memory Map
MC9S12B Family, Rev. 2.8
8
Freescale Semiconductor
Features
$0000
1K Register Space
$03FF
$0800
Mappable to any 2K Boundary
$0000
$0400
$0800
1K Bytes EEPROM
Repeated twice in the 2K Space
$0FFF
$3000
$3FFF
$4000
Mappable to any 2K Boundary
$1000
$3000
4K Bytes RAM
Mappable to any 4K Boundary
$4000
$8000
$C000
1K, 2K, 4K or 8K Protected Sector
16K Fixed Flash EEPROM
$7FFF
$8000
16K Page Window
Eight * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF)
$0000 - $07FF: 1K EEPROM (not visible)
$2000 - $3FFF: 12K Flash
Figure 4. MC9S12Bx128 User Configurable Memory Map
MC9S12B Family, Rev. 2.8
Freescale Semiconductor
9
Features
$0000
1K Register Space
$03FF
$0800
Mappable to any 2K Boundary
$0000
$0400
$0800
1K Bytes EEPROM
Repeated twice in the 2K Space
$0FFF
Mappable to any 2K Boundary
$1000
$3800
$4000
$3800
$3FFF
2K Bytes RAM
Mappable to any 2K Boundary
$4000
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
$8000
$7FFF
$8000
16K Page Window
four * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0800 - $0FFF: 2K RAM
$0400 - $07FF: 1K EEPROM
$2000 - $3FFF: 12K Flash
Figure 5. MC9S12Bx64 User Configurable Memory Map
MC9S12B Family, Rev. 2.8
10
Freescale Semiconductor
Features
4X
0.20 T L-M N
4X 28 TIPS
0.20 T L-M N
4X
P
J1
J1
PIN 1
IDENT
112
85
C
1
84
L
VIEW Y
X
108X
G
X=L, M OR N
VIEW Y
V
B
L
M
AA
J
B1
V1
28
57
BASE
METAL
F
D
29
56
M
0.13
T L-M N
N
SECTION J1-J1
A1
S1
ROTATED 90 COUNTERCLOCKWISE
°
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
S
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.46.
C2
VIEW AB
θ2
C
0.050
112X
0.10
T
SEATING
PLANE
θ3
MILLIMETERS
T
DIM MIN
MAX
20.000 BSC
10.000 BSC
A
A1
B
B1
C
20.000 BSC
10.000 BSC
---
1.600
θ
C1 0.050
C2 1.350
0.150
1.450
0.370
0.750
0.330
D
E
F
0.270
0.450
0.270
R R2
G
J
0.650 BSC
0.090
0.170
K
P
0.500 REF
0.325 BSC
0.25
R R1
R1 0.100
R2 0.100
0.200
0.200
GAGE PLANE
S
S1
V
V1
Y
22.000 BSC
11.000 BSC
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
(K)
C1
θ1
E
Z
(Y)
(Z)
AA 0.090
0.160
8 °
0 °
θ
θ1
θ2
θ3
3 °
11 °
11 °
7 °
VIEW AB
13 °
13 °
Figure 6. 112-pin LQFP Mechanical Dimensions (case no. 987)
MC9S12B Family, Rev. 2.8
Freescale Semiconductor
11
Features
L
60
41
61
40
B
B
P
-A-
-B-
L
V
B
-A-,-B-,-D-
DETAIL A
DETAIL A
21
80
F
1
20
-D-
A
M
S
S
S
0.20
H
A-B
D
D
0.05 A-B
J
N
S
M
S
0.20
C A-B
D
M
E
DETAIL C
M
S
S
D
0.20
C
A-B
SECTION B-B
VIEW ROTATED 90
C
DATUM
PLANE
-H-
°
-C-
SEATING
PLANE
0.10
H
M
G
NOTES:
MILLIMETERS
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
DIM MIN
MAX
14.10
14.10
2.45
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING LINE.
4. DATUMS -A-, -B- AND -D- TO BE
DETERMINED AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -C-.
A
B
C
D
E
F
G
H
J
13.90
13.90
2.15
0.22
2.00
0.22
U
0.38
2.40
T
0.33
0.65 BSC
DATUM
PLANE
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
---
0.13
0.65
0.25
0.23
0.95
-H-
R
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR
THE FOOT.
K
L
12.35 REF
M
N
P
Q
R
S
T
U
V
W
X
5
°
0.13
10
°
0.17
0.325 BSC
0
K
7
Q
°
°
W
0.13
16.95
0.13
0
0.30
17.45
---
X
DETAIL C
---
°
16.95
0.35
17.45
0.45
1.6 REF
Figure 7. 80-pin QFP Mechanical Dimensions (case no. 841B)
MC9S12B Family, Rev. 2.8
12
Freescale Semiconductor
Features
MC9S12B Family, Rev. 2.8
Freescale Semiconductor
13
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