935338883557 [NXP]
Multifunction Peripheral;
| 型号： | 935338883557 |
| 厂家： | 
NXP |
| 描述： | Multifunction Peripheral |
| 文件： | 总260页 (文件大小：3375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number LS1043A
Rev. 2, 01/2017
NXP Semiconductors
Data Sheet: Technical Data
LS1043A
QorIQ LS1043A, LS1023A
Data Sheet
Features
• Four SerDes lanes for high-speed peripheral interfaces
– Three PCI Express 2.0 controllers supporting x4
operation
• LS1043A contains 32-bit /64-bit ARM® Cortex®-A53
MPCore Processor with the following capabilities:
– Speed up to 1.6 GHz
– One Serial ATA (SATA 3.0) controller
– Up to four SGMII supporting 1000 Mbit/s
– Up to two SGMII supporting 2500 Mbit/s
– Up to one XFI (10 GbE) interface
– Up to one QSGMII
– 32 KB L1 Instruction Cache w/parity
– 32 KB L1 Data Cache w/ECC
– Neon SIMD Co-processor
– ARM v8 Cryptography Extensions
– Supports 1000Base-KX
• 1 MB unified I/D L2 Cache w/ECC
• Additional peripheral interfaces
– One Quad Serial Peripheral Interface (QSPI)
controller, one Deserial Serial Peripheral Interface
(DSPI) controller
• Hierarchical interconnect fabric
– Hardware Managed Data coherency
– Up to 400 MHz operation
– Integrated Flash Controller (IFC) supporting NAND
and NOR flash with 28-bit addressing and 16-bit
data
– Three USB 3.0 controllers with integrated PHY
– Enhanced Secure Digital Host Controller (eSDHC)
supporting SD 3.0, eMMC 4.4, and eMMC 4.5
modes
• One 32-bit DDR3L/DDR4 SDRAM memory controller
– ECC and interleaving support
– Up to 1.6 GT/s
• Data Path Acceleration Architecture (DPAA)
incorporating acceleration for the following functions:
– Packet parsing, classification, and distribution
(FMan)
– uQE supporting TDM/HDLC
– Queue management for scheduling, packet
sequencing, and congestion management (QMan)
– Hardware buffer management for buffer allocation
and de-allocation (BMan)
– Four I2C controllers
– Two 16550 compliant DUARTs and six low-power
UARTs (LPUARTs)
– General Purpose IO (GPIO), eight Flextimers, five
Watchdog timer, four independent PWM/counters/
timer
– Trust Architecture
– Debug supporting run control, data acquisition,
high-speed trace, and performance/event monitoring
– Cryptography acceleration (SEC)
• Parallel Ethernet interfaces
– Up to two RGMII interfaces
– IEEE 1588 support
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1 Introduction.......................................................................................... 3
3.17 Flextimer interface.....................................................................182
3.18 SPI interface.............................................................................. 185
3.19 QuadSPI interface......................................................................187
3.20 Enhanced secure digital host controller (eSDHC).....................189
3.21 JTAG controller.........................................................................198
3.22 I2C interface.............................................................................. 201
3.23 GPIO interface...........................................................................204
3.24 GIC interface............................................................................. 208
3.25 High-speed serial interfaces (HSSI).......................................... 210
4 Hardware design considerations...........................................................232
4.1 System clocking........................................................................ 233
4.2 Connection recommendations................................................... 242
5 Thermal................................................................................................ 247
5.1 Recommended thermal model...................................................249
5.2 Temperature diode.....................................................................249
5.3 Thermal management information............................................ 249
6 Package information.............................................................................252
6.1 Package parameters for the FC-PBGA......................................252
6.2 Mechanical dimensions of the FC-PBGA................................. 252
7 Security fuse processor.........................................................................255
8 Ordering information............................................................................255
8.1 Part numbering nomenclature....................................................255
8.2 Part marking ............................................................................. 256
9 Revision history....................................................................................257
2 Pin assignments....................................................................................4
2.1 621 ball layout diagrams........................................................... 4
2.2 Pinout list (21x21).....................................................................10
2.3 780 ball layout diagrams........................................................... 48
2.4 Pinout list...................................................................................54
3 Electrical characteristics.......................................................................96
3.1 Overall DC electrical characteristics.........................................96
3.2 Power sequencing......................................................................104
3.3 Power down requirements......................................................... 106
3.4 Power characteristics.................................................................107
3.5 Low power mode saving estimation..........................................110
3.6 I/O power dissipation................................................................ 111
3.7 Power-on ramp rate................................................................... 113
3.8 Input clocks............................................................................... 113
3.9 RESET initialization..................................................................120
3.10 DDR4 and DDR3L SDRAM controller.................................... 121
3.11 Ethernet interface, Ethernet management interface, IEEE Std
1588........................................................................................... 128
3.12 QUICC engine specifications....................................................153
3.13 USB 3.0 interface...................................................................... 158
3.14 Integrated Flash Controller........................................................162
3.15 LPUART interface.....................................................................179
3.16 DUART interface...................................................................... 181
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
2
NXP Semiconductors
Introduction
1 Introduction
LS1043A is a cost-effective, power-efficient, and highly integrated system-on-chip (SoC)
design that extends the reach of the NXP value-performance line of QorIQ
communications processors. Featuring extremely power-efficient 64-bit ARM®
Cortex®-A53 cores with ECC-protected L1 and L2 cache memories for high reliability,
running up to 1.6 GHz.
This chip can be used for networking and wireless access points, industrial gateways,
industrial automation, M2M for enterprise, consumer networking and router applications.
This figure shown below represents the block diagram of the LS1043A chip.
ARM® Cortex®-A53
64-bit Core
32 KB
32 KB
D-Cache
I-Cache
32-bit
DDR3L/4
Memory Controller
1 MB L2 - Cache
Secure Boot
CCI-400™ Coherency Fabric
Trust Zone
Power Management
IFC, QuadSPI, SPI
SD/SDIO/eMMC
SMMUs
Real Time Debug
Security
Engine
(SEC)
Frame Manager
Queue
Manager
DMA
Watchpoint
Cross
Trigger
Parse, classify,
distribute
2x DUART
4x I2C, 4x GPIO
8x FlexTimer
Perf
Monitor
Trace
Buffer
Manager
1G 1G 1G
1/2.5G
1G 1G
1/2.5/10G
3x USB3.0 w/PHY
6x LPUART
DPAA Hardware
4-Lane, 10 GHz SerDes
Core Complex
Accelerators and Memory Control
Basic Peripherals, Interconnect and Debug
Networking Elements
Figure 1. LS1043A Block Diagram
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
3
Pin assignments
This figure shown below represents the block diagram of the LS1023A chip.
®
®
ARM Cortex -A53
64-bit Core
32 KB
32 KB
I-Cache
D-Cache
32-bit
DDR3L/4
Memory Controller
1 MB L2 - Cache
Secure Boot
CCI-400™ Coherency Fabric
Trust Zone
Power Management
IFC, QuadSPI, SPI
SD/SDIO/eMMC
SMMUs
Real Time Debug
Security
Engine
(SEC)
Frame Manager
Queue
Manager
DMA
Watchpoint
Cross
Trigger
Parse, classify,
distribute
2x DUART
4x I2C, 4x GPIO
8x FlexTimer
Perf
Monitor
Trace
Buffer
Manager
1G 1G 1G
1/2.5G
1G 1G
1/2.5/10G
3x USB3.0 w/PHY
6x LPUART
DPAA Hardware
4-Lane 10 GHz SerDes
Core Complex
Accelerators and Memory Control
Basic Peripherals, Interconnect and Debug
Networking Elements
Figure 2. LS1023A Block Diagram
2 Pin assignments
This section describes the ball map diagram and pin list table for both 21x21 and 23x23
packages of LS1043A.
2.1 621 ball layout diagrams
This figure shows the complete view of the LS1043A ball map diagram for the 21x21
package. Figure 4, Figure 5, Figure 6, and Figure 7 show quadrant views.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
4
NXP Semiconductors
Pin assignments
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A
A
B
B
C
C
D
D
E
E
F
F
SEE DETAIL A
SEE DETAIL B
G
H
G
H
J
J
K
K
L
L
M
N
M
N
P
P
R
R
T
T
U
U
V
V
SEE DETAIL C
SEE DETAIL D
W
Y
W
Y
AA
AB
AC
AD
AE
AA
AB
AC
AD
AE
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
DDR Interface 1
Interrupts
SYSCLK
IFC
DUART
eSPI
eSDHC
ASLEEP
DFT
Battery Backed Trust
DDR Clocking
Analog Signals
Ethernet MI 1
USB
Trust
System Control
Debug
RTC
JTAG
Serdes 1
Ethernet MI 2
TA_BB_RTC
USB3 PHY
1
USB3 PHY 2
USB PHY
I2C
3
Ethernet Cont. 1
DIFF_SYSCLK
Ethernet Cont. 2
Power
Ground
No Connects
Figure 3. Complete BGA Map for the LS1043A
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
5
Pin assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
USB3_
RX_
P
USB3_
RX_
M
USB3_
D_
USB3_
VBUS
IFC_
IFC_
IFC_
IFC_
IFC_
IFC_
A
A
B
C
D
E
F
GND001
GND002
AD01
AD03
AD04
AD06
AD08
AD09
M
USB3_
USB3_
TX_
M
USB3_
D_
P
USB3_
ID
IFC_
AD00
IFC_
AD02
IFC_
AD05
IFC_
AD07
B
TX_
GND004
GND005
GND006
GND007
GND008
P
USB2_
RX_
P
USB2_
RX_
M
USB2_
D_
M
USB2_
VBUS
IFC_
A17
IFC_
A18
IFC_
A20
IFC_
A21
IFC_
A23
IFC_
A25
C
GND013
GND014
GND015
USB2_
USB2_
TX_
M
USB2_
D_
P
USB2_
ID
IFC_
A16
IFC_
A19
IFC_
A22
IFC_
A24
D
TX_
GND017
GND018
GND019
GND020
ASLEEP
SYSCLK
GND021
EVT3_B
GND035
P
USB1_
RX_
P
USB1_
RX_
M
USB1_
D_
M
USB1_
VBUS
E
GND025
GND026
GND027
EVT2_B
GND033
EVT0_B
EVT4_B
GND034
EVT1_B
GND036
USB1_
USB1_
TX_
M
USB1_
D_
P
USB1_
ID
PORESET_
B
F
TX_
GND030
GND031
GND032
P
USB1_
USB2_
USB3_
USB_
RESET_
REQ_B
DIFF_
DIFF_
HRESET_
B
AVDD_
CGA2
AVDD_
CGA1
AVDD_
PLAT
G
G
H
J
GND039
GND040
RESREF
RESREF
RESREF
PWRFAULT
SYSCLK
SYSCLK_B
UART1_
SOUT
UART1_
SIN
USB_
DRVVBUS
H
GND043
IRQ03
GND044
IRQ04
GND045
IRQ05
IRQ06
IRQ07
IRQ08
EVT9_B
GND056
GND062
GND069
GND078
GND046
GND047
GND048
GND049
GND050
OVDD1
GND064
VDD05
GND051
OVDD2
VDD01
UART1_
CTS_B
UART1_
RTS_B
USB_
HVDD1
USB_
HVDD2
USB_
SVDD1
USB_
SVDD2
J
IRQ02
UART2_
SIN
IIC2_
SCL
NC_
K6
USB_
SDVDD1
USB_
SDVDD2
K
K
L
GND060
GND061
DVDD1
DVDD2
EVDD
GND063
VDD04
UART2_
RTS_B
UART2_
SOUT
IIC2_
SDA
IIC3_
SCL
NC_
L6
L
GND070
VDD08
GND071
VDD09
GND072
VDD10
IIC1_
SDA
UART2_
CTS_B
IIC4_
SCL
IIC3_
SDA
NC_
M6
M
M
N
GND079
GND080
IIC1_
SCL
IIC4_
SDA
N
GND085
GND086
IRQ09
GND087
OVDD7
VDD13
GND088
VDD14
GND089
VDD15
GND090
1
2
3
4
5
6
7
8
9
10
11
12
13
DDR Interface 1
Interrupts
SYSCLK
JTAG
IFC
DUART
Trust
eSPI
eSDHC
Battery Backed Tru
DDR Clocking
Analog Signals
Ethernet MI 1
USB
System Control
Debug
ASLEEP
DFT
RTC
Serdes 1
USB3 PHY 1
Ethernet Cont. 1
DIFF_SYSCLK
USB3 PHY 2
USB PHY 3
I2C
Ethernet MI 2
TA_BB_RTC
Ethernet Cont. 2
Power
Ground
No Connects
Figure 4. Detail A
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
6
NXP Semiconductors
Pin assignments
13
14
15
16
17
18
19
20
21
22
23
24
25
IFC_
IFC_
IFC_
IFC_
IFC_
IFC_
IFC_
IFC_
SCAN_
D1_
D1_
A
B
C
D
E
F
A
GND003
AD09
AD11
AD13
AD14
AD15
AVD
CS1_B
CLK0
MODE_B
MECC1
MDQS8_B
IFC_
AD10
IFC_
AD12
IFC_
NDDQS
IFC_
PAR0
IFC_
CLK1
D1_
MDM8
D1_
MDQS8
D1_
MDQ20
B
GND008
GND009
GND010
GND011
GND012
IFC_
A25
IFC_
A27
IFC_
WE0_B
IFC_
RB0_B
IFC_
CS0_B
IFC_
OE_B
IFC_
CLE
IFC_
CS3_B
TBSCAN_
EN_B
D1_
MECC0
D1_
MDQ16
D1_
MDQ17
C
D
E
F
GND016
IFC_
A24
IFC_
A26
IFC_
RB1_B
IFC_
PAR1
IFC_
WP0_B
IFC_
CS2_B
D1_
MECC2
D1_
MECC3
D1_
MDQ21
D1_
MDQS2_B
GND022
IFC_BCTL
IRQ00
GND023
TCK
GND024
IFC_
NDDDR_
CLK
IFC_
TE
IFC_
PERR_B
TEST_
SEL_B
D1_
MDM2
D1_
MDQS2
EVT1_B
GND036
TRST_B
DDRCLK
TDO
GND028
GND029
TA_
PROG_
SFP
D1_
MDQ24
D1_
MDQ29
D1_
MDQ18
D1_
MDQ22
RTC
GND037
TMS
GND038 TAG_BSR_VSEL
TA_
TMP_
TA_BB_
TMP_
AVDD_
PLAT
PROG_
MTR
CLK_
OUT
D1_
TA_BB_RTC
D1_
D1_
G
H
J
G
H
J
IRQ01
TDI
GND041
GND042
MDQ28
MDM3
MDQ23
DETECT_B
DETECT_B
CKSTP_
OUT_B
D1_
MVREF
TA_BB_
VDD
D1_
MDQ25
D1_
MDQS3_B
D1_
MDQS3
D1_
MDQ04
D1_
MDQ19
GND051
OVDD2
VDD01
GND052
OVDD3
GND065
VDD06
GND053
OVDD4
VDD02
GND054
OVDD5
GND066
VDD07
GND055
OVDD6
VDD03
GND074
VDD12
D1_
D1_
MDQ31
D1_
MDQ26
D1_
MDQ00
G1VDD01
G1VDD02
G1VDD04
G1VDD05
GND057
GND067
GND075
GND083
GND058
G1VDD03
GND076
GND059
MDQ30
D1_
MDQ12
D1_
MDQ27
D1_
MDQ01
D1_
MDQ05
K
L
K
L
GND068
D1_
MDM1
D1_
MDQ13
D1_
MDQ08
D1_
MDM0
GND072
VDD10
GND073
VDD11
GND077
D1_
MDQ14
D1_
MDQ09
D1_
MDQS0
D1_
MDQS0_B
M
N
M
N
GND081
GND082
G1VDD06
GND084
D1_
MDQ10
D1_
MDQS1
D1_
MDQS1_B
D1_
MDQ02
D1_
MDQ06
GND090
VDD16
GND091
VDD17
GND092
G1VDD07
GND093
GND094
13
14
15
16
17
18
19
20
21
22
23
24
25
DDR Interface 1
Interrupts
SYSCLK
JTAG
IFC
DUART
Trust
eSPI
eSDHC
Battery Backed Tru
DDR Clocking
Analog Signals
Ethernet MI 1
USB
System Control
Debug
ASLEEP
DFT
RTC
Serdes 1
USB3 PHY 1
Ethernet Cont. 1
DIFF_SYSCLK
USB3 PHY 2
USB PHY 3
I2C
Ethernet MI 2
TA_BB_RTC
Ethernet Cont. 2
Power
Ground
No Connects
Figure 5. Detail B
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
7
Pin assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
IIC1_
SCL
IIC4_
SDA
GND085
GND086
IRQ09
GND087
OVDD7
VDD13
GND088
VDD14
GND089
VDD15
GND090
N
N
SDHC_
DAT0
SDHC_
CMD
SDHC_
CLK
TH_
TPA
TD1_
IRQ10
GND095
GND096
VDD23
VDD18
GND104
VDD29
GND097
VDD24
VDD19
GND105
VDD30
GND098
VDD25
VDD20
GND106
VDD31
LVDD2
CATHODE
P
P
SDHC_
DAT2
SDHC_
DAT1
SPI_
CLK
SPI_
MOSI
SPI_
MISO
TD1_
ANODE
FA_
VL
R
R
FA_
ANALOG_
PIN
SDHC_
DAT3
SPI_
CS0_B
SPI_
CS1_B
TH_
VDD
GND111
GND112
GND113
VDD32
GND114
VDD33
GND115
LVDD1
T
T
EC1_
RX_
CLK
EC1_
GTX_
CLK
FA_
ANALOG_
G_V
EC1_
RXD3
SPI_
CS3_B
SPI_
CS2_B
GND118
TVDD
GND119
GND124
GND120
GND126
U
U
EC1_
RXD2
EC1_
TXD3
EC1_
TXD2
SENSE
GND
GND122
IRQ11
GND123
GND125
GND127
GND128
V
V
SD1_
REF_
CLK1_N
SD1_
REF_
CLK1_P
AVDD_
SD1_
PLL1
SD1_
IMP_
CAL_RX
EC1_
RXD1
EC1_
RXD0
EC1_
TXD1
EMI1_
MDIO
EMI2_
MDIO
SENSE
VDD
SD_
GND06
SD_
GND07
GND131
W
W
Y
EC1_
RX_
DV
EC1_
TX_
EN
EC1_
TXD0
EMI1_
MDC
EMI2_
MDC
NC_
Y7
SD_
GND08
SD_
GND09
SD_
GND10
SD_
GND11
SD_
GND12
NC_
Y13
GND133
Y
EC2_
RX_
CLK
EC1_
GTX_
CLK125
EC2_
GTX_
CLK
EC2_
RXD3
NC_
AA5
NC_
AA6
NC_
AA7
NC_
AA8
NC_
AA9
NC_
AA10
NC_
AA11
NC_
AA12
SD_
GND18
AA
AA
AB
AC
AD
AE
EC2_
RXD2
EC2_
TXD3
NC_
AB5
NC_
AB6
NC_
AB7
NC_
AB8
NC_
AB9
NC_
NC_
NC_
SD_
GND135
GND136
AB10
AB11
AB12
GND21
AB
EC2_
RXD1
EC2_
RXD0
EC2_
TXD2
EC2_
TXD1
NC_
AC5
NC_
AC6
NC_
AC7
NC_
AC8
NC_
AC9
NC_
AC10
NC_
AC11
NC_
AC12
SD_
GND24
AC
EC2_
RX_
DV
EC2_
TXD0
NC_
AD5
NC_
AD6
NC_
AD7
NC_
AD8
NC_
AD9
NC_
AD10
NC_
AD11
NC_
AD12
SD_
GND32
GND137
GND138
AD
EC2_
TX_
EN
EC2_
GTX_
CLK125
NC_
AE5
NC_
AE6
NC_
AE7
NC_
AE8
NC_
AE9
NC_
AE10
NC_
AE11
NC_
AE12
SD_
GND36
GND139
AE
1
2
3
4
5
6
7
8
9
10
11
12
13
DDR Interface 1
Interrupts
SYSCLK
JTAG
IFC
DUART
Trust
eSPI
eSDHC
Battery Backed Tru
DDR Clocking
Analog Signals
Ethernet MI 1
USB
System Control
Debug
ASLEEP
DFT
RTC
Serdes 1
USB3 PHY 1
Ethernet Cont. 1
DIFF_SYSCLK
USB3 PHY 2
USB PHY 3
I2C
Ethernet MI 2
TA_BB_RTC
Ethernet Cont. 2
Power
Ground
No Connects
Figure 6. Detail C
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
8
NXP Semiconductors
Pin assignments
13
14
15
16
17
18
19
20
21
22
23
24
25
D1_
MDQ10
D1_
MDQS1
D1_
MDQS1_B
D1_
MDQ02
D1_
MDQ06
GND090
VDD16
GND091
VDD17
GND092
G1VDD07
GND093
GND094
N
N
D1_
D1_
D1_
VDD20
GND106
VDD31
LVDD2
GND099
VDD26
VDD21
GND107
S1VDD1
GND100
VDD27
VDD22
GND108
S1VDD3
G1VDD08
VDD28
GND101
GND109
G1VDD09
GND102
GND103
MDQ11
MDQ15
MDQ07
P
P
D1_
TPA
D1_
MA08
D1_
MDQ03
G1VDD10
G1VDD11
GND110
R
R
AVDD_
D1
D1_
MODT1
D1_
MA11
D1_
MA13
GND116
LVDD3
S1VDD2
S1VDD4
GND117
GND121
GND130
GND132
GND134
G1VDD18
G1VDD12
G1VDD13
T
T
D1_
MAPAR_
OUT
SD_
GND01
SD_
GND02
SD_
GND03
SD_
GND04
SD_
GND05
D1_
MA15
D1_
MODT0
D1_
MCS0_B
D1_
MA07
U
U
SD1_
PLL1_
TPD
SD1_
PLL1_
TPA
SD1_
PLL2_
TPD
SD1_
PLL2_
TPA
AVDD_
SD1_
PLL2
D1_
MCS1_B
D1_
MA02
D1_
MDIC0
GND128
GND129
S1VDD5
G1VDD14
G1VDD15
V
V
SD1_
IMP_
CAL_RX
SD1_
IMP_
CAL_TX
D1_
MCKE0
D1_
MA09
D1_
MA05
D1_
MCK1
D1_
MCK1_B
X1VDD1
X1VDD2
X1VDD3
X1VDD4
W
Y
W
Y
NC_
Y13
SD_
GND13
SD_
GND14
SD_
GND15
SD_
GND16
SD_
GND17
D1_
MWE_B
D1_
MBA1
D1_
MDIC1
X1VDD5
G1VDD16
G1VDD17
SD1_
TX0_
P
SD1_
TX1_
P
SD1_
TX2_
P
SD1_
TX3_
P
SD_
GND18
SD_
GND19
SD_
GND20
D1_
MA01
D1_
MCS3_B
D1_
MA04
D1_
MCK0
D1_
MCK0_B
AA
AB
AC
AD
AE
AA
AB
AC
AD
AE
SD1_
TX0_
N
SD1_
TX1_
N
SD1_
TX2_
N
SD1_
TX3_
N
SD_
SD_
SD_
D1_
D1_
D1_
D1_
G1VDD19
G1VDD20
GND21
GND22
GND23
MCS2_B
MCKE1
MA10
MRAS_B
SD_
GND24
SD_
GND25
SD_
GND26
SD_
GND27
SD_
GND28
SD_
GND29
SD_
GND30
SD_
GND31
D1_
MBA0
D1_
MCAS_B
D1_
MA12
D1_
MA06
D1_
MA00
SD1_
RX0_
N
SD1_
RX1_
N
SD1_
RX2_
N
SD1_
RX3_
N
SD1_
REF_
CLK2_N
D1_
MAPAR_
ERR_B
SD_
GND32
SD_
GND33
SD_
GND34
SD_
GND35
D1_
MA03
G1VDD21
G1VDD22
SD1_
RX0_
P
SD1_
RX1_
P
SD1_
RX2_
P
SD1_
RX3_
P
SD1_
REF_
CLK2_P
SD_
GND36
SD_
GND37
SD_
GND38
SD_
GND39
D1_
MA14
D1_
MBA2
G1VDD23
13
14
15
16
17
18
19
20
21
22
23
24
25
DDR Interface 1
Interrupts
SYSCLK
JTAG
IFC
DUART
Trust
eSPI
eSDHC
Battery Backed Tru
DDR Clocking
Analog Signals
Ethernet MI 1
USB
System Control
Debug
ASLEEP
DFT
RTC
Serdes 1
USB3 PHY 1
Ethernet Cont. 1
DIFF_SYSCLK
USB3 PHY 2
USB PHY 3
I2C
Ethernet MI 2
TA_BB_RTC
Ethernet Cont. 2
Power
Ground
No Connects
Figure 7. Detail D
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
9
Pin assignments
2.2 Pinout list (21x21)
This table provides the pinout listing for the LS1043A (21x21) by bus. Primary functions
are bolded in the table.
Table 1. Pinout list by bus
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
DDR SDRAM Memory Interface 1
D1_MA00
D1_MA01
D1_MA02
D1_MA03
D1_MA04
D1_MA05
D1_MA06
D1_MA07
D1_MA08
D1_MA09
D1_MA10
D1_MA11
D1_MA12
D1_MA13
D1_MA14
D1_MA15
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
AC25
AA21
V23
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
G1VDD
---
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
---
---
---
---
---
---
---
---
---
---
---
---
---
25
25
1, 6, 25
25
---
---
25
25
---
---
---
---
2
AD23
AA23
W23
AC24
U24
R22
W22
AB23
T23
AC23
T25
AE22
U21
D1_MAPAR_ERR_B
D1_MAPAR_OUT
D1_MBA0
Address Parity Error
Address Parity Out
Bank Select
AD24
U25
O
O
O
O
O
O
O
O
O
O
O
O
O
O
AC21
Y23
D1_MBA1
Bank Select
D1_MBA2
Bank Select
AE23
AC22
AA24
AA25
W24
W25
W21
AB21
U23
D1_MCAS_B
D1_MCK0
Column Address Strobe
Clock
D1_MCK0_B
D1_MCK1
Clock Complement
Clock
D1_MCK1_B
D1_MCKE0
D1_MCKE1
D1_MCS0_B
D1_MCS1_B
D1_MCS2_B
Clock Complement
Clock Enable
Clock Enable
Chip Select
2
---
---
---
Chip Select
V21
Chip Select
AB20
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
10
NXP Semiconductors
Pin assignments
Notes
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
D1_MCS3_B
Chip Select
AA22
V25
Y25
L25
L21
E23
G23
B22
J25
O
G1VDD
---
D1_MDIC0
D1_MDIC1
D1_MDM0
D1_MDM1
D1_MDM2
D1_MDM3
D1_MDM8
D1_MDQ00
D1_MDQ01
D1_MDQ02
D1_MDQ03
D1_MDQ04
D1_MDQ05
D1_MDQ06
D1_MDQ07
D1_MDQ08
D1_MDQ09
D1_MDQ10
D1_MDQ11
D1_MDQ12
D1_MDQ13
D1_MDQ14
D1_MDQ15
D1_MDQ16
D1_MDQ17
D1_MDQ18
D1_MDQ19
D1_MDQ20
D1_MDQ21
D1_MDQ22
D1_MDQ23
D1_MDQ24
D1_MDQ25
D1_MDQ26
D1_MDQ27
D1_MDQ28
D1_MDQ29
Driver Impedence Calibration
IO
IO
O
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
3
Driver Impedence Calibration
3
Data Mask
Data Mask
Data Mask
Data Mask
Data Mask
Data
1, 25
1, 25
1, 25
1, 25
1, 25
---
O
O
O
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Data
K24
N24
R24
H24
K25
N25
P25
L23
M23
N21
P21
K21
L22
M21
P23
C24
C25
F24
H25
B24
D24
F25
G25
F22
H21
J23
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
K23
G21
F23
---
Data
---
Data
---
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
11
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
D1_MDQ30
D1_MDQ31
D1_MDQS0
D1_MDQS0_B
D1_MDQS1
D1_MDQS1_B
D1_MDQS2
D1_MDQS2_B
D1_MDQS3
D1_MDQS3_B
D1_MDQS8
D1_MDQS8_B
D1_MECC0
D1_MECC1
D1_MECC2
D1_MECC3
D1_MODT0
D1_MODT1
D1_MRAS_B
D1_MWE_B
Data
Data
J21
J22
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
G1VDD
---
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
2
Data Strobe
M24
M25
N22
N23
E25
D25
H23
H22
B23
A23
C22
A22
D22
D23
U22
T21
AB25
Y21
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Error Correcting Code
Error Correcting Code
Error Correcting Code
Error Correcting Code
On Die Termination
On Die Termination
Row Address Strobe
Write Enable
O
2
O
25
25
O
Integrated Flash Controller
IFC_A16/QSPI_A_CS0
IFC_A17/QSPI_A_CS1
IFC_A18/QSPI_A_SCK
IFC_A19/QSPI_B_CS0
IFC_A20/QSPI_B_CS1
IFC Address
IFC Address
IFC Address
IFC Address
IFC Address
IFC Address
D8
C8
O
O
O
O
O
O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
1, 5
1, 5
1, 5
1, 5
1, 5
1, 4
C9
D10
C10
C11
IFC_A21/QSPI_B_SCK/
cfg_dram_type
IFC_A22/QSPI_A_DATA0/
IFC_WP1_B
IFC Address
IFC Address
IFC Address
IFC Address
D11
C12
D13
C13
O
O
O
O
OVDD
OVDD
OVDD
OVDD
1
1
1
1
IFC_A23/QSPI_A_DATA1/
IFC_WP2_B
IFC_A24/QSPI_A_DATA2/
IFC_WP3_B
IFC_A25/GPIO2_25/
QSPI_A_DATA3/FTM5_CH0/
IFC_CS4_B/IFC_RB2_B
IFC_A26/GPIO2_26/
FTM5_CH1/IFC_CS5_B/
IFC_RB3_B
IFC Address
D14
O
OVDD
1
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
12
NXP Semiconductors
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
IFC_A27/GPIO2_27/
IFC Address
C14
O
OVDD
1
FTM5_EXTCLK/IFC_CS6_B
IFC_AD00/cfg_gpinput0
IFC_AD01/cfg_gpinput1
IFC_AD02/cfg_gpinput2
IFC_AD03/cfg_gpinput3
IFC_AD04/cfg_gpinput4
IFC_AD05/cfg_gpinput5
IFC_AD06/cfg_gpinput6
IFC_AD07/cfg_gpinput7
IFC_AD08/cfg_rcw_src0
IFC_AD09/cfg_rcw_src1
IFC_AD10/cfg_rcw_src2
IFC_AD11/cfg_rcw_src3
IFC_AD12/cfg_rcw_src4
IFC_AD13/cfg_rcw_src5
IFC_AD14/cfg_rcw_src6
IFC_AD15/cfg_rcw_src7
IFC_AVD
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address Valid
IFC Buffer control
B8
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
4
A8
4
B9
4
A9
4
A10
B11
A11
B12
A12
A13
B14
A14
B15
A15
A16
A17
A18
E15
C19
4
4
4
4
4
4
4
4
4
4
4
4
1, 5
2
IFC_BCTL
O
IFC_CLE/cfg_rcw_src8
IFC Command Latch Enable /
Write Enable
O
1, 4
IFC_CLK0
IFC_CLK1
IFC_CS0_B
IFC Clock
A20
B20
C17
A19
O
O
O
O
OVDD
OVDD
OVDD
OVDD
2
IFC Clock
2
IFC Chip Select
IFC Chip Select
1, 6
1, 6
IFC_CS1_B/GPIO2_10/
FTM7_CH0
IFC_CS2_B/GPIO2_11/
FTM7_CH1
IFC Chip Select
IFC Chip Select
D20
C20
O
O
OVDD
OVDD
1, 6
1, 6
IFC_CS3_B/GPIO2_12/
QSPI_B_DATA3/
FTM7_EXTCLK
IFC_CS4_B/IFC_A25/
GPIO2_25/QSPI_A_DATA3/
FTM5_CH0/IFC_RB2_B
IFC Chip Select
IFC Chip Select
C13
D14
O
O
OVDD
OVDD
1
1
IFC_CS5_B/IFC_A26/
GPIO2_26/FTM5_CH1/
IFC_RB3_B
IFC_CS6_B/IFC_A27/
GPIO2_27/FTM5_EXTCLK
IFC Chip Select
C14
E16
O
O
OVDD
OVDD
1
2
IFC_NDDDR_CLK
IFC NAND DDR Clock
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
13
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
IFC_NDDQS
IFC DQS Strobe
B17
C18
B18
IO
O
OVDD
---
IFC_OE_B/cfg_eng_use1
IFC Output Enable
OVDD
OVDD
1, 4, 21
---
IFC_PAR0/GPIO2_13/
IFC Address & Data Parity
IO
QSPI_B_DATA0/FTM6_CH0
IFC_PAR1/GPIO2_14/
QSPI_B_DATA1/FTM6_CH1
IFC Address & Data Parity
IFC Parity Error
D17
E17
IO
I
OVDD
OVDD
---
1
IFC_PERR_B/GPIO2_15/
QSPI_B_DATA2/
FTM6_EXTCLK
IFC_RB0_B
IFC_RB1_B
IFC Ready / Busy CS0
IFC Ready / Busy CS1
IFC Ready/Busy CS 2
C16
D16
C13
I
I
I
OVDD
OVDD
OVDD
6
6
1
IFC_RB2_B/IFC_A25/
GPIO2_25/QSPI_A_DATA3/
FTM5_CH0/IFC_CS4_B
IFC_RB3_B/IFC_A26/
GPIO2_26/FTM5_CH1/
IFC_CS5_B
IFC Ready/Busy CS 3
D14
E14
I
OVDD
OVDD
1
IFC_TE/cfg_ifc_te
IFC External Transceiver
Enable
O
1, 4
IFC_WE0_B/cfg_eng_use0
IFC_WP0_B/cfg_eng_use2
IFC Write Enable
IFC Write Protect
IFC Write Protect
C15
D19
D11
O
O
O
OVDD
OVDD
OVDD
1, 4, 21
1, 4, 21
1
IFC_WP1_B/IFC_A22/
QSPI_A_DATA0
IFC_WP2_B/IFC_A23/
QSPI_A_DATA1
IFC Write Protect
IFC Write Protect
C12
D13
O
O
OVDD
OVDD
1
1
IFC_WP3_B/IFC_A24/
QSPI_A_DATA2
DUART
UART1_CTS_B/GPIO1_21/
UART3_SIN/FTM4_CH4/
LPUART2_SIN
Clear To Send
Ready to Send
J1
J2
I
DVDD
DVDD
1
1
UART1_RTS_B/GPIO1_19/
UART3_SOUT/
O
LPUART2_SOUT/FTM4_CH2
UART1_SIN/GPIO1_17
Receive Data
Transmit Data
Clear To Send
H2
H1
M2
I
O
I
DVDD
DVDD
DVDD
1
1
1
UART1_SOUT/GPIO1_15
UART2_CTS_B/GPIO1_22/
UART4_SIN/FTM4_CH5/
LPUART1_CTS_B/
LPUART4_SIN
UART2_RTS_B/GPIO1_20/
UART4_SOUT/
Ready to Send
L1
O
DVDD
1
LPUART4_SOUT/FTM4_CH3/
LPUART1_RTS_B
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
14
NXP Semiconductors
Pin assignments
Notes
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
UART2_SIN/GPIO1_18/
FTM4_CH1/LPUART1_SIN
Receive Data
Transmit Data
K1
L2
J1
I
O
I
DVDD
1
1
1
UART2_SOUT/GPIO1_16/
LPUART1_SOUT/FTM4_CH0
DVDD
DVDD
UART3_SIN/UART1_CTS_B/ Receive Data
GPIO1_21/FTM4_CH4/
LPUART2_SIN
UART3_SOUT/
UART1_RTS_B/GPIO1_19/
LPUART2_SOUT/FTM4_CH2
Transmit Data
J2
O
I
DVDD
DVDD
1
1
UART4_SIN/UART2_CTS_B/ Receive Data
GPIO1_22/FTM4_CH5/
M2
LPUART1_CTS_B/
LPUART4_SIN
UART4_SOUT/
Transmit Data
L1
O
DVDD
1
UART2_RTS_B/GPIO1_20/
LPUART4_SOUT/FTM4_CH3/
LPUART1_RTS_B
SPI Interface
SPI_CLK
SPI Clock
R3
T3
O
O
OVDD
OVDD
1
1
SPI_CS0_B/GPIO2_00/
SPI Chip Select
SDHC_DAT4/SDHC_VS
SPI_CS1_B/GPIO2_01/
SDHC_DAT5/
SDHC_CMD_DIR
SPI Chip Select
SPI Chip Select
SPI Chip Select
T5
U5
U3
O
O
O
OVDD
OVDD
OVDD
1
1
1
SPI_CS2_B/GPIO2_02/
SDHC_DAT6/
SDHC_DAT0_DIR
SPI_CS3_B/GPIO2_03/
SDHC_DAT7/
SDHC_DAT123_DIR
SPI_MISO/
SDHC_CLK_SYNC_IN
Master In Slave Out
Master Out Slave In
R5
R4
I
OVDD
OVDD
1
SPI_MOSI/
O
---
SDHC_CLK_SYNC_OUT
eSDHC
SDHC_CD_B/IIC2_SCL/
GPIO4_02/FTM3_QD_PHA/
CLK9/QE_SI1_STROBE0/
BRGO2
Command
Host to Card Clock
IN
K3
P3
R5
I
O
I
DVDD
EVDD
OVDD
1
1
1
SDHC_CLK/GPIO2_09/
LPUART3_CTS_B/
LPUART6_SIN/
FTM4_QD_PHB
SDHC_CLK_SYNC_IN/
SPI_MISO
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
15
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
SDHC_CLK_SYNC_OUT/
SPI_MOSI
OUT
Command/Response
R4
P2
T5
P1
U5
O
IO
O
OVDD
1
SDHC_CMD/GPIO2_04/
LPUART3_SOUT/FTM4_CH6
EVDD
OVDD
EVDD
OVDD
---
1
SDHC_CMD_DIR/SPI_CS1_B/ DIR
GPIO2_01/SDHC_DAT5
SDHC_DAT0/GPIO2_05/
FTM4_CH7/LPUART3_SIN
Data
DIR
IO
O
---
1
SDHC_DAT0_DIR/
SPI_CS2_B/GPIO2_02/
SDHC_DAT6
SDHC_DAT1/GPIO2_06/
LPUART5_SOUT/
FTM4_FAULT/
Data
R2
IO
EVDD
---
LPUART2_RTS_B
SDHC_DAT123_DIR/
SPI_CS3_B/GPIO2_03/
SDHC_DAT7
DIR
U3
R1
O
OVDD
EVDD
1
SDHC_DAT2/GPIO2_07/
LPUART2_CTS_B/
LPUART5_SIN/
Data
IO
---
FTM4_EXTCLK
SDHC_DAT3/GPIO2_08/
LPUART6_SOUT/
FTM4_QD_PHA/
Data
T1
IO
EVDD
---
LPUART3_RTS_B
SDHC_DAT4/SPI_CS0_B/
GPIO2_00/SDHC_VS
Data
Data
Data
Data
T3
T5
U5
U3
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
---
---
---
---
SDHC_DAT5/SPI_CS1_B/
GPIO2_01/SDHC_CMD_DIR
SDHC_DAT6/SPI_CS2_B/
GPIO2_02/SDHC_DAT0_DIR
SDHC_DAT7/SPI_CS3_B/
GPIO2_03/
SDHC_DAT123_DIR
SDHC_VS/SPI_CS0_B/
GPIO2_00/SDHC_DAT4
VS
T3
L3
O
I
OVDD
DVDD
1
1
SDHC_WP/IIC2_SDA/
GPIO4_03/FTM3_QD_PHB/
CLK10/QE_SI1_STROBE1/
BRGO3
Write Protect
Programmable Interrupt Controller
EVT9_B
IRQ00
Interrupt Output
H7
F15
G15
O
I
OVDD
OVDD
OVDD
1, 6, 7
External Interrupt
External Interrupt
1
1
IRQ01
I
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
16
NXP Semiconductors
Pin assignments
Notes
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
IRQ02
External Interrupt
J6
J3
I
I
OVDD
1
1
IRQ03/GPIO1_23/FTM3_CH7/ External Interrupt
TDMB_TSYNC/
UC3_RTSB_TXEN
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
IRQ04/GPIO1_24/FTM3_CH0/ External Interrupt
TDMA_RXD/UC1_RXD7/
TDMA_TXD
J4
J5
I
I
I
I
I
I
I
1
1
1
1
1
1
1
IRQ05/GPIO1_25/FTM3_CH1/ External Interrupt
TDMA_RSYNC/
UC1_CTSB_RXDV
IRQ06/GPIO1_26/FTM3_CH2/ External Interrupt
TDMA_RXD_EXC/
TDMA_TXD/UC1_TXD7
K5
L5
M5
N5
P4
V5
IRQ07/GPIO1_27/FTM3_CH3/ External Interrupt
TDMA_TSYNC/
UC1_RTSB_TXEN
IRQ08/GPIO1_28/FTM3_CH4/ External Interrupt
TDMB_RXD/UC3_RXD7/
TDMB_TXD
IRQ09/GPIO1_29/FTM3_CH5/ External Interrupt
TDMB_RSYNC/
UC3_CTSB_RXDV
IRQ10/GPIO1_30/FTM3_CH6/ External Interrupt
TDMB_RXD_EXC/
TDMB_TXD/UC3_TXD7
IRQ11/GPIO1_31
External Interrupt
I
I
I
LVDD
1
Battery Backed Trust
TA_BB_TMP_DETECT_B
TA_TMP_DETECT_B
Battery Backed Tamper Detect
Trust
G19
TA_BB_VDD
OVDD
---
1
Tamper Detect
G16
System Control
HRESET_B
Hard Reset
G10
F10
G7
IO
I
OVDD
OVDD
OVDD
6, 7
---
PORESET_B
RESET_REQ_B
Power On Reset
Reset Request (POR or Hard)
O
1, 5
Power Management
ASLEEP/GPIO1_13
SYSCLK
Asleep
E9
F9
O
I
OVDD
OVDD
OVDD
OVDD
1, 4
18
18
1
SYSCLK
System Clock
DDR Clocking
DDR Controller Clock
RTC
DDRCLK
F19
F16
I
RTC/GPIO1_14
Real Time Clock
Debug
I
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
17
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
CKSTP_OUT_B
CLK_OUT
EVT0_B
Reserved
H18
G17
E10
E13
E8
O
O
OVDD
6, 7
Clock Out
Event 0
Event 1
Event 2
Event 3
Event 4
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
DVDD
2
IO
IO
IO
IO
IO
IO
9
EVT1_B
---
---
---
---
---
EVT2_B
EVT3_B
E12
E11
L4
EVT4_B
EVT5_B/IIC3_SCL/GPIO4_10/ Event 5
USB2_DRVVBUS/BRGO4/
FTM8_CH0/CLK11
EVT6_B/IIC3_SDA/GPIO4_11/ Event 6
USB2_PWRFAULT/BRGO1/
FTM8_CH1/CLK12_CLK8
M4
M3
IO
IO
DVDD
DVDD
---
---
EVT7_B/IIC4_SCL/GPIO4_12/ Event 7
USB3_DRVVBUS/TDMA_RQ/
FTM3_FAULT/
UC1_CDB_RXER
EVT8_B/IIC4_SDA/GPIO4_13/ Event 8
USB3_PWRFAULT/
N3
IO
DVDD
---
TDMB_RQ/FTM3_EXTCLK/
UC3_CDB_RXER
DFT
JTAG_BSR_VSEL
An IEEE 1149.1 JTAG
compliance enable pin. 0:
F21
I
OVDD
36
Normal operation. 1: To be
compliant to the 1149.1
specification for boundary scan
functions. The JTAG compliant
state is documented in the
BSDL.
SCAN_MODE_B
TBSCAN_EN_B
Reserved
A21
C21
I
I
OVDD
OVDD
10
35
An IEEE 1149.1 JTAG
compliance enable pin. 0:To be
compliant to the 1149.1
specification for boundary scan
functions. The JTAG compliant
state is documented in the
BSDL. 1: JTAG connects to
DAP controller for the ARM
core debug.
TEST_SEL_B
Reserved
JTAG
E21
I
OVDD
23
TCK
TDI
Test Clock
Test Data In
Test Data Out
E18
G18
E20
I
I
OVDD
OVDD
OVDD
---
9
TDO
O
2
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
18
NXP Semiconductors
Pin assignments
Notes
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
TMS
Test Mode Select
F18
E19
I
I
OVDD
9
9
TRST_B
Test Reset
OVDD
Analog Signals
D1_MVREF
D1_TPA
SSTL Reference Voltage
H19
R20
IO
IO
G1VDD/2
---
DDR Controller 1 Test Point
Analog
12
FA_ANALOG_G_V
FA_ANALOG_PIN
TD1_ANODE
Reserved
U7
T7
R6
P6
P5
IO
IO
IO
IO
-
15
15
17
17
12
Reserved
Thermal diode anode
Thermal diode cathode
Thermal Test Point Analog
TD1_CATHODE
TH_TPA
-
SerDes
SD1_IMP_CAL_RX
SD1_IMP_CAL_TX
SD1_PLL1_TPA
SerDes Receive Impedence
Calibration
W13
W19
V16
I
I
S1VDD
11
16
12
SerDes Transmit Impedance
Calibration
X1VDD
SerDes PLL 1 Test Point
Analog
O
AVDD_SD1_PLL1
SD1_PLL1_TPD
SD1_PLL2_TPA
SerDes Test Point Digital
V15
V18
O
O
X1VDD
12
12
SerDes PLL 2 Test Point
Analog
AVDD_SD1_PLL2
SD1_PLL2_TPD
SerDes Test Point Digital
V17
W9
O
I
X1VDD
S1VDD
12
---
SD1_REF_CLK1_N
SerDes PLL 1 Reference Clock
Complement
SD1_REF_CLK1_P
SD1_REF_CLK2_N
SerDes PLL 1 Reference Clock
W10
I
I
S1VDD
S1VDD
---
---
SerDes PLL 2 Reference Clock
Complement
AD20
SD1_REF_CLK2_P
SD1_RX0_N
SerDes PLL 2 Reference Clock
AE20
AD14
I
I
S1VDD
S1VDD
---
---
SerDes Receive Data
(negative)
SD1_RX0_P
SD1_RX1_N
SD1_RX1_P
SD1_RX2_N
SD1_RX2_P
SD1_RX3_N
SerDes Receive Data
(positive)
AE14
AD15
AE15
AD17
AE17
AD18
I
I
I
I
I
I
S1VDD
S1VDD
S1VDD
S1VDD
S1VDD
S1VDD
---
---
---
---
---
---
SerDes Receive Data
(negative)
SerDes Receive Data
(positive)
SerDes Receive Data
(negative)
SerDes Receive Data
(positive)
SerDes Receive Data
(negative)
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
19
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
SD1_RX3_P
SD1_TX0_N
SD1_TX0_P
SD1_TX1_N
SD1_TX1_P
SD1_TX2_N
SD1_TX2_P
SD1_TX3_N
SD1_TX3_P
SerDes Receive Data
(positive)
AE18
AB14
AA14
AB15
AA15
AB17
AA17
AB18
AA18
I
S1VDD
---
SerDes Transmit Data
(negative)
O
O
O
O
O
O
O
O
X1VDD
X1VDD
X1VDD
X1VDD
X1VDD
X1VDD
X1VDD
X1VDD
---
---
---
---
---
---
---
---
SerDes Transmit Data
(positive)
SerDes Transmit Data
(negative)
SerDes Transmit Data
(positive)
SerDes Transmit Data
(negative)
SerDes Transmit Data
(positive)
SerDes Transmit Data
(negative)
SerDes Transmit Data
(positive)
USB3 PHY 1
USB1_D_M
USB1_D_P
USB1_ID
USB PHY HS Data (-)
USB PHY HS Data (+)
USB PHY ID Detect
E6
F6
F5
G3
IO
IO
I
USB_HVDD
---
---
29
27
USB_HVDD
-
-
USB1_RESREF
USB PHY Impedance
Calibration
IO
USB1_RX_M
USB1_RX_P
USB1_TX_M
USB1_TX_P
USB PHY SS Receive Data (-)
USB PHY SS Receive Data (+)
USB PHY SS Transmit Data (-)
E4
E3
F2
F1
I
USB_SVDD
USB_SVDD
USB_SVDD
USB_SVDD
---
---
---
---
I
O
O
USB PHY SS Transmit Data
(+)
USB1_VBUS
USB PHY VBUS
E7
I
-
28
USB3 PHY 2
USB2_D_M
USB2_D_P
USB2_ID
USB PHY HS Data (-)
USB PHY HS Data (+)
USB PHY ID Detect
C6
D6
D5
G4
IO
IO
I
USB_HVDD
---
---
29
27
USB_HVDD
-
-
USB2_RESREF
USB PHY Impedance
Calibration
IO
USB2_RX_M
USB2_RX_P
USB2_TX_M
USB2_TX_P
USB PHY SS Receive Data (-)
USB PHY SS Receive Data (+)
USB PHY SS Transmit Data (-)
C4
C3
D2
D1
I
USB_SVDD
USB_SVDD
USB_SVDD
USB_SVDD
---
---
---
---
I
O
O
USB PHY SS Transmit Data
(+)
USB2_VBUS
USB PHY VBUS
C7
I
-
28
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
20
NXP Semiconductors
Pin assignments
Notes
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
USB3 PHY 3
USB3_D_M
USB3_D_P
USB3_ID
USB PHY HS Data (-)
USB PHY HS Data (+)
USB PHY ID Detect
A6
B6
B5
G5
IO
IO
I
USB_HVDD
---
---
29
27
USB_HVDD
-
-
USB3_RESREF
USB PHY Impedance
Calibration
IO
USB3_RX_M
USB3_RX_P
USB3_TX_M
USB3_TX_P
USB PHY SS Receive Data (-)
USB PHY SS Receive Data (+)
USB PHY SS Transmit Data (-)
A4
A3
B2
B1
I
USB_SVDD
USB_SVDD
USB_SVDD
USB_SVDD
---
---
---
---
I
O
O
USB PHY SS Transmit Data
(+)
USB3_VBUS
USB PHY VBUS
A7
I
-
28
Ethernet Management Interface 1
EMI1_MDC/GPIO3_00
EMI1_MDIO/GPIO3_01
Management Data Clock
Management Data In/Out
Y5
O
LVDD
LVDD
1
W5
IO
---
Ethernet Management Interface 2
EMI2_MDC/GPIO4_00
EMI2_MDIO/GPIO4_01
Management Data Clock
Y6
O
TVDD
TVDD
1
Management Data In/Out
Transmit Clock Out
W6
IO
---
Ethernet Controller 1
EC1_GTX_CLK/GPIO3_07/
U4
O
LVDD
1
FTM1_EXTCLK
EC1_GTX_CLK125/GPIO3_08 Reference Clock
AA3
W2
I
I
LVDD
LVDD
1
1
EC1_RXD0/GPIO3_12/
Receive Data
Receive Data
Receive Data
Receive Data
Receive Clock
Receive Data Valid
Transmit Data
Transmit Data
Transmit Data
Transmit Data
FTM1_CH0
EC1_RXD1/GPIO3_11/
FTM1_CH1
W1
V1
U2
U1
Y1
Y3
W3
V4
V3
I
I
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
1
1
1
1
1
1
1
1
1
EC1_RXD2/GPIO3_10/
FTM1_CH6
EC1_RXD3/GPIO3_09/
FTM1_CH4
I
EC1_RX_CLK/GPIO3_13/
FTM1_QD_PHA
I
EC1_RX_DV/GPIO3_14/
FTM1_QD_PHB
I
EC1_TXD0/GPIO3_05/
FTM1_CH2
O
O
O
O
EC1_TXD1/GPIO3_04/
FTM1_CH3
EC1_TXD2/GPIO3_03/
FTM1_CH7
EC1_TXD3/GPIO3_02/
FTM1_CH5
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
21
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
EC1_TX_EN/GPIO3_06/
FTM1_FAULT
Transmit Enable
Y4
O
O
LVDD
1, 14
Ethernet Controller 2
EC2_GTX_CLK/GPIO3_20/
Transmit Clock Out
AA4
LVDD
1
FTM2_EXTCLK
EC2_GTX_CLK125/GPIO3_21 Reference Clock
AE4
AC2
I
I
LVDD
LVDD
1
1
EC2_RXD0/GPIO3_25/
TSEC_1588_TRIG_IN2/
FTM2_CH0
Receive Data
EC2_RXD1/GPIO3_24/
TSEC_1588_PULSE_OUT1/
FTM2_CH1
Receive Data
AC1
I
LVDD
1
EC2_RXD2/GPIO3_23/
FTM2_CH6
Receive Data
Receive Data
Receive Clock
AB1
AA2
AA1
I
I
I
LVDD
LVDD
LVDD
1
1
1
EC2_RXD3/GPIO3_22/
FTM2_CH4
EC2_RX_CLK/GPIO3_26/
TSEC_1588_CLK_IN/
FTM2_QD_PHA
EC2_RX_DV/GPIO3_27/
TSEC_1588_TRIG_IN1/
FTM2_QD_PHB
Receive Data Valid
Transmit Data
Transmit Data
Transmit Data
Transmit Data
Transmit Enable
AD2
AD3
AC4
AC3
AB3
AE3
I
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
1
EC2_TXD0/GPIO3_18/
TSEC_1588_PULSE_OUT2/
FTM2_CH2
O
O
O
O
O
1
EC2_TXD1/GPIO3_17/
TSEC_1588_CLK_OUT/
FTM2_CH3
1
EC2_TXD2/GPIO3_16/
TSEC_1588_ALARM_OUT1/
FTM2_CH7
1
EC2_TXD3/GPIO3_15/
TSEC_1588_ALARM_OUT2/
FTM2_CH5
1
EC2_TX_EN/GPIO3_19/
1, 14
FTM2_FAULT
I2C
IIC1_SCL
IIC1_SDA
Serial Clock (supports PBL)
Serial Data (supports PBL)
Serial Clock
N1
M1
K3
IO
IO
IO
DVDD
DVDD
DVDD
7, 8
7, 8
7, 8
IIC2_SCL/GPIO4_02/
SDHC_CD_B/FTM3_QD_PHA/
CLK9/QE_SI1_STROBE0/
BRGO2
IIC2_SDA/GPIO4_03/
Serial Data
L3
IO
DVDD
7, 8
SDHC_WP/FTM3_QD_PHB/
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
22
NXP Semiconductors
Pin assignments
Notes
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
CLK10/QE_SI1_STROBE1/
BRGO3
IIC3_SCL/GPIO4_10/EVT5_B/ Serial Clock
USB2_DRVVBUS/BRGO4/
FTM8_CH0/CLK11
L4
M4
M3
IO
IO
IO
DVDD
7, 8
7, 8
7, 8
IIC3_SDA/GPIO4_11/EVT6_B/ Serial Data
USB2_PWRFAULT/BRGO1/
FTM8_CH1/CLK12_CLK8
DVDD
DVDD
IIC4_SCL/GPIO4_12/EVT7_B/ Serial Clock
USB3_DRVVBUS/TDMA_RQ/
FTM3_FAULT/
UC1_CDB_RXER
IIC4_SDA/GPIO4_13/EVT8_B/ Serial Data
USB3_PWRFAULT/
N3
IO
DVDD
7, 8
TDMB_RQ/FTM3_EXTCLK/
UC3_CDB_RXER
USB
USB2_DRVVBUS/IIC3_SCL/ DRV VBus
GPIO4_10/EVT5_B/BRGO4/
FTM8_CH0/CLK11
L4
M4
M3
O
I
DVDD
DVDD
DVDD
1
1
1
USB2_PWRFAULT/IIC3_SDA/ PWR Fault
GPIO4_11/EVT6_B/BRGO1/
FTM8_CH1/CLK12_CLK8
USB3_DRVVBUS/IIC4_SCL/ DRV Bus
GPIO4_12/EVT7_B/
O
TDMA_RQ/FTM3_FAULT/
UC1_CDB_RXER
USB3_PWRFAULT/IIC4_SDA/ PWR Fault
GPIO4_13/EVT8_B/
N3
I
DVDD
1
TDMB_RQ/FTM3_EXTCLK/
UC3_CDB_RXER
USB_DRVVBUS/GPIO4_29
USB_DRVVBUS
H6
G6
O
I
DVDD
DVDD
1
1
USB_PWRFAULT/GPIO4_30 USB_PWRFAULT
Battery Backed RTC
G20
TA_BB_RTC
Reserved
I
TA_BB_VDD
33
DSYSCLK
DIFF_SYSCLK
Single Source System Clock
Differential (positive)
G8
G9
I
I
OVDD
OVDD
19
19
DIFF_SYSCLK_B
Single Source System Clock
Differential (negative)
Power-On-Reset Configuration
cfg_dram_type/IFC_A21/
Power-on-Reset Configuration
C11
I
OVDD
1, 4
QSPI_B_SCK
cfg_eng_use0/IFC_WE0_B
cfg_eng_use1/IFC_OE_B
Power-on-Reset Configuration
Power-on-Reset Configuration
C15
C18
I
I
OVDD
OVDD
1, 4
1, 4
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
23
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
cfg_eng_use2/IFC_WP0_B
cfg_gpinput0/IFC_AD00
cfg_gpinput1/IFC_AD01
cfg_gpinput2/IFC_AD02
cfg_gpinput3/IFC_AD03
cfg_gpinput4/IFC_AD04
cfg_gpinput5/IFC_AD05
cfg_gpinput6/IFC_AD06
cfg_gpinput7/IFC_AD07
cfg_ifc_te/IFC_TE
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
D19
B8
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
OVDD
1, 4
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
A8
B9
A9
A10
B11
A11
B12
E14
A12
A13
B14
A14
B15
A15
A16
A17
C19
cfg_rcw_src0/IFC_AD08
cfg_rcw_src1/IFC_AD09
cfg_rcw_src2/IFC_AD10
cfg_rcw_src3/IFC_AD11
cfg_rcw_src4/IFC_AD12
cfg_rcw_src5/IFC_AD13
cfg_rcw_src6/IFC_AD14
cfg_rcw_src7/IFC_AD15
cfg_rcw_src8/IFC_CLE
General Purpose Input/Output
GPIO1_13/ASLEEP
GPIO1_14/RTC
General Purpose Input/Output
E9
F16
H1
L2
O
OVDD
OVDD
DVDD
DVDD
1, 4
---
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
IO
IO
IO
GPIO1_15/UART1_SOUT
---
GPIO1_16/UART2_SOUT/
---
LPUART1_SOUT/FTM4_CH0
GPIO1_17/UART1_SIN
General Purpose Input/Output
General Purpose Input/Output
H2
K1
IO
IO
DVDD
DVDD
---
---
GPIO1_18/UART2_SIN/
FTM4_CH1/LPUART1_SIN
GPIO1_19/UART1_RTS_B/
UART3_SOUT/
LPUART2_SOUT/FTM4_CH2
General Purpose Input/Output
General Purpose Input/Output
J2
L1
IO
IO
DVDD
DVDD
---
---
GPIO1_20/UART2_RTS_B/
UART4_SOUT/
LPUART4_SOUT/FTM4_CH3/
LPUART1_RTS_B
GPIO1_21/UART1_CTS_B/
UART3_SIN/FTM4_CH4/
LPUART2_SIN
General Purpose Input/Output
General Purpose Input/Output
J1
IO
IO
DVDD
DVDD
---
---
GPIO1_22/UART2_CTS_B/
M2
UART4_SIN/FTM4_CH5/
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
24
NXP Semiconductors
Pin assignments
Notes
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
LPUART1_CTS_B/
LPUART4_SIN
GPIO1_23/IRQ03/FTM3_CH7/ General Purpose Input/Output
TDMB_TSYNC/
UC3_RTSB_TXEN
J3
J4
IO
IO
IO
IO
IO
IO
IO
IO
DVDD
---
---
---
---
---
---
---
---
GPIO1_24/IRQ04/FTM3_CH0/ General Purpose Input/Output
TDMA_RXD/UC1_RXD7/
TDMA_TXD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
GPIO1_25/IRQ05/FTM3_CH1/ General Purpose Input/Output
TDMA_RSYNC/
UC1_CTSB_RXDV
J5
GPIO1_26/IRQ06/FTM3_CH2/ General Purpose Input/Output
TDMA_RXD_EXC/
TDMA_TXD/UC1_TXD7
K5
L5
M5
N5
P4
GPIO1_27/IRQ07/FTM3_CH3/ General Purpose Input/Output
TDMA_TSYNC/
UC1_RTSB_TXEN
GPIO1_28/IRQ08/FTM3_CH4/ General Purpose Input/Output
TDMB_RXD/UC3_RXD7/
TDMB_TXD
GPIO1_29/IRQ09/FTM3_CH5/ General Purpose Input/Output
TDMB_RSYNC/
UC3_CTSB_RXDV
GPIO1_30/IRQ10/FTM3_CH6/ General Purpose Input/Output
TDMB_RXD_EXC/
TDMB_TXD/UC3_TXD7
GPIO1_31/IRQ11
General Purpose Input/Output
General Purpose Input/Output
V5
T3
IO
IO
LVDD
OVDD
---
---
GPIO2_00/SPI_CS0_B/
SDHC_DAT4/SDHC_VS
GPIO2_01/SPI_CS1_B/
SDHC_DAT5/
SDHC_CMD_DIR
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
T5
U5
U3
IO
IO
IO
OVDD
OVDD
OVDD
---
---
---
GPIO2_02/SPI_CS2_B/
SDHC_DAT6/
SDHC_DAT0_DIR
GPIO2_03/SPI_CS3_B/
SDHC_DAT7/
SDHC_DAT123_DIR
GPIO2_04/SDHC_CMD/
LPUART3_SOUT/FTM4_CH6
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
P2
P1
R2
IO
IO
IO
EVDD
EVDD
EVDD
---
---
---
GPIO2_05/SDHC_DAT0/
FTM4_CH7/LPUART3_SIN
GPIO2_06/SDHC_DAT1/
LPUART5_SOUT/
FTM4_FAULT/
LPUART2_RTS_B
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
25
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
GPIO2_07/SDHC_DAT2/
LPUART2_CTS_B/
LPUART5_SIN/
General Purpose Input/Output
R1
T1
P3
IO
IO
IO
EVDD
---
FTM4_EXTCLK
GPIO2_08/SDHC_DAT3/
LPUART6_SOUT/
FTM4_QD_PHA/
General Purpose Input/Output
General Purpose Input/Output
EVDD
---
---
LPUART3_RTS_B
GPIO2_09/SDHC_CLK/
LPUART3_CTS_B/
LPUART6_SIN/
EVDD
FTM4_QD_PHB
GPIO2_10/IFC_CS1_B/
FTM7_CH0
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
A19
D20
C20
IO
IO
IO
OVDD
OVDD
OVDD
---
---
---
GPIO2_11/IFC_CS2_B/
FTM7_CH1
GPIO2_12/IFC_CS3_B/
QSPI_B_DATA3/
FTM7_EXTCLK
GPIO2_13/IFC_PAR0/
QSPI_B_DATA0/FTM6_CH0
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
B18
D17
E17
IO
IO
IO
OVDD
OVDD
OVDD
---
---
---
GPIO2_14/IFC_PAR1/
QSPI_B_DATA1/FTM6_CH1
GPIO2_15/IFC_PERR_B/
QSPI_B_DATA2/
FTM6_EXTCLK
GPIO2_25/IFC_A25/
QSPI_A_DATA3/FTM5_CH0/
IFC_CS4_B/IFC_RB2_B
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
C13
D14
C14
IO
IO
IO
OVDD
OVDD
OVDD
---
---
---
GPIO2_26/IFC_A26/
FTM5_CH1/IFC_CS5_B/
IFC_RB3_B
GPIO2_27/IFC_A27/
FTM5_EXTCLK/IFC_CS6_B
GPIO3_00/EMI1_MDC
GPIO3_01/EMI1_MDIO
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
Y5
W5
V3
IO
IO
IO
LVDD
LVDD
LVDD
---
---
---
GPIO3_02/EC1_TXD3/
FTM1_CH5
GPIO3_03/EC1_TXD2/
FTM1_CH7
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
V4
W3
Y3
Y4
IO
IO
IO
IO
LVDD
LVDD
LVDD
LVDD
---
---
---
---
GPIO3_04/EC1_TXD1/
FTM1_CH3
GPIO3_05/EC1_TXD0/
FTM1_CH2
GPIO3_06/EC1_TX_EN/
FTM1_FAULT
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
26
NXP Semiconductors
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
GPIO3_07/EC1_GTX_CLK/
General Purpose Input/Output
U4
IO
LVDD
---
FTM1_EXTCLK
GPIO3_08/EC1_GTX_CLK125 General Purpose Input/Output
AA3
U2
IO
IO
LVDD
LVDD
---
---
GPIO3_09/EC1_RXD3/
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
FTM1_CH4
GPIO3_10/EC1_RXD2/
FTM1_CH6
V1
W1
W2
U1
IO
IO
IO
IO
IO
IO
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
---
---
---
---
---
---
GPIO3_11/EC1_RXD1/
FTM1_CH1
GPIO3_12/EC1_RXD0/
FTM1_CH0
GPIO3_13/EC1_RX_CLK/
FTM1_QD_PHA
GPIO3_14/EC1_RX_DV/
Y1
FTM1_QD_PHB
GPIO3_15/EC2_TXD3/
TSEC_1588_ALARM_OUT2/
FTM2_CH5
AB3
GPIO3_16/EC2_TXD2/
TSEC_1588_ALARM_OUT1/
FTM2_CH7
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
AC3
AC4
AD3
IO
IO
IO
LVDD
LVDD
LVDD
---
---
---
GPIO3_17/EC2_TXD1/
TSEC_1588_CLK_OUT/
FTM2_CH3
GPIO3_18/EC2_TXD0/
TSEC_1588_PULSE_OUT2/
FTM2_CH2
GPIO3_19/EC2_TX_EN/
FTM2_FAULT
General Purpose Input/Output
General Purpose Input/Output
AE3
AA4
IO
IO
LVDD
LVDD
---
---
GPIO3_20/EC2_GTX_CLK/
FTM2_EXTCLK
GPIO3_21/EC2_GTX_CLK125 General Purpose Input/Output
AE4
AA2
IO
IO
LVDD
LVDD
---
---
GPIO3_22/EC2_RXD3/
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
FTM2_CH4
GPIO3_23/EC2_RXD2/
AB1
AC1
IO
IO
LVDD
LVDD
---
---
FTM2_CH6
GPIO3_24/EC2_RXD1/
TSEC_1588_PULSE_OUT1/
FTM2_CH1
GPIO3_25/EC2_RXD0/
TSEC_1588_TRIG_IN2/
FTM2_CH0
General Purpose Input/Output
General Purpose Input/Output
AC2
AA1
IO
IO
LVDD
LVDD
---
---
GPIO3_26/EC2_RX_CLK/
TSEC_1588_CLK_IN/
FTM2_QD_PHA
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
27
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
GPIO3_27/EC2_RX_DV/
TSEC_1588_TRIG_IN1/
FTM2_QD_PHB
General Purpose Input/Output
AD2
IO
LVDD
---
GPIO4_00/EMI2_MDC
GPIO4_01/EMI2_MDIO
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
Y6
W6
K3
IO
IO
IO
TVDD
TVDD
DVDD
---
---
---
GPIO4_02/IIC2_SCL/
SDHC_CD_B/FTM3_QD_PHA/
CLK9/QE_SI1_STROBE0/
BRGO2
GPIO4_03/IIC2_SDA/
SDHC_WP/FTM3_QD_PHB/
CLK10/QE_SI1_STROBE1/
BRGO3
General Purpose Input/Output
L3
IO
DVDD
---
GPIO4_10/IIC3_SCL/EVT5_B/ General Purpose Input/Output
USB2_DRVVBUS/BRGO4/
FTM8_CH0/CLK11
L4
M4
M3
IO
IO
IO
DVDD
DVDD
DVDD
---
---
---
GPIO4_11/IIC3_SDA/EVT6_B/ General Purpose Input/Output
USB2_PWRFAULT/BRGO1/
FTM8_CH1/CLK12_CLK8
GPIO4_12/IIC4_SCL/EVT7_B/ General Purpose Input/Output
USB3_DRVVBUS/TDMA_RQ/
FTM3_FAULT/
UC1_CDB_RXER
GPIO4_13/IIC4_SDA/EVT8_B/ General Purpose Input/Output
USB3_PWRFAULT/
N3
IO
DVDD
---
TDMB_RQ/FTM3_EXTCLK/
UC3_CDB_RXER
GPIO4_29/USB_DRVVBUS
General Purpose Input/Output
H6
G6
IO
IO
DVDD
DVDD
---
---
GPIO4_30/USB_PWRFAULT General Purpose Input/Output
Frequency Timer Module 1
FTM1_CH0/EC1_RXD0/
GPIO3_12
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
W2
IO
IO
IO
IO
IO
IO
IO
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
---
---
---
---
---
---
---
FTM1_CH1/EC1_RXD1/
GPIO3_11
W1
Y3
W3
U2
V3
V1
FTM1_CH2/EC1_TXD0/
GPIO3_05
FTM1_CH3/EC1_TXD1/
GPIO3_04
FTM1_CH4/EC1_RXD3/
GPIO3_09
FTM1_CH5/EC1_TXD3/
GPIO3_02
FTM1_CH6/EC1_RXD2/
GPIO3_10
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
28
NXP Semiconductors
Pin assignments
Notes
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
FTM1_CH7/EC1_TXD2/
GPIO3_03
Channel 7
V4
U4
Y4
U1
Y1
IO
LVDD
---
1
FTM1_EXTCLK/
EC1_GTX_CLK/GPIO3_07
Ext Clock
Fault
I
I
I
I
LVDD
LVDD
LVDD
LVDD
FTM1_FAULT/EC1_TX_EN/
GPIO3_06
1
FTM1_QD_PHA/
EC1_RX_CLK/GPIO3_13
Phase A
1
FTM1_QD_PHB/EC1_RX_DV/ Phase B
1
GPIO3_14
Frequency Timer Module 2
FTM2_CH0/EC2_RXD0/
GPIO3_25/
TSEC_1588_TRIG_IN2
Channel 0
Channel 1
Channel 2
Channel 3
AC2
IO
IO
IO
IO
LVDD
LVDD
LVDD
LVDD
---
---
---
---
FTM2_CH1/EC2_RXD1/
GPIO3_24/
TSEC_1588_PULSE_OUT1
AC1
AD3
AC4
FTM2_CH2/EC2_TXD0/
GPIO3_18/
TSEC_1588_PULSE_OUT2
FTM2_CH3/EC2_TXD1/
GPIO3_17/
TSEC_1588_CLK_OUT
FTM2_CH4/EC2_RXD3/
GPIO3_22
Channel 4
Channel 5
AA2
AB3
IO
IO
LVDD
LVDD
---
---
FTM2_CH5/EC2_TXD3/
GPIO3_15/
TSEC_1588_ALARM_OUT2
FTM2_CH6/EC2_RXD2/
GPIO3_23
Channel 6
Channel 7
AB1
AC3
IO
IO
LVDD
LVDD
---
---
FTM2_CH7/EC2_TXD2/
GPIO3_16/
TSEC_1588_ALARM_OUT1
FTM2_EXTCLK/
EC2_GTX_CLK/GPIO3_20
Ext Clock
Fault
AA4
AE3
AA1
I
I
I
LVDD
LVDD
LVDD
1
1
1
FTM2_FAULT/EC2_TX_EN/
GPIO3_19
FTM2_QD_PHA/
Phase A
EC2_RX_CLK/GPIO3_26/
TSEC_1588_CLK_IN
FTM2_QD_PHB/EC2_RX_DV/ Phase B
GPIO3_27/
AD2
I
LVDD
1
TSEC_1588_TRIG_IN1
Frequency Timer Module 3
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
29
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
FTM3_CH0/IRQ04/GPIO1_24/ Channel 0
TDMA_RXD/UC1_RXD7/
TDMA_TXD
J4
IO
IO
IO
IO
IO
IO
IO
IO
I
DVDD
---
FTM3_CH1/IRQ05/GPIO1_25/ Channel 1
TDMA_RSYNC/
UC1_CTSB_RXDV
J5
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
---
---
---
---
---
---
---
1
FTM3_CH2/IRQ06/GPIO1_26/ Channel 2
TDMA_RXD_EXC/
TDMA_TXD/UC1_TXD7
K5
L5
M5
N5
P4
J3
FTM3_CH3/IRQ07/GPIO1_27/ Channel 3
TDMA_TSYNC/
UC1_RTSB_TXEN
FTM3_CH4/IRQ08/GPIO1_28/ Channel 4
TDMB_RXD/UC3_RXD7/
TDMB_TXD
FTM3_CH5/IRQ09/GPIO1_29/ Channel 5
TDMB_RSYNC/
UC3_CTSB_RXDV
FTM3_CH6/IRQ10/GPIO1_30/ Channel 6
TDMB_RXD_EXC/
TDMB_TXD/UC3_TXD7
FTM3_CH7/IRQ03/GPIO1_23/ Channel 7
TDMB_TSYNC/
UC3_RTSB_TXEN
FTM3_EXTCLK/IIC4_SDA/
GPIO4_13/EVT8_B/
Ext Clock
N3
USB3_PWRFAULT/
TDMB_RQ/UC3_CDB_RXER
FTM3_FAULT/IIC4_SCL/
GPIO4_12/EVT7_B/
USB3_DRVVBUS/TDMA_RQ/
UC1_CDB_RXER
Fault
M3
K3
L3
I
I
I
DVDD
DVDD
DVDD
1
1
1
FTM3_QD_PHA/IIC2_SCL/
GPIO4_02/SDHC_CD_B/
CLK9/QE_SI1_STROBE0/
BRGO2
Phase A
Phase B
FTM3_QD_PHB/IIC2_SDA/
GPIO4_03/SDHC_WP/CLK10/
QE_SI1_STROBE1/BRGO3
Frequency Timer Module 4
FTM4_CH0/UART2_SOUT/
GPIO1_16/LPUART1_SOUT
Channel 0
Channel 1
Channel 2
L2
IO
IO
IO
DVDD
DVDD
DVDD
---
---
---
FTM4_CH1/UART2_SIN/
GPIO1_18/LPUART1_SIN
K1
J2
FTM4_CH2/UART1_RTS_B/
GPIO1_19/UART3_SOUT/
LPUART2_SOUT
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
30
NXP Semiconductors
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
FTM4_CH3/UART2_RTS_B/
GPIO1_20/UART4_SOUT/
LPUART4_SOUT/
Channel 3
L1
IO
DVDD
---
LPUART1_RTS_B
FTM4_CH4/UART1_CTS_B/
GPIO1_21/UART3_SIN/
LPUART2_SIN
Channel 4
Channel 5
J1
IO
IO
DVDD
DVDD
---
---
FTM4_CH5/UART2_CTS_B/
GPIO1_22/UART4_SIN/
LPUART1_CTS_B/
M2
LPUART4_SIN
FTM4_CH6/SDHC_CMD/
GPIO2_04/LPUART3_SOUT
Channel 6
Channel 7
P2
P1
R1
IO
IO
I
EVDD
EVDD
EVDD
---
---
1
FTM4_CH7/SDHC_DAT0/
GPIO2_05/LPUART3_SIN
FTM4_EXTCLK/SDHC_DAT2/ Ext Clock
GPIO2_07/LPUART2_CTS_B/
LPUART5_SIN
FTM4_FAULT/SDHC_DAT1/
GPIO2_06/LPUART5_SOUT/
LPUART2_RTS_B
Fault
R2
T1
P3
I
I
I
EVDD
EVDD
EVDD
1
1
1
FTM4_QD_PHA/SDHC_DAT3/ Phase A
GPIO2_08/LPUART6_SOUT/
LPUART3_RTS_B
FTM4_QD_PHB/SDHC_CLK/ Phase B
GPIO2_09/LPUART3_CTS_B/
LPUART6_SIN
Frequency Timer Module 5
FTM5_CH0/IFC_A25/
GPIO2_25/QSPI_A_DATA3/
IFC_CS4_B/IFC_RB2_B
Channel 0
Channel 1
Ext Clock
C13
IO
IO
I
OVDD
OVDD
OVDD
---
---
1
FTM5_CH1/IFC_A26/
GPIO2_26/IFC_CS5_B/
IFC_RB3_B
D14
C14
FTM5_EXTCLK/IFC_A27/
GPIO2_27/IFC_CS6_B
Frequency Timer Module 6
FTM6_CH0/IFC_PAR0/
GPIO2_13/QSPI_B_DATA0
Channel 0
Channel 1
B18
IO
IO
I
OVDD
OVDD
OVDD
---
---
1
FTM6_CH1/IFC_PAR1/
GPIO2_14/QSPI_B_DATA1
D17
E17
FTM6_EXTCLK/IFC_PERR_B/ Ext Clock
GPIO2_15/QSPI_B_DATA2
Frequency Timer Module 7
FTM7_CH0/IFC_CS1_B/
Channel 0
A19
IO
OVDD
---
GPIO2_10
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
31
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
FTM7_CH1/IFC_CS2_B/
GPIO2_11
Channel 1
D20
IO
I
OVDD
---
FTM7_EXTCLK/IFC_CS3_B/ Ext Clock
GPIO2_12/QSPI_B_DATA3
C20
OVDD
DVDD
1
Frequency Timer Module 8
FTM8_CH0/IIC3_SCL/
GPIO4_10/EVT5_B/
USB2_DRVVBUS/BRGO4/
CLK11
Channel 0
Channel 1
L4
IO
IO
---
FTM8_CH1/IIC3_SDA/
GPIO4_11/EVT6_B/
USB2_PWRFAULT/BRGO1/
CLK12_CLK8
M4
DVDD
---
LPUART
LPUART1_CTS_B/
Clear to send
M2
I
DVDD
1
1
UART2_CTS_B/GPIO1_22/
UART4_SIN/FTM4_CH5/
LPUART4_SIN
LPUART1_RTS_B/
Request to send
L1
O
DVDD
UART2_RTS_B/GPIO1_20/
UART4_SOUT/
LPUART4_SOUT/FTM4_CH3
LPUART1_SIN/UART2_SIN/
GPIO1_18/FTM4_CH1
Receive data
Transmit data
K1
L2
I
DVDD
DVDD
1
LPUART1_SOUT/
UART2_SOUT/GPIO1_16/
FTM4_CH0
IO
---
LPUART2_CTS_B/
SDHC_DAT2/GPIO2_07/
LPUART5_SIN/
Clear to send
R1
R2
I
EVDD
1
1
FTM4_EXTCLK
LPUART2_RTS_B/
SDHC_DAT1/GPIO2_06/
LPUART5_SOUT/
FTM4_FAULT
Request to send
O
EVDD
LPUART2_SIN/
UART1_CTS_B/GPIO1_21/
UART3_SIN/FTM4_CH4
Receive data
Transmit data
Clear to send
J1
J2
P3
I
IO
I
DVDD
DVDD
EVDD
1
LPUART2_SOUT/
UART1_RTS_B/GPIO1_19/
UART3_SOUT/FTM4_CH2
---
1
LPUART3_CTS_B/
SDHC_CLK/GPIO2_09/
LPUART6_SIN/
FTM4_QD_PHB
LPUART3_RTS_B/
Request to send
T1
O
EVDD
1
SDHC_DAT3/GPIO2_08/
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
32
NXP Semiconductors
Pin assignments
Notes
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
LPUART6_SOUT/
FTM4_QD_PHA
LPUART3_SIN/SDHC_DAT0/ Receive data
GPIO2_05/FTM4_CH7
P1
P2
I
EVDD
1
LPUART3_SOUT/
SDHC_CMD/GPIO2_04/
FTM4_CH6
Transmit data
Receive data
IO
EVDD
DVDD
---
LPUART4_SIN/
M2
L1
I
1
UART2_CTS_B/GPIO1_22/
UART4_SIN/FTM4_CH5/
LPUART1_CTS_B
LPUART4_SOUT/
Transmit data
IO
DVDD
---
UART2_RTS_B/GPIO1_20/
UART4_SOUT/FTM4_CH3/
LPUART1_RTS_B
LPUART5_SIN/SDHC_DAT2/ Receive data
GPIO2_07/LPUART2_CTS_B/
FTM4_EXTCLK
R1
R2
I
EVDD
EVDD
1
LPUART5_SOUT/
SDHC_DAT1/GPIO2_06/
FTM4_FAULT/
Transmit data
IO
---
LPUART2_RTS_B
LPUART6_SIN/SDHC_CLK/
GPIO2_09/LPUART3_CTS_B/
FTM4_QD_PHB
Receive data
Transmit data
P3
T1
I
EVDD
EVDD
1
LPUART6_SOUT/
SDHC_DAT3/GPIO2_08/
FTM4_QD_PHA/
IO
---
LPUART3_RTS_B
QUICC Engine
CLK10/IIC2_SDA/GPIO4_03/ QE clock
SDHC_WP/FTM3_QD_PHB/
QE_SI1_STROBE1/BRGO3
L3
L4
I
I
I
DVDD
DVDD
DVDD
1
1
1
CLK11/IIC3_SCL/GPIO4_10/ QE clock
EVT5_B/USB2_DRVVBUS/
BRGO4/FTM8_CH0
CLK12_CLK8/IIC3_SDA/
GPIO4_11/EVT6_B/
USB2_PWRFAULT/BRGO1/
FTM8_CH1
QE clock
M4
CLK9/IIC2_SCL/GPIO4_02/
SDHC_CD_B/FTM3_QD_PHA/
QE_SI1_STROBE0/BRGO2
QE clock
K3
K3
I
DVDD
DVDD
1
1
QE_SI1_STROBE0/IIC2_SCL/ SI strobe
GPIO4_02/SDHC_CD_B/
O
FTM3_QD_PHA/CLK9/BRGO2
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
33
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
QE_SI1_STROBE1/IIC2_SDA/ SI strobe
GPIO4_03/SDHC_WP/
FTM3_QD_PHB/CLK10/
BRGO3
L3
O
I
DVDD
1
1
UC1_CDB_RXER/IIC4_SCL/ Receive error
GPIO4_12/EVT7_B/
M3
DVDD
USB3_DRVVBUS/TDMA_RQ/
FTM3_FAULT
UC1_CTSB_RXDV/IRQ05/
GPIO1_25/FTM3_CH1/
TDMA_RSYNC
Receive data
J5
L5
J4
I
O
I
DVDD
DVDD
DVDD
DVDD
DVDD
1
1
1
1
1
UC1_RTSB_TXEN/IRQ07/
GPIO1_27/FTM3_CH3/
TDMA_TSYNC
Transmit enable
UC1_RXD7/IRQ04/GPIO1_24/ Receive data
FTM3_CH0/TDMA_RXD/
TDMA_TXD
UC1_TXD7/IRQ06/GPIO1_26/ Transmit data
FTM3_CH2/TDMA_RXD_EXC/
TDMA_TXD
K5
N3
O
I
UC3_CDB_RXER/IIC4_SDA/ Receive error
GPIO4_13/EVT8_B/
USB3_PWRFAULT/
TDMB_RQ/FTM3_EXTCLK
UC3_CTSB_RXDV/IRQ09/
GPIO1_29/FTM3_CH5/
TDMB_RSYNC
Receive data
N5
J3
I
DVDD
DVDD
DVDD
DVDD
1
1
1
1
UC3_RTSB_TXEN/IRQ03/
GPIO1_23/FTM3_CH7/
TDMB_TSYNC
Transmit enable
O
I
UC3_RXD7/IRQ08/GPIO1_28/ Receive data
FTM3_CH4/TDMB_RXD/
TDMB_TXD
M5
P4
UC3_TXD7/IRQ10/GPIO1_30/ Transmit data
FTM3_CH6/TDMB_RXD_EXC/
TDMB_TXD
O
Baud rate generator
BRGO1/IIC3_SDA/GPIO4_11/ Baud Rate Generator 1
EVT6_B/USB2_PWRFAULT/
FTM8_CH1/CLK12_CLK8
M4
K3
L3
O
O
O
DVDD
DVDD
DVDD
1
1
1
BRGO2/IIC2_SCL/GPIO4_02/ Baud Rate Generator 2
SDHC_CD_B/FTM3_QD_PHA/
CLK9/QE_SI1_STROBE0
BRGO3/IIC2_SDA/GPIO4_03/ Baud Rate Generator 3
SDHC_WP/FTM3_QD_PHB/
CLK10/QE_SI1_STROBE1
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
34
NXP Semiconductors
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
BRGO4/IIC3_SCL/GPIO4_10/ Baud Rate Generator 4
EVT5_B/USB2_DRVVBUS/
FTM8_CH0/CLK11
L4
O
O
DVDD
1
Time Division Multiplexing
TDMA_RQ/IIC4_SCL/
GPIO4_12/EVT7_B/
USB3_DRVVBUS/
FTM3_FAULT/
RQ
M3
DVDD
1
UC1_CDB_RXER
TDMA_RSYNC/IRQ05/
GPIO1_25/FTM3_CH1/
UC1_CTSB_RXDV
RSYNC
RXD
J5
J4
K5
L5
J4
K5
N3
I
I
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
1
1
1
1
1
1
1
TDMA_RXD/IRQ04/
GPIO1_24/FTM3_CH0/
UC1_RXD7/TDMA_TXD
TDMA_RXD_EXC/IRQ06/
GPIO1_26/FTM3_CH2/
TDMA_TXD/UC1_TXD7
Recieve Data
TSYNC
I
TDMA_TSYNC/IRQ07/
GPIO1_27/FTM3_CH3/
UC1_RTSB_TXEN
I
TDMA_TXD/IRQ04/GPIO1_24/ Transmit Data
FTM3_CH0/TDMA_RXD/
UC1_RXD7
O
O
O
TDMA_TXD/IRQ06/GPIO1_26/ Transmit Data
FTM3_CH2/TDMA_RXD_EXC/
UC1_TXD7
TDMB_RQ/IIC4_SDA/
GPIO4_13/EVT8_B/
USB3_PWRFAULT/
FTM3_EXTCLK/
RQ
UC3_CDB_RXER
TDMB_RSYNC/IRQ09/
GPIO1_29/FTM3_CH5/
UC3_CTSB_RXDV
RSYNC
RXD
N5
M5
P4
J3
I
I
DVDD
DVDD
DVDD
DVDD
DVDD
1
1
1
1
1
TDMB_RXD/IRQ08/
GPIO1_28/FTM3_CH4/
UC3_RXD7/TDMB_TXD
TDMB_RXD_EXC/IRQ10/
GPIO1_30/FTM3_CH6/
TDMB_TXD/UC3_TXD7
Recieve Data
TSYNC
I
TDMB_TSYNC/IRQ03/
GPIO1_23/FTM3_CH7/
UC3_RTSB_TXEN
I
TDMB_TXD/IRQ08/GPIO1_28/ Transmit Data
FTM3_CH4/TDMB_RXD/
M5
O
UC3_RXD7
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
35
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
TDMB_TXD/IRQ10/GPIO1_30/ Transmit Data
FTM3_CH6/TDMB_RXD_EXC/
UC3_TXD7
P4
O
DVDD
1
TSEC_1588
TSEC_1588_ALARM_OUT1/ Alarm Out
EC2_TXD2/GPIO3_16/
FTM2_CH7
AC3
AB3
AA1
AC4
AC1
AD3
AD2
AC2
O
O
I
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
1
1
1
1
1
1
1
1
TSEC_1588_ALARM_OUT2/ Alarm Out
EC2_TXD3/GPIO3_15/
FTM2_CH5
TSEC_1588_CLK_IN/
EC2_RX_CLK/GPIO3_26/
FTM2_QD_PHA
Clock In
TSEC_1588_CLK_OUT/
EC2_TXD1/GPIO3_17/
FTM2_CH3
Clock Out
Pulse Out
Pulse Out
Trigger In
Trigger In
O
O
O
I
TSEC_1588_PULSE_OUT1/
EC2_RXD1/GPIO3_24/
FTM2_CH1
TSEC_1588_PULSE_OUT2/
EC2_TXD0/GPIO3_18/
FTM2_CH2
TSEC_1588_TRIG_IN1/
EC2_RX_DV/GPIO3_27/
FTM2_QD_PHB
TSEC_1588_TRIG_IN2/
EC2_RXD0/GPIO3_25/
FTM2_CH0
I
QSPI
QSPI_A_CS0/IFC_A16
QSPI_A_CS1/IFC_A17
Chip Select
Chip Select
Data
D8
C8
O
O
OVDD
OVDD
OVDD
1
1
QSPI_A_DATA0/IFC_A22/
IFC_WP1_B
D11
IO
---
---
---
---
QSPI_A_DATA1/IFC_A23/
IFC_WP2_B
Data
Data
Data
C12
D13
C13
IO
IO
IO
OVDD
OVDD
OVDD
QSPI_A_DATA2/IFC_A24/
IFC_WP3_B
QSPI_A_DATA3/IFC_A25/
GPIO2_25/FTM5_CH0/
IFC_CS4_B/IFC_RB2_B
QSPI_A_SCK/IFC_A18
QSPI_B_CS0/IFC_A19
QSPI_B_CS1/IFC_A20
QSPI_A Clock
Chip Select
Chip Select
Data
C9
O
O
OVDD
OVDD
OVDD
OVDD
1, 5
1
D10
C10
B18
O
1
QSPI_B_DATA0/IFC_PAR0/
IO
---
GPIO2_13/FTM6_CH0
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
36
NXP Semiconductors
Pin assignments
Notes
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
QSPI_B_DATA1/IFC_PAR1/
GPIO2_14/FTM6_CH1
Data
Data
D17
IO
IO
OVDD
---
---
QSPI_B_DATA2/
E17
OVDD
IFC_PERR_B/GPIO2_15/
FTM6_EXTCLK
QSPI_B_DATA3/IFC_CS3_B/ Data
GPIO2_12/FTM7_EXTCLK
C20
C20
C11
IO
IO
O
OVDD
OVDD
OVDD
---
QSPI_B_DATA3/IFC_CS3_B/ Data
GPIO2_12/FTM7_EXTCLK
---
QSPI_B_SCK/IFC_A21/
QSPI_B Clock
1, 4
cfg_dram_type
Power and Ground Signals
GND001
GND002
GND003
GND004
GND005
GND006
GND007
GND008
GND009
GND010
GND011
GND012
GND013
GND014
GND015
GND016
GND017
GND018
GND019
GND020
GND021
GND022
GND023
GND024
GND025
GND026
GND027
GND028
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A2
A5
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
A24
B3
B4
B7
B10
B13
B16
B19
B21
B25
C1
C2
C5
C23
D3
D4
D7
D9
D12
D15
D18
D21
E1
E2
E5
E22
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
37
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
GND029
GND030
GND031
GND032
GND033
GND034
GND035
GND036
GND037
GND038
GND039
GND040
GND041
GND042
GND043
GND044
GND045
GND046
GND047
GND048
GND049
GND050
GND051
GND052
GND053
GND054
GND055
GND056
GND057
GND058
GND059
GND060
GND061
GND062
GND063
GND064
GND065
GND066
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E24
F3
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
F4
F7
F8
F11
F12
F13
F17
F20
G1
G2
G22
G24
H3
H4
H5
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
J7
J19
J20
J24
K2
K4
K7
K10
K12
K14
K16
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
38
NXP Semiconductors
Pin assignments
Notes
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
GND067
GND068
GND069
GND070
GND071
GND072
GND073
GND074
GND075
GND076
GND077
GND078
GND079
GND080
GND081
GND082
GND083
GND084
GND085
GND086
GND087
GND088
GND089
GND090
GND091
GND092
GND093
GND094
GND095
GND096
GND097
GND098
GND099
GND100
GND101
GND102
GND103
GND104
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K19
K22
L7
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
L9
L11
L13
L15
L17
L19
L20
L24
M7
M10
M12
M14
M16
M19
M22
N2
N4
N6
N9
N11
N13
N15
N17
N19
N20
P7
P8
P10
P12
P14
P16
P19
P22
P24
R9
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
39
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130
GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
SD_GND01
SD_GND02
SD_GND03
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R11
R13
R15
R17
R19
R25
T2
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
34
34
34
T4
T8
T10
T12
T14
T20
U6
U9
U11
U20
V2
V8
V9
V10
V11
V12
V13
V14
V20
W4
W20
Y2
Y20
AB2
AB4
AD1
AD4
AE2
U15
U16
U17
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
40
NXP Semiconductors
Pin assignments
Notes
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
SD_GND04
SD_GND05
SD_GND06
SD_GND07
SD_GND08
SD_GND09
SD_GND10
SD_GND11
SD_GND12
SD_GND13
SD_GND14
SD_GND15
SD_GND16
SD_GND17
SD_GND18
SD_GND19
SD_GND20
SD_GND21
SD_GND22
SD_GND23
SD_GND24
SD_GND25
SD_GND26
SD_GND27
SD_GND28
SD_GND29
SD_GND30
SD_GND31
SD_GND32
SD_GND33
SD_GND34
SD_GND35
SD_GND36
SD_GND37
SD_GND38
SD_GND39
SENSEGND
OVDD1
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
GND Sense pin
U18
U19
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
W8
W11
Y8
Y9
Y10
Y11
Y12
Y14
Y15
Y16
Y17
Y18
AA13
AA16
AA19
AB13
AB16
AB19
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AD13
AD16
AD19
AD21
AE13
AE16
AE19
AE21
V7
General I/O supply
J12
OVDD
---
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
41
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
OVDD2
OVDD3
OVDD4
OVDD5
OVDD6
OVDD7
DVDD1
General I/O supply
J13
J14
J15
J16
J17
N7
---
OVDD
---
General I/O supply
General I/O supply
General I/O supply
General I/O supply
General I/O supply
---
---
---
---
---
---
OVDD
OVDD
OVDD
OVDD
OVDD
DVDD
---
---
---
---
---
---
UART/I2C/QE supply -
switchable
K8
DVDD2
UART/I2C/QE supply -
switchable
L8
---
DVDD
---
EVDD
eSDHC supply - switchable
M8
---
---
EVDD
LVDD
---
---
LVDD1
Ethernet controller 1 & 2
supply
U12
LVDD2
LVDD3
TVDD
Ethernet controller 1 & 2
supply
U13
U14
V6
---
---
---
LVDD
LVDD
TVDD
---
---
---
Ethernet controller 1 & 2
supply
1.2V/LVDD supply for MDIO
interface for 10G Fman (EC2)
G1VDD01
G1VDD02
G1VDD03
G1VDD04
G1VDD05
G1VDD06
G1VDD07
G1VDD08
G1VDD09
G1VDD10
G1VDD11
G1VDD12
G1VDD13
G1VDD14
G1VDD15
G1VDD16
G1VDD17
G1VDD18
G1VDD19
G1VDD20
G1VDD21
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
J18
K18
K20
L18
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
M18
M20
N18
P18
P20
R21
R23
T22
T24
V22
V24
Y22
Y24
AA20
AB22
AB24
AD22
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
42
NXP Semiconductors
Pin assignments
Notes
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
G1VDD22
G1VDD23
S1VDD1
S1VDD2
S1VDD3
S1VDD4
S1VDD5
X1VDD1
X1VDD2
X1VDD3
X1VDD4
X1VDD5
FA_VL
DDR supply
AD25
AE24
T15
---
G1VDD
---
---
---
---
---
---
---
---
---
---
---
---
15
15
31
DDR supply
---
---
---
---
---
---
---
---
---
---
---
---
---
---
G1VDD
SerDes1 core logic supply
SerDes1 core logic supply
SerDes1 core logic supply
SerDes1 core logic supply
SerDes1 core logic supply
SerDes1 transceiver supply
SerDes1 transceiver supply
SerDes1 transceiver supply
SerDes1 transceiver supply
SerDes1 transceiver supply
Reserved
S1VDD
T16
S1VDD
T17
S1VDD
T18
S1VDD
W14
W15
W16
W17
W18
Y19
R7
S1VDD
X1VDD
X1VDD
X1VDD
X1VDD
X1VDD
FA_VL
PROG_MTR
Reserved
G14
F14
PROG_MTR
TA_PROG_SFP
TA_PROG_SFP
SFP Fuse Programming
Override supply
TH_VDD
VDD01
VDD02
VDD03
VDD04
VDD05
VDD06
VDD07
VDD08
VDD09
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
Thermal Monitor Unit supply
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
T6
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
TH_VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
32
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
K13
K15
K17
L10
L12
L14
L16
M9
M11
M13
M15
M17
N8
N10
N12
N14
N16
P9
P11
P13
P15
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
43
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
TA_BB_VDD
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
P17
R8
---
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
R10
R12
R14
R16
R18
T9
T11
T13
U8
U10
H20
Battery Backed Security
Monitor supply
TA_BB_VDD
AVDD_CGA1
AVDD_CGA2
AVDD_CGA1
AVDD_CGA2
CPU Cluster Group A PLL1
supply.
G12
G11
---
---
30
30
CPU Cluster Group A PLL2
supply.
AVDD_PLAT
AVDD_D1
Platform PLL supply.
DDR1 PLL supply.
SerDes1 PLL 1 supply.
SerDes1 PLL 2 supply.
Vdd Sense pin
G13
T19
W12
V19
W7
J8
---
---
---
---
---
---
---
---
AVDD_PLAT
AVDD_D1
30
30
30
30
---
---
---
---
AVDD_SD1_PLL1
AVDD_SD1_PLL2
SENSEVDD
AVDD_SD1_PLL1
AVDD_SD1_PLL2
SENSEVDD
USB_HVDD
USB_HVDD1
USB_HVDD2
USB_SDVDD1
3.3V High Supply
3.3V High Supply
J9
USB_HVDD
1.0 V Analog and digital HS
supply
K9
USB_SDVDD
USB_SDVDD2
USB_SVDD1
USB_SVDD2
1.0 V Analog and digital HS
supply
K11
J10
J11
---
---
---
USB_SDVDD
USB_SVDD
USB_SVDD
---
---
---
1.0 V Analog and digital SS
supply
1.0 V Analog and digital SS
supply
No Connection Pins
NC_AA10
NC_AA11
NC_AA12
NC_AA5
NC_AA6
NC_AA7
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
AA10
AA11
AA12
AA5
---
---
---
---
---
---
---
---
---
---
---
---
12
12
12
12
12
12
AA6
AA7
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
44
NXP Semiconductors
Pin assignments
Notes
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
NC_AA8
NC_AA9
NC_AB10
NC_AB11
NC_AB12
NC_AB5
NC_AB6
NC_AB7
NC_AB8
NC_AB9
NC_AC10
NC_AC11
NC_AC12
NC_AC5
NC_AC6
NC_AC7
NC_AC8
NC_AC9
NC_AD10
NC_AD11
NC_AD12
NC_AD5
NC_AD6
NC_AD7
NC_AD8
NC_AD9
NC_AE10
NC_AE11
NC_AE12
NC_AE5
NC_AE6
NC_AE7
NC_AE8
NC_AE9
NC_K6
No Connection
AA8
AA9
AB10
AB11
AB12
AB5
AB6
AB7
AB8
AB9
AC10
AC11
AC12
AC5
AC6
AC7
AC8
AC9
AD10
AD11
AD12
AD5
AD6
AD7
AD8
AD9
AE10
AE11
AE12
AE5
AE6
AE7
AE8
AE9
K6
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
NC_L6
L6
NC_M6
M6
NC_Y13
Y13
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
45
Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
NC_Y7
No Connection
Y7
---
---
12
1. Functionally, this pin is an output or an input, but structurally it is an I/O because it
either sample configuration input during reset, is a muxed pin, or has other manufacturing
test functions. This pin will therefore be described as an I/O for boundary scan.
2. This output is actively driven during reset rather than being tri-stated during reset.
3. MDIC[0] is grounded through a 162Ω precision 1% resistor and MDIC[1] is connected
to GVDD through a 162Ω precision 1% resistor. For either full or half driver strength
calibration of DDR IOs, use the same MDIC resistor value of 162Ω. The memory
controller register setting can be used to determine automatic calibration is done to full or
half drive strength. These pins are used for automatic calibration of the DDR3L/DDR4
IOs. The MDIC[0:1] pins must be connected to 162Ω precision 1% resistors.
4. This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that
is enabled only when the processor is in its reset state. This pull-up is designed such that
it can be overpowered by an external 4.7 kΩ resistor. However, if the signal is intended to
be high after reset, and if there is any device on the net that might pull down the value of
the net at reset, a pull-up or active driver is needed.
5. Pin must NOT be pulled down during power-on reset. This pin may be pulled up,
driven high, or if there are any externally connected devices, left in tristate. If this pin is
connected to a device that pulls down during reset, an external pull-up is required to drive
this pin to a safe state during reset.
6. Recommend that a weak pull-up resistor (2-10 kΩ) be placed on this pin to the
respective power supply.
7. This pin is an open-drain signal.
8. Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective
power supply.
9. This pin has a weak (~20 kΩ) internal pull-up P-FET that is always enabled.
10. These are test signals for factory use only and must be pulled up (100Ω to 1-kΩ) to
the respective power supply for normal operation.
11. This pin requires a 200Ω pull-up to respective power-supply.
12. Do not connect. These pins should be left floating.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
46
NXP Semiconductors
Pin assignments
14. This pin requires an external 1-kΩ pull-down resistor to prevent PHY from seeing a
valid Transmit Enable before it is actively driven.
15. These pins must be pulled to ground (GND).
16. This pin requires a 698Ω pull-up to respective power-supply.
17. These pins should be tied to ground if the diode is not utilized for temperature
monitoring.
18. This pin should be connected to ground through 2-10kΩ resistor when not used.
19. This pin should be connected to ground through 2-10kΩ resistor when SYSCLK input
is used as system clock.
21. This pin has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the
processor is in its reset state. This pin should have an optional pull down resistor on
board. This is required to support DIFF_SYSCLK/DIFF_SYSCLK_B.
23. This pin must be pulled to OVDD through a 100-ohm to 1k-ohm resistor for a four
core LS1043A device and tied to ground for a two core LS1023A device.
25. The alternate signal in DDR4 configuration is mentioned in corresponding Reference
Manual.
27. Attach 200 Ohm +/-1% 100-ppm/C precision resistor-to-ground. Voltage range
0-250mV
28. The permissible voltage range is 0 V - 5.25 V.
29. The permissible voltage range for input signal is 0 - 1.8V
30. It is measured at the input of the supply filter and not at the SoC pin.
31. Connect to ground when fuses are read-only.
32. TH_VDD must be tied to OVDD.
33. Recommend that a weak pull-down resistor (2-10 k-ohm) be placed on this pin to
GND.
34. SD_GND must be directly connected to GND.
35. This pin is used for debug purposes. It is advised that boards are built with the ability
to pull up and pull down this pin.
36. This pin must be pulled down to ground with a resistor of value 4.7k ohm.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
47
Pin assignments
Warning
See "Connection Recommendations" for additional details on
properly connecting these pins for specific applications.
2.3 780 ball layout diagrams
This figure shows the complete view of the LS1043A_23x23 ball map diagram. Figure 9,
Figure 10, Figure 11, and Figure 12 show quadrant views.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
48
NXP Semiconductors
Pin assignments
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A
A
B
B
C
C
D
D
E
E
F
F
SEE DETAIL A
SEE DETAIL B
G
G
H
H
J
J
K
K
L
L
M
N
M
N
P
P
R
R
T
T
U
U
V
V
W
Y
W
Y
SEE DETAIL C
SEE DETAIL D
AA
AB
AC
AD
AE
AF
AG
AH
AA
AB
AC
AD
AE
AF
AG
AH
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
DDR Interface 1
Interrupts
SYSCLK
IFC
DUART
SPI
eSDHC
ASLEEP
DFT
Battery Backed Trust
DDR Clocking
Analog Signals
Ethernet MI 1
USB
Trust
System Control
Debug
RTC
JTAG
Serdes 1
Ethernet MI 2
TA_BB_RTC
USB3 PHY
1
USB3 PHY 2
USB PHY
I2C
3
Ethernet Cont. 1
DIFF_SYSCLK
Ethernet Cont. 2
Power
Ground
No Connects
Figure 8. Complete BGA Map for the LS1043A_23x23
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
49
Pin assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
USB3_
RX_
P
USB3_
RX_
M
USB3_
D_
USB3_
VBUS
IFC_
IFC_
IFC_
IFC_
IFC_
IFC_
IFC_
GND001
GND002
A
A
B
C
D
E
F
AD01
AD03
AD04
AD06
AD08
AD09
AD11
M
USB3_
USB3_
TX_
M
USB3_
D_
P
USB3_
ID
IFC_
AD00
IFC_
AD02
IFC_
AD05
IFC_
AD07
IFC_
AD10
TX_
GND004
GND005
GND006
GND007
GND008
B
P
USB2_
RX_
P
USB2_
RX_
M
USB2_
D_
M
USB2_
VBUS
IFC_
A17
IFC_
A18
IFC_
A20
IFC_
A21
IFC_
A23
IFC_
A25
IFC_
A27
GND014
GND015
GND016
C
USB2_
USB2_
TX_
M
USB2_
D_
P
USB2_
ID
IFC_
A16
IFC_
A19
IFC_
A22
IFC_
A24
IFC_
A26
TX_
GND019
GND020
GND021
GND022
ASLEEP
GND023
EVT3_B
D
P
USB1_
RX_
P
USB1_
RX_
M
USB1_
D_
M
USB1_
VBUS
IFC_
TE
GND028
GND029
GND030
EVT2_B
EVT0_B
EVT4_B
IRQ00
EVT1_B
E
USB1_
USB1_
TX_
M
USB1_
D_
P
USB1_
ID
HRESET_ PORESET_ RESET_
B
PROG_
MTR
TX_
GND033
GND034
GND035
EVT9_B
IRQ02
TA_BB_RTC
GND036
SYSCLK
GND050
OVDD1
F
B
REQ_B
P
TA_
PROG_
SFP
USB1_
RESREF
USB2_
RESREF
USB3_
USB_
TH_
VDD
TA_BB_
VDD
GND040
GND041
GND042
GND043
GND044
G
G
H
J
RESREF PWRFAULT
TA_BB_
TMP_
DETECT_B
UART1_
SOUT
UART1_
SIN
USB_
GND049
TH_
TPA
AVDD_
CGA1
AVDD_
CGA2
AVDD_
PLAT
TD1_
CATHODE
GND047
IRQ03
GND048
IRQ04
H
DRVVBUS
UART1_
CTS_B
UART1_
RTS_B
TD1_
ANODE
IRQ05
IRQ06
IRQ07
IRQ08
IRQ09
GND057
GND069
GND075
GND084
GND095
GND058
GND059
GND060
GND061
GND062
GND063
J
UART2_
SIN
IIC2_
SCL
USB_
SVDD1
USB_
HVDD1
NC_
K9
NC_
K10
NC_
K11
NC_
K12
NC_
K14
GND067
GND068
GND070
K
K
L
UART2_
RTS_B
UART2_
SOUT
IIC2_
SDA
IIC3_
SCL
USB_
SVDD2
USB_
HVDD2
NC_
L9
NC_
L11
NC_
L13
GND076
VDD06
GND077
VDD07
GND078
VDD08
L
IIC1_
SDA
UART2_
CTS_B
IIC4_
SCL
IIC3_
SDA
USB_
SDVDD1
USB_
SDVDD2
GND085
VDD11
GND086
VDD12
GND087
VDD13
M
M
N
P
IIC1_
SCL
IIC4_
SDA
GND093
GND094
DVDD1
GND096
GND097
GND098
GND099
N
SDHC_
DAT0
SDHC_
CMD
SDHC_
CLK
NC_
P5
NC_
P8
IRQ10
GND105
DVDD2
GND106
VDD17
GND107
VDD18
GND108
VDD19
P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DDR Interface 1
Interrupts
SYSCLK
JTAG
IFC
DUART
SPI
eSDHC
Battery Backed Tru
DDR Clocking
Analog Signals
Ethernet MI 1
USB
Trust
System Control
Debug
ASLEEP
RTC
DFT
Serdes 1
Ethernet MI 2
TA_BB_RTC
USB3 PHY 1
Ethernet Cont. 1
DIFF_SYSCLK
USB3 PHY 2
Ethernet Cont. 2
Power
USB PHY 3
I2C
Ground
No Connects
Figure 9. Detail A
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
50
NXP Semiconductors
Pin assignments
15
16
17
18
19
20
21
22
23
24
25
26
27
28
IFC_
IFC_
IFC_
IFC_
IFC_
IFC_
NC_
D1_
D1_
D1_
NC_
D1_
GND003
A
B
C
D
E
F
A
AD13
AD14
AD15
AVD
CS1_B
CLK0
A22
MECC1
MDQS8_B
MDQS8
A26
MECC3
IFC_
AD12
IFC_
NDDQS
IFC_
PAR0
IFC_
CLK1
D1_
MDM8
D1_
B
GND009
GND010
GND011
GND017
GND026
GND031
NC_B22
GND012
NC_B25
GND013
G1VDD01
MCKE1
IFC_
WE0_B
IFC_
RB0_B
IFC_
CS0_B
IFC_
OE_B
IFC_
CLE
IFC_
CS3_B
D1_
MECC0
D1_
MDQS3_B
D1_
MDQ30
D1_
MDQ20
D1_
MECC2
D1_
C
GND018
MCKE0
IFC_
RB1_B
IFC_
PAR1
IFC_
WP0_B
IFC_
CS2_B
D1_
MDQ25
D1_
MDQS3
D1_
MDQ21
D1_
MDQ16
D1_
D
GND024
IFC_BCTL
IRQ01
GND025
TCK
GND027
G1VDD02
MACT_B
IFC_
NDDDR_
CLK
IFC_
PERR_B
D1_
MDQ24
D1_
MDQ31
D1_
MDQ17
D1_
MDM2
D1_
MBG0
D1_
E
TRST_B
TDO
GND032
MBG1
TBSCAN_
EN_B
TEST_
SEL_B
D1_
TPA
D1_
MDQ29
D1_
MDQ26
D1_
MDQS2
D1_
MDQS2_B
D1_
F
GND037
RTC
GND038
TMS
GND039
G1VDD03
MALERT_B
CKSTP_
OUT_B
CLK_
OUT
NC_
G19
NC_
G20
D1_
MDQ28
D1_
MDQ27
D1_
MDQ18
D1_
MDQ22
D1_
MA12
D1_
G
TDI
GND045
GND055
GND064
GND074
GND046
G
H
J
MA09
TA_
TMP_
DETECT_B
SCAN_
MODE_B
D1_
MDM3
D1_
MDQ13
D1_
MDQ19
D1_
MDQ23
D1_
H
GND051
OVDD2
GND071
VDD03
GND052
OVDD3
GND053
OVDD4
GND072
VDD04
GND089
VDD15
GND054
GND056
G1VDD04
MA11
D1_
MDQ12
D1_
MDQ09
D1_
MDM1
D1_
MA07
D1_
J
OVDD5 AG_BSR_VSELDDRCLK
GND065
GND066
MA08
NC_
K16
NC_
K22
D1_
MDQ08
D1_
MDQ14
D1_
MDQS1_B
D1_
MDQS1
D1_
K
VDD01
GND080
VDD10
GND073
VDD05
VDD02
G1VDD05
K
L
MA06
NC_
L21
D1_
MDQ10
D1_
MDQ15
D1_
MA05
D1_
L
GND079
VDD09
GND081
G1VDD06
G1VDD07
G1VDD09
GND082
GND092
GND103
GND083
MA04
NC_
M20
D1_
MDQ11
D1_
MDQ04
D1_
MDQ00
D1_
M
GND088
VDD14
GND090
VDD16
GND091
G1VDD08
M
N
P
MA03
NC_
N21
D1_
MDQ05
D1_
MDQ01
D1_
MA01
D1_
N
GND100
GND101
GND102
GND104
MA02
NC_
P20
D1_
MVREF
D1_
MDM0
D1_
MDQS0
D1_
MDQS0_B
D1_
P
GND109
VDD20
GND110
VDD21
GND111
G1VDD10
GND112
G1VDD11
MDIC0
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DDR Interface 1
Interrupts
SYSCLK
JTAG
IFC
DUART
SPI
eSDHC
Battery Backed Tru
DDR Clocking
Analog Signals
Ethernet MI 1
USB
Trust
System Control
Debug
ASLEEP
DFT
RTC
Serdes 1
Ethernet MI 2
TA_BB_RTC
USB3 PHY 1
Ethernet Cont. 1
DIFF_SYSCLK
USB3 PHY 2
USB PHY 3
I2C
Ethernet Cont. 2
Power
Ground
No Connects
Figure 10. Detail B
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
51
Pin assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SDHC_
DAT2
SDHC_
DAT1
SPI_
PCS1
GND113
GND114
EVDD
OVDD6
GND115
VDD22
GND116
VDD23
GND117
VDD24
GND118
R
R
FA_
ANALOG_
G_V
SDHC_
DAT3
SPI_
NC_
T8
GND124
GND125
GND126
GND136
GND147
TVDD
LVDD1
LVDD2
LVDD3
GND127
VDD33
VDD28
GND138
VDD39
GND128
VDD34
VDD29
GND139
VDD40
GND129
VDD35
VDD30
GND140
VDD41
PCS2
T
T
FA_
ANALOG_
PIN
SPI_
PCS0
SPI_
SCK
SPI_
SIN
FA_
VL
GND137
U
U
SPI_
PCS3
SPI_
SOUT
SENSE
VDD
NC_
V8
GND145
GND146
GND148
GND149
GND150
V
V
EC1_
RX_
CLK
EC1_
GTX_
CLK
EC1_
RXD3
SENSE
GND
NC_
W7
NC_
W8
NC_
W9
NC_
W10
NC_
W11
NC_
W13
NC_
W14
IRQ11
GND155
W
W
SD1_
IMP_
EC1_
RXD2
EC1_
TXD3
EC1_
TXD2
NC_
Y5
SD_
SD_
SD_
SD_
SD_
NC_
Y12
GND157
GND158
GND159
GND164
GND05
GND06
GND07
GND08
GND09
CAL_RX
Y
Y
SD1_
REF_
CLK1_P
AVDD_
SD1_
PLL1
EC1_
RXD1
EC1_
RXD0
EC1_
TXD1
SD_
GND12
NC_
AA6
SD_
GND13
SD_
GND14
NC_
AA10
SD_
GND15
DIFF_
SYSCLK
GND163
AA
AA
AB
AC
AD
AE
AF
AG
AH
EC1_
RX_
DV
EC1_
TX_
EN
SD1_
REF_
EC1_
TXD0
NC_
AB5
NC_
AB6
SD_
SD_
NC_
NC_
DIFF_
SD_
GND167
GND168
GND19
GND20
AB10
AB11
SYSCLK_B
GND21
CLK1_N
AB
EC2_
RX_
CLK
EC1_
GTX_
CLK125
EC2_
GTX_
CLK
EC2_
RXD3
SD_
GND24
SD_
GND25
NC_
AC7
SD_
GND26
NC_
AC9
SD_
GND27
SD_
GND28
NC_
AC12
NC_
AC13
X1VDD1
AC
SD1_
TX0_
P
SD1_
TX1_
P
EC2_
RXD2
EC2_
TXD3
SD_
GND33
SD_
GND34
NC_
AD8
SD_
GND35
NC_
AD11
SD_
GND36
NC_
AD13
SD_
GND37
GND172
GND173
AD
SD1_
TX0_
N
SD1_
TX1_
N
EC2_
RXD1
EC2_
RXD0
EC2_
TXD2
EC2_
TXD1
SD_
GND40
SD_
GND41
NC_
AE8
SD_
GND42
NC_
AE11
SD_
GND43
NC_
AE13
SD_
GND44
AE
EC2_
RX_
DV
SD1_
PLL1_
TPA
SD1_
PLL1_
TPD
EMI1_
MDIO
EC2_
TXD0
NC_
AF5
SD_
GND47
SD_
GND48
SD_
GND49
SD_
GND50
SD_
GND51
SD_
GND52
NC_
AF14
GND177
AF
EC2_
TX_
EN
EC2_
GTX_
CLK125
SD1_
RX0_
P
SD1_
RX1_
P
EMI1_
MDC
SD_
GND58
SD_
GND59
NC_
AG8
SD_
GND60
NC_
AG11
SD_
GND61
NC_
AG13
SD_
GND62
GND180
AG
SD1_
RX0_
N
SD1_
RX1_
N
EMI2_
MDIO
EMI2_
MDC
SD_
GND65
SD_
GND66
NC_
AH8
SD_
GND67
NC_
AH11
SD_
GND68
NC_
AH13
SD_
GND69
GND183
AH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DDR Interface 1
Interrupts
SYSCLK
JTAG
IFC
DUART
SPI
eSDHC
Battery Backed Tru
DDR Clocking
Analog Signals
Ethernet MI 1
USB
Trust
System Control
Debug
ASLEEP
DFT
RTC
Serdes 1
Ethernet MI 2
TA_BB_RTC
USB3 PHY 1
Ethernet Cont. 1
DIFF_SYSCLK
USB3 PHY 2
USB PHY 3
I2C
Ethernet Cont. 2
Power
Ground
No Connects
Figure 11. Detail C
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
52
NXP Semiconductors
Pin assignments
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AVDD_
D1
D1_
MDQ07
D1_
MDQ06
D1_
MCK0_B
D1_
MCK0
VDD25
GND119
VDD26
GND120
VDD27
GND121
G1VDD12
GND122
GND123
R
R
NC_
T20
D1_
D1_
D1_
D1_
GND130
VDD36
VDD31
GND141
VDD42
GND131
VDD37
VDD32
GND132
VDD38
GND133
G1VDD13
G1VDD14
G1VDD16
GND156
GND134
GND144
GND153
GND135
MDQ03
MDQ02
MCK1_B
MCK1
T
T
NC_
U21
NC_
U24
NC_
U25
NC_
U26
D1_
MDIC1
GND142
GND143
G1VDD15
U
U
SD_
GND01
NC_
V18
SD_
GND02
NC_
V20
NC_
V24
NC_
V25
D1_
MA00
D1_
MPAR
GND151
GND152
GND154
V
V
NC_
W15
NC_
W16
NC_
W17
SD_
GND03
NC_
W19
SD_
GND04
NC_
W21
NC_
W23
NC_
W24
NC_
W25
NC_
W26
D1_
MBA1
G1VDD17
W
W
SD1_
IMP_
SD_
SD_
NC_
Y22
NC_
Y24
NC_
Y25
D1_
D1_
S1VDD1
S1VDD2
S1VDD3
GND160
GND165
GND161
GND162
GND10
GND11
MBA0
MA10
CAL_TX
Y
Y
AVDD_
SD1_
PLL2
SD1_
PLL2_
TPD
NC_
AA15
SD_
GND16
SD_
GND17
SD_
GND18
NC_
AA22
NC_
AA23
NC_
AA25
NC_
AA26
D1_
MRAS_B
GND166
G1VDD18
AA
AB
AC
AD
AE
AF
AG
AH
AA
SD1_
REF_
SD1_
REF_
NC_
NC_
SD_
SD_
NC_
NC_
NC_
NC_
NC_
D1_
D1_
GND169
AB15
AB16
GND22
GND23
AB21
AB22
AB23
AB24
AB25
MCS0_B
MWE_B
CLK2_P
CLK2_N
AB
SD_
GND29
SD_
GND30
SD_
GND31
SD_
GND32
NC_
AC22
NC_
AC23
NC_
AC25
NC_
AC26
D1_
MCAS_B
X1VDD2
X1VDD3
GND170
GND171
G1VDD19
AC
SD1_
TX2_
P
SD1_
TX3_
P
NC_
AD15
SD_
GND38
NC_
AD18
SD_
GND39
NC_
AD21
NC_
AD22
NC_
AD23
NC_
AD24
NC_
AD25
D1_
MA13
D1_
MODT0
GND174
AD
SD1_
TX2_
N
SD1_
TX3_
N
NC_
AE15
SD_
GND45
NC_
AE18
SD_
GND46
NC_
AE22
NC_
AE23
NC_
AE25
NC_
AE26
D1_
MCS1_B
GND175
GND178
GND176
G1VDD20
AE
SD1_
PLL2_
TPA
SD_
GND53
SD_
GND54
SD_
GND55
SD_
GND56
SD_
GND57
NC_
AF22
NC_
AF23
NC_
AF24
NC_
AF25
D1_
MODT1
D1_
MCS3_B
GND179
GND182
AF
SD1_
RX2_
P
SD1_
RX3_
P
NC_
AG15
SD_
GND63
NC_
AG18
SD_
GND64
NC_
AG21
NC_
AG22
NC_
AG23
NC_
AG25
D1_
MCS2_B
GND181
G1VDD21
G1VDD22
AG
SD1_
RX2_
N
SD1_
RX3_
N
NC_
AH15
SD_
GND70
NC_
AH18
SD_
GND71
NC_
AH22
NC_
AH23
NC_
AH24
NC_
AH25
NC_
AH26
GND184
AH
28
15
16
17
18
19
20
21
22
23
24
25
26
27
DDR Interface 1
Interrupts
SYSCLK
JTAG
IFC
DUART
SPI
eSDHC
Battery Backed Tru
DDR Clocking
Analog Signals
Ethernet MI 1
USB
Trust
System Control
Debug
ASLEEP
DFT
RTC
Serdes 1
Ethernet MI 2
TA_BB_RTC
USB3 PHY 1
Ethernet Cont. 1
DIFF_SYSCLK
USB3 PHY 2
USB PHY 3
I2C
Ethernet Cont. 2
Power
Ground
No Connects
Figure 12. Detail D
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
53
Pin assignments
2.4 Pinout list
This table provides the pinout listing for the LS1043A_23X23 by bus. Primary functions
are bolded in the table.
Table 2. Pinout list by bus
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
DDR SDRAM Memory Interface 1
D1_MA00
D1_MA01
D1_MA02
D1_MA03
D1_MA04
D1_MA05
D1_MA06
D1_MA07
D1_MA08
D1_MA09
D1_MA10
D1_MA11
D1_MA12
D1_MA13
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
Address
V27
N27
N28
M28
L28
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
G1VDD
---
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
---
---
---
---
---
---
---
---
---
---
---
---
---
25
1, 6, 25
---
---
25
25
25
---
---
---
---
2
L27
K28
J27
J28
G28
Y28
H28
G27
AD27
D28
D1_MACT_B
D1_MALERT_B
D1_MBA0
Address Parity Error
Bank Select
Bank Select
Bank Select
Address
F28
Y27
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
D1_MBA1
W28
E27
D1_MBG0
D1_MBG1
E28
D1_MCAS_B
D1_MCK0
Column Address Strobe
Clock
AC28
R28
D1_MCK0_B
D1_MCK1
Clock Complement
Clock
R27
T28
D1_MCK1_B
D1_MCKE0
D1_MCKE1
D1_MCS0_B
D1_MCS1_B
D1_MCS2_B
D1_MCS3_B
Clock Complement
Clock Enable
Clock Enable
Chip Select
T27
C28
B28
2
AB27
AE28
AG28
AF28
---
---
---
---
Chip Select
Chip Select
Chip Select
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
54
NXP Semiconductors
Pin assignments
Notes
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
D1_MDIC0
D1_MDIC1
D1_MDM0
D1_MDM1
D1_MDM2
D1_MDM3
D1_MDM8
D1_MDQ00
D1_MDQ01
D1_MDQ02
D1_MDQ03
D1_MDQ04
D1_MDQ05
D1_MDQ06
D1_MDQ07
D1_MDQ08
D1_MDQ09
D1_MDQ10
D1_MDQ11
D1_MDQ12
D1_MDQ13
D1_MDQ14
D1_MDQ15
D1_MDQ16
D1_MDQ17
D1_MDQ18
D1_MDQ19
D1_MDQ20
D1_MDQ21
D1_MDQ22
D1_MDQ23
D1_MDQ24
D1_MDQ25
D1_MDQ26
D1_MDQ27
D1_MDQ28
D1_MDQ29
D1_MDQ30
Driver Impedence Calibration
P28
U28
P24
J25
IO
IO
O
G1VDD
3
Driver Impedence Calibration
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
3
Data Mask
Data Mask
Data Mask
Data Mask
Data Mask
Data
1, 25
1, 25
1, 25
1, 25
1, 25
---
O
E25
H22
B23
M26
N25
T25
T24
M25
N24
R25
R24
K23
J24
O
O
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
L24
M24
J22
---
Data
---
Data
---
Data
H23
K24
L25
D26
E24
G24
H25
C25
D25
G25
H26
E22
D22
F23
G23
G22
F22
C24
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Data
---
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
55
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
D1_MDQ31
D1_MDQS0
D1_MDQS0_B
D1_MDQS1
D1_MDQS1_B
D1_MDQS2
D1_MDQS2_B
D1_MDQS3
D1_MDQS3_B
D1_MDQS8
D1_MDQS8_B
D1_MECC0
D1_MECC1
D1_MECC2
D1_MECC3
D1_MODT0
D1_MODT1
D1_MPAR
Data
E23
P25
P26
K26
K25
F25
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
G1VDD
---
Data Strobe
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
---
---
---
---
---
---
---
---
---
---
---
---
---
---
2
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
F26
Data Strobe
D23
C23
A25
A24
C22
A23
C26
A27
AD28
AF27
V28
AA28
AB28
Data Strobe
Data Strobe
Data Strobe
Error Correcting Code
Error Correcting Code
Error Correcting Code
Error Correcting Code
On Die Termination
On Die Termination
Address Parity Out
Row Address Strobe
Write Enable
O
2
O
25
25
25
D1_MRAS_B
D1_MWE_B
O
O
Integrated Flash Controller
IFC_A16/QSPI_A_CS0
IFC_A17/QSPI_A_CS1
IFC_A18/QSPI_A_SCK
IFC_A19/QSPI_B_CS0
IFC_A20/QSPI_B_CS1
IFC Address
IFC Address
IFC Address
IFC Address
IFC Address
IFC Address
D8
C8
O
O
O
O
O
O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
1, 5
1, 5
1, 5
1, 5
1, 5
1, 4
C9
D10
C10
C11
IFC_A21/QSPI_B_SCK/
cfg_dram_type
IFC_A22/QSPI_A_DATA0/
IFC_WP1_B
IFC Address
IFC Address
IFC Address
IFC Address
D11
C12
D13
C13
O
O
O
O
OVDD
OVDD
OVDD
OVDD
1
1
1
1
IFC_A23/QSPI_A_DATA1/
IFC_WP2_B
IFC_A24/QSPI_A_DATA2/
IFC_WP3_B
IFC_A25/GPIO2_25/
QSPI_A_DATA3/FTM5_CH0/
IFC_CS4_B/IFC_RB2_B
IFC_A26/GPIO2_26/
FTM5_CH1/IFC_CS5_B/
IFC_RB3_B
IFC Address
D14
O
OVDD
1
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
56
NXP Semiconductors
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
IFC_A27/GPIO2_27/
IFC Address
C14
O
OVDD
1
FTM5_EXTCLK/IFC_CS6_B
IFC_AD00/cfg_gpinput0
IFC_AD01/cfg_gpinput1
IFC_AD02/cfg_gpinput2
IFC_AD03/cfg_gpinput3
IFC_AD04/cfg_gpinput4
IFC_AD05/cfg_gpinput5
IFC_AD06/cfg_gpinput6
IFC_AD07/cfg_gpinput7
IFC_AD08/cfg_rcw_src0
IFC_AD09/cfg_rcw_src1
IFC_AD10/cfg_rcw_src2
IFC_AD11/cfg_rcw_src3
IFC_AD12/cfg_rcw_src4
IFC_AD13/cfg_rcw_src5
IFC_AD14/cfg_rcw_src6
IFC_AD15/cfg_rcw_src7
IFC_AVD
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address / Data
IFC Address Valid
IFC Buffer control
B8
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
4
A8
4
B9
4
A9
4
A10
B11
A11
B12
A12
A13
B14
A14
B15
A15
A16
A17
A18
E15
C19
4
4
4
4
4
4
4
4
4
4
4
4
1, 5
2
IFC_BCTL
O
IFC_CLE/cfg_rcw_src8
IFC Command Latch Enable /
Write Enable
O
1, 4
IFC_CLK0
IFC_CLK1
IFC_CS0_B
IFC Clock
A20
B20
C17
A19
O
O
O
O
OVDD
OVDD
OVDD
OVDD
2
IFC Clock
2
IFC Chip Select
IFC Chip Select
1, 6
1, 6
IFC_CS1_B/GPIO2_10/
FTM7_CH0
IFC_CS2_B/GPIO2_11/
FTM7_CH1
IFC Chip Select
IFC Chip Select
D20
C20
O
O
OVDD
OVDD
1, 6
1, 6
IFC_CS3_B/GPIO2_12/
QSPI_B_DATA3/
FTM7_EXTCLK
IFC_CS4_B/IFC_A25/
GPIO2_25/QSPI_A_DATA3/
FTM5_CH0/IFC_RB2_B
IFC Chip Select
IFC Chip Select
C13
D14
O
O
OVDD
OVDD
1
1
IFC_CS5_B/IFC_A26/
GPIO2_26/FTM5_CH1/
IFC_RB3_B
IFC_CS6_B/IFC_A27/
GPIO2_27/FTM5_EXTCLK
IFC Chip Select
C14
E16
O
O
OVDD
OVDD
1
2
IFC_NDDDR_CLK
IFC NAND DDR Clock
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
57
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
IFC_NDDQS
IFC DQS Strobe
B17
C18
B18
IO
O
OVDD
---
IFC_OE_B/cfg_eng_use1
IFC Output Enable
OVDD
OVDD
1, 4, 21
---
IFC_PAR0/GPIO2_13/
IFC Address & Data Parity
IO
QSPI_B_DATA0/FTM6_CH0
IFC_PAR1/GPIO2_14/
QSPI_B_DATA1/FTM6_CH1
IFC Address & Data Parity
IFC Parity Error
D17
E17
IO
I
OVDD
OVDD
---
1
IFC_PERR_B/GPIO2_15/
QSPI_B_DATA2/
FTM6_EXTCLK
IFC_RB0_B
IFC_RB1_B
IFC Ready / Busy CS0
IFC Ready / Busy CS1
IFC Ready/Busy CS 2
C16
D16
C13
I
I
I
OVDD
OVDD
OVDD
6
6
1
IFC_RB2_B/IFC_A25/
GPIO2_25/QSPI_A_DATA3/
FTM5_CH0/IFC_CS4_B
IFC_RB3_B/IFC_A26/
GPIO2_26/FTM5_CH1/
IFC_CS5_B
IFC Ready/Busy CS 3
D14
E14
I
OVDD
OVDD
1
IFC_TE/cfg_ifc_te
IFC External Transceiver
Enable
O
1, 4
IFC_WE0_B/cfg_eng_use0
IFC_WP0_B/cfg_eng_use2
IFC Write Enable
IFC Write Protect
IFC Write Protect
C15
D19
D11
O
O
O
OVDD
OVDD
OVDD
1, 4, 21
1, 4, 21
1
IFC_WP1_B/IFC_A22/
QSPI_A_DATA0
IFC_WP2_B/IFC_A23/
QSPI_A_DATA1
IFC Write Protect
IFC Write Protect
C12
D13
O
O
OVDD
OVDD
1
1
IFC_WP3_B/IFC_A24/
QSPI_A_DATA2
DUART
UART1_CTS_B/GPIO1_21/
UART3_SIN/FTM4_CH4/
LPUART2_SIN
Clear To Send
Ready to Send
J1
J2
I
DVDD
DVDD
1
1
UART1_RTS_B/GPIO1_19/
UART3_SOUT/
O
LPUART2_SOUT/FTM4_CH2
UART1_SIN/GPIO1_17
Receive Data
Transmit Data
Clear To Send
H2
H1
M2
I
O
I
DVDD
DVDD
DVDD
1
1
1
UART1_SOUT/GPIO1_15
UART2_CTS_B/GPIO1_22/
UART4_SIN/FTM4_CH5/
LPUART1_CTS_B/
LPUART4_SIN
UART2_RTS_B/GPIO1_20/
UART4_SOUT/
Ready to Send
L1
O
DVDD
1
LPUART4_SOUT/FTM4_CH3/
LPUART1_RTS_B
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
58
NXP Semiconductors
Pin assignments
Notes
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
UART2_SIN/GPIO1_18/
FTM4_CH1/LPUART1_SIN
Receive Data
Transmit Data
K1
L2
J1
I
O
I
DVDD
1
1
1
UART2_SOUT/GPIO1_16/
LPUART1_SOUT/FTM4_CH0
DVDD
DVDD
UART3_SIN/UART1_CTS_B/ Receive Data
GPIO1_21/FTM4_CH4/
LPUART2_SIN
UART3_SOUT/
UART1_RTS_B/GPIO1_19/
LPUART2_SOUT/FTM4_CH2
Transmit Data
J2
O
I
DVDD
DVDD
1
1
UART4_SIN/UART2_CTS_B/ Receive Data
GPIO1_22/FTM4_CH5/
M2
LPUART1_CTS_B/
LPUART4_SIN
UART4_SOUT/
Transmit Data
L1
O
DVDD
1
UART2_RTS_B/GPIO1_20/
LPUART4_SOUT/FTM4_CH3/
LPUART1_RTS_B
SPI Interface
SPI_PCS0/GPIO2_00/
SDHC_DAT4/SDHC_VS
SPI Chip Select
SPI Chip Select
U1
R3
O
O
OVDD
OVDD
1
1
SPI_PCS1/GPIO2_01/
SDHC_DAT5/
SDHC_CMD_DIR
SPI_PCS2/GPIO2_02/
SDHC_DAT6/
SDHC_DAT0_DIR
SPI Chip Select
SPI Chip Select
T3
V1
O
O
OVDD
OVDD
1
1
SPI_PCS3/GPIO2_03/
SDHC_DAT7/
SDHC_DAT123_DIR
SPI_SCK
SPI Clock
U2
U3
O
I
OVDD
OVDD
1
1
SPI_SIN/
Master In Slave Out
SDHC_CLK_SYNC_IN
SPI_SOUT/
SDHC_CLK_SYNC_OUT
Master Out Slave In
Command
V3
K3
IO
I
OVDD
DVDD
---
1
eSDHC
SDHC_CD_B/IIC2_SCL/
GPIO4_02/FTM3_QD_PHA/
CLK9/QE_SI1_STROBE0/
BRGO2
SDHC_CLK/GPIO2_09/
LPUART3_CTS_B/
LPUART6_SIN/
Host to Card Clock
P3
U3
O
I
EVDD
1
1
FTM4_QD_PHB
SDHC_CLK_SYNC_IN/
IN
OVDD
SPI_SIN
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
59
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
SDHC_CLK_SYNC_OUT/
SPI_SOUT
OUT
Command/Response
V3
P2
R3
P1
T3
R2
O
IO
O
OVDD
1
SDHC_CMD/GPIO2_04/
LPUART3_SOUT/FTM4_CH6
EVDD
OVDD
EVDD
OVDD
EVDD
---
1
SDHC_CMD_DIR/SPI_PCS1/ DIR
GPIO2_01/SDHC_DAT5
SDHC_DAT0/GPIO2_05/
FTM4_CH7/LPUART3_SIN
Data
IO
O
---
1
SDHC_DAT0_DIR/SPI_PCS2/ DIR
GPIO2_02/SDHC_DAT6
SDHC_DAT1/GPIO2_06/
LPUART5_SOUT/
FTM4_FAULT/
Data
IO
---
LPUART2_RTS_B
SDHC_DAT123_DIR/
SPI_PCS3/GPIO2_03/
SDHC_DAT7
DIR
V1
R1
O
OVDD
EVDD
1
SDHC_DAT2/GPIO2_07/
LPUART2_CTS_B/
LPUART5_SIN/
Data
IO
---
FTM4_EXTCLK
SDHC_DAT3/GPIO2_08/
LPUART6_SOUT/
FTM4_QD_PHA/
Data
T1
IO
EVDD
---
LPUART3_RTS_B
SDHC_DAT4/SPI_PCS0/
GPIO2_00/SDHC_VS
Data
Data
Data
Data
U1
R3
T3
V1
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
---
---
---
---
SDHC_DAT5/SPI_PCS1/
GPIO2_01/SDHC_CMD_DIR
SDHC_DAT6/SPI_PCS2/
GPIO2_02/SDHC_DAT0_DIR
SDHC_DAT7/SPI_PCS3/
GPIO2_03/
SDHC_DAT123_DIR
SDHC_VS/SPI_PCS0/
GPIO2_00/SDHC_DAT4
VS
U1
L3
O
I
OVDD
DVDD
1
1
SDHC_WP/IIC2_SDA/
GPIO4_03/FTM3_QD_PHB/
CLK10/QE_SI1_STROBE1/
BRGO3
Write Protect
Programmable Interrupt Controller
EVT9_B
IRQ00
IRQ01
IRQ02
Interrupt Output
G7
F11
F15
H7
O
I
OVDD
OVDD
OVDD
OVDD
1, 6, 7
External Interrupt
External Interrupt
External Interrupt
1
1
1
I
I
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
60
NXP Semiconductors
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
IRQ03/GPIO1_23/FTM3_CH7/ External Interrupt
TDMB_TSYNC/
UC3_RTSB_TXEN
J3
I
I
I
I
I
I
I
I
DVDD
1
1
1
1
1
1
1
1
IRQ04/GPIO1_24/FTM3_CH0/ External Interrupt
TDMA_RXD/UC1_RXD7/
TDMA_TXD
J4
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
IRQ05/GPIO1_25/FTM3_CH1/ External Interrupt
TDMA_RSYNC/
UC1_CTSB_RXDV
J5
IRQ06/GPIO1_26/FTM3_CH2/ External Interrupt
TDMA_RXD_EXC/
TDMA_TXD/UC1_TXD7
K5
L5
IRQ07/GPIO1_27/FTM3_CH3/ External Interrupt
TDMA_TSYNC/
UC1_RTSB_TXEN
IRQ08/GPIO1_28/FTM3_CH4/ External Interrupt
TDMB_RXD/UC3_RXD7/
TDMB_TXD
M5
N5
P4
W3
IRQ09/GPIO1_29/FTM3_CH5/ External Interrupt
TDMB_RSYNC/
UC3_CTSB_RXDV
IRQ10/GPIO1_30/FTM3_CH6/ External Interrupt
TDMB_RXD_EXC/
TDMB_TXD/UC3_TXD7
IRQ11/GPIO1_31
External Interrupt
I
I
I
LVDD
1
Battery Backed Trust
TA_BB_TMP_DETECT_B
TA_TMP_DETECT_B
Battery Backed Tamper Detect
Trust
H12
TA_BB_VDD
OVDD
---
1
Tamper Detect
H20
System Control
HRESET_B
Hard Reset
F8
F9
IO
I
OVDD
OVDD
OVDD
6, 7
---
PORESET_B
RESET_REQ_B
Power On Reset
Reset Request (POR or Hard)
F10
O
1, 5
Power Management
ASLEEP/GPIO1_13
SYSCLK
Asleep
E9
O
I
OVDD
OVDD
OVDD
OVDD
OVDD
1, 4
18
SYSCLK
System Clock
DDR Clocking
DDR Controller Clock
RTC
G14
J20
F17
G15
DDRCLK
I
18
RTC/GPIO1_14
CKSTP_OUT_B
Real Time Clock
Debug
I
1
Reserved
O
6, 7
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
61
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
CLK_OUT
EVT0_B
EVT1_B
EVT2_B
EVT3_B
EVT4_B
Clock Out
G16
E10
E13
E8
O
OVDD
2
9
Event 0
Event 1
Event 2
Event 3
Event 4
IO
IO
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
OVDD
DVDD
---
---
---
---
---
E12
E11
L4
EVT5_B/IIC3_SCL/GPIO4_10/ Event 5
USB2_DRVVBUS/BRGO4/
FTM8_CH0/CLK11
EVT6_B/IIC3_SDA/GPIO4_11/ Event 6
USB2_PWRFAULT/BRGO1/
FTM8_CH1/CLK12_CLK8
M4
M3
IO
IO
DVDD
DVDD
---
---
EVT7_B/IIC4_SCL/GPIO4_12/ Event 7
USB3_DRVVBUS/TDMA_RQ/
FTM3_FAULT/
UC1_CDB_RXER
EVT8_B/IIC4_SDA/GPIO4_13/ Event 8
USB3_PWRFAULT/
N3
IO
DVDD
---
TDMB_RQ/FTM3_EXTCLK/
UC3_CDB_RXER
DFT
JTAG_BSR_VSEL
An IEEE 1149.1 JTAG
compliance enable pin. 0:
J19
I
OVDD
36
Normal operation. 1: To be
compliant to the 1149.1
specification for boundary scan
functions. The JTAG compliant
state is documented in the
BSDL.
SCAN_MODE_B
TBSCAN_EN_B
Reserved
H19
F19
I
I
OVDD
OVDD
10
35
An IEEE 1149.1 JTAG
compliance enable pin. 0:To be
compliant to the 1149.1
specification for boundary scan
functions. The JTAG compliant
state is documented in the
BSDL. 1: JTAG connects to
DAP controller for the ARM
core debug.
TEST_SEL_B
Reserved
F20
I
OVDD
23
JTAG
TCK
TDI
Test Clock
Test Data In
Test Data Out
Test Mode Select
E18
G17
E20
G18
I
I
OVDD
OVDD
OVDD
OVDD
---
9
TDO
TMS
O
I
2
9
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
62
NXP Semiconductors
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
TRST_B
Test Reset
E19
I
OVDD
9
Analog Signals
D1_MVREF
D1_TPA
SSTL Reference Voltage
P21
F21
IO
IO
G1VDD/2
---
DDR Controller 1 Test Point
Analog
12
FA_ANALOG_G_V
FA_ANALOG_PIN
TD1_ANODE
Reserved
T5
U4
IO
IO
IO
IO
-
15
15
17
17
12
Reserved
Thermal diode anode
Thermal diode cathode
Thermal Test Point Analog
J13
H13
H8
TD1_CATHODE
TH_TPA
-
SerDes
SD1_IMP_CAL_RX
SD1_IMP_CAL_TX
SD1_PLL1_TPA
SerDes Receive Impedence
Calibration
Y11
Y20
I
I
S1VDD
11
16
12
SerDes Transmit Impedance
Calibration
X1VDD
SerDes PLL 1 Test Point
Analog
AF12
O
AVDD_SD1_PLL1
SD1_PLL1_TPD
SD1_PLL2_TPA
SerDes Test Point Digital
AF13
AF20
O
O
X1VDD
12
12
SerDes PLL 2 Test Point
Analog
AVDD_SD1_PLL2
SD1_PLL2_TPD
SerDes Test Point Digital
AA20
AB8
O
I
X1VDD
S1VDD
12
---
SD1_REF_CLK1_N
SerDes PLL 1 Reference Clock
Complement
SD1_REF_CLK1_P
SD1_REF_CLK2_N
SerDes PLL 1 Reference Clock
AA8
I
I
S1VDD
S1VDD
---
---
SerDes PLL 2 Reference Clock
Complement
AB19
SD1_REF_CLK2_P
SD1_RX0_N
SerDes PLL 2 Reference Clock
AB18
AH6
I
I
S1VDD
S1VDD
---
---
SerDes Receive Data
(negative)
SD1_RX0_P
SD1_RX1_N
SD1_RX1_P
SD1_RX2_N
SD1_RX2_P
SD1_RX3_N
SerDes Receive Data
(positive)
AG6
AH10
AG10
AH16
AG16
AH19
I
I
I
I
I
I
S1VDD
S1VDD
S1VDD
S1VDD
S1VDD
S1VDD
---
---
---
---
---
---
SerDes Receive Data
(negative)
SerDes Receive Data
(positive)
SerDes Receive Data
(negative)
SerDes Receive Data
(positive)
SerDes Receive Data
(negative)
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
63
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
SD1_RX3_P
SD1_TX0_N
SD1_TX0_P
SD1_TX1_N
SD1_TX1_P
SD1_TX2_N
SD1_TX2_P
SD1_TX3_N
SD1_TX3_P
SerDes Receive Data
(positive)
AG19
I
S1VDD
---
SerDes Transmit Data
(negative)
AE6
O
O
O
O
O
O
O
O
X1VDD
X1VDD
X1VDD
X1VDD
X1VDD
X1VDD
X1VDD
X1VDD
---
---
---
---
---
---
---
---
SerDes Transmit Data
(positive)
AD6
SerDes Transmit Data
(negative)
AE10
AD10
AE16
AD16
AE19
AD19
SerDes Transmit Data
(positive)
SerDes Transmit Data
(negative)
SerDes Transmit Data
(positive)
SerDes Transmit Data
(negative)
SerDes Transmit Data
(positive)
USB3 PHY 1
USB1_D_M
USB1_D_P
USB1_ID
USB PHY HS Data (-)
USB PHY HS Data (+)
USB PHY ID Detect
E6
F6
F5
G3
IO
IO
I
USB_HVDD
---
---
29
27
USB_HVDD
-
-
USB1_RESREF
USB PHY Impedance
Calibration
IO
USB1_RX_M
USB1_RX_P
USB1_TX_M
USB1_TX_P
USB PHY SS Receive Data (-)
USB PHY SS Receive Data (+)
USB PHY SS Transmit Data (-)
E4
E3
F2
F1
I
USB_SVDD
USB_SVDD
USB_SVDD
USB_SVDD
---
---
---
---
I
O
O
USB PHY SS Transmit Data
(+)
USB1_VBUS
USB PHY VBUS
E7
I
-
28
USB3 PHY 2
USB2_D_M
USB2_D_P
USB2_ID
USB PHY HS Data (-)
USB PHY HS Data (+)
USB PHY ID Detect
C6
D6
D5
G4
IO
IO
I
USB_HVDD
---
---
29
27
USB_HVDD
-
-
USB2_RESREF
USB PHY Impedance
Calibration
IO
USB2_RX_M
USB2_RX_P
USB2_TX_M
USB2_TX_P
USB PHY SS Receive Data (-)
USB PHY SS Receive Data (+)
USB PHY SS Transmit Data (-)
C4
C3
D2
D1
I
USB_SVDD
USB_SVDD
USB_SVDD
USB_SVDD
---
---
---
---
I
O
O
USB PHY SS Transmit Data
(+)
USB2_VBUS
USB PHY VBUS
C7
I
-
28
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
64
NXP Semiconductors
Pin assignments
Notes
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
USB3 PHY 3
USB3_D_M
USB3_D_P
USB3_ID
USB PHY HS Data (-)
USB PHY HS Data (+)
USB PHY ID Detect
A6
B6
B5
G5
IO
IO
I
USB_HVDD
---
---
29
27
USB_HVDD
-
-
USB3_RESREF
USB PHY Impedance
Calibration
IO
USB3_RX_M
USB3_RX_P
USB3_TX_M
USB3_TX_P
USB PHY SS Receive Data (-)
USB PHY SS Receive Data (+)
USB PHY SS Transmit Data (-)
A4
A3
B2
B1
I
USB_SVDD
USB_SVDD
USB_SVDD
USB_SVDD
---
---
---
---
I
O
O
USB PHY SS Transmit Data
(+)
USB3_VBUS
USB PHY VBUS
A7
I
-
28
Ethernet Management Interface 1
EMI1_MDC/GPIO3_00
EMI1_MDIO/GPIO3_01
Management Data Clock
Management Data In/Out
AG2
AF2
O
LVDD
LVDD
1
IO
---
Ethernet Management Interface 2
EMI2_MDC/GPIO4_00
EMI2_MDIO/GPIO4_01
Management Data Clock
AH4
AH3
O
TVDD
TVDD
1
Management Data In/Out
Transmit Clock Out
IO
---
Ethernet Controller 1
EC1_GTX_CLK/GPIO3_07/
W4
O
LVDD
1
FTM1_EXTCLK
EC1_GTX_CLK125/GPIO3_08 Reference Clock
AC3
AA2
I
I
LVDD
LVDD
1
1
EC1_RXD0/GPIO3_12/
Receive Data
Receive Data
Receive Data
Receive Data
Receive Clock
Receive Data Valid
Transmit Data
Transmit Data
Transmit Data
Transmit Data
FTM1_CH0
EC1_RXD1/GPIO3_11/
FTM1_CH1
AA1
Y1
I
I
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
1
1
1
1
1
1
1
1
1
EC1_RXD2/GPIO3_10/
FTM1_CH6
EC1_RXD3/GPIO3_09/
FTM1_CH4
W2
W1
AB1
AB3
AA3
Y4
I
EC1_RX_CLK/GPIO3_13/
FTM1_QD_PHA
I
EC1_RX_DV/GPIO3_14/
FTM1_QD_PHB
I
EC1_TXD0/GPIO3_05/
FTM1_CH2
O
O
O
O
EC1_TXD1/GPIO3_04/
FTM1_CH3
EC1_TXD2/GPIO3_03/
FTM1_CH7
EC1_TXD3/GPIO3_02/
Y3
FTM1_CH5
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
65
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
EC1_TX_EN/GPIO3_06/
FTM1_FAULT
Transmit Enable
AB4
O
O
LVDD
1, 14
Ethernet Controller 2
EC2_GTX_CLK/GPIO3_20/
Transmit Clock Out
AC4
LVDD
1
FTM2_EXTCLK
EC2_GTX_CLK125/GPIO3_21 Reference Clock
AG4
AE2
I
I
LVDD
LVDD
1
1
EC2_RXD0/GPIO3_25/
TSEC_1588_TRIG_IN2/
FTM2_CH0
Receive Data
EC2_RXD1/GPIO3_24/
TSEC_1588_PULSE_OUT1/
FTM2_CH1
Receive Data
AE1
I
LVDD
1
EC2_RXD2/GPIO3_23/
FTM2_CH6
Receive Data
Receive Data
Receive Clock
AD1
AC2
AC1
I
I
I
LVDD
LVDD
LVDD
1
1
1
EC2_RXD3/GPIO3_22/
FTM2_CH4
EC2_RX_CLK/GPIO3_26/
TSEC_1588_CLK_IN/
FTM2_QD_PHA
EC2_RX_DV/GPIO3_27/
TSEC_1588_TRIG_IN1/
FTM2_QD_PHB
Receive Data Valid
Transmit Data
Transmit Data
Transmit Data
Transmit Data
Transmit Enable
AF1
AF3
AE4
AE3
AD3
AG3
I
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
1
EC2_TXD0/GPIO3_18/
TSEC_1588_PULSE_OUT2/
FTM2_CH2
O
O
O
O
O
1
EC2_TXD1/GPIO3_17/
TSEC_1588_CLK_OUT/
FTM2_CH3
1
EC2_TXD2/GPIO3_16/
TSEC_1588_ALARM_OUT1/
FTM2_CH7
1
EC2_TXD3/GPIO3_15/
TSEC_1588_ALARM_OUT2/
FTM2_CH5
1
EC2_TX_EN/GPIO3_19/
1, 14
FTM2_FAULT
I2C
IIC1_SCL
IIC1_SDA
Serial Clock (supports PBL)
Serial Data (supports PBL)
Serial Clock
N1
M1
K3
IO
IO
IO
DVDD
DVDD
DVDD
7, 8
7, 8
7, 8
IIC2_SCL/GPIO4_02/
SDHC_CD_B/FTM3_QD_PHA/
CLK9/QE_SI1_STROBE0/
BRGO2
IIC2_SDA/GPIO4_03/
Serial Data
L3
IO
DVDD
7, 8
SDHC_WP/FTM3_QD_PHB/
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
66
NXP Semiconductors
Pin assignments
Notes
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
CLK10/QE_SI1_STROBE1/
BRGO3
IIC3_SCL/GPIO4_10/EVT5_B/ Serial Clock
USB2_DRVVBUS/BRGO4/
FTM8_CH0/CLK11
L4
M4
M3
IO
IO
IO
DVDD
7, 8
7, 8
7, 8
IIC3_SDA/GPIO4_11/EVT6_B/ Serial Data
USB2_PWRFAULT/BRGO1/
FTM8_CH1/CLK12_CLK8
DVDD
DVDD
IIC4_SCL/GPIO4_12/EVT7_B/ Serial Clock
USB3_DRVVBUS/TDMA_RQ/
FTM3_FAULT/
UC1_CDB_RXER
IIC4_SDA/GPIO4_13/EVT8_B/ Serial Data
USB3_PWRFAULT/
N3
IO
DVDD
7, 8
TDMB_RQ/FTM3_EXTCLK/
UC3_CDB_RXER
USB
USB2_DRVVBUS/IIC3_SCL/ DRV VBus
GPIO4_10/EVT5_B/BRGO4/
FTM8_CH0/CLK11
L4
M4
M3
O
I
DVDD
DVDD
DVDD
1
1
1
USB2_PWRFAULT/IIC3_SDA/ PWR Fault
GPIO4_11/EVT6_B/BRGO1/
FTM8_CH1/CLK12_CLK8
USB3_DRVVBUS/IIC4_SCL/ DRV Bus
GPIO4_12/EVT7_B/
O
TDMA_RQ/FTM3_FAULT/
UC1_CDB_RXER
USB3_PWRFAULT/IIC4_SDA/ PWR Fault
GPIO4_13/EVT8_B/
N3
I
DVDD
1
TDMB_RQ/FTM3_EXTCLK/
UC3_CDB_RXER
USB_DRVVBUS/GPIO4_29
USB_DRVVBUS
H6
G6
O
I
DVDD
DVDD
1
1
USB_PWRFAULT/GPIO4_30 USB_PWRFAULT
Battery Backed RTC
F12
TA_BB_RTC
Reserved
I
TA_BB_VDD
33
DSYSCLK
DIFF_SYSCLK
Single Source System Clock
Differential (positive)
AA13
AB13
I
I
OVDD
OVDD
19
19
DIFF_SYSCLK_B
Single Source System Clock
Differential (negative)
Power-On-Reset Configuration
cfg_dram_type/IFC_A21/
Power-on-Reset Configuration
C11
I
OVDD
1, 4
QSPI_B_SCK
cfg_eng_use0/IFC_WE0_B
cfg_eng_use1/IFC_OE_B
Power-on-Reset Configuration
Power-on-Reset Configuration
C15
C18
I
I
OVDD
OVDD
1, 4
1, 4
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
67
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
cfg_eng_use2/IFC_WP0_B
cfg_gpinput0/IFC_AD00
cfg_gpinput1/IFC_AD01
cfg_gpinput2/IFC_AD02
cfg_gpinput3/IFC_AD03
cfg_gpinput4/IFC_AD04
cfg_gpinput5/IFC_AD05
cfg_gpinput6/IFC_AD06
cfg_gpinput7/IFC_AD07
cfg_ifc_te/IFC_TE
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
Power-on-Reset Configuration
D19
B8
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
OVDD
1, 4
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
A8
B9
A9
A10
B11
A11
B12
E14
A12
A13
B14
A14
B15
A15
A16
A17
C19
cfg_rcw_src0/IFC_AD08
cfg_rcw_src1/IFC_AD09
cfg_rcw_src2/IFC_AD10
cfg_rcw_src3/IFC_AD11
cfg_rcw_src4/IFC_AD12
cfg_rcw_src5/IFC_AD13
cfg_rcw_src6/IFC_AD14
cfg_rcw_src7/IFC_AD15
cfg_rcw_src8/IFC_CLE
General Purpose Input/Output
GPIO1_13/ASLEEP
GPIO1_14/RTC
General Purpose Input/Output
E9
F17
H1
L2
O
OVDD
OVDD
DVDD
DVDD
1, 4
---
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
IO
IO
IO
GPIO1_15/UART1_SOUT
---
GPIO1_16/UART2_SOUT/
---
LPUART1_SOUT/FTM4_CH0
GPIO1_17/UART1_SIN
General Purpose Input/Output
General Purpose Input/Output
H2
K1
IO
IO
DVDD
DVDD
---
---
GPIO1_18/UART2_SIN/
FTM4_CH1/LPUART1_SIN
GPIO1_19/UART1_RTS_B/
UART3_SOUT/
LPUART2_SOUT/FTM4_CH2
General Purpose Input/Output
General Purpose Input/Output
J2
L1
IO
IO
DVDD
DVDD
---
---
GPIO1_20/UART2_RTS_B/
UART4_SOUT/
LPUART4_SOUT/FTM4_CH3/
LPUART1_RTS_B
GPIO1_21/UART1_CTS_B/
UART3_SIN/FTM4_CH4/
LPUART2_SIN
General Purpose Input/Output
General Purpose Input/Output
J1
IO
IO
DVDD
DVDD
---
---
GPIO1_22/UART2_CTS_B/
M2
UART4_SIN/FTM4_CH5/
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
68
NXP Semiconductors
Pin assignments
Notes
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
LPUART1_CTS_B/
LPUART4_SIN
GPIO1_23/IRQ03/FTM3_CH7/ General Purpose Input/Output
TDMB_TSYNC/
UC3_RTSB_TXEN
J3
J4
IO
IO
IO
IO
IO
IO
IO
IO
DVDD
---
---
---
---
---
---
---
---
GPIO1_24/IRQ04/FTM3_CH0/ General Purpose Input/Output
TDMA_RXD/UC1_RXD7/
TDMA_TXD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
GPIO1_25/IRQ05/FTM3_CH1/ General Purpose Input/Output
TDMA_RSYNC/
UC1_CTSB_RXDV
J5
GPIO1_26/IRQ06/FTM3_CH2/ General Purpose Input/Output
TDMA_RXD_EXC/
TDMA_TXD/UC1_TXD7
K5
L5
M5
N5
P4
GPIO1_27/IRQ07/FTM3_CH3/ General Purpose Input/Output
TDMA_TSYNC/
UC1_RTSB_TXEN
GPIO1_28/IRQ08/FTM3_CH4/ General Purpose Input/Output
TDMB_RXD/UC3_RXD7/
TDMB_TXD
GPIO1_29/IRQ09/FTM3_CH5/ General Purpose Input/Output
TDMB_RSYNC/
UC3_CTSB_RXDV
GPIO1_30/IRQ10/FTM3_CH6/ General Purpose Input/Output
TDMB_RXD_EXC/
TDMB_TXD/UC3_TXD7
GPIO1_31/IRQ11
General Purpose Input/Output
General Purpose Input/Output
W3
U1
IO
IO
LVDD
OVDD
---
---
GPIO2_00/SPI_PCS0/
SDHC_DAT4/SDHC_VS
GPIO2_01/SPI_PCS1/
SDHC_DAT5/
SDHC_CMD_DIR
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
R3
T3
V1
IO
IO
IO
OVDD
OVDD
OVDD
---
---
---
GPIO2_02/SPI_PCS2/
SDHC_DAT6/
SDHC_DAT0_DIR
GPIO2_03/SPI_PCS3/
SDHC_DAT7/
SDHC_DAT123_DIR
GPIO2_04/SDHC_CMD/
LPUART3_SOUT/FTM4_CH6
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
P2
P1
R2
IO
IO
IO
EVDD
EVDD
EVDD
---
---
---
GPIO2_05/SDHC_DAT0/
FTM4_CH7/LPUART3_SIN
GPIO2_06/SDHC_DAT1/
LPUART5_SOUT/
FTM4_FAULT/
LPUART2_RTS_B
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
69
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
GPIO2_07/SDHC_DAT2/
LPUART2_CTS_B/
LPUART5_SIN/
General Purpose Input/Output
R1
T1
P3
IO
IO
IO
EVDD
---
FTM4_EXTCLK
GPIO2_08/SDHC_DAT3/
LPUART6_SOUT/
FTM4_QD_PHA/
General Purpose Input/Output
General Purpose Input/Output
EVDD
---
---
LPUART3_RTS_B
GPIO2_09/SDHC_CLK/
LPUART3_CTS_B/
LPUART6_SIN/
EVDD
FTM4_QD_PHB
GPIO2_10/IFC_CS1_B/
FTM7_CH0
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
A19
D20
C20
IO
IO
IO
OVDD
OVDD
OVDD
---
---
---
GPIO2_11/IFC_CS2_B/
FTM7_CH1
GPIO2_12/IFC_CS3_B/
QSPI_B_DATA3/
FTM7_EXTCLK
GPIO2_13/IFC_PAR0/
QSPI_B_DATA0/FTM6_CH0
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
B18
D17
E17
IO
IO
IO
OVDD
OVDD
OVDD
---
---
---
GPIO2_14/IFC_PAR1/
QSPI_B_DATA1/FTM6_CH1
GPIO2_15/IFC_PERR_B/
QSPI_B_DATA2/
FTM6_EXTCLK
GPIO2_25/IFC_A25/
QSPI_A_DATA3/FTM5_CH0/
IFC_CS4_B/IFC_RB2_B
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
C13
D14
C14
IO
IO
IO
OVDD
OVDD
OVDD
---
---
---
GPIO2_26/IFC_A26/
FTM5_CH1/IFC_CS5_B/
IFC_RB3_B
GPIO2_27/IFC_A27/
FTM5_EXTCLK/IFC_CS6_B
GPIO3_00/EMI1_MDC
GPIO3_01/EMI1_MDIO
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
AG2
AF2
Y3
IO
IO
IO
LVDD
LVDD
LVDD
---
---
---
GPIO3_02/EC1_TXD3/
FTM1_CH5
GPIO3_03/EC1_TXD2/
FTM1_CH7
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
Y4
IO
IO
IO
IO
LVDD
LVDD
LVDD
LVDD
---
---
---
---
GPIO3_04/EC1_TXD1/
FTM1_CH3
AA3
AB3
AB4
GPIO3_05/EC1_TXD0/
FTM1_CH2
GPIO3_06/EC1_TX_EN/
FTM1_FAULT
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
70
NXP Semiconductors
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
GPIO3_07/EC1_GTX_CLK/
General Purpose Input/Output
W4
IO
LVDD
---
FTM1_EXTCLK
GPIO3_08/EC1_GTX_CLK125 General Purpose Input/Output
AC3
W2
IO
IO
LVDD
LVDD
---
---
GPIO3_09/EC1_RXD3/
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
FTM1_CH4
GPIO3_10/EC1_RXD2/
FTM1_CH6
Y1
IO
IO
IO
IO
IO
IO
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
---
---
---
---
---
---
GPIO3_11/EC1_RXD1/
FTM1_CH1
AA1
AA2
W1
GPIO3_12/EC1_RXD0/
FTM1_CH0
GPIO3_13/EC1_RX_CLK/
FTM1_QD_PHA
GPIO3_14/EC1_RX_DV/
AB1
AD3
FTM1_QD_PHB
GPIO3_15/EC2_TXD3/
TSEC_1588_ALARM_OUT2/
FTM2_CH5
GPIO3_16/EC2_TXD2/
TSEC_1588_ALARM_OUT1/
FTM2_CH7
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
AE3
AE4
AF3
IO
IO
IO
LVDD
LVDD
LVDD
---
---
---
GPIO3_17/EC2_TXD1/
TSEC_1588_CLK_OUT/
FTM2_CH3
GPIO3_18/EC2_TXD0/
TSEC_1588_PULSE_OUT2/
FTM2_CH2
GPIO3_19/EC2_TX_EN/
FTM2_FAULT
General Purpose Input/Output
General Purpose Input/Output
AG3
AC4
IO
IO
LVDD
LVDD
---
---
GPIO3_20/EC2_GTX_CLK/
FTM2_EXTCLK
GPIO3_21/EC2_GTX_CLK125 General Purpose Input/Output
AG4
AC2
IO
IO
LVDD
LVDD
---
---
GPIO3_22/EC2_RXD3/
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
FTM2_CH4
GPIO3_23/EC2_RXD2/
AD1
AE1
IO
IO
LVDD
LVDD
---
---
FTM2_CH6
GPIO3_24/EC2_RXD1/
TSEC_1588_PULSE_OUT1/
FTM2_CH1
GPIO3_25/EC2_RXD0/
TSEC_1588_TRIG_IN2/
FTM2_CH0
General Purpose Input/Output
General Purpose Input/Output
AE2
AC1
IO
IO
LVDD
LVDD
---
---
GPIO3_26/EC2_RX_CLK/
TSEC_1588_CLK_IN/
FTM2_QD_PHA
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
71
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
GPIO3_27/EC2_RX_DV/
TSEC_1588_TRIG_IN1/
FTM2_QD_PHB
General Purpose Input/Output
AF1
IO
LVDD
---
GPIO4_00/EMI2_MDC
GPIO4_01/EMI2_MDIO
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
AH4
AH3
K3
IO
IO
IO
TVDD
TVDD
DVDD
---
---
---
GPIO4_02/IIC2_SCL/
SDHC_CD_B/FTM3_QD_PHA/
CLK9/QE_SI1_STROBE0/
BRGO2
GPIO4_03/IIC2_SDA/
SDHC_WP/FTM3_QD_PHB/
CLK10/QE_SI1_STROBE1/
BRGO3
General Purpose Input/Output
L3
IO
DVDD
---
GPIO4_10/IIC3_SCL/EVT5_B/ General Purpose Input/Output
USB2_DRVVBUS/BRGO4/
FTM8_CH0/CLK11
L4
M4
M3
IO
IO
IO
DVDD
DVDD
DVDD
---
---
---
GPIO4_11/IIC3_SDA/EVT6_B/ General Purpose Input/Output
USB2_PWRFAULT/BRGO1/
FTM8_CH1/CLK12_CLK8
GPIO4_12/IIC4_SCL/EVT7_B/ General Purpose Input/Output
USB3_DRVVBUS/TDMA_RQ/
FTM3_FAULT/
UC1_CDB_RXER
GPIO4_13/IIC4_SDA/EVT8_B/ General Purpose Input/Output
USB3_PWRFAULT/
N3
IO
DVDD
---
TDMB_RQ/FTM3_EXTCLK/
UC3_CDB_RXER
GPIO4_29/USB_DRVVBUS
General Purpose Input/Output
H6
G6
IO
IO
DVDD
DVDD
---
---
GPIO4_30/USB_PWRFAULT General Purpose Input/Output
Frequency Timer Module 1
FTM1_CH0/EC1_RXD0/
GPIO3_12
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
AA2
IO
IO
IO
IO
IO
IO
IO
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
---
---
---
---
---
---
---
FTM1_CH1/EC1_RXD1/
GPIO3_11
AA1
AB3
AA3
W2
Y3
FTM1_CH2/EC1_TXD0/
GPIO3_05
FTM1_CH3/EC1_TXD1/
GPIO3_04
FTM1_CH4/EC1_RXD3/
GPIO3_09
FTM1_CH5/EC1_TXD3/
GPIO3_02
FTM1_CH6/EC1_RXD2/
Y1
GPIO3_10
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
72
NXP Semiconductors
Pin assignments
Notes
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
FTM1_CH7/EC1_TXD2/
GPIO3_03
Channel 7
Y4
IO
LVDD
---
1
FTM1_EXTCLK/
EC1_GTX_CLK/GPIO3_07
Ext Clock
Fault
W4
I
I
I
I
LVDD
LVDD
LVDD
LVDD
FTM1_FAULT/EC1_TX_EN/
GPIO3_06
AB4
W1
1
FTM1_QD_PHA/
EC1_RX_CLK/GPIO3_13
Phase A
1
FTM1_QD_PHB/EC1_RX_DV/ Phase B
AB1
1
GPIO3_14
Frequency Timer Module 2
FTM2_CH0/EC2_RXD0/
GPIO3_25/
TSEC_1588_TRIG_IN2
Channel 0
Channel 1
Channel 2
Channel 3
AE2
IO
IO
IO
IO
LVDD
LVDD
LVDD
LVDD
---
---
---
---
FTM2_CH1/EC2_RXD1/
GPIO3_24/
TSEC_1588_PULSE_OUT1
AE1
AF3
AE4
FTM2_CH2/EC2_TXD0/
GPIO3_18/
TSEC_1588_PULSE_OUT2
FTM2_CH3/EC2_TXD1/
GPIO3_17/
TSEC_1588_CLK_OUT
FTM2_CH4/EC2_RXD3/
GPIO3_22
Channel 4
Channel 5
AC2
AD3
IO
IO
LVDD
LVDD
---
---
FTM2_CH5/EC2_TXD3/
GPIO3_15/
TSEC_1588_ALARM_OUT2
FTM2_CH6/EC2_RXD2/
GPIO3_23
Channel 6
Channel 7
AD1
AE3
IO
IO
LVDD
LVDD
---
---
FTM2_CH7/EC2_TXD2/
GPIO3_16/
TSEC_1588_ALARM_OUT1
FTM2_EXTCLK/
EC2_GTX_CLK/GPIO3_20
Ext Clock
Fault
AC4
AG3
AC1
I
I
I
LVDD
LVDD
LVDD
1
1
1
FTM2_FAULT/EC2_TX_EN/
GPIO3_19
FTM2_QD_PHA/
Phase A
EC2_RX_CLK/GPIO3_26/
TSEC_1588_CLK_IN
FTM2_QD_PHB/EC2_RX_DV/ Phase B
GPIO3_27/
AF1
I
LVDD
1
TSEC_1588_TRIG_IN1
Frequency Timer Module 3
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
73
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
FTM3_CH0/IRQ04/GPIO1_24/ Channel 0
TDMA_RXD/UC1_RXD7/
TDMA_TXD
J4
IO
IO
IO
IO
IO
IO
IO
IO
I
DVDD
---
FTM3_CH1/IRQ05/GPIO1_25/ Channel 1
TDMA_RSYNC/
UC1_CTSB_RXDV
J5
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
LVDD
DVDD
---
---
---
---
---
---
---
1
FTM3_CH2/IRQ06/GPIO1_26/ Channel 2
TDMA_RXD_EXC/
TDMA_TXD/UC1_TXD7
K5
L5
M5
N5
P4
J3
FTM3_CH3/IRQ07/GPIO1_27/ Channel 3
TDMA_TSYNC/
UC1_RTSB_TXEN
FTM3_CH4/IRQ08/GPIO1_28/ Channel 4
TDMB_RXD/UC3_RXD7/
TDMB_TXD
FTM3_CH5/IRQ09/GPIO1_29/ Channel 5
TDMB_RSYNC/
UC3_CTSB_RXDV
FTM3_CH6/IRQ10/GPIO1_30/ Channel 6
TDMB_RXD_EXC/
TDMB_TXD/UC3_TXD7
FTM3_CH7/IRQ03/GPIO1_23/ Channel 7
TDMB_TSYNC/
UC3_RTSB_TXEN
FTM3_EXTCLK/IIC4_SDA/
GPIO4_13/EVT8_B/
Ext Clock
N3
USB3_PWRFAULT/
TDMB_RQ/UC3_CDB_RXER
FTM3_FAULT/IIC4_SCL/
GPIO4_12/EVT7_B/
USB3_DRVVBUS/TDMA_RQ/
UC1_CDB_RXER
Fault
M3
K3
L3
I
I
I
DVDD
DVDD
DVDD
1
1
1
FTM3_QD_PHA/IIC2_SCL/
GPIO4_02/SDHC_CD_B/
CLK9/QE_SI1_STROBE0/
BRGO2
Phase A
Phase B
FTM3_QD_PHB/IIC2_SDA/
GPIO4_03/SDHC_WP/CLK10/
QE_SI1_STROBE1/BRGO3
Frequency Timer Module 4
FTM4_CH0/UART2_SOUT/
GPIO1_16/LPUART1_SOUT
Channel 0
Channel 1
Channel 2
L2
IO
IO
IO
DVDD
DVDD
DVDD
---
---
---
FTM4_CH1/UART2_SIN/
GPIO1_18/LPUART1_SIN
K1
J2
FTM4_CH2/UART1_RTS_B/
GPIO1_19/UART3_SOUT/
LPUART2_SOUT
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
74
NXP Semiconductors
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
FTM4_CH3/UART2_RTS_B/
GPIO1_20/UART4_SOUT/
LPUART4_SOUT/
Channel 3
L1
IO
DVDD
---
LPUART1_RTS_B
FTM4_CH4/UART1_CTS_B/
GPIO1_21/UART3_SIN/
LPUART2_SIN
Channel 4
Channel 5
J1
IO
IO
DVDD
DVDD
---
---
FTM4_CH5/UART2_CTS_B/
GPIO1_22/UART4_SIN/
LPUART1_CTS_B/
M2
LPUART4_SIN
FTM4_CH6/SDHC_CMD/
GPIO2_04/LPUART3_SOUT
Channel 6
Channel 7
P2
P1
R1
IO
IO
I
EVDD
EVDD
EVDD
---
---
1
FTM4_CH7/SDHC_DAT0/
GPIO2_05/LPUART3_SIN
FTM4_EXTCLK/SDHC_DAT2/ Ext Clock
GPIO2_07/LPUART2_CTS_B/
LPUART5_SIN
FTM4_FAULT/SDHC_DAT1/
GPIO2_06/LPUART5_SOUT/
LPUART2_RTS_B
Fault
R2
T1
P3
I
I
I
EVDD
EVDD
EVDD
1
1
1
FTM4_QD_PHA/SDHC_DAT3/ Phase A
GPIO2_08/LPUART6_SOUT/
LPUART3_RTS_B
FTM4_QD_PHB/SDHC_CLK/ Phase B
GPIO2_09/LPUART3_CTS_B/
LPUART6_SIN
Frequency Timer Module 5
FTM5_CH0/IFC_A25/
GPIO2_25/QSPI_A_DATA3/
IFC_CS4_B/IFC_RB2_B
Channel 0
Channel 1
Ext Clock
C13
IO
IO
I
OVDD
OVDD
OVDD
---
---
1
FTM5_CH1/IFC_A26/
GPIO2_26/IFC_CS5_B/
IFC_RB3_B
D14
C14
FTM5_EXTCLK/IFC_A27/
GPIO2_27/IFC_CS6_B
Frequency Timer Module 6
FTM6_CH0/IFC_PAR0/
GPIO2_13/QSPI_B_DATA0
Channel 0
Channel 1
B18
IO
IO
I
OVDD
OVDD
OVDD
---
---
1
FTM6_CH1/IFC_PAR1/
GPIO2_14/QSPI_B_DATA1
D17
E17
FTM6_EXTCLK/IFC_PERR_B/ Ext Clock
GPIO2_15/QSPI_B_DATA2
Frequency Timer Module 7
FTM7_CH0/IFC_CS1_B/
Channel 0
A19
IO
OVDD
---
GPIO2_10
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
75
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
FTM7_CH1/IFC_CS2_B/
GPIO2_11
Channel 1
D20
IO
I
OVDD
---
FTM7_EXTCLK/IFC_CS3_B/ Ext Clock
GPIO2_12/QSPI_B_DATA3
C20
OVDD
DVDD
1
Frequency Timer Module 8
FTM8_CH0/IIC3_SCL/
GPIO4_10/EVT5_B/
USB2_DRVVBUS/BRGO4/
CLK11
Channel 0
Channel 1
L4
IO
IO
---
FTM8_CH1/IIC3_SDA/
GPIO4_11/EVT6_B/
USB2_PWRFAULT/BRGO1/
CLK12_CLK8
M4
DVDD
---
LPUART
LPUART1_CTS_B/
Clear to send
M2
I
DVDD
1
1
UART2_CTS_B/GPIO1_22/
UART4_SIN/FTM4_CH5/
LPUART4_SIN
LPUART1_RTS_B/
Request to send
L1
O
DVDD
UART2_RTS_B/GPIO1_20/
UART4_SOUT/
LPUART4_SOUT/FTM4_CH3
LPUART1_SIN/UART2_SIN/
GPIO1_18/FTM4_CH1
Receive data
Transmit data
K1
L2
I
DVDD
DVDD
1
LPUART1_SOUT/
UART2_SOUT/GPIO1_16/
FTM4_CH0
IO
---
LPUART2_CTS_B/
SDHC_DAT2/GPIO2_07/
LPUART5_SIN/
Clear to send
R1
R2
I
EVDD
1
1
FTM4_EXTCLK
LPUART2_RTS_B/
SDHC_DAT1/GPIO2_06/
LPUART5_SOUT/
FTM4_FAULT
Request to send
O
EVDD
LPUART2_SIN/
UART1_CTS_B/GPIO1_21/
UART3_SIN/FTM4_CH4
Receive data
Transmit data
Clear to send
J1
J2
P3
I
IO
I
DVDD
DVDD
EVDD
1
LPUART2_SOUT/
UART1_RTS_B/GPIO1_19/
UART3_SOUT/FTM4_CH2
---
1
LPUART3_CTS_B/
SDHC_CLK/GPIO2_09/
LPUART6_SIN/
FTM4_QD_PHB
LPUART3_RTS_B/
Request to send
T1
O
EVDD
1
SDHC_DAT3/GPIO2_08/
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
76
NXP Semiconductors
Pin assignments
Notes
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
LPUART6_SOUT/
FTM4_QD_PHA
LPUART3_SIN/SDHC_DAT0/ Receive data
GPIO2_05/FTM4_CH7
P1
P2
I
EVDD
1
LPUART3_SOUT/
SDHC_CMD/GPIO2_04/
FTM4_CH6
Transmit data
Receive data
IO
EVDD
DVDD
---
LPUART4_SIN/
M2
L1
I
1
UART2_CTS_B/GPIO1_22/
UART4_SIN/FTM4_CH5/
LPUART1_CTS_B
LPUART4_SOUT/
Transmit data
IO
DVDD
---
UART2_RTS_B/GPIO1_20/
UART4_SOUT/FTM4_CH3/
LPUART1_RTS_B
LPUART5_SIN/SDHC_DAT2/ Receive data
GPIO2_07/LPUART2_CTS_B/
FTM4_EXTCLK
R1
R2
I
EVDD
EVDD
1
LPUART5_SOUT/
SDHC_DAT1/GPIO2_06/
FTM4_FAULT/
Transmit data
IO
---
LPUART2_RTS_B
LPUART6_SIN/SDHC_CLK/
GPIO2_09/LPUART3_CTS_B/
FTM4_QD_PHB
Receive data
Transmit data
P3
T1
I
EVDD
EVDD
1
LPUART6_SOUT/
SDHC_DAT3/GPIO2_08/
FTM4_QD_PHA/
IO
---
LPUART3_RTS_B
QUICC Engine
CLK10/IIC2_SDA/GPIO4_03/ CLK9
SDHC_WP/FTM3_QD_PHB/
QE_SI1_STROBE1/BRGO3
L3
L4
I
I
I
DVDD
DVDD
DVDD
1
1
1
CLK11/IIC3_SCL/GPIO4_10/ Clock 11
EVT5_B/USB2_DRVVBUS/
BRGO4/FTM8_CH0
CLK12_CLK8/IIC3_SDA/
GPIO4_11/EVT6_B/
USB2_PWRFAULT/BRGO1/
FTM8_CH1
CLK8
M4
CLK9/IIC2_SCL/GPIO4_02/
SDHC_CD_B/FTM3_QD_PHA/
QE_SI1_STROBE0/BRGO2
CLK9
K3
K3
I
DVDD
DVDD
1
1
QE_SI1_STROBE0/IIC2_SCL/ SI Strobe
GPIO4_02/SDHC_CD_B/
O
FTM3_QD_PHA/CLK9/BRGO2
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
77
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
QE_SI1_STROBE1/IIC2_SDA/ SI Strobe
GPIO4_03/SDHC_WP/
FTM3_QD_PHB/CLK10/
BRGO3
L3
O
I
DVDD
1
1
UC1_CDB_RXER/IIC4_SCL/ Receive Error
GPIO4_12/EVT7_B/
M3
DVDD
USB3_DRVVBUS/TDMA_RQ/
FTM3_FAULT
UC1_CTSB_RXDV/IRQ05/
GPIO1_25/FTM3_CH1/
TDMA_RSYNC
Receive Data
J5
L5
J4
I
O
I
DVDD
DVDD
DVDD
DVDD
DVDD
1
1
1
1
1
UC1_RTSB_TXEN/IRQ07/
GPIO1_27/FTM3_CH3/
TDMA_TSYNC
Transmit Enable
UC1_RXD7/IRQ04/GPIO1_24/ Receive Data
FTM3_CH0/TDMA_RXD/
TDMA_TXD
UC1_TXD7/IRQ06/GPIO1_26/ Transmit Data
FTM3_CH2/TDMA_RXD_EXC/
TDMA_TXD
K5
N3
O
I
UC3_CDB_RXER/IIC4_SDA/ Receive Error
GPIO4_13/EVT8_B/
USB3_PWRFAULT/
TDMB_RQ/FTM3_EXTCLK
UC3_CTSB_RXDV/IRQ09/
GPIO1_29/FTM3_CH5/
TDMB_RSYNC
Receive Data
N5
J3
I
DVDD
DVDD
DVDD
DVDD
1
1
1
1
UC3_RTSB_TXEN/IRQ03/
GPIO1_23/FTM3_CH7/
TDMB_TSYNC
Transmit Enable
O
I
UC3_RXD7/IRQ08/GPIO1_28/ Receive Data
FTM3_CH4/TDMB_RXD/
TDMB_TXD
M5
P4
UC3_TXD7/IRQ10/GPIO1_30/ Transmit Data
FTM3_CH6/TDMB_RXD_EXC/
TDMB_TXD
O
Baud rate generator
BRGO1/IIC3_SDA/GPIO4_11/ Baud Rate Generator 1
EVT6_B/USB2_PWRFAULT/
FTM8_CH1/CLK12_CLK8
M4
K3
L3
O
O
O
DVDD
DVDD
DVDD
1
1
1
BRGO2/IIC2_SCL/GPIO4_02/ Baud Rate Generator 2
SDHC_CD_B/FTM3_QD_PHA/
CLK9/QE_SI1_STROBE0
BRGO3/IIC2_SDA/GPIO4_03/ Baud Rate Generator 3
SDHC_WP/FTM3_QD_PHB/
CLK10/QE_SI1_STROBE1
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
78
NXP Semiconductors
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
BRGO4/IIC3_SCL/GPIO4_10/ Baud Rate Generator 4
EVT5_B/USB2_DRVVBUS/
FTM8_CH0/CLK11
L4
O
O
DVDD
1
Time Division Multiplexing
TDMA_RQ/IIC4_SCL/
GPIO4_12/EVT7_B/
USB3_DRVVBUS/
FTM3_FAULT/
RQ
M3
DVDD
1
UC1_CDB_RXER
TDMA_RSYNC/IRQ05/
GPIO1_25/FTM3_CH1/
UC1_CTSB_RXDV
RSYNC
RXD
J5
J4
K5
L5
J4
K5
N3
I
I
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
1
1
1
1
1
1
1
TDMA_RXD/IRQ04/
GPIO1_24/FTM3_CH0/
UC1_RXD7/TDMA_TXD
TDMA_RXD_EXC/IRQ06/
GPIO1_26/FTM3_CH2/
TDMA_TXD/UC1_TXD7
Recieve Data
TSYNC
I
TDMA_TSYNC/IRQ07/
GPIO1_27/FTM3_CH3/
UC1_RTSB_TXEN
I
TDMA_TXD/IRQ04/GPIO1_24/ Transmit Data
FTM3_CH0/TDMA_RXD/
UC1_RXD7
O
O
O
TDMA_TXD/IRQ06/GPIO1_26/ Transmit Data
FTM3_CH2/TDMA_RXD_EXC/
UC1_TXD7
TDMB_RQ/IIC4_SDA/
GPIO4_13/EVT8_B/
USB3_PWRFAULT/
FTM3_EXTCLK/
RQ
UC3_CDB_RXER
TDMB_RSYNC/IRQ09/
GPIO1_29/FTM3_CH5/
UC3_CTSB_RXDV
RSYNC
RXD
N5
M5
P4
J3
I
I
DVDD
DVDD
DVDD
DVDD
DVDD
1
1
1
1
1
TDMB_RXD/IRQ08/
GPIO1_28/FTM3_CH4/
UC3_RXD7/TDMB_TXD
TDMB_RXD_EXC/IRQ10/
GPIO1_30/FTM3_CH6/
TDMB_TXD/UC3_TXD7
Recieve Data
TSYNC
I
TDMB_TSYNC/IRQ03/
GPIO1_23/FTM3_CH7/
UC3_RTSB_TXEN
I
TDMB_TXD/IRQ08/GPIO1_28/ Transmit Data
FTM3_CH4/TDMB_RXD/
M5
O
UC3_RXD7
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
79
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
TDMB_TXD/IRQ10/GPIO1_30/ Transmit Data
FTM3_CH6/TDMB_RXD_EXC/
UC3_TXD7
P4
O
DVDD
1
TSEC_1588
TSEC_1588_ALARM_OUT1/ Alarm Out
EC2_TXD2/GPIO3_16/
FTM2_CH7
AE3
AD3
AC1
AE4
AE1
AF3
AF1
AE2
O
O
I
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
1
1
1
1
1
1
1
1
TSEC_1588_ALARM_OUT2/ Alarm Out
EC2_TXD3/GPIO3_15/
FTM2_CH5
TSEC_1588_CLK_IN/
EC2_RX_CLK/GPIO3_26/
FTM2_QD_PHA
Clock In
TSEC_1588_CLK_OUT/
EC2_TXD1/GPIO3_17/
FTM2_CH3
Clock Out
Pulse Out
Pulse Out
Trigger In
Trigger In
O
O
O
I
TSEC_1588_PULSE_OUT1/
EC2_RXD1/GPIO3_24/
FTM2_CH1
TSEC_1588_PULSE_OUT2/
EC2_TXD0/GPIO3_18/
FTM2_CH2
TSEC_1588_TRIG_IN1/
EC2_RX_DV/GPIO3_27/
FTM2_QD_PHB
TSEC_1588_TRIG_IN2/
EC2_RXD0/GPIO3_25/
FTM2_CH0
I
QSPI
QSPI_A_CS0/IFC_A16
QSPI_A_CS1/IFC_A17
Chip Select
Chip Select
Data
D8
C8
O
O
OVDD
OVDD
OVDD
1, 5
1, 5
---
QSPI_A_DATA0/IFC_A22/
D11
IO
IFC_WP1_B
QSPI_A_DATA1/IFC_A23/
IFC_WP2_B
Data
Data
Data
C12
D13
C13
IO
IO
IO
OVDD
OVDD
OVDD
---
---
---
QSPI_A_DATA2/IFC_A24/
IFC_WP3_B
QSPI_A_DATA3/IFC_A25/
GPIO2_25/FTM5_CH0/
IFC_CS4_B/IFC_RB2_B
QSPI_A_SCK/IFC_A18
QSPI_B_CS0/IFC_A19
QSPI_B_CS1/IFC_A20
Serial Clock
Chip Select
Chip Select
Data
C9
O
O
OVDD
OVDD
OVDD
OVDD
1, 5
1, 5
1, 5
---
D10
C10
B18
O
QSPI_B_DATA0/IFC_PAR0/
IO
GPIO2_13/FTM6_CH0
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
80
NXP Semiconductors
Pin assignments
Notes
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
QSPI_B_DATA1/IFC_PAR1/
GPIO2_14/FTM6_CH1
Data
Data
D17
IO
IO
OVDD
---
---
QSPI_B_DATA2/
E17
OVDD
IFC_PERR_B/GPIO2_15/
FTM6_EXTCLK
QSPI_B_DATA3/IFC_CS3_B/ Data
GPIO2_12/FTM7_EXTCLK
C20
C20
C11
IO
IO
O
OVDD
OVDD
OVDD
---
QSPI_B_DATA3/IFC_CS3_B/ Data
GPIO2_12/FTM7_EXTCLK
---
QSPI_B_SCK/IFC_A21/
Serial Clock
1, 4
cfg_dram_type
Power and Ground Signals
GND001
GND002
GND003
GND004
GND005
GND006
GND007
GND008
GND009
GND010
GND011
GND012
GND013
GND014
GND015
GND016
GND017
GND018
GND019
GND020
GND021
GND022
GND023
GND024
GND025
GND026
GND027
GND028
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A2
A5
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
A21
B3
B4
B7
B10
B13
B16
B19
B21
B24
B26
C1
C2
C5
C21
C27
D3
D4
D7
D9
D12
D15
D18
D21
D24
E1
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
81
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
GND029
GND030
GND031
GND032
GND033
GND034
GND035
GND036
GND037
GND038
GND039
GND040
GND041
GND042
GND043
GND044
GND045
GND046
GND047
GND048
GND049
GND050
GND051
GND052
GND053
GND054
GND055
GND056
GND057
GND058
GND059
GND060
GND061
GND062
GND063
GND064
GND065
GND066
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E2
E5
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
E21
E26
F3
F4
F7
F14
F16
F18
F24
G1
G2
G9
G10
G11
G21
G26
H3
H4
H5
H14
H15
H16
H17
H18
H21
H24
J6
J7
J8
J9
J10
J11
J12
J21
J23
J26
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
82
NXP Semiconductors
Pin assignments
Notes
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
GND067
GND068
GND069
GND070
GND071
GND072
GND073
GND074
GND075
GND076
GND077
GND078
GND079
GND080
GND081
GND082
GND083
GND084
GND085
GND086
GND087
GND088
GND089
GND090
GND091
GND092
GND093
GND094
GND095
GND096
GND097
GND098
GND099
GND100
GND101
GND102
GND103
GND104
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K2
K4
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
K6
K13
K15
K17
K19
K21
L6
L10
L12
L14
L16
L18
L20
L23
L26
M6
M9
M11
M13
M15
M17
M19
M21
M23
N2
N4
N6
N8
N10
N12
N14
N16
N18
N20
N23
N26
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
83
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130
GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P6
P9
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
P11
P13
P15
P17
P19
P23
R4
R5
R8
R10
R12
R14
R16
R18
R20
R23
R26
T2
T4
T6
T9
T11
T13
T15
T17
T19
T21
T23
T26
U6
U8
U10
U12
U14
U16
U18
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
84
NXP Semiconductors
Pin assignments
Notes
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160
GND161
GND162
GND163
GND164
GND165
GND166
GND167
GND168
GND169
GND170
GND171
GND172
GND173
GND174
GND175
GND176
GND177
GND178
GND179
GND180
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U20
U23
V2
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
V4
V6
V9
V11
V13
V15
V21
V23
V26
W12
W22
Y2
Y13
Y14
Y21
Y23
Y26
AA4
AA14
AA21
AA24
AB2
AB12
AB26
AC21
AC24
AD2
AD4
AD26
AE21
AE24
AF4
AF21
AF26
AG1
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
85
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
GND181
GND
GND
GND
GND
AG24
AG26
AH2
AH21
V17
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
GND182
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
GND183
---
GND184
---
SD_GND01
SD_GND02
SD_GND03
SD_GND04
SD_GND05
SD_GND06
SD_GND07
SD_GND08
SD_GND09
SD_GND10
SD_GND11
SD_GND12
SD_GND13
SD_GND14
SD_GND15
SD_GND16
SD_GND17
SD_GND18
SD_GND19
SD_GND20
SD_GND21
SD_GND22
SD_GND23
SD_GND24
SD_GND25
SD_GND26
SD_GND27
SD_GND28
SD_GND29
SD_GND30
SD_GND31
SD_GND32
SD_GND33
SD_GND34
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
V19
W18
W20
Y6
Y7
Y8
Y9
Y10
Y15
Y16
AA5
AA7
AA9
AA12
AA17
AA18
AA19
AB7
AB9
AB14
AB17
AB20
AC5
AC6
AC8
AC10
AC11
AC15
AC16
AC18
AC19
AD5
AD7
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
86
NXP Semiconductors
Pin assignments
Notes
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
SD_GND35
SD_GND36
SD_GND37
SD_GND38
SD_GND39
SD_GND40
SD_GND41
SD_GND42
SD_GND43
SD_GND44
SD_GND45
SD_GND46
SD_GND47
SD_GND48
SD_GND49
SD_GND50
SD_GND51
SD_GND52
SD_GND53
SD_GND54
SD_GND55
SD_GND56
SD_GND57
SD_GND58
SD_GND59
SD_GND60
SD_GND61
SD_GND62
SD_GND63
SD_GND64
SD_GND65
SD_GND66
SD_GND67
SD_GND68
SD_GND69
SD_GND70
SD_GND71
SENSEGND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
Serdes core logic GND
GND Sense pin
AD9
AD12
AD14
AD17
AD20
AE5
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
AE7
AE9
AE12
AE14
AE17
AE20
AF6
AF7
AF8
AF9
AF10
AF11
AF15
AF16
AF17
AF18
AF19
AG5
AG7
AG9
AG12
AG14
AG17
AG20
AH5
AH7
AH9
AH12
AH14
AH17
AH20
W5
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
87
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
OVDD1
OVDD2
OVDD3
OVDD4
OVDD5
OVDD6
DVDD1
General I/O supply
J14
J15
J16
J17
J18
R7
---
OVDD
---
General I/O supply
General I/O supply
General I/O supply
General I/O supply
General I/O supply
---
---
---
---
---
---
OVDD
OVDD
OVDD
OVDD
OVDD
DVDD
---
---
---
---
---
---
UART/I2C/QE supply -
switchable
N7
DVDD2
UART/I2C/QE supply -
switchable
P7
---
DVDD
---
EVDD
eSDHC supply - switchable
R6
T7
---
---
EVDD
LVDD
---
---
LVDD1
Ethernet controller 1 & 2
supply
LVDD2
LVDD3
TVDD
Ethernet controller 1 & 2
supply
U7
V7
---
---
---
LVDD
LVDD
TVDD
---
---
---
Ethernet controller 1 & 2
supply
1.2V/LVDD supply for MDIO
interface for 10G Fman (EC2)
W6
G1VDD01
G1VDD02
G1VDD03
G1VDD04
G1VDD05
G1VDD06
G1VDD07
G1VDD08
G1VDD09
G1VDD10
G1VDD11
G1VDD12
G1VDD13
G1VDD14
G1VDD15
G1VDD16
G1VDD17
G1VDD18
G1VDD19
G1VDD20
G1VDD21
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
DDR supply
B27
D27
F27
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
G1VDD
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
H27
K27
L22
M22
M27
N22
P22
P27
R22
T22
U22
U27
V22
W27
AA27
AC27
AE27
AG27
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
88
NXP Semiconductors
Pin assignments
Notes
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
G1VDD22
S1VDD1
S1VDD2
S1VDD3
X1VDD1
X1VDD2
X1VDD3
FA_VL
DDR supply
AH27
Y17
---
G1VDD
---
---
---
---
---
---
---
15
15
31
SerDes1 core logic supply
SerDes1 core logic supply
SerDes1 core logic supply
SerDes1 transceiver supply
SerDes1 transceiver supply
SerDes1 transceiver supply
Reserved
---
---
---
---
---
---
---
---
---
S1VDD
Y18
S1VDD
Y19
S1VDD
AC14
AC17
AC20
U5
X1VDD
X1VDD
X1VDD
FA_VL
PROG_MTR
Reserved
F13
PROG_MTR
TA_PROG_SFP
TA_PROG_SFP
SFP Fuse Programming
Override supply
G13
TH_VDD
VDD01
VDD02
VDD03
VDD04
VDD05
VDD06
VDD07
VDD08
VDD09
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
Thermal Monitor Unit supply
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
G8
K18
K20
L15
L17
L19
M10
M12
M14
M16
M18
N9
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
TH_VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
32
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
N11
N13
N15
N17
N19
P10
P12
P14
P16
P18
R9
R11
R13
R15
R17
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
89
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
TA_BB_VDD
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
Supply for cores and platform
R19
T10
T12
T14
T16
T18
U9
---
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
U11
U13
U15
U17
U19
V10
V12
V14
V16
G12
Battery Backed Security
Monitor Supply
TA_BB_VDD
AVDD_CGA1
AVDD_CGA2
AVDD_CGA1
AVDD_CGA2
CPU Cluster Group A PLL1
supply.
H9
---
---
30
30
CPU Cluster Group A PLL2
supply.
H10
AVDD_PLAT
AVDD_D1
Platform PLL supply.
DDR1 PLL supply.
SerDes1 PLL 1 supply.
SerDes1 PLL 2 supply.
Vdd Sense pin
H11
R21
AA11
AA16
V5
---
---
---
---
---
---
---
---
AVDD_PLAT
AVDD_D1
30
30
30
30
---
---
---
---
AVDD_SD1_PLL1
AVDD_SD1_PLL2
SENSEVDD
AVDD_SD1_PLL1
AVDD_SD1_PLL2
SENSEVDD
USB_HVDD
USB_HVDD1
USB_HVDD2
USB_SDVDD1
3.3V High Supply
K8
3.3V High Supply
L8
USB_HVDD
1.0 V Analog and digital HS
supply
M7
USB_SDVDD
USB_SDVDD2
USB_SVDD1
USB_SVDD2
1.0 V Analog and digital HS
supply
M8
K7
L7
---
---
---
USB_SDVDD
USB_SVDD
USB_SVDD
---
---
---
1.0 V Analog and digital SS
supply
1.0 V Analog and digital SS
supply
No Connection Pins
NC_A22
NC_A26
No Connection
No Connection
A22
A26
---
---
---
---
---
---
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
90
NXP Semiconductors
Pin assignments
Notes
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
NC_AA10
NC_AA15
NC_AA22
NC_AA23
NC_AA25
NC_AA26
NC_AA6
No Connection
AA10
AA15
AA22
AA23
AA25
AA26
AA6
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
NC_AB10
NC_AB11
NC_AB15
NC_AB16
NC_AB21
NC_AB22
NC_AB23
NC_AB24
NC_AB25
NC_AB5
AB10
AB11
AB15
AB16
AB21
AB22
AB23
AB24
AB25
AB5
NC_AB6
AB6
NC_AC12
NC_AC13
NC_AC22
NC_AC23
NC_AC25
NC_AC26
NC_AC7
AC12
AC13
AC22
AC23
AC25
AC26
AC7
NC_AC9
AC9
NC_AD11
NC_AD13
NC_AD15
NC_AD18
NC_AD21
NC_AD22
NC_AD23
NC_AD24
NC_AD25
NC_AD8
AD11
AD13
AD15
AD18
AD21
AD22
AD23
AD24
AD25
AD8
NC_AE11
NC_AE13
AE11
AE13
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
91
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
NC_AE15
NC_AE18
NC_AE22
NC_AE23
NC_AE25
NC_AE26
NC_AE8
No Connection
AE15
AE18
AE22
AE23
AE25
AE26
AE8
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
NC_AF14
NC_AF22
NC_AF23
NC_AF24
NC_AF25
NC_AF5
AF14
AF22
AF23
AF24
AF25
AF5
NC_AG11
NC_AG13
NC_AG15
NC_AG18
NC_AG21
NC_AG22
NC_AG23
NC_AG25
NC_AG8
NC_AH11
NC_AH13
NC_AH15
NC_AH18
NC_AH22
NC_AH23
NC_AH24
NC_AH25
NC_AH26
NC_AH8
NC_B22
AG11
AG13
AG15
AG18
AG21
AG22
AG23
AG25
AG8
AH11
AH13
AH15
AH18
AH22
AH23
AH24
AH25
AH26
AH8
B22
NC_B25
B25
NC_G19
G19
NC_G20
G20
NC_K10
K10
NC_K11
K11
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
92
NXP Semiconductors
Pin assignments
Notes
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
Power supply
type
number
NC_K12
NC_K14
NC_K16
NC_K22
NC_K9
No Connection
K12
K14
K16
K22
K9
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
NC_L11
NC_L13
NC_L21
NC_L9
L11
L13
L21
L9
NC_M20
NC_N21
NC_P20
NC_P5
M20
N21
P20
P5
NC_P8
P8
NC_T20
NC_T8
T20
T8
NC_U21
NC_U24
NC_U25
NC_U26
NC_V18
NC_V20
NC_V24
NC_V25
NC_V8
U21
U24
U25
U26
V18
V20
V24
V25
V8
NC_W10
NC_W11
NC_W13
NC_W14
NC_W15
NC_W16
NC_W17
NC_W19
NC_W21
NC_W23
NC_W24
NC_W25
NC_W26
W10
W11
W13
W14
W15
W16
W17
W19
W21
W23
W24
W25
W26
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
93
Pin assignments
Table 2. Pinout list by bus (continued)
Signal
Signal description
Package
pin
Pin
type
Power supply
Notes
number
NC_W7
NC_W8
NC_W9
NC_Y12
NC_Y22
NC_Y24
NC_Y25
NC_Y5
No Connection
W7
W8
W9
Y12
Y22
Y24
Y25
Y5
---
---
---
---
---
---
---
---
---
---
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
---
---
---
---
---
---
---
---
---
---
---
---
---
---
1. Functionally, this pin is an output or an input, but structurally it is an I/O because it
either sample configuration input during reset, is a muxed pin, or has other manufacturing
test functions. This pin will therefore be described as an I/O for boundary scan.
2. This output is actively driven during reset rather than being tri-stated during reset.
3. MDIC[0] is grounded through a 162Ω precision 1% resistor and MDIC[1] is connected
to GVDD through a 162Ω precision 1% resistor. For either full or half driver strength
calibration of DDR IOs, use the same MDIC resistor value of 162Ω. The memory
controller register setting can be used to determine automatic calibration is done to full or
half drive strength. These pins are used for automatic calibration of the DDR3L/DDR4
IOs. The MDIC[0:1] pins must be connected to 162Ω precision 1% resistors.
4. This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that
is enabled only when the processor is in its reset state. This pull-up is designed such that
it can be overpowered by an external 4.7 kΩ resistor. However, if the signal is intended to
be high after reset, and if there is any device on the net that might pull down the value of
the net at reset, a pull-up or active driver is needed.
5. Pin must NOT be pulled down during power-on reset. This pin may be pulled up,
driven high, or if there are any externally connected devices, left in tristate. If this pin is
connected to a device that pulls down during reset, an external pull-up is required to drive
this pin to a safe state during reset.
6. Recommend that a weak pull-up resistor (2-10 kΩ) be placed on this pin to the
respective power supply.
7. This pin is an open-drain signal.
8. Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective
power supply.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
94
NXP Semiconductors
Pin assignments
9. This pin has a weak (~20 kΩ) internal pull-up P-FET that is always enabled.
10. These are test signals for factory use only and must be pulled up (100Ω to 1-kΩ) to
the respective power supply for normal operation.
11. This pin requires a 200Ω pull-up to respective power-supply.
12. Do not connect. These pins should be left floating.
14. This pin requires an external 1-kΩ pull-down resistor to prevent PHY from seeing a
valid Transmit Enable before it is actively driven.
15. These pins must be pulled to ground (GND).
16. This pin requires a 698Ω pull-up to respective power-supply.
17. These pins should be tied to ground if the diode is not utilized for temperature
monitoring.
18. This pin should be connected to ground through 2-10kΩ resistor when not used.
19. This pin should be connected to ground through 2-10kΩ resistor when SYSCLK input
is used as system clock.
21. This pin has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the
processor is in its reset state. This pin should have an optional pull down resistor on
board. This is required to support DIFF_SYSCLK/DIFF_SYSCLK_B.
23. This pin must be pulled to OVDD through a 100-ohm to 1k-ohm resistor for a four
core LS1043A device and tied to ground for a two core LS1023A device.
25. The alternate signal in DDR4 configuration is mentioned in corresponding Reference
Manual.
27. Attach 200 Ohm +/-1% 100-ppm/C precision resistor-to-ground. Voltage range
0-250mV.
28. The permissible voltage range is 0 V - 5.25 V.
29. The permissible voltage range for input signal is 0 - 1.8 V.
30. It is measured at the input of the supply filter and not at the SoC pin.
31. Connect to ground when fuses are read-only.
32. TH_VDD must be tied to OVDD.
33. Recommend that a weak pull-down resistor (2-10 kΩ) be placed on this pin to GND.
34. SD_GND must be directly connected to GND.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
95
Electrical characteristics
35. This pin is used for debug purposes. It is advised that boards are built with the ability
to pull up and pull down this pin.
36. This pin must be pulled down to ground with a resistor of value 4.7kohm.
Warning
See "Connection Recommendations" for additional details on
properly connecting these pins for specific applications.
3 Electrical characteristics
This section describes the DC and AC electrical specifications for the chip. The chip is
currently targeted to these specifications, some of which are independent of the I/O cell
but are included for a more complete reference. These are not purely I/O buffer design
specifications.
3.1 Overall DC electrical characteristics
This section describes the ratings, conditions, and other characteristics.
3.1.1 Absolute maximum ratings
This table provides the absolute maximum ratings.
Table 3. Absolute maximum ratings1
Characteristic
Core and platform supply voltage
Symbol
Max Value
-0.3 to 1.08
Unit
Notes
VDD
V
V
4
9
PLL supply voltage (core PLL, platform, DDR)
AVDD_CGA1,
AVDD_CGA2,
AVDD_D1,
-0.3 to 1.98
AVDD_PLAT
PLL supply voltage (SerDes, filtered from X1VDD
)
AVDD_SD1_PLL1
AVDD_SD1_PLL2
TA_PROG_SFP
TH_VDD
-0.3 to 1.48
V
—
SFP Fuse Programming
-0.3 to 1.98
-0.3 to 1.98
-0.3 to 1.98
V
V
V
—
—
—
Thermal Unit Monitor supply
IFC, SPI, GIC (IRQ 0/1/2), Temper_Detect, System
control and power management, SYSCLK,
DDR_CLK, DIFF_SYSCLK, GPIO2, GPIO1,
eSDHC[4-7]/VS/DAT123_DIR/DAT0_DIR/CMD_DIR/
SYNC), Debug, SYSCLK, JTAG, RTC, FTM5/6/7,
POR signals
OVDD
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
96
NXP Semiconductors
Electrical characteristics
Table 3. Absolute maximum ratings1 (continued)
Characteristic
Symbol
Max Value
-0.3 to 3.63
Unit
Notes
DUART1/2, I2C, DMA, QE, LPUART1,
LPUART2_SOUT/SIN, LPUART4, GPIO1, GPIO4,
GIC (IRQ 3/4/5/6/7/8/9/10), FTM 3/8, USB Control
(DRVVBUS, PWRFAULT), FTM4_CH0/1/2/3/4/5
DVDD
EVDD
G1VDD
V
V
-
-0.3 to 1.98
eSDHC[0-3]/CLK/CMD, GPIO2,
LPUART2_CTS_B,LPUART2_RTS_B, LPUART3,
LPUART5, LPUART6, FTM4_CH6/7,
-0.3 to 3.63
-0.3 to 1.98
—
FTM4_EXTCLK/FAULT/QD_PHA/QD_PHB,
DDR3L DRAM I/O voltage
DDR4 DRAM I/O voltage
-0.3 to 1.42
-0.3 to 1.26
-0.3 to 1.08
V
V
—
—
Main power supply for internal circuitry of SerDes and S1VDD
pad power supply for SerDes receivers
Pad power supply for SerDes transmitter
X1VDD
LVDD
-0.3 to 1.48
-0.3 to 2.75
-0.3 to 1.98
V
V
—
—
Ethernet Interface 1/2, Ethernet management
interface 1 (EMI1), TSEC_1588, GPIO1, GPIO3,
FTM1/2, GIC (IRQ11)
Ethernet management interface 2 (EMI2), GPIO4
TVDD
-0.3 to 2.75
-0.3 to 1.98
-0.3 to 1.32
-0.3 to 3.63
-0.3 to 1.08
-0.3 to 1.08
-0.3 to 1.08
-55 to 150
V
—
USB PHY Transceiver supply voltage
USB_HVDD
USB_SDVDD
USB_SVDD
TA_BB_VDD
TSTG
V
6
V
7
V
8
Battery Backed Security Monitor supply
Storage temperature range
Notes:
V
—
--
°C
See next table.
This table provides the absolute maximum ratings for input signal voltage levels.
Table 4. Absolute maximum ratings for input signal voltage levels1
Interface Input signals
Symbol
Max DC V_input range
(MAX_DC_IN)
Max undershoot and
overshoot voltage range
(MAX_OV_RNG)
Unit Notes
DDR4 and DDR3L DRAM signals
DDR3L DRAM reference
MVIN
GND to (G1VDD x 1.05)
-0.3 to (G1VDD x 1.1)
-0.3 to (G1VDD/2 x 1.1)
V
2, 3, 11
2, 3
D1_MVR GND to (G1VDD/2 x 1.05)
V
EF
Ethernet Interface 1/2, Ethernet
management interface 1 (EMI1),
TSEC_1588, GPIO1, GPIO3,
FTM1/2, GIC (IRQ11)
LVIN
GND to (LVDD x 1.1)
-0.3 to (LVDD x 1.15)
V
2, 3
IFC, SPI, GIC (IRQ 0/1/2),
OVIN
GND to (OVDD x 1.1)
-0.3 to (OVDD x 1.15)
V
2, 3
Temper_Detect, System control and
power management, SYSCLK,
DDR_CLK, DIFF_SYSCLK, GPIO2,
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
97
Electrical characteristics
Table 4. Absolute maximum ratings for input signal voltage levels1 (continued)
Interface Input signals
Symbol
Max DC V_input range
(MAX_DC_IN)
Max undershoot and
overshoot voltage range
(MAX_OV_RNG)
Unit Notes
GPIO1, eSDHC[4-7]/VS/
DAT123_DIR/DAT0_DIR/CMD_DIR/
SYNC), Debug, SYSCLK, JTAG,
RTC, FTM5/6/7, POR signals
eSDHC[0-3]/CLK/CMD, GPIO2,
LPUART2_CTS_B,LPUART2_RTS_
B, LPUART3, LPUART5, LPUART6,
FTM4_CH6/7, FTM4_EXTCLK/
FAULT/QD_PHA/QD_PHB
EVIN
GND to (EVDD x 1.1)
GND to (DVDD x 1.1)
-0.3 to (EVDD x 1.15)
-0.3 to (DVDD x 1.15)
V
2, 3
2, 3
DUART1/2, I2C, DMA, QE,
DVIN
V
LPUART1, LPUART2_SOUT/SIN,
LPUART4, GPIO1, GPIO4, GIC
(IRQ 3/4/5/6/7/8/9/10), FTM 3/8,
USB Control (DRVVBUS,
PWRFAULT), FTM4_CH0/1/2/3/4/5
Main power supply for internal
circuitry of SerDes and pad power
supply for SerDes receivers
S1VIN
GND to (S1VDD x 1.05)
-0.3 to (S1VDD x 1.1)
V
2, 3
USB PHY Transceiver signals
USB_H GND to (USB_HVDD x 1.05)
VIN
-0.3 to (USB_HVDD x 1.15)
-0.3 to (USB_SVDD x 1.15)
-0.3 to (USB_SDVDD x 1.15)
-0.3 to (TVDDDD x 1.1)
V
V
V
V
2, 3, 6
2, 3, 8
2, 3, 7
2, 3
USB_SV GND to (USB_SVDD x 1.1)
IN
USB_S GND to (USB_SDVDD x 1.1)
DVIN
Ethernet management interface 2
(EMI2), GPIO4
TVDDIN GND to (TVDDDD x 1.05)
Notes:
1. Functional operating conditions are given in Recommended operating conditions. Absolute maximum ratings are stress
ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.
2. Caution: The input voltage level of the signals must not exceed corresponding Max DC V_input range (MAX_DC_IN). For
example DDR4 and DDR3L DRAM signals (MVIN) must not exceed 5% of G1VDD. Similarly, DDR3L DRAM reference
(D1_MVREF) must not exceed 5% of (G1VDD/2).
3. Caution: In case of overshoot/undershoot, the voltage may exceed corresponding MAX_DC_IN level, but it must not
exceed corresponding MAX_OV_RNG for more than 10% of the Unit interval of the functional frequency. See the Overshoot/
Undershoot voltage figure in Recommended operating conditions
4. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin.
6. Transceiver supply for USBPHY
7. Analog and Digital HS supply for USBPHY.
8. Analog and Digital SS supply for USBPHY.
9. AVDD_PLAT, AVDD_CGA1, AVDD_CGA2 and AVDD_D1 are measured at the input to the filter and not at the pin of the
device. See the application note titled LS1043A QorIQ Integrated Processor Design Checklist (document AN5012).
10. Exposing device to Absolute Maximum Ratings conditions for long periods of time may affect reliability or cause
permanent damage.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
98
NXP Semiconductors
Electrical characteristics
Table 4. Absolute maximum ratings for input signal voltage levels1
Interface Input signals
Symbol
Max DC V_input range
(MAX_DC_IN)
Max undershoot and
overshoot voltage range
(MAX_OV_RNG)
Unit Notes
11. Typical DDR interface uses ODT enabled mode. For tests purposes with ODT off mode, simulation should be done first
so as to make sure that the overshoot signal level at the input pin does not exceed GVDD by more than 10%. The Overshoot/
Undershoot period should comply with JEDEC standards.
3.1.2 Recommended operating conditions
This table provides the recommended operating conditions for this chip.
NOTE
The values shown are the recommended operating conditions
and proper device operation outside these conditions is not
guaranteed.
Table 5. Recommended operating conditions
Characteristic
Symbol
Recommended
Value
Unit
Notes
Core and platform supply voltage
VDD
0.9 V 30 mV
1.0 V 30 mV
V
3, 4, 5, 10
Battery backed security monitor supply
TA_BB_VDD 0.9 V 30 mV
1.0 V 30 mV
V
V
10
—
PLL supply voltage (core PLL, platform, DDR)
AVDD_CGA1, 1.8 V 90 mV
AVDD_CGA2,
AVDD_D1,
AVDD_PLAT
PLL supply voltage (SerDes, filtered from X1VDD
)
AVDD_SD1_P 1.35 V 67 mV
LL1
V
—
AVDD_SD1_P
LL2
SFP Fuse Programming
TA_PROG_S 1.8 V 90 mV
FP
V
2
Thermal monitor unit supply
TH_VDD
1.8 V 90 mV
1.8 V 90 mV
V
V
IFC, SPI, GIC (IRQ 0/1/2), Temper_Detect, System control and OVDD
power management, SYSCLK, DDR_CLK, DIFF_SYSCLK,
GPIO2, GPIO1, eSDHC[4-7]/VS/DAT123_DIR/DAT0_DIR/
CMD_DIR/SYNC), Debug, SYSCLK, JTAG, RTC, FTM5/6/7,
POR signals
—
DUART1/2, I2C, DMA, QE, LPUART1, LPUART2_SOUT/SIN,
LPUART4, GPIO1, GPIO4, GIC (IRQ 3/4/5/6/7/8/9/10), FTM 3/8,
USB Control (DRVVBUS, PWRFAULT), FTM4_CH0/1/2/3/4/5
DVDD
3.3 V 165 mV
1.8 V 90 mV
V
V
6
eSDHC[0-3]/CLK/CMD, GPIO2,
LPUART2_CTS_B,LPUART2_RTS_B, LPUART3, LPUART5,
EVDD
3.3 V 165 mV
1.8 V 90 mV
—
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
99
Electrical characteristics
Table 5. Recommended operating conditions (continued)
Characteristic
Symbol
Recommended
Value
Unit
Notes
LPUART6, FTM4_CH6/7, FTM4_EXTCLK/FAULT/QD_PHA/
QD_PHB
DDR DRAM I/O voltage
DDR4
G1VDD
1.2V 60 mV
V
—
DDR3L
1.35 V 67 mV
Main power supply for internal circuitry of SerDes and pad
power supply for SerDes receivers
S1VDD
0.9 V + 50 mV / - 30
mV
V
10
1.0 V + 50 mV / - 30
mV
Pad power supply for SerDes transmitters
X1VDD
1.35 V 67 mV
2.5 V 125 mV
1.8 V 90 mV
2.5 V 125 mV
1.8 V 90 mV
1.2V 60 mV
3.3 V 165 mV
V
V
—
1
Ethernet Interface 1/2, Ethernet management interface 1 (EMI1), LVDD
TSEC_1588, GPIO1, GPIO3, FTM1/2, GIC (IRQ11)
Ethernet management interface 2 (EMI2), GPIO4
USB PHY Transceiver supply voltage
TVDD
V
USB_HVDD
USB_SVDD
V
V
6
0.9 V + 50 mV / - 30
mV
8, 10
7, 10
—
1.0 V + 50 mV / - 30
mV
USB_SDVDD 0.9 V + 50 mV / - 30
mV
V
V
1.0 V + 50 mV / - 30
mV
Input voltage
DDR3L and DDR4 DRAM MVIN
signals
GND to G1VDD
DDR3L DRAM reference D1_MVREF
G1VDD/2 1%
GND to LVDD
V
V
—
—
Ethernet Interface 1/2,
Ethernet management
interface 1 (EMI1),
TSEC_1588, GPIO1,
GPIO3, FTM1/2, GIC
(IRQ11)
LVIN
IFC, SPI, GIC (IRQ 0/1/2), OVIN
Temper_Detect, System
control and power
GND to OVDD
V
—
management, SYSCLK,
DDR_CLK,
DIFF_SYSCLK, GPIO2,
GPIO1, eSDHC[4-7]/VS/
DAT123_DIR/DAT0_DIR/
CMD_DIR/SYNC), Debug,
SYSCLK, JTAG, RTC,
FTM5/6/7, POR signals
DUART1/2, I2C, DMA,
QE, LPUART1,
DVIN
GND to DVDD
V
—
LPUART2_SOUT/SIN,
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
100
NXP Semiconductors
Electrical characteristics
Table 5. Recommended operating conditions (continued)
Characteristic
Symbol
Recommended
Value
Unit
Notes
LPUART4, GPIO1,
GPIO4, GIC (IRQ
3/4/5/6/7/8/9/10), FTM
3/8, USB Control
(DRVVBUS,
PWRFAULT),
FTM4_CH0/1/2/3/4/5
eSDHC[0-3]/CLK/CMD,
GPIO2,
EVIN
GND to EVDD
V
—
LPUART2_CTS_B,LPUA
RT2_RTS_B, LPUART3,
LPUART5, LPUART6,
FTM4_CH6/7,
FTM4_EXTCLK/FAULT/
QD_PHA/QD_PHB
Main power supply for
internal circuitry of SerDes
S1VIN
GND to S1VDD
V
—
—
6
Ethernet management
interface 2 (EMI2), GPIO4
TVIN
GND to TVDD
V
PHY Transceiver signals
USB Transceiver supply
for USBPHY
USB_HVIN
USB_SVIN
GND to USB_HVDD
GND to USB_SVDD
V
Analog and Digital SS
supply for USBPHY
V
8
Analog and Digital HS
supply for USBPHY
USB_SDVIN 0.3 to USB_SDVDD
V
7
Operating temperature range
Normal operation
TA,
TJ
TA = 0 (min) to
TJ = 105(max)
TA = -40 (min) to
TJ = 105(max)
TA = 0 (min) to
TJ = 105(max)
°C
—
Extended temperature
TA,
TJ
°C
°C
9
2
Secure boot fuse
programming
TA,
TJ
Notes:
1. RGMII is supported at 2.5 V or 1.8 V only.
2. TA_PROG_SFP must be supplied 1.8 V and the chip must operate in the specified fuse programming temperature range
only during secure boot fuse programming. For all other operating conditions, TA_PROG_SFP must be tied to GND, subject
to the power sequencing constraints shown in Power sequencing.
3. For supply filtering requirements, refer to "LS1043A QorIQ Integrated Processor Design Checklist (AN5012)".
4. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin.
5. Operation at 1.08V is allowable for up to 25 ms at initial power on.
6. Transceiver supply for USBPHY
7. Analog and Digital HS supply for USBPHY
8. Analog and Digital SS supply for USBPHY
9. Only valid in case of 1.0 V operation
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
101
Electrical characteristics
Table 5. Recommended operating conditions
Characteristic
Symbol
Recommended
Value
Unit
Notes
10. For part numbering nomenclature refer to Part numbering nomenclature.
This figure shows the undershoot and overshoot voltages at the interfaces of the chip.
Maximum overshoot
D/E/S1/G1/L/O/T/USB*V
DD
V
IH
GND
V
IL
Minimum undershoot
Overshoot/undershoot period
Notes:
The overshoot/undershoot period should be less than 10% of shortest possible toggling period of the input signal
or per input signal specific protocol requirement. For GPIO input signal overshoot/undershoot period, it should be
less than 10% of the SYSCLK period.
Figure 13. Overshoot/Undershoot voltage for G1VDD/OVDD/S1VDD/DVDD/TVDD/ LVDD/EVDD/
USB*VDD
See Table 5 for actual recommended core voltage. Voltage to the processor interface I/Os
are provided through separate sets of supply pins and must be provided at the voltages
shown in Table 5. The input voltage threshold scales with respect to the associated I/O
supply voltage. DVDD, EVDD, OVDD, and LVDD based receivers are simple CMOS I/O
circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM
interface uses differential receivers referenced by the externally supplied D1_MVREF
signal (nominally set to G1VDD/2) as is appropriate for the SSTL_1.35/SSTL_1.2
electrical signaling standard. The DDR DQS receivers cannot be operated in single-ended
fashion. The complement signal must be properly driven and cannot be grounded.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
102
NXP Semiconductors
Electrical characteristics
3.1.3 Output driver characteristics
This chip provides information on the characteristics of the output driver strengths.
NOTE
These values are preliminary estimates.
Table 6. Output drive capability
Driver type
Output impedance (Ω)
Typical
Supply
Voltage
Not
es
Minimum2
Maximum3
DDR4 signal
DDR3L signal
-
18 (full-strength
mode)
-
G1VDD = 1.2 V
1
27 (half-strength
mode)
-
18 (full-strength
mode)
-
G1VDD = 1.35 V 1
27 (half-strength
mode)
Ethernet Interface 1/2, Ethernet management
interface 1 (EMI1), TSEC_1588, GPIO1, GPIO3,
FTM1/2, GIC (IRQ11)
30
30
50
45
70
60
LVDD = 2.5 V
LVDD = 1.8 V
MDC of Ethernet management interface 2 (EMI 2) 45
65
55
60
40
33
40
45
100
75
90
60
44
57
60
TVDD = 1.2 V
TVDD = 1.8 V
TVDD = 2.5 V
TVDD = 1.2 V
TVDD = 1.8 V
TVDD = 2.5 V
OVDD = 1.8 V
-
-
-
40
40
MDIO of Ethernet management interface 2 (EMI 30
2)
25
25
IFC, SPI, GIC (IRQ 0/1/2), Temper_Detect,
System control and power management,
SYSCLK, DDR_CLK, DIFF_SYSCLK, GPIO2,
GPIO1, eSDHC[4-7]/VS/DAT123_DIR/
DAT0_DIR/CMD_DIR/SYNC), Debug, SYSCLK,
JTAG, RTC, FTM5/6/7, POR signals
30
DUART1/2, I2C, DMA, QE, LPUART1,
LPUART2_SOUT/SIN, LPUART4, GPIO1,
GPIO4, GIC (IRQ 3/4/5/6/7/8/9/10), FTM 3/8,
USB Control (DRVVBUS, PWRFAULT),
FTM4_CH0/1/2/3/4/5
45
40
65
55
90
75
DVDD = 3.3 V
DVDD = 1.8 V
-
-
eSDHC[0-3]/CLK/CMD, GPIO2,
45
40
65
55
90
75
EVDD = 3.3 V
EVDD = 1.8 V
LPUART2_CTS_B,LPUART2_RTS_B,
LPUART3, LPUART5, LPUART6, FTM4_CH6/7,
FTM4_EXTCLK/FAULT/QD_PHA/QD_PHB
1. The drive strength of the DDR4 or DDR3L interface in half-strength mode is at Tj = 105 °C and at G1VDD (min).
2. Estimated number based on best case processed device.
3. Estimated number based on worst case processed device.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
103
Electrical characteristics
3.1.4 General AC timing specifications
This table lists the AC timing specifications for the sections that are not covered under
the specific interface sections.
Table 7. AC Timing specifications
Parameter
Symbol
Min
Max
Unit
ns
Notes
Input signal rise and fall times
tR/tF
-
5
1
1. Rise time refers to the signal transitions from 10% to 90% of supply and fall time refers to the signal transitions from 90%
to 10% of supply.
3.2 Power sequencing
The chip requires that its power rails be applied in a specific sequence in order to ensure
the proper device operation. For power up, these requirements are as follows:
1. AVDD_CGA1, AVDD_CGA2, AVDD_PLAT, AVDD_D1, OVDD, DVDD, LVDD,
EVDD, USB_HVDD, TVDD
Drive TA_PROG_SFP = GND
PORESET_B input must be driven asserted and held during this step.
2. VDD, S1VDD, TA_BB_VDD, USB_SDVDD, USB_SVDD
The 3.3 V (USB_HVDD) in Step 1 and 1.0 V (USB_SDVDD, USB_SVDD) in Step 2
supplies can power up in any sequence, provided all these USB supplies ramp up
within 10 ms with respect to each other.
3. a. When using DDR3L : G1VDD, X1VDD, AVDD_SD1_PLL1, AVDD_SD1_PLL2
ramps up in Step 3.
b. When using DDR4 : G1VDD ramps up in Step 3, whereas X1VDD,
AVDD_SD1_PLL1, AVDD_SD1_PLL2 may ramp up with Step 1 supplies.
AVDD_SD1_PLL1 and AVDD_SD1_PLL2 are derived from X1VDD
Items on the same line have no ordering requirement with respect to one another. Items
on separate lines must be ordered sequentially such that voltage rails on a previous step
must reach 90% of their value before the voltage rails on the current step reach 10% of
their value.
NOTE
If using Trust Architecture Security Monitor battery backed
features, prior to VDD ramping up to the 0.5 V level, ensure
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
104
NXP Semiconductors
Electrical characteristics
that OVDD is ramped to recommended operational voltage and
SYSCLK or DIFF_SYSCLK/DIFF_SYSCLK_B is running.
These clock should have a minimum frequency of 800 Hz and a
maximum frequency no greater than the supported system clock
frequency for the device.
All supplies must be at their stable values within 400 ms.
Negate PORESET_B input when the required assertion/hold time meets as listed in Table
27.
NOTE
• While VDD is ramping up, current may be supplied from
VDD through the LS1043A processor to G1VDD.
• Ramp rate requirements should meet as listed in Table 16.
Warning
Only 300,000 POR cycles are permitted per lifetime of a
device. This value is based on design estimates and is
preliminary.
For secure boot fuse programming, use the following steps:
1. After the negation of PORESET_B signal, drive TA_PROG_SFP = 1.8 V after a
required minimum delay as listed in Table 8.
2. After the fuse programming is complete, it is required to return TA_PROG_SFP =
GND before the system is power cycled (PORESET_B assertion) or powered down
(VDD ramp down) per the required timing specified in Table 8. For additional details,
see the section Security fuse processor.
Warning
No activity other than that required for secure boot fuse
programming is permitted while TA_PROG_SFP is driven
to any voltage above GND, including the reading of the
fuse block. The reading of the fuse block may only occur
while TA_PROG_SFP = GND.
This figure shows the TA_PROG_SFP timing diagram.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
105
Electrical characteristics
Fuse programming
10% TA_PROG_SFP
10% TA_PROG_SFP
TA_PROG_SFP
90% VDD
tTA_PROG_SFP_VDD
V
DD
tTA_PROG_SFP_PROG
tTA_PROG_SFP_DELAY
90% OVDD
90% OVDD
PORESET_B
tTA_PROG_SFP_RST
NOTE: TA_PROG_SFP must be stable at 1.8 V prior to initiating fuse programming.
Figure 14. TA_PROG_SFP timing diagram
This table provides the information on the shut down and start up sequence parameters
for TA_PROG_SFP.
Table 8. TA_PROG_SFP timing 5
Driver type
tTA_PROG_SFP_DELAY
Min
Max
Unit
SYSCLKs
Notes
100
0
—
—
—
—
1
2
3
4
tTA_PROG_SFP_PROG
tTA_PROG_SFP_VDD
tTA_PROG_SFP_RST
Notes:
us
us
us
0
0
1. Delay required from the deassertion of PORESET_B to driving TA_PROG_SFP ramp up. Delay measured from
PORESET_B deassertion at 90% OVDD to 10% TA_PROG_SFP ramp up.
2. Delay required from fuse programming completion to TA_PROG_SFP ramp down start. Fuse programming must complete
while TA_PROG_SFP is stable at 1.8 V. No activity other than that required for secure boot fuse programming is permitted
while TA_PROG_SFP is driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse
block may only occur while TA_PROG_SFP = GND. After fuse programming is complete, it is required to return
TA_PROG_SFP = GND.
3. Delay required from TA_PROG_SFP ramp-down complete to VDD ramp-down start. TA_PROG_SFP must be grounded to
minimum 10% TA_PROG_SFP before VDD reaches 90% VDD
4. Delay required from TA_PROG_SFP ramp-down complete to PORESET_B assertion. TA_PROG_SFP must be grounded
to minimum 10% TA_PROG_SFP before PORESET_B assertion reaches 90% OVDD
.
.
5. Only six secure boot fuse programming events are permitted per lifetime of a device.
3.3 Power down requirements
The shut down cycle must complete such that power supply values are below 0.4 V
before a new start up cycle can be started.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
106
NXP Semiconductors
Electrical characteristics
If performing secure boot fuse programming as per the requirements listed in Power
sequencing, it is required that TA_PROG_SFP = GND before the system is power cycled
(PORESET_B assertion) or shut down (VDD ramp down) per the required timing
specified in Power sequencing.
3.4 Power characteristics
This table shows the power dissipations of the VDD supply for various operating platform
clock frequencies versus the core and DDR clock frequencies. Note that these numbers
are based on design estimates only and are preliminary.
Table 9. LS1043A core power dissipation (VDD = 0.9 V)
Core
freq
(MHz)
Platform
freq (MHz)
DDR
data
rate
VDD (V)
S1VDD Junction
Power
mode
Power (W)
VDD S1VDD
Total Core
and
platform
power
Notes
(V)
temp.
(ºC)
8
(MT/s)
(W)1
2.80
1200
1000
300
1300
0.9
0.9
0.9
65
Typical
Thermal
2.44
3.63
0.36
0.39
0.39
0.36
0.39
0.39
2, 3
105
4.02
4, 7
Maximum 4.29
4.68
5, 6, 7
2, 3
300
1300
0.9
65
Typical
2.34
3.53
2.70
105
Thermal
3.92
4, 7
Maximum 3.95
4.34
5, 6, 7
1. Combined power of VDD and S1VDD with platform at power-on reset default state, DDR controller and all SerDes banks
active. Does not include I/O power.
2. Typical power assumes Dhrystone running with activity factor of 70% (for cores) and executing DMA on the platform with
100% activity factor.
3. Typical power based on nominal, processed device.
4. Thermal power assumes Dhrystone running with activity factor of 70% (for cores) and executing DMA on the platform at
100% activity factor.
5. Maximum power assumes Dhrystone running with activity factor at 100% (for cores) and executing DMA on the platform at
115% activity factor.
6. Maximum and Maximum power is provided for power supply design sizing.
7. Thermal and maximum power are based on worst case processed device.
8. Total S1VDD Power conditions:
a. SerDes Lane 1, XFI@ 10G
b. SerDes Lane 2 - 4, PCIe@ 5G
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
107
Electrical characteristics
Table 10. LS1043A core power dissipation (VDD = 1.0 V)
Core
freq
(MHz)
Platform
freq (MHz)
DDR
data
rate
VDD (V)
S1VDD Junction
Power
mode
Power (W)
VDD S1VDD
Total Core
and
platform
power
Notes
(V)
temp.
(ºC)
8
(MT/s)
(W)1
4.18
7.06
7.80
3.69
5.57
6.16
3.57
5.45
6.04
3.45
5.33
5.87
1600
1400
1200
1000
400
1600
1.0
1.0
1.0
1.0
1.0
65
Typical
Thermal
3.79
6.67
0.39
0.39
0.39
0.36
0.39
0.39
0.36
0.39
0.39
0.36
0.39
0.39
2, 3
105
4, 7
Maximum 7.41
5, 6, 7
2, 3
300
300
300
1600
1600
1600
1.0
1.0
1.0
65
Typical
3.30
5.18
105
Thermal
4, 7
Maximum 5.77
5, 6, 7
2, 3
65
Typical
3.18
5.06
105
Thermal
4, 7
Maximum 5.65
5, 6, 7
2, 3
65
Typical
3.06
4.94
105
Thermal
4, 7
Maximum 5.48
5, 6, 7
1. Combined power of VDD and S1VDD with platform at power-on reset default state, DDR controller and all SerDes banks
active. Does not include I/O power.
2. Typical power assumes Dhrystone running with activity factor of 70% (for cores) and executing DMA on the platform with
100% activity factor.
3. Typical power based on nominal, processed device.
4. Thermal power assumes Dhrystone running with activity factor of 70% (for cores) and executing DMA on the platform at
100% activity factor.
5. Maximum power assumes Dhrystone running with activity factor at 100% (for cores) and executing DMA on the platform at
115% activity factor.
6. Maximum and Maximum power is provided for power supply design sizing.
7. Thermal and maximum power are based on worst case processed device.
8. Total S1VDD Power conditions:
a. SerDes Lane 1, XFI@ 10G
b. SerDes Lane 2 - 4, PCIe@ 5G
Table 11. LS1023A core power dissipation (VDD = 0.9 V)
Core
freq
(MHz)
Platform
freq (MHz)
DDR
data
rate
VDD (V)
S1VDD Junction
Power
mode
Power (W)
S1VDD
Total Core
and
platform
power
Notes
(V)
temp.
(ºC)
8
VDD
(MT/s)
(W)1
2.55
1200
1000
300
1300
0.9
0.9
0.9
65
Typical
Thermal
2.19 0.36
3.18 0.39
2, 3
105
3.57
4, 7
Maximum 3.48 0.39
Typical 2.13 0.36
3.87
5, 6, 7
2, 3
300
1300
0.9
65
2.49
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
108
NXP Semiconductors
Electrical characteristics
Table 11. LS1023A core power dissipation (VDD = 0.9 V) (continued)
Core
freq
(MHz)
Platform
freq (MHz)
DDR
data
rate
VDD (V)
S1VDD Junction
Power
mode
Power (W)
S1VDD
Total Core
and
platform
power
Notes
(V)
temp.
(ºC)
8
VDD
(MT/s)
(W)1
3.51
105
Thermal
3.12 0.39
4, 7
5, 6, 7
Maximum 3.40 0.39
3.79
1. Combined power of VDD and S1VDD with platform at power-on reset default state, DDR controller and all SerDes banks
active. Does not include I/O power.
2. Typical power assumes Dhrystone running with activity factor of 80% (for cores) and executing DMA on the platform with
100% activity factor.
3. Typical power based on nominal, processed device.
4. Thermal power assumes Dhrystone running with activity factor of 80% (for cores) and executing DMA on the platform at
100% activity factor.
5. Maximum power assumes Dhrystone running with activity factor at 100% (for cores) and executing DMA on the platform at
115% activity factor.
6. Maximum power is provided for power supply design sizing.
7. Thermal and maximum power are based on worst case processed device.
8. Total S1VDD Power conditions:
a. SerDes Lane 1, XFI@ 10G
b. SerDes Lane 2 - 4, PCIe@ 5G
Table 12. LS1023A core power dissipation (VDD = 1.0 V)
Core
freq
(MHz)
Platform
freq (MHz)
DDR
data
rate
VDD (V)
S1VDD Junction
Power
mode
Power (W)
S1VDD
Total Core
and
platform
power
Notes
(V)
temp.
(ºC)
8
VDD
(MT/s)
(W)1
3.69
6.08
6.55
3.25
4.81
5.19
3.17
4.74
5.12
3.10
4.66
5.03
1600
1400
1200
1000
400
1600
1.0
1.0
1.0
1.0
1.0
65
Typical
Thermal
3.30 0.39
5.69 0.39
2, 3
105
4, 7
Maximum 6.16 0.39
5, 6, 7
2, 3
300
300
300
1600
1600
1600
1.0
1.0
1.0
65
Typical
2.86 0.39
4.42 0.39
105
Thermal
4, 7
Maximum 4.80 0.39
5, 6, 7
2, 3
65
Typical
2.78 0.39
4.35 0.39
105
Thermal
4, 7
Maximum 4.73 0.39
5, 6, 7
2, 3
65
Typical
2.71 0.39
4.27 0.39
105
Thermal
4, 7
Maximum 4.64 0.39
5, 6, 7
1. Combined power of VDD and S1VDD with platform at power-on reset default state, DDR controller and all SerDes banks
active. Does not include I/O power.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
109
Electrical characteristics
Table 12. LS1023A core power dissipation (VDD = 1.0 V)
Core
freq
(MHz)
Platform
freq (MHz)
DDR
data
rate
VDD (V)
S1VDD Junction
Power
mode
Power (W)
S1VDD
Total Core
and
platform
power
Notes
(V)
temp.
(ºC)
8
VDD
(MT/s)
(W)1
2. Typical power assumes Dhrystone running with activity factor of 80% (for cores) and executing DMA on the platform with
100% activity factor.
3. Typical power based on nominal, processed device.
4. Thermal power assumes Dhrystone running with activity factor of 80% (for cores) and executing DMA on the platform at
100% activity factor.
5. Maximum power assumes Dhrystone running with activity factor at 100% (for cores) and executing DMA on the platform at
115% activity factor.
6. Maximum power is provided for power supply design sizing.
7. Thermal and maximum power are based on worst case processed device.
8. Total S1VDD Power conditions:
a. SerDes Lane 1, XFI@ 10G
b. SerDes Lane 2 - 4, PCIe@ 5G
3.5 Low power mode saving estimation
Refer to this table for low power mode savings.
Table 13. Low power mode savings, 0.9 V, 65C1, 2, 3
Mode
PW15
Core
Core
Units
Comments
Notes
Frequency = Frequency =
1.0 GHz
0.03
1.2 GHz
0.04
Watts
Watts
Saving realized moving from run --> PW15 state,
single core. ARM in STANDBYWFI/WFE
4
SWLPM20 0.16
0.19
Saving realized moving from PW15 --> SWLPM20
state, 4 cores. ARM in STANDBYWFI/WFE
5, 6
Notes:
1. Power for VDD only
2. Typical power assumes Dhrystone running with activity factor of 80%
3. Typical power based on nominal process distribution for this device
4. PW15 power savings with 1 core. Maximum savings would be N times, where N is the number of used cores
5. SWLPM20 has all platform clocks disabled
6. SWLPM20 power saving with all the 4 cores in STANDBYWFI/WFE
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
110
NXP Semiconductors
Electrical characteristics
Table 14. Low power mode savings, 1.0 V, 65C1, 2, 3
Mode
PW15
Core
Core
Core
Core
Units
Comments
Notes
Frequenc Frequenc Frequenc Frequenc
y = 1.0
GHz
y = 1.2
GHz
y = 1.4
GHz
y = 1.6
GHz
0.04
0.05
0.06
0.06
Watts
Watts
Saving realized moving from run --> PW15
state, single core. ARM in
STANDBYWFI/WFE
4
SWLPM2 0.20
0
0.24
0.31
0.36
Saving realized moving from PW15 -->
SWLPM20 state, 4 cores. ARM in
STANDBYWFI/WFE
5, 6
Notes:
1. Power for VDD only
2. Typical power assumes Dhrystone running with activity factor of 80%
3. Typical power based on nominal process distribution for this device
4. PW15 power savings with 1 core. Maximum savings would be N times, where N is the number of used cores
5. SWLPM20 has all platform clocks disabled
6. SWLPM20 power saving with all the 4 cores in STANDBYWFI/WFE
3.6 I/O power dissipation
This table provides the estimated I/O power numbers for each block: DDR, PCI Express,
IFC, Ethernet controller, SGMII, eSDHC, USB, eSPI, DUART, IIC, SATA and GPIO.
Note that these numbers are based on design estimates only.
Table 15. I/O power supply estimated values
Interface
Parameter
Symbol
Typical
Maximum
Unit
mW
Note
1, 2, 6
DDR3L
1600 MT/s data G1VDD (1.35 V)
rate
630
490
1250
DDR4
1600 MT/s data G1VDD (1.2 V)
rate
990
mW
mW
1, 8, 9
1, 4, 7
PCI Express
x1, 2.5 GT/s
x2, 2.5 GT/s
x4, 2.5 GT/s
x1, 5 GT/s
x2, 5 GT/s
x4, 5 GT/s
X1VDD (1.35 V)
80
86
132
237
80
137
242
86
133
239
77
138
244
82
SGMII
x1, 1.25 GBaud X1VDD (1.35 V)
x2, 1.25 GBaud
mW
1, 4, 7
127
177
227
136
186
235
x3, 1.25 GBaud
x4, 1.25 GBaud
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
111
Electrical characteristics
Table 15. I/O power supply estimated values (continued)
Interface
Parameter
x1, 3.125 GBaud
x2, 3.125 GBaud
x1, 5 GBaud
x1, 10 GBaud
3.0 GBaud
Symbol
Typical
Maximum
Unit
Note
80
132
80
81
73
74
60
24
17
24
17
19
19
85
140
85
87
78
79
84
71
42
71
42
39
42
201
153
24
QSGMII
X1VDD (1.35 V)
X1VDD (1.35 V)
X1VDD (1.35 V)
mW
1, 4, 7
XFI
mW
mW
1, 4, 7
1, 4, 7
SATA (per port)
6.0 GBaud
IFC
16-bit, 100 MHz OVDD (1.8 V)
mW
mW
mW
mW
1, 3, 7
1, 3, 7
1, 3, 7
1, 3, 7
EC1
RGMII
RGMII
RGMII
RGMII
LVDD (2.5 V)
LVDD (1.8 V)
LVDD (2.5 V)
LVDD (1.8 V)
EVDD (3.3 V)
EVDD (1.8 V)
EC2
eSDHC
mW
mW
1, 3, 7
1, 3, 7
USB1, USB2, USB3
USB_HVDD (3.3 V) 138
USB_SVDD (1.0 V) 111
USB_SDVDD (1.0
V)
12
SPI
I2C
OVDD (1.8 V)
DVDD (3.3 V)
DVDD (1.8 V)
DVDD (3.3 V)
DVDD (1.8 V)
LVDD (2.5 V)
LVDD (1.8 V)
DVDD (3.3 V)
DVDD (1.8 V)
3.3 V
8
14
18
9
mW
mW
1, 3, 7
1, 3, 7
17
9
DUART
IEEE1588
QE
18
9
23
10
34
21
79
31
8
mW
mW
mW
mW
1, 3, 7
1, 3, 7
14
10
39
19
5
1, 3, 7
GPIO
x8
1, 3, 5, 7
2.5 V
4
7
1.8 V
3
5
System Control
OVDD (1.8 V)
16
30
17
30
mW
mW
1, 3, 7
1, 3, 7
PLL core and system
AVDD_CGA1,
AVDD_CGA2,
AVDD_PLAT (1.8 V)
PLL DDR
AVDD_D1 (1.8 V)
30
40
50
mW
mW
1, 3, 7
1, 3, 7
PLL SerDes
AVDD_SD1_PLL1, 50
AVDD_SD1_PLL2
(1.35 V)
PROG_SFP
TH_VDD
QSPI
PROG_SFP (1.8 V) 173
-
mW
mW
mW
mW
1, 10
TH_VDD (1.8 V)
OVDD (1.8 V)
OVDD (1.8 V)
18
2
-
1
1
1
5
15
JTAG + DFT
10
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
112
NXP Semiconductors
Electrical characteristics
Table 15. I/O power supply estimated values (continued)
Interface
Parameter
Symbol
Typical
Maximum
Unit
Note
1. The typical values are estimates and based on simulations at nominal recommended voltage for the I/O power supply and
assuming at 65° C junction temperature.
2. Typical DDR power numbers are based on 2 Rank DIMM with 40% utilization.
3. Assuming 15 pF total capacitance load per pin.
4. The total power numbers of X1VDD is dependent on customer application use case. This table lists all the SerDes
configurations possible for the device. To get the X1VDD power numbers, the user should add the combined lanes to match
to the total SerDes Lanes used, not simply multiply the power numbers by the number of lanes.
5. GPIOs are supported on OVDD, LVDD, DVDD, TVDD and EVDD power rails.
6. Maximum DDR3L/DDR4 power numbers are based on 2 Ranks DIMM with 100% utilization.
7. The maximum values are dependent on actual use case such as what application, external components used,
environmental conditions such as temperature voltage and frequency. This is not intended to be the maximum guaranteed
power. Expect different results depending on the use case. The maximum values are estimated and they are based on
simulations at 105ºC junction temperature.
8. Typical DDR4 power numbers are based on single Rank DIMM with 40% utilization.
9. Maximum DDR4 power numbers are based on single Rank DIMM with 100% utilization.
10. The max power requirement is during programming. No active power beyond leakage levels should be drawn and the
supply must be grounded when not programming.
3.7 Power-on ramp rate
This section describes the AC electrical specifications for the power-on ramp rate
requirements. Controlling the maximum power-on ramp rate is required to avoid excess
in-rush current.
This table provides the power supply ramp rate specifications.
Table 16. Power supply ramp rate
Parameter
Min
Max
Unit
V/ms
Notes
1, 2
Required ramp rate for all voltage supplies (including OVDD/DVDD/G1VDD
S1VDD/X1VDD/LVDD/EVDD/TVDD all core and platform VDD supplies, Dn_MVREF
TA_PROG_SFP, and all AVDD supplies.)
/
--
25
25
,
Required ramp rate for PROG_SFP
Required ramp rate for USB_HVDD
Notes:
--
--
V/ms
V/ms
1,2
1,2
26.7
1. Ramp rate is specified as a linear ramp from 10% to 90%. If non-linear (for example, exponential), the maximum rate of
change from 200 mV to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.
2. Over full recommended operating temperature range. See Table 5.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
113
Electrical characteristics
3.8 Input clocks
3.8.1 System clock (SYSCLK)
This section describes the system clock DC electrical characteristics and AC timing
specifications.
3.8.1.1 SYSCLK DC electrical characteristics
This table provides the SYSCLK DC characteristics.
Table 17. SYSCLK DC electrical characteristics3
Parameter
Input high voltage
Symbol
Min
Typical
Max
Unit
Notes
VIH
VIL
CIN
1.2
—
—
—
7
—
V
1
1
Input low voltage
Input capacitance
0.6
12
V
—
pF
—
Input current (OVIN= 0 V or OVIN
OVDD)
=
IIN
—
—
50
µA
2
Notes:
1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 5.
2. At recommended operating conditions with OVDD = 1.8 V. See Table 5.
3.8.1.2 SYSCLK AC timing specifications
This table provides the SYSCLK AC timing specifications.
Table 18. SYSCLK AC timing specifications1, 7
Parameter/condition
SYSCLK frequency
Symbol
fSYSCLK
Min
Typ
Max
Unit
MHz
Notes
64.0
10.0
40
—
—
—
—
—
—
—
100.0
15.6
60
2, 5, 6
SYSCLK cycle time
SYSCLK duty cycle
SYSCLK slew rate
tSYSCLK
ns
1, 2
2
tKHK/tSYSCLK
%
—
—
1
4
V/ns
ps
3
SYSCLK peak period jitter
—
150
500
1.8
—
4
SYSCLK jitter phase noise at -56 dBc —
—
kHz
V
AC Input Swing Limits at 1.8 V OVDD ΔVAC
1.08
—
Notes:
1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequencies do not exceed their
respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
114
NXP Semiconductors
Electrical characteristics
Table 18. SYSCLK AC timing specifications1, 7
Parameter/condition
Symbol
Min
Typ
Max
Unit
Notes
3. Slew rate as measured from 0.35 x OVDD to 0.65 x OVDD
.
4. Phase noise is calculated as FFT of TIE jitter.
5. The 64 MHz SYSCLK reference frequency support is specifically for QE requirements. It provides support for profibus for
Industrial markets.
6. The 100 MHz reference frequency is needed if USB is used. The reference clock to USB PHY is selectable between
SYSCLK or DIFF_SYSCLK/DIF_SYSCLK_B. The selected clock must meet the clock specifications as mentioned in USB 3.0
reference clock requirements .
7. At recommended operating conditions with OVDD = 1.8 V. See Table 5.
3.8.2 Spread-spectrum sources
Spread-spectrum clock sources are an increasingly popular way to control
electromagnetic interference emissions (EMI) by spreading the emitted noise to a wider
spectrum and reducing the peak noise magnitude in order to meet industry and
government requirements. These clock sources intentionally add long-term jitter to
diffuse the EMI spectral content.
The jitter specification given in this table considers short-term (cycle-to-cycle) jitter only.
The clock generator's cycle-to-cycle output jitter should meet the chip's input cycle-to-
cycle jitter requirement.
Frequency modulation and spread are separate concerns; the chip is compatible with
spread-spectrum sources if the recommendations listed in this table are observed.
Table 19. Spread-spectrum clock source recommendations3
Parameter
Frequency modulation
Min
Max
Unit
Notes
—
—
60
kHz
%
—
Frequency spread
1.0
1, 2
Notes:
1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and
maximum specifications given in Table 18.
2. Maximum spread-spectrum frequency may not result in exceeding any maximum operating frequency of the device.
3. At recommended operating conditions with OVDD = 1.8 V. See Table 5.
CAUTION
The processor's minimum and maximum SYSCLK and core/
platform/DDR frequencies must not be exceeded, regardless of
the type of clock source. Therefore, systems in which the
processor is operated at its maximum rated core/platform/DDR
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
115
Electrical characteristics
frequency should use only down-spreading to avoid violating
the stated limits.
3.8.3 Real-time clock timing (RTC)
The real-time clock timing (RTC) input is sampled by the platform clock. The output of
the sampling latch is then used as an input to the time base unit of the core; there is no
need for jitter specification. The minimum period of the RTC signal should be greater
than or equal to 16x the period of the platform clock with a 50% duty cycle. There is no
minimum RTC frequency; RTC may be grounded if not needed. .
3.8.4 Gigabit Ethernet reference clock timing
This table provides the Ethernet gigabit reference clock DC electrical characteristics with
LVDD = 1.8 V.
Table 20. ECn_GTX_CLK125 DC electrical characteristics (LVDD = 1.8 V)1
Parameter
Symbol
VIH
Min
Typical
Max
Unit
Notes
Input high voltage
Input low voltage
Input capacitance
1.2
—
—
—
—
—
0.6
6
V
2
VIL
CIN
IIN
—
—
—
V
2
pF
µA
—
3
Input current (VIN = 0 V or VIN = LVDD
)
50
Notes:
1. For recommended operating conditions, refer to table Table 5.
2. The min VIL and max VIH values are based on the respective min and max VIN values found in Table 5.
3. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 5.
This table provides the Ethernet gigabit reference clock DC electrical characteristics with
LVDD = 2.5 V.
Table 21. ECn_GTX_CLK125 DC electrical characteristics (LVDD = 2.5 V)1
Parameter
Symbol
VIH
Min
Typical
Max
Unit
Notes
Input high voltage
Input low voltage
Input capacitance
1.7
—
—
—
—
—
0.7
6
V
2
VIL
CIN
IIN
—
—
—
V
2
pF
µA
—
3
Input current (VIN = 0 V or VIN = LVDD
)
50
Notes:
1. For recommended operating conditions, refer to table Table 5.
2. The min VIL and max VIH values are based on the respective min and max VIN values found in Table 5.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
116
NXP Semiconductors
Electrical characteristics
Table 21. ECn_GTX_CLK125 DC electrical characteristics (LVDD = 2.5 V)1
Parameter
Symbol
Min
Typical
Max
Unit
Notes
3. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 5.
This table provides the Ethernet gigabit reference clock AC timing specifications.
Table 22. ECn_GTX_CLK125 AC timing specifications 1, 4
Parameter/Condition
ECn_GTX_CLK125 frequency
ECn_GTX_CLK125 cycle time
ECn_GTX_CLK125 rise and fall time
LVDD = 1.8 V
Symbol
fG125
Min
Typical
Max
Unit
Notes
125 - 100 ppm 125
8
125 + 100 ppm MHz
ns
—
—
2
tG125
tG125R/tG125F
—
—
ns
0.54
0.75
LVDD = 2.5 V
ECn_GTX_CLK125 duty cycle
1000Base-T for RGMII
ECn_GTX_CLK125 jitter
Notes:
tG125H/tG125
40
—
—
—
60
%
4
4
—
150
ps
1. At recommended operating conditions with LVDD = 1.8V/ 2.5V. See Table 5.
2. Rise and fall times for ECn_GTX_CLK125 are measured from 20% to 80% LVDD
4. ECn_GTX_CLK125 is used to generate the GTX clock for the Ethernet transmitter. See RGMII AC timing specifications for
duty cycle for the 10Base-T and 100Base-T reference clocks.
3.8.5 DDR clock (DDRCLK)
This section provides the DDRCLK DC electrical characteristics and AC timing
specifications.
3.8.5.1 DDRCLK DC electrical characteristics
This table provides the DDRCLK DC electrical characteristics.
Table 23. DDRCLK DC electrical characteristics3
Parameter
Input high voltage
Symbol
Min
Typical
Max
Unit
Notes
VIH
VIL
CIN
IIN
1.2
—
—
—
—
—
7
—
V
1
1
Input low voltage
Input capacitance
0.6
12
V
pF
μA
—
2
Input current (OVIN= 0 V or OVIN
OVDD)
=
—
50
Notes:
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
117
Electrical characteristics
Parameter
Table 23. DDRCLK DC electrical characteristics3
Symbol
Min
Typical
Max
Unit
Notes
1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 5.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Table 5.
3. At recommended operating conditions with OVDD = 1.8 V. see Table 5.
3.8.5.2 DDRCLK AC timing specifications
This table provides the DDRCLK AC timing specifications.
Table 24. DDRCLK AC timing specifications5
Parameter/Condition
DDRCLK frequency
Symbol
fDDRCLK
Min
Typ
Max
Unit
MHz
Notes
1, 2
64.0
10
—
—
—
—
—
—
—
100.0
15.6
60
DDRCLK cycle time
DDRCLK duty cycle
DDRCLK slew rate
tDDRCLK
ns
1, 2
2
tKHK/tDDRCLK
40
%
—
—
1
4
V/ns
ps
3
DDRCLK peak period jitter
—
150
500
1.8
—
4
DDRCLK jitter phase noise at -56 dBc —
AC Input Swing Limits at 1.8 V OVDD ΔVAC
Notes:
—
kHz
V
1.08
—
1. Caution: The relevant clock ratio settings must be chosen such that the resulting DDRCLK frequencies do not exceed
their respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
3. Slew rate as measured from 0.35 x OVDD to 0.65 x OVDD
.
4. Phase noise is calculated as FFT of TIE jitter.
5. At recommended operating conditions with OVDD = 1.8V. See Table 5.
3.8.6 Differential system clock (DIFF_SYSCLK/DIFF_SYSCLK_B)
timing specifications
Single Source clocking mode requires single onboard oscillator to provide reference
clock input to Differential System clock pair (DIFF_SYSCLK/DIFF_SYSCLK_B).
This Differential clock pair input provides clock to Core, Platform, DDR and USB PLL's
This figure shows a receiver reference diagram of the Differential System clock.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
118
NXP Semiconductors
Electrical characteristics
DIFF_SYSCLK
LVDS
RX
100 Ohm
DIFF_SYSCLK_B
Figure 15. LVDS receiver
This section provides the differential system clock DC and AC timing specifications.
3.8.6.1 Differential system clock DC timing characteristics
The Differential System clock receiver voltage requirements are as specified in the
Recommended operating conditions table.
The Differential system clock can also be single-ended. For this, DIFF_SYSCLK_B
should be connected to OVDD/2.
This table provides the differential system clock (DIFF_SYSCLK/DIFF_SYSCLK_B)
DC specifications.
Table 25. Differential system clock DC electrical characteristics1
Parameter
Input differential voltage swing
Input common mode voltage
Power supply current
Input capacitance
Symbol
Min
Typical
Max
Unit
mV
Notes
Vid
100
50
-
600
1570
5
2
-
Vicm
Icc
-
mV
mA
pF
-
-
-
Cin
1.45
1.5
1.55
-
Note:
1. At recommended operating conditions with OVDD = 1.8 V, see Table 5 for details.
2. Input differential voltage swing (Vid) specified is equal to |VDIFF_SYSCLK_P - VDIFF_SYSCLK_N|
3.8.6.2 Differential system clock AC timing specifications
Spread Spectrum clocking is not supported on Differential System clock pair input.
This table provides the differential system clock (DIFF_SYSCLK/DIFF_SYSCLK_B)
AC specifications.
Table 26. Differential system clock AC electrical characteristics1
Parameter
Symbol
Min
Typical
Max
Unit
MHz
Notes
DIFF_SYSCLK/DIFF_SYSCLK_B
frequency range
tDIFF_SYSCLK
-
100
-
-
-
-
DIFF_SYSCLK/DIFF_SYSCLK_B
frequency tolerance
tDIFF_TOL
-300
+300
ppm
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
119
Electrical characteristics
Table 26. Differential system clock AC electrical characteristics1 (continued)
Parameter
Symbol
tDIFF_DUTY
tDIFF_TJ
Min
Typical
Max
Unit
Notes
Duty cycle
40
-
50
-
60
100
4
%
-
Clock period jitter (peak to peak)
ps
1
-
Slew rate
tDIFF_slew
0.5
-
V/ns
Note:
1. This is evaluated with supply noise profile at +/- 5% sine wave
2. At recommended operating conditions with OVDD = 1.8 V, see Table 5
3. The 100 MHz reference frequency is needed if USB is used. The reference clock to USB PHY is selectable between
SYSCLK or DIFF_SYSCLK/DIF_SYSCLK_B. The selected clock must meet the clock specifications as mentioned in USB 3.0
reference clock requirements .
3.8.7 Other input clocks
A description of the overall clocking of this device is available in the chip reference
manual in the form of a clock subsystem block diagram. For information about the input
clock requirements of functional modules sourced external of the chip, such as SerDes,
Ethernet management, eSDHC, and IFC, see the specific interface section.
3.9 RESET initialization
This table provides the AC timing specifications for the RESET initialization timing.
Table 27. RESET Initialization timing specifications
Parameter/Condition
Required assertion time of PORESET_B after VDD is stable
Required input assertion time of HRESET_B
Maximum rise/fall time of HRESET_B
Min
Max
Unit
Notes
1
—
—
10
1
ms
1
32
—
—
SYSCLKs
SYSCLK
SYSCLK
μs
2, 3
4,5
4,6
—
Maximum rise/fall time of PORESET_B
PLL input setup time with stable SYSCLK before HRESET_B negation 100
—
—
Input setup time for POR configs with respect to negation of
PORESET_B
4
SYSCLKs
2
Input hold time for all POR configs with respect to negation of
PORESET_B
2
—
5
SYSCLKs
SYSCLKs
2
2
Maximum valid-to-high impedance time for actively driven POR
configs with respect to negation of PORESET_B
—
Notes:
1. PORESET_B must be driven asserted before the core and platform power supplies are powered up.
2. SYSCLK is the primary clock input for the chip.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
120
NXP Semiconductors
Electrical characteristics
Table 27. RESET Initialization timing specifications
Parameter/Condition
Min
Max
Unit
Notes
3. The device asserts HRESET_B as an output when PORESET_B is asserted to initiate the power-on reset process. The
device releases HRESET_B sometime after PORESET_B is deasserted. The exact sequencing of HRESET_B deassertion is
documented in the reference manual's "Power-on Reset Sequence" section.
4. The system/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
5. For HRESET_B the rise/fall time should not exceed 10 SYSCLKs. Rise time refers to signal transitions from 20% to 70% of
OVDD. Fall time refers to transitions from 70% to 20% of OVDD.
6. For PORESET_B the rise/fall time should not exceed 1 SYSCLK. Rise time refers to signal transitions from 20% to 70% of
OVDD. Fall time refers to transitions from 70% to 20% of OVDD.
This table provides the phase-locked loop (PLL) lock times.
Table 28. PLL lock times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times (Core, platform, DDR only)
—
100
μs
—
3.10 DDR4 and DDR3L SDRAM controller
This section describes the DC and AC electrical specifications for the DDR4 and DDR3L
SDRAM controller interface. Note that the required G1VDD(typ) voltage is 1.2 V when
interfacing to DDR4 SDRAM and the G1VDD(typ) voltage is 1.35 V when interfacing to
DDR3L SDRAM.
3.10.1 DDR4 and DDR3L SDRAM interface DC electrical
characteristics
This table provides the recommended operating conditions for the DDR SDRAM
controller when interfacing to DDR3L SDRAM.
Table 29. DDR3L SDRAM interface DC electrical characteristics (G1VDD = 1.35 V)1, 9
Parameter
I/O reference voltage
Symbol
Min
Max
Unit
Note
2, 3, 4
D1_MVREF
0.49 x G1VDD
0.51 x G1VDD
V
V
V
Input high voltage
VIH
VIL
IOH
IOL
D1_MVREF + 0.090 G1VDD
5
Input low voltage
GND
-
D1_MVREF - 0.090
5
Output high current (VOUT = 0.641V)
Output low current (VOUT =0.641 V)
-23.3
-
mA
mA
7, 8
7, 8
23.3
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
121
Electrical characteristics
Table 29. DDR3L SDRAM interface DC electrical characteristics (G1VDD = 1.35 V)1, 9
(continued)
Parameter
I/O leakage current
Notes:
Symbol
IOZ
Min
Max
Unit
Note
-165
165
μA
6
1. G1VDD is expected to be within 50 mV of the DRAM's voltage supply at all times. The voltage supply of DRAM and
memory controller may or may not be from the same source.
2. D1_MVREF is expected to be equal to 0.5 x G1VDD and to track G1VDD DC variations as measured at the receiver. Peak-
to-peak noise on D1_MVREF may not exceed the D1_MVREF DC level by more than 1% of G1VDD (that is, 13.5mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to D1_MVREF with a min value of D1_MVREF - 0.04 and a max value of D1_MVREF + 0.04. VTT should track variations
in the DC level of D1_MVREF
.
4. The voltage regulator for D1_MVREF must meet the specifications listed below in table "Current draw characteristics for
D1_MVREF1".
5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ G1VDD
7. See the IBIS model for the complete output IV curve characteristics.
8. IOH and IOL are measured at G1VDD = 1.282 V.
.
9. For recommended operating conditions, refer to Table 5.
This table provides the recommended operating conditions for the DDR SDRAM
controller when interfacing to DDR4 SDRAM.
Table 30. DDR4 SDRAM interface DC electrical characteristics (G1VDD = 1.2 V)1, 8
Parameter
Symbol
VIL
Min
Max
Unit
Note
1, 3, 7
Input low
Input high
-
0.7 x G1VDD - 0.175 V
VIH
0.7 x G1VDD
0.175
+
-
V
1, 3, 7
Output high current (VOUT = 0.57V)
Output low current (VOUT =0.57V)
I/O leakage current
IOH
IOL
IOZ
-
-20.7
-
mA
mA
μA
4, 5
4, 5
6
20.7
-165
165
Notes:
1. G1VDD is expected to be within 60 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's
voltage supply may or may not be from the same source.
2. VTT and VREFCA are applied directly to the DRAM device. Both VTT and VREFCA voltages must track G1VDD/2.
3. Input capacitance load for MDQ, MDQS, and MDQS_B are available in the IBIS models.
4. IOH and IOL are measured at G1VDD = 1.14 V.
5. Refer to the IBIS model for the complete output IV curve characteristics.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ G1VDD
7. Internal Vref for data must be set to 0.7 x G1VDD
8. For recommended operating conditions, refer to Table 5.
.
.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
122
NXP Semiconductors
Electrical characteristics
This table provides the current draw characteristics for D1_MVREF
.
1
Table 31. Current draw characteristics for D1_MVREF
Parameter
Symbol
Min
Max
Unit
Notes
Current draw for DDR3L SDRAM for
D1_MVREF
ID1_MVREF
-
500
μA
-
Note:
1. For recommended operating conditions, refer to Table 5.
3.10.2 DDR4 and DDR3L SDRAM interface AC timing specifications
This section provides the AC timing specifications for the DDR SDRAM controller
interface. The DDR controller supports DDR4 and DDR3L memories. Note that the
required G1VDD(typ) voltage is 1.2 V when interfacing to DDR4 SDRAM. The required
G1VDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.
3.10.2.1 DDR4 and DDR3L SDRAM interface input AC timing
specifications
This table provides the input AC timing specifications for the DDR controller when
interfacing to DDR3L SDRAM.
Table 32. DDR3L SDRAM interface input AC timing specifications1
Parameter
Symbol
Min
Max
D1_MVREF- 0.135
D1_MVREF- 0.160
-
Unit
Notes
AC input low voltage
AC input high voltage
Notes:
> 1200 MT/s data rate VILAC
-
V
-
-
≤ 1200 MT/s data rate
> 1200 MT/s data rate VIHAC
≤ 1200 MT/s data rate
D1_MVREF+ 0.135
D1_MVREF+ 0.160
V
1. For recommended operating conditions, see Table 5.
This table provides the input AC timing specifications for the DDR controller when
interfacing to DDR4 SDRAM.
Table 33. DDR4 SDRAM interface input AC timing specifications1
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage ≤ 1600 MT/s data rate VILAC
-
0.7 x G1VDD -
0.175
V
-
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
123
Electrical characteristics
Table 33. DDR4 SDRAM interface input AC timing specifications1 (continued)
Parameter
Symbol
VIHAC
Min
Max
Unit
Notes
AC input high voltage
≤ 1600 MT/s data rate
0.7 x G1VDD +
0.175
-
V
-
Notes:
1. For recommended operating conditions, see Table 5.
This table provides the input AC timing specifications for the DDR controller when
interfacing to DDR3L and DDR4 SDRAM.
Table 34. DDR4 and DDR3L SDRAM interface input AC timing specifications3
Parameter
Controller Skew for MDQS-MDQ/MECC
1600 MT/s data rate
Symbol
tCISKEW
Min
Max
Unit
Notes
ps
-112
-125
-142
-170
112
125
142
170
1
1
1300 MT/s data rate
1200 MT/s data rate
1, 4
1, 4
1000 MT/s data rate
Tolerated Skew for MDQS-MDQ/MECC
1600 MT/s data rate
tDISKEW
ps
-200
-250
-275
-300
200
250
275
300
2
1300 MT/s data rate
2
1200 MT/s data rate
2, 4
2, 4
1000 MT/s data rate
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This must be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW = (T ꢀ 4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW
.
3. For recommended operating conditions, see Table 5.
4. DDR3L only
This figure shows the DDR4 and DDR3L SDRAM interface input timing diagram.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
124
NXP Semiconductors
Electrical characteristics
MCK_B[n]
MCK[n]
tMCK
MDQS[n]
MDQ[x]
tDISKEW
D0
D1
tDISKEW
tDISKEW
Figure 16. DDR4 and DDR3L SDRAM Interface Input Timing Diagram
3.10.2.2 DDR4 and DDR3L SDRAM interface output AC timing
specifications
This table provides the output AC timing targets for the DDR4 and DDR3L SDRAM
interface.
Table 35. DDR4 and DDR3L SDRAM interface output AC timing specifications8
Parameter
MCK[n] cycle time
Symbol1
Min
Max
Unit
Notes
tMCK
tDDKHAS
1250
495
2000
—
ps
ps
2
3
ADDR/CMD/CNTL
output setup with
respect to MCK
1600 MT/s data
rate
1300 MT/s data
rate
606
675
744
495
606
675
—
—
—
—
—
—
1200 MT/s data
rate
3, 6
3, 6
3
1000 MT/s data
rate
ADDR/CMD/CNTL
output hold with
respect to MCK
1600 MT/s data
rate
tDDKHAX
ps
1300 MT/s data
rate
1200 MT/s data
rate
3, 6
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
125
Electrical characteristics
Table 35. DDR4 and DDR3L SDRAM interface output AC timing specifications8 (continued)
Parameter
1000 MT/s data
rate
Symbol1
Min
Max
Unit
Notes
3, 6
744
—
MCK to MDQS Skew
tDDKHMH
-245
245
ps
ps
4, 7
5
≥ 1000 MT/s data rate, ≤ 1600 MT/s data
rate
MDQ/MECC/MDM
output Data eye
1600 MT/s data
rate
tDDKXDEYE,
400
500
550
600
—
—
—
—
—
1300 MT/s data
rate
1200 MT/s data
rate
5, 6
5, 6
1000 MT/s data
rate
MDQS preamble
MDQS postamble
Notes:
tDDKHMP
tDDKHME
900 x tMCK
400 x tMCK
ps
ps
—
—
600 x tMCK
1. The symbols used for timing specifications follow these patterns: t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD)
from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS
symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are
setup (S) or output valid time.
2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through
control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the
same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two
parameters have been set to the same adjustment value. See the chip reference manual for a description and explanation of
the timing modifications enabled by the use of these bits.
5. Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller
will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization.
6. DDR3L only.
7. Note that it is required to program the start value of the MDQS adjust for write leveling.
8. For recommended operating conditions, refer to table Table 5.
NOTE
For the ADDR/CMD setup and hold specifications in
Recommended operating conditions, it is assumed that the
clock control register is set to adjust the memory clocks by ½
applied cycle.
This figure shows the DDR4 and DDR3L SDRAM interface output timing for the MCK
to MDQS skew measurement (tDDKHMH).
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
126
NXP Semiconductors
Electrical characteristics
MCK_B[n]
MCK[n]
t
MCK
t
DDKHMH(max)
MDQS
MDQS
t
DDKHMH(min)
Figure 17. tDDKHMH timing diagram
This figure shows the DDR4 and DDR3L SDRAM output timing diagram.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
127
Electrical characteristics
MCK_B
MCK
tMCK
tDDKHAS
tDDKHAX
NOOP
ADDR/CMD
Write A0
tDDKHMP
tDDKHMH
MDQS[n]
MDQ[x]
tDDKHME
D0
D1
tDDKXDEYE
tDDKXDEYE
Figure 18. DDR4 and DDR3L output timing diagram
3.11 Ethernet interface, Ethernet management interface, IEEE
Std 1588™
This section describes the DC and AC electrical characteristics for the Ethernet
controller, Ethernet management, and IEEE Std 1588 interfaces.
3.11.1 SGMII interface
Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of
the chip, as shown in Figure 19, where CTX is the external (on board) AC-coupled
capacitor. Each SerDes transmitter differential pair features 100-Ω output impedance.
Each input of the SerDes receiver differential pair features 50-Ω on-die termination to
XGNDn. The reference circuit of the SerDes transmitter and receiver is shown in Figure
94.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
128
NXP Semiconductors
Electrical characteristics
3.11.1.1 SGMII clocking requirements for SD1_REF_CLKn_P and
SD1_REF_CLKn_N
When operating in SGMII mode, the ECn_GTX_CLK125 clock is not required for this
port. Instead, a SerDes reference clock is required on SD1_REF_CLK[1:2]_P and
SD1_REF_CLK[1:2]_N pins. SerDes lanes may be used for SerDes SGMII
configurations based on the RCW Configuration field SRDS_PRTCL.
For more information on these specifications, see SerDes reference clocks.
3.11.1.2 SGMII DC electrical characteristics
This section describes the electrical characteristics for the SGMII interface.
3.11.1.2.1 SGMII and SGMII 2.5G transmit DC specifications
This table describes the SGMII SerDes transmitter AC-coupled DC electrical
characteristics. Transmitter DC characteristics are measured at the transmitter outputs
(SD1_TXn_P and SD1_TXn_N)as shown in SGMII and SGMII 2.5G transmit DC
specifications.
Table 36. SGMII DC transmitter electrical characteristics (X1VDD = 1.35 V)4
Parameter
Symbo
l
Min
Typ
Max
Un
it
Notes
Output high voltage
Output low voltage
VOH
VOL
-
-
-
1.5 x │VOD
│
-max
mV 1
mV 1
│VOD
min/2
│
-
-
Output differential
voltage2, 3, 5
│VOD
│
320
500.0 725.0
459.0 665.6
417.0 604.7
376.0 545.2
333.0 482.9
292.0 423.4
250.0 362.5
mV LNmTECR0[AMP_RED]=0b000000
LNmTECR0[AMP_RED]=0b000001
LNmTECR0[AMP_RED]=0b000011
LNmTECR0[AMP_RED]=0b000010
LNmTECR0[AMP_RED]=0b000110
LNmTECR0[AMP_RED]=0b000111
LNmTECR0[AMP_RED]=0b010000
293.8
266.9
240.6
213.1
186.9
160.0
80
(XVDD-Typ at 1.35 V)
Output impedance
(differential)
RO
100
120
Ω
-
Notes:
1. This does not align to DC-coupled SGMII.
2. │VOD│ = │VSD_TXn_P - VSD_TXn_N│. │VOD│ is also referred to as output differential peak voltage. VTX-DIFFp-p = 2 x │VOD
│
.
3. The │VOD│ value shown in the Typ column is based on the condition of XVDD_SRDSn-Typ = 1.35 V, no common mode
offset variation. SerDes transmitter is terminated with 100-Ω differential load between SDn _TXn_P and SDn_TXn_N.
4. For recommended operating conditions, see Table 5.
5. Example amplitude reduction setting for SGMII on lane A: LNaTECR0[AMP_RED] = 0b000001 for an output differential
voltage of 459 mV typical.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
129
Electrical characteristics
This figure shows an example of a 4-wire AC-coupled SGMII serial link connection.
SDn_RXn_P
SDn_TXn_P
CTX
50 Ω
Transmitter
Receiver
100 Ω
CTX
SDn_TXn_N
SDn_RXn_N
50 Ω
SGMII
SerDes Interface
SDn_RXn_P
SDn_TXn_P
CTX
50 Ω
Receiver
Transmitter
100 Ω
CTX
SDn_RXn_N
SDn_TXn_N
50 Ω
Figure 19. 4-wire AC-coupled SGMII serial link connection example
This figure shows the SGMII transmitter DC measurement circuit.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
130
NXP Semiconductors
Electrical characteristics
SGMII
SerDes Interface
SDn_TXn_P
50 Ω
Transmitter
VOD
100 Ω
50 Ω
SDn_TXn_N
Figure 20. SGMII transmitter DC measurement circuit
This table defines the SGMII 2.5G transmitter DC electrical characteristics for 3.125
GBaud.
Table 37. SGMII 2.5G transmitter DC electrical characteristics (X1VDD = 1.35 V)1
Parameter
Symbol
│VOD
RO
Min
Typical
Max
Unit
Notes
Output differential voltage
│
400
80
-
600
120
mV
Ω
-
-
Output impedance (differential)
100
Notes:
1. For recommended operating conditions, see Table 5.
3.11.1.2.2 SGMII and SGMII 2.5G DC receiver electrical characteristics
This table lists the SGMII DC receiver electrical characteristics. Source synchronous
clocking is not supported. Clock is recovered from the data.
Table 38. SGMII DC receiver electrical characteristics (S1VDD)4
Parameter
DC input voltage range
Symbol
Min
Typ
Max
Unit Notes
-
N/A
100
175
30
-
1
Input differential voltage
REIDL_TH = 001
REIDL_TH = 100
REIDL_TH = 001
REIDL_TH = 100
VRX_DIFFp-p
-
-
-
-
1200
mV
2, 5
Loss of signal threshold
VLOS
100
175
mV
3, 5
65
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
131
Electrical characteristics
Table 38. SGMII DC receiver electrical characteristics (S1VDD)4 (continued)
Parameter
Symbol
ZRX_DIFF
Min
Typ
Max
Unit Notes
Receiver differential input impedance
Notes:
80
-
120
Ω
-
1. Input must be externally AC coupled.
2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See PCI
Express DC physical layer receiver specifications, and PCI Express AC physical layer receiver specifications, for further
explanation.
4. For recommended operating conditions, see Table 5.
5. The REIDL_TH shown in the table refers to the chip's SRDSxLNmGCR1[REIDL_TH] bit field.
This table defines the SGMII 2.5G receiver DC electrical characteristics for 3.125
GBaud.
Table 39. SGMII 2.5G receiver DC timing specifications (S1VDD)1
Parameter
Input differential voltage
Loss of signal threshold
Receiver differential input impedance
Notes:
Symbol
Min
Typical
Max
Unit
Notes
VRX_DIFFp-p 200
-
-
-
1200
200
mV
mV
Ω
-
-
-
VLOS
75
80
ZRX_DIFF
120
1. For recommended operating conditions, see Table 5.
3.11.1.3 SGMII AC timing specifications
This section describes the AC timing specifications for the SGMII interface.
3.11.1.3.1 SGMII and SGMII 2.5G transmit AC timing specifications
This table provides the SGMII and SGMII 2.5G transmit AC timing specifications. A
source synchronous clock is not supported. The AC timing specifications do not include
RefClk jitter.
Table 40. SGMII transmit AC timing specifications4
Parameter
Deterministic jitter
Symbol
JD
Min
Typ
Max
Unit
UI p-p
UI p-p
Notes
-
-
-
-
0.17
0.35
-
Total jitter
JT
UI
2
1
1
Unit Interval: 1.25 GBaud (SGMII)
800 - 100 ppm 800
320 - 100 ppm 320
800 + 100 ppm ps
320 + 100 ppm ps
Unit Interval: 3.125 GBaud (2.5G SGMII]) UI
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
132
NXP Semiconductors
Electrical characteristics
Table 40. SGMII transmit AC timing specifications4 (continued)
Parameter
AC coupling capacitor
Symbol
CTX
Min
Typ
Max
Unit
Notes
10
-
200
nF
3
Notes:
1. Each UI is 800 ps 100 ppm or 320 ps 100 ppm.
2. See SGMII and SGMII 2.5G receiver AC timing Specification for single frequency sinusoidal jitter measurements.
3. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter output.
4. For recommended operating conditions, see Table 5.
3.11.1.3.2 SGMII AC measurement details
Transmitter and receiver AC characteristics are measured at the transmitter outputs
(SDn_TXn_P and SDn_TXn_N) or at the receiver inputs (SDn_RXn_P and
SDn_RXn_N) respectively, as shown in this figure.
D + package pin
C = CTX
Transmitter
silicon
+ package
C = CTX
D - package pin
R = 50 Ω
R = 50 Ω
Figure 21. SGMII AC test/measurement load
3.11.1.3.3 SGMII and SGMII 2.5G receiver AC timing Specification
This table provides the SGMII and SGMII 2.5G receiver AC timing specifications. The
AC timing specifications do not include RefClk jitter. Source synchronous clocking is not
supported. Clock is recovered from the data.
Table 41. SGMII Receive AC timing specifications3
Parameter
Deterministic jitter tolerance
Symbol
JD
Min
Typ
Max
Unit
Notes
-
-
-
-
0.37
0.55
UI p-p
1
1
Combined deterministic and random jitter tolerance JDR
UI p-p
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
133
Electrical characteristics
Table 41. SGMII Receive AC timing specifications3 (continued)
Parameter
Symbol
JT
Min
Typ
Max
Unit
Notes
1, 2
Total jitter tolerance
-
-
-
-
0.65
UI p-p
Bit error ratio
BER
UI
10-12
-
-
Unit Interval: 1.25 GBaud (SGMII)
Unit Interval: 3.125 GBaud (2.5G SGMII])
Notes:
800 - 100 ppm 800
320 - 100 ppm 320
800 + 100 ppm ps
320 + 100 ppm ps
1
1
UI
1. Measured at receiver
2.Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of the figure given below. The sinusoidal jitter
component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
3. For recommended operating conditions, see Table 5.
The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in
the unshaded region of this figure.
8.5 UI p-p
Sinuosidal
Jitter
20 dB/dec
Amplitude
0.10 UI p-p
20 MHz
baud/142000
baud/1667
Frequency
Figure 22. Single-frequency sinusoidal jitter limits
3.11.2 QSGMII interface
This section describes the QSGMII clocking and its DC and AC electrical characteristics.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
134
NXP Semiconductors
Electrical characteristics
3.11.2.1 QSGMII clocking requirements for SD1_REF_CLKn_P and
SD1_REF_CLKn_N
For more information on these specifications, see SerDes reference clocks.
3.11.2.2 QSGMII DC electrical characteristics
This section discusses the electrical characteristics for the QSGMII interface.
3.11.2.2.1 QSGMII transmitter DC specifications
This table describes the QSGMII SerDes transmitter AC-coupled DC electrical
characteristics. Transmitter DC characteristics are measured at the transmitter outputs
(SDn_TXn and SDn_TXn_B).
Table 42. QSGMII DC transmitter electrical characteristics (X1VDD = 1.35V)1
Parameter
Symbol
Min
Typ
Max
Unit
mV
Notes
Output differential voltage
VDIFF
400
80
-
900
120
-
-
Differential resistance
TRD
100
Ω
Notes:
1. For recommended operating conditions, see Table 5.
3.11.2.2.2 QSGMII DC receiver electrical characteristics
This table defines the QSGMII receiver DC electrical characteristics.
Table 43. QSGMII receiver DC timing specifications (S1VDD)1
Parameter
Input differential voltage
Differential resistance
Notes:
Symbol
VDIFF
RRDIN
Min
Typical
Max
Unit
Notes
100
80
-
900
120
mV
Ω
-
-
100
1. For recommended operating conditions, see Table 5.
3.11.2.3 QSGMII AC timing specifications
This section discusses the AC timing specifications for the QSGMII interface.
3.11.2.3.1 QSGMII transmit AC timing specifications
This table provides the QSGMII transmitter AC timing specifications.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
135
Electrical characteristics
Table 44. QSGMII transmit AC timing specifications1
Parameter
Transmitter baud rate
Uncorrelated high probability jitter
Total jitter tolerance
Notes:
Symbol
TBAUD
TUHPJ
JT
Min
Typ
Max
5.000 + 100 ppm
0.15
Unit
Gb/s
Notes
5.000 - 100 ppm 5.000
-
-
-
-
-
-
-
UI p-p
UI p-p
0.30
1. For recommended operating conditions, see Table 5.
3.11.2.3.2 QSGMII receiver AC timing Specification
This table provides the QSGMII receiver AC timing specifications.
Table 45. QSGMII receive AC timing specifications2
Parameter
Symbol
RBAUD
RDJ
Min
Typ
Max
Unit
Notes
Receiver baud rate
5.000 - 100 ppm 5.000
5.000 + 100 ppm Gb/s
-
-
1
-
-
-
-
Uncorrelated bounded high probability jitter
Correlated bounded high probability jitter
Bounded high probability jitter
Sinusoidal jitter, maximum
-
-
-
-
-
-
-
-
-
-
-
-
0.15
0.30
0.45
5.00
0.05
0.60
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
RCBHPJ
RBHPJ
RSJ-max
RSJ-hf
RTj
Sinusoidal jitter, high frequency
Total jitter (does not include sinusoidal jitter)
Notes:
1. The jitter (RCBHPJ) and amplitude have to be correlated, for example, by a PCB trace.
2. For recommended operating conditions, see Table 5.
The sinusoidal jitter may have any amplitude and frequency in the unshaded region of
this figure.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
136
NXP Semiconductors
Electrical characteristics
5 UI p-p
Sinuosidal
Jitter
Amplitude
0.05 UI p-p
20 MHz
35.2 kHz
3 MHz
Frequency
Figure 23. QSGMII single-frequency sinusoidal jitter limits
3.11.3 XFI interface
This section describes the XFI clocking requirements and its DC and AC electrical
characteristics.
3.11.3.1 XFI clocking requirements for SD1_REF_CLKn_P and
SD1_REF_CLKn_N
Only SerDes PLL1 (SD1_REF_CLK1_P and SD1_REF_CLK1_N) is allowed be used
for XFI configurations based on the RCW Configuration field SRDS_PRTCL.
For more information on these specifications, see SerDes reference clocks.
3.11.3.2 XFI DC electrical characteristics
This section describes the DC electrical characteristics for XFI.
3.11.3.2.1 XFI transmitter DC electrical characteristics
This table defines the XFI transmitter DC electrical characteristics.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
137
Electrical characteristics
Table 46. XFI transmitter DC electrical characteristics (XVDD = 1.35V)1
Parameter
Symbol
VTX-DIFF
Min
Typical
Max
Unit
Notes
Output differential voltage
360
0.6
-
770
1.6
mV
dB
-
-
De-emphasized differential output
voltage (ratio)
VTX-DE-
1.1
3.5
4.6
6.0
9.5
100
RATIO-1.14dB
De-emphasized differential output
voltage (ratio)
VTX-DE-
3
4
dB
dB
dB
dB
Ω
-
-
-
-
-
RATIO-3.5dB
De-emphasized differential output
voltage (ratio)
VTX-DE-
4.1
5.5
9
5.1
6.5
10
RATIO-4.66dB
De-emphasized differential output
voltage (ratio)
VTX-DE-
RATIO-6.0dB
De-emphasized differential output
voltage (ratio)
VTX-DE-
RATIO-9.5dB
Differential resistance
Notes:
TRD
80
120
1. For recommended operating conditions, see Table 5.
3.11.3.2.2 XFI receiver DC electrical characteristics
This table defines the XFI receiver DC electrical characteristics.
Table 47. XFI receiver DC electrical characteristics (S1VDD)2
Parameter
Input differential voltage
Differential resistance
1. Measured at receiver
Symbol
VRX-DIFF
RRD
Min
Typical
Max
Unit
Notes
110
80
-
1050
120
mV
Ω
1
-
100
2. For recommended operating conditions, see Table 5.
3.11.3.3 XFI AC timing specifications
This section describes the AC timing specifications for XFI.
3.11.3.3.1 XFI transmitter AC timing specifications
This table defines the XFI transmitter AC timing specifications. RefClk jitter is not
included.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
138
NXP Semiconductors
Electrical characteristics
Table 48. XFI transmitter AC timing specifications1
Parameter
Transmitter baud rate
Symbol
TBAUD
Min
Typical
Max
Unit
10.3125 - 100ppm 10.3125
10.3125 +
100ppm
-
Gb/s
ps
Unit Interval
Deterministic jitter
Total jitter
UI
DJ
TJ
-
-
-
96.96
-
-
0.15
0.30
UI p-p
UI p-p
Notes:
1. For recommended operating conditions, see Table 5.
3.11.3.3.2 XFI receiver AC timing specifications
This table defines the XFI receiver AC timing specifications. RefClk jitter is not
included.
Table 49. XFI receiver AC timing specifications3
Parameter
Receiver baud rate
Symbol
RBAUD
Min
Typical
10.3125
Max
Unit
Gb/s
Notes
10.3125 -
100ppm
10.3125 +
100ppm
-
Unit Interval
UI
-
-
-
96.96
-
ps
-
Total non-EQJ jitter
Total jitter tolerance
TNON-EQJ
TJ
-
-
0.45
0.65
UI p-p
UI p-p
1
1, 2
1. The total jitter (TJ) consists of Random Jitter (RJ), Duty Cycle Distortion (DCD), Periodic Jitter (PJ), and Inter symbol
Interference (ISI). Non-EQJ jitter can include duty cycle distortion (DCD), random jitter (RJ), and periodic jitter (PJ). Non-EQJ
jitter is uncorrelated to the primary data stream with exception of the DCD and so cannot be equalized by the receiver under
test. It can exhibit a wide spectrum. Non - EQJ = TJ - ISI = RJ + DCD + PJ
2. The XFI channel has a loss budget of 9.6 dB @5.5GHz. The channel loss including connector @ 5.5GHz is 6dB. The
channel crosstalk and reflection margin is 3.6dB. Manual tuning of TX Equalization and amplitude will be required for
performance optimization.
3. For recommended operating conditions, see Table 5.
This figure shows the sinusoidal jitter tolerance of XFI receiver.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
139
Electrical characteristics
1.13x 0.2 + 0.1 , f in MHz
f
-20 dB/Dec
0.17
0.05
80
0.04
4
8
27.2
Frequency (MHz)
Figure 24. XFI host receiver input sinusoidal jitter tolerance
3.11.4 1000Base-KX interface
This section discusses the electrical characteristics for the 1000Base-KX. Only AC-
coupled operation is supported.
3.11.4.1 1000Base-KX DC electrical characteristics
3.11.4.1.1 1000Base-KX Transmitter DC Specifications
This table describes the 1000Base-KX SerDes transmitter DC specification at TP1 per
IEEE Std 802.3ap-2007. Transmitter DC characteristics are measured at the transmitter
outputs (SD1_TXn_P and SD1_TXn_N).
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
140
NXP Semiconductors
Electrical characteristics
Table 50. 1000Base-KX Transmitter DC Specifications
Parameter
Symbols
VTX-DIFFp-p
Min
Typ
Max
1600
Units
Notes
Output differential
voltage
800
80
-
mV
1
-
Differential
resistance
TRD
100
120
ohm
Notes:
1. SRDSxLNmTECR0[AMP_RED]=00_0000.
2. For recommended operating conditions, see Table 5.
3.11.4.1.2 1000Base-KX Receiver DC Specifications
Table below provides the 1000Base-KX receiver DC timing specifications.
Table 51. 1000Base-KX Receiver DC Specifications
Parameter
Symbols
VRX-DIFFp-p
Min
Typical
Max
1600
Units
Notes
Input differential
voltage
-
-
-
mV
1
-
Differential
resistance
TRDIN
80
120
ohm
Notes:
1. For recommended operating conditions, see Table 5.
3.11.4.2 1000Base-KX AC electrical characteristics
3.11.4.2.1 1000Base-KX Transmitter AC Specifications
Table below provides the 1000Base-KX transmitter AC specification.
Table 52. 1000Base-KX Transmitter AC Specifications
Parameter
Baud Rate
Symbols
TBAUD
Min
Typical
Max
Units
Notes
1.25-100ppm
1.25
-
1.25+100pp Gb/s
m
-
-
Uncorrelated High
Probability Jitter/
Random Jitter
TUHPJTRJ
-
0.15
UI p-p
Deterministic Jitter
Total Jitter
TDJ
TTJ
-
-
-
-
0.10
0.25
UI p-p
UI p-p
-
1
Notes:
1. Total jitter is specified at a BER of 10-12
.
2. For recommended operating conditions, see Table 5.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
141
Electrical characteristics
3.11.4.2.2 1000Base-KX Receiver AC Specifications
Table below provides the 1000Base-KX receiver AC specification with parameters
guided by IEEE Std 802.3ap-2007.
Table 53. 1000Base-KX Receiver AC Specifications
Parameter
Symbols
Min
Typical
Max
Units
Notes
Receiver Baud Rate TBAUD
1.25-100ppm
1.25
1.25+100pp Gb/s
m
-
Random Jitter
RRJ
-
-
-
-
0.15
0.10
UI p-p
UI p-p
1
2
Sinusoidal Jitter,
maximum
RSJ-max
Total Jitter
Notes:
RTJ
-
-
See Note 3 UI p-p
2
1. Random jitter is specified at a BER of 10-12
.
2. The receiver interference tolerance level of this parameter shall be measured as described in Annex 69A of the IEEE Std
802.3ap-2007.
3. Per IEEE 802.3ap-clause 70.
4. The AC specifications do not include Refclk jitter.
5. For recommended operating conditions, see Table 5.
3.11.5 RGMII electrical specifications
This section describes the electrical characteristics for the RGMII interface.
3.11.5.1 RGMII DC electrical characteristics
This table provides the DC electrical characteristics for the RGMII interface at
LVDD = 2.5 V.
Table 54. RGMII DC electrical characteristics (LVDD = 2.5 V)4
Parameters
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
1.70
—
—
V
1
1
VIL
0.70
50
V
Input current (LVIN=0 V or LVIN= LVDD
)
IIN
—
µA
V
2, 3
3
Output high voltage (LVDD = min,IOH = -1.0 mA)
Output low voltage (LVDD = min, IOL = 1.0 mA)
Notes:
VOH
VOL
2.00
—
—
0.4
V
3
1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 5.
2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Table 5.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
142
NXP Semiconductors
Electrical characteristics
Table 54. RGMII DC electrical characteristics (LVDD = 2.5 V)4
Parameters
Symbol
Min
Max
Unit
Notes
3. The symbol LVDD, in this case, represents the LVDD and symbol referenced in Table 5.
4. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for the RGMII interface at
LVDD = 1.8 V.
Table 55. RGMII DC electrical characteristics (LVDD = 1.8 V)4
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
Input low voltage
VIH
VIL
IIN
1.2
—
—
V
1
0.6
V
1
Input current (LVIN = 0 V or LVIN= LVDD
)
—
50
µA
V
2, 3
3
Output high voltage (LVDD = min, IOH = -0.5 mA)
Output low voltage (LVDD = min, IOL = 0.5 mA)
Notes:
VOH
VOL
1.35
—
—
0.4
V
3
1. The min VIL and max VIH values are based on the min and max LVIN values found in Table 5.
2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Table 5.
3. The symbol LVDD, in this case, represents the LVDD symbol referenced in Table 5.
4. For recommended operating conditions, see Table 5.
3.11.5.2 RGMII AC timing specifications
This table provides the RGMII AC timing specifications.
Table 56. RGMII AC timing specifications (LVDD = 2.5 /1.8 V)8
Parameter/Condition
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver)
Symbol1
tSKRGT_TX
tSKRGT_RX
Min
-500
Typ
Max
Unit
Notes
0
500
2.6
ps
ns
7
1.0
—
2
Clock period duration
Duty cycle for 10BASE-T and 100BASE-TX
Duty cycle for Gigabit
Rise time (20%-80%)
LVDD = 2.5V
tRGT
7.2
40
45
—
8.0
50
50
—
8.8
60
55
—
ns
%
%
ns
3
tRGTH/tRGT
tRGTH/tRGT
tRGTR
3, 4
—
5, 6
0.75
0.54
—
LVDD = 1.8V
Fall time (20%-80%)
LVDD = 2.5V
tRGTF
—
—
ns
5, 6
0.75
0.54
LVDD = 1.8V
Notes:
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
143
Electrical characteristics
Table 56. RGMII AC timing specifications (LVDD = 2.5 /1.8 V)8
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII
timing. Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols
representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their device. If so,
additional PCB delay is probably not needed.
3. For 10 and 100 Mbps, tRGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. Applies to inputs and outputs.
6. The system/board must be designed to ensure this input requirement to the chip is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
7. The frequency of ECn_RX_CLK (input) should not exceed the frequency of ECn_GTX_CLK (output) by more than
300 ppm.
8. For recommended operating conditions, see Table 5.
This figure shows the RGMII AC timing and multiplexing diagrams.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
144
NXP Semiconductors
Electrical characteristics
t
RGT
t
RGTH
GTX_CLK
(At MAC, output)
t
t
SKRGT_TX
SKRGT_TX
TXDS[8:5][3:0]
TXD[7:4][3:0]
TXD[8:5]
TXD[7:4]
TXD[3:0]
(At MAC, output)
TXD[9]
TXERR
TXD[4]
TXEN
TX_CTL
(At MAC, output)
PHY equivalent to t
SKRGT_RX
PHY equivalent to t
SKRGT_RX
TX_CLK
(At PHY, input)
t
RGT
t
RGTH
RX_CLK
(At PHY, output)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[7:4]
RXD[3:0]
PHY equivalent to t
(At PHY, output)
SKRGT_TX
PHY equivalent to t
SKRGT_TX
RXD[9]
RXERR
RXD[4]
RXDV
RX_CTL
(At PHY, output)
t
t
SKRGT_RX
SKRGT_RX
RX_CLK
(At MAC, input)
Figure 25. RGMII AC timing and multiplexing diagrams
Warning
NXP guarantees timings generated from the MAC. Board
designers must ensure delays needed at the PHY or the MAC.
3.11.6 Ethernet management interface (EMI)
This section describes the electrical characteristics for the Ethernet Management Interface
(EMI) interface.
Both the interfaces (EMI1 and EMI2) interface timing is compatible with IEEE Std
802.3™ clause 22.
3.11.6.1 Ethernet management interface 1 (EMI1)
This section describes the electrical characteristics for the EMI1 interface.
The EMI1 interface timing is compatible with IEEE Std 802.3™ clause 22.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
145
Electrical characteristics
3.11.6.1.1 EMI1 DC electrical characteristics
This section describes the DC electrical characteristics for EMI1_MDIO and
EMI1_MDC. The pins are available on LVDD. For operating voltages, see Table 5.
This table provides the EMI1 DC electrical characteristics when LVDD = 2.5 V.
Table 57. EMI1 DC electrical characteristics (LVDD = 2.5 V)4
Parameters
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
1.70
—
—
V
1
1
VIL
0.70
50
V
Input current (LVIN = 0 or LVIN = LVDD
)
IIN
—
µA
V
2, 3
—
Output high voltage (LVDD = min, IOH = -1.0 mA)
Output low voltage (LVDD = min, IOL = 1.0 mA)
Notes:
VOH
VOL
2.00
—
—
0.40
V
—
1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 5.
2. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 5.
3. The symbol LVDD, in this case, represents the LVDD symbols referenced in Table 5.
4. For recommended operating conditions, see Table 5.
This table provides the EMI1 DC electrical characteristics when LVDD = 1.8 V.
Table 58. EMI1 DC electrical characteristics (LVDD = 1.8 V)4
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
Input low voltage
VIH
VIL
IIN
1.2
—
—
V
1
1
0.6
V
Input current (LVIN = 0 V or LVIN = LVDD
)
—
50
µA
V
2, 3
3
Output high voltage (LVDD = min, IOH = -0.5 mA)
Output low voltage (LVDD = min, IOL = 0.5 mA)
Notes:
VOH
VOL
1.35
—
—
0.4
V
3
1. The min VIL and max VIH values are based on the min and max LVIN respective values found in Table 5.
2. The symbol LVIN represents the LVIN symbols referenced in Table 5.
3. The symbol LVDD, in this case, represents the LVDD symbols referenced in Table 5.
4. For recommended operating conditions, see Table 5.
3.11.6.1.2 EMI1 AC timing specifications
This table provides the EMI1 AC timing specifications.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
146
NXP Semiconductors
Electrical characteristics
Table 59. EMI1 AC timing specifications6
Parameter/Condition
MDC frequency
Symbol1
Min
Typ
Max
Unit
MHz
Notes
fMDC
—
—
—
—
2.5
—
2
MDC clock pulse width high
MDC to MDIO delay
tMDCH
160
ns
ns
—
tMDKHDX
(5 x tenet_clk) - 4.8
(5 x tenet_clk) +
4.6
3, 4
MDIO to MDC setup time
MDIO to MDC hold time
Notes:
tMDDVKH
tMDDXKH
8
—
—
—
—
ns
ns
—
5
2.75
1. The symbols used for timing specifications follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management
data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time.
2. This parameter is dependent on the Ethernet clock frequency. The MDIO_CFG [MDIO_CLK_DIV] field determines the
clock frequency of the MgmtClk Clock EC_MDC.
3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to 5 Ethernet clock periods 3 ns. For
example, with an Ethernet clock of 400 MHz, the min/max delay is 12.5 ns 3 ns.
4. tenet_clk is the Ethernet clock period (Frame Manager clock period x 2).
5. For more details, see the application note titled QorIQ LS1043A Design Checklist (document AN5012).
6. For recommended operating conditions, see Table 5.
This figure shows the Ethernet management interface 1 timing diagram
t
MDC
MDC
t
MDCH
MDIO
(Input)
t
MDDVKH
t
MDDXKH
MDIO
(Output)
t
MDKHDX
Figure 26. Ethernet management interface 1 timing diagram
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
147
Electrical characteristics
3.11.6.2 Ethernet management interface 2 (EMI2)
This section describes the electrical characteristics for the EMI2 interface.
The EMI2 interface timing is compatible with IEEE Std 802.3™ clause 45.
3.11.6.2.1 EMI2 DC electrical characteristics
This section describes the DC electrical characteristics for EMI2_MDIO and
EMI2_MDC. The pins are available on TVDD. For operating voltages, see Recommended
operating conditions .
This table provides the EMI2 DC electrical characteristics when TVDD = 2.5 V.
Table 60. EMI2 DC electrical characteristics (TVDD = 2.5 V)4
Parameters
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
0.7 x TVDD
—
V
1
1
VIL
—
0.2 x TVDD
V
Input current (TVIN = 0 or TVIN = TVDD
)
IIN
—
50
—
µA
V
2, 3
—
Output high voltage (TVDD = min, IOH = -1.0 mA)
Output low voltage (TVDD = min, IOL = 1.0 mA)
Notes:
VOH
VOL
2.00
—
0.4
V
—
1. The min VIL and max VIH values are based on the respective min and max TVIN values found in Recommended operating
conditions.
2. The symbol VIN, in this case, represents the TVIN symbols referenced in Recommended operating conditions.
3. The symbol TVDD, in this case, represents the TVDD symbols referenced in Recommended operating conditions.
4. For recommended operating conditions, see Table 5.
This table provides the EMI2 DC electrical characteristics when TVDD = 1.8 V.
Table 61. EMI2 DC electrical characteristics (TVDD = 1.8 V)4
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
Input low voltage
VIH
VIL
IIN
0.7 x TVDD
—
V
1
1
—
0.2 x TVDD
V
Input current (TVIN = 0 V or TVIN = TVDD
)
—
50
—
µA
V
2, 3
3
Output high voltage (TVDD = min, IOH = -0.5 mA) VOH
1.35
—
Output low voltage (TVDD = min, IOL = 0.5 mA)
VOL
0.4
V
3
Notes:
1. The min VIL and max VIH values are based on the min and max TVIN respective values found in Recommended operating
conditions.
2. The symbol TVIN represents the TVIN symbols referenced in Recommended operating conditions.
3. The symbol TVDD, in this case, represents the TVDD symbols referenced in Recommended operating conditions.
4. For recommended operating conditions, see Table 5.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
148
NXP Semiconductors
Electrical characteristics
This table provides the EMI2 DC electrical characteristics when TVDD = 1.2 V.
Table 62. EMI2 DC electrical characteristics (TVDD = 1.2 V) 4
Parameter
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
0.7 x TVDD
—
V
—
—
—
—
—
—
VIL
—
4
0.2 x TVDD
V
Output low current (VOL = 0.2 V)
Output high voltage (TVDD = min, IOH = -100uA)
Output low voltage (TVDD = min, IOL = 100 uA)
Input Capacitance
IOL
mA
V
VOH
VOL
CIN
1.0
—
—
—
0.2
10
V
pF
Notes:
1. For recommended operating conditions, see Table 5.
3.11.6.2.2 EMI2 AC timing specifications
This table provides the EMI2 AC timing specifications.
Table 63. EMI2 AC timing specifications at 2.5 MHz7
Parameter/Condition
MDC frequency
Symbol1
Min
Typ
Max
Unit
Notes
fMDC
—
—
—
—
—
—
2.5
—
MHz
ns
2
MDC clock pulse width high
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
Notes:
tMDCH
160
—
3, 4
6
tMDKHDX
tMDDVKH
tMDDXKH
(5 x tenet_clk) - 115
(5 x tenet_clk) + 115 ns
90
—
—
ns
ns
2.75
5
1. The symbols used for timing specifications follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management
data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time.
2. This parameter is dependent on the Ethernet clock frequency. The MDIO_CFG [MDIO_CLK_DIV] field determines the
clock frequency of the MgmtClk Clock EC_MDC.
3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to 5 Ethernet clock periods 115 ns.
Note that the reference is measured from falling edge of the clock.
4. tenet_clk is the Ethernet clock period (Frame Manager clock period x 2).
5. For more details, see the application note titled LS1043A Design Checklist (document AN5012).
6. The setup time tMDDVKH is measured at
a) 470pf load @ 1.2 V in open-drain configuration.
b) 300pf load @ 1.2 V in push-pull configuration.
7. For recommended operating conditions, see Table 5
This table provides the EMI2 AC timing specifications.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
149
Electrical characteristics
Table 64. EMI2 AC timing specifications at 10 MHz (TVDD = 1.2V)8
Parameter/Condition
MDC frequency
Symbol1
Min
Typ
Max
Unit
MHz
ns
Notes
fMDC
—
—
—
—
—
—
10
—
2
MDC clock pulse width high
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
Notes:
tMDCH
35
—
3, 4
6
tMDKHDX
tMDDVKH
tMDDXKH
(5 x tenet_clk) - 30
(5 x tenet_clk) + 20 ns
30
—
—
ns
ns
2.75
5
1. The symbols used for timing specifications follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management
data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time.
2. This parameter is dependent on the Ethernet clock frequency. The MDIO_CFG [MDIO_CLK_DIV] field determines the
clock frequency of the MgmtClk Clock EC_MDC.
3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to 5 Ethernet clock periods 115 ns.
Note that the reference is measured from falling edge of the clock.
4. tenet_clk is the Ethernet clock period (Frame Manager clock period x 2).
5. For more details, see the application note titled LS1043A Design Checklist (document AN5012).
6. The setup time tMDDVKH is measured at 75pf load.
7. Valid for open-drain and push-pull configuration.
8. For recommended operating conditions, see Table 5
This figure shows the Ethernet management interface 2 timing diagram
t
MDC
MDC
t
MDCH
MDIO
(Input)
t
MDDVKH
t
MDDXKH
MDIO
(Output)
t
MDKHDX
Figure 27. Ethernet management interface 2 timing diagram
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
150
NXP Semiconductors
Electrical characteristics
3.11.7 IEEE 1588 electrical specifications
3.11.7.1 IEEE 1588 DC electrical characteristics
This table provides the IEEE 1588 DC electrical characteristics when operating at
LVDD = 2.5 V supply.
Table 65. IEEE 1588 DC electrical characteristics(LVDD = 2.5 V)3
Parameters
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
1.70
—
—
V
1
1
2
VIL
0.70
50
V
Input current (LVIN= 0 V or LVIN= LVDD
)
IIN
—
µA
V
Output high voltage (LVDD = min, IOH = -1.0 mA)
Output low voltage (LVDD = min, IOL = 1.0 mA)
Notes:
VOH
VOL
2.00
—
—
—
—
0.40
V
1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 5.
2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
This table provides the IEEE 1588 DC electrical characteristics when operating at
LVDD = 1.8 V supply.
Table 66. IEEE 1588 DC electrical characteristics(LVDD = 1.8 V)3
Parameters
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
1.2
—
—
V
1
VIL
0.6
V
1
Input current (LVIN= 0 V or LVIN= LVDD
)
IIN
—
50
µA
V
2
Output high voltage (LVDD = min, IOH = -0.5 mA)
Output low voltage (LVDD = min, IOL = 0.5 mA)
Notes:
VOH
VOL
1.35
—
—
—
—
0.40
V
1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 5.
2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
3.11.7.2 IEEE 1588 AC timing specifications
This table provides the IEEE 1588 AC timing specifications.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
151
Electrical characteristics
Table 67. IEEE 1588 AC timing specifications5
Parameter/Condition
Symbol
tT1588CLK
tT1588CLKH
tT1588CLK
TSEC_1588_CLK_IN peak-to-peak jitter tT1588CLKINJ
Min
Typ
Max
Unit
Notes
1, 3
TSEC_1588_CLK_IN clock period
TSEC_1588_CLK_IN duty cycle
5.0
40
—
TRX_CLK x 7 ns
/
50
60
%
2
—
—
—
250
2.0
ps
ns
—
—
Rise time TSEC_1588_CLK_IN
(20%-80%)
tT1588CLKINR
tT1588CLKINF
tT1588CLKOUT
1.0
Fall time TSEC_1588_CLK_IN
(80%-20%)
1.0
5.0
30
—
—
50
—
2.0
—
ns
ns
%
—
4
TSEC_1588_CLK_OUT clock period
TSEC_1588_CLK_OUT duty cycle
tT1588CLKOTH
/
70
3.0
—
—
tT1588CLKOUT
TSEC_1588_PULSE_OUT1/2,
TSEC_1588_ALARM_OUT1/2
TSEC_1588_TRIG_IN1/2 pulse width
Notes:
tT1588OV
0.5
ns
tT1588TRIGH
2 x tT1588CLK_MAX
—
—
ns
3
1. TRX_CLK is the maximum clock period of the ethernet receiving clock selected by TMR_CTRL[CKSEL]. See the chip
reference manual for a description of TMR_CTRL registers.
2. This needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the chip reference
manual for a description of TMR_CTRL registers.
3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK will be 2800, 280, and 56 ns, respectively.
4. There are three input clock sources for 1588: TSEC_1588_CLK_IN, RTC, and MAC clock / 2. When using
TSEC_1588_CLK_IN, the minimum clock period is 2 x tT1588CLK
.
5. For recommended operating conditions, see Table 5.
This figure shows the data and command output AC timing diagram.
tT1588CLKOUT
tT1588CLKOUTH
TSEC_1588_CLK_OUT
tT1588OV
TSEC_1588_PULSE_OUT1/2
TSEC_1588_ALARM_OUT1/2
Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting.
Otherwise, it is counted starting at the falling edge.
Figure 28. IEEE 1588 output AC timing
This figure shows the data and command input AC timing diagram.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
152
NXP Semiconductors
Electrical characteristics
tT1588CLK
tT1588CLKH
TSEC_1588_CLK_IN
TSEC_1588_TRIG_IN1/2
tT1588TRIGH
Figure 29. IEEE 1588 input AC timing
3.12 QUICC engine specifications
The rise/fall time on QUICC engine block input pins should not exceed 5 ns. This should
be enforced especially on clock signals. Rise time refers to signal transitions from 10% to
90% of VDD. Fall time refers to transitions from 90% to 10% of VDD.
3.12.1 HDLC interface
This section describes the DC and AC electrical specifications for the high-level data link
control (HDLC) interface.
3.12.1.1 HDLC and Synchronous UART DC electrical characteristics
This table provides the DC electrical characteristics for the HDLC and Synchronous
UART protocols when DVDD = 3.3 V.
Table 68. HDLC and Synchronous UART DC electrical characteristics (DVDD = 3.3 V)3
Parameter
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
0.7 x DVDD
—
V
1
VIL
—
—
2.4
—
0.2 x DVDD
V
1
Input current (VIN = 0 V or VIN = DVDD
)
IIN
50
—
μA
V
2
Output high voltage (DVDD = min, IOH = -2 mA)
Output low voltage (DVDD = min, IOH = 2 mA)
Notes:
VOH
VOL
—
—
0.4
V
1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 5.
2. The symbol VIN, in this case, represents the input voltage of the supply referenced in Table 5.
3. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for the HDLC and Synchronous
UART protocols when DVDD = 1.8 V.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
153
Electrical characteristics
Table 69. HDLC and Synchronous UART DC electrical characteristics (DVDD = 1.8 V)3
Parameter
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
0.7 x DVDD
—
V
1
VIL
IIN
—
0.2 x DVDD
V
1
Input current (VIN = 0 V or VIN = DVDD
)
—
50
—
μA
V
2
Output high voltage (DVDD = min, IOH = -0.5 mA) VOH
1.35
—
—
—
Output low voltage (DVDD = min, IOH = 0.5 mA)
VOL
0.4
V
Notes:
1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 5.
2. The symbol VIN, in this case, represents the input voltage of the supply referenced in Table 5.
3. For recommended operating conditions, see Table 5.
3.12.1.2 HDLC and Synchronous UART AC timing specifications
This table provides the input and output AC timing specifications for HDLC and
Synchornous UART protocols.
Table 70. HDLC AC timing specifications2
Parameter
Outputs-Internal clock delay
Symbol
tHIKHOV
Min
Max
Unit
Notes
0
5.5
10.5
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
1
Outputs-External clock delay
tHEKHOV
tHIKHOX
tHEKHOX
tHIIVKH
1
1
Outputs-Internal clock High Impedance
Outputs-External clock High Impedance
Inputs-Internal clock input setup time
Inputs-External clock input setup time
Inputs-Internal clock input Hold time
Inputs-External clock input hold time
Notes:
0
1
1
1
10
4
—
—
—
—
—
tHEIVKH
tHIIXKH
—
0
—
tHEIXKH
1
—
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. For recommended operating conditions, see Table 5.
This table provides the input and output AC timing specifications for the synchronous
UART protocols.
Table 71. Synchronous UART AC timing specifications2
Parameter
Outputs-Internal clock delay
Symbol
tHIKHOV
tHEKHOV
tHIKHOX
Min
Max
Unit
Notes
0
1
0
11
14
11
ns
ns
ns
1
1
1
Outputs-External clock delay
Outputs-Internal clock High Impedance
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
154
NXP Semiconductors
Electrical characteristics
Table 71. Synchronous UART AC timing specifications2
(continued)
Parameter
Outputs-External clock High Impedance
Inputs-Internal clock input setup time
Inputs-External clock input setup time
Inputs-Internal clock input Hold time
Inputs-External clock input hold time
Notes:
Symbol
tHEKHOX
Min
Max
Unit
Notes
1
14
—
—
—
—
ns
ns
ns
ns
ns
1
tHIIVKH
tHEIVKH
tHIIXKH
tHEIXKH
10
8
—
—
—
—
0
1
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. For recommended operating conditions, see Table 5.
This figure shows the AC test load.
Output
OVDD/2
Z0= 50 Ω
RL = 50 Ω
Figure 30. AC test load
These figures represent the AC timing from Table 70 and Table 71. Note that, although
the specifications generally reference the rising edge of the clock, these AC timing
diagrams also apply when the falling edge is the active edge.
This figure shows the timing with an external clock.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
155
Electrical characteristics
Serial CLK (input)
tHEIXKH
tHEIVKH
Input Signals:
(see Note)
tHEKHOV
Output Signals:
(see Note)
tHEKHOX
Note: The clock edge is selectable.
Figure 31. AC timing (external clock) diagram
This figure shows the timing with an internal clock.
Serial CLK (output)
tHIIXKH
tHIIVKH
Input Signals:
(see Note)
tHIKHOV
Output Signals:
(see Note)
tHIKHOX
Note: The clock edge is selectable.
Figure 32. AC timing (internal clock) diagram
3.12.2 Time-division-multiplexed and serial interface (TDM/SI)
This section describes the DC and AC electrical specifications for the TDM/SI.
3.12.2.1 TDM/SI DC electrical characteristics
This table provides the TDM/SI DC electrical characteristics when DVDD = 3.3 V.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
156
NXP Semiconductors
Electrical characteristics
Table 72. TDM/SI DC electrical characteristics (DVDD = 3.3 V)3
Parameter
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
0.7 x DVDD
—
V
1
VIL
—
—
2.4
—
0.2 x DVDD
V
1
Input current (VIN = 0 V or VIN = DVDD
)
IIN
50
—
μA
V
2
Output high voltage (DVDD = min, IOH = -2 mA)
Output low voltage (DVDD = min, IOH = 2 mA)
Notes:
VOH
VOL
—
—
0.4
V
1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 5.
2. The symbol VIN, in this case, represents the input voltage of the supply referenced in Table 5.
3. For recommended operating conditions, see Table 5.
This table provides the TDM/SI DC electrical characteristics when DVDD = 1.8 V.
Table 73. TDM/SI DC electrical characteristics (DVDD = 1.8 V)3
Parameter
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
0.7 x DVDD
—
V
1
VIL
IIN
—
0.2 x DVDD
V
1
Input current (VIN = 0 V or VIN = DVDD
)
—
50
—
μA
V
2
Output high voltage (DVDD = min, IOH = -0.5 mA) VOH
1.35
—
—
—
Output low voltage (DVDD = min, IOH = 0.5 mA)
VOL
0.4
V
Notes:
1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 5.
2. The symbol VIN, in this case, represents the input voltage of the supply referenced in Table 5.
3. For recommended operating conditions, see Table 5.
3.12.2.2 TDM/SI AC timing specifications
This table provides the TDM/SI input and output AC timing specifications.
Table 74. TDM/SI AC timing specifications 1
Parameter
TDM/SI outputs-External clock delay
TDM/SI outputs-External clock High Impedance
TDM/SI inputs-External clock input setup time
TDM/SI inputs-External clock input hold time
Notes:
Symbol 1
Min
Max
Unit
tSEKHOV
2
2
5
2
12.75
10
ns
ns
ns
ns
tSEKHOX
tSEIVKH
tSEIXKH
—
—
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
157
Electrical characteristics
This figure shows the AC test load for the TDM/SI.
Output
OVDD/2
Z0= 50 Ω
RL = 50 Ω
Figure 33. TDM/SI AC test load
This figure represents the AC timing from Table 74. Note that, although the
specifications generally reference the rising edge of the clock, these AC timing diagrams
also apply when the falling edge is the active edge.
This figure shows the TDM/SI timing with an external clock.
TDM/SICLK (input)
tSEIXKH
tSEIVKH
Input Signals:
TDM/SI
(see Note)
tSEKHOV
Output Signals:
TDM/SI
(see Note)
tSEKHOX
Note: The clock edge is selectable on TDM/SI.
Figure 34. TDM/SI AC timing (external clock) diagram
3.13 USB 3.0 interface
This section describes the DC and AC electrical specifications for the USB 3.0 interface.
3.13.1 USB 3.0 PHY transceiver supply DC voltage
This table provides the DC electrical characteristics for the USB 3.0 interface when
operating at USB_HVDD = 3.3 V.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
158
NXP Semiconductors
Electrical characteristics
Table 75. USB 3.0 PHY transceiver supply DC voltage (USB_HVDD = 3.3 V)3
Parameter
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
2.0
—
—
V
V
V
V
1
VIL
0.8
—
1
Output high voltage (USB_HVDD = min, IOH = -2 mA)
Output low voltage (USB_HVDD = min, IOL = 2 mA)
Notes:
VOH
VOL
2.8
—
—
—
0.3
1. The min VILand max VIH values are based on the respective min and max USB_HVIN values found in Table 5.
2. The symbol USB_HVIN, in this case, represents the USB_HVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
3.13.2 USB 3.0 DC electrical characteristics
This table provides the USB 3.0 transmitter DC electrical characteristics at package pins.
Table 76. USB 3.0 transmitter DC electrical characteristics1
Characteristic
Differential output voltage
Symbol
Min
Nom
1000
Max
1200
Unit
mVp-p
Vtx-diff-pp
800
Low power differential output voltage
Tx de-emphasis
Vtx-diff-pp-low 400
—
1200
4
mVp-p
dB
Vtx-de-ratio
ZdiffTX
3
—
Differential impedance
72
18
—
100
—
120
30
Ohm
Ohm
mV
Tx common mode impedance
Absolute DC common mode voltage between U1 and U0
RTX-DC
TTX-CM-DC-
—
200
ACTIVEIDLE-
DELTA
DC electrical idle differential output voltage
VTX-IDLE-
0
—
10
mV
DIFF-DC
Note:
1. For recommended operating conditions, see Table 5.
This table provides the USB 3.0 receiver DC electrical characteristics at the Rx package
pins.
Table 77. USB 3.0 receiver DC electrical characteristics
Characteristic
Differential Rx input impedance
Symbol
Min
Nom
100
Max
Unit
Ohm
Notes
RRX-DIFF-DC 72
120
30
—
—
—
Receiver DC common mode impedance
RRX-DC
18
25 K
—
—
Ohm
Ohm
DC input CM input impedance for V > 0 during
reset or power down
ZRX-
HIGH-IMP-
DC
—
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
159
Electrical characteristics
Table 77. USB 3.0 receiver DC electrical characteristics (continued)
Characteristic
Symbol
Min
Nom
Max
Unit
Notes
LFPS detect threshold
VRX-IDLE- 100
DET-DC-
—
300
mV
1
DIFFpp
Note:
1. Below the minimum is noise. Must wake up above the maximum.
3.13.3 USB 3.0 AC timing specifications
This table provides the USB 3.0 transmitter AC timing specifications at package pins.
Table 78. USB 3.0 transmitter AC timing specifications1
Parameter
Symbol
Min
Nom
Max
Unit
Gb/s
Notes
Speed
—
—
5.0
—
—
—
—
—
—
—
2
Transmitter eye
Unit interval
tTX-Eye
UI
0.625
199.94
75
UI
ps
nF
200.06
200
AC coupling capacitor
AC
—
coupling
capacitor
Note:
1. For recommended operating conditions, see Table 5.
2. UI does not account for SSC-caused variations.
This table provides the USB 3.0 receiver AC timing specifications at Rx package pins.
Table 79. USB 3.0 receiver AC timing specifications1
Parameter
Symbol
UI
Min
199.94
Nom
Max
200.06
Unit
Notes
Unit interval
—
ps
2
Notes:
1. For recommended operating conditions, see Table 5.
2. UI does not account for SSC-caused variations.
3.13.4 USB 3.0 reference clock requirements
USB 3.0 SSPHY needs a reference clock. There are two options for the reference clock:
SYSCLK or DIFF_SYSCLK/DIFF_SYSCLK_B.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
160
NXP Semiconductors
Electrical characteristics
This table summarizes the requirements of the reference clock provided to the USB 3.0
SSPHY. 100 MHz reference clock is required with the following specifications:
Table 80. Reference clock requirements4
Parameter
Symbol
Min
Typ
Max
Unit
ppm
Notes
Reference clock frequency offset
FREF_OFFSET
-300
—
—
—
—
300
3
—
Reference clock random jitter (RMS) RMSJREF_CLK
ps
ps
1, 2
3
Reference clock deterministic jitter
DJREF_CLK
—
150
Notes:
1. 1.5 MHz to Nyquist frequency. For 100 MHz reference clock, the Nyquist frequency is 50 MHz.
2. The peak-to-peak Rj specification is calculated as 14.069 times the RMS Rj for 10-12 BER.
3. DJ across all frequencies.
4. SYSCLK or DIFF_SYSCLK/DIFF_SYSCLK_B must meet the clock specification mentioned in this table when used as a
clock source for USB PHY.
3.13.5 USB 3.0 LFPS specifications
This table provides the key LFPS electrical specifications at the transmitter.
Table 81. LFPS electrical specifications at the transmitter
Parameter
Symbol
tPeriod
VTX-DIFF-PP-LFPS
Min
Typ
Max
Unit
Notes
Period
Peak-to-peak differential amplitude
20
—
—
—
100
ns
—
800
1200
600
mV
mV
—
—
Low-power peak-to-peak differential VTX-DIFF-PP-LFPS-LP 400
amplitude
Rise/fall time
Duty cycle
Note:
tRiseFall20-80
Duty cycle
—
—
—
4
ns
%
1
1
40
60
1. Measured at compliance TP1. See Figure 35 for details.
This figure shows the Tx normative setup with reference channel as per USB 3.0
specifications.
SMP
Measurement Tool
Reference Test Channel
Reference Cable
DUT
TP1
Figure 35. Tx normative setup
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
161
Electrical characteristics
3.14 Integrated Flash Controller
This section describes the DC and AC electrical specifications for the integrated flash
controller.
3.14.1 IFC DC electrical characteristics
This table provides the DC electrical characteristics for the IFC when operating at
OVDD= 1.8 V.
Table 82. IFC DC electrical characteristics (1.8 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
Note
VIH
VIL
IIN
1.2
—
—
V
1
1
2
Input low voltage
Input current
0.6
V
—
50
µA
(VIN = 0 V or VIN = OVDD
Output high voltage
)
VOH
1.6
—
—
V
V
—
—
(OVDD = min, IOH = -0.5 mA)
Output low voltage
(OVDD = min, IOL = 0.5 mA)
Notes:
VOL
0.32
1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 5.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
3.14.2 Integrated Flash Controller AC Timing Specifications
This section describes the AC timing specifications for the integrated flash controller.
3.14.2.1 Test Condition
Figure below provides the AC test load for the integrated flash controller.
Figure 36. Integrated Flash Controller AC Test Load
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
162
NXP Semiconductors
Electrical characteristics
3.14.2.2 IFC AC Timing Specifications (GPCM/GASIC)
Table below describes the input AC timing specifications of the IFC-GPCM and IFC-
GASIC interface.
Table 83. Integrated Flash Controller Input Timing Specifications for GPCM and GASIC
mode (OVDD = 1.8 V)1
Parameter
Symbol
tIBIVKH1
tIBIXKH1
Min
Max
Unit
Notes
Input setup
Input hold
NOTE:
4
1
-
-
ns
ns
-
-
1. For recommended operating conditions, see Table 5
Figure below shows the input AC timing diagram for IFC-GPCM, IFC-GASIC interface.
IFC_CLK[0]
tIBIXKH1
tIBIVKH 1
Input Signals
Figure 37. IFC-GPCM, IFC-GASIC Input AC Timings
Table below describes the output AC timing specifications of IFC-GPCM and IFC-
GASIC interface .
Table 84. Integrated Flash Controller IFC-GPCM and IFC-GASIC interface Output Timing
Specifications (OVDD = 1.8 V)2
Parameter
IFC_CLK cycle time
Symbol
Min
Max
Unit
Notes
tIBK
10
45
-
-
ns
%
-
IFC_CLK duty cycle
Output delay
tIBKH/ tIBK
tIBKLOV1
tIBKLOX
55
1.5
-2
-
ns
ns
ps
-
Output hold
-
1
-
IFC_CLK[0] to IFC_CLK[m] skew
NOTE:
tIBKSKEW
0
75
1. Output hold is negative. This means that output transition happens earlier than the falling edge of IFC_CLK.
2. For recommended operating conditions, see Table 5
Figure below shows the output AC timing diagram for IFC-GPCM, IFC-GASIC
interface.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
163
Electrical characteristics
IFC_CLK_0
tIBKLOV1
tIBKLOX
Output Signals
Figure 38. IFC-GPCM, IFC-GASIC Signals
3.14.2.3 IFC AC Timing Specifications (NOR)
Table below describes the input timing specifications of the IFC-NOR interface.
Table 85. Integrated Flash Controller Input Timing Specifications for NOR mode (OVDD = 1.8
V)2
Parameter
Symbol
tIBIVKH2
tIBIXKH2
Min
Max
Unit
Notes
Input setup
Input hold
(2 x tIP_CLK) + 2
(1 x tIP_CLK) + 1
-
-
ns
ns
1
1
NOTE
1. tIP_CLK is the period of ip clock (not the IFC_CLK) on which IFC is running.
2. For recommended operating conditions, see Table 5.
Figure below shows the AC input timing diagram for input signals of IFC-NOR interface.
Here TRAD is a programmable delay parameter, refer to IFC section of for more
information.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
164
NXP Semiconductors
Electrical characteristics
(TRAD+1) x tIP_CLK
OE_B
tIBIXKH2
tIBIVKH2
AD (Data Phase, Read)
Figure 39. IFC-NOR Interface Input AC Timings
Table below describes the output AC timing specifications of IFC-NOR interface .
Table 86. Integrated Flash Controller IFC-NOR Interface Output Timing Specifications (OVDD
= 1.8 V)2
Parameter
Symbol
tIBKLOV2
Min
Max
Unit
Notes
Output delay
-
1.5
ns
1
NOTE:
1. This effectively means that a signal change may appear anywhere within tIBKLOV2 (max) duration, from the point where it's
expected to change.
2. For recommended operating conditions, see Table 5
Figure below shows the AC timing diagram for output signals of IFC-NOR interface. The
timing specs have been illustrated here by taking timings between two signals, CS_B and
OE_B as an example. In a read operation, OE_B is suppose to change TACO (a
programmable delay, refer to IFC section of for more information) time after CS_B.
Because of skew between the signals, OE_B may change anywhere within time window
defined by tIBKLOV2. This concept applies to other output signalsof IFC-NOR interface
as well. The diagram is an example to show the skew between any two chronological
toggling signals as per the protocol. Here is the list of IFC-NOR output signals NRALE,
NRAVD_B, NRWE_B, NROE_B, CS_B, AD(Address phase).
CS_B
TACO
tIBKLOV2
OE_B
Figure 40. IFC-NOR Interface Output AC Timings
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
165
Electrical characteristics
3.14.2.4 IFC AC Timing Specifications (NAND)
Table below describes the input timing specifications of the IFC-NAND interface.
Table 87. Integrated Flash Controller Input Timing Specifications for NAND mode (OVDD
1.8 V)2
=
Parameter
Symbol
tIBIVKH3
tIBIXKH3
tIBCH
Min
Max
Unit
Notes
Input setup
Input hold
(2 x tIP_CLK) + 2
-
-
-
ns
ns
1
1
1
1
2
IFC_RB_B pulse width
tIP_CLK
NOTE:
1. tIP_CLK is the period of ip clock on which IFC is running.
2. For recommended operating conditions, see
Figure below shows the AC input timing diagram for input signals of IFC-NAND
interface. Here TRAD is a programmable delay parameter, refer to IFC section of for
more information.
Figure 41. IFC-NAND Interface Input AC Timings
NOTE
tIP_CLK is the period of ip clock (not the IFC_CLK) on which
IFC is running.
Table below describes the output AC timing specifications of IFC-NAND interface.
Table 88. Integrated Flash Controller IFC-NAND Interface Output Timing Specifications
(OVDD = 1.8 V)2
Parameter
Symbol
tIBKLOV3
Table continues on the next page...
Min
Max
Unit
Notes
Output delay
-
1.5
ns
1
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
166
NXP Semiconductors
Electrical characteristics
Table 88. Integrated Flash Controller IFC-NAND Interface Output Timing Specifications
(OVDD = 1.8 V)2 (continued)
Parameter
Symbol
Min
Max
Unit
Notes
NOTE:
1. This effectively means that a signal change may appear anywhere within tIBKLOV3 (min) to tIBKLOV3 (max) duration, from the
point where it's expected to change.
2. For recommended operating conditions, see Table 5
Figure below shows the AC timing diagram for output signals of IFC-NAND
interface.The timing specs have been illustrated here by taking timings between two
signals, CS_B and CLE as an example. CLE is suppose to change TCCST (a
programmable delay, refer to IFC section of for more information) time after CS_B.
Because of skew between the signals CLE may change anywhere within time window
defined by tIBKLOV3. This concept applies to other output signals of IFC-NAND interface
as well. The diagram is an example to show the skew between any two chronological
toggling signals as per the protocol. Here is the list of output signals NDWE_B,
NDRE_B, NDALE, WP_B, NDCLE, CS_B, AD.
Figure 42. IFC-NAND Interface Output AC Timings
3.14.2.5 IFC-NAND SDR AC Timing Specifications
Table below describes the AC timing specifications of IFC-NAND SDR interface. These
specifications are compliant to SDR mode of ONFI specification revision 3.0.
Table 89. Integrated Flash Controller IFC-NAND SDR Interface AC Timing Specifications
(OVDD = 1.8 V)
Parameter
Symbol
I/O Min
Max
Unit
Notes Fig
Figure 43
Address cycle to data tADL
loading time
O
TADLE - 1500(ps)
TADLE + 1500(ps) tIP_CLK
ALE hold time
tALH
tALS
tAR
O
O
O
O
TWCHT - 1500(ps)
TWP - 1500(ps)
TWHRE - 1500(ps)
5 + 1500(ps)
TWCHT + 1500(ps) tIP_CLK
Figure 44
Figure 44
Figure 45
Figure 44
ALE setup time
ALE to RE_n delay
CE_n hold time
TWP + 1500(ps)
TWHRE + 1500(ps) tIP_CLK
- ns
tIP_CLK
tCH
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
167
Electrical characteristics
Table 89. Integrated Flash Controller IFC-NAND SDR Interface AC Timing Specifications
(OVDD = 1.8 V) (continued)
CE_n high to input hi-Z tCHZ
I
TRHZ - 1500(ps)
TWCHT - 1500(ps)
TWHRE - 1500(ps)
TWP - 1500(ps)
150 - 1500(ps)
TRHZ + 1500(ps)
tIP_CLK
Figure 46
Figure 44
Figure 47
Figure 44
Figure 46
CLE hold time
tCLH
tCLR
tCLS
tCOH
O
O
O
I
TWCHT + 1500(ps) tIP_CLK
TWHRE - 1500(ps) tIP_CLK
CLE to RE_n delay
CLE setup time
TWP + 1500(ps)
-
tIP_CLK
ns
CE_n high to input
hold
CE_n setup time
Data hold time
Data setup time
tCS
O
O
O
O
TCS - 1500(ps)
TWCHT - 1500(ps)
TWP - 1500(ps)
-
TCS + 1500(ps)
tIP_CLK
Figure 44
Figure 44
Figure 44
Figure 48
tDH
TWCHT + 1500(ps) tIP_CLK
tDS
TWP + 1500(ps)
FTOCNT
tIP_CLK
tIP_CLK
Busy time for Set
Features and Get
Features
tFEAT
Output hi-Z to RE_n
low
tIR
O
O
O
TWHRE - 1500(ps)
TWHRE + 1500(ps) tIP_CLK
Figure 49
Figure 48
Figure 46
Interface and Timing
Mode Change time
tITC
tRC
-
FTOCNT
tIP_CLK
tIP_CLK
RE_n cycle time
TRP + TREH - 1500(ps)
TRP + TREH +
1500(ps)
RE_n access time
tREA
I
I
I
-
(TRAD - 1) + 2(ns) tIP_CLK
Figure 46
Figure 46
Figure 46
RE_n high hold time
tREH
TREH
0
TREH
-
tIP_CLK
ns
RE_n high to input
hold
tRHOH
RE_n high to WE_n
low
tRHW
O
100 + 1500(ps)
-
ns
Figure 50
RE_n high to input hi-Z tRHZ
I
I
TRHZ - 1500(ps)
0
TRHZ + 1500(ps)
-
tIP_CLK
ns
Figure 46
Figure 51
RE_n low to input data tRLOH
hold
RE_n pulse width
tRP
tRR
O
O
TRP
TRP
tIP_CLK
tIP_CLK
Figure 46
Figure 46
Ready to data input
cycle (data only)
TRR - 1500(ps)
TRR + 1500(ps)
Device reset time,
measured from the
falling edge of R/B_n
to the rising edge of R/
B_n.
tRST (raw
NAND)
O
O
O
-
FTOCNT
tIP_CLK
tIP_CLK
tIP_CLK
Figure 52
Figure 52
Figure 44
Device reset time,
measured from the
falling edge of R/B_n
to the rising edge of R/
B_n.
tRST2 (EZ
NAND)
-
FTOCNT
(WE_n high or CLK
rising edge) to SR[6]
low
tWB
TWBE + TWH - 1500(ps)
TWBE + TWH +
1500(ps)
WE_n cycle time
tWC
tWH
O
O
TWP + TWH
TWH
TWP + TWH
TWH
tIP_CLK
tIP_CLK
Figure 53
Figure 53
WE_n high hold time
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
168
NXP Semiconductors
Electrical characteristics
Table 89. Integrated Flash Controller IFC-NAND SDR Interface AC Timing Specifications
(OVDD = 1.8 V) (continued)
Command, address, or tWHR
data input cycle to data
output cycle
O
TWHRE + TWH - 1500(ps) TWHRE + TWH + tIP_CLK
1500(ps)
Figure 54
WE_n pulse width
tWP
O
O
TWP
TWP
tIP_CLK
tIP_CLK
Figure 44
Figure 55
WP_n transition to
command cycle
tWW
TWW - 1500(ps)
TWW + 1500(ps)
Data Input hold
tIBIXKH4
I
1
-
tIP_CLK
Figure 56
NOTE:
1. tIP_CLK is the clock period of IP clock (on which IFC IP is running). Note that that the IFC IP clcok doesn't come out of
device.
WE_B
RE_B
tADL
Cycle type
DATA
ADDR
Figure 43. tADL Timing
tCLH
CLE
tCLS
tCH
tCS
CE_n
WE_n
tWP
tALS
tALH
ALE
tDS
tDH
Command
IO0-7
R/B_n
tWB
Figure 44. Command Cycle
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
169
Electrical characteristics
ALE
tAR
RE_n
Figure 45. tAR Timings
tCHZ
tCEA
CE_n
RE_n
R/B_n
tCOH
tRP
tRP
tRP
tRHOH
tRHZ
tREH
tRR
tRC
tRHZ
tRHZ
tRHZ
tREA
tREA
tREA
D0
D1
Dn
IOx
Figure 46. Data Input Cycle Timings
CLE
tCLR
RE_n
Figure 47. tCLR Timings
RE_B
Cycle type
RB_B
DATA
DATA
DATA
CMD
ADDR
tWB
tRR
tFEAT/tITC
Figure 48. tWB, tFEAT, tITC, tRR Timings
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
170
NXP Semiconductors
Electrical characteristics
tCLR
CLE
tCLH
tCH
tCLS
tCS
tCEA
CE_n
WE_n
tWP
tCHZ
tCOH
tWHR
RE_n
IO7-0
tRHZ
tDS
tDH
tRHOH
70h
Status
tIR
tREA
Figure 49. Read StatusTimings
CLK
CLE
WR_B
Cycle type
DIN
CMD
tRHW
Figure 50. tRHW Timings
tCHZ
CE_n
RE_n
tCOH
tRP
tREH
tRR
tRC
tRHZ
tREA
tREA
R/B_n
IOx
tRHOH
tRLOH
D0
D1
Dn
tCEA
Figure 51. EDO Mode Data Input CycleTimings
WE_B
Cycle type
RB_B
CMD
tWB
tRST
Figure 52. tWB, tRST Timings
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
171
Electrical characteristics
tCLS
CLE
tCS
CE_n
WE_n
ALE
tWC
tWP
tWH
tALS
tALH
tDH
tDS
IO0-7
Address
Figure 53. Address Latch Timings
WE_n
tWHR
RE_n
Figure 54. tWHR Timings
WP_B
tWW
CLE_B
Figure 55. tWW Timings
Figure 56. tIBIXKH4 Timings
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
172
NXP Semiconductors
Electrical characteristics
3.14.2.6 IFC-NAND NVDDR AC Timing Specification
Table below describes the AC timing specifications of IFC-NAND NVDDR interface.
These specifications are compliant to NVDDR mode of ONFI specification revision 3.0.
Table 90. Integrated Flash Controller IFC-NAND NVDDR Interface AC Timing Specifications
(OVDD = 1.8 V)
Parameter
Symbol
tAC
I/O Min
Max
Unit
ns
Notes
Fig
Access window of DQ[7:0]
from CLK
I
3 - 150 (ps) 20 + 150
(ps)
Figure 60
Address cycle to data
loading time
tADL
I
TADL
-
tIP_CL
Figure 61
Figure 57
K
Command, Address, Data
delay (command to
command, address to
address, command to
address, address to
command, command/
address to start of data)
Fast
tCADf
O
TCAD -
150 (ps)
TCAD + 150 tIP_CL
(ps)
K
Command, Address, Data
delay (command to
command, address to
address, command to
address, address to
command, command/
address to start of data)
slow
tCADs
O
TCAD -
150 (ps)
TCAD + 150 tIP_CL
Figure 57
(ps)
K
Command/address DQ hold tCAH
time
O
O
O
O
O
O
O
2 + 150
(ps)
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Figure 57
Figure 57
Figure 57
Figure 57
Figure 57
Figure 57
Figure 57
CLE and ALE hold time
tCALH
tCALS
tCAS
tCH
2 + 150
(ps)
CLE and ALE setup time
2 + 150
(ps)
Command/address DQ
setup time
2 + 150
(ps)
CE# hold time
2 + 150
(ps)
Average clock cycle time,
also known as tCK
tCK(avg)
or tCK
10
Absolute clock period,
measured from rising edge
to the next consecutive
rising edge
tCK(abs)
tCK(avg) + tCK(avg) + ns
tJIT(per)
min
tJIT(per)
max
Clock cycle high
tCKH(abs O 0.45
)
0.55
0.55
tCK
tCK
Figure 57
Figure 57
Figure 60
Clock cycle low
tCKL(abs O 0.45
)
Data input end to W/R# high tCKWR
B16
O
TCKWR -
150 (ps)
TCKWR +
150 (ps)
tIP_CL
K
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
173
Electrical characteristics
Table 90. Integrated Flash Controller IFC-NAND NVDDR Interface AC Timing Specifications
(OVDD = 1.8 V) (continued)
CE# setup time
tCS
O
TCS - 150 TCS + 150 tIP_CL
Figure 59
(ps)
1050
-
(ps)
K
Data DQ hold time
tDH
O
I
-
ps
Figure 59
Figure 60
Access window of DQS from tDQSCK
CLK
20 + 150
(ps)
ns
W/R# low to DQS/DQ driven tDQSD
by device
I
-150 (ps)
0.45
18 + 150
(ps)
ns
Figure 60
DQS output high pulse width tDQSH
O
O
0.55
tCK
Figure 59
Figure 57
W/R# high to DQS/DQ tri-
state by device
tDQSHZ
RHZ - 150 RHZ + 150 tIP_CL
(ps)
0.45
-
(ps)
K
DQS output low pulse width tDQSL
DQS-DQ skew, DQS to last
O
I
0.55
1000
tCK
Figure 59
Figure 60
tDQSQ
ps
DQ valid, per ac cess (1.0V)
DQS-DQ skew, DQS to last
DQ valid, per access (0.9V)
930
Data output to first DQS
latching transition
tDQSS
O
0.75 + 150 1.25 - 150
tCK
Figure 59
(ps)
(ps)
Data DQ setup time
tDS
O
O
1050
-
-
ps
Figure 59
Figure 59
DQS falling edge to CLK
rising - hold time
tDSH
0.2 + 150
(ps)
tCK
DQS falling edge to CLK
rising - setup time
tDSS
O
I
0.2 + 150
(ps)
-
-
tCK
ns
Figure 59
Figure 60
Input data valid window
tDVW
tDVW =
tQH -
tDQSQ
Busy time for Set Features tFEAT
and Get Features
I
-
FTOCNT
-
tIP_CL
Figure 62
Figure 60
K
Half-clock period
tHP
O
tHP =
ns
min(tCKL,
tCKH)
Interface and Timing Mode tITC
Change time
I
-
FTOCNT
0.5
tIP_CL
Figure 62
-
K
The deviation of a given
tCK(abs) from tCK(avg)
tJIT(per)
O
I
-0.5
ns
DQ-DQS hold, DQS to first tQH
DQ to go non-valid, per
access
tQH = tHP - -
tQHS
tIP_CL
Figure 60
K
Data hold skew factor
tQHS
I
-
1 + 150(ps) ns
-
Data input cycle to
command, address, or data
output cycle
tRHW
O
TRHW
-
tIP_CL
Figure 63
K
Ready to data input cycle
(data only)
tRR
I
TRR
-
tIP_CL
Figure 62
K
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
174
NXP Semiconductors
Electrical characteristics
Table 90. Integrated Flash Controller IFC-NAND NVDDR Interface AC Timing Specifications
(OVDD = 1.8 V) (continued)
Device reset time,
tRST (raw O FTOCNT
NAND)
FTOCNT
tIP_CL
Figure 64
measured from the falling
edge of R/B# to the rising
edge of R/B#.
K
Device reset time,
tRST2
(EZ
NAND)
O
FTOCNT
FTOCNT
tIP_CL
Figure 64
measured from the falling
edge of R/B# to the rising
edge of R/B#.
K
CLK rising edge to SR[6]
low
tWB
O
O
TWB - 150 TWB + 150 tIP_CL
Figure 64
Figure 65
(ps)
(ps)
K
Command, address or data tWHR
output cycle to data input
cycle
TWHR
-
tIP_CL
K
DQS write preamble
DQS write postamble
tWPRE
tWPST
O
O
I
1.5
1.5
-
-
tCK
tCK
Figure 59
Figure 59
Figure 60
W/R# low to data input cycle tWRCK
TWRCK -
150 (ps)
TWRCK +
150 (ps)
tIP_CL
K
WP# transition to command tWW
cycle
O
TWW - 150 TWW + 150 tIP_CL
(ps) (ps)
Figure 66
K
NOTE:
1. tIP_CLK is the clock period of IP clock (on which IFC IP is running). Note that that the IFC IP clcok doesn't come out
of device.
Following diagrams show the AC timing diagram for IFC-NAND NVDDR interface.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
175
Electrical characteristics
tCH
CE_B
tCALS
tCALS
CLE
ALE
CLK
tCALS tCALH
tCKL tCKH
tCK
tCALS
tCALH
W/R_B
DQS
tDQSHZ
tCAS
tCAH
DQ[7:0]
Command
Figure 57. Command Cycle
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
176
NXP Semiconductors
Electrical characteristics
tCH
CE#
tCALS
tCALS
CLE
ALE
CLK
tCALS tCALH
tCKL tCKH
tCK
tCALS
tCALH
W/R#
DQS
tCAS
tCAH
DQ[7:0]
Address
Figure 58. Address Cycle
tCH
CE#
CLE
ALE
tCALS
tCAD
tCALH
tCALS
tCKH
tCKL
tCALH
CLK
tCK
W/R#
DQS
tDSS
tDSS
tDSH
tDSS
tDSH
tDQSH
tDQSS tDSH
tDSH
tDQSH
tDQSL
tDQSL
tDQSH
DN
D
D
D
D
DN-2
D3
DQ[7:0]
1
2
0
N-1
tDS
tDS
tDH
tDH
Figure 59. Write Cycle
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
177
Electrical characteristics
tCH
CE_B
CLE
tCAL
H
tCALS
tCALS
ALE
tCKH
tCALH
tHP
tCKL
tCK
tHP
tHP
tHP
tHP
tHP
CLK
tCALS
tDSC
W/R_B
DQS
tDQSHZ
tCALS
tDQSD
tDVW
tDVW
tDVW tDVW
tDVW
DQ[7:0]
D
0
D
1
D
D
D
0
D
0
D
0
D
0
2
3
tDQSQ
tDQSQ
tDQSQ
tDQSQ
tQH tQH
tQH
tQH
Don’t Care
DataTransitioning
DeviceDriving
Figure 60. Read Cycle
CLK
CLE
ALE
tADL
Cycle type
DATA
ADDR
Figure 61. tADL Timings
CLK
ALE
WR_B
Cycle type
RB_B
DATA
CMD
ADDR
tWB
tRR
tFEAT/tITC
Figure 62. tWB, tFEAT, tITC, tRR Timings
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
178
NXP Semiconductors
Electrical characteristics
CLK
CLE
WR_B
Cycle type
DIN
CMD
tRHW
Figure 63. tRHW Timings
CLK
CLE
ALE
W/R#
DQ[7:0]
DQS
CMD
tWB
tRST
R/B#
Figure 64. tWB, tRST Timings
CLE
ALE
CLK
tWHR
Cycle type
DATA
CMD
Figure 65. tWHR Timings
CLK
CLE
CMD
Cycle Type
tWW
WP#
Bus shall
be idle
Figure 66. tWW Timings
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
179
Electrical characteristics
3.15 LPUART interface
This section describes the DC and AC electrical specifications for the LPUART interface.
3.15.1 LPUART DC electrical characteristics
This table provides the DC electrical characteristics for the LPUART interface when
operating at D/EVDD = 3.3 V.
Table 91. LPUART DC electrical characteristics (DVDD/EVDD = 3.3 V)2
Parameter
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
0.7 x D/
EVDD
—
V
V
1
1
VIL
—
0.2 x
D/EVDD
Input current (D/EVIN = 0 V or D/EVIN = D/EVDD
Output high voltage ( IOH = -2.0 mA)
Output low voltage ( IOL = 2.0 mA)
Notes:
)
IIN
—
50
—
μA
V
—
—
—
VOH
VOL
2.4
—
0.4
V
1. The min VIL and max VIH values are based on the min and max D/EVDD respective values found in Table 5.
2. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for the LPUART interface when
operating at D/EVDD = 1.8 V.
Table 92. LPUART DC electrical characteristics (DVDD/EVDD = 1.8 V)3
Parameter
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
0.7 x D/
EVDD
—
V
V
1
1
VIL
—
0.2 x
D/EVDD
Input current (D/EVIN = 0 V or D/EVIN = D/EVDD
)
IIN
—
50
—
μA
V
2
Output high voltage (D/EVDD = min, IOH = -0.5 mA)
Output low voltage (D/EVDD = min, IOL = 0.5 mA)
Notes:
VOH
VOL
1.35
—
—
—
0.4
V
1. The min VIL and max VIH values are based on the min and max D/EVDD respective values found in Table 5.
2. The symbol D/EVIN represents the input voltage of the supply referenced in Table 5.
3. For recommended operating conditions, see Table 5.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
180
NXP Semiconductors
Electrical characteristics
3.15.2 LPUART AC timing specifications
This table provides the AC timing specifications for the LPUART interface.
Table 93. LPUART AC timing specifications
Parameter
Value
fPLAT/(2 x 32 x 8192)
fPLAT/(2 x 4)
Unit
Notes
Minimum baud rate
Maximum baud rate
Notes:
baud
baud
1, 3, 4
1, 2, 4
1. fPLAT refers to the internal platform clock.
2. The actual attainable baud rate is limited by the latency of interrupt processing.
3. Every bit can be over sampled with a sample clock rate of 8 and 64 times (software configurable) and each bit is the
majority of the values sampled at the sample rate divided by two, (sample rate/2)+1 and (sample rate/2)+2.
4. The 1-to-0 transition during a data word can cause a resynchronization of the sample point.
3.16 DUART interface
This section describes the DC and AC electrical specifications for the DUART interface.
3.16.1 DUART DC electrical characteristics
This table provides the DC electrical characteristics for the DUART interface at
DVDD = 3.3 V.
Table 94. DUART DC electrical characteristics (3.3 V)3
Parameter
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
0.7 x DVDD
—
V
1
VIL
—
—
2.4
—
0.2 x DVDD
V
1
Input current (DVIN = 0 V or DVIN = DVDD
)
IIN
50
—
µA
V
2
Output high voltage (DVDD = min, IOH = -2.0 mA)
Output low voltage (DVDD = min, IOL = 2.0 mA)
Notes:
VOH
VOL
—
—
0.4
V
1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 5.
2. The symbol DVIN represents the input voltage of the supply referenced in Table 5.
3. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for the DUART interface at
DVDD = 1.8 V.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
181
Electrical characteristics
Table 95. DUART DC electrical characteristics (1.8 V)3
Parameter
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
0.7 x DVDD
—
V
1
VIL
—
0.2 x DVDD
V
1
Input current (DVIN = 0 V or DVIN = DVDD
)
IIN
—
50
—
µA
V
2
Output high voltage (DVDD = min, IOH = -0.5 mA)
Output low voltage (DVDD = min, IOL = 0.5 mA)
Notes:
VOH
VOL
1.35
—
—
—
0.4
V
1. The min VIL and max VIH values are based on the min and max DVIN respective values found in Table 5.
2. The symbol DVIN represents the input voltage of the supply referenced in Table 5.
3. For recommended operating conditions, see Table 5.
3.16.2 DUART AC timing specifications
This table provides the AC timing specifications for the DUART interface.
Table 96. DUART AC timing specifications
Parameter
Value
fPLAT/(2 x 1,048,576)
fPLAT/(2 x 16)
Unit
Notes
Minimum baud rate
Maximum baud rate
Notes:
baud
baud
1, 3
1, 2
1. fPLAT refers to the internal platform clock.
2. The actual attainable baud rate is limited by the latency of interrupt processing.
3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values
are sampled each 16th sample.
3.17 Flextimer interface
This section describes the DC and AC electrical characteristics for the Flextimer
interface. There are Flextimer pins on various power supplies in this device.
3.17.1 Flextimer DC electrical characteristics
This table provides the DC electrical characteristics for Flextimer pins operating at D/
EVDD = 3.3 V.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
182
NXP Semiconductors
Electrical characteristics
Table 97. Flextimer DC electrical characteristics (DVDD/EVDD = 3.3 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
IIN
0.7 x D/EVDD
—
V
1
Input low voltage
—
0.2 x D/EVDD
V
1
Input current (VIN = 0 V or VIN= D/EVDD)
Output high voltage
—
50
—
μA
V
2
VOH
2.4
—
(D/EVDD = min, IOH = -2 mA)
Output low voltage
VOL
—
0.4
V
—
(D/EVDD = min, IOL = 2 mA)
Notes:
1. The min VIL and max VIH values are based on the respective min and max DVIN/EVIN values found in Table 5.
2. The symbol VIN, in this case, represents the DVIN/EVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for Flextimer pins operating at D/
EVDD = 1.8 V.
Table 98. Flextimer DC electrical characteristics (DVDD/EVDD = 1.8 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
IIN
0.7 x D/EVDD
—
V
1
Input low voltage
—
0.2 x D/EVDD
V
1
Input current (VIN = 0 V or VIN = D/EVDD
)
—
50
—
μA
V
2
Output high voltage
VOH
1.35
—
(D/EVDD = min, IOH = -0.5 mA)
Output low voltage
VOL
—
0.4
V
—
(D/EVDD = min, IOL = 0.5 mA)
Notes:
1. The min VIL and max VIH values are based on the respective min and max DVIN/EVIN values found in Table 5.
2. The symbol VIN, in this case, represents the DVIN/EVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for Flextimer pins operating at
LVDD = 2.5 V.
Table 99. Flextimer DC electrical characteristics (2.5 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
IIN
1.7
—
—
V
1
1
2
Input low voltage
0.7
V
Input current (VIN = 0 V or VIN= LVDD
)
—
50
μA
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
183
Electrical characteristics
Table 99. Flextimer DC electrical characteristics (2.5 V)3 (continued)
Parameter
Output high voltage
Symbol
VOH
Min
Max
Unit
Notes
2.0
—
—
V
V
—
—
(LVDD = min, IOH = -1 mA)
Output low voltage
(LVDD = min, IOL = 1 mA)
Notes:
VOL
0.4
1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 5.
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for Flextimer pins operating at L/
OVDD = 1.8 V.
Table 100. Flextimer DC electrical characteristics (1.8 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
IIN
1.2
—
—
V
1
Input low voltage
0.6
V
1
Input current (VIN = 0 V or VIN = L/OVDD
)
—
50
μA
V
2
Output high voltage
VOH
1.35
—
—
(L/OVDD = min, IOH = -0.5 mA)
Output low voltage
VOL
—
0.4
V
—
(L/OVDD = min, IOL = 0.5 mA)
Notes:
1. The min VIL and max VIH values are based on the respective min and max L/OVIN values found in Table 5.
2. The symbol VIN, in this case, represents the L/OVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
3.17.2 Flextimer AC timing specifications
This table provides the Flextimer AC timing specifications.
Table 101. Flextimer AC timing specifications2
Parameter
Flextimer inputs—minimum pulse width
Notes:
Symbol
tPIWID
Min
Unit
Notes
20
ns
1
1. Flextimer inputs and outputs are asynchronous to any visible clock. Flextimer outputs should be synchronized before use
by any external synchronous logic. Flextimer inputs are required to be valid for at least tPIWID to ensure proper operation.
2. For recommended operating conditions, see Table 5.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
184
NXP Semiconductors
Electrical characteristics
This figure provides the AC test load for the Flextimer.
Output
(L/O) VDD/2
Z0= 50 Ω
RL = 50 Ω
Figure 67. Flextimer AC test load
3.18 SPI interface
This section describes the DC and AC electrical characteristics for the SPI interface.
3.18.1 SPI DC electrical characteristics
This table provides the DC electrical characteristics for the SPI interface operating at
OVDD = 1.8 V.
Table 102. SPI DC electrical characteristics (1.8 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
IIN
1.2
—
—
V
1
Input low voltage
0.6
V
1
Input current (VIN = 0 V or VIN = OVDD
)
—
50
μA
V
2
Output high voltage
VOH
1.35
—
—
(OVDD = min, IOH = -0.5 mA)
Output low voltage
VOL
—
0.4
V
—
(OVDD = min, IOL = 0.5 mA)
Notes:
1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 5.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
185
Electrical characteristics
3.18.2 SPI AC timing specifications
This table provides the SPI timing specifications.
Table 103. SPI AC timing specifications
Parameter
SCK Clock Pulse Width
Symbol
Condition
Min
Max
60%
Unit
tSCK
tSDC
tCSC
tASC
—
40%
16
16
8
CS to SCK Delay
Master
Master
Master
Master
Master
Master
—
—
—
—
7
ns
ns
ns
ns
ns
ns
After SCK Delay
Data Setup Time for Inputs
Data Hold Time for Inputs
Data Valid (after SCK edge) for Outputs
Data Hold Time for Outputs
tNIIVKH
tNIIXKH
tNIKHOV
tNIKHOX
0
—
0
—
This figure shows the SPI timing master when CPHA = 0.
tCSC
tASC
CSx
tSDC
tSCK
SCK Output
(CPOL = 0)
tSDC
SCK Output
(CPOL = 1)
tNIIXKH
tNIIVKH
SIN
First Data
Data
Last Data
tNIKHOX
tNIKHOV
SOUT
Last Data
First Data
Data
Figure 68. SPI timing master, CPHA = 0
This figure shows the SPI timing master when CPHA = 1.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
186
NXP Semiconductors
Electrical characteristics
CSx
SCK Output
(CPOL = 0)
tNIIXKH
SCK Output
(CPOL = 1)
tNIIVKH
SIN
Data
First Data
Last Data
t NIKHOX
tNIKHOV
SOUT
Last Data
Data
First Data
Figure 69. SPI timing master, CPHA = 1
3.19 QuadSPI interface
This section describes the DC and AC electrical characteristics for the QuadSPI interface.
3.19.1 QuadSPI DC electrical characteristics
This table provides the DC electrical characteristics for the QuadSPI interface operating
at OVDD = 1.8 V.
Table 104. QuadSPI DC electrical characteristics (1.8 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
IIN
1.2
—
—
V
1
Input low voltage
0.6
V
1
Input current (VIN = 0 V or VIN = OVDD
)
—
50
μA
V
2
Output high voltage
VOH
1.35
—
—
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
187
Electrical characteristics
Table 104. QuadSPI DC electrical characteristics (1.8 V)3 (continued)
Parameter
Symbol
Min
Max
Unit
Notes
(OVDD = min, IOH = -0.5 mA)
Output low voltage
(OVDD = min, IOL = 0.5 mA)
Notes:
VOL
—
0.4
V
—
1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 5.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
3.19.2 QuadSPI AC timing specifications
This section describes the QuadSPI timing specifications in SDR mode. All data is based
on a negative edge data launch from the device and a positive edge data capture, as
shown in the timing figures in this section.
3.19.2.1 QuadSPI timing SDR mode
This table provides the QuadSPI input and output timing in SDR mode.
Table 105. SDR mode QuadSPI input and output timing
Parameter
Symbol
FSCK
Min
Max
Unit
Clock frequency
Clock rise/fall time
CS output hold time
CS output delay
—
62.5
—
MHz
ns
TRISE/TFALL
tNIKHOX2
tNIKHOV2
tNIIVKH
1
-3.4
—
—
ns
3.5
—
ns
Setup time for incoming data
Hold time requirement for incoming data
Output data valid
8.6
0.4
—
ns
tNIIXKH
—
ns
tNIKHOV
tNIKLOV
tNIKHOX
tNIKLOX
4.5
ns
Output data hold
-4.4
—
ns
This figure shows the QuadSPI AC timing in SDR mode.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
188
NXP Semiconductors
Electrical characteristics
QSPI_CK_A
QSPI_CK_B
tNIIXKH
tNIIVKH
Input Signals:
tNIKHOX
tNIKHOV
Output Signals:
tNIKHOX2
tNIKHOV2
QSPI_CS_A0
QSPI_CS_A1
QSPI_CS_B0
QSPI_CS_B1
Figure 70. QuadSPI AC timing — SDR mode
3.20 Enhanced secure digital host controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC interface.
3.20.1 eSDHC DC electrical characteristics
This table provides the DC electrical characteristics for the eSDHC interface.
Table 106. eSDHC interface DC electrical characteristics3
Characteristic
Input high voltage
Input low voltage
Output high voltage
Symbol
Condition
Min
0.625 x D/EVDD
-
Max
Unit
Notes
VIH
VIL
-
-
-
V
1
1
-
0.25 x D/EVDD
-
V
V
VOH
IOH = -100 μA at
D/EVDD min
0.75 x D/EVDD
Output low voltage
Output low voltage
VOL
VOL
IOL = 100 μA at
D/EVDD min
-
0.125 x D/EVDD
V
-
IOL = 2 mA
-
-
0.3
10
V
2
2
Input/output leakage
current
IIN/IOZ
-10
μA
Notes:
1. The min VIL and max VIH values are based on the respective min and max D/EVIN values found in the Recommended
operating conditions table..
2. Open-drain mode is for MMC cards only.
3. At Recommended operating conditions with D/EVDD=3.3V.
4. Interface signals are distributed over different voltages (D/EVDD), ensure that voltage is set to 3.3V when in operation.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
189
Electrical characteristics
Table 107. eSDHC interface DC electrical characteristics (dual-voltage cards)2
Characteristic
Input high voltage
Symbol
Condition
Min
0.7 * O/D/EVDD
-
Max
Unit
Notes
VIH
VIL
-
-
-
V
1
1
-
Input low voltage
0.2 * O/D/EVDD
-
V
V
Output high voltage
VOH
IOH = -100 μA at
O/D/EVDD min
O/D/EVDD - 0.2
Output low voltage
Output low voltage
VOL
VOL
IOL = 100 μA at
O/D/EVDD min
-
0.2
V
-
IOL = 2 mA
-
-
0.3
10
V
4
4
Input/output leakage current IIN/IOZ
-10
μA
Notes:
1. The min VIL and max VIH values are based on the respective min and max O/D/EVIN values found in the Recommended
operating conditions tableReplace with xref to Recommended operating conditions table.
2. At Recommended operating conditions for 1.8V or 3.3V.
3. Interface signals are distributed over different voltages (O/D/EVDD), ensure that voltage is set to a common level when in
operation.
4. Open-drain mode is for MMC cards only.
3.20.2 eSDHC AC timing specifications
This section provides the AC timing specifications.
This table provides the eSDHC AC timing specifications as defined in Figure 71, Figure
72, and Figure 73.
Table 108. eSDHC AC timing specifications (high-speed mode)6
Parameter
SDHC_CLK clock frequency:
Symbol1
Min
Max
Unit Notes
SD/SDIO (full-
speed/high-speed
mode)
fSHSCK
0
25/50 MHz
20/52
2, 4
MMC (full-speed/
high-speed mode)
SDHC_CLK clock low time (full-speed/high-speed mode)
SDHC_CLK clock high time (full-speed/high-speed mode)
SDHC_CLK clock rise and fall times
tSHSCKL
tSHSCKH
10/7
10/7
-
-
ns
ns
ns
4
4
4
-
tSHSCKR/
tSHSCKF
tSHSIVKH
tSHSIXKH
tSHSKHOX
3
Input setup times: SDHC_CMD, SDHC_DATx to SDHC_CLK
Input hold times: SDHC_CMD, SDHC_DATx to SDHC_CLK
Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid
2.5
2.5
-3
-
ns
ns
ns
ns
3, 4, 5
4, 5
-
-
4, 5
Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid tSHSKHOV
-
3
4, 5
Notes:
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
190
NXP Semiconductors
Electrical characteristics
Table 108. eSDHC AC timing specifications (high-speed mode)6
Parameter
Symbol1
Min
Max
Unit Notes
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSHKHOX symbolizes eSDHC high-
speed mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the
invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the
clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
2. In full-speed mode, the clock frequency value can be 0-25MHz for an SD/SDIO card and 0-20MHz for an MMC card. In
high-speed mode, the clock frequency value can be 0-50MHz for an SD/SDIO card and 0-52MHz for an MMC card.
3. SDHC_SYNC_OUT/IN loop back is recommended to compensate the clock delay. In case the SDHC_SYNC_OUT/IN
loopback is not used, to satisfy setup timing, one-way board-routing delay between host and card, on SDHC_CLK,
SDHC_CMD, and SDHC_DATx should not exceed 1ns for any high-speed MMC card. For any high-speed or default speed
mode SD card, the one-way board-routing delay between host and card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx
should not exceed 1.5ns.
4. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF.
5. The parameter values apply to both full-speed and high-speed modes.
6. At recommended operating conditions with OVDD/EVDD=1.8V or 3.3V.
This figure provides the eSDHC clock input timing diagram.
eSDHC
external clock
VM
VM
VM
operational mode
tSHSCKL
tSHSCKH
tSHSCK
tSHSCKR
tSHSCKF
VM = Midpoint voltage (OVDD/2)
Figure 71. eSDHC clock input timing diagram
This figure provides the input AC timing diagram for high-speed mode.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
191
Electrical characteristics
VM
VM
VM
VM
SDHC_CLK
tSHSIVKH
tSHSIXKH
SDHC_DAT/SDHC_CMD
inputs
VM = Midpoint Voltage (OVDD/2)
Figure 72. eSDHC high-speed mode input AC timing diagram
This figure provides the output AC timing diagram for high-speed mode.
VM
VM
VM
VM
SDHC_CLK
SDHC_CMD/SDHC_CMD_DIR
SDHC_DAT/SDHC_DATn_DIR
outputs
tSHSKHOV
tSHSKHOX
VM = Midpoint Voltage (OV /2)
DD
Figure 73. eSDHC high-speed mode output AC timing diagram
This table provides the eSDHC AC timing specifications for SDR50 mode.
Table 109. eSDHC AC timing specifications (SDR50)2
Parameter
Symbol
fSHCK
-
tSHCKR/
Min
Max
Unit
MHz
Notes
SDHC_CLK clock frequency
SDHC_CLK duty cycle
-
80
60
1
-
-
40
-
%
SDHC_CLK clock rise and fall times
ns
1
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
192
NXP Semiconductors
Electrical characteristics
Table 109. eSDHC AC timing specifications (SDR50)2 (continued)
Parameter
Symbol
tSHCKF
Min
Max
Unit
Notes
Skew between SDHC_CLK_SYNC_OUT and SDHC_CLK
-
-0.1
0.1
ns
ns
-
-
Input setup times: SDHC_CMD, SDHC_DATx to
SDHC_CLK_SYNC_IN
tSHIVKH
3.1
1.0
2.85
-
-
Input hold times: SDHC_CMD, SDHC_DATx to
SDHC_CLK_SYNC_IN
tSHIXKH
-
ns
ns
ns
-
-
-
Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid,
SDHC_DATx_DIR, SDHC_CMD_DIR
tSHKHOX
-
Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid, tSHKHOV
SDHC_DATx_DIR, SDHC_CMD_DIR
8.05
Notes:
1. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 30 pF.
2. At recommended operating conditions with OVDD=1.8V.
This figure provides the eSDHC clock input timing diagram for SDR50 mode.
eSDHC
external clock
VM
VM
VM
operational mode
tSHCK
tSHCKR
tSHCKF
VM = Midpoint voltage (EVDD/2)
Figure 74. eSDHC SDR50 mode clock input timing diagram
This figure provides the eSDHC input AC timing diagram for SDR50 mode.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
193
Electrical characteristics
T
CLK
SDHC_CLK_SYNC_IN
T
T
SHIXKH
SHIVKH
SDHC_CMD/
SDHC_DAT
input
Figure 75. eSDHC SDR50 mode input AC timing diagram
This figure provides the eSDHC output timing diagram for SDR50 mode.
T
CLK
SD_CLK
T
SHKHOV
SDHC_CMD/SDHC_CMD_DIR
SDHC_DAT/SDHC_DATn_DIR
output
T
SHKHOX
Figure 76. eSDHC SDR50 mode output timing diagram
This table provides the eSDHC AC timing specifications for DDR50/DDR mode.
Table 110. eSDHC AC timing specifications (DDR50/DDR)3
Parameter
SDHC_CLK clock frequency
Symbol
Min
Max
Unit
MHz
Notes
SD/SDIO DDR50 fSHCK
-
37
37
-
mode
eMMC DDR
mode
SDHC_CLK duty cycle
Skew between SDHC_CLK_SYNC_OUT and SDHC_CLK
-
-
47.0
-0.1
53.0
0.1
%
-
-
ns
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
194
NXP Semiconductors
Electrical characteristics
Table 110. eSDHC AC timing specifications (DDR50/DDR)3 (continued)
Parameter
Symbol
Min
Max
Unit
Notes
SDHC_CLK clock rise and fall times
SD/SDIO DDR50 tSHCKR/
mode
-
5.4
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
eMMC DDR
mode
tSHCKF
Input setup times: SDHC_DATx to
SDHC_CLK_SYNC_IN
SD/SDIO DDR50 tSHDIVKH
mode
3.82
3.91
-
-
-
-
-
-
-
-
-
-
-
eMMC DDR
mode
Input hold times: SDHC_DATx to
SDHC_CLK_SYNC_IN
SD/SDIO DDR50 tSHDIXKH
mode
-
1.0
0.98
eMMC DDR
mode
Output hold time: SDHC_CLK to
SDHC_DATx valid, SDHC_DATx_DIR
SD/SDIO DDR50 tSHDKHOX
mode
2.4
4.12
eMMC DDR
mode
Output delay time: SDHC_CLK to
SDHC_DATx valid, SDHC_DATx_DIR
SD/SDIO DDR50 tSHDKHOV
mode
-
9.01
9.61
eMMC DDR
mode
Input setup times: SDHC_CMD to
SDHC_CLK_SYNC_IN
SD/SDIO DDR50 tSHCIVKH
mode
10.13
10.27
-
-
-
eMMC DDR
mode
Input hold times: SDHC_CMD to
SDHC_CLK_SYNC_IN
SD/SDIO DDR50 tSHCIXKH
mode
1.0
0.98
eMMC DDR
mode
Output hold time: SDHC_CLK to
SDHC_CMD valid, SDHC_CMD_DIR
SD/SDIO DDR50 tSHCKHOX
mode
2.4
4.62
eMMC DDR
mode
Output delay time: SDHC_CLK to
SDHC_CMD valid, SDHC_CMD_DIR
SD/SDIO DDR50 tSHCKHOV
mode
-
19.02
22.17
eMMC DDR
mode
Notes:
1. CCARD ≤ 10pF, (1 card).
2. CL = CBUS + CHOST + CCARD ≤ 20pF for MMC, 40pF for SD.
3. At recommended operating conditions with OVDD/EVDD=1.8 or 3.3V for eMMC DDR mode, OVDD=1.8 V for DDR50.
This figure provides the eSDHC DDR50/DDR mode input AC timing diagram.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
195
Electrical characteristics
T
SHCK
SDHC_CLK_SYNC_IN
T
T
SHDIXKH
SHDIVKH
SDHC_DAT
input
T
T
SHCIXKH
SHCIVKH
SDHC_CMD
input
Figure 77. eSDHC DDR50/DDR mode input AC timing diagram
This figure provides the eSDHC DDR50/DDR mode output AC timing diagram.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
196
NXP Semiconductors
Electrical characteristics
T
SHCK
SDHC_CLK
T
SHDKHOV
SDHC_DAT/
SDHC_DATn_DIR
output
T
SHDKHOX
T
SHCKHOV
SDHC_CMD/
SD_CMD_DIR
output
T
SHCKHOX
Figure 78. eSDHC DDR50/DDR mode output AC timing diagram
This table provides the eSDHC AC timing specifications for SDR104/eMMC HS200
mode.
Table 111. eSDHC AC timing specifications (SDR104/eMMC HS200)
Parameter
Symbol1
Min
Max
120
Unit Notes
SDHC_CLK clock frequency
SD/SDIO
SDR104
mode
fSHCK
-
MHz
-
116.7
eMMC
HS200
mode
SDHC_CLK duty cycle
40
-
60
1
%
-
SDHC_CLK clock rise and fall times
tSHCKR/tSHCKF
TSHKHOX
ns
ns
1
-
Output hold time: SDHC_CLK to SDHC_CMD,
SDHC_DATx valid, SDHC_CMD_DIR,
SDHC_DATx_DIR
SD/SDIO
SDR104
mode
-
-
1.93
1.96
eMMC
HS200
mode
Output delay time: SDHC_CLK to SDHC_CMD,
SDHC_DATx valid, SDHC_CMD_DIR,
SDHC_DATx_DIR
SD/SDIO
SDR104
mode
TSHKHOV
-
-
ns
-
5.9
6.11
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
197
Electrical characteristics
Table 111. eSDHC AC timing specifications (SDR104/eMMC HS200) (continued)
Parameter
Symbol1
Min
Max
Unit Notes
eMMC
HS200
mode
Input data window (UI)
SD/SDIO
SDR104
mode
tSHIDV
-
-
Unit
Interva
l
-
0.5
0.475
eMMC
HS200
mode
Notes:
1. CL = CBUS + CHOST + CCARD ≤ 10pF.
2. At recommended operating conditions with OVDD =1.8 V.
This figure provides the eSDHC SDR104/HS200 mode timing diagram.
T
SHCK
SDHC_CLK
T
SHIDV
SDHC_CMD/
SDHC_DAT input
DATA
T
SHKHOV
SDHC_CMD/SDHC_CMD_DIR
SDHC_DAT/SDHC_DATn_DIR
output
DATA
T
DATA
SHKHOX
Figure 79. eSDHC SDR104/HS200 mode timing diagram
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
198
NXP Semiconductors
Electrical characteristics
3.21 JTAG controller
This section describes the DC and AC electrical specifications for the IEEE 1149.1
(JTAG) interface.
3.21.1 JTAG DC electrical characteristics
This table provides the JTAG DC electrical characteristics.
Table 112. JTAG DC electrical characteristics (OVDD = 1.8V)3
Parameter
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
1.2
—
—
V
1
VIL
0.6
V
1
Input current (OVIN = 0 V or OVIN = OVDD
)
IIN
—
50
µA
V
2
Output high voltage (OVDD = min, IOH = -0.5 mA)
Output low voltage (OVDD = min, IOL= 0.5 mA)
Notes:
VOH
VOL
1.35
—
—
—
—
0.4
V
1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 5.
2. The symbol VIN, in this case, represents the OVIN symbol found in Table 5.
3. For recommended operating conditions, see Table 5.
3.21.2 JTAG AC timing specifications
This table provides the JTAG AC timing specifications as defined in Figure 80, Figure
81, Figure 82, and Figure 83.
Table 113. JTAG AC timing specifications4
Parameter
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST_B assert time
Symbol1
Min
Max
33.3
Unit
MHz
Notes
fJTG
0
—
—
—
—
2
tJTG
30
15
0
—
—
2
ns
ns
ns
ns
ns
ns
ns
tJTKHKL
tJTGR/tJTGF
tTRST
25
4
—
—
—
15
10
—
Input setup times
tJTDVKH
tJTDXKH
tJTKLDV
—
—
3
Input hold times
10
—
—
0
Output valid times
Boundary-scan data
TDO
Output hold times
tJTKLDX
ns
3
Notes:
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
199
Electrical characteristics
Table 113. JTAG AC timing specifications4
Parameter
Symbol1
Min
Max
Unit
Notes
1. The symbols used for timing specifications follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K)
going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals
(D) reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the
clock reference symbol representation is based on three letters representing the clock of a particular function. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.TRST_B is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The
output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be
added for trace lengths, vias, and connectors in the system.
4. For recommended operating conditions, see Table 5.
This figure shows the AC test load for TDO and the boundary-scan outputs of the device.
Output
OVDD/2
Z0= 50 Ω
RL = 50 Ω
Figure 80. AC test load for the JTAG interface
This figure shows the JTAG clock input timing diagram.
VM
VM
VM
JTAG external clock
tJTGR
tJTKHKL
tJTGF
tJTG
VM = Midpoint voltage (OVDD/2)
Figure 81. JTAG clock input timing diagram
This figure shows the TRST_B timing diagram.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
200
NXP Semiconductors
Electrical characteristics
TRST_B
VM
VM
tTRST
VM = Midpoint voltage (OVDD/2)
Figure 82. TRST_B timing diagram
This figure shows the boundary-scan timing diagram.
JTAG External Clock
VM
VM
tJTDVKH
tJTDXKH
Boundary Data Inputs
Input Data Valid
tJTKLDV
tJTKLDX
Boundary Data Outputs
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 83. Boundary-scan timing diagram
3.22 I2C interface
This section describes the DC and AC electrical characteristics for the I2C interfaces.
3.22.1 I2C DC electrical characteristics
This table provides the DC electrical characteristics for the I2C interfaces operating at
DVDD = 3.3 V.
Table 114. I2C DC electrical characteristics (DVDD = 3.3 V)4
Parameter
Symbol
VIH
Min
0.7 x
DVDD
Max
Unit
Notes
Input high voltage
—
V
1
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
201
Electrical characteristics
Table 114. I2C DC electrical characteristics (DVDD = 3.3 V)4 (continued)
Parameter
Symbol
VIL
Min
Max
Unit
Notes
Input low voltage
—
—
0.2 x
DVDD
0.4
V
V
1
2
Output low voltage
VOL
(DVDD = min, IOL = 3 mA)
Pulse width of spikes which must be suppressed by the input filter
tI2KHKL
0
50
50
ns
3
-
Input current each I/O pin (input voltage is between 0.1 x DVDD and 0.9 II
x DVDD(max)
-50
µA
Capacitance for each I/O pin
CI
—
10
pF
—
Notes:
1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 5.
2. The output voltage (open drain or open collector) condition = 3 mA sink current.
3. See the chip reference manual for information about the digital filter used.
4. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for the I2C interfaces operating at
DVDD = 1.8 V.
Table 115. I2C DC electrical characteristics (DVDD = 1.8 V)4
Parameter
Symbol
VIH
Min
Max
Unit
Notes
Input high voltage
Input low voltage
0.7 x
DVDD
—
—
V
V
1
1
2
VIL
0.2 x
DVDD
Output low voltage (DVDD = min, IOL = 3 mA)
VOL
0
0.36
V
Pulse width of spikes which must be suppressed by the input filter
tI2KHKL
0
50
50
ns
3
-
Input current each I/O pin (input voltage is between 0.1 x DVDD and 0.9 II
x DVDD(max)
-50
µA
Capacitance for each I/O pin
CI
—
10
pF
—
Notes:
1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 5.
2. The output voltage (open drain or open collector) condition = 3 mA sink current.
3. See the chip reference manual for information about the digital filter used.
4. For recommended operating conditions, see Table 5.
3.22.2 I2C AC timing specifications
This table provides the AC timing specifications for the I2C interfaces.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
202
NXP Semiconductors
Electrical characteristics
Table 116. I2C AC timing specifications5
Parameter
Symbol1
Min
Max
Unit
Notes
SCL clock frequency
fI2C
0
400
—
kHz
μs
2
Low period of the SCL clock
tI2CL
1.3
0.6
0.6
0.6
—
—
—
—
High period of the SCL clock
tI2CH
—
μs
Setup time for a repeated START condition
tI2SVKH
tI2SXKL
—
μs
Hold time (repeated) START condition (after this period, the
first clock pulse is generated)
—
μs
Data setup time
tI2DVKH
tI2DXKL
100
—
—
—
—
0.9
—
—
—
ns
μs
—
3
Data input hold time
CBUS compatible masters
I2C bus devices
0
Data output delay time
tI2OVKL
tI2PVKH
tI2KHDX
VNL
—
μs
μs
μs
V
4
Setup time for STOP condition
0.6
1.3
—
—
—
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device
(including hysteresis)
0.1 x DVDD
0.2 x DVDD
—
Noise margin at the HIGH level for each connected device
(including hysteresis)
VNH
Cb
—
V
—
—
Capacitive load for each bus line
400
pF
Notes:
1. The symbols used for timing specifications herein follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2)
with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the
high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START
condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH
symbolizes I2C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative
to the tI2C clock reference (K) going to the high (H) state or setup time.
2. The requirements for I2C frequency calculation must be followed. See Determining the I2C Frequency Divider Ratio for
SCL (AN2919).
3. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP
condition. When the chip acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on
SCL and SDA are balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns
SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the
chip as transmitter, see Determining the I2C Frequency Divider Ratio for SCL (AN2919).
4. The maximum tI2OVKL has to be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
5. For recommended operating conditions, see Table 5.
This figure shows the AC test load for the I2C.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
203
Electrical characteristics
Output
DVDD/2
Z0= 50 Ω
RL = 50 Ω
Figure 84. I2C AC test load
This figure shows the AC timing diagram for the I2C bus.
SDA
tI2KHKL
tI2DVKH
tI2KHDX
tI2SXKL
tI2CL
SCL
tI2CH
tI2SVKH
tI2PVKH
tI2SXKL
tI2DXKL, tI2OVKL
P
S
S
Sr
Figure 85. I2C bus AC timing diagram
3.23 GPIO interface
This section describes the DC and AC electrical characteristics for the GPIO interface.
There are GPIO pins on various power supplies in this device.
3.23.1 GPIO DC electrical characteristics
This table provides the DC electrical characteristics for GPIO pins operating at D/
EVDD = 3.3 V.
Table 117. GPIO DC electrical characteristics (DVDD/EVDD = 3.3 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
IIN
0.7 x D/EVDD
—
V
1
Input low voltage
—
0.2 x D/EVDD
V
1
Input current (VIN = 0 V or VIN= D/EVDD)
Output high voltage
—
50
—
μA
V
2
VOH
2.4
—
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
204
NXP Semiconductors
Electrical characteristics
Table 117. GPIO DC electrical characteristics (DVDD/EVDD = 3.3 V)3 (continued)
Parameter
Symbol
Min
Max
Unit
Notes
(D/EVDD = min, IOH = -2 mA)
Output low voltage
(D/EVDD = min, IOL = 2 mA)
Notes:
VOL
—
0.4
V
—
1. The min VIL and max VIH values are based on the respective min and max DVIN/EVIN values found in Table 5.
2. The symbol VIN, in this case, represents the DVIN/EVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for GPIO pins operating at
TVDD = 2.5 V.
Table 118. GPIO DC electrical characteristics (TVDD = 2.5 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
IIN
0.7 x TVDD
—
V
1
Input low voltage
—
0.2 x TVDD
V
1
Input current (VIN = 0 V or VIN= TVDD)
Output high voltage
(TVDD = min, IOH = -1 mA)
Output low voltage
—
50
—
μA
V
2
VOH
2.0
—
VOL
—
0.4
V
—
(TVDD = min, IOL = 1 mA)
Notes:
1. The min VIL and max VIH values are based on the respective min and max TVIN values found in Table 5.
2. The symbol VIN, in this case, represents the TVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for GPIO pins operating at DVDD/
EVDD/TVDD = 1.8 V.
Table 119. GPIO DC electrical characteristics (DVDD/EVDD/TVDD = 1.8 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
IIN
0.7 x D/E/TVDD
—
V
1
1
2
Input low voltage
—
—
0.2 x D/E/TVDD
50
V
Input current (VIN = 0 V or VIN = D/E/
μA
TVDD
)
Output high voltage
VOH
1.35
—
—
V
V
—
—
(D/E/TVDD = min, IOH = -0.5 mA)
Output low voltage
VOL
0.4
(D/E/TVDD = min, IOL = 0.5 mA)
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
205
Electrical characteristics
Table 119. GPIO DC electrical characteristics (DVDD/EVDD/TVDD = 1.8 V)3 (continued)
Parameter
Symbol
Min
Max
Unit
Notes
Notes:
1. The min VIL and max VIH values are based on the respective min and max DVIN/EVIN/TVIN values found in Table 5.
2. The symbol VIN, in this case, represents the DVIN/EVIN/TVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for GPIO pins operating at
TVDD = 1.2 V.
Table 120. GPIO DC electrical characteristics (TVDD = 1.2 V)3
Parameter
Input high voltage
Symbol
Min
0.7 x TVDD
—
Max
Unit
Notes
VIH
VIL
—
V
V
V
Input low voltage
0.2 x TVDD
—
Output high voltage
(TVDD = min, IOH = -100uA)
Output low voltage
(TVDD = min, IOL = 100uA)
Input Capacitance
Notes:
VOH
1.0
—
—
—
VOL
CIN
—
—
0.2
10
V
pF
1. The min VIL and max VIH values are based on the respective min and max TVIN values found in Table 5.
2. The symbol VIN, in this case, represents the TVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for GPIO pins operating at LVDD
= 2.5 V.
Table 121. GPIO DC electrical characteristics (LVDD = 2.5 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
IIN
1.7
—
—
V
1
Input low voltage
0.7
V
1
Input current (VIN = 0 V or VIN= LVDD
Output high voltage
(LVDD = min, IOH = -1 mA)
Output low voltage
)
—
50
μA
V
2
VOH
2.0
—
—
VOL
—
0.4
V
—
(LVDD = min, IOL = 1 mA)
Notes:
1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 5.
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
206
NXP Semiconductors
Electrical characteristics
This table provides the DC electrical characteristics for GPIO pins operating at OVIN/
LVIN = = = 1.8 V.
Table 122. GPIO DC electrical characteristics (OVDD/LVDD = 1.8 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
IIN
1.2
—
—
V
1
Input low voltage
0.6
V
1
Input current (VIN = 0 V or VIN = O/LVDD
)
—
50
μA
V
2
Output high voltage
VOH
1.35
—
—
(O/LVDD = min, IOH = -0.5 mA)
Output low voltage
VOL
—
0.4
V
—
(O/LVDD = min, IOL = 0.5 mA)
Notes:
1. The min VIL and max VIH values are based on the respective min and max OVIN/LVIN values found in Table 5.
2. The symbol VIN, in this case, represents the OVIN/LVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
3.23.2 GPIO AC timing specifications
Table below provides the GPIO input and output AC timing specifications.
Table 123. GPIO Input AC timing specifications
Parameter
GPIO inputs-minimum pulse width
Notes:
Symbol
tPIWID
Min
Unit
Notes
20
ns
1
1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation.
2. For recommended operating conditions, see Table 5
Figure below provides the AC test load for the GPIO.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
207
Electrical characteristics
Output
(L/O) VDD/2
Z0= 50 Ω
RL = 50 Ω
Figure 86. GPIO AC test load
3.24 GIC interface
This section describes the DC and AC electrical characteristics for the GIC interface.
3.24.1 GIC DC electrical characteristics
This table provides the DC electrical characteristics for GIC pins operating at
DVDD = 3.3 V.
Table 124. GIC DC electrical characteristics (DVDD = 3.3 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
IIN
0.7 x DVDD
—
V
1
Input low voltage
—
0.2 x DVDD
V
1
Input current (VIN = 0 V or VIN= DVDD)
Output high voltage
—
50
—
μA
V
2
VOH
2.4
—
(DVDD = min, IOH = -2 mA)
Output low voltage
VOL
—
0.4
V
—
(DVDD = min, IOL = 2 mA)
Notes:
1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 5.
2. The symbol VIN, in this case, represents the DVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for GIC pins operating at
DVDD = 1.8 V.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
208
NXP Semiconductors
Electrical characteristics
Table 125. GIC DC electrical characteristics (DVDD = 1.8 V)3
Parameter
Input high voltage
Symbol
Min
0.7 x DVDD
—
Max
Unit
Notes
Notes
Notes
VIH
VIL
IIN
—
V
1
Input low voltage
0.2 x DVDD
V
1
Input current (VIN = 0 V or VIN = DVDD
)
—
50
—
μA
V
2
Output high voltage
VOH
1.35
—
(DVDD = min, IOH = -0.5 mA)
Output low voltage
VOL
—
0.4
V
—
(DVDD = min, IOL = 0.5 mA)
Notes:
1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 5.
2. The symbol VIN, in this case, represents the DVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for GIC pins operating at
LVDD = 2.5 V.
Table 126. GIC DC electrical characteristics (LVDD = 2.5 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
VIH
VIL
IIN
1.7
—
—
V
1
Input low voltage
0.7
V
1
Input current (VIN = 0 V or VIN= LVDD
Output high voltage
(LVDD = min, IOH = -1 mA)
Output low voltage
)
—
50
μA
V
2
VOH
2.0
—
—
VOL
—
0.4
V
—
(LVDD = min, IOL = 1 mA)
Notes:
1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 5.
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
This table provides the DC electrical characteristics for GIC pins operating at O/
LVDD = 1.8 V.
Table 127. GIC DC electrical characteristics (O/LVDD = 1.8 V)3
Parameter
Input high voltage
Symbol
Min
Max
Unit
VIH
VIL
IIN
1.2
—
—
V
1
1
2
Input low voltage
0.6
V
Input current (VIN = 0 V or VIN = O/LVDD
)
—
50
μA
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
209
Electrical characteristics
Table 127. GIC DC electrical characteristics (O/LVDD = 1.8 V)3 (continued)
Parameter
Output high voltage
Symbol
Min
Max
Unit
Notes
VOH
1.35
—
—
V
V
—
—
(O/LVDD = min, IOH = -0.5 mA)
Output low voltage
VOL
0.4
(O/LVDD = min, IOL = 0.5 mA)
Notes:
1. The min VIL and max VIH values are based on the respective min and max O/LVIN values found in Table 5.
2. The symbol VIN, in this case, represents the O/LVIN symbol referenced in Table 5.
3. For recommended operating conditions, see Table 5.
3.24.2 GIC AC timing specifications
This table provides the GIC input and output AC timing specifications.
Table 128. GIC Input AC timing specifications2
Characteristic
Symbol
tPIWID
Min
Max
Unit
Notes
GIC inputs-minimum pulse width
3
-
SYSCLKs
1
1. GIC inputs and outputs are asynchronous to any visible clock. GIC outputs must be synchronized before use by any
external synchronous logic. GIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working
in edge triggered mode.
2. For recommended operating conditions, see Table 5.
3.25 High-speed serial interfaces (HSSI)
The chip features a Serializer/Deserializer (SerDes) interface to be used for high-speed
serial interconnect applications. The SerDes interface can be used for PCI Express,
SGMII, QSGMII, XFI, 1000Base-KX and serial ATA (SATA) data transfers.
This section describes the most common portion of the SerDes DC electrical
specifications: the DC requirement for SerDes reference clocks. The SerDes data lane's
transmitter (Tx) and receiver (Rx) reference circuits are also described.
3.25.1 Signal terms definitions
The SerDes utilizes differential signaling to transfer data across the serial link. This
section defines the terms that are used in the description and specification of differential
signals.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
210
NXP Semiconductors
Electrical characteristics
This figure shows how the signals are defined. For illustration purposes only, one SerDes
lane is used in the description. This figure shows the waveform for either a transmitter
output (SD_TXn_P and SD_TXn_N) or a receiver input (SD_RXn_P and SD_RXn_N).
Each signal swings between A volts and B volts where A > B.
SD_TXn_P or
SD_RXn_P
A Volts
Vcm= (A + B)/2
SD_TXn_N or
SD_RXn_N
B Volts
Differential swing, VID orVOD = A - B
Differential peak voltage, VDIFFp = |A - B|
Differential peak-to-peak voltage, VDIFFpp =2 x VDIFFp (not shown)
Figure 87. Differential voltage definitions for transmitter or receiver
Using this waveform, the definitions are as described in the following list. To simplify
the illustration, the definitions assume that the SerDes transmitter and receiver operate in
a fully symmetrical differential signaling environment:
Single-Ended Swing
The transmitter output signals and the receiver input signals SD_TXn_P, SD_TXn_N,
SD_RXn_P and SD_RXn_N each have a peak-to-peak swing of A - B volts. This is
also referred to as each signal wire's single-ended swing.
Differential Output Voltage, VOD (or Differential Output Swing)
The differential output voltage (or swing) of the transmitter, VOD, is defined as the
difference of the two complementary output voltages: VSD_TXn_P - VSD_TXn_N. The
VOD value can be either positive or negative.
Differential Input Voltage, VID (or Differential Input Swing)
The differential input voltage (or swing) of the receiver, VID, is defined as the
difference of the two complementary input voltages: VSD_RXn_P- VSD_RXn_N. The VID
value can be either positive or negative.
Differential Peak Voltage, VDIFFp
The peak value of the differential transmitter output signal or the differential receiver
input signal is defined as the differential peak voltage, VDIFFp = |A - B| volts.
Differential Peak-to-Peak, VDIFFp-p
Because the differential output signal of the transmitter and the differential input
signal of the receiver each range from A - B to -(A - B) volts, the peak-to-peak value
of the differential transmitter output signal or the differential receiver input signal is
defined as differential peak-to-peak voltage, VDIFFp-p = 2 x VDIFFp = 2 x |(A - B)| volts,
which is twice the differential swing in amplitude, or twice the differential peak. For
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
211
Electrical characteristics
example, the output differential peak-to-peak voltage can also be calculated as VTX-
DIFFp-p = 2 x |VOD|.
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal
(SD_TXn_N, for example) from the non-inverting signal (SD_TXn_P, for example)
within a differential pair. There is only one signal trace curve in a differential
waveform. The voltage represented in the differential waveform is not referenced to
ground. See Figure 92 as an example for differential waveform.
Common Mode Voltage, Vcm
The common mode voltage is equal to half of the sum of the voltages between each
conductor of a balanced interchange circuit and ground. In this example, for SerDes
output, Vcm_out = (VSD_TXn_P + VSD_TXn_N) ÷ 2 = (A + B) ÷ 2, which is the arithmetic
mean of the two complementary output voltages within a differential pair. In a system,
the common mode voltage may often differ from one component's output to the other's
input. It may be different between the receiver input and driver output circuits within
the same component. It is also referred to as the DC offset on some occasions.
To illustrate these definitions using real values, consider the example of a current mode
logic (CML) transmitter that has a common mode voltage of 2.25 V and outputs, TD and
TD_B. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak voltage swing
of each signal (TD or TD_B) is 500 mV p-p, which is referred to as the single-ended
swing for each signal. Because the differential signaling environment is fully symmetrical
in this example, the transmitter output's differential swing (VOD) has the same amplitude
as each signal's single-ended swing. The differential output signal ranges between 500
mV and -500 mV. In other words, VOD is 500 mV in one phase and -500 mV in the other
phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential
voltage (VDIFFp-p) is 1000 mV p-p.
3.25.2 SerDes reference clocks
The SerDes reference clock inputs are applied to an internal phase-locked loop (PLL)
whose output creates the clock used by the corresponding SerDes lanes. The SerDes
reference clocks inputs are SD1_REF_CLK[1:2]_P and SD1_REF_CLK[1:2]_N.
SerDes may be used for various combinations of the following IP block based on the
RCW Configuration field SRDS_PRTCLn:
• SGMII (1.25 Gbps or 3.125 Gbps), QSGMII (5 Gbps)
• XFI (10Gbps)
• PCIe (2.5 Gbps and 5 Gbps )
• SATA (1.5 Gbps, 3.0 Gbps and 6.0 Gbps)
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
212
NXP Semiconductors
Electrical characteristics
The following sections describe the SerDes reference clock requirements and provide
application information.
3.25.2.1 SerDes spread-spectrum clock source recommendations
SD1_REF_CLKn_P and SD1_REF_CLKn_N are designed to work with spread-spectrum
clocking for the PCI Express protocol only with the spreading specification defined in
Table 129. When using spread-spectrum clocking for PCI Express, both ends of the link
partners should use the same reference clock. For best results, a source without
significant unintended modulation must be used.
The SerDes transmitter does not support spread-spectrum clocking for the SATA
protocol. The SerDes receiver does support spread-spectrum clocking on receive, which
means the SerDes receiver can receive data correctly from a SATA serial link partner
using spread-spectrum clocking.
Spread-spectrum clocking cannot be used if the same SerDes reference clock is shared
with other non-spread-spectrum-supported protocols. For example, if spread-spectrum
clocking is desired on a SerDes reference clock for the PCI Express protocol and the
same reference clock is used for any other protocol, such as SATA or SGMII because of
the SerDes lane usage mapping option, spread-spectrum clocking cannot be used at all.
This table provides the source recommendations for SerDes spread-spectrum clocking.
Table 129. SerDes spread-spectrum clock source recommendations 1
Parameter
Min
Max
Unit
Notes
Frequency modulation
Frequency spread
Notes:
30
+0
33
kHz
%
—
2
-0.5
1. At recommended operating conditions. See Table 5.
2. Only down-spreading is allowed.
3.25.2.2 SerDes reference clock receiver characteristics
This figure shows a receiver reference diagram of the SerDes reference clocks.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
213
Electrical characteristics
50 Ω
SD1_REF_CLKn_P
Input
amp
SD1_REF_CLKn_N
50 Ω
Figure 88. Receiver of SerDes reference clocks
The characteristics of the clock signals are as follows:
• The SerDes transceiver's core power supply voltage requirements (S1VDD) are as
specified in Table 5.
• The SerDes reference clock receiver reference circuit structure is as follows:
• The SD1_REF_CLKn_P and SD1_REF_CLKn_N are internally AC-coupled
differential inputs as shown in Figure 88. Each differential clock input
(SD1_REF_CLKn_P or SD1_REF_CLKn_N) has on-chip 50-Ω termination to
SGNDn followed by on-chip AC-coupling.
• The external reference clock driver must be able to drive this termination.
• The SerDes reference clock input can be either differential or single-ended. See
the differential mode and single-ended mode descriptions in Signal terms
definitions for detailed requirements.
• The maximum average current requirement also determines the common mode
voltage range.
• When the SerDes reference clock differential inputs are DC coupled externally
with the clock driver chip, the maximum average current allowed for each input
pin is 8 mA. In this case, the exact common mode input voltage is not critical as
long as it is within the range allowed by the maximum average current of 8 mA
because the input is AC-coupled on-chip.
• This current limitation sets the maximum common mode input voltage to be less
than 0.4 V (0.4 V ÷ 50 = 8 mA) while the minimum common mode input level is
0.1 V above SGNDn. For example, a clock with a 50/50 duty cycle can be
produced by a clock driver with output driven by its current source from 0 mA to
16 mA (0-0.8 V), such that each phase of the differential input has a single-
ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.
• If the device driving the SD1_REF_CLKn_P and SD1_REF_CLKn_N inputs
cannot drive 50 Ω to SGNDn DC or the drive strength of the clock driver chip
exceeds the maximum input current limitations, it must be AC-coupled off-chip.
• The input amplitude requirement is described in detail in the following sections.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
214
NXP Semiconductors
Electrical characteristics
3.25.2.3 DC-level requirements for SerDes reference clocks
The DC-level requirements for the SerDes reference clock inputs are different depending
on the signaling mode used to connect the clock driver chip and SerDes reference clock
inputs, as described below:
• Differential Mode
• The input amplitude of the differential clock must be between 400 mV and 1600
mV differential peak-to-peak (or between 200 mV and 800 mV differential
peak). In other words, each signal wire of the differential pair must have a
single-ended swing of less than 800 mV and greater than 200 mV. This
requirement is the same for both external DC-coupled or AC-coupled
connection.
• For an external DC-coupled connection, as described in Figure 88, the maximum
average current requirements set the requirement for average voltage (common
mode voltage) as between 100 mV and 400 mV.
• This figure shows the SerDes reference clock input requirement for a DC-
coupled connection scheme.
200 mV < Input amplitude or differential peak < 800 mV
SD1_REF_CLKn_P
Vmax < 800mV
100 mV < Vcm < 400 mV
Vmin > 0 V
SD1_REF_CLKn_N
Figure 89. Differential reference clock input DC requirements (external DC-coupled)
• For an external AC-coupled connection, there is no common mode voltage
requirement for the clock driver. Because the external AC-coupling capacitor
blocks the DC level, the clock driver and the SerDes reference clock receiver
operate in different common mode voltages. The SerDes reference clock receiver
in this connection scheme has its common mode voltage set to SGNDn. Each
signal wire of the differential inputs is allowed to swing below and above the
common mode voltage (SGNDn).
• This figure shows the SerDes reference clock input requirement for an AC-
coupled connection scheme.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
215
Electrical characteristics
200 mV < Input amplitude or differential peak < 800 mV
SD1_REF_CLKn_P
Vmax < Vcm + 400 mV
Vcm
Vmin > Vcm - 400 mV
SD1_REF_CLKn_N
Figure 90. Differential reference clock input DC requirements (external AC-coupled)
• Single-ended mode
• The reference clock can also be single-ended. The SD1_REF_CLKn_P input
amplitude (single-ended swing) must be between 400 mV and 800 mV peak-to-
peak (from VMIN to VMAX) with SD1_REF_CLKn_N either left unconnected or
tied to ground.
• To meet the input amplitude requirement, the reference clock inputs may need to
be externally DC- or AC-coupled. For the best noise performance, the reference
of the clock could be DC- or AC-coupled into the unused phase
(SD1_REF_CLKn_N) through the same source impedance as the clock input
(SD1_REF_CLKn_P) in use.
• The SD1_REF_CLKn_P input average voltage must be between 200 and 400
mV.
• This figure shows the SerDes reference clock input requirement for single-ended
signaling mode.
400 mV < SD1_REF_CLKn input amplitude < 800 mV
SD1_REF_CLKn_P
0 V
SD1_REF_CLKn_N
Figure 91. Single-ended reference clock input DC requirements
3.25.2.4 AC requirements for SerDes reference clocks
This table provides the AC requirements for SerDes reference clocks for PCI Express
protocols running at data rates up to 5 Gb/s.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
216
NXP Semiconductors
Electrical characteristics
This includes PCI Express (2.5 and 5 GT/s), QSGMII (5Gbps), SGMII (1.25 Gbps and
3.125 Gbps), and SATA (1.5, 3.0 and 6.0 Gbps). SerDes reference clocks need to be
verified by the customer's application design.
Table 130. SD1_REF_CLKn_P and SD1_REF_CLKn_N input clock requirements (S1VDD) 1
Parameter
Symbol
Min
Typ
Max
Unit
MHz
Notes
SD1_REF_CLKn_P/ SD1_REF_CLKn_N frequency tCLK_REF
—
100/125/156.25
—
2
3
4
5
range
SD1_REF_CLKn_P/ SD1_REF_CLKn_N clock
tCLK_TOL
tCLK_TOL
-300
-100
40
—
—
50
—
—
300
100
60
ppm
ppm
%
frequency tolerance
SD1_REF_CLKn_P/ SD1_REF_CLKn_N clock
frequency tolerance
SD1_REF_CLKn_P/ SD1_REF_CLKn_N reference tCLK_DUTY
clock duty cycle
SD1_REF_CLKn_P/ SD1_REF_CLKn_N max
tCLK_DJ
tCLK_TJ
—
42
ps
—
6
deterministic peak-to-peak jitter at 10-6 BER
SD1_REF_CLKn_P/ SD1_REF_CLKn_N total
reference clock jitter at 10-6 BER (peak-to-peak jitter
at refClk input)
—
86
ps
SD1_REF_CLKn_P/ SD1_REF_CLKn_N 10 kHz to tREFCLK-LF-RMS
1.5 MHz RMS jitter
—
—
—
—
3
ps
RMS
7
7
9
SD1_REF_CLKn_P/ SD1_REF_CLKn_N > 1.5 MHz tREFCLK-HF-RMS
to Nyquist RMS jitter
—
3.1
4
ps
RMS
SD1_REF_CLKn_P/ SD1_REF_CLKn_N rising/
tCLKRR/ CLKFR
t
0.6
V/ns
falling edge rate
Differential input high voltage
Differential input low voltage
VIH
VIL
150
—
—
—
—
—
mV
mV
%
5
-150
20
5
Rising edge rate (SD1_REF_CLKn_P) to falling
edge rate (SD1_REF_CLKn_N) matching
Rise-Fall
Matching
—
10, 11
Notes:
1. For recommended operating conditions, see Table 5.
2. Caution: Only 100, 125 and 156.25 MHz frequencies have been tested. In-between values do not work correctly with the
rest of the system.
3. For PCI Express (2.5 and 5 GT/s).
4. For SGMII and QSGMII.
5. Measurement taken from differential waveform.
6. Limits from PCI Express CEM Rev 2.0.
7. For PCI Express 5 GT/s, per PCI Express base specification Rev 3.0.
9. Measured from -150 mV to +150 mV on the differential waveform (derived from SD1_REF_CLKn_P minus
SD1_REF_CLKn_N). The signal must be monotonic through the measurement region for rise and fall time. The 300 mV
measurement window is centered on the differential zero crossing. See Figure 92.
10. Measurement taken from single-ended waveform.
11. Matching applies to rising edge for SD1_REF_CLKn_P and falling edge rate for SD1_REF_CLKn_N. It is measured using
a +/-75 mV window centered on the median cross point where SD1_REF_CLKn_P rising meets SD1_REF_CLKn_N falling.
The median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations.
The rise edge rate of SD1_REF_CLKn_P must be compared to the fall edge rate of SD1_REF_CLKn_N, the maximum
allowed difference should not exceed 20% of the slowest edge rate. See Figure 93.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
217
Electrical characteristics
This table lists the AC requirements for SerDes reference clocks for protocols running at
data rates greater than 8 GBaud.
This includes XFI (10.3125 GBaud), SerDes reference clocks to be guaranteed by the
customer's application design.
Table 131. SD1_REF_CLKn_P/ SD1_REF_CLKn_N input clock requirements (S1VDD)1
Parameter
Symbol
tCLK_REF
tCLK_TOL
Min
Typ
156.25
Max
Unit
MHz
Notes
SD1_REF_CLKn_P/ SD1_REF_CLKn_N frequency range
-
-
2
SD1_REF_CLKn_P/ SD1_REF_CLKn_N clock frequency
tolerance
-100
-
100
ppm
-
SD1_REF_CLKn_P/ SD1_REF_CLKn_N reference clock
duty cycle
tCLK_DUTY 40
50
-
60
%
3
SD1_REF_CLKn_P/ SD1_REF_CLKn_N single side band
noise
@1 kHz
-
-
-
-
-
-
-
-
-85
dBC/Hz 4
dBC/Hz 4
dBC/Hz 4
dBC/Hz 4
dBC/Hz 4
SD1_REF_CLKn_P/ SD1_REF_CLKn_N single side band
noise
@10 kHz
-
-108
-128
-138
-138
0.8
SD1_REF_CLKn_P/ SD1_REF_CLKn_N single side band
noise
@100
kHz
-
SD1_REF_CLKn_P/ SD1_REF_CLKn_N single side band
noise
@1 MHz
-
SD1_REF_CLKn_P/ SD1_REF_CLKn_N single side band
noise
@10MHz
-
SD1_REF_CLKn_P/ SD1_REF_CLKn_N random jitter (1.2 tCLK_RJ
MHz to 15 MHz)
-
ps
-
-
-
SD1_REF_CLKn_P/ SD1_REF_CLKn_N total reference
clock jitter at 10-12 BER (1.2 MHz to 15 MHz)
tCLK_TJ
-
11
ps
SD1_REF_CLKn_P/ SD1_REF_CLKn_N spurious noise (1.2 -
MHz to 15 MHz)
-
-75
dBC
Notes:
1. For recommended operating conditions, see Table 5.
2. Caution: Only 156.25 have been tested. In-between values do not work correctly with the rest of the system.
3. Measurement taken from differential waveform.
4. Per XFP Spec. Rev 4.5, the Module Jitter Generation spec at XFI Optical Output is 10mUI (RMS) and 100 mUI (p-p). In the
CDR mode the host is contributing 7 mUI (RMS) and 50 mUI (p-p) jitter.
This figure shows the differential measurement points for rise and fall time.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
218
NXP Semiconductors
Electrical characteristics
Rise-edge rate
Fall-edge rate
VIH = +150 mV
0.0 V
VIL = -150 mV
SD1_REF_CLKn_P -
SD1_REF_CLKn_N
Figure 92. Differential measurement points for rise and fall time
This figure shows the single-ended measurement points for rise and fall time matching.
SD1_REF_CLKn_N
SD1_REF_CLKn_N
T
T
RISE
FALL
VCROSS MEDIAN +75 mV
VCROSS MEDIAN
VCROSS MEDIAN
VCROSS MEDIAN -75 mV
SD1_REF_CLKn_P
SD1_REF_CLKn_P
Figure 93. Single-ended measurement points for rise and fall time matching
3.25.3 SerDes transmitter and receiver reference circuits
This figure shows the reference circuits for SerDes data lane's transmitter and receiver.
SDn_TXn_P
SDn_RXn_P
50 Ω
50 Ω
Transmitter
100 Ω
Receiver
SDn_TXn_N
SDn_RXn_N
Figure 94. SerDes transmitter and receiver reference circuits
The DC and AC specifications of the SerDes data lanes are defined in each interface
protocol section below based on the application usage:
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
219
Electrical characteristics
• PCI Express
• Serial ATA (SATA) interface
• SGMII interface
• QSGMII interface
• XFI interface
Note that an external AC-coupling capacitor is required for the above serial transmission
protocols with the capacitor value defined in the specification of each protocol section.
3.25.4 PCI Express
This section describes the clocking dependencies, as well as the DC and AC electrical
specifications for the PCI Express bus.
3.25.4.1 Clocking dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 ppm of
each other at all times. This is specified to allow bit rate clock sources with a 300 ppm
tolerance.
3.25.4.2 PCI Express DC physical layer specifications
This section contains the DC specifications for the physical layer of PCI Express on this
chip.
3.25.4.2.1 PCI Express DC physical layer transmitter specifications
This section discusses the PCI Express DC physical layer transmitter specifications for
2.5 GT/s and 5 GT/s.
This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential
output at all transmitters. The parameters are specified at the component pins.
Table 132. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications
(X1VDD = 1.35 V)1
Parameter
Symbol
Min Typical Max Units
Notes
Differential peak-to-peak
output voltage
VTX-DIFFp-p
800
1000
1200 mV
VTX-DIFFp-p = 2 x │ VTX-D+ - VTX-D- │
De-emphasized differential VTX-DE-RATIO 3.0
output voltage (ratio)
3.5
4.0 dB
Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by the VTX-
DIFFp-p of the first bit after a transition.
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
220
NXP Semiconductors
Electrical characteristics
Table 132. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications
(X1VDD = 1.35 V)1 (continued)
Parameter
Symbol
Min Typical Max Units
Notes
DC differential transmitter ZTX-DIFF-DC 80
impedance
100
120
Ω
Transmitter DC differential mode low Impedance
Transmitter DC impedance ZTX-DC
40
50
60
Ω
Required transmitter D+ as well as D- DC
Impedance during all states
Notes:
1. For recommended operating conditions, see Table 5.
This table defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential
output at all transmitters. The parameters are specified at the component pins.
Table 133. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications (X1VDD
= 1.35 V)1
Parameter
Symbol
VTX-DIFFp-p
Min Typical Max Units
Notes
Differential peak-to-peak
output voltage
800
1000
1200 mV
VTX-DIFFp-p = 2 x │ VTX-D+ - VTX-D-
│
│
Low power differential
peak-to-peak output
voltage
VTX-DIFFp-p_low
400
500
1200 mV
VTX-DIFFp-p = 2 x │ VTX-D+ - VTX-D-
De-emphasized differential VTX-DE-RATIO-3.5dB 3.0
output voltage (ratio)
3.5
6.0
4.0
6.5
dB
dB
Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition.
De-emphasized differential VTX-DE-RATIO-6.0dB 5.5
output voltage (ratio)
Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition.
DC differential transmitter ZTX-DIFF-DC
impedance
80
40
100
50
120
60
Ω
Ω
Transmitter DC differential mode low
impedance
Transmitter DC
Impedance
ZTX-DC
Required transmitter D+ as well as D- DC
impedance during all states
Notes:
1. For recommended operating conditions, see Table 5.
3.25.4.2.2 PCI Express DC physical layer receiver specifications
This section discusses the PCI Express DC physical layer receiver specifications for 2.5
GT/s and 5 GT/s.
This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential
input at all receivers. The parameters are specified at the component pins.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
221
Electrical characteristics
Table 134. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (S1VDD)4
Parameter
Symbol
VRX-DIFFp-p
Min
Typ
Max Units
Notes
Differential input peak-to-peak
voltage
120 1000
1200 mV
VRX-DIFFp-p = 2 x |VRX-D+ - VRX-D-| See
Note 1.
DC differential input impedance
ZRX-DIFF-DC
ZRX-DC
80
40
100
50
120
60
Ω
Ω
Receiver DC differential mode
impedance. See Note 2
DC input impedance
Required receiver D+ as well as D- DC
Impedance (50 20% tolerance). See
Notes 1 and 2.
Powered down DC input impedance ZRX-HIGH-IMP-DC 50
-
-
-
kΩ
Required receiver D+ as well as D- DC
Impedance when the receiver
terminations do not have power. See
Note 3.
Electrical idle detect threshold
VRX-IDLE-DET-
65
175 mV
VRX-IDLE-DET-DIFFp-p = 2 x |VRX-D+ -VRX-
|
DIFFp-p
D-
Measured at the package pins of the
receiver
Notes:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This
helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must
be measured at 300 mV above the receiver ground.
4. For recommended operating conditions, see Table 5.
This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential
input at all receivers. The parameters are specified at the component pins.
Table 135. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (S1VDD)4
Parameter
Symbol
Min
Typ
Max Units
Notes
Differential input peak-to-peak voltage VRX-DIFFp-p
120 1000
1200 mV
VRX-DIFFp-p = 2 x |VRX-D+ - VRX-D-
See Note 1.
|
DC differential input impedance
DC input impedance
ZRX-DIFF-DC
ZRX-DC
80
40
100
50
120
60
Ω
Ω
Receiver DC differential mode
impedance. See Note 2
Required receiver D+ as well as D-
DC Impedance (50 20%
tolerance). See Notes 1 and 2.
Powered down DC input impedance
Electrical idle detect threshold
ZRX-HIGH-IMP-DC 50
-
-
-
kΩ
Required receiver D+ as well as D-
DC Impedance when the receiver
terminations do not have power.
See Note 3.
VRX-IDLE-DET-
65
175 mV
VRX-IDLE-DET-DIFFp-p = 2 x |VRX-D+
VRX-D-
-
|
DIFFp-p
Measured at the package pins of
the receiver
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
222
NXP Semiconductors
Electrical characteristics
Table 135. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (S1VDD)4
(continued)
Parameter
Symbol
Min
Typ
Max Units
Notes
Notes:
1. Measured at the package pins with a test load of 50 Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This
helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must
be measured at 300 mV above the receiver ground.
4. For recommended operating conditions, see Table 5 .
3.25.4.3 PCI Express AC physical layer specifications
This section describes the AC specifications for the physical layer of PCI Express on this
device.
3.25.4.3.1 PCI Express AC physical layer transmitter specifications
This section discusses the PCI Express AC physical layer transmitter specifications for
2.5 GT/s and 5 GT/s.
This table defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential
output at all transmitters. The parameters are specified at the component pins. The AC
timing specifications do not include RefClk jitter.
Table 136. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC specifications4
Parameter
Unit interval
Symbol
Min
Typ
Max
Units
Notes
UI
399.88 400 400.12 ps
Each UI is 400 ps 300 ppm. UI does not
account for spread-spectrum clock dictated
variations.
Minimum transmitter eye
width
TTX-EYE
0.75
-
-
-
UI
The maximum transmitter jitter can be
derived as TTX-MAX-JITTER = 1 - TTX-EYE
=
0.25 UI. Does not include spread-spectrum
or RefCLK jitter. Includes device random
jitter at 10-12
.
See Notes 1 and 2.
Maximum time between the TTX-EYE-MEDIAN-
-
0.125 UI
Jitter is defined as the measurement
jitter median and maximum
deviation from the median
variation of the crossing points (VTX-DIFFp-p
0 V) in relation to a recovered transmitter
UI. A recovered transmitter UI is calculated
over 3500 consecutive unit intervals of
sample data. Jitter is measured using all
=
to- MAX-JITTER
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
223
Electrical characteristics
Table 136. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC specifications4
(continued)
Parameter
Symbol
Min
Typ
Max
Units
Notes
edges of the 250 consecutive UI in the
center of the 3500 UI used for calculating
the transmitter UI. See Notes 1 and 2.
AC coupling capacitor
CTX
75
-
200
nF
All transmitters must be AC coupled. The
AC coupling is required either within the
media or within the transmitting component
itself. See Note 3.
Notes:
1. Specified at the measurement point into a timing and voltage test load as shown in Test and measurement load and
measured over any 250 consecutive transmitter UIs.
2. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the
transmitter collected over any 250 consecutive transmitter UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the
total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the
same as the mean. The jitter median describes the point in time where the number of jitter points on either side is
approximately equal as opposed to the averaged time value.
3. The chip's SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
4. For recommended operating conditions, see Table 5.
This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential
output at all transmitters. The parameters are specified at the component pins. The AC
timing specifications do not include RefClk jitter.
Table 137. PCI Express 2.0 (5 GT/s) differential transmitter output AC specifications3
Parameter
Unit Interval
Symbol
Min
Typ
Max Units
Notes
UI
199.94 200.00 200.06 ps
Each UI is 200 ps 300 ppm. UI does not
account for spread-spectrum clock dictated
variations.
Minimum transmitter eye width TTX-EYE
0.75
-
-
UI
The maximum transmitter jitter can be
derived as: TTX-MAX-JITTER = 1 - TTX-EYE
0.25 UI.
=
See Note 1.
-
Transmitter RMS deterministic TTX-HF-DJ-DD
jitter > 1.5 MHz
-
-
0.15
-
UI
ps
nF
Transmitter RMS deterministic TTX-LF-RMS
jitter < 1.5 MHz
-
3.0
-
Reference input clock RMS jitter (< 1.5
MHz) at pin < 1 ps
AC coupling capacitor
CTX
75
200
All transmitters must be AC coupled. The
AC coupling is required either within the
media or within the transmitting component
itself. See Note 2.
Notes:
1. Specified at the measurement point into a timing and voltage test load as shown in Test and measurement load and
measured over any 250 consecutive transmitter UIs.
2. The chip's SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
3. For recommended operating conditions, see Table 5.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
224
NXP Semiconductors
Electrical characteristics
3.25.4.3.2 PCI Express AC physical layer receiver specifications
This section discusses the PCI Express AC physical layer receiver specifications for 2.5
GT/s and 5 GT/s.
This table defines the AC specifications for the PCI Express 2.0 (2.5 GT/s) differential
input at all receivers. The parameters are specified at the component pins. The AC timing
specifications do not include RefClk jitter.
Table 138. PCI Express 2.0 (2.5 GT/s) differential receiver input AC specifications4
Parameter
Unit Interval
Symbol
Min
Typ
Max
Units
Notes
UI
399.88 400.00 400.12 ps
Each UI is 400 ps 300 ppm. UI does not
account for spread-spectrum clock
dictated variations.
Minimum receiver eye width TRX-EYE
0.4
-
-
-
UI
UI
The maximum interconnect media and
transmitter jitter that can be tolerated by
the receiver can be derived as TRX-MAX-
JITTER = 1 - TRX-EYE= 0.6 UI.
See Notes 1 and 2.
Maximum time between the TRX-EYE-MEDIAN-
-
0.3
Jitter is defined as the measurement
variation of the crossing points (VRX-DIFFp-p
= 0 V) in relation to a recovered
jitter median and maximum
deviation from the median.
to-MAX-JITTER
transmitter UI. A recovered transmitter UI
is calculated over 3500 consecutive unit
intervals of sample data. Jitter is
measured using all edges of the 250
consecutive UI in the center of the 3500
UI used for calculating the transmitter UI.
See Notes 1, 2 and 3.
Notes:
1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Test and measurement
load must be used as the receiver device when taking measurements. If the clocks to the receiver and transmitter are not
derived from the same reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as a reference
for the eye diagram.
2. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget
collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same as the mean. The jitter
median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the
averaged time value. If the clocks to the receiver and transmitter are not derived from the same reference clock, the
transmitter UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
3. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a
fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental
and simulated data.
4. For recommended operating conditions, see Table 5.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
225
Electrical characteristics
This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential
input at all receivers. The parameters are specified at the component pins. The AC timing
specifications do not include RefClk jitter.
Table 139. PCI Express 2.0 (5 GT/s) differential receiver input AC specifications1
Parameter
Unit Interval
Symbol
Min
Typ
Max
Units
Notes
UI
199.40 200.00 200.06 ps
Each UI is 200 ps 300 ppm. UI does
not account for spread-spectrum clock
dictated variations.
Max receiver inherent timing TRX-TJ-CC
error
-
-
-
-
0.4
UI
UI
The maximum inherent total timing error
for common RefClk receiver architecture
Max receiver inherent
TRX-DJ-DD-CC
0.30
The maximum inherent deterministic
timing error for common RefClk receiver
architecture
deterministic timing error
Note:
1. For recommended operating conditions, see Table 5.
0.03 MHz
100 MHz
Sj sweep range
1.0 UI
0.1 UI
20 dB
decade
Sj
Rj
~ 3.0 ps RMS
0.01 MHz
0.1 MHz
1.0 MHz
10 MHz
100 MHz
1000 MHz
Figure 95. Swept sinusoidal jitter mask
3.25.4.4 Test and measurement load
The AC timing and voltage parameters must be verified at the measurement point. The
package pins of the device must be connected to the test/measurement load within 0.2
inches of that load, as shown in the following figure.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
226
NXP Semiconductors
Electrical characteristics
NOTE
The allowance of the measurement point to be within 0.2 inches
of the package pins is meant to acknowledge that package/
board routing may benefit from D+ and D- not being exactly
matched in length at the package pin boundary. If the vendor
does not explicitly state where the measurement point is
located, the measurement point is assumed to be the D+ and D-
package pins.
D + package pin
C = CTX
Transmitter
silicon
+ package
C = CTX
D - package pin
R = 50 Ω
R = 50 Ω
Figure 96. Test and measurement load
3.25.5 Serial ATA (SATA) interface
This section describes the DC and AC electrical specifications for the SATA interface.
3.25.5.1 SATA DC electrical characteristics
This section describes the DC electrical characteristics for SATA.
3.25.5.1.1 SATA DC transmitter output characteristics
This table provides the differential transmitter output DC characteristics for the SATA
interface at Gen1i/1m or 1.5 Gbits/s transmission.
Table 140. Gen1i/1m 1.5 G transmitter DC specifications (X1VDD = 1.35 V)3
Parameter
Symbol
Min
Typ
Max
Units
Notes
Tx differential output voltage
VSATA_TXDIFF
400
85
500
100
600
115
mV p-p
1
2
Tx differential pair impedance
NXP Semiconductors
ZSATA_TXDIFFIM
Ω
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
227
Electrical characteristics
Table 140. Gen1i/1m 1.5 G transmitter DC specifications (X1VDD = 1.35 V)3 (continued)
Parameter
Symbol
Min
Typ
Max
Units
Notes
Notes:
1. Terminated by 50 Ω load.
2. DC impedance.
3. For recommended operating conditions, see Table 5.
This table provides the differential transmitter output DC characteristics for the SATA
interface at Gen2i/2m or 3.0 Gbits/s transmission.
Table 141. Gen 2i/2m 3 G transmitter DC specifications (X1VDD = 1.35 V)2
Parameter
Symbol
Min
Typ
Max
Units
Notes
Transmitter differential output voltage
VSATA_TXDIFF
400
85
—
700
115
mV p-p
1
Transmitter differential pair impedance
Notes:
ZSATA_TXDIFFIM
100
Ω
—
1. Terminated by 50 Ω load.
2. For recommended operating conditions, see Table 5.
This table provides the differential transmitter output DC characteristics for the SATA
interface at Gen 3i transmission.
Table 142. Gen 3i transmitter DC specifications (X1VDD = 1.35 V)2
Parameter
Transmitter differential output voltage
Transmitter differential pair impedance
Notes:
Symbol
VSATA_TXDIFF
ZSATA_TXDIFFIM
Min
Typ
Max
Units
mV p-p
Ω
Notes
240
85
—
900
115
1
100
—
1. Terminated by 50 Ω load.
2. For recommended operating conditions, see Table 5.
3.25.5.1.2 SATA DC receiver input characteristics
This table provides the Gen1i/1m or 1.5 Gbits/s differential receiver input DC
characteristics for the SATA interface.
Table 143. Gen1i/1m 1.5 G receiver input DC specifications (S1VDD)3
Parameter
Symbol
Min
Typical
Max
Units
mV p-p
Ω
Notes
Differential input voltage
VSATA_RXDIFF
240
85
500
100
600
115
1
2
Differential receiver input impedance ZSATA_RXSEIM
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
228
NXP Semiconductors
Electrical characteristics
Table 143. Gen1i/1m 1.5 G receiver input DC specifications (S1VDD)3 (continued)
Parameter
OOB signal detection threshold
Notes:
Symbol
VSATA_OOB
Min
Typical
Max
Units
Notes
50
120
240
mV p-p
—
1. Voltage relative to common of either signal comprising a differential pair.
2. DC impedance.
3. For recommended operating conditions, see Table 5.
This table provides the Gen2i/2m or 3 Gbits/s differential receiver input DC
characteristics for the SATA interface.
Table 144. Gen2i/2m 3 G receiver input DC specifications (S1VDD)3
Parameter
Differential input voltage
Differential receiver input impedance
OOB signal detection threshold
Notes:
Symbol
VSATA_RXDIFF
ZSATA_RXSEIM
VSATA_OOB
Min
Typical
Max
Units
mV p-p
Notes
240
85
—
750
115
240
1
2
2
100
120
Ω
75
mV p-p
1. Voltage relative to common of either signal comprising a differential pair.
2. DC impedance.
3. For recommended operating conditions, see Table 5.
This table provides the Gen 3i differential receiver input DC characteristics for the SATA
interface.
Table 145. Gen 3i receiver input DC specifications (S1VDD)3
Parameter
Symbol
Min
Typical
Max
Units
mV p-p
Ω
Notes
Differential input voltage
VSATA_RXDIFF
240
85
—
1000
115
1
2
Differential receiver input impedance ZSATA_RXSEIM
100
120
OOB signal detection threshold
—
75
200
mV p-p
—
Notes:
1. Voltage relative to common of either signal comprising a differential pair.
2. DC impedance.
3. For recommended operating conditions, see Table 5.
3.25.5.2 SATA AC timing specifications
This section describes the SATA AC timing specifications.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
229
Electrical characteristics
3.25.5.2.1 AC requirements for SATA REF_CLK
This table provides the AC requirements for the SATA reference clock. These
requirements must be guaranteed by the customer's application design.
Table 146. SATA reference clock input requirements6
Parameter
Symbol
Min
Typ
Max
Unit
MHz
Notes
SD1_REF_CLK1_P/SD1_REF_CLK1_N
frequency range
tCLK_REF
—
100/125
—
1
SD1_REF_CLK1_P/SD1_REF_CLK1_N clock tCLK_TOL
frequency tolerance
-350
40
—
50
—
—
+350
60
ppm
%
—
5
SD1_REF_CLK1_P/SD1_REF_CLK1_N
reference clock duty cycle
tCLK_DUTY
SD1_REF_CLK1_P/SD1_REF_CLK1_N cycle- tCLK_CJ
to-cycle clock jitter (period jitter)
—
100
+50
ps
2
SD1_REF_CLK1_P/SD1_REF_CLK1_N total
reference clock jitter, phase jitter (peak-to-peak)
tCLK_PJ
-50
ps
2, 3, 4
Notes:
1. Caution: Only 100 and 125 MHz have been tested. In-between values do not work correctly with the rest of the system.
2. At RefClk input.
3. In a frequency band from 150 kHz to 15 MHz at BER of 10-12
.
4. Total peak-to-peak deterministic jitter must be less than or equal to 50 ps.
5. Measurement taken from differential waveform.
6. For recommended operating conditions, see Table 5.
3.25.5.2.2 AC transmitter output characteristics
This table provides the differential transmitter output AC characteristics for the SATA
interface at Gen 1i/1m or 1.5 Gbits/s transmission. The AC timing specifications do not
include RefClk jitter.
Table 147. Gen 1i/1m 1.5 G transmitter AC specifications2
Parameter
Channel speed
Symbol
tCH_SPEED
Min
Typ
Max
Units
Gbps
Notes
—
1.5
—
—
Unit interval
TUI
666.4333
666.6667
670.2333
0.355
0.47
ps
—
1
Total jitter data-data 5 UI
Total jitter, data-data 250 UI
Deterministic jitter, data-data 5 UI
Deterministic jitter, data-data 250 UI
Notes:
USATA_TXTJ5UI
USATA_TXTJ250UI
USATA_TXDJ5UI
USATA_TXDJ250UI
—
—
—
—
—
—
—
—
UI p-p
UI p-p
UI p-p
UI p-p
1
0.175
0.22
1
1
1. Measured at transmitter output pins peak-to-peak phase variation; random data pattern.
2. For recommended operating conditions, see Table 5.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
230
NXP Semiconductors
Electrical characteristics
This table provides the differential transmitter output AC characteristics for the SATA
interface at Gen 2i/2m or 3.0 Gbits/s transmission. The AC timing specifications do not
include RefClk jitter.
Table 148. Gen 2i/2m 3 G transmitter AC specifications2
Parameter
Channel speed
Symbol
tCH_SPEED
Min
Typ
Max
Units
Gbps
Notes
—
3.0
—
—
Unit Interval
TUI
333.2167
333.3333
335.1167
0.37
ps
—
1
Total jitter fC3dB = fBAUD ꢀ 500
Total jitter fC3dB = fBAUD ꢀ 1667
USATA_TXTJfB/500
USATA_TXTJfB/1667
—
—
—
—
—
—
—
—
UI p-p
UI p-p
UI p-p
UI p-p
0.55
1
Deterministic jitter, fC3dB = fBAUD ꢀ 500 USATA_TXDJfB/500
0.19
1
Deterministic jitter, fC3dB = fBAUD
1667
ꢀ
USATA_TXDJfB/1667
0.35
1
Notes:
1. Measured at transmitter output pins peak-to-peak phase variation; random data pattern.
2. For recommended operating conditions, see Table 5.
This table provides the differential transmitter output AC characteristics for the SATA
interface at Gen 3i transmission. The AC timing specifications do not include RefClk
jitter.
Table 149. Gen 3i transmitter AC specifications
Parameter
Symbol
Min
Typ
Max
Units
Gb/s
Speed
—
—
—
—
6.0
—
—
Total jitter before and after compliance interconnect channel JT
0.52
0.18
UI p-p
UI p-p
Random jitter before compliance interconnect channel
Unit interval
JR
UI
—
166.6083 166.6667 167.5583 ps
3.25.5.2.3 AC differential receiver input characteristics
This table provides the Gen1i/1m or 1.5 Gbits/s differential receiver input AC
characteristics for the SATA interface. The AC timing specifications do not include
RefClk jitter.
Table 150. Gen 1i/1m 1.5 G receiver AC specifications2
Parameter
Symbol
Min
Typical
Max
670.2333
0.43
Units
ps
Notes
Unit Interval
TUI
666.4333
666.6667
—
Total jitter data-data 5 UI
USATA_RXTJ5UI
USATA_RXTJ250UI
USATA_RXDJ5UI
—
—
—
—
—
—
UI p-p
UI p-p
UI p-p
1
1
1
Total jitter, data-data 250 UI
Deterministic jitter, data-data 5 UI
0.60
0.25
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
231
Hardware design considerations
Table 150. Gen 1i/1m 1.5 G receiver AC specifications2 (continued)
Parameter
Symbol
Min
Typical
Max
Units
Notes
Deterministic jitter, data-data 250 UI USATA_RXDJ250UI
Notes:
—
—
0.35
UI p-p
1
1. Measured at the receiver.
2. For recommended operating conditions, see Table 5.
This table provides the differential receiver input AC characteristics for the SATA
interface at Gen2i/2m or 3.0 Gbits/s transmission. The AC timing specifications do not
include RefClk jitter.
Table 151. Gen 2i/2m 3 G receiver AC specifications2
Parameter
Symbol
Min
Typical
Max
335.1167
0.60
Units
ps
Notes
Unit Interval
TUI
USATA_RXTJfB/500
USATA_RXTJfB/1667
333.2167
333.3333
—
Total jitter fC3dB = fBAUD ꢀ 500
Total jitter fC3dB = fBAUD ꢀ 1667
—
—
—
—
—
—
—
—
UI p-p
UI p-p
UI p-p
UI p-p
1
1
1
1
0.65
Deterministic jitter, fC3dB = fBAUD ꢀ 500 USATA_RXDJfB/500
Deterministic jitter, fC3dB = fBAUD ꢀ 1667 USATA_RXDJfB/1667
Notes:
0.42
0.35
1. Measured at the receiver.
2. For recommended operating conditions, see Table 5.
This table provides the differential receiver input AC characteristics for the SATA
interface at Gen 3i transmission The AC timing specifications do not include RefClk
jitter.
Table 152. Gen 3i receiver AC specifications2
Parameter
Symbol
Min
Typical
Max
Units
Notes
Total jitter after compliance
interconnect channel
JT
JR
UI
—
—
—
—
0.60
0.18
UI p-p
1
1
Random jitter before compliance
interconnect channel
UI p-p
ps
Unit interval: 6.0 Gb/s
Notes:
166.6083
166.6667
167.5583
—
1. Measured at the receiver.
2. The AC specifications do not include RefClk jitter.
4 Hardware design considerations
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
232
NXP Semiconductors
Hardware design considerations
4.1 System clocking
This section describes the PLL configuration of the chip.
4.1.1 PLL characteristics
Characteristics of the chip's PLLs include the following:
• Core cluster CGA PLL1 generates a clock for all the cores and/or FMAN, from the
externally supplied SYSCLK or LVDS generated (single ended) input.
• Core cluster CGA PLL2 generates a clock for all the cores and/or FMAN & eSDHC,
from the externally supplied SYSCLK or LVDS generated (single ended) input.
• The frequency ratio between the platform and SYSCLK is selected using the
platform PLL ratio configuration bits as described in Platform to SYSCLK PLL
ratio.
• The DDR block PLL generates an asynchronous DDR clock from the externally
supplied DDRCLK input.
• The 4 lane SerDes blocks has two PLLs which generate a clock from their respective
externally supplied SD1_REF_CLKn_P/SD1_REF_CLKn_N inputs. The frequency
ratio is selected using the SerDes PLL RCW configuration bits as described in Valid
reference clocks and PLL configurations for SerDes protocols .
4.1.2 Clock ranges
This table provides the clocking specifications for the processor core, platform, memory,
and integrated flash controller.
Table 153. Processor, platform, and memory clocking specifications (VDD = 0.9 V)
Characteristic
Maximum processor core frequency
1000 MHz 1200 MHz
Min Max Min Max
Unit
Notes
Core cluster group PLL frequency
Platform clock frequency
Memory Bus Clock Frequency (DDR3L)
Memory Bus Clock Frequency (DDR4)
IFC clock frequency
1000
256
500
650
-
1000
300
650
650
100
500
1000
256
500
650
-
1200
300
650
650
100
500
MHz
MHz
MHz
MHz
MHz
MHz
1
1
1, 2, 3
1, 3
4
-
FMan
350
350
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
233
Hardware design considerations
Table 153. Processor, platform, and memory clocking specifications (VDD = 0.9 V)
(continued)
Characteristic
Maximum processor core frequency
1000 MHz 1200 MHz
Min Max Min Max
Unit
Notes
1. Caution:The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting
SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum
operating frequencies.
2. The memory bus clock speed is half the DDR3L/DDR4 data rate. DDR3L memory bus clock frequency is limited to min =
1000 MT/s whereas DDR4 memory bus clock frequency is limited to min/max = 1300 MT/s.
3. The memory bus clock speed is dictated by its own PLL.
4. The integrated flash controller (IFC) clock speed on IFC_CLK[0:1] is determined by the IFC module input clock (platform
clock / 2) divided by the IFC ratio programmed in CCR[CLKDIV]. See the chip reference manual for more information.
5. The minimum platform frequency should meet the requirements in Minimum platform frequency requirements for high-
speed interfaces.
6. For supported voltage/frequency options, refer to orderable part list of QorIQ LS1043A and LS1023A Multicore
Communications Processors at www.nxp.com
Table 154. Processor, platform, and memory clocking specifications (VDD = 1.0 V)
Characteristic
Maximum processor core frequency
1200 MHz 1400 MHz
Min Max Min Max
Unit
Notes
1000 MHz
Min Max
1600 MHz
Min Max
1000 1600 MHz
Core cluster group PLL
frequency
1000
1000
1000
1200
1000
1400
1
Platform clock frequency
256
500
300
800
256
500
300
800
256
500
300
800
256
500
400
800
MHz
1
Memory Bus Clock Frequency
(DDR3L)
MHz
1, 2, 3
Memory Bus Clock Frequency
(DDR4)
650
800
650
800
650
800
650
800
MHz
1, 3
4
IFC clock frequency
FMan
-
100
500
-
100
500
-
100
500
-
100
500
MHz
MHz
350
350
350
350
1. Caution:The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting
SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum
operating frequencies.
2. The memory bus clock speed is half the DDR3L/DDR4 data rate. DDR3L memory bus clock frequency is limited to min =
1000 MT/s whereas DDR4 memory bus clock frequency is limited to min = 1300 MT/s.
3. The memory bus clock speed is dictated by its own PLL.
4. The integrated flash controller (IFC) clock speed on IFC_CLK[0:1] is determined by the IFC module input clock (platform
clock / 2) divided by the IFC ratio programmed in CCR[CLKDIV]. See the chip reference manual for more information.
5. The minimum platform frequency should meet the requirements in Minimum platform frequency requirements for high-
speed interfaces.
6. For supported voltage/frequency options, refer to orderable part list of QorIQ LS1043A and LS1023A Multicore
Communications Processors at www.nxp.com
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
234
NXP Semiconductors
Hardware design considerations
4.1.2.1 DDR clock ranges
The DDR memory controller can run only in asynchronous mode, where the memory bus
is clocked with the clock provided on the DDRCLK input pin, which has its own
dedicated PLL.
This table provides the clocking specifications for the memory bus.
Table 155. Memory bus clocking specifications
Characteristic
Min Freq.(MHz)
Max Freq.(MHz)
Min Data Rate
(MT/s)
Max Data Rate
(MT/s)
Notes
Memory bus clock 500
frequency and Data
Rate for DDR3L
800
1000
1600
1, 2, 3
1, 2, 3
Memory bus clock 650
frequency and Data
Rate for DDR4
800
1300
1600
Notes:
1. Caution: The platform clock to SYSCLK ratio and core to platform clock ratio settings must be chosen such that the
resulting SYSCLK frequency, core frequency, and platform frequency do not exceed their respective maximum or minimum
operating frequencies. See Platform to SYSCLK PLL ratio, and Core cluster to SYSCLK PLL ratio, and DDR controller PLL
ratios, for ratio settings.
2. The memory bus clock refers to the chip's memory controllers' Dn_MCK[0:3] and Dn_MCK[0:3]_B output clocks, running at
half of the DDR data rate.
3. The memory bus clock speed is dictated by its own PLL. See DDR controller PLL ratios.
4. For supported voltage/frequency options, refer to orderable part list of QorIQ LS1043A and LS1023A Multicore
Communications Processors at www.nxp.com
4.1.3 Platform to SYSCLK PLL ratio
This table lists the allowed platform clock to SYSCLK ratios.
Because the DDR operates asynchronously, the memory-bus clock-frequency is
decoupled from the platform bus frequency.
For all valid platform frequencies supported on this chip, set the RCW Configuration
field SYS_PLL_CFG = 0b00.
Table 156. Platform to SYSCLK PLL ratios
Binary Value of SYS_PLL_RAT
Platform:SYSCLK Ratio
0_0011
0_0100
0_0101
3:1
4:1
5:1
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
235
Hardware design considerations
Table 156. Platform to SYSCLK PLL ratios
(continued)
Binary Value of SYS_PLL_RAT
Platform:SYSCLK Ratio
0_0110
All Others
Notes:
6:1
Reserved
1. For supported voltage/frequency options, refer to orderable part list of QorIQ LS1043A and LS1023A Multicore
Communications Processors at www.nxp.com.
4.1.4 Core cluster to SYSCLK PLL ratio
The clock ratio between SYSCLK and each of the core cluster PLLs is determined by the
binary value of the RCW Configuration field CGm_PLLn_RAT. This table describes the
supported ratios. For all valid core cluster frequencies supported on this chip, set the
RCW Configuration field CGn_PLL_CFG = 0b00.
This table below lists the supported asynchronous core cluster to SYSCLK ratios.
Table 157. Core cluster PLL to SYSCLK ratios
Binary value of CGm_PLLn_RAT
00_1010
Core cluster:SYSCLK Ratio
10:1
11:1
12:1
13:1
14:1
15:1
16:1
17:1
18:1
19:1
20:1
21:1
22:1
23:1
24:1
25:1
Reserved
00_1011
00_1100
00_1101
00_1110
00_1111
01_0000
01_0001
01_0010
01_0011
01_0100
01_0101
01_0110
01_0111
01_1000
01_1001
All others
Notes:
1. For supported voltage/frequency options, see the orderable part list of QorIQ LS1043A and LS1023A multicore
communications processors at www.nxp.com.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
236
NXP Semiconductors
Hardware design considerations
4.1.5 Core complex PLL select
The clock frequency of each core is determined by the binary value of the RCW
Configuration field C1_PLL_SEL. The tables describe the selections available for each
core, where each individual core can select a frequency from their respective tables.
Table 158. Core PLL select
Binary Value of C1_PLL_SEL
Core cluster ratio
0000
0001
0100
0101
CGA PLL1 /1
CGA PLL1 /2
CGA PLL2 /1
CGA PLL2 /2
4.1.6 DDR controller PLL ratios
DDR memory controller operates asynchronous to the platform.
In asynchronous DDR mode, the DDR data rate to DDRCLK ratios supported are listed
in the following table. This ratio is determined by the binary value of the RCW
Configuration field MEM_PLL_RAT (bits 10-15).
The RCW Configuration field MEM_PLL_CFG (bits 8-9) must be set to
MEM_PLL_CFG = 0b00 for all valid DDR PLL reference clock frequencies supported
on this chip.
Table 159. DDR clock ratio
Binary value of MEM_PLL_RAT
DDR data-
rate:DDRCLK
ratio
Maximum supported DDR data-rate (MT/s)
00_1010
10:1
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
00_1011
00_1100
00_1101
00_1110
00_1111
11:1
12:1
13:1
14:1
15:1
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
237
Hardware design considerations
Table 159. DDR clock ratio (continued)
Binary value of MEM_PLL_RAT
DDR data-
rate:DDRCLK
ratio
Maximum supported DDR data-rate (MT/s)
01_0000
16:1
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
01_0001
01_0010
01_0011
01_0100
01_0101
01_0110
01_0111
01_1000
17:1
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
18:1
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
19:1
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
20:1
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
21:1
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
22:1
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
23:1
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
24:1
The product of Input DDR Clock X Multiplication factor
should range between 1000 MHz-1600MHz.
All Others
Reserved
-
Notes:
1. For supported voltage/frequency options, refer to orderable part list of QorIQ LS1043A and LS1023A Multicore
Communications Processors at www.nxp.com.
4.1.7 Valid reference clocks and PLL configurations for SerDes
protocols
Each supported SerDes protocol allows for a finite set of valid SerDes-related RCW
fields and reference clock frequencies.
The clock ratio between each SerDes PLLs and their respective externally supplied
SD1_REF_CLKn_P/SD1_REF_CLKn_N inputs is determined by a set of RCW
configuration fields, SRDS_PRTCL_S1, SRDS_PLL_REF_CLK_SEL_S1, and
SRDS_DIV_PEX as shown in this table.
Table 160. Valid SerDes RCW encodings and reference clocks
SerDes protocol
(given lane)
Valid reference
clock frequency SRDS_PRTCL_S1
Valid setting for
Valid setting for SRDS_PLL_REF
_CLK_SEL_S1
Valid setting for
SRDS_DIV_PEX
PLL1
PLL2
High Speed Serial interface
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
238
NXP Semiconductors
Hardware design considerations
Table 160. Valid SerDes RCW encodings and reference clocks (continued)
SerDes protocol
(given lane)
Valid reference
clock frequency SRDS_PRTCL_S1
Valid setting for
Valid setting for SRDS_PLL_REF
_CLK_SEL_S1
Valid setting for
SRDS_DIV_PEX
PLL1
0: 100 MHz
PLL2
0: 100 MHz
PCI Express 2.5
Gbit/s (doesn't
negotiate upwards)
100 MHz
125 MHz
Any PCIe
Any PCIe
10: 2.5 G
01: 5 G
1: 125 MHz
1: 125 MHz
PCI Express 5
Gbit/s (can
negotiate up to 5
Gbit/s)
100 MHz
125 MHz
0: 100 MHz
1: 125 MHz
0: 100 MHz
1: 125 MHz
SATA (1.5, 3, 6
Gbit/s)
100 MHz
125 MHz
Any SATA
0: 100 MHz
1: 125 MHz
-
-
Don't Care
Networking interfaces
SGMII (1.25 Gbit/s) 100 MHz
125 MHz
SGMII @ 1.25
Gbit/s
0: 100 MHz
1: 125 MHz
0: 125 MHz
1: 156.25 MHz
0: 100 MHz
1: 125 MHz
0: 100 MHz
Don't Care
Don't Care
Don't Care
-
1: 125 MHz
2.5 G SGMII (3.125 125 Mhz
Gbit/s)
SGMII @ 3.125
Gbit/s
-
156.25 MHz
-
QSGMII (5 Gbit/s) 100 MHz
125 MHz
Any QSGMII
0: 100 MHz
1: 125 MHz
XFI (10.3125
Gbit/s)
156.25 Mhz
-
-
1: 156.25 MHz
Notes:
1) A spread-spectrum reference clock is permitted for PCI Express. However, if any other high speed interface such as
SGMII, QSGMII, SATA, or Debug is used concurrently on the same SerDes bank, spread-spectrum clocking is not permitted.
2) SerDes lanes configured as SATA initially operate at 3.0 Gbit/s. 1.5 Gbit/s operation may later be enabled through the
SATA IP itself. It is possible for software to set each SATA at different rates.
4.1.8 Frequency options
This section discusses interface frequency options.
4.1.8.1 SYSCLK and core cluster frequency options
This table shows the expected frequency options for SYSCLK and core cluster
frequencies.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
239
Hardware design considerations
Table 161. SYSCLK and core cluster frequency1
Core cluster: SYSCLK Ratio
SYSCLK (MHz)
64.00
66.67
100.00
Core cluster Frequency - (MHz)1
10:1
1000
11:1
12:1
13:1
14:1
15:1
16:1
17:1
18:1
19:1
20:1
21:1
22:1
23:1
24:1
25:1
Notes:
1100
1200
1300
1400
1500
1600
1000
1067
1133
1200
1267
1333
1400
1467
1533
1600
1024
1088
1152
1216
1280
1344
1408
1472
1536
1600
1. Core cluster output is the operating frequency of the core.
2. Core cluster frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed)
3. When using Single Source clocking only 100 MHz input is available.
4. For supported voltage/frequency options, see the orderable part list of QorIQ LS1043A and LS1023A Multicore
Communications Processors at www.nxp.com.
4.1.8.2 SYSCLK and platform frequency options
This table shows the expected frequency options for SYSCLK and platform frequencies.
Table 162. SYSCLK and platform frequency options
Platform: SYSCLK Ratio
SYSCLK (MHz)
64.00
66.67
100.00
Platform Frequency (MHz)1
3:1
4:1
5:1
6:1
300
400
256
320
384
267
333
400
Notes:
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
240
NXP Semiconductors
Hardware design considerations
Table 162. SYSCLK and platform frequency options
Platform: SYSCLK Ratio
SYSCLK (MHz)
64.00
66.67
100.00
Platform Frequency (MHz)1
1. Platform frequency values are shown rounded down to the nearest whole number (decimal place accuracy removed)
2. When using Single source clocking, only 100 MHz options are valid
3. For supported voltage/frequency options, see the orderable part list of QorIQ LS1043A and LS1023A Multicore
Communications Processors at www.nxp.com.
4.1.8.3 DDRCLK and DDR data rate frequency options
This table shows the expected frequency options for DDRCLK and DDR data rate
frequencies.
Table 163. DDRCLK and DDR data rate frequency options
DDR data rate: DDRCLK Ratio
DDRCLK (MHz)
64.00
66.67
100.00
DDR Data Rate (MT/s)1
10:1
1000
1100
1200
1300
1400
1500
1600
11:1
12:1
13:1
14:1
15:1
16:1
17:1
18:1
19:1
20:1
21:1
22:1
23:1
24:1
Notes:
1000
1024
1088
1152
1216
1280
1344
1408
1472
1536
1067
1133
1200
1266
1333
1400
1466
1533
1600
1. DDR data rate values are shown rounded up to the nearest whole number (decimal place accuracy removed)
2. When using Single Source clocking, only 100 MHz options are available.
3. Minimum Frequency supported by DDR4 is 1300 MT/s. DDR3 supports a minimum of 1000 MT/s.
4. For supported voltage/frequency options, see the orderable part list of QorIQ LS1043A and LS1023A Multicore
Communications Processors at www.nxp.com.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
241
Hardware design considerations
4.1.8.4 SYSCLK and eSDHC high speed modes frequency options
This table shows the frequency multiplier options for SYSCLK when eSDHC operates in
High Speed modes (>=52 MHz). For low frequency options CGA PLL2 is bypassed and
eSDHC receives platform clock directly.
Table 164. SYSCLK multiplier/frequency options when eSDHC operates in High Speed
mode (clocked by CGA PLL2 / 1)
Core cluster: SYSCLK Ratio
SYSCLK (MHz)
64.00
66.67
100.00
Resultant Frequency (MHz)1
12:1
1200
18:1
1152
1200
Notes:
1. Resultant frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed)
2. For Low speed operation, eSDHC is clocked from Platform PLL and does not use CGA PLL2.
4.1.8.5 Minimum platform frequency requirements for high-speed
interfaces
The platform clock frequency must be considered for proper operation of high-speed
interfaces as described below:.For proper PCI Express operation, the platform clock
frequency must be greater than or equal to:
527 MHz x (PCI Express link width)
16
Figure 97. Gen 1 PEX minimum platform frequency
527 MHz x (PCI Express link width)
8
Figure 98. Gen 2 PEX minimum platform frequency
See section "Link Width," in the chip reference manual for PCI Express interface width
details. Note that "PCI Express link width" in the above equation refers to the negotiated
link width as the result of PCI Express link training, which may or may not be the same
as the link width POR selection. It refers to the widest port in use, not the combined
width of the number ports in use.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
242
NXP Semiconductors
Hardware design considerations
4.2 Connection recommendations
The following is a list of connection recommendations:
• To ensure reliable operation, it is highly recommended to connect unused inputs to
an appropriate signal level. Unless otherwise noted in this document, all unused
active low inputs should be tied to VDD, TA_BB_VDD, OVDD, TVDD, DVDD, EVDD,
LVDD, G1VDD, S1VDD, X1VDD as required. All unused active high inputs should be
connected to GND. All NC (no-connect) signals must remain unconnected. Power
and ground connections must be made to all external VDD, TA_BB_VDD, OVDD,
TVDD, DVDD, EVDD, LVDD, G1VDD, S1VDD, X1VDD and GND pins of the device.
• The chip has temperature diodes on the microprocessor that can be used in
conjunction with other system temperature monitoring devices (such as Analog
Devices, ADT7461A™). If a temperature diode monitoring device is not connected,
these pins must be connected to GND.
4.2.1 JTAG configuration signals
Correct operation of the JTAG interface requires configuration of a group of system
control pins, as demonstrated in Figure 100. Take care to ensure that these pins are
maintained at a valid deasserted state under normal operating conditions as most have
asynchronous behavior and spurious assertion will give unpredictable results.
The JTAG port of these processors allows a remote computer system (typically, a PC
with dedicated hardware and debugging software) to access and control the internal
operations of the processor. The ARM Cortex 10-pin header connects primarily through
the JTAG port of the processor, with some additional status monitoring signals.
The Cortex Debug Connector has a standard header, as shown in Figure 99. The
connector typically has pin 7 removed as a connector key.
The ARM Cortex 10-pin header adds many benefits, such as breakpoints, watchpoints,
register and memory examination/modification, and other standard debugger features. An
inexpensive option can be to leave the ARM Cortex 10-pin header unpopulated until
needed.
4.2.1.1 Termination of unused signals
If the JTAG interface and ARM Cortex 10-pin header are not used, no pull-up/pull-down
is required for TDI, TMS, or TDO.
This figure shows the ARM Cortex 10-pin header physical pinout.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
243
Hardware design considerations
1
3
5
2
4
TMS
VDD
GND
TCK
GND
6
TDO
KEY
No pin
TDI
KEY
8
GNDDetect
9
10
nRESET
Figure 99. ARM Cortex 10-pin header physical pinout
This figure shows the JTAG interface connection.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
244
NXP Semiconductors
Hardware design considerations
1 kΩ
OVDD
From target
board sources
(if any)
HRESET_B
HRESET_B
PORESET_B
10 kΩ
10 kΩ
PORESET_B
2
nRESET
10
10 kΩ
OVDD
10 kΩ
TRST_B
Other TRST_B source
(for example, boundary scan)
1
3
5
2
4
10 Ω
VDD
1
2
6
KEY
No pin
8
TMS
TDO
9
10
TMS
TDO
TDI
ARM Cortex 10-pin
physical pinout
6
8
4
TDI
TCK
TCK
10 kΩ
GNDDetect1
GND
9
5
3
GND
Note:
1. GNDDetect is an optional board feature. Check with 3rd-party tool vendor.
2. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, ensure this switch is closed.
Figure 100. JTAG interface connection
4.2.2 Guidelines for high-speed interface termination
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
245
Hardware design considerations
4.2.2.1 SerDes interface entirely unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated
as described in this section.
Note that S1VDD, X1VDD , AVDD_SD1_PLL1, and AVDD_SD1_PLL2 must remain
powered.
AVDD_SD1_PLL1 must be connected to X1VDD through a 0-Ω resistor (instead of
through a filter circuit, as shown in Figure 2).
The following pins must be left unconnected:
• SD1_TX[3:0]_P
• SD1_TX[3:0]_N
• SD1_IMP_CAL_RX
• SD1_IMP_CAL_TX
The following pins must be connected to SD_GND:
• SD1_REF_CLK1_P, SD1_REF_CLK2_P
• SD1_REF_CLK1_N, SD1_REF_CLK2_N
It is recommended for the following pins to be connected to SD_GND:
• SD1_RX[3:0]_P
• SD1_RX[3:0]_N
It is possible to disable the SerDes module by disabling all PLLs associated with it. Use
the following method to disable the SerDes module:
• SRDS_PLL_PD_S1 = 2’b11 (Both PLLs are configured as powered down; all data
lanes selected by the protocols defined in SRDS_PRTCL_S1 associated to the PLLs
are powered down, as well.)
• SRDS_PLL_REF_CLK_SEL_S1 = 2’b00
• SRDS_PRTCL_S1 = 2 (No other values are permitted when both PLLs are powered
down.)
4.2.2.2 SerDes interface partly unused
If only part of the high-speed SerDes interface pins are used, the remaining high-speed
serial I/O pins should be terminated as described in this section.
Note that both S1VDD and X1VDD must remain powered.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
246
NXP Semiconductors
Thermal
If any of the PLLs are unused, the corresponding AVDD_SD1_PLL1 and
AVDD_SD1_PLL2 must be connected to X1VDD through a 0-Ω resistor (instead of
through a filter circuit, as shown in Figure 2).
The following unused pins must be left unconnected:
• SD1_TX0_P
• SD1_TX0_N
The following unused pins must be connected to SD_GND:
• SD1_REF_CLKn_P, SD1_REF_CLKn_N (If the entire SerDes is unused.)
It is recommended for the following unused pins to be connected to SD_GND:
• SD1_RX0_P
• SD1_RX0_N
In the RCW configuration field SRDS_PLL_PD_S1, the respective bits for each unused
PLL must be set to power it down. A module is disabled when both its PLLs are turned
off.
Unused lanes must be powered down through the SRDSx Lane m General Control 0
(LNmGCR0) register as follows:
• LNmGCR0[RRST] = 0
• LNmGCR0[TRST] = 0
• LNmGCR0[RX_PD] = 1
• LNmGCR0[TX_PD] = 1
Note that in the case where the SerDes pins are connected to slots, it is acceptable to have
these pins unterminated when unused.
5 Thermal
This table shows the thermal characteristics for the chip. Note that these numbers are
based on design estimates and are preliminary.
Table 165. Package thermal characteristics6
Rating
Board
Symbol
Value
33
Unit
°C/W
Notes
1, 2
Junction to ambient, natural convection
Junction to ambient, natural convection
Junction to ambient (at 200 ft./min.)
Junction to ambient (at 200 ft./min.)
Single-layer board (1s) RΘJA
Four-layer board (2s2p) RΘJA
Single-layer board (1s) RΘJMA
Four-layer board (2s2p) RΘJMA
24
27
20
°C/W
°C/W
°C/W
1, 2
1, 2
1, 2
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
247
Thermal
Table 165. Package thermal characteristics6 (continued)
Rating
Board
Symbol
RΘJB
RΘJCtop
Value
14
<0.1
Unit
°C/W
°C/W
Notes
Junction to board
-
-
3
4
Junction to case (Top)
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package. Board temperature is measured on the top surface of the board near the package.
4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5. See Thermal management information, for additional details.
6. Package thermal characteristics are applicable for the 21x21mm and 23x23mm package.
Table 166. Thermal Resistance with Heat Sink in Open Flow, No Lid4
Heat Sink with Thermal Grease
Air Flow
Thermal
Resistance
°C/W
Wakefield 53 x 53 x 25 mm Pin Fin
Natural Convection
0.5 m/s
6.9
4.3
3.3
2.8
2.5
9.2
5.5
4.6
4.0
3.5
12.9
8.7
6.9
5.4
4.5
9.3
5.9
4.5
3.6
3.0
1.0 m/s
2.0 m/s
4.0 m/s
Aavid 35 x 31 x 23 mm Pin Fin
Aavid 30 x 30 x 9.4 mm Pin Fin
Aavid 43 x 41 x 16.5 mm Pin Fin
Natural Convection
0.5 m/s
1.0 m/s
2.0 m/s
4.0 m/s
Natural Convection
0.5 m/s
1.0 m/s
2.0 m/s
4.0 m/s
Natural Convection
0.5 m/s
1.0 m/s
2.0 m/s
4.0 m/s
1. Simulations with heat sinks were done with package mounted on 2s2p thermal board.
2. Standard thermal interface was a typical thermal grease with thermal resistance 67 C-mm2/W.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
248
NXP Semiconductors
Thermal
Table 166. Thermal Resistance with Heat Sink in Open Flow, No Lid4
Heat Sink with Thermal Grease
Air Flow
Thermal
Resistance
°C/W
3. See Thermal management information, for additional details.
4. Thermal Resistance with Heat Sink in Open Flow (No Lid) are applicable for 21x21mm and 23x23mm package.
5.1 Recommended thermal model
Information about Flotherm models of the package or thermal data not available in this
document can be obtained from your local NXP sales office.
5.2 Temperature diode
The chip has a temperature diode on the microprocessor that can be used in conjunction
with other system temperature monitoring devices (such as Analog Devices,
ADT7461A). These devices feature series resistance cancellation using three current
measurements, where up to 1.5 kΩ of resistance can be automatically cancelled from the
temperature result, allowing noise filtering and a more accurate reading.
The following are the specifications of the chip's on-board temperature diode:
Operating range: 10 - 230 μA
Ideality factor over 13.5 - 220 μA; Temperature range 80°C - 105°C: n = 1.004 0.008
5.3 Thermal management information
This section provides thermal management information for the flip-chip, plastic-ball, grid
array (FC-PBGA) package for air-cooled applications. Proper thermal control design is
primarily dependent on the system-level design-the heat sink, airflow, and thermal
interface material.
The recommended attachment method to the heat sink is illustrated in Figure 101. The
heat sink should be attached to the printed-circuit board with the spring force centered
over the die. This spring force should not exceed 15 pounds force (65 Newton).
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
249
Thermal
FC-PBGA package (no lid)
Heat sink
Heat sink clip
Adhesive or
thermal interface material
Die
Printed circuit-board
Figure 101. Package exploded, cross-sectional view-FC-PBGA (no lid)
The system board designer can choose between several types of heat sinks to place on the
device. There are several commercially-available thermal interfaces to choose from in the
industry. Ultimately, the final selection of an appropriate heat sink depends on many
factors, such as thermal performance at a given air velocity, spatial volume, mass,
attachment method, assembly, and cost.
5.3.1 Internal package conduction resistance
For the package, the intrinsic internal conduction thermal resistance paths are as follows:
• The die junction-to-case thermal resistance
• The die junction-to-board thermal resistance
This figure shows the primary heat transfer path for a package with an attached heat sink
mounted to a printed-circuit board.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
250
NXP Semiconductors
Thermal
External resistance
Radiation Convection
Heat sink
Thermal interface material
Die/Package
Die junction
Internal resistance
Package/Solder balls
Printed-circuit board
External resistance
(Note the internal versus external package resistance)
Radiation Convection
Figure 102. Package with heat sink mounted to a printed-circuit board
The heat sink removes most of the heat from the device. Heat generated on the active side
of the chip is conducted through the silicon and through the heat sink attach material (or
thermal interface material), and finally to the heat sink. The junction-to-case thermal
resistance is low enough that the heat sink attach material and heat sink thermal
resistance are the dominant terms.
5.3.2 Thermal interface materials
A thermal interface material is required at the package-to-heat sink interface to minimize
the thermal contact resistance. The performance of thermal interface materials improves
with increasing contact pressure; this performance characteristic chart is generally
provided by the thermal interface vendor. The recommended method of mounting heat
sinks on the package is by means of a spring clip attachment to the printed-circuit board
(see Figure 101).
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
251
Package information
The system board designer can choose among several types of commercially available
thermal interface materials.
6 Package information
6.1 Package parameters for the FC-PBGA
The package type is 21 mm x 21 mm, 621 flip-chip, plastic ball grid array (FC-PBGA).
• Package outline - 21 mm x 21 mm
• Interconnects - 621
• Ball Pitch - 0.8 mm
• Ball Diameter (nominal) - 0.45 mm
• Ball Height (nominal) - 0.3 mm
• Solder Balls Composition - SAC305
• Module height (typical) - 1.77 mm (minimum), 1.92 mm (typical), 2.07 mm
(maximum).
The package type is 23 mm x 23 mm, 780 flip-chip, plastic ball grid array (FC-PBGA).
• Package outline - 23 mm x 23 mm
• Interconnects - 780
• Ball Pitch - 0.8 mm
• Ball Diameter (nominal) - 0.45 mm
• Ball Height (nominal) - 0.3 mm
• Solder Balls Composition - SAC305
• Module height (typical) - 1.77 mm (minimum), 1.92 mm (typical), 2.07 mm
(maximum).
6.2 Mechanical dimensions of the FC-PBGA
This figure shows the mechanical dimensions and bottom surface nomenclature of the
chip in 21x21 mm (621 balls) pakage.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
252
NXP Semiconductors
Package information
Figure 103. Mechanical dimensions of the FC-PBGA 21x21 mm (621 balls)
Notes:
1. ALL DIMESNSIONS IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM
A.
4. DATUM A, THE SEATING PLANE, IS DETERMINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
253
Package information
5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK
ON TOP SURFACE OF PACKAGE.
This figure shows the mechanical dimensions and bottom surface nomenclature of the
chip in 23x23 mm (780 balls) package.
Figure 104. Mechanical dimensions of the FC-PBGA 23x23 mm (780 balls)
Notes:
1. ALL DIMENSIONS IN MILLIMETRES.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
254
NXP Semiconductors
Security fuse processor
2. DIMESNSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALEL TO DATUM
A
4. DATUM A, THE SEATING PLANE, IS DETERMINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK
ON TOP SURFACE OF PACKAGE.
7 Security fuse processor
This chip implements the QorIQ platform's Trust Architecture, supporting capabilities
such as secure boot. Use of the Trust Architecture features is dependent on programming
fuses in the Security Fuse Processor (SFP). The details of the Trust Architecture and SFP
can be found in the chip reference manual.
To program SFP fuses, the user is required to supply 1.8 V to the TA_PROG_SFP pin per
Power sequencing. TA_PROG_SFP should only be powered for the duration of the fuse
programming cycle, with a per device limit of six fuse programming cycles. All other
times, TA_PROG_SFP should be connected to GND. The sequencing requirements for
raising and lowering TA_PROG_SFP are shown in Power sequencing. To ensure device
reliability, fuse programming must be performed within the recommended fuse
programming temperature range per Table 5.
NOTE
Users not implementing the QorIQ platform's Trust
Architecture features should connect TA_PROG_SFP to GND.
8 Ordering information
This table provides the NXP QorIQ platform part numbering nomenclature.
8.1 Part numbering nomenclature
This table provides the NXP QorIQ platform part numbering nomenclature.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
255
Ordering information
Table 167. Part numbering nomenclature
p
ls
n
nn
n
x
t
e
n
c
d
l
r
P="Sampling" LS
Blank="Qual"
1
04 =
Four
Cores
3
A =
S =
E = SEC
7 =
LCFC
621 balls
K = 1000 N = 1300 L = Low A = Rev
ARM Standard
temp
MHz
MT/s
Power
1.0
N = SEC
not present
M = 1200 Q = 1600
B = Rev
1.1
02 =
Two
Cores
X =
Extended
temp
MHz
MT/s
8 =
LCFC
780 balls MHz
Q = 1600
MHz
P = 1400
1. For the LS1043A family of devices, parts marked with "L" (before Die-Revision) require 0.9V operating voltage. All others
require 1.0 V.
2. For supported voltage/frequency options, refer to orderable part list of QorIQ LS1043A and LS1023A Multicore
Communications Processors at www.nxp.com
8.2 Part marking
Parts are marked as in the example shown in this figure.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
256
NXP Semiconductors
Revision history
LS1043XXXXXXXXX
AWLYYWW
MMMMM CCCCC
YWWLAZ
Legend:
LS1043XXXXXXXXX is the orderable part number
AWLYYWW is the test traceability code
MMMMM is the mask number
CCCCC is the country code
YWWLAZ is the assembly traceability code
Figure 105. Part marking for FC-PBGA chip LS1043A
9 Revision history
This table summarizes revisions to this document.
Table 168. Revision history
Revision
Date
Description
2
01/2017
• Pinlist changes
• Updated Signal description for JTAG_BSR_VSEL and TBSCAN_EN_B, added notes
• Updated note 3 with minor changes for DDR
• Updated USB_VBUS voltage to 5.25 V
• Updated USB_ID voltage reference, added note in 23x23 package
• Updated voltage reference for GPIO1_31/IRQ11 in 23x23 package
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
257
Revision history
Table 168. Revision history (continued)
Revision
Date
Description
• Removed reference for Ganged sense-line implementation from note 4 in Absolute maximum
ratings
• Updated number of secure boot programming cycles to six in Power sequencing and Security
fuse processor
• Updated DDR data rate unit to MT/s in Part numbering nomenclature
• Removed SDHC_CD constraints in eSDHC AC timing specifications
• Updated table Low power mode saving estimation
• Updated Die revision in Part numbering nomenclature
1
06/2016
• Pinlist changes
• Updated TA_BB_RTC as "Reserved"
• Updated CKSTP_OUT_B as "Reserved"
• Removed reference to USB_REFCLK/USB_REFCLK_ALT
• Updated description of TA_BB_VDD as "Battery Backed Security Monitor Power"
• Removed cfg_soc_use
• Updated headings for Pinout list for more clarity
• Updated pinlist sub-section for QSPI, removed "Data Strobe"
• Updated package in number for QSPI_A_DATA1 in sub-section for QSPI
• Updated note 23 to personality selection between LS1023A/LS1043A
• Added note for SD_GND
• Added Core power dissipation @ 0.9V for 4 cores and 2 cores personalities; updated core
and platform activity factors in Power characteristics
• Updated low power mode nomenclature (PW20->PH20); deleted PH20 and LPM20 power
numbers; Added Low power saving estimate table for 0.9V in Low power mode saving
estimation. Removed PCL10. Corrected typo LMP20->LPM20
• Removed AC specification for TA_BB_RTC; updated RTC spec in Real-time clock timing
(RTC)
• Added reference to USB 3.0 clock specification in SYSCLK AC timing specifications and
Differential system clock AC timing specifications
• Updated USB 3.0 clock specification in USB 3.0 AC timing specifications
• Added note for "Trust Architecture Security Monitor battery backed features" and deleted
SYSCLK/DIFF_SYSCLK in note section of Power sequencing
• Added note 2 in Differential system clock DC timing characteristics to clarify differential swing.
• Removed note depicting restriction between PLL cluster and platform in Core complex PLL
select
• Corrected typo in Guidelines for high-speed interface termination
• Added 0.9 V support; updated note 3 in Recommended operating conditions
• Updated IFC-NVDDR specification for 0.9V in IFC-NAND NVDDR AC Timing Specification
• Added 10 MHz MDC/MDIO specification in EMI2 AC timing specifications
• Added 23x23 780 ball package details; ball layout diagrams, pinout list Pinout list and
mechanical drawing Mechanical dimensions of the FC-PBGA
• Corrected typo in PCI Express AC physical layer transmitter specifications
• Removed power supply filters to avoid duplication with Design-Checklist.
• Updated PORESET_B text in RESET initialization
• Updated IO interface power numbers in I/O power dissipation
• Corrected recommendations for Temperature diodes terminals in Connection
recommendations.
• Replaced mechanical dimension with updated format; No change in dimensions in in
Mechanical dimensions of the FC-PBGA
• Added notes in Part numbering nomenclature.
• Added foot note refering to orderable part list on NXP website in the following table
• DDR clock ranges
• Platform to SYSCLK PLL ratio
• DDR controller PLL ratios
• Core cluster to SYSCLK PLL ratio
• SYSCLK and core cluster frequency options
Table continues on the next page...
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
258
NXP Semiconductors
Revision history
Table 168. Revision history (continued)
Revision
Date
Description
• SYSCLK and platform frequency options
• DDRCLK and DDR data rate frequency options
• Clock ranges
0
02/2016
Initial release
QorIQ LS1043A, LS1023A Data Sheet, Rev. 2, 01/2017
NXP Semiconductors
259
How to Reach Us:
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
Home Page:
nxp.com
Web Support:
nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customer’s technical experts. NXP
does not convey any license under its patent rights nor the rights of others. NXP
sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/SalesTermsandConditions.
NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER
WORLD, Freescale, the Freescale logo, Layerscape, QUICC Engine, and QorIQ
are trademarks of NXP B.V. All other product or service names are the property
of their respective owners. ARM, ARM Powered, Cortex, and TrustZone are
registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or
elsewhere. NEON is a trademark of ARM Limited (or its subsidiaries) in the EU
and/or elsewhere. All rights reserved.
© 2017 NXP B.V.
Document Number LS1043A
Revision 2, 01/2017
相关型号：
©2020 ICPDF网 联系我们和版权申明