935343646531 [NXP]
RISC Microcontroller;
| 型号： | 935343646531 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 外围集成电路 |
| 文件： | 总39页 (文件大小：1139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QN9080-001-M17
Ultra Low-Power Bluetooth Smart 5.0 SIP
Rev. 1.0 — 5 December 2018
Objective data sheet
1. General description
The QN9080-001-M17 is a fully certified device supporting BLE and NFC. It has ultra-low
power consumption, highly integrated with rich feature sets, fully FCC/CE/IC/MIC certified.
The QN9080-001-M17 supports Bluetooth 5, and it is intended for ultra-small, portable
connected wireless applications.
This ultra-small device is based on QN9080 die and NT3H2211 die. QN9080 is powered
by an Arm Cortex-M4F, and has a dedicated fusion sensor co-processor (FSP) to
further reduce power consumption by off-loading complex math computations to the
hardware. 512 KB of on-board flash and 128 KB SRAM provide enough room and
flexibility for complex applications. NT3H2211 is NFC Forum Type 2 Tag compliant IC with
I2C interface, which supplies the fastest, least expensive way to add tap-and-go
connectivity to just about any electronic applications.
The QN9080-001-M17 also integrates 32 MHz and 32.768 kHz crystals, a 2.4 GHz
optimized antenna, and necessary components for QN9080 system to run. It offers a
complete solution for applications requiring BLE wireless connectivity and fast pairing with
NTAG as an option. Its low external component count reduces overall system size,
complexity and shortens development time.
2. Features and benefits
Key features:
Bluetooth 5.0 certified
Integrated antenna
Integrated 32 MHz and 32.768 kHz crystals
32-bit Arm Cortex-M4F core at 32 MHz
512 KB flash
128 KB RAM
TX power: up to +2 dBm
RX sensitivity: -92.7 dBm in 1 Mbps mode and -89 dBm in 2 Mbps mode
True single-chip Bluetooth Low Energy (v5.0) SoC solution:
Integrated Bluetooth LE radio, protocol stack and application profiles
Support central and peripherals roles
Support master/slave concurrency
Support 16 simultaneous links
Support secure connections
Support data packet length extension
48-bit unique BD address
-92.7 dBm in 1 Mbps mode and -89 dBm in 2 Mbps mode
Ultra Low-Power Bluetooth Smart
NXP Semiconductors
QN9080-001-M17
TX output power from -20 dBm to +2 dBm
Very low power consumption:
Single 1.67 V ~3.6 V power supply
1 A power-down mode, to wake up by GPIO
2 A power-down mode, to wake up by 32 kHz sleep timer, RTC and GPIO
4 mA RX current at 3 V supply in 1 Mbps
Ultra Low power Bluetooth Low Energy 5.0 module
3.5 mA TX current at 0 dBm TX power at 3 V supply in 1 Mbps mode
Interface:
32 General-Purpose Input/Output (GPIO) pins, with configurable pull-up/pull-down
resistors
8 external ADC inputs (shared with GPIO pins)
2 Analog Comparator input pins (share with GPIO pins)
Single power supply 1.67 V to 3.6 V
Operating temperature range -40 °C to +85 °C
6 x9.7x1.17 mm LFLGA package
2.1 Feature of QN9080
True single-chip Bluetooth Low Energy (v5.0) SoC solution
Integrated Bluetooth LE radio, protocol stack and application profiles
Supports central and peripherals roles
Supports master/slave concurrency
Supports 16 simultaneous links
Supports secure connections
Supports data packet length extension
Wifi/Bluetooth LE coexistence interface
48-bit unique bluetooth device address
RF
Fast and reliable RSSI in 1 dB step
TX output power from 20 dBm to 2 dBm
Single-ended RF port with integrated balun
Generic FSK modulation with programmed data rate from 250 Kbps to 2 Mbps
Compatible with worldwide radio frequency regulations
Very low power consumption
Single 1.67 V to 3.6 V power supply
Integrated DC-to-DC buck converter and LDO
1.0 A power-down 1 mode, to wake up by GPIO
2.5 A power-down 0 mode, to wake up by 32 kHz sleep timer, RTC and GPIO
3.5 mA RX current with DC-to-DC convertor enabled at 3 V supply in 1Mbps mode
4 mA TX current at 0 dBm TX power with DC-to-DC converter enabled at 3 V
supply in 1 Mbps mode
Arm Cortex-M4 core (version r0p1)
Arm Cortex-M4 processor, running at a frequency of up to 32 MHz
Floating Point Unit (FPU) and Memory Protection Unit (MPU)
QN9080-001-M17
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
Objective data sheet
Rev. 1.0 — 5 December 2018
2 of 39
Ultra Low-Power Bluetooth Smart
NXP Semiconductors
QN9080-001-M17
Arm Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC)
Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators,
and four watch points, including serial wire output for enhanced debug capabilities
System tick timer
On-chip memory
512 KB on-chip flash program memory and 2 KB page erase and write
128 KB SRAM
256 KB ROM
ROM API support
Flash In-System Programming (ISP)
Serial interfaces
Four Flexcomm serial peripherals
USART protocol supported by Flexcomm0, USART and I2C by Flexcomm1, SPI
and I2C by Flexcomm2, and SPI by Flexcomm3
Each Flexcomm includes a FIFO
I2C-bus interfaces support fast mode and with multiple address recognition and
monitor mode
USB 2.0 (full speed) device interface
Two quadrature decoders
SPI Flash Interface (SPIFI) uses a SPI bus superset with four data lines to access
off-chip quad SPI flash memory at a much higher rate than is possible using
standard SPI or SSP interfaces
Supports SPI memories with 1 or 4 data lines
Digital peripherals
DMA controller with 20 channels, able to access memories and DMA capable
peripherals
Up to 35 General Purpose Input Output (GPIO) pins, with configurable pull-up or
pull-down resistors
GPIO registers are located on the AHB for fast access
32 GPIOs can be selected as Pin INTerrupts (PINT), triggered by rising, or falling
input edges
AES-128 security coprocessor
Random Number Generator (RNG)
CRC engine
Fusion Signal Processor (FSP) for data fusion and machine learning algorithms
resulting in low power consumption compared to software processing
QN9080-001-M17
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
Objective data sheet
Rev. 1.0 — 5 December 2018
3 of 39
Ultra Low-Power Bluetooth Smart
NXP Semiconductors
QN9080-001-M17
Analog peripherals
16-bit ADC with 8 external input channels, with sample rates of up to 32k sample
per second, and with multiple internal and external trigger inputs
Integrated temperature sensor, connected to one internal dedicated ADC channel
Integrated battery monitor connected to one internal dedicated ADC channel
General-purpose 8-bit 1M sample per second DAC
Integrated capacitive sense up to 8 channels, able to wake up the MCU from low
power states.
Two ultra low-power analog comparators, able to wake up the MCU from low power
states.
Timers
Four 32-bit general-purpose timers or counters, support capture inputs and
compare outputs, PWM mode, and external count input
Sleep timer, which can work in power-down mode and wake up MCU
32-bit Real Time Clock (RTC) with 1 second resolution running in the always-on
power domain; can be used for wake-up from all low power modes including
power-down
Watchdog Timer.
SC Timer or PWM.
Clock generation
32 MHz internal RC oscillator, which can be used as a system clock
16 MHz or 32 MHz crystal oscillator, which can be used as a system and RF
reference
32 kHz on-chip RC oscillator
32.768 kHz crystal oscillator
Power control
Programmable Power Management Unit (PMU) to minimize power consumption
Reduced power modes: sleep, and power-down
Power-On Reset (POR)
Brown-Out Detection (BOD) with separate thresholds for interrupt and forced reset
Single power supply 1.67 V to 3.6 V
Operating temperature range 40 °C to +85 °C
See QN908x data sheet for more details.
2.2 Features of NTAG
Interoperability
ISO/IEC 14443 Part 2 and 3 compliant
NTAG I2C plus development board is certified as NFC Forum Type 2 Tag
(Certification ID: 58514)
Unique 7-byte UID
GET_VERSION command for easy identification of chip type and supported
features
Input capacitance of 50 pF
Host interface
I2C slave
QN9080-001-M17
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
Objective data sheet
Rev. 1.0 — 5 December 2018
4 of 39
Ultra Low-Power Bluetooth Smart
NXP Semiconductors
QN9080-001-M17
Configurable event detection pin to signal NFC or pass-through data events
Memory
1912 bytes of EEPROM-based user memory
64 bytes SRAM buffer for transfer of data between NFC and I2C interfaces with
memory mirror or pass-through mode
Clear arbitration between NFC and I2C memory access
Data transfer
Pass-through mode with 64-byte SRAM buffer
FAST_WRITE and FAST_READ NFC commands for higher data throughput
Security and memory-access management
Full, read-only, or no memory access from NFC interface, based on 32-bit
password
Full, read-only, or no memory access from I2C interface
NFC silence feature to disable the NFC interface
Originality signature based on Elliptic Curve Cryptography (ECC) for simple,
genuine authentication
Power Management
Configurable field-detection output signal for data-transfer synchronization and
device wake-up
Energy harvesting from NFC field, so as to power external devices (e.g. connected
microcontroller)
See NT3H2111_2211 Product Data Sheet for more details.
2.3 Features of integrated 2.4 GHz antenna
Monolithic SMD with small, low-profile and light-weight type.
Wide bandwidth
RoHS compliant
Note: When NFC function is required, the NFC tag antenna need to be connected
externally.
3. Applications
Health and medical devices
Sports and fitness trackers
Building and home automation
Retail and advertising beacons
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
LFLGA54
Description
Version
QN9080-001-M17
SIP module in LGA package; body 6 9.7 1.17 mm SOT1910 AA1
QN9080-001-M17
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
Objective data sheet
Rev. 1.0 — 5 December 2018
5 of 39
Ultra Low-Power Bluetooth Smart
NXP Semiconductors
QN9080-001-M17
Table 2.
Ordering options
Type number
Package
number
Flash (KB) TotalSRAM Cortex-M4 FSP
USB FS
GPIO
(KB)
with FPU
QN9080-001-M17 3322 960 18570 512
128
1
1
1
32
5. Marking
QN9080-1-M17
XXXXX
XXXXXXXXXXXX
EtDYYWWXX
Fig 1. QN9080-001-M17 package marking
Table 3.
Marking codes
Content
Line
Descriptions
number
NXP
Logo
1
2
3
4
5
QN9080-1-M17
Product identifier
XXXXX
STR number request. It will be removed on production
QN batch number
XXXXXXXXXXXX
E
TSMC
t
ASE-K
D
RoHS indicator (Dark green)
year; last two digits of year code of assembly
week code of assembly
YY
WW
X
mask version
X
for SIP before CQS; it will be removed after
QN9080-001-M17 has the following top-side marking:
Table 4.
Revision identifier (R)
001
Device revision table
Revision description
Initial SIP module revision
QN9080-001-M17 device has received FCC "Modular Approval", in compliance with CFR
47 FCC part 15 regulations and in accordance to FCC public notice DA00-1407. The
modular approvals notice and test reports are available on request.
Remark: FCC, IC & Japan ID are not mentioned on the package due to the small device
size.
QN9080-001-M17
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
Objective data sheet
Rev. 1.0 — 5 December 2018
6 of 39
Ultra Low-Power Bluetooth Smart
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QN9080-001-M17
6. Block diagram
QN9080M
Antenna
Harmonic filter
L2 3.3 nH
ANT IN
C3
C5
C4
C1
1.8 pF
C2
1.8 pF
¾
¾
¾
0.1
F
0.1
F
0.1
F
DCDC
DVDD
IDC
RVDD
AVDD
L1
10
L3
10nH
XTAL_IN
¾
H
Y1
32 MHz
XTAL_OUT
C6
¾
1
F
VCC
VCC
XTAL32_IN
Y2
32.768 kHz
RF
RF OUT
QN9080 die
XTAL32_OUT
PA31-PA00
CHIP_MODE
SCL
CHRG_SCL
CHRG_SDA
NTAG_LA
NTAG
NT3H2211
SDA
FD
NTAG_LB
RSTN
GND
NTAG_VOUT
VSS
GND
GND
DAP
NTAG_FD
NTAG_VCC
Fig 2.
QN9080-001-M17 – high level HW block diagram
QN9080-001-M17
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© NXP Semiconductors B.V. 2018. All rights reserved.
Objective data sheet
Rev. 1.0 — 5 December 2018
7 of 39
Ultra Low-Power Bluetooth Smart
NXP Semiconductors
QN9080-001-M17
QN9080M
Antenna
Harmonic filter
L2 3.3 nH
ANT IN
C3
C5
C4
C1
1.8 pF
C2
1.8 pF
¾
¾
¾
0.1
F
0.1
F
0.1
F
DCDC
DVDD
IDC
RVDD
AVDD
L3
10nH
L1
XTAL_IN
10
¾
H
Y1
32 MHz
XTAL_OUT
C6
¾
1
F
Designed and provided by customer
External
Antenna
VCC
VCC
Harmonic filter
XTAL32_IN
L2 3.3 nH
Y2
32.768 kHz
RF OUT
RF
QN9080 die
XTAL32_OUT
C2
1.8 pF
C1
1.8 pF
PA31-PA00
CHIP_MODE
SCL
CHRG_SCL
CHRG_SDA
NTAG_LA
NTAG
NT3H2211
SDA
FD
NTAG_LB
RSTN
GND
NTAG_VOUT
VSS
GND
GND
DAP
NTAG_FD
NTAG_VCC
Fig 3.
QN9080-001-M17 block diagram using external antenna
Remark: (1) QN9080-001-M17 is not certified with external antenna but only with its
internal antenna. Customer using external antenna has to do new certification. (2)
Harmonic filter is in adequacy with board.
QN9080-001-M17
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
Objective data sheet
Rev. 1.0 — 5 December 2018
8 of 39
Ultra Low-Power Bluetooth Smart
NXP Semiconductors
QN9080-001-M17
7. Pinning information
7.1 Pinning
1
35
34
33
32
31
30
29
28
27
26
25
24
23
44 43 42
41 40 39 38 37 36
2
3
4
5
51
52
54
53
6
7
8
9
10
11
12
13
22
14 15 16 17 18 19 20
21
50
45
46
47
49
48
Fig 4. QN9080-001-M17 pinout diagram
7.2 Pin description
Table 5.
Pin description
Symbol LFLGA54 Reset
state[1]
Alternate function Type Description
PA30
1
PU
GPIOA30
I/O
AI
general-purpose digital input output pin
analog comparator 1 positive input
ETM trace data output bit 3
timer 3 match output 1
ACMP1P
ETM_TRACEDAT3
CTIMER3_MAT1
FC2_SCK
O
O
I/O
I/O
I/O
flexcomm 2: SPI clock
FC3_MOSI
flexcomm 3: SPI MOSI
SPIFI_IO3
data bit 3 for the SPI flash interface
QN9080-001-M17
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© NXP Semiconductors B.V. 2018. All rights reserved.
Objective data sheet
Rev. 1.0 — 5 December 2018
9 of 39
Ultra Low-Power Bluetooth Smart
NXP Semiconductors
QN9080-001-M17
Table 5.
Pin description …continued
Symbol LFLGA54 Reset
state[1]
Alternate function Type Description
PA29
PA28
PA27
PA26
2
3
4
5
PU
PU
PU
PU
GPIOA29
I/O
AI
O
general-purpose digital input output pin
analog comparator 1 negative input
ETM trace data output bit 2
ACMP1N
ETM_TRACEDAT2
CTIMER3_MAT0
FC2_SCK
O
timer 3 match output 0
I/O
I/O
I/O
I/O
O
flexcomm 2: SPI clock
FC3_MISO
SPIFI_IO2
GPIOA28
flexcomm 3: SPI MISO
data bit 2 for the SPI flash interface
general-purpose digital input output pin
AHB clock output
CLK_AHB
ETM_TRACECLK
RTC_CAP
O
ETM trace clock output
I
RTC capture input
FC1_SCK
I/O
O
flexcomm 1: USART clock
SD_DAC
sigma-delta modulator DAC output
active low chip select output for the SPI flash interface
general-purpose digital input output pin
USB0 bidirectional D- line
SPIFI_CSN
GPIOA27
O
I/O
I/O
I
USB_DM
SCT0_IN1
CTIMER1_MAT2
FC2_SCL_MISO
QDEC0_B
BLE_IN_PROC
GPIOA26
SCTimer input 1
O
32-bit CTimer 1 match output 2
flexcomm 2: I2C SCL, SPI MISO
quadrature decoder 0 input channel B
BLE event in process indicator for coexistence
general-purpose digital input output pin
USB0 bidirectional D+ line
I/O
I
O
I/O
I/O
I
USB_DP
SCT0_IN0
CTIMER1_MAT0
FC2_SDA_MOSI
QDEC0_A
BLE_SYNC
SCTimer input 0
O
32-bit CTimer 1 match output 0
flexcomm 2: I2C SDA, SPI MOSI
quadrature decoder 0 input channel A
BLE sync pulse
I/O
I
O
LB
6
7
8
RF
RF
I/O
AI
NTAG antenna/coil terminal B
NTAG antenna/coil terminal A
general-purpose digital input output pin
LA
PA25
PU
GPIOA25
ACMP0P/CS7
analog comparator 0 positive input, or capacitive touch sense
button input 7
ETM_TRACEDAT1
CTIMER3_CAP1
RFE_TX_EN
O
ETM trace data output bit 1
timer 3 input capture 1
I
O
TX enable for external RF front-end
flexcomm 3: SPI SSEL0
FC3_SSEL0
I/O
I/O
SPIFI_IO1
data bit 1 for the SPI flash interface
QN9080-001-M17
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© NXP Semiconductors B.V. 2018. All rights reserved.
Objective data sheet
Rev. 1.0 — 5 December 2018
10 of 39
Ultra Low-Power Bluetooth Smart
NXP Semiconductors
QN9080-001-M17
Table 5.
Pin description …continued
Symbol LFLGA54 Reset
state[1]
Alternate function Type Description
PA24
9
PU
GPIOA24
I/O
AI
general-purpose digital input output pin
ACMP0N/CS6
analog comparator 0 negative input, or capacitive touch
sense button input 6
ETM_TRACEDAT0
CTIMER3_CAP0
RFE_RX_EN
FC3_SSEL1
SPIFI_IO0
O
ETM trace data output bit 0
I
timer 3 input capture 0
O
RX enable for external RF front-end
flexcomm 3: SPI SSEL1
I/O
I/O
I/O
I/O
I
data bit 0 for the SPI flash interface
serial wire debug I/O; it is the default function after booting
general-purpose digital input output pin
SCTimer input 3
SWDIO/
PA23
10
11
12
13
PU
PU
PU
PU
SWDIO
GPIOA23
SCT0_IN3
CTIMER3_MAT1
O
32-bit CTimer 3 match output 1
flexcomm 2: I2C SCL, SPI SSEL1
flexcomm 3: SPI SSEL2
FC2_SCL_SSEL1 I/O
FC3_SSEL2
QDEC1_B
SWCLK
I/O
I
quadrature decoder 1 input channel B
serial wire clock; it is the default function after reset
general-purpose digital input output pin
SCTimer input 2
SWCLK
/PA22
I/O
I/O
I
GPIOA22
SCT0_IN2
CTIMER3_MAT0
O
32-bit CTimer 3 match output 0
flexcomm 2: I2C SDA, SPI SSEL0
flexcomm 3: SPI SSEL3
FC2_SDA_SSEL0 I/O
FC3_SSEL3
QDEC1_A
I/O
I
quadrature decoder 1 input channel A
general-purpose digital input output pin
quadrature decoder 1 input channel B
SCTimer output 0, PWM output 0
32-bit CTimer 2 match output 1
flexcomm 2: SPI SSEL3
PA21
GPIOA21
I/O
I
QDEC1_B
SCT0_OUT0
CTIMER2_MAT1
FC2_SSEL3
FC1_CTS_SDA
SPIFI_CSN
GPIOA20
O
O
I/O
I/O
O
flexcomm 1: USART CTS, I2C SDA
active low chip select output for the SPI flash interface
general-purpose digital input output pin
quadrature decoder 1 input channel A
SCTimer output 1, PWM output 1
32-bit CTimer 2 match output 0
serial wire trace output
PA20
I/O
I
QDEC1_A
SCT0_OUT1
CTIMER2_MAT0
SWO
O
O
I/O
I/O
O
FC1_RTS_SCL
SPIFI_CLK
flexcomm 1: USART RTS, I2C SCL
clock output for the SPI flash interface
QN9080-001-M17
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© NXP Semiconductors B.V. 2018. All rights reserved.
Objective data sheet
Rev. 1.0 — 5 December 2018
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Ultra Low-Power Bluetooth Smart
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QN9080-001-M17
Table 5.
Pin description …continued
Symbol LFLGA54 Reset
state[1]
Alternate function Type Description
PA19
PA18
PA17
PA16
PA15
14
15
16
17
18
PU
PU
PU
PU
PU
GPIOA19
I/O
AI
O
general-purpose digital input output pin
capacitive touch sense button input 5
SCTimer output 2, PWM output 2
enable for external RF front-end
flexcomm 0: USART clock
CS5
SCT0_OUT2
RFE_EN
O
FC0_SCK
FC3_SSEL3
BLE_IN_PROC
GPIOA18
I/O
I/O
O
flexcomm 3: SPI SSEL3
BLE event in process indicator for coexistence
general-purpose digital input output pin
capacitive touch sense button input 4
SCTimer output 3, PWM output 3
32-bit CTimer 2 match output 2
flexcomm 0: USART clock
I/O
AI
O
CS4
SCT0_OUT3
CTIMER2_MAT2
FC0_SCK
FC3_SSEL2
BLE_SYNC
GPIOA17
O
I/O
I/O
O
flexcomm 3: SPI SSEL2
BLE sync pulse
I/O
AI
O
general-purpose digital input output pin
capacitive touch sense button input 3
sigma-delta modulator DAC output
32-bit CTimer 2 match output 1
flexcomm 0: USART RXD
CS3
SD_DAC
CTIMER2_MAT1
FC0_RXD
FC3_MISO
QDEC0_B
GPIOA16
O
I/O
I/O
I
flexcomm 3: SPI MISO
quadrature decoder 0 input channel B
general-purpose digital input output pin
capacitive touch sense button input 2
SCTimer output 1, PWM output 1
32-bit CTimer 2 match output 0
flexcomm 0: USART TXD
I/O
AI
O
CS2
SCT0_OUT1
CTIMER2_MAT0
FC0_TXD
FC3_MOSI
QDEC0_A
GPIOA15
O
I/O
I/O
I
flexcomm 3: SPI MOSI
quadrature decoder 0 input channel A
general-purpose digital input output pin
capacitive touch sense button input 1
SCTimer output 0, PWM output 0
timer 2 input capture 1
I/O
AI
O
CS1
SCT0_OUT0
CTIMER2_CAP1
FC0_CTS
FC3_SCK
QDEC1_B
I
I/O
I/O
I
flexcomm 0: USART CTS
flexcomm 3: SPI clock
quadrature decoder 1 input channel B
QN9080-001-M17
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© NXP Semiconductors B.V. 2018. All rights reserved.
Objective data sheet
Rev. 1.0 — 5 December 2018
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Ultra Low-Power Bluetooth Smart
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QN9080-001-M17
Table 5.
Pin description …continued
Symbol LFLGA54 Reset
state[1]
Alternate function Type Description
PA14
19
20
21
PU
PU
PU
GPIOA14
I/O
AI
O
general-purpose digital input output pin
capacitive touch sense button input 0
external antenna switch for diversity
timer 2 input capture 0
CS0
ANT_SW
CTIMER2_CAP0
FC0_RTS
FC3_SSEL0
QDEC1_A
GPIOA13
I
I/O
I/O
I
flexcomm 0: USART RTS
flexcomm 3: SPI SSEL0
quadrature decoder 1 input channel A
general-purpose digital input output pin
reserved
PA13
I/O
I/O
O
R
SCT0_OUT4
ACMP1_OUT
FC1_RXD_SDA
FC3_SSEL1
RFE_EN
SCTimer output 4
O
analog comparator 1 output
flexcomm 1: USART RXD, I2C SDA
flexcomm 3: SPI SSEL1
I/O
I/O
O
enable for external RF front-end
CHIP_M
ODE/PB
02
CHIP_MODE
I
boot selection with pull-up by default; it should be pulled low
to go through the normal ISP process for firmware
programming, otherwise the ISP process is escaped to jump
to flash
GPIOB02
I/O
O
general-purpose digital input output pin
external antenna switch for diversity
active low reset input
ANT_SW
RSTN
22
23
24
PU
I
ANT_IN
RF
RF
Internal antenna
RF_OU
T
RF input output port with Tx or Rx switch integrated on chip
GND
PA12
25
26
ground
PU
GPIOA12
R
I/O
O
general-purpose digital input output pin
reserved
SCT0_OUT5
ACMP0_OUT
FC1_TXD_SCL
SD_DAC
O
SCTimer output 5
O
analog comparator 0 output
flexcomm 1: USART TXD, I2C SCL
sigma-delta modulator DAC output
external antenna switch for diversity
general-purpose digital input output pin
ADC external input 7
I/O
O
ANT_SW
GPIOA11
ADC7
O
PA11
27
PU
I/O
AI
I
SCT0_IN3
CTIMER1_MAT2
FC2_SSEL2
ACMP1_OUT
BLE_RX
SCTimer input 3
O
32-bit CTimer 1 match output 2
flexcomm 2: SPI SSEL2
I/O
O
analog comparator 1 output
BLE reception indicator for coexistence
O
QN9080-001-M17
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Table 5.
Pin description …continued
Symbol LFLGA54 Reset
state[1]
Alternate function Type Description
PA10
PA09
PA08
PA07
PA06
28
29
30
31
32
PU
PU
PU
PU
PU
GPIOA10
I/O
AI
I
general-purpose digital input output pin
ADC external input 6
ADC6
SCT0_IN2
SCTimer input 2
CTIMER1_MAT1
FC1_SCK
O
32-bit CTimer 1 match output 1
flexcomm 1: USART clock
I/O
O
ACMP0_OUT
BLE_TX
analog comparator 0 output
O
BLE transmit indicator for coexistence
general-purpose digital input output pin
ADC external input 5
GPIOA9
I/O
AI
I
ADC5
SCT0_IN1
SCTimer input 1
CTIMER1_MAT0
FC1_RXD_SDA
BLE_PTI3
O
32-bit CTimer 1 match output 0
flexcomm 1: USART RXD, I2C SDA
BLE packet traffic information bit 3
data bit 3 for the SPI flash interface
general-purpose digital input output pin
ADC external input 4
I/O
O
SPIFI_IO3
I/O
I/O
AI
I
GPIOA8
ADC4
SCT0_IN0
SCTimer input 0
CTIMER1_CAP1
FC1_TXD_SCL
BLE_PTI2
I
timer 1 input capture 1
I/O
O
flexcomm 1: USART TXD, I2C SCL
BLE packet traffic information 2
data bit 2 for the SPI flash interface
general-purpose digital input output pin
ADC external reference voltage input
SCTimer output 2
SPIFI_IO2
I/O
I/O
AI
O
GPIOA7
ADC_VREFI
SCT0_OUT2
CTIMER1_CAP0
FC1_CTS_SDA
BLE_PTI1
I
timer 1 input capture 0
I/O
O
flexcomm 1: USART CTS, I2C SDA
BLE packet traffic information 1
active low chip select output for the SPI flash interface
general-purpose digital input output pin
connected with ADC external capacitor
SCTimer output 3
SPIFI_CSN
GPIOA6
O
I/O
A
ADC_EX_CAP
SCT0_OUT3
CTIMER0_MAT2
FC1_RTS_SCL
BLE_PTI0
O
O
32-bit CTimer 0 match output 2
flexcomm 1: USART RTS, I2C SCL
BLE packet traffic information bit 0
clock output for the SPI flash interface
I/O
O
SPIFI_CLK
O
QN9080-001-M17
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Table 5.
Pin description …continued
Symbol LFLGA54 Reset
state[1]
Alternate function Type Description
PA05
PA04
PA03
PA02
33
34
35
36
37
PU
PU
PU
PU
GPIOA5
I/O
AI
O
general-purpose digital input output pin
ADC external input 3
ADC3
SCT0_OUT5
CTIMER0_MAT1
FC0_RXD
FC2_SCL_MISO
SPIF_IO1
SCTimer output 5
O
32-bit CTimer 0 match output 1
flexcomm 0: USART RXD
flexcomm 2: SCL, SPI MISO
data bit 1 for the SPI flash interface
general-purpose digital input output pin
ADC external input 2
I/O
I/O
I/O
I/O
AI
O
GPIOA4
ADC2
SCT0_OUT4
CTIMER0_MAT0
FC0_TXD
SCTimer output 4
O
32-bit CTimer 0 match output 0
flexcomm 0: USART TXD
I/O
I/O
I/O
I/O
I
FC2_SDA_MOSI
SPIF_IO0
flexcomm 2: I2C SDA, SPI MOSI
data bit 0 for the SPI flash interface
general-purpose digital input output pin
quadrature decoder 0 input channel B
SCTimer output 3
GPIOA3
QDEC0_B
SCT0_OUT3
CTIMER0_MAT1
R
O
O
32-bit CTimer 0 match output 1
reserved
O
FC2_SDA_SSEL0 I/O
flexcomm 2: I2C SDA, SPI SSEL0
TX enable for external RF front-end
general-purpose digital input output pin
quadrature decoder 0 input channel A
SCTimer output 2
RFE_TX_EN
GPIOA2
O
I/O
I
QDEC0_A
SCT0_OUT2
CTIMER0_MAT0
R
O
O
32-bit CTimer 0 match output 0
reserved
I/O
FC2_SCL_SSEL1 I/O
flexcomm 2: I2C SCL, SPI SSEL1
RX enable for external RF front-end
field detection
RFE_RX_EN
O
O
NTAG_
FD
VCC
38
39
power supply
NTAG_
VCC
NTAG power supply
VOUT
VSS1
40
41
output supply voltage(energy harvesting)
ground
QN9080-001-M17
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Table 5.
Pin description …continued
Symbol LFLGA54 Reset
state[1]
Alternate function Type Description
PA01
PA00
PA31
42
43
44
PU
PU
PU
GPIOA1
I/O
AI
O
general-purpose digital input output pin
ADC external input 1
ADC1
SCT0_OUT1
CTIMER0_CAP1
FC0_CTS
FC2_SSEL2
WLAN_RX
GPIOA0
SCTimer output 1
I
32-bit CTimer 0 capture input 1
flexcomm 0: USART CTS
flexcomm 2: SPI SSEL2
WLAN active high RX active indicator for coexistence
general-purpose digital input output pin
ADC external input 0
I/O
I/O
I
I/O
AI
O
ADC0
SCT0_OUT0
CTIMER0_CAP0
FC0_RTS
FC2_SSEL3
WLAN_TX
GPIOA31
DAC
SCTimer output 0
I
32-bit CTimer 0 capture input 0
flexcomm 0: USART RTS
flexcomm 2: SPI SSEL3
WLAN active high TX active indicator for coexistence
general-purpose digital input output pin
DAC analog output
I/O
I/O
I
I/O
AO
I
RTC_CAP
CTIMER3_MAT2
SWO
RTC capture input
O
Timer 3 match output 2
I/O
I/O
O
serial wire trace output
FC3_SCK
SPIFI_CLK
flexcomm 3: SPI clock
clock output for the SPI flash interface
ground
GND
GND
GND
45
46
47
48
ground
ground
ANT_Pi
n3
Internal antenna ground
ANT_Pi
n2
49
50
Internal antenna ground
Internal antenna ground
ANT_Pi
n1
GND
GND
GND
GND
51
52
53
54
ground
ground
ground
ground
[1] PU = input mode, pull-up enabled (pull-up resistor pulls up pin to VCC). Z = high impedance; pull-up or pull-down disabled, AI = analog
input, AO = analog output, I = input, O = output, F = floating. Reset state reflects the pin state at reset without boot code operation.
7.2.1 Termination of unused pins
Table 6 shows how to terminate pins that are not used in the application. In many cases,
unused pins should be connected externally or configured correctly by software to
minimize the overall power consumption of the part.
QN9080-001-M17
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Unused pins with GPIO function should be configured as outputs LOW with their internal
pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the GPIO
function in the IOCON register, select output in the GPIO DIR register, and write a 0 to the
GPIO PORT register for that pin. Disable the pull-up in the pin's IOCON register.
In addition, it is recommended to configure all GPIO pins that are not bonded out on
smaller packages as outputs driven LOW with their internal pull-up disabled.
Table 6.
Termination of unused pins
Pin
Default
state[1]
Recommended termination of unused pins
RSTN
I; PU
I; PU
I; PU
the RSTN pin can be left unconnected if the application does
not use it.
all PAnm
can be left unconnected if driven LOW and configured as
GPIO output with pull-up disabled by software
CHIP_MODE
can be left unconnected if driven LOW and configured as
GPIO output with pull-up disabled by software
[1] I = Input, IA = Inactive (no pull-up/pull-down enabled), PU = Pull-Up enabled.
7.2.2 Pin states in different power modes
Table 7.
Pin
Pin states in different power modes
Active - Sleep - Power Down modes
all PAnm
RSTN
As configured in the SYSCON[1]. Default: internal pull-up enabled.
Reset function enabled. Default: input, internal pull-up enabled
[1] Default and programmed pin states are retained in sleep, and power-down mode.
8. Compliance statements and documentation
• The FCC ID number of the QN9080-001-M17 is XXMQN9080M17
• The IC ID number of the QN9080-001-M17 is 8764A-QN9080M17
207-990010
• The Japan ID number of the QN9080-001-M17 is
8.1 FCC Statements and documentation
This section contains the Federal Communication Commission (FCC) statements and
documents.
8.1.1 FCC interference Statements
• This equipment has been tested and found to comply with the limits for a Class B
digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to
provide reasonable protection against harmful interference in a residential installation.
This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instructions, may cause harmful
interference to radio communications. However, there is no guarantee that
interference will not occur in a particular installation. If this equipment does cause
harmful interference to radio or television reception, which can be determined by
turning the equipment off and on, the user is encouraged to try to correct the
interference by one of the following measures:
QN9080-001-M17
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– Reorient or relocate the receiving antenna
– Increase the separation between the equipment and receiver
– Connect the equipment into an outlet on a circuit different from that to which the
receiver is connected
– Consult the dealer or an experienced radio/TV technician for help
• OEM integrators instructions
– The OEM integrators are responsible for ensuring that the end-user has no manual
instructions to remove or install SIP
– The SIP is limited to installation in mobile or fixed applications, according to CFR
47 Part 2.1091(b)
– Separate approval is required for all other operating configurations, including
portable configurations with respect to CFR 47 Part 2.1093 and different antenna
configurations
• User guide mandatory statements
User's instructions of the host device must contain the following statements in addition
to operation instructions:
* "This device complies with part 15 of the FCC Rules. Operation is subject to the
following two conditions:
(1) This device may not cause harmful interference, and
(2) This device must accept any interference received, including interference that may
cause undesired operation"
* "Changes or modifications not expressly approved by the party responsible for
compliance could void the user's authority to operate the equipment"
• FCC RF Exposure requirements
User's instructions of the host device must contain the following instructions in
addition to operation instructions:
Avoid direct contact to the antenna, or keep it to a 20cm minimum distance while
using this equipment. This device must not be collocated or operating in conjunction
with another antenna or transmitter.
This SIP has been designed to operate etheir with internal antenna or with external
antennas having a maximum gain of 2 dBi. Antennas having a gain greater than 2 dBi are
strictly prohibited for use with this device. The required antenna impedance is 50 ohms
8.1.2 FCC end product labelling
The final 'end product' should be labelled in a visible area with the following:
"Contains TX FCC ID: XXMQN9080M17 to reflect the SIP being used inside the product.
QN9080-001-M17
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8.2 Industry Canada Statement
This device complies with Industry Canada licence-exempt Le présent appareil est conforme aux CNR d'Industrie Canada
RSS standard(s). Operation is subject to the following two applicables aux appareils radio exempts de licence.
conditions: (1) this device may not cause interference, and L'exploitation est autorisée aux deux conditions suivantes : (1)
(2) this device must accept any interference, including
interference that may cause undesired operation of the
device.
il ne doit pas produire de brouillage, et (2) l'utilisateur du
dispositif doit être prêt à accepter tout brouillage
radioélectrique re?u, même si ce brouillage est susceptible de
compromettre le fonctionnement du dispositif.
This device complies with Industry Canada RF radiation
exposure limits set forth for general population (uncontrolled Le présent appareil est conforme aux niveaux limites
exposure). This device must be installed to provide a d'exigences d'exposition RF aux personnes définies par
separation distance of at least 20 cm from all persons and Industrie Canada. Cet appareil doit être installé afin d'offrir une
must not be collocated or operating in conjunction with any distance de séparation d'au moins 20 cm avec l'utilisateur, et
other antenna or transmitter.
ne doit pas être installé à proximité ou être utilisé en
conjonction avec une autre antenne ou un autre émetteur.
To reduce potential radio interference to other users, the antenna type and its gain should
be so chosen that the equivalent isotropic radiated power (e.i.r.p.) is not more than that
permitted for successful communication.
The Gain of SIP with internal antenna is -3dBi.
If customer wants, he can also use the SIP with external antenna with maximum gain of
2dbi. This feature is not certified by NXP and need to be done by the customer. Antennas
having a gain greater than 2 dBi are strictly prohibited for use with this device. The
required antenna impedance is 50 ohms.
As long as the above condition is met, further transmitter testing will not be required.
However, the OEM integrator is still responsible for testing their end-product for any
additional compliance requirements required with this SIP installed (for example, digital
device emissions, PC peripheral requirements, etc.).
8.2.1 Industry of Canada end product labelling
For Industry Canada purposes the following should be used:
"Contains Industry Canada ID IC: 8764A-QN9080M17
8.3 Japanese Radio Certification Statement
This equipment has been tested and found to comply with the Japanese Radio
Certification Rules
8.3.1 Radio Certification end product labelling
For Japanese Radio Certification purposes, the following should be used:
207-990010
"Contains Japanese Radio certificate product: Japan ID number is
QN9080-001-M17
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9. Static characteristics
9.1 General operating conditions
Table 8.
General operating conditions
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
fclk
Parameter
Conditions
Min
Typ[1]
Max
32
Unit
MHz
V
Clock frequency
Supply voltage
VCC
1.67
3
3.6
2
VESD
Electrostatic discharge
voltage
Human body model[2]; all pins
Charged device model; all pins
kV
V
300
85
TJ(max)
Maximum junction
temperature
C
[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 °C), nominal supply voltages.
[2] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
9.2 Power consumption
Power measurements in active, sleep, power down modes were performed under the
following conditions:
• All peripherals disabled
• Analog peripherals (ADC/DAC/ACMP/Capacitive Sense) powered down
• RF off
• Internal 32 MHz HFRCO powered down
Table 9.
Static characteristics: Power consumption in active modes
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol Parameter Conditions
32 MHz HFXO; DC-DC converter enabled, VCC = 3.0 V
Min
Typ[1]
Max
Unit
ICC
Supply current
CoreMark code executed from flash
CLK_AHB = 16 MHz
[2]
920
A
[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).
[2] Characterized through bench measurements using typical samples.
Table 10. Static characteristics: Bluetooth LE power consumption in active modes
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1][2] Max[3]
Unit
32 MHz crystal oscillator, CLK_AHB = 16 MHz, transmitter mode: fc = 2440 MHz, 1 Mbps mode
ICC
supply current
DC-to-DC converter enabled, Vcc = 3 V
Tx power = 0 dBm
3.5
mA
mA
32 MHz crystal oscillator, CLK_AHB = 16 MHz, transmitter mode: fc = 2440 MHz, 1 Mbps mode
ICC
supply current
DC-to-DC converter enabled, Vcc = 3 V
-92.7 dBm RX sensitivity
4
[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).
QN9080-001-M17
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[2] Characterized through bench measurements using typical samples, with 50 loading on RF port.
[3] Guaranteed by characterization, not tested in production.
Table 11. Static characteristics: Power consumption in sleep, and power-down modes
Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1][2]
Max[3]
Unit
ICC
Supply current
Sleep mode:
all SRAM on. Flash in standby mode. DC-to-DC converter enabled, Vcc = 3 V.
32 MHz crystal oscillator
CLK_AHB = 16 MHz
470
A
A
A
Power down mode; all clocks off.
Flash is powered down. DC-DC disabled, Vcc = 3 V. Tamb = 25 C.
8 KB SRAM powered
1.0
Power down mode; 32.768 kHz LFXO on.
Flash is powered down. DC-DC disabled, Vcc = 3 V. Tamb = 25 C.
8 KB SRAM powered 2.5
[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).
[2] Characterized through bench measurements using typical samples.
[3] Guaranteed by characterization, not tested in production.
9.3 Clock source
Table 12. 32 MHz clock source characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fnom
Nominal frequency
Frequency tolerance
Load capacitance
Equivalent resistance
32
10
MHz
ppm
pF
at +25°C
-10
+10
CL
Rr
60
Table 13. 32.768 kHz clock source characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
kHz
ppm
fnom
Nominal frequency
Frequency tolerance
32.768
at +253°C, Not -20
+20
include aging
CL
Rr
Load capacitance
12.5
pF
Equivalent resistance
120
k
QN9080-001-M17
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10. RF characteristics
10.1 Receiver
Table 14. Receiver characteristics
Tamb = 25 °C; based on characterization; not tested in production. VCC = 3 V; fc = 2440 MHz; BER <
0.1 %, 1 Mbps mod
Symbol
Parameter
Conditions
Min
Typ
Max Unit
SRX
low power mode with
DC-to-DC converter
92.7
dBm
RX sensitivity
Pi(max)
C/I[1]
maximum input
power
0
dBm
co-channel
6
dB
carrier-to-interfere
nce ratio
adjacent channel at 1 MHz
alternate channel at2 MHz
4
41
41
dB
dB
[1]
image
image rejection
dB
[1]
sup(oob)
30 MHz to 2000 MHz
2003 MHz to 2399 MHz
2484 MHz to 2997 MHz
3 GHz to 12.75 GHz
1
dBm
dBm
dBm
dBm
10
10
10
out-of-band
suppression
[1] The values of these parameters are from QN9080 data sheet
10.2 Transmitter
Table 15. Transmitter characteristics
Tamb = 25 °C; based on QN9080 characterization; not tested in production.VCC = 3 V; fc = 2440 MHz
Symbol Parameter
Conditions
Min
Typ
Max
Unit
fo(RF)
CS
Po
RF output
frequency
2400
2483.5 MHz
channel
separation
2
MHz
output power
TX power
20
+2
dBm
dB
Po(RF)step RF output power
step
1
Po(acc)
TX power
accuracy
2
+2
dB
Remark: The QN9080-001-M17 is a fully certified device supporting Bluetooth 5.0. There
is a marginality (5% drift compare to the Min value of 185 kHz) on frequency deviation df2
99.9% at -40°C.
QN9080-001-M17
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11. Internal antenna characteristic
Table 16. BOD static characteristics
Tamb = 25 °C; based on characterization; not tested in production.
Parameter
Min
2400
Typ
Max
2480
Unit
MHz
Frequency range
Impedance
50
Peak gain
0.5
dBi
QN9080-001-M17
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12. Layout guideline
12.1 Footprint information for reflow soldering
Fig 5. Footprint information for reflow soldering of SIPs
QN9080-001-M17
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12.2 Layout recommendation for ground plane implementation and
clearance area for QN9080-001-M17 with integrated 2.4 GHz antenna
Antenna Clearance
On EVB(mm)
Module + Antenna
Clearance(mm)
Physical View
4.65
4
Scenario
#A
(Center
Edge)
13.7
0.55
6.55
6.55
4 x 4.65 mm
7.5
13.7x 6.55 mm
3.75
13.45
Scenario
#B
(Corner)
7.5
7.5 x 3.75 mm
13.45 x 7.5 mm
Fig 6. QN9080-001-M17 chip with integrated 2.4 GHz antenna / SIP clearance size (top view)
QN9080-001-M17
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12.2.1 Center edge PCB ground plane design
Integrated 2.4 GHz antenna function pin
9.7mm
Fig 7. QN9080-001-M17 module on 36 mm x 31 mm PCB layout guide- center edge
• Do not route signal trace across antenna clearance area
• Connect pin 49 to Upper GND, pin 50 to lower GND
QN9080-001-M17
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ʊ10.5mm
Pin49
3.5mm
Trace
route
≥ 36mm
Pin50
Trace
route
0.55mm
Trace
route
Lower GND
≥ 31mm
Fig 8. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - center edge - clearance area
G
A
B
Parameter
Units : mm
1.25
A
B
C
D
E
F
H
2.9
Antenna Clearance Area
5.5
I
Parameter Units : mm
0.5
0.5
3.5
C
0.38
G
0.55
H
0.25
D
I
E
F
Layer 1
Layer 1
Fig 9. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - center edge - clearance area layer 1
dimensions
QN9080-001-M17
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J
Antenna Clearance Area
Parameter
J
Units : mm
4.15
2
L
K
L
K
5.5
Layer 2,3,4
Fig 10. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - center edge - clearance area layers
2, 3, 4 dimensions
QN9080-001-M17
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12.2.2 Corner EVB ground plane design
Antenna Function Pin
9.7mm
6 mm
Fig 11. QN9080-001-M17 module on 36 mm x 31 mm PCB layout guide - corner
• Do not route signal trace across antenna clearance area
• Connect pin 48 to antenna trace
QN9080-001-M17
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3.5mm
Ant. Trace
Trace
route
Trace
route
Pin48
≥ 31mm
0.25mm
Trace
route
≥ 36mm
Layer 1
Fig 12. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - corner - clearance area
L
A
D
C
B
Antenna Clearance Area
Parameter Units : mm
M
E
F
Parameter Units : mm
I
A
B
C
D
E
F
G
H
I
0.5
4.34
0.5
1
O
L
6.75
3.5
2
H
M
N
O
N
G
2.9
1.5
1.5
2
2.9
3.5
0.25
0.25
J
J
K
K
Layer 1
Layer 1
Fig 13. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - corner - clearance area layer 1
dimensions
QN9080-001-M17
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P
Antenna Clearance Area
R
S
Parameter Units : mm
Q
P
Q
R
S
6.75
2
2.9
5.5
Layer 2,3,4
Fig 14. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - corner - clearance area layers 2, 3,
4 dimensions
12.3 Reflow profile
QN9080-001-M17 is an MSL3 and PSL R5G product. PSL has been defined based on the
standard J-STD-075. For reflow soldering, it is requested to follow the reflow profile and
the paste manufacturer's guidelines on peak flow temperature, soak times, time above
liquid and ramp rates.
Table 17. Recommended solder reflow profile
Temperature range
Peak temperature: 255 C
Time
10 s Max.
30 s Max.
60-120 s
Heating: 230 C or higher
Preheating: 150 C to 180 C
12.4 Soldering paste and cleaning
NXP does not recommend to use a solder paste that requires the module and PCB
assembly to be cleaned (rinsed in water) for the following reasons:
• Solder flux residues and water can be trapped by the PCB, can or components and
result in short circuits
NXP recommends to use a 'no clean' solder paste for all its module products.
QN9080-001-M17
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13. Package outline
Fig 15. Package outline LFLGA54 (SOT1910-1)
QN9080-001-M17
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14. Abbreviations
Table 18. Abbreviations
Acronym
ADC
AES
API
Description
Analog to Digital Converter
Advanced Encryption Standard
Application Program Interface
CLocK
CLK
CRC
CTS
DC
Cyclic redundancy Check
Clear-To-Send
Direct current
DIO
Digital Input Output
DMA
EEPROM
FIFO
GPIO
ID
Direct memory Access
Electrically-Erasable Programmable Read Only Memory
First In First Out
General Purpose Input Output
IDentification
IF
Intermediate frequency
Input Output
IO
MSL
NVIC
PCB
PHY
POR
PWM
RAM
RC
Moisture sensitivity level
Nested Vector Interrupt Controller
Printed-Circuit Board
PHYsical
Power-On Reset
Pulse Width Modulation
Random Access Memory
Remote Control
RF
Radio Frequency
RoHS
RSSI
RTS
RX
Restriction of Hazardous Substances
Receive Signal Strength Indication
Request-To-Send
Received
SCL
Serial CLock
SDA
SMDs
SPI-bus
SysTick
TX
Serial DatA
Surface Mount Devices
Serial Peripheral Interface -bus
System Tick timer
Transmit
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15. References
[1] IEEE Std 802.15.4-2011 IEEE Standard for Information Technology Part 15.4 —
Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications
for Low-Rate Wireless Personal Area Networks (LR-WPANs).
[2] Wireless Connectivity —
http://www.nxp.com/products/wireless-connectivity:WIRELESS-CONNECTIVITY
QN9080-001-M17
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16. Revision history
Table 19. Revision history
Document ID
Release date
20181205
Data sheet status
Change notice
Supersedes
QN9080-001-M17 v1.0
Objective data sheet
Public release
-
QN9080-001-M17
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17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
17.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
QN9080-001-M17
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
QN9080-001-M17
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19. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .5
Table 2. Ordering options . . . . . . . . . . . . . . . . . . . . . . . .6
Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 4. Device revision table. . . . . . . . . . . . . . . . . . . . . .6
Table 5. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 6. Termination of unused pins. . . . . . . . . . . . . . . .17
Table 7. Pin states in different power modes . . . . . . . . .17
Table 8. General operating conditions . . . . . . . . . . . . . .20
Table 9. Static characteristics: Power consumption in
active modes. . . . . . . . . . . . . . . . . . . . . . . . . . .20
consumption in active modes. . . . . . . . . . . . . . 20
Table 11. Static characteristics: Power consumption in
sleep, and power-down modes . . . . . . . . . . . . 21
Table 12. 32 MHz clock source characteristics . . . . . . . . 21
Table 13. 32.768 kHz clock source characteristics . . . . . 21
Table 14. Receiver characteristics. . . . . . . . . . . . . . . . . . 22
Table 15. Transmitter characteristics . . . . . . . . . . . . . . . . 22
Table 16. BOD static characteristics . . . . . . . . . . . . . . . . 23
Table 17. Recommended solder reflow profile. . . . . . . . . 31
Table 18. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 19. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 10. Static characteristics: Bluetooth LE power
20. Figures
Fig 1. QN9080-001-M17 package marking . . . . . . . . . . .6
PCB layout guide - center edge - clearance area
layers 2, 3, 4 dimensions. . . . . . . . . . . . . . . . . . . 28
Fig 11. QN9080-001-M17 module on 36 mm x 31 mm PCB
layout guide - corner . . . . . . . . . . . . . . . . . . . . . . 29
Fig 12. QN9080-001-M17 module on 36 mm x 31 mm GND
PCB layout guide - corner - clearance area . . . . 30
Fig 13. QN9080-001-M17 module on 36 mm x 31 mm GND
PCB layout guide - corner - clearance area layer 1
dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Fig 14. QN9080-001-M17 module on 36 mm x 31 mm GND
PCB layout guide - corner - clearance area layers 2,
3, 4 dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Fig 15. Package outline LFLGA54 (SOT1910-1) . . . . . . 32
Fig 2.
Fig 3.
QN9080-001-M17 – high level HW block diagram7
QN9080-001-M17 block diagram using external
antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Fig 4. QN9080-001-M17 pinout diagram . . . . . . . . . . . . .9
Fig 5. Footprint information for reflow soldering of SIPs24
Fig 6. QN9080-001-M17 chip with integrated 2.4 GHz
antenna / SIP clearance size (top view). . . . . . . .25
Fig 7. QN9080-001-M17 module on 36 mm x 31 mm PCB
layout guide- center edge . . . . . . . . . . . . . . . . . .26
Fig 8. QN9080-001-M17 module on 36 mm x 31 mm GND
PCB layout guide - center edge - clearance area27
Fig 9. QN9080-001-M17 module on 36 mm x 31 mm GND
PCB layout guide - center edge - clearance area
layer 1 dimensions . . . . . . . . . . . . . . . . . . . . . . .27
Fig 10. QN9080-001-M17 module on 36 mm x 31 mm GND
QN9080-001-M17
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21. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
10.1
10.2
Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Feature of QN9080. . . . . . . . . . . . . . . . . . . . . . 2
Features of NTAG. . . . . . . . . . . . . . . . . . . . . . . 4
Features of integrated 2.4 GHz antenna . . . . . 5
11
Internal antenna characteristic . . . . . . . . . . . 23
2.1
2.2
2.3
12
12.1
12.2
Layout guideline . . . . . . . . . . . . . . . . . . . . . . . 24
Footprint information for reflow soldering. . . . 24
Layout recommendation for ground plane
implementation and clearance area for
QN9080-001-M17 with integrated 2.4 GHz
antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Center edge PCB ground plane design . . . . . 26
Corner EVB ground plane design . . . . . . . . . 29
Reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . 31
Soldering paste and cleaning. . . . . . . . . . . . . 31
3
4
5
6
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering information. . . . . . . . . . . . . . . . . . . . . 5
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12.2.1
12.2.2
12.3
7
7.1
7.2
7.2.1
7.2.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 9
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9
Termination of unused pins. . . . . . . . . . . . . . . 16
Pin states in different power modes . . . . . . . . 17
12.4
13
14
15
16
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 32
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 33
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Revision history . . . . . . . . . . . . . . . . . . . . . . . 35
8
8.1
8.1.1
8.1.2
8.2
8.2.1
8.3
Compliance statements and documentation 17
FCC Statements and documentation . . . . . . . 17
FCC interference Statements . . . . . . . . . . . . . 17
FCC end product labelling . . . . . . . . . . . . . . . 18
Industry Canada Statement . . . . . . . . . . . . . . 19
. . . .Industry of Canada end product labelling 19
Japanese Radio Certification Statement . . . . 19
Radio Certification end product labelling . . . . 19
17
Legal information . . . . . . . . . . . . . . . . . . . . . . 36
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 36
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.1
17.2
17.3
17.4
8.3.1
18
19
20
21
Contact information . . . . . . . . . . . . . . . . . . . . 37
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9
Static characteristics. . . . . . . . . . . . . . . . . . . . 20
General operating conditions . . . . . . . . . . . . . 20
Power consumption . . . . . . . . . . . . . . . . . . . . 20
Clock source. . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.1
9.2
9.3
10
RF characteristics . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors B.V. 2018.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 December 2018
Document identifier: QN9080-001-M17
相关型号：
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