935362254557 [NXP]
RISC Microcontroller;型号: | 935362254557 |
厂家: | NXP |
描述: | RISC Microcontroller 微控制器 |
文件: | 总83页 (文件大小:1299K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number S32K1XX
Rev. 8, 06/2018
NXP Semiconductors
Data Sheet: Advance Information
S32K1XX
S32K1xx Data Sheet
Notes
• Power management
– Low-power Arm Cortex-M4F/M0+ core with
excellent energy efficiency
• Technical information for S32K118 device is
preliminary, until this device achieves qualification.
– Power Management Controller (PMC) with multiple
power modes: HSRUN, RUN, STOP, VLPR, and
VLPS. Note: CSEc (Security) or EEPROM writes/
erase will trigger error flags in HSRUN mode (112
MHz) because this use case is not allowed to
execute simultaneously. The device will need to
switch to RUN mode (80 Mhz) to execute CSEc
(Security) or EEPROM writes/erase.
• Following two are the available attachments with
Datasheet:
– S32K1xx_Orderable_Part_Number_ List.xlsx
– S32K1xx_Power_Modes_Configuration.xlsx
Key Features
• Operating characteristics
– Voltage range: 2.7 V to 5.5 V
– Ambient temperature range: -40 °C to 105 °C for
HSRUN mode, -40 °C to 125 °C for RUN mode
– Clock gating and low power operation supported on
specific peripherals.
• Memory and memory interfaces
• Arm™ Cortex-M4F/M0+ core, 32-bit CPU
– Supports up to 112 MHz frequency (HSRUN mode)
with 1.25 Dhrystone MIPS per MHz
– Arm Core based on the Armv7 Architecture and
Thumb®-2 ISA
– Up to 2 MB program flash memory with ECC
– 64 KB FlexNVM for data flash memory with ECC
and EEPROM emulation. Note: CSEc (Security) or
EEPROM writes/erase will trigger error flags in
HSRUN mode (112 MHz) because this use case is
not allowed to execute simultaneously. The device
will need to switch to RUN mode (80 MHz) to
execute CSEc (Security) or EEPROM writes/erase.
– Up to 256 KB SRAM with ECC
– Integrated Digital Signal Processor (DSP)
– Configurable Nested Vectored Interrupt Controller
(NVIC)
– Single Precision Floating Point Unit (FPU)
– Up to 4 KB of FlexRAM for use as SRAM or
EEPROM emulation
– Up to 4 KB Code cache to minimize performance
impact of memory access latencies
• Clock interfaces
– 4 - 40 MHz fast external oscillator (SOSC)
– 48 MHz Fast Internal RC oscillator (FIRC)
– 8 MHz Slow Internal RC oscillator (SIRC)
– 128 kHz Low Power Oscillator (LPO)
– Up to 112 MHz (HSRUN) System Phased Lock
Loop (SPLL)
– QuadSPI with HyperBus™ support
• Mixed-signal analog
– Up to two 12-bit Analog-to-Digital Converter
(ADC) with up to 32 channel analog inputs per
module
– Up to 50 MHz DC external square wave input clock
– Real Time Counter (RTC)
– One Analog Comparator (CMP) with internal 8-bit
Digital to Analog Converter (DAC)
• Debug functionality
– Serial Wire JTAG Debug Port (SWJ-DP) combines
– Debug Watchpoint and Trace (DWT)
– Instrumentation Trace Macrocell (ITM)
– Test Port Interface Unit (TPIU)
– Flash Patch and Breakpoint (FPB) Unit
• Human-machine interface (HMI)
– Up to 156 GPIO pins with interrupt functionality
– Non-Maskable Interrupt (NMI)
This document contains information on a pre-production product. Specifications
and pre-production information herein are subject to change without notice.
• Communications interfaces
– Up to three Low Power Universal Asynchronous Receiver/Transmitter (LPUART/LIN) modules with DMA support
and low power availability
– Up to three Low Power Serial Peripheral Interface (LPSPI) modules with DMA support and low power availability
– Up to two Low Power Inter-Integrated Circuit (LPI2C) modules with DMA support and low power availability
– Up to three FlexCAN modules (with optional CAN-FD support)
– FlexIO module for emulation of communication protocols and peripherals (UART, I2C, SPI, I2S, LIN, PWM, etc).
– Up to one 10/100Mbps Ethernet with IEEE1588 support and two Synchronous Audio Interface (SAI) modules.
• Safety and Security
– Cryptographic Services Engine (CSEc) implements a comprehensive set of cryptographic functions as described in the
SHE (Secure Hardware Extension) Functional Specification. Note: CSEc (Security) or EEPROM writes/erase will
trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The
device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase.
– 128-bit Unique Identification (ID) number
– Error-Correcting Code (ECC) on flash and SRAM memories
– System Memory Protection Unit (System MPU)
– Cyclic Redundancy Check (CRC) module
– Internal watchdog (WDOG)
– External Watchdog monitor (EWM) module
• Timing and control
– Up to eight independent 16-bit FlexTimers (FTM) modules, offering up to 64 standard channels (IC/OC/PWM)
– One 16-bit Low Power Timer (LPTMR) with flexible wake up control
– Two Programmable Delay Blocks (PDB) with flexible trigger system
– One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels
– 32-bit Real Time Counter (RTC)
• Package
– 32-pin QFN, 48-pin LQFP, 64-pin LQFP, 100-pin LQFP, 100-pin MAPBGA, 144-pin LQFP, 176-pin LQFP package
options
• 16 channel DMA with up to 63 request sources using DMAMUX
S32K1xx Data Sheet, Rev. 8, 06/2018
2
NXP Semiconductors
Table of Contents
1
2
3
Block diagram.................................................................................... 4
6.2.5 SPLL electrical specifications .....................................32
6.3 Memory and memory interfaces................................................32
6.3.1 Flash memory module (FTFC) electrical
Feature comparison............................................................................ 5
Ordering information......................................................................... 7
3.1 Selecting orderable part number ...............................................7
3.2 Ordering information ................................................................8
General............................................................................................... 9
4.1 Absolute maximum ratings........................................................9
4.2 Voltage and current operating requirements..............................10
4.3 Thermal operating characteristics..............................................11
4.4 Power and ground pins.............................................................. 12
4.5 LVR, LVD and POR operating requirements............................14
4.6 Power mode transition operating behaviors.............................. 15
4.7 Power consumption................................................................... 16
4.8 ESD handling ratings.................................................................21
4.9 EMC radiated emissions operating behaviors........................... 21
I/O parameters....................................................................................22
5.1 AC electrical characteristics...................................................... 22
5.2 General AC specifications......................................................... 22
5.3 DC electrical specifications at 3.3 V Range.............................. 23
5.4 DC electrical specifications at 5.0 V Range.............................. 24
5.5 AC electrical specifications at 3.3 V range .............................. 25
5.6 AC electrical specifications at 5 V range ................................. 25
5.7 Standard input pin capacitance.................................................. 26
5.8 Device clock specifications....................................................... 26
Peripheral operating requirements and behaviors..............................27
6.1 System modules.........................................................................27
6.2 Clock interface modules............................................................ 27
6.2.1 External System Oscillator electrical specifications....27
6.2.2 External System Oscillator frequency specifications . 29
6.2.3 System Clock Generation (SCG) specifications..........31
specifications................................................................32
6.3.1.1
Flash timing specifications —
4
commands................................................ 32
Reliability specifications..........................37
6.3.1.2
6.3.2 QuadSPI AC specifications..........................................38
6.4 Analog modules.........................................................................42
6.4.1 ADC electrical specifications...................................... 42
6.4.1.1
6.4.1.2
12-bit ADC operating conditions.............42
12-bit ADC electrical characteristics....... 44
6.4.2 CMP with 8-bit DAC electrical specifications............ 46
6.5 Communication modules...........................................................50
6.5.1 LPUART electrical specifications............................... 50
6.5.2 LPSPI electrical specifications.................................... 50
6.5.3 LPI2C electrical specifications.................................... 56
6.5.4 FlexCAN electical specifications.................................57
6.5.5 SAI electrical specifications........................................ 57
6.5.6 Ethernet AC specifications.......................................... 59
6.5.7 Clockout frequency......................................................62
6.6 Debug modules.......................................................................... 62
6.6.1 SWD electrical specofications .................................... 62
6.6.2 Trace electrical specifications......................................64
6.6.3 JTAG electrical specifications..................................... 65
Thermal attributes.............................................................................. 68
7.1 Description.................................................................................68
7.2 Thermal characteristics..............................................................68
7.3 General notes for specifications at maximum junction
5
6
7
temperature................................................................................ 73
Dimensions.........................................................................................74
8.1 Obtaining package dimensions .................................................74
Pinouts................................................................................................75
9.1 Package pinouts and signal descriptions....................................75
6.2.3.1
Fast internal RC Oscillator (FIRC)
8
9
electrical specifications............................ 31
Slow internal RC oscillator (SIRC)
6.2.3.2
electrical specifications ........................... 31
6.2.4 Low Power Oscillator (LPO) electrical specifications
......................................................................................32
10 Revision History.................................................................................75
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
3
Block diagram
1 Block diagram
Following figures show superset high level architecture block diagrams of S32K14x
series and S32K11x series respectively. Other devices within the family have a subset of
the features. See Feature comparison for chip specific values.
Arm Cortex M4F
MCM
Core
Async
Trace
port
TPIU
PPB
NVIC
ITM
AWIC
JTAG &
SWJ-DP
AHB-AP
Serial Wire
FPU
FPB
Clock generation
DSP DWT
DMA
MUX
SOSC
4-40 MHz
FIRC
48 MHz
SIRC
8 MHz
LPO
128 kHz
8-40 MHz
Mux
SPLL
eDMA
TCD
512B
LMEM
2
Main SRAM
LMEM
controller
Upper region
Lower region
EIM
Code Cache
ENET
M3
M2
M1
M0
S2
S3
S1
Crossbar switch (AXBS-Lite)
S0
1
1
1
System MPU
System MPU
System MPU
Mux
QuadSPI
GPIO
Flash memory
controller
Peripheral bus controller
FlexRAM/
SRAM
Low Power
Timer
LPIT
ERM
WDOG
12-bit ADC
LPI2C
FlexIO
Code flash
memory
Data flash
memory
CMP
8-bit DAC
EWM
CRC
LPUART
LPSPI
FlexCAN
FlexTimer
QSPI
3
CSEc
TRGMUX
PDB
RTC
SAI
1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from
accessing restricted memory regions. This system MPU provides memory protection at the
level of the Crossbar Switch. Each Crossbar master (Core, DMA, Ethernet) can be assigned
different access rights to each protected memory region. The Arm M4 core version in this family
does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU.
Device architectural IP
on all S32K devices
Key:
Peripherals present
on all S32K devices
2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"
chapter of the S32K1xx Series Reference Manual.
Peripherals present
on selected S32K devices
(see the "Feature Comparison"
section)
3: CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this
use case is not allowed to execute simultaneously. The device need to switch to RUN mode (80 MHz) to
execute CSEc (Security) or EEPROM writes/erase.
Figure 1. High-level architecture diagram for the S32K14x family
S32K1xx Data Sheet, Rev. 8, 06/2018
4
NXP Semiconductors
Feature comparison
IO PORT
Arm Cortex M0+
IO PORT
Clock generation
FIRC
SOSC
4-40 MHz
SIRC
8 MHz
LPO
128 kHz
SW-DP
Serial Wire
NVIC
48 MHz
AHB-AP
AWIC
DMA
MUX
PPB
BPU
MTB+DWT
eDMA
M2
M0
S0
Crossbar switch (AXBS-Lite)
S1
S2
1
1
System MPU
System MPU
EIM
Flash memory
controller
2
SRAM
FlexRAM/
2
SRAM
Peripheral bus controller
Code flash
memory
Data flash
memory
Low Power
Timer
ERM
WDOG
12-bit ADC
LPI2C
FlexIO
LPIT
CSEc
CMP
8-bit DAC
CMU
LPUART
FlexCAN
FlexTimer
GPIO
CRC
TRGMUX
LPSPI
PDB
RTC
1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from
accessing restricted memory regions. This system MPU provides memory protection at the
level of the Crossbar Switch. Crossbar master (Core, DMA) can be assigned
different access rights to each protected memory region. The Arm M0+ core version in this family
does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU.
Device architectural IP
on all S32K devices
Peripherals present
on all S32K devices
Key:
Peripherals present
on selected S32K devices
(see the "Feature Comparison"
section)
2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"
chapter of the S32K1xx Series Reference Manual.
Figure 2. High-level architecture diagram for the S32K11x family
2 Feature comparison
The following figure summarizes the memory, peripherals and packaging options for the
S32K1xx devices. All devices which share a common package are pin-to-pin compatible.
NOTE
Availability of peripherals depends on the pin availability in a
particular package. For more information see IO Signal
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
5
Feature comparison
Description Input Multiplexing sheet(s) attached with
Reference Manual.
S32K11x
S32K14x
Parameter
K116
K118
K142
K144
K146
K148
®
®
Core
Arm Cortex™-M0+
48 MHz
Arm Cortex™-M4F
Frequency
IEEE-754 FPU
80 MHz (RUN mode) or 112 MHz (HSRUN mode)1
1
Cryptographic Services Engine (CSEc)
CRC module
1x
1x
capable up to ASIL-B
capable up to ASIL-B
ISO 26262
Peripheral speed
Crossbar
up to 48 MHz
up to 112 MHz (HSRUN)
DMA
External Watchdog Monitor (EWM)
Memory Protection Unit (MPU)
FIRC CMU
Watchdog
1x
1x
Low power modes
HSRUN mode1
Number of I/Os
Single supply voltage
up to 43
up to 58
up to 89
up to 128
2.7 - 5.5 V
-40oC to +105oC / +125oC
up to 156
2.7 - 5.5 V
-40oC to +105oC / +125oC
Ambient Operation Temperature (T
Flash
)
a
2
128 KB
256 KB
256 KB
32 KB
512 KB
1 MB
2 MB
Error Correcting Code (ECC)
System RAM (including FlexRAM and MTB)
FlexRAM (also available as system RAM)
Cache
17 KB
25 KB
64 KB
128 KB
256 KB
2 KB
4 KB
4 KB
1
EEPROM emulated by FlexRAM
2 KB (up to 32 KB D-Flash)
4 KB (up to 64 KB D-Flash)
See footnote 3
QuadSPI incl.
HyperBus™
External memory interface
Low Power Interrupt Timer (LPIT)
1x
2x (16)
1x
1x
FlexTimer (16-bit counter) 8 channels
Low Power Timer (LPTMR)
Real Time Counter (RTC)
4x (32)
6x (48)
8x (64)
1x
1x
1x
Programmable Delay Block (PDB)
Trigger mux (TRGMUX)
1x
2x
1x (43)
1x (13)
1x (45)
1x (16)
1x (64)
1x (73)
2x (24)
1x (81)
2x (32)
12-bit SAR ADC (1 Msps each)
Comparator with 8-bit DAC
2x (16)
1x
1x
10/100 Mbps IEEE-1588 Ethernet MAC
Serial Audio Interface (AC97, TDM, I2S)
1x
2x
Low Power UART/LIN (LPUART)
2x
1x
2x
2x
3x
3x
(Supports LIN protocol versions 1.3, 2.0, 2.1, 2.2A, and SAE J2602)
Low Power SPI (LPSPI)
Low Power I2C (LPI2C)
1x
2x
1x
3x
2x
FlexCAN
(CAN-FD ISO/CD 11898-1)
1x
2x
3x
3x
(1x with FD)
(1x with FD)
(1x with FD)
(2x with FD)
(3x with FD)
FlexIO (8 pins configurable as UART, SPI, I2C, I2S)
Debug & trace
1x
1x
SWD, JTAG
(ITM, SWV,
SWO), ETM
4
SWD, JTAG (ITM, SWV, SWO)
SWD, MTB (1 KB), JTAG
Ecosystem
(IDE, compiler, debugger)
NXP S32 Design Studio (GCC) + SDK,
IAR, GHS, Arm®, Lauterbach, iSystems
NXP S32 Design Studio (GCC) + SDK,
IAR, GHS, Arm®, Lauterbach, iSystems
64-pin LQFP
64-pin LQFP
100-pin LQFP
100-pin MAPBGA
100-pin MAPBGA
144-pin LQFP
176-pin LQFP
32-pin QFN
48-pin LQFP
48-pin LQFP
64-pin LQFP
64-pin LQFP
100-pin LQFP
100-pin MAPBGA
100-pin LQFP
144-pin LQFP
Packages5
LEGEND:
Not implemented
Available on the device
1 No write or erase access to Flash module, including Security (CSEc) and EEPROM commands, are allowed when
device is running at HSRUN mode (112MHz) or VLPR mode.
2 Available when EEEPROM, CSEc and Data Flash are not used. Else only up to 1,984 KB is available for Program Flash.
3 4 KB (up to 512 KB D-Flash as a part of 2 MB Flash). Up to 64 KB of flash is used as EEPROM backup and the remaining 448 KB
of the last 512 KB block can be used as Data flash or Program flash. See chapter FTFC for details.
4 Only for Boundary Scan Register
5 See Dimensions section for package drawings
Figure 3. S32K1xx product series comparison
S32K1xx Data Sheet, Rev. 8, 06/2018
6
NXP Semiconductors
Ordering information
3 Ordering information
3.1 Selecting orderable part number
Not all part number combinations are available. See the attachment
S32K1xx_Orderable_Part_Number_ List.xlsx attached with the Datasheet for a list of
standard orderable part numbers.
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
7
Ordering information
3.2 Ordering information
F/P S32 K 1 0 0 X Y T0 M LH R
Product status
Product type/brand
Product line
Series/Family
(including generation)
Core platform/
Performance
Memory size
Ordering option 1: Letter
Ordering option 2: Letter
Wafer Fab and
revision
Temperature
Package
Tape and Reel
Temperature
Ordering option
X: Speed
Product status
P: Prototype
F: Qualified
V: -40C to 105C
M: -40C to 125C
W: -40C to 150C2
B: 48 MHz without DMA (S32K11x only)
L: 48 MHz with DMA (S32K11x only)
H: 80 MHz
Product type/brand
S32: Automotive 32-bit MCU
U1: 112 MHz (Not valid with M temperature/125C)
Package
Y: Optional feature
Product line
K: Arm Cortex MCUs
R: Base feature set
F: CAN FD, FlexIO
A1: CAN FD, FlexIO, Security
E: Ethernet, Serial Audio Interface (S32K148 only)
J1: Ethernet, Serial Audio Interface, CAN FD,
FlexIO, Security (S32K148 only)
LQFP
Pins
32
QFN
BGA
-
-
FM
-
LF
Series/Family
1: 1st product series
2: 2nd product series
-
-
48
64
-
LH
LL
MH
100
144
-
-
-
-
-
LQ
LU
Core platform/Performance
1: Arm Cortex M0+
Wafer, Fab and revision
Fx: ATMC2
176
4: Arm Cortex M4F
Tx: GF
XX: Flex #2
Tape and Reel
T: Trays/Tubes
R: Tape and Reel
Memory size
x0: 1st revision
2
4
8
6
S32K11x
S32K14x
128K 256K
1M
256K 512K
2M
1. CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to
execute simultaneously. The device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase.
2. Not supported yet
3. Part numbers no longer offered as standard include:
Ordering Option X (M:64MHz); Ordering Option Y (N: limited RAM. 16KB for K142, 48KB for K144, 96KB for K146, 192KB for K148
S: Security); Temperature (C: -40C to 85C)
NOTE
Not all part number combinations are available. See S32K1xx_Orderable_Part_Number_List.xlsx
attached with the Datasheet for list of standard orderable parts.
Figure 4. Ordering information
S32K1xx Data Sheet, Rev. 8, 06/2018
8
NXP Semiconductors
General
4 General
4.1 Absolute maximum ratings
NOTE
• Functional operating conditions appear in the DC electrical
characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maximum
values is not guaranteed. See footnotes in the following
table for specific conditions.
• Stress beyond the listed maximum values may affect device
reliability or cause permanent damage to the device.
• All the limits defined in the datasheet specification must be
honored together and any violation to any one or more will
not guarantee desired operation.
• Unless otherwise specified, all maximum and minimum
values in the datasheet are across process, voltage, and
temperature.
Table 1. Absolute maximum ratings
Symbol
Parameter
Conditions1
Min
-0.3
-0.3
-3
Max
5.8 3
5.8 3
+3
Unit
V
2
VDD
2.7 V - 5. 5V input supply voltage
3.3 V / 5.0 V ADC high reference voltage
—
—
—
VREFH
V
4
IINJPAD_DC_ABS
Continuous DC input current (positive /
negative) that can be injected into an I/O
pin
mA
VIN_DC
Continuous DC Voltage on any I/O pin
with respect to VSS
—
—
-0.8
—
5.85
30
V
IINJSUM_DC_ABS
Sum of absolute value of injected currents
on all the pins (Continuous DC limit)
mA
6
Tramp
ECU supply ramp rate
MCU supply ramp rate
Ambient temperature
Storage temperature
—
—
—
—
—
0.5 V/min
0.5 V/min
-40
500 V/ms
100 V/ms
125
—
—
°C
°C
V
7
Tramp_MCU
8
TA
TSTG
-55
165
6.8 9
VIN_TRANSIENT
Transient overshoot voltage allowed on
I/O pin beyond VIN_DC limit
—
1. All voltages are referred to VSS unless otherwise specified.
2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the
ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.
3. 60 s lifetime – No restrictions i.e. The part can switch.
10 hours lifetime – Device in reset i.e. The part cannot switch.
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
9
General
4. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.
5. While respecting the maximum current injection limit
6. This is the Electronic Control Unit (ECU) supply ramp rate and not directly the MCU ramp rate. Limit applies to both
maximum absolute maximum ramp rate and typical operating conditions.
7. This is the MCU supply ramp rate and the ramp rate assumes that the S32K1xx HW design guidelines in AN5426 are
followed. Limit applies to both maximum absolute maximum ramp rate and typical operating conditions.
8. TJ (Junction temperature)=135 °C. Assumes TA=125 °C for RUN mode
TJ (Junction temperature)=125 °C. Assumes TA=105 °C for HSRUN mode
• Assumes maximum θJA for 2s2p board. See Thermal characteristics
9. 60 seconds lifetime; device in reset (no outputs enabled/toggling)
4.2 Voltage and current operating requirements
NOTE
Device functionality is guaranteed up to the LVR assert level,
however electrical performance of 12-bit ADC, CMP with 8-bit
DAC, IO electrical characteristics, and communication modules
electrical characteristics would be degraded when voltage drops
below 2.7 V
Table 2. Voltage and current operating requirements 1
Symbol
Description
Min.
2.73
0
Max.
5.5
Unit
V
Notes
2
VDD
Supply voltage
4
VDD_OFF
Voltage allowed to be developed on VDD
pin when it is not powered from any
external power supply source.
0.1
V
VDDA
VDD – VDDA
VREFH
Analog supply voltage
2.7
– 0.1
2.7
5.5
0.1
V
V
4
4
5
VDD-to-VDDA differential voltage
ADC reference voltage high
ADC reference voltage low
Open drain pullup voltage level
VDDA + 0.1
0.1
V
VREFL
-0.1
VDD
-3
V
VODPU
VDD
V
6
7
IINJPAD_DC_OP
Continuous DC input current (positive /
negative) that can be injected into an I/O
pin
+3
mA
IINJSUM_DC_OP
Continuous total DC input current that can
be injected across all I/O pins such that
there's no degradation in accuracy of
analog modules: ADC and ACMP (See
section Analog Modules)
—
30
mA
1. Typical conditions assumes VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise
stated.
2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the
ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.
3. S32K148 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged S32K148 is guaranteed to
operate from 2.97 V. All other S32K family devices operate from 2.7 V in all modes.
4. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC
only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for
reference supply design for SAR ADC.
S32K1xx Data Sheet, Rev. 8, 06/2018
10
NXP Semiconductors
General
5. VREFH should always be equal to or less than VDDA + 0.1 V and VDD + 0.1 V
6. Open drain outputs must be pulled to VDD
.
7. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.
4.3 Thermal operating characteristics
Table 3. Thermal operating characteristics for 64 LQFP, 100 LQFP, and 100 MAP-BGA
packages.
Symbol
Parameter
Value
Typ.
—
Unit
Min.
−40
−40
−40
−40
−40
−40
Max.
851
TA C-Grade Part
TJ C-Grade Part
TA V-Grade Part
TJ V-Grade Part
TA M-Grade Part
TJ M-Grade Part
Ambient temperature under bias
Junction temperature under bias
Ambient temperature under bias
Junction temperature under bias
Ambient temperature under bias
Junction temperature under bias
℃
℃
℃
℃
℃
℃
—
1051
1051
1251
1252
1352
—
—
—
—
1. Values mentioned are measured at ≤ 112 MHz in HSRUN mode.
2. Values mentioned are measured at ≤ 80 MHz in RUN mode.
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
11
General
4.4 Power and ground pins
VDD
VDD
VSS
32 QFN
Package
VDD
VSS
VREFH/VDDA
/
VDD
48 LQFP
Package
V
/V
REFH DDA
VREFL/VSSA/VSS
VREFL/VSSA/VSS
C
DEC
VDD
VDD
VDDA
VDD
VSS
VDD
VSS
VDDA
64 LQFP
Package
100 LQFP
Package
VREFH
VREFL
VREFH
VREFL/VSSA/VSS
VSSA/VSS
C
DEC
C
C
C
DEC
DEC
DEC
VDD
VSS
VDD
VSS
VDD
VDDA
VREFH
VDDA
VREFH
VSS
VDD
VSS
VDD
VSS
144 LQFP
Package
176 LQFP
Package
VREFL
VSSA/VSS
VREFL
VSSA/VSS
VDD
VDD
VSS
VSS
C
C
C
C
DEC
DEC
DEC
DEC
NOTE: VDD and VDDA must be shorted to a common source on PCB
Figure 5. Pinout decoupling
S32K1xx Data Sheet, Rev. 8, 06/2018
12
NXP Semiconductors
General
Table 4. Supplies decoupling capacitors 1, 2
Symbol
Description
Min. 3
70
Typ.
100
100
Max.
—
Unit
nF
, 4
5
CREF
,
ADC reference high decoupling capacitance
Recommended decoupling capacitance
CDEC5, 6, 7
70
—
nF
1. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC
only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for
reference supply design for SAR ADC. All VSS pins should be connected to common ground at the PCB level.
2. All decoupling capacitors must be low ESR ceramic capacitors (for example X7R type).
3. Minimum recommendation is after considering component aging and tolerance.
4. For improved performance, it is recommended to use 10 μF, 0.1 μF and 1 nF capacitors in parallel.
5. All decoupling capacitors should be placed as close as possible to the corresponding supply and ground pins.
6. Contact your local Field Applications Engineer for details on best analog routing practices.
7. The filtering used for decoupling the device supplies must comply with the following best practices rules:
• The protection/decoupling capacitors must be on the path of the trace connected to that component.
• No trace exceeding 1 mm from the protection to the trace or to the ground.
• The protection/decoupling capacitors must be as close as possible to the input pin of the device (maximum 2 mm).
• The ground of the protection is connected as short as possible to the ground plane under the integrated circuit.
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
13
General
V
OSC
= 3.3 V nominal
FIRC
SIRC
SPLL
SOSC
ADC
CMP
V
= 1.2 V/1.4 V nominal
CORE
V
Flash
= 3.3 V nominal
PMC
Pads
System RAM
TCD RAM
I/D Cache
EEE RAM
Flash
LV SOG
GPIO
*Note: VSSA and VSS are shorted at package level
Figure 6. Power diagram
4.5 LVR, LVD and POR operating requirements
Table 5. VDD supply LVR, LVD and POR operating requirements
Symbol
VPOR
Description
Min.
1.1
Typ.
1.6
Max.
2.0
Unit
V
Notes
Rising and falling VDD POR detect voltage
VLVR
LVR falling threshold (RUN, HSRUN, and
STOP modes)
2.50
2.58
2.7
V
LVR hysteresis
—
45
—
mV
1
1
VLVR_HYST
VLVR_LP
VLVD
LVR falling threshold (VLPS/VLPR modes)
Falling low-voltage detect threshold
LVD hysteresis
1.97
2.8
—
2.22
2.875
50
2.44
3
V
V
—
mV
VLVD_HYST
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
14
NXP Semiconductors
General
Table 5. VDD supply LVR, LVD and POR operating requirements (continued)
Symbol
VLVW
Description
Min.
4.19
—
Typ.
4.305
75
Max.
4.5
Unit
V
Notes
Falling low-voltage warning threshold
LVW hysteresis
VLVW_HYST
VBG
—
mV
V
1
Bandgap voltage reference
0.97
1.00
1.03
1. Rising threshold is the sum of falling threshold and hysteresis voltage.
4.6 Power mode transition operating behaviors
All specifications in the following table assume this clock configuration:
• RUN Mode:
• Clock source: FIRC
• SYS_CLK/CORE_CLK = 48 MHz
• BUS_CLK = 48 MHz
• FLASH_CLK = 24 MHz
• HSRUN Mode:
• Clock source: SPLL
• SYS_CLK/CORE_CLK = 112 MHz
• BUS_CLK = 56 MHz
• FLASH_CLK = 28 MHz
• VLPR Mode:
• Clock source: SIRC
• SYS_CLK/CORE_CLK = 4 MHz
• BUS_CLK = 4 MHz
• FLASH_CLK = 1 MHz
• STOP1/STOP2 Mode:
• Clock source: FIRC
• SYS_CLK/CORE_CLK = 48 MHz
• BUS_CLK = 48 MHz
• FLASH_CLK = 24 MHz
• VLPS Mode: All clock sources disabled 1
Table 6. Power mode transition operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
tPOR
After a POR event, amount of time from the point VDD
reaches 2.7 V to execution of the first instruction
across the operating temperature range of the chip.
—
325
—
μs
Table continues on the next page...
1.
•
•
For S32K11x – FIRC/SOSC
For S32K14x – FIRC/SOSC/SPLL
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
15
General
Table 6. Power mode transition operating behaviors (continued)
Symbol
Description
Min.
8
Typ.
—
Max.
17
Unit
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
VLPS → RUN
STOP1 → RUN
0.07
0.07
19
0.075
0.075
—
0.08
0.08
26
STOP2 → RUN
VLPR → RUN
VLPR → VLPS
5.1
18.8
0.72
0.3
0.35
0.2
0.3
3.5
105
1
5.7
6.5
VLPS → VLPR
23
27.75
0.77
0.35
0.4
RUN → Compute operation
HSRUN → Compute operation
RUN → STOP1
0.75
0.31
0.38
0.23
0.35
3.8
RUN → STOP2
0.25
0.4
RUN → VLPS
RUN → VLPR
5
VLPS → Asynchronous DMA Wakeup
STOP1 → Asynchronous DMA Wakeup
STOP2 → Asynchronous DMA Wakeup
Pin reset → Code execution
110
1.1
125
1.3
1
1.1
1.3
—
214
—
NOTE
HSRUN should only be used when frequencies in excess of 80
MHz are required. When using 80 MHz and below, RUN mode
is the recommended operating mode.
4.7 Power consumption
The following table shows the power consumption targets for the device in various mode
of operations. Attached S32K1xx_Power_Modes _Configuration.xlsx details the modes
used in gathering the power consumption data stated in the following table Table 7. For
full functionality refer to table: Module operation in available power modes of the
Reference Manual.
S32K1xx Data Sheet, Rev. 8, 06/2018
16
NXP Semiconductors
Table 7. Power consumption (Typicals unless stated otherwise) 1
STOP1 STOP2
RUN@48
MHz (mA)
RUN@64 MHz RUN@80 MHz HSRUN@112
VLPS (μA) 2
VLPR (mA)
(mA)
(mA)
(mA)
(mA)
MHz (mA) 3
S32K116
25
85
Typ
Typ
Max
Typ
Max
Typ
Max
26
76
40
93
1.05 1.07 TBD
6.3
6.6
8
7.2
7.5
11.8 20.3
NA
245
251
279
255
302
NA
1.1
1.11 TBD
1.4 NA
12
20.6
287
139
590
NA
891
300
164
603
NA
904
1.39
8.9
13.4 22.1
12.3 20.8
14.5 23.1
105
125
1.15 1.16 TBD
6.8
9.2
NA
10.4
7.7
1.68 1.69
NA NA
2.02 2.04
NA
TBD
NA
10.1
NA
NA
NA
11.3
15.6 24.1
325
S32K118
S32K142
25
Typ
Typ
Max
Max
26
38
1.9
2.5
TBD
7
12
TBD TBD
TBD TBD
TBD TBD
NA
TBD
TBD
TBD
TBD
105
TBD
TBD
TBD
TBD TBD TBD TBD
TBD TBD TBD TBD
TBD TBD TBD TBD
TBD
TBD
TBD
TBD
TBD
TBD
125
TBD
42
25
85
Typ
Typ
Max
Typ
Max
Typ
29
40
1.17 1.21 2.19
1.48 1.51 2.31
6.4
7
7.4
8
17.3 24.6
17.6 24.9
24.5
25
31.3
28.8
29.1
32
37.5
40.5
41.1
44
52.2
52.5
55.6
53.1
57.4
360
364
400
373
423
NA
128
335
240
740
NA
137
360
257
791
NA
31.6
33.5
31.9
35.3
NA
37.7
40
1.87 1.89
NA
8.6
7.6
9.9
NA
9.4
8.3
10.9
NA
22
28.2
26.9
25.5
27.8
NA
105
125
1.58 1.61 2.44
18.3 25.7
23.1 30.2
29.8
33.8
NA
38
41.5
44.9
2.32 2.34
NA NA
NA
40.7
NA
2.84
NA
NA
NA
Table continues on the next page...
Table 7. Power consumption (Typicals unless stated otherwise) 1 (continued)
STOP1 STOP2
RUN@48
MHz (mA)
RUN@64 MHz RUN@80 MHz HSRUN@112
VLPS (μA) 2
VLPR (mA)
(mA)
(mA)
(mA)
(mA)
MHz (mA) 3
Max
1637
1694
3.1
3.21
NA
12.7
13.7
25
32.9
30.7
38.8
36
43.8
NA
450
S32K144
S32K146
S32K1488
25
85
Typ
Typ
Max
Typ
Max
Typ
Max
29.8
150
359
256
850
NA
42
1.48 1.50 2.91
1.72 1.85 3.08
7
7.7
8.1
19.7 26.9
20.4 27.1
23.2 29.6
20.6 27.4
23.9 30.6
25.1
26.1
29.3
26.6
30.3
NA
33.3
33.5
36.2
33.8
37.3
NA
30.2
30.5
34.8
31.2
35.6
NA
39.6
40
43.3
43.9
46.3
44.8
47.9
55.6
56.1
59.7
57.1
61.3
378
381
435
390
445
NA
159
384
273
900
NA
7.2
9.2
7.8
10.3
NA
2.60 2.65
NA
9.9
42.1
40.5
43.5
NA
105
125
1.80 2.10 3.23
8.5
2.65 2.70
NA NA
NA
3.65
NA
11.1
NA
NA
NA
NA
NA
1960
1998 3.18 3.25
12.9
13.8
26.9 33.6
35
40.3
38.7
46.8
484
25
85
Typ
Typ
Max
Typ
Max
Typ
Max
37
207
974
419
2004
NA
47
1.57 1.61
3.3
8
9.2
10.1
13.9
11
23.4 31.4
24.4 32.4
29.3 37.9
25.3 33.4
34.1 42.6
30.5
31.5
36.7
32.5
41.3
NA
40.2
41.3
47
36.2
37.2
42.4
38.1
46.9
NA
47.6
48.7
54.4
49.6
58.8
NA
52
68.3
69.8
78
452
465
530
477
587
NA
209
981
422
1.79 1.83 3.54
3.32 3.38 NA
1.99 2.04 3.78
8.9
53.3
60.3
54.4
65.7
12.7
9.8
105
125
42.2
51.4
NA
70.8
82.8
2017 4.06 4.13
NA NA NA
3380 5.28 5.38
NA
4.44
NA
17.1
NA
18.3
NA
NA
NA
NA
NA
3358
22.6
23.7
40.2 48.8
47.3
57.4
52.8
64.8
660
25
85
Typ
Typ
38
54
2.17 2.20 3.45
2.30 2.35 3.74
8.5
9.6
27.6 34.9
29.1 37.0
35.5
36.8
45.3
46.6
42.1
43.4
57.7
59.9
60.3
62.9
83.3
88.7
526
543
336
357
10.1
11.1
Table continues on the next page...
Table 7. Power consumption (Typicals unless stated otherwise) 1 (continued)
STOP1 STOP2
RUN@48
MHz (mA)
RUN@64 MHz RUN@80 MHz HSRUN@112
(mA) (mA)
MHz (mA) 3
VLPS (μA) 2
VLPR (mA)
(mA)
(mA)
Max
Typ
Max
Typ
Max
1660
560
1736 3.48 3.55
577 2.49 2.54 4.03
2970 4.40 4.47
NA NA NA
4166 6.00 6.08
NA
14.5
10.9
18.0
NA
15.6
11.9
19.0
NA
34.8 43.6
29.8 37.8
38.4 46.8
41.9
37.6
44.9
NA
53.9
48.7
45.2
51.6
NA
65.1
70.4
63.8
73.6
96.1
89.1
97.4
609
565
645
NA
105
125
47.5
55.3
NA
61.5
66.8
NA
2945
NA
NA
4.85
NA
NA
NA
NA
NA
3990
23.4
24.5
44.3 52.5
50.9
61.3
57.5
71.6
719
1. Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user configuration. Typical conditions assumes
VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise stated. All output pins are floating and On-chip pulldown is enabled for
all unused input pins.
2. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
3. HSRUN mode must not be used at 125°C. Max ambient temperature for HSRUN mode is 105°C.
4. Values mentioned for S32K14x devices are measured at RUN@80 MHz with peripherals disabled and values mentioned for S32K11x devices are measured at
RUN@48 MHz with peripherals disabled.
5. With PMC_REGSC[CLKBIASDIS] set to 1. See Reference Manual for details.
6. Data collected using RAM
7. Numbers on limited samples size and data collected with Flash
8. The S32K148 data points assume that ENET/QuadSPI/SAI etc. are inactive.
Table 8. VLPS additional use-case power consumption at typical conditions
Use-case
Description
Temp.
Device
Unit
S32K116
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
S32K118
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
S32K142
S32K144
30
S32K146
30
S32K148
40
VLPS and RTC
• Clock source: LPO or RTC_CLKIN
25
85
30
110
230
570
230
320
490
890
100
170
260
530
670
880
1080
1970
250
340
430
740
2.99
3.26
3.5
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
mA
mA
mA
μA
μA
μA
μA
170
330
680
230
400
550
1070
100
240
400
580
690
960
1250
1980
250
340
430
760
3.19
3.7
180
240
105
125
25
350
490
810
1250
250
VLPS and LPUART
TX/RX
• Clock source: SIRC
• Transmiting or receiving continuously
using DMA
250
85
410
490
105
125
25
600
850
• Baudrate: 19.2 kbps
1250
110
1960
110
VLPS and LPUART
wake-up
• Clock source: SIRC
• Wake-up address feature enabled
• Baudrate: 19.2 kbps
85
280
350
105
125
25
480
600
1000
820
1280
900
VLPS and LPI2C
master
• Clock Source: SIRC
• Transmit/receive using DMA
• Baudrate: 100 kHz
85
1220
1660
2860
270
1370
2060
3690
280
105
125
25
VLPS and LPI2C
slave wake-up
• Clock source: SIRC
• Wake-up address feature enabled
• Baudrate: 100 kHz
85
410
510
105
125
25
610
810
1170
3.75
4.35
4.93
5.97
120
1540
4.11
4.93
5.74
7.38
130
VLPS and LPSPI
master
• Clock source: SIRC
• Transmit/receive using DMA
• Baudrate: 500 kHz
85
105
125
25
4.2
3.93
100
190
310
640
4.63
100
250
410
750
VLPS and LPIT
• Clock source: SIRC
• 1 channel enable
• Mode: 32-bit periodic counter
85
260
320
105
125
440
570
910
1280
General
The following table shows the power consumption targets for S32K148 in various mode
of operations measure at 3.3 V.
Table 9. Power consumption at 3.3 V
Chip/Device
Ambient
Temperature
(°C)
RUN@80 MHz (mA)
HSRUN@112 MHz (mA)1
Peripherals
enabled +
QSPI
Peripherals
enabled +
Peripherals
enabled +
QSPI
Peripherals
enabled +
ENET + SAI
ENET + SAI
S32K148
25
85
Typ
Typ
Max
Typ
Max
Max
67.3
67.4
82.5
68.0
80.3
83.5
79.1
79.2
88.2
79.8
89.1
94.7
89.8
95.6
105.5
105.9
117.4
106.7
119.0
109.7
96.6
105
125
109.0
NA
1. HSRUN mode must not be used at 125°C. Max ambient temperature for HSRUN mode is 105°C.
4.8 ESD handling ratings
Symbol
VHBM
Description
Min.
Max.
Unit
Notes
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
All pins except the corner pins
− 4000
4000
V
1
2
VCDM
− 500
− 750
− 100
500
750
100
V
V
Corner pins only
ILAT
Latch-up current at ambient temperature of 125 °C
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.9 EMC radiated emissions operating behaviors
EMC measurements to IC-level IEC standards are available from NXP on request.
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
21
I/O parameters
5 I/O parameters
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 7. Input signal measurement reference
5.2 General AC specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
50
—
ns
3
disabled, passive filter disabled) — Asynchronous path
WFRST
RESET input filtered pulse
—
10
—
ns
ns
4
5
WNFRST RESET input not filtered pulse
Maximum of
(100 ns, bus
clock period)
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop and VLPS modes, the synchronizer is bypassed so shorter pulses can be recognized in
that case.
2. The greater of synchronous and asynchronous timing must be met.
3. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized.
4. Maximum length of RESET pulse which will be filtered by internal filter.
5. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter. This number depends on bus clock
period also. For example, in VLPR mode bus clock is 4 MHz, which make clock period of 250 ns. In this case, minimum
pulse width which will cause reset is 250 ns. For faster bus clock frequencies which have clock period less than 100 ns,
the minimum pulse width not filtered will be 100 ns.
S32K1xx Data Sheet, Rev. 8, 06/2018
22
NXP Semiconductors
I/O parameters
5.3 DC electrical specifications at 3.3 V Range
NOTE
For details on the pad types defined in Table 11 and Table 12,
see Reference Manual section IO Signal Table and IO Signal
Description Input Multiplexing sheet(s) attached with
Reference Manual.
Table 11. DC electrical specifications at 3.3 V Range
Symbol
Parameter
Value
Typ.
3.3
—
Unit
Notes
Min.
2.7
Max.
VDD
Vih
I/O Supply Voltage
4
VDD + 0.3
0.3 × VDD
—
V
V
1
2
3
Input Buffer High Voltage
Input Buffer Low Voltage
Input Buffer Hysteresis
0.7 × VDD
VSS − 0.3
0.06 × VDD
3.5
Vil
—
V
Vhys
—
V
IohGPIO
I/O current source capability measured when
pad Voh = (VDD − 0.8 V)
—
—
mA
IohGPIO-HD_DSE_0
IolGPIO
IolGPIO-HD_DSE_0
IohGPIO-HD_DSE_1
I/O current sink capability measured when
pad Vol = 0.8 V
3
—
—
mA
I/O current source capability measured when
pad Voh = (VDD − 0.8 V)
14
12
—
—
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
4
4
5
5
5
5
IolGPIO-HD_DSE_1
I/O current sink capability measured when
pad Vol = 0.8 V
IohGPIO-FAST_DSE_0 I/O current sink capability measured when
pad Voh=VDD-0.8 V
9.5
10
—
IolGPIO-FAST_DSE_0 I/O current sink capability measured when
pad Vol = 0.8 V
—
IohGPIO-FAST_DSE_1 I/O current sink capability measured when
pad Voh=VDD-0.8 V
16
—
IolGPIO-FAST_DSE_1 I/O current sink capability measured when
pad Vol = 0.8 V
15.5
—
—
IOHT
IIN
Output high current total for all ports
100
Input leakage current (per pin) for full temperature range at VDD = 3.3 V
6
All pins other than high drive port pins
High drive port pins 7
0.005
0.010
0.5
0.5
60
μA
μA
kΩ
kΩ
RPU
RPD
Internal pullup resistors
20
20
8
9
Internal pulldown resistors
60
1. S32K148 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged S32K148 is guaranteed to
operate from 2.97 V. All other S32K family devices operate from 2.7 V in all modes.
2. For reset pads, same Vih levels are applicable
3. For reset pads, same Vil levels are applicable
4. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard
value given above.
5. For refernce only. Run simulations with the IBIS model and custom board for accurate results.
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
23
I/O parameters
6. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
other GPIOs are normal drive only. For details see IO Signal Description Input Multiplexing sheet(s) attached with the
Reference Manual.
7. When using ENET and SAI on S32K148, the overall device limits associated with high drive pin configurations must be
respected i.e. On 144-pin LQFP the general purpose pins: PTA10, PTD0, and PTE4 must be set to low drive.
8. Measured at input V = VSS
9. Measured at input V = VDD
5.4 DC electrical specifications at 5.0 V Range
Table 12. DC electrical specifications at 5.0 V Range
Symbol
Parameter
Value
Typ.
—
Unit
Notes
Min.
Max.
5.5
VDD
Vih
I/O Supply Voltage
4
V
V
Input Buffer High Voltage
0.65 x
VDD
—
VDD + 0.3
1
2
Vil
Input Buffer Low Voltage
Input Buffer Hysteresis
VSS − 0.3
—
—
0.35 x VDD
—
V
V
Vhys
0.06 x
VDD
IohGPIO
I/O current source capability measured
when pad Voh= (VDD - 0.8 V)
5
—
—
—
—
mA
mA
IohGPIO-HD_DSE_0
IolGPIO
IolGPIO-HD_DSE_0
IohGPIO-HD_DSE_1
I/O current sink capability measured
when pad Vol= 0.8 V
5
I/O current source capability measured
when pad Voh = VDD - 0.8 V
20
20
—
—
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
3
3
4
4
4
4
IolGPIO-HD_DSE_1
IohGPIO-FAST_DSE_0
IolGPIO-FAST_DSE_0
IohGPIO-FAST_DSE_1
IolGPIO-FAST_DSE_1
I/O current sink capability measured
when pad Vol = 0.8 V
I/O current sink capability measured
when pad Voh = VDD - 0.8 V
14.0
14.5
21
—
I/O current sink capability measured
when pad Vol= 0.8 V
—
I/O current sink capability measured
when pad Voh = VDD - 0.8 V
—
I/O current sink capability measured
when pad Vol= 0.8 V
20.5
—
—
IOHT
IIN
Output high current total for all ports
100
Input leakage current (per pin) for full temperature range at VDD = 5.5 V
5
All pins other than high drive port pins
High drive port pins
0.005
0.010
0.5
0.5
50
μA
μA
kΩ
kΩ
RPU
RPD
Internal pullup resistors
20
20
6
7
Internal pulldown resistors
50
1. For reset pads, same Vih levels are applicable
2. For reset pads, same Vil levels are applicable
3. The strong pad I/O pin is capable of switching a 50 pF load up to 40 MHz.
4. For refernce only. Run simulations with the IBIS model and custom board for accurate results.
S32K1xx Data Sheet, Rev. 8, 06/2018
24
NXP Semiconductors
I/O parameters
5. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
other GPIOs are normal drive only. For details refer to SK3K144_IO_Signal_Description_Input_Multiplexing.xlsx attached
with the Reference Manual.
6. Measured at input V = VSS
7. Measured at input V = VDD
5.5 AC electrical specifications at 3.3 V range
Table 13. AC electrical specifications at 3.3 V Range
Symbol
DSE
Rise time (nS) 1
Fall time (nS) 1
Capacitance (pF) 2
Min.
Max.
14.5
23.7
80.0
14.5
23.7
80.0
5.8
Min.
Max.
15.7
26.2
88.4
15.7
26.2
88.4
6.1
tRFGPIO
NA
3.2
5.7
20.0
3.2
5.7
20.0
1.5
2.4
6.3
0.6
3.0
12.0
0.4
1.5
7.4
3.4
6.0
25
50
20.8
3.4
200
25
tRFGPIO-HD
0
1
0
1
6.0
50
20.8
1.7
200
25
8.0
2.6
8.3
50
22.0
2.8
6.0
23.8
2.8
200
25
tRFGPIO-FAST
0.5
7.1
2.6
7.5
50
27.0
1.3
10.3
0.38
1.4
26.8
1.3
200
25
3.8
3.9
50
14.9
7.0
15.3
200
1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.
2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be
different, for example for ENET, QSPI etc. . For protocol specific AC specifications, see respective sections.
5.6 AC electrical specifications at 5 V range
Table 14. AC electrical specifications at 5 V Range
Symbol
DSE
Rise time (nS)1
Fall time (nS) 1
Capacitance (pF) 2
Min.
Max .
9.4
Min.
Max.
10.7
17.4
59.7
10.7
17.4
tRFGPIO
NA
2.8
5.0
2.9
5.1
25
50
15.7
54.8
9.4
17.3
2.8
17.6
2.9
200
25
tRFGPIO-HD
0
5.0
15.7
5.1
50
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
25
I/O parameters
Symbol
Table 14. AC electrical specifications at 5 V Range (continued)
DSE
Rise time (nS)1
Fall time (nS) 1
Capacitance (pF) 2
Min.
Max .
54.8
4.6
Min.
Max.
59.7
5.0
17.3
1.1
17.6
1.1
200
25
1
0
1
2.0
5.7
2.0
5.8
50
5.4
16.0
2.2
5.0
16.0
2.2
200
25
tRFGPIO-FAST
0.42
2.0
0.37
1.9
5.0
5.2
50
9.3
18.8
0.9
8.5
19.3
0.9
200
25
0.37
1.2
0.35
1.2
2.7
2.9
50
6.0
11.8
6.0
12.3
200
1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.
2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be
different, for example for ENET, QSPI etc. . For protocol specific AC specifications, see respective sections.
5.7 Standard input pin capacitance
Table 15. Standard input pin capacitance
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance: digital pins
—
7
pF
NOTE
Please refer to External System Oscillator electrical
specifications for EXTAL/XTAL pins.
5.8 Device clock specifications
Table 16. Device clock specifications 1
Symbol
Description
Min.
Max.
Unit
High Speed run mode2
fSYS
fBUS
System and core clock
Bus clock
—
—
—
112
56
MHz
MHz
MHz
fFLASH
Flash clock
28
Normal run mode (S32K11x series)
fSYS
fBUS
System and core clock
Bus clock
—
—
48
48
MHz
MHz
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
26
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 16. Device clock specifications 1 (continued)
Symbol
Description
Min.
Max.
Unit
fFLASH
Flash clock
—
24
MHz
Normal run mode (S32K14x series) 3
fSYS
fBUS
System and core clock
Bus clock
—
—
—
80
404
MHz
MHz
MHz
fFLASH
Flash clock
26.67
VLPR mode5
fSYS
fBUS
fFLASH
fERCLK
System and core clock
Bus clock
—
—
—
—
4
4
MHz
MHz
MHz
MHz
Flash clock
1
External reference clock
16
1. Refer to the section Feature comparison for the availability of modes and other specifications.
2. Only available on some devices. See section Feature comparison.
3. With SPLL as system clock source.
4. 48 MHz when fSYS is 48 MHz
5. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
6 Peripheral operating requirements and behaviors
6.1 System modules
There are no electrical specifications necessary for the device's system modules.
6.2 Clock interface modules
6.2.1 External System Oscillator electrical specifications
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
27
Clock interface modules
Single input comparator
(EXTAL WAVE)
ref_clk
Mux
Differential input comparator
(HG/LP mode)
Peak detector
LP mode
Driver
(HG/LP mode)
Pull down resistor (OFF)
ESD PAD
280 ohms
ESD PAD
40 ohms
XTAL pin
EXTAL pin
Series resistor for current
limitation
1M ohms Feedback Resistor
Crystal or resonator
C1
C2
Figure 8. Oscillator connections scheme
Table 17. External System Oscillator electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
gmXOSC Crystal oscillator transconductance
SCG_SOSCCFG[RANGE]=2'b10 for 4-8 MHz
SCG_SOSCCFG[RANGE]=2'b11 for 8-40 MHz
2.2
16
—
—
—
—
13.7
47
mA/V
mA/V
V
VIL
VIH
Input low voltage — EXTAL pin in external clock mode
VSS
1.15
VDD
Input high voltage — EXTAL pin in external clock
mode
0.7 * VDD
V
C1
C2
RF
EXTAL load capacitance
XTAL load capacitance
Feedback resistor
—
—
—
—
—
—
1
1
2
Low-gain mode (HGO=0)
—
—
—
MΩ
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
28
NXP Semiconductors
Clock interface modules
Table 17. External System Oscillator electrical specifications
(continued)
Symbol Description
High-gain mode (HGO=1)
Series resistor
Min.
Typ.
Max.
Unit
Notes
—
1
—
MΩ
RS
Low-gain mode (HGO=0)
—
—
0
0
—
—
kΩ
kΩ
High-gain mode (HGO=1)
Vpp
Peak-to-peak amplitude of oscillation (oscillator mode)
Low-gain mode (HGO=0)
3
—
—
1.0
3.3
—
—
V
V
High-gain mode (HGO=1)
1. Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit. The gm_crit is defined as:
gm_crit = 4 * ESR * (2πF)2 * (C0 + CL)2
where:
• gmXOSC is the transconductance of the internal oscillator circuit
• ESR is the equivalent series resistance of the external crystal
• F is the external crystal oscillation frequency
• C0 is the shunt capacitance of the external crystal
• CL is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)]
• Cs is stray or parasitic capacitance on the pin due to any PCB traces
• C1, C2 external load capacitances on EXTAL and XTAL pins
See manufacture datasheet for external crystal component values
2.
• When low-gain is selected, internal RF will be selected and external RF should not be attached.
• When high-gain is selected, external RF (1 M Ohm) needs to be connected for proper operation of the crystal. For
external resistor, up to 5% tolerance is allowed.
3. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.2.2 External System Oscillator frequency specifications
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
29
Table 18. External System Oscillator frequency specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
S32K14x
S32K11x
S32K14x
S32K11x
S32K14x
S32K11x
fosc_hi
fec_extal
tdc_extal
tcst
Oscillator crystal or resonator
frequency
4
—
—
50
40
MHz
MHz
%
Input clock frequency (external clock
mode)
—
48
50
48
1
1
Input clock duty cycle (external clock
mode)
52
Crystal Start-up Time
8 MHz low-gain mode (HGO=0)
8 MHz high-gain mode (HGO=1)
40 MHz low-gain mode (HGO=0)
40 MHz high-gain mode (HGO=1)
—
—
—
—
1.5
2.5
2
—
—
—
—
ms
2
2
1. Frequencies below 40 MHz can be used for degraded duty cycle upto 40-60%
2. Proper PC board layout procedures must be followed to achieve specifications.
System Clock Generation (SCG) specifications
6.2.3 System Clock Generation (SCG) specifications
6.2.3.1 Fast internal RC Oscillator (FIRC) electrical specifications
Table 19. Fast internal RC Oscillator electrical specifications
Symbol
Parameter1
Value
Typ.
48
Unit
Min.
Max.
FFIRC
FIRC target frequency
—
—
MHz
ΔF
Frequency deviation across process, voltage, and
temperature < 105°C
—
—
0.5
0.5
1
%FFIRC
ΔF125
Frequency deviation across process, voltage, and
temperature < 125°C
1.1
%FFIRC
TStartup
Startup time
3.4
300
0.04
5
µs2
ps
, 3
TJIT
Cycle-to-Cycle jitter
Long term jitter over 1000 cycles
—
—
500
0.1
3
TJIT
%FFIRC
1. With FIRC regulator enable
2. Startup time is defined as the time between clock enablement and clock availability for system use.
3. FIRC as system clock
NOTE
Fast internal RC Oscillator is compliant with CAN and LIN
standards.
6.2.3.2 Slow internal RC oscillator (SIRC) electrical specifications
Table 20. Slow internal RC oscillator (SIRC) electrical specifications
Symbol
Parameter
Value
Typ.
8
Unit
Min.
—
Max.
—
FSIRC
SIRC target frequency
MHz
ΔF
Frequency deviation across process, voltage, and
temperature < 105°C
—
—
3
%FSIRC
ΔF125
Frequency deviation across process, voltage, and
temperature < 125°C
—
—
—
9
3.3
%FSIRC
µs1
TStartup
Startup time
12.5
1. Startup time is defined as the time between clock enablement and clock availability for system use.
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
31
Memory and memory interfaces
6.2.4 Low Power Oscillator (LPO) electrical specifications
Table 21. Low Power Oscillator (LPO) electrical specifications
Symbol
FLPO
Parameter
Internal low power oscillator frequency
Startup Time
Min.
113
—
Typ.
128
—
Max.
139
20
Unit
kHz
µs
Tstartup
6.2.5 SPLL electrical specifications
Table 22. SPLL electrical specifications
Symbol
Parameter
PLL Reference Frequency Range
PLL Input Frequency
Min.
8
Typ.
—
Max.
Unit
1
2
FSPLL_REF
16
40
MHz
MHz
MHz
MHz
FSPLL_Input
FVCO_CLK
FSPLL_CLK
JCYC_SPLL
8
—
VCO output frequency
180
90
—
320
160
PLL output frequency
PLL Period Jitter (RMS)3
—
at FVCO_CLK 180 MHz
—
—
120
75
—
—
ps
ps
at FVCO_CLK 320 MHz
JACC_SPLL
PLL accumulated jitter over 1µs (RMS)3
at FVCO_CLK 180 MHz
—
1350
600
—
—
—
ps
ps
%
s
at FVCO_CLK 320 MHz
—
DUNL
Lock exit frequency tolerance
TSPLL_LOCK Lock detector detection time4
4.47
—
5.97
150 × 10-6
+
—
1075(1/FSPLL_REF
)
1. FSPLL_REF is PLL reference frequency range after the PREDIV. For PREDIV and MULT settings refer SCG_SPLLCFG
register of Reference Manual.
2. FSPLL_Input is PLL input frequency range before the PREDIV must be limited to the range 8 MHz to 40 MHz. This input
source could be derived from a crystal oscillator or some other external square wave clock source using OSC bypass
mode. For external clock source settings refer SCG_SOSCCFG register of Reference Manual.
3. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each
PCB and results will vary
4. Lock detector detection time is defined as the time between PLL enablement and clock availability for system use.
6.3 Memory and memory interfaces
6.3.1 Flash memory module (FTFC) electrical specifications
This section describes the electrical characteristics of the flash memory module.
S32K1xx Data Sheet, Rev. 8, 06/2018
32
NXP Semiconductors
Memory and memory interfaces
6.3.1.1 Flash timing specifications — commands
Table 23. Flash command timing specifications for S32K14x
Symbol
Description1
S32K142
Typ Max
S32K144
Typ Max
S32K146
Typ Max
S32K148
Typ Max Unit Notes
trd1blk
Read 1 Block
execution time
32 KB flash
64 KB flash
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ms
0.5
—
0.5
—
0.5
—
—
128 KB flash —
256 KB flash —
512 KB flash —
—
2
—
—
—
—
1.8
75
100
95
2
2
trd1sec
Read 1 Section 2 KB flash
execution time
—
—
—
75
100
95
75
100
95
75
100
100
µs
4 KB flash
tpgmchk
tpgm8
Program Check
execution time
—
µs
µs
ms
Program Phrase —
execution time
90
225
90
225
90
225
90
225
tersblk
Erase Flash
Block execution
time
32 KB flash
—
64 KB flash 30
128 KB flash —
256 KB flash 250
512 KB flash —
—
—
—
—
—
—
—
—
—
—
2
2
550
—
30
—
550
—
30
—
550
—
—
—
2125
—
—
—
—
—
—
250
12
4250
130
250
12
4250 250
4250
130
tersscr
Erase Flash
Sector execution
time
—
12
130
130
12
ms
ms
ms
tpgmsec1k
Program Section —
execution time
(1KB flash)
5
—
5
—
5
—
5
—
trd1all
Read 1s All
Block execution
time
—
—
2.8
—
2.3
—
5.2
—
8.2
trdonce
tpgmonce
tersall
Read Once
execution time
—
—
—
30
—
—
30
—
30
—
—
30
—
µs
µs
Program Once
execution time
90
250
—
90
—
90
700
—
90
Erase All Blocks —
execution time
2800 400
35
4900
35
10000 1400 17000 ms
35 35 µs
2
tvfykey
Verify Backdoor
Access Key
—
—
—
execution time
tersallu
Erase All Blocks —
Unsecure
execution time
250
70
2800 400
4900
—
700
70
10000 1400 17000 ms
2
3
tpgmpart
Program
32 KB
—
—
70
71
—
—
—
—
—
ms
Partition for
EEPROM
EEPROM
backup
execution time
64 KB
71
—
71
150
EEPROM
backup
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
33
Memory and memory interfaces
Table 23. Flash command timing specifications for S32K14x (continued)
Symbol
Description1
S32K142
Typ Max
S32K144
Typ Max
S32K146
Typ Max
S32K148
Typ Max Unit Notes
tsetram
Set FlexRAM
Control
0.08
—
0.08
—
0.08
—
0.08
—
ms
3
Function
Code 0xFF
execution time
32 KB
0.8
1.2
0.8
1.2
0.8
1.2
—
—
EEPROM
backup
48 KB
EEPROM
backup
1
1.5
1.9
1
1.5
1
1.5
—
1.3
—
—
—
64 KB
EEPROM
backup
1.3
385
430
475
385
430
475
360
1.3
1.9
1.3
385
430
475
385
430
475
360
1.9
1.9
—
teewr8b
Byte write to
FlexRAM
32 KB
EEPROM
backup
1700 385
1850 430
2000 475
1700 385
1850 430
2000 475
2000 360
1700
1850
2000
1700
1850
2000
2000
1700
1850
µs
3,4
execution time
48 KB
EEPROM
backup
—
64 KB
EEPROM
backup
2000 475
4000
—
teewr16b
16-bit write to
FlexRAM
32 KB
EEPROM
backup
1700
1850
—
—
µs
3,4
execution time
48 KB
EEPROM
backup
—
64 KB
EEPROM
backup
2000 475
2000 360
4000
2000
teewr32bers
32-bit write to
erased FlexRAM
location
—
µs
µs
execution time
teewr32b
32-bit write to
FlexRAM
execution time
32 KB
EEPROM
backup
630
720
810
200
2000 630
2125 720
2250 810
2000
2125
2250
630
720
810
2000
2125
—
—
—
3,4
48 KB
EEPROM
backup
—
64 KB
EEPROM
backup
2250 810
4500
tquickwr
32-bit Quick
Write execution write
time: Time from
CCIF clearing
(start the write)
until CCIF
1st 32-bit
550
550
200
150
550
550
200
150
550
550
200
150
1100
550
µs
4,5,6
2nd through 150
Next to Last
(Nth-1) 32-
bit write
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
34
NXP Semiconductors
Memory and memory interfaces
Table 23. Flash command timing specifications for S32K14x (continued)
Symbol
Description1
S32K142
Typ Max
S32K144
Typ Max
S32K146
Typ Max
S32K148
Typ Max Unit Notes
setting (32-bit
Last (Nth)
32-bit write
(time for
write only,
not cleanup)
200
550
200
550
200
550
200
550
write complete,
ready for next
32-bit write)
tquickwrClnup Quick Write
Cleanup
—
—
(# of
—
(# of
—
(# of
—
(# of
ms
7
Quick
Writes
) * 2.0
Quick
Writes )
* 2.0
Quick
Writes
) * 2.0
Quick
Writes
) * 2.0
execution time
1. All command times assumes 25 MHz or greater flash clock frequency (for synchronization time between internal/external
clocks).
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred. This may
be verified by executing FCCOB Command 0x77, and checking FCCOB number 5 contents show 0x00 - No EEPROM
issues detected.
4. 1st time EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2× the
times shown.
5. Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur
after this point even after a brownout or reset. If power on reset occurs before the Nth write completes, the last valid record
set will still be valid and the new records will be discarded.
6. Quick Write times may take up to 550 µs, as additional cleanup may occur when crossing sector boundaries.
7. Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes,
assuming still powered. Or via SETRAM cleanup execution command is requested at a later point.
Table 24. Flash command timing specifications for S32K11x
Symbol
Description1
S32K116
Typ Max
S32K118
Max
Typ
Unit
ms
Notes
trd1blk
Read 1 Block execution 32 KB flash
—
—
—
—
—
—
—
—
0.36
—
—
—
—
—
—
—
—
—
0.36
—
time
64 KB flash
128 KB flash
256 KB flash
512 KB flash
1.2
—
—
2
—
—
trd1sec
Read 1 Section
execution time
2 KB flash
4 KB flash
—
75
75
µs
100
100
100
100
tpgmchk
tpgm8
Program Check
execution time
µs
µs
ms
Program Phrase
execution time
—
90
225
90
225
tersblk
Erase Flash Block
execution time
32 KB flash
64 KB flash
128 KB flash
256 KB flash
512 KB flash
15
—
300
—
15
—
—
300
—
2
120
—
1100
—
—
250
—
2125
—
—
—
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
35
Memory and memory interfaces
Table 24. Flash command timing specifications for S32K11x (continued)
Symbol
Description1
S32K116
Typ Max
S32K118
Max
Typ
Unit
ms
Notes
tersscr
Erase Flash Sector
execution time
—
—
12
5
130
12
5
130
2
tpgmsec1k
Program Section
execution time (1 KB
flash)
—
—
ms
trd1all
Read 1s All Block
execution time
—
—
—
1.7
30
—
—
90
2.8
30
ms
µs
trdonce
tpgmonce
tersall
Read Once execution
time
—
Program Once execution —
time
90
—
—
µs
Erase All Blocks
execution time
—
—
—
150
—
1500
35
230
—
2500
35
ms
µs
2
tvfykey
tersallu
tpgmpart
Verify Backdoor Access
Key execution time
Erase All Blocks
Unsecure execution time
150
1500
—
230
71
2500
—
ms
ms
2
3
Program Partition for
32 KB EEPROM 71
EEPROM execution time backup
64 KB EEPROM
—
—
—
—
backup
tsetram
Set FlexRAM Function
execution time
Control Code
0xFF
0.08
—
0.08
0.8
—
—
ms
3
32 KB EEPROM 0.8
backup
1.2
—
1.2
—
48 KB EEPROM
backup
—
64 KB EEPROM
backup
—
—
—
—
teewr8b
Byte write to FlexRAM
execution time
32 KB EEPROM 385
backup
1700
—
385
—
1700
—
µs
µs
µs
3,4
48 KB EEPROM
backup
—
64 KB EEPROM
backup
—
—
—
—
teewr16b
16-bit write to FlexRAM 32 KB EEPROM 385
execution time
1700
—
385
—
1700
—
3,4
backup
48 KB EEPROM
backup
—
64 KB EEPROM
backup
—
—
—
—
teewr32bers
32-bit write to erased
FlexRAM location
execution time
—
360
2000
360
2000
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
36
NXP Semiconductors
Memory and memory interfaces
Table 24. Flash command timing specifications for S32K11x (continued)
Symbol
Description1
S32K116
Typ Max
32-bit write to FlexRAM 32 KB EEPROM 630
S32K118
Max
Typ
630
Unit
µs
Notes
3,4
teewr32b
2000
—
2000
execution time
backup
48 KB EEPROM
backup
—
—
—
—
64 KB EEPROM
backup
—
—
—
tquickwr
32-bit Quick Write
1st 32-bit write
200
550
550
200
150
550
550
µs
4,5,6
execution time: Time
from CCIF clearing (start
the write) until CCIF
setting (32-bit write
complete, ready for next
32-bit write)
2nd through Next 150
to Last (Nth-1)
32-bit write
Last (Nth) 32-bit 200
write (time for
write only, not
cleanup)
550
200
—
550
tquickwrClnup
Quick Write Cleanup
execution time
—
—
(# of
(# of Quick
Writes ) * 2.0
ms
7
Quick
Writes ) *
2.0
1. All command times assume 25 MHz or greater flash clock frequency (for synchronization time between internal/external
clocks).
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred. This may
be verified by executing FCCOB Command 0x77, and checking FCCOB number 5 contents show 0x00 - No EEPROM
issues detected.
4. 1st time EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2x the
times shown.
5. Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur
after this point even after a brownout or reset. If power on reset occurs before the Nth write completes, the last valid record
set will still be valid and the new records will be discarded.
6. Quick Write times may take up to 550 µs, as additional cleanup may occur when crossing sector boundaries.
7. Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes,
assuming still powered. Or via SETRAM cleanup execution command is requested at a later point.
NOTE
Under certain circumstances FlexMEM maximum times may be
exceeded. In this case the user or application may wait, or assert
reset to the FTFC macro to stop the operation.
6.3.1.2 Reliability specifications
Table 25. NVM reliability specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
When using as Program and Data Flash
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
20
—
—
—
—
years
1
1 K
cycles
2, 3
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
37
Memory and memory interfaces
Table 25. NVM reliability specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
When using FlexMemory feature : FlexRAM as Emulated EEPROM
tnvmretee Data retention
5
—
—
years
4
Write endurance
nnvmwree16
5, 6, 7
100 K
1.6 M
—
—
—
—
writes
writes
• EEPROM backup to FlexRAM ratio = 16
nnvmwree256
• EEPROM backup to FlexRAM ratio = 256
1. Data retention period per block begins upon initial user factory programming or after each subsequent erase.
2. Program and Erase for PFlash and DFlash are supported across product temperature specification in Normal Mode (not
supported in HSRUN mode).
3. Cycling endurance is per DFlash or PFlash Sector.
4. Data retention period per block begins upon initial user factory programming or after each subsequent erase. Background
maintenance operations during normal FlexRAM usage extend effective data retention life beyond 5 years.
5. FlexMemory write endurance specified for 16-bit and/or 32-bit writes to FlexRAM and is supported across product
temperature specification in Normal Mode (not supported in HSRUN mode). Greater write endurance may be achieved
with larger ratios of EEPROM backup to FlexRAM.
6. For usage of any EEE driver other than the FlexMemory feature, the endurance spec will fall back to the specified
endurance value of the D-Flash specification (1K).
7. FlexMemory calculator tool is available at NXP web site for help in estimation of the maximum write endurance achievable
at specific EEPROM/FlexRAM ratios. The “In Spec” portions of the online calculator refer to the NVM reliability
specifications section of data sheet. This calculator is only applies to the FlexMemory feature.
6.3.2 QuadSPI AC specifications
The following table describes the QuadSPI electrical characteristics.
• Measurements are with maximum output load of 25 pF, input transition of 1 ns and
pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the
interface should be OFF.
• Add 50 ohm series termination on board in QuadSPI SCK for Flash A to avoid loop
back reflection when using in Internal DQS (PAD Loopback) mode.
• QuadSPI trace length should be 3 inches.
• For non-Quad mode of operation if external device doesn’t have pull-up feature,
external pull-up needs to be added at board level for non-used pads.
• With external pull-up, performance of the interface may degrade based on load
associated with external pull-up.
S32K1xx Data Sheet, Rev. 8, 06/2018
38
NXP Semiconductors
Table 26. QuadSPI electrical specifications
FLASH PORT
Sym Unit
FLASH A
FLASH B
RUN1
SDR
HSRUN1
SDR
RUN/HSRUN2
QuadSPI Mode
SDR
DDR3
Internal
Internal DQS
Internal
Internal DQS
Internal
External DQS
Sampling
Sampling
Sampling
N1
PAD
Internal
N1
PAD
Internal
N1
External DQS
Loopback
Loopback
Loopback
Loopback
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Register Settings
MCR[DDR_EN]
MCR[DQS_EN]
-
-
-
-
-
-
-
-
-
0
0
-
0
1
1
1
-
0
1
0
0
-
0
0
-
0
1
1
1
-
0
1
0
0
-
0
0
-
1
1
-
MCR[SCLKCFG[0]]
MCR[SCLKCFG[1]]
MCR[SCLKCFG[2]]
MCR[SCLKCFG[3]]
MCR[SCLKCFG[5]]
SMPR[FSPHS]
-
-
-
-
-
-
-
0
0
1
0
0
-
-
-
-
-
-
-
-
0
0
0
-
0
1
0
0
0
0
0
23
0
0
0
-
0
1
0
0
0
0
0
30
0
0
0
-
SMPR[FSDLY]
SOCCR
[SOCCFG[7:0]]
SOCCR[SOCCFG[15:8]]
FLSHCR[TDH]
-
-
-
-
-
-
-
-
-
30
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
Timing Parameters
SCK Clock Frequency
SCK Clock Period
fSCK
tSCK
MHz
ns
-
38
-
-
64
-
-
48
-
-
40
-
-
80
-
-
50
-
-
20
-
-
204
-
50.0
50.04
Table continues on the next page...
Table 26. QuadSPI electrical specifications (continued)
FLASH PORT
Sym Unit
FLASH A
FLASH B
RUN1
SDR
HSRUN1
SDR
RUN/HSRUN2
QuadSPI Mode
SDR
DDR3
Internal
Internal DQS
Internal
Internal DQS
Internal
External DQS
Sampling
Sampling
Sampling
N1
PAD
Internal
N1
PAD
Internal
N1
External DQS
Loopback
Loopback
Loopback
Loopback
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
SCK Duty Cycle
tSDC
ns
Data Input Setup Time
Data Input Hold Time
Data Output Valid Time
tIS
tIH
ns
ns
ns
ns
15
0
-
-
-
2.5
-
-
10
1
-
-
-
14
0
-
-
-
1.6
-
-
9
1
-
-
-
25
0
-
-
-
2
20
-
-
-
1
-
1
-
tOV
tIV
4.5
5
4.5
5
4.5
5
4
5
4
35
4
5
10
5
10
-
Data Output In-Valid
Time
-
-
-
-
-
-
-
5
CS to SCK Time 6
SCK to CS Time 7
Output Load
tCSSCK
tSCKCS
ns
ns
pf
5
5
-
-
5
5
-
-
5
5
-
-
5
5
-
-
5
5
-
-
5
5
-
-
10
5
-
-
10
5
-
-
25
25
25
25
25
25
25
25
1. See Reference Manual for details on mode settings
2. See Reference Manual for details on mode settings
3. Valid for HyperRAM only
4. RWDS(External DQS CLK) frequency
5. For operating frequency ≤ 64 Mhz,Output invalid time is 5 ns.
6. Program register value QuadSPI_FLSHCR[TCSS] = 4`h2
7. Program register value QuadSPI_FLSHCR[TCSH] = 4`h1
Memory and memory interfaces
1
2
3
Clock
SCK
CS
tSCK
tSDC
tSDC
tIH
tIS
Data in
Figure 9. QuadSPI input timing (SDR mode) diagram
1
2
3
Clock
SCK
CS
tSCK
tSDC
tSDC
tSCKCS
tCSSCK
tIV
tOV
Invalid
Data out
Figure 10. QuadSPI output timing (SDR mode) diagram
TIS
TIS
TIH
TIH
invalid
invalid
D1
invalid
invalid
D4
D5
D2
D3
TIS– Setup Time
Figure 11. QuadSPI input timing (HyperRAM mode) diagram
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
41
Analog modules
SCK
tIV
tOV
Output Invalid Data
Figure 12. QuadSPI output timing (HyperRAM mode) diagram
6.4 Analog modules
6.4.1 ADC electrical specifications
6.4.1.1 12-bit ADC operating conditions
Table 27. 12-bit ADC operating conditions
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit Notes
VREFH ADC reference voltage high
See Voltage
and current
operating
VDDA
See Voltage
and current
operating
V
2
requirements
for values
requirements
for values
VREFL ADC reference voltage low
See Voltage
and current
operating
0
See Voltage mV
and current
operating
2
requirements
for values
requirements
for values
VADIN Input voltage
VREFL
—
—
—
VREFH
5
V
RS
Source impedendance
fADCK < 4 MHz
kΩ
kΩ
RSW1
Channel Selection Switch
Impedance
—
0.75
1.2
RAD
CP1
CP2
CS
Sampling Switch Impedance
Pin Capacitance
—
—
—
—
2
10
—
4
5
—
4
kΩ
pF
pF
pF
Analog Bus Capacitance
Sampling capacitance
5
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
42
NXP Semiconductors
ADC electrical specifications
Table 27. 12-bit ADC operating conditions (continued)
Symbol Description
fADCK ADC conversion clock
frequency
fCONV ADC conversion frequency
Conditions
Min.
Typ.1
Max.
Unit Notes
Normal usage
2
40
50
MHz
3, 4
No ADC hardware
averaging.5 Continuous
conversions enabled,
subsequent conversion
time
46.4
1.45
928
29
1160
Ksps
6, 7
ADC hardware averaging
set to 32. 5 Continuous
conversions enabled,
subsequent conversion
time
36.25
Ksps
6, 7
1. Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated.
Typical values are for reference only, and are not tested in production.
2. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSS
.
To get maximum performance, reference supply quality should be better than SAR ADC. See application note AN5032 for
details.
3. Clock and compare cycle need to be set according to the guidelines mentioned in the Reference Manual .
4. ADC conversion will become less reliable above maximum frequency.
5. When using ADC hardware averaging, see the Reference Manual to determine the most appropriate setting for AVGS.
6. Numbers based on the minimum sampling time of 275 ns.
7. For guidelines and examples of conversion rate calculation, see the Reference Manual section 'Calibration function'
Figure 13. ADC input impedance equivalency diagram
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
43
ADC electrical specifications
6.4.1.2 12-bit ADC electrical characteristics
NOTE
• ADC performance specifications are documented using a
single ADC. For parallel/simultaneous operation of both
ADCs, either for sampling the same channel by both ADCs
or for sampling different channels by each ADC, some
amount of decrease in performance can be expected. Care
must be taken to stagger the two ADC conversions, in
particular the sample phase, to minimize the impact of
simultaneous conversions.
• On reduced pin packages where ADC reference pins are
shared with supply pins, ADC analog performance
characteristics may be impacted. The amount of variation
will be directly impacted by the external PCB layout and
hence care must be taken with PCB routing. See AN5426
for details
Table 28. 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL = VSS)
Symbol Description
VDDA Supply voltage
Conditions 1
Min.
2.7
—
Typ.2
Max.
3
Unit
V
Notes
—
IDDA_ADC Supply current per ADC
SMPLTS Sample Time
0.6
—
—
mA
ns
3
275
Refer to
the
Reference
Manual
TUE4
DNL
INL
Total unadjusted error
Differential non-linearity
Integral non-linearity
—
—
—
4
8
—
—
LSB5
LSB5
LSB5
6, 7, 8, 9
6, 7, 8, 9
6, 7, 8, 9
1.0
2.0
1. All accuracy numbers assume the ADC is calibrated with VREFH=VDDA=VDD, with the calibration frequency set to less than
or equal to half of the maximum specified ADC clock frequency.
2. Typical values assume VDDA = 3 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF.
3. The ADC supply current depends on the ADC conversion rate.
4. Represents total static error, which includes offset and full scale error.
5. 1 LSB = (VREFH - VREFL)/2N
6. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device
use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings
for AVGS.
7. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC
performance may be observed.
8. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the
internal analog parameters, assume minor degradation.
9. All the parameters in the table are given assuming system clock as the clocking source for ADC.
S32K1xx Data Sheet, Rev. 8, 06/2018
44
NXP Semiconductors
ADC electrical specifications
Table 29. 12-bit ADC characteristics (3 V to 5.5 V)(VREFH = VDDA, VREFL = VSS)
Symbol Description
VDDA Supply voltage
Conditions 1
Min.
3
Typ.2
Max.
5.5
Unit
V
Notes
—
IDDA_ADC Supply current per ADC
SMPLTS Sample Time
—
1
—
mA
ns
3
275
—
Refer to
the
Reference
Manual
TUE4
DNL
INL
Total unadjusted error
Differential non-linearity
Integral non-linearity
—
—
—
4
8
—
—
LSB5
LSB5
LSB5
6, 7, 8, 9
6, 7, 8, 9
6, 7, 8, 9
0.7
1.0
1. All accuracy numbers assume the ADC is calibrated with VREFH=VDDA=VDD, with the calibration frequency set to less than
or equal to half of the maximum specified ADC clock frequency.
2. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated.
3. The ADC supply current depends on the ADC conversion rate.
4. Represents total static error, which includes offset and full scale error.
5. 1 LSB = (VREFH - VREFL)/2N
6. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device
use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings
for AVGS.
7. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC
performance may be observed.
8. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the
internal analog parameters, assume minor degradation.
9. All the parameters in the table are given assuming system clock as the clocking source for ADC.
NOTE
• Due to triple bonding in lower pin packages like 32-QFN,
48-LQFP, and 64-LQFP degradation might be seen in ADC
parameters.
• When using high speed interfaces such as the QuadSPI,
SAI0, SAI1 or ENET there may be some ADC degradation
on the adjacent analog input paths. See following table for
details.
Pin name
PTE8
TGATE purpose
CMP0_IN3
PTC3
ADC0_SE11/CMP0_IN4
ADC0_SE10/CMP0_IN5
CMP0_IN6
PTC2
PTD7
PTD6
CMP0_IN7
PTD28
PTD27
ADC1_SE22
ADC1_SE21
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
45
ADC electrical specifications
6.4.2 CMP with 8-bit DAC electrical specifications
Table 31. Comparator with 8-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
IDDHS
Supply current, High-speed mode1
μA
-40 - 125 ℃
—
230
300
IDDLS
Supply current, Low-speed mode1
-40 - 105 ℃
μA
—
6
6
11
13
-40 - 125 ℃
VAIN
VAIO
Analog input voltage
Analog input offset voltage, High-speed mode
-40 - 125 ℃
0
0 - VDDA
VDDA
V
mV
-25
-40
—
1
4
25
40
VAIO
Analog input offset voltage, Low-speed mode
mV
ns
-40 - 125 ℃
tDHSB
Propagation delay, High-speed mode2
-40 - 105 ℃
35
35
200
300
-40 - 125 ℃
tDLSB
tDHSS
tDLSS
Propagation delay, Low-speed mode2
µs
ns
µs
-40 - 105 ℃
—
—
0.5
0.5
2
3
-40 - 125 ℃
Propagation delay, High-speed mode3
-40 - 105 ℃
—
—
70
70
400
500
-40 - 125 ℃
Propagation delay, Low-speed mode3
-40 - 105 ℃
—
—
1
1
5
5
-40 - 125 ℃
tIDHS
Initialization delay, High-speed mode4
μs
μs
-40 - 125 ℃
—
—
—
1.5
10
0
3
tIDLS
Initialization delay, Low-speed mode4
-40 - 125 ℃
30
—
VHYST0
Analog comparator hysteresis, Hyst0
-40 - 125 ℃
mV
mV
VHYST1
Analog comparator hysteresis, Hyst1, High-speed
mode
-40 - 125 ℃
—
—
—
19
15
34
66
40
Analog comparator hysteresis, Hyst1, Low-speed
mode
-40 - 125 ℃
VHYST2
Analog comparator hysteresis, Hyst2, High-speed
mode
mV
-40 - 125 ℃
133
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
46
NXP Semiconductors
ADC electrical specifications
Table 31. Comparator with 8-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
80
Unit
Analog comparator hysteresis, Hyst2, Low-speed
mode
-40 - 125 ℃
—
23
VHYST3
Analog comparator hysteresis, Hyst3, High-speed
mode
mV
-40 - 125 ℃
—
46
200
120
Analog comparator hysteresis, Hyst3, Low-speed
mode
-40 - 125 ℃
—
32
IDAC8b
8-bit DAC current adder (enabled)
3.3V Reference Voltage
—
—
6
9
16
μA
μA
LSB6
LSB6
μs
5V Reference Voltage
10
—
—
—
INL5
DNL
tDDAC
8-bit DAC integral non-linearity
8-bit DAC differential non-linearity
Initialization and switching settling time
–0.75
–0.5
—
0.75
0.5
30
1. Difference at input > 200mV
2. Applied (100 mV + VHYST0/1/2/3+ max. of VAIO) around switch point.
3. Applied (30 mV + 2 × VHYST0/1/2/3+ max. of VAIO) around switch point.
4. Applied (100 mV + VHYST0/1/2/3).
5. Calculation method used: Linear Regression Least Square Method
6. 1 LSB = Vreference/256
NOTE
For comparator IN signals adjacent to VDD/VSS or XTAL/
EXTAL or switching pins cross coupling may happen and
hence hysteresis settings can be used to obtain the desired
comparator performance. Additionally, an external capacitor
(1nF) should be used to filter noise on input signal. Also, source
drive should not be weak (Signal with < 50 K pull up/down is
recommended).
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
47
ADC electrical specifications
Figure 14. Typical hysteresis vs. Vin level (VDDA = 3.3 V, PMODE = 0)
Figure 15. Typical hysteresis vs. Vin level (VDDA = 3.3 V, PMODE = 1)
S32K1xx Data Sheet, Rev. 8, 06/2018
48
NXP Semiconductors
ADC electrical specifications
Figure 16. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 0)
Figure 17. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 1)
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
49
Communication modules
6.5 Communication modules
6.5.1 LPUART electrical specifications
Refer to General AC specifications for LPUART specifications.
6.5.1.1 Supported baud rate
Baud rate = Baud clock / ((OSR+1) * SBR).
For details, see section: 'Baud rate generation' of the Reference Manual.
6.5.2 LPSPI electrical specifications
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable. The
following tables provide timing characteristics for classic LPSPI timing modes.
• All timing is shown with respect to 20% VDD and 80% VDD thresholds.
• All measurements are with maximum output load of 50 pF, input transition of 1 ns
and pad configured with fastest slew setting ( DSE = 1 ).
S32K1xx Data Sheet, Rev. 8, 06/2018
50
NXP Semiconductors
Table 32. LPSPI electrical specifications1
Num Symbol Description
Conditions
Run Mode2
HSRUN Mode2
5.0 V IO 3.3 V IO
VLPR Mode
5.0 V IO 3.3 V IO
Unit
5.0 V IO 3.3 V IO
Min.
Max.
40
Min.
Max.
40
Min.
Max.
56
Min.
Max.
56
Min.
Max.
Min.
Max.
, 3, 4
fperiph
Peripheral
Frequency
Slave
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
4
4
-
-
-
4
4
4
MHz
Master
40
40
56
56
Master
40
48
48
48
Loopback5
Master
-
48
-
48
-
48
-
48
-
4
-
4
Loopback(slow)6
1
2
3
fop
Frequency of Slave
-
-
-
10
10
20
-
-
-
10
10
12
-
-
-
14
14
24
-
-
-
14 7
14 7
12
-
-
-
2
2
2
-
-
-
2
2
2
MHz
operation
Master
Master
Loopback5
Master
-
12
-
12
-
12
-
12
-
2
-
2
Loopback(slow)6
tSPSCK SPSCK
period
Slave
100
100
50
-
-
-
100
100
83
-
-
-
72
72
42
-
-
-
72
72
83
-
-
-
500
500
500
-
-
-
500
500
500
-
-
-
ns
Master
Master
Loopback5
Master
83
-
-
83
-
-
83
-
-
83
-
-
500
-
-
500
-
-
Loopback(slow)6
8
tLead
Enable lead
Slave
-
-
-
-
-
-
-
-
-
-
-
-
ns
time (PCS to
SPSCK delay)
Master
Master
Loopback5
Master
Loopback(slow)6
Table continues on the next page...
Table 32. LPSPI electrical specifications1 (continued)
Num Symbol Description
Conditions
Run Mode2
HSRUN Mode2
VLPR Mode
5.0 V IO 3.3 V IO
Min. Max.
Unit
5.0 V IO 3.3 V IO
5.0 V IO 3.3 V IO
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
9
4
tLag
Enable lag
time (After
SPSCK delay)
Slave
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
Master
Master
Loopback5
Master
Loopback(slow)6
10
5
6
tWSPSCK Clock(SPSCK Slave
ns
ns
) high or low
time (SPSCK
duty cycle)
Master
Master
Loopback5
Master
Loopback(slow)6
tSU
Data setup
time(inputs)
Slave
3
-
-
5
-
-
3
-
-
5
3711
32 12
7
-
-
18
72
-
-
18
78
-
-
Master
29
38
26
Master
7
8
-
-
8
-
-
5
7
-
-
-
-
20
20
-
-
20
20
-
-
Loopback5
Master
10
9
Loopback(slow)6
7
tHI
Data hold
time(inputs)
Slave
3
0
3
-
-
-
3
0
3
-
-
-
3
0
2
-
-
-
3
0
3
-
-
-
14
0
-
-
-
14
0
-
-
-
ns
Master
Master
11
11
Loopback5
Master
3
-
3
-
3
-
3
-
12
-
12
-
Loopback(slow)6
Table continues on the next page...
Table 32. LPSPI electrical specifications1 (continued)
Num Symbol Description
Conditions
Run Mode2
HSRUN Mode2
VLPR Mode
5.0 V IO 3.3 V IO
Unit
5.0 V IO 3.3 V IO
5.0 V IO 3.3 V IO
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
8
9
ta
Slave access Slave
time
-
50
-
50
-
50
-
50
-
100
-
100
ns
ns
tdis
Slave MISO
(SOUT)
Slave
-
-
50
30
-
-
50
39
-
50
26
-
50
-
100
92
-
100
96
disable time
10
tv
Data valid
(after SPSCK
edge)
Slave
-
-
36 11
31 12
15
-
-
ns
Master
-
-
12
12
-
-
16
16
-
-
11
11
-
-
-
-
47
47
-
-
48
48
Master
15
Loopback5
Master
-
8
-
10
-
7
-
9
-
44
-
44
Loopback(slow)6
11
12
13
tHO
Data hold
time(outputs)
Slave
4
-
-
-
4
-
-
-
4
-
-
-
4
-
-
-
4
-
-
-
4
-
-
-
ns
ns
ns
Master
-15
-10
-22
-14
-15
-10
-23
-14
-22
-14
-29
-19
Master
Loopback5
Master
-15
-
-22
-
-15
-
-22
-
-21
-
-27
-
Loopback(slow)6
tRI/FI
Rise/Fall time Slave
input
-
-
-
1
-
-
-
1
-
-
-
1
-
-
-
1
-
-
-
1
-
-
-
1
Master
Master
Loopback5
Master
-
-
-
-
-
-
Loopback(slow)6
tRO/FO Rise/Fall time Slave
-
-
-
25
-
-
-
25
-
-
-
25
-
-
-
25
-
-
-
25
-
-
-
25
output
Master
Master
Loopback 5
Table continues on the next page...
Table 32. LPSPI electrical specifications1 (continued)
Num Symbol Description
Conditions
Run Mode2
HSRUN Mode2
5.0 V IO 3.3 V IO
Min. Max. Min. Max.
VLPR Mode
5.0 V IO 3.3 V IO
Min. Max. Min. Max.
Unit
5.0 V IO 3.3 V IO
Min.
Max.
Min.
Max.
Master
-
-
-
-
-
-
Loopback(slow)
6
1. Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode.
2. While transitioning from HSRUN mode to RUN mode, LPSPI output clock should not be more than 14 MHz.
3. fperiph = LPSPI peripheral clock
4. tperiph = 1/fperiph
5. Master Loopback mode - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1.
Clock pads used are PTD15 and PTE0. Applicable only for LPSPI0.
6. Master Loopback (slow) - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1.
Clock pad used is PTB2. Applicable only for LPSPI0.
7. This is the maximum operating frequency (fop) for LPSPI0 with medium PAD type only. Otherwise, the maximum operating frequency (fop) is 12 Mhz.
8. Set the PCSSCK configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where PCSSCK ranges from 0 to 255.
9. Set the SCKPCS configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where SCKPCS ranges from 0 to 255.
10. While selecting odd dividers, ensure Duty Cycle is meeting this parameter.
11. Maximum operating frequency (fop ) is 12 MHz irrespective of PAD type and LPSPI instance.
12. Applicable for LPSPI0 only with medium PAD type, with maximum operating frequency (fop) as 14 MHz.
Communication modules
1
SS
(OUTPUT)
3
2
12
12
13
13
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
MSB IN
LSB IN
10
11
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. LPSPI master mode timing (CPHA = 0)
1
SS
(OUTPUT)
2
12
12
13
13
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
11
BIT 6 . . . 1
10
MOSI
(OUTPUT)
2
PORT DATA
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 19. LPSPI master mode timing (CPHA = 1)
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
55
Communication modules
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
See
See
note 1
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
note1
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
Notes:
1. Undefined
Figure 20. LPSPI slave mode timing (CPHA = 0)
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
See
note 1
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
MOSI
(INPUT)
MSB IN
Notes:
1. Undefined
Figure 21. LPSPI slave mode timing (CPHA = 1)
6.5.3 LPI2C electrical specifications
See General AC specifications for LPI2C specifications.
For supported baud rate see section 'Chip-specific LPI2C information' of the Reference
Manual.
S32K1xx Data Sheet, Rev. 8, 06/2018
56
NXP Semiconductors
Communication modules
6.5.4 FlexCAN electical specifications
For supported baud rate, see section 'Protocol timing' of the Reference Manual.
6.5.5 SAI electrical specifications
The following table describes the SAI electrical characteristics.
• Measurements are with maximum output load of 50 pF, input transition of 1 ns and
pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the
interface should be OFF.
Table 33. Master mode timing specifications
Symbol
—
Description
Operating voltage
Min.
2.97
40
Max.
3.6
—
Unit
V
S1
SAI_MCLK cycle time
ns
MCLK period
ns
S2
SAI_MCLK pulse width high/low
SAI_BCLK cycle time
45%
80
55%
—
S3
S4
SAI_BCLK pulse width high/low
45%
28
55%
—
BCLK period
ns
S5
SAI_RXD input setup before
SAI_BCLK
S6
S7
SAI_RXD input hold after
SAI_BCLK
0
—
-2
28
0
—
8
ns
ns
ns
ns
ns
ns
ns
SAI_BCLK to SAI_TXD output
valid
S8
SAI_BCLK to SAI_TXD output
invalid
—
—
—
8
S9
SAI_FS input setup before
SAI_BCLK
S10
S11
S12
SAI_FS input hold after
SAI_BCLK
SAI_BCLK to SAI_FS output
valid
—
-2
SAI_BCLK to SAI_FS output
invalid
—
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
57
Communication modules
S1
S2
S2
SAI_MCLK (output)
SAI_BCLK (output)
SAI_FS (output)
SAI_FS (input)
SAI_TXD
S3
S4
S4
S11
S12
S10
S9
S7
S8
S7
S8
S5
S6
SAI_RXD
Figure 22. SAI Timing — Master modes
Table 34. Slave mode timing specifications
Symbol
Description
Min.
2.97
80
Max.
3.6
Unit
—
Operating voltage
V
ns
S13
S141
SAI_BCLK cycle time (input)
—
SAI_BCLK pulse width high/low
(input)
45%
55%
BCLK period
S15
S16
S17
S18
S19
SAI_RXD input setup before
SAI_BCLK
8
2
—
—
28
—
—
ns
ns
ns
ns
ns
SAI_RXD input hold after
SAI_BCLK
SAI_BCLK to SAI_TXD output
valid
—
0
SAI_BCLK to SAI_TXD output
invalid
SAI_FS input setup before
SAI_BCLK
8
S20
S21
S22
SAI_FS input hold after SAI_BCLK
SAI_BCLK to SAI_FS output valid
2
—
0
—
28
—
ns
ns
ns
SAI_BCLK to SAI_FS output
invalid
1. The slave mode parameters (S15 - S22) assume 50% duty cycle on SAI_BCLK input. Any change in SAI_BCLK duty cycle
input must be taken care during the board design or by the master timing.
S32K1xx Data Sheet, Rev. 8, 06/2018
58
NXP Semiconductors
Communication modules
S13
S14
SAI_BCLK (input)
SAI_FS (output)
SAI_FS (input)
SAI_TXD
S14
S21
S22
S19
S20
S17
S18
S17
S18
S15
S16
SAI_RXD
Figure 23. SAI Timing — Slave modes
6.5.6 Ethernet AC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
The following table describes the MII electrical characteristics.
• Measurements are with maximum output load of 25 pF, input transition of 1 ns and
pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the
interface should be OFF.
Table 35. MII signal switching specifications
Symbol
—
Description
Min.
—
Max.
25
Unit
RXCLK frequency
MHz
MII1
MII2
MII3
MII4
—
RXCLK pulse width high
35%
35%
5
65%
65%
—
RXCLK period
RXCLK pulse width low
RXCLK period
RXD[3:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[3:0], RXDV, RXER hold
TXCLK frequency
ns
5
—
ns
—
25
MHz
TXCLK period
TXCLK period
ns
MII5
MII6
MII7
MII8
TXCLK pulse width high
35%
35%
2
65%
65%
—
TXCLK pulse width low
TXCLK to TXD[3:0], TXEN, TXER invalid
TXCLK to TXD[3:0], TXEN, TXER valid
—
25
ns
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
59
Communication modules
MII2
MII3
MII1
MII4
RXCLK (input)
Valid data
RXD[n:0]
RXDV
Valid data
Valid data
RXER
Figure 24. MII receive diagram
MII6
MII5
TXCLK (input)
TXD[n:0]
TXEN
MII8
MII7
Valid data
Valid data
Valid data
TXER
Figure 25. MII transmit signal diagram
The following table describes the RMII electrical characteristics.
• Measurements are with maximum output load of 25 pF, input transition of 1 ns and
pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the
interface should be OFF.
Table 36. RMII signal switching specifications
Symbol
Description
Min.
—
Max.
50
Unit
—
RMII input clock RMII_CLK Frequency
MHz
RMII1, RMII5 RMII_CLK pulse width high
35%
65%
RMII_CLK
period
RMII2, RMII6 RMII_CLK pulse width low
35%
65%
RMII_CLK
period
RMII3
RMII4
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
Table continues on the next page...
4
2
—
—
ns
ns
S32K1xx Data Sheet, Rev. 8, 06/2018
60
NXP Semiconductors
Communication modules
Table 36. RMII signal switching specifications
(continued)
Symbol
RMII7
Description
Min.
2
Max.
—
Unit
ns
RMII_CLK to TXD[1:0], TXEN invalid
RMII_CLK to TXD[1:0], TXEN valid
RMII8
—
15
ns
RMII2
RMII3
RMII1
RMII4
RMII_CLK(input)
RXD[n:0]
Valid data
Valid data
Valid data
CRS_DV
RXER
Figure 26. RMII receive diagram
RMII6
RMII5
RMII_CLK (input)
TXD[n:0]
RMII8
RMII7
Valid data
Valid data
TXEN
Figure 27. RMII transmit diagram
The following table describes the MDIO electrical characteristics.
• Measurements are with maximum output load of 25 pF, input transition of 1 ns and
pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the
interface should be OFF.
• MDIO pin must have external Pull-up.
Table 37. MDIO timing specifications
Symbol
Description
MDC Clock Frequency
Min.
Max.
Unit
—
—
2.5
MHz
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
61
Debug modules
Table 37. MDIO timing specifications (continued)
Symbol
MDC1
MDC2
MDC3
MDC4
MDC5
Description
MDC pulse width high
Min.
40%
40%
25
Max.
60%
60%
—
Unit
MDC period
MDC pulse width low
MDC period
MDIO (input) to MDC rising edge setup
MDIO (input) to MDC rising edge hold
ns
ns
ns
0
—
MDC falling edge to MDIO output valid
(maximum propagation delay)
—
25
MDC6
MDC falling edge to MDIO output invalid
(minimum propagation delay)
-10
—
ns
MDC1
MDC2
MDC (output)
MDC6
MDIO (output)
MDIO (input)
MDC5
MDC3
MDC4
Figure 28. MII/RMII serial management channel timing diagram
6.5.7 Clockout frequency
Maximum supported clock out frequency for this device is 20 MHz
6.6 Debug modules
6.6.1 SWD electrical specofications
S32K1xx Data Sheet, Rev. 8, 06/2018
62
NXP Semiconductors
Table 38. SWD electrical specifications
Symbol
Description
Run Mode
HSRUN Mode
5.0 V IO 3.3 V IO
VLPR Mode
5.0 V IO 3.3 V IO
Min. Max.
Unit
5.0 V IO
Min. Max.
3.3 V IO
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
S1
SWD_CLK frequency of
operation
-
25
-
25
-
25
-
25
-
10
-
10
MHz
S2
S3
SWD_CLK cycle period
1/S1
-
1/S1
-
1/S1
-
1/S1
-
1/S1
-
1/S1
-
ns
ns
SWD_CLK clock pulse width
S4
S9
SWD_CLK rise and fall times
-
1
-
-
1
-
-
1
-
-
1
-
-
1
-
-
1
-
ns
ns
SWD_DIO input data setup time
to SWD_CLK rise
4
4
4
4
16
16
S10
S11
S12
S13
SWD_DIO input data hold time
after SWD_CLK rise
3
-
-
3
-
-
3
-
-
3
-
-
10
-
-
10
-
-
ns
ns
ns
ns
SWD_CLK high to SWD_DIO
data valid
28
28
-
38
38
-
28
28
-
38
38
-
70
70
-
77
77
-
SWD_CLK high to SWD_DIO
high-Z
-
-
-
-
-
-
SWD_CLK high to SWD_DIO
data invalid
0
0
0
0
0
0
Debug modules
S2
S4
S3
S3
SWD_CLK (input)
S4
Figure 29. Serial wire clock input timing
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
S9
S10
Input data valid
S11
S13
Output data valid
S12
Figure 30. Serial wire data timing
6.6.2 Trace electrical specifications
The following table describes the Trace electrical characteristics.
• Measurements are with maximum output load of 50 pF, input transition of 1 ns and
pad configured with fastest slew settings (DSE = 1'b1).
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the
interface should be OFF.
Table 39. Trace specifications
Symbol
Description
RUN Mode
HSRUN Mode
112 80
VLPR
Mode
Unit
—
Fsys
System frequency
80
48
40
4
MHz
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
64
NXP Semiconductors
Debug modules
Table 39. Trace specifications (continued)
Symbol
Description
RUN Mode
HSRUN Mode
VLPR
Unit
Mode
fTRACE
Max Trace frequency
Data Output Valid
Data Output Invalid
80
48
4
40
4
74.667
80
4
4
MHz
ns
tDVO
tDIV
4
4
20
-2
-2
-2
-2
-2
-10
ns
fTRACE
tDVO
tDIV
Max Trace frequency
Data Output Valid
Data Output Invalid
22.86
24
8
20
8
22.4
8
22.86
8
4
MHz
ns
8
20
-10
-4
-4
-4
-4
-4
ns
Figure 31. TRACE CLKOUT specifications
6.6.3 JTAG electrical specifications
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
65
Table 40. JTAG electrical specifications
Symbol
Description
Run Mode
3.3 V IO
Min. Max.
HSRUN Mode
5.0 V IO 3.3 V IO
VLPR Mode
5.0 V IO 3.3 V IO
Unit
5.0 V IO
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
JI
TCLK frequency of operation
Boundary Scan
JTAG
MHz
-
-
20
-
-
20
20
-
-
-
20
20
-
-
-
20
20
-
-
-
10
10
-
-
-
10
10
-
20
-
J2
J3
TCLK cycle period
TCLK clock pulse width
Boundary Scan
JTAG
1/JI
1/JI
1/JI
1/JI
1/JI
1/JI
ns
ns
J4
J5
TCLK rise and fall times
-
1
-
-
1
-
-
1
-
-
1
-
-
1
-
-
1
-
ns
ns
Boundary scan input data
setup time to TCLK rise
5
5
5
5
15
15
J6
J7
Boundary scan input data
hold time after TCLK rise
5
-
-
28
-
5
-
-
32
-
5
-
-
28
-
5
-
-
32
-
8
-
-
80
-
8
-
-
80
-
ns
ns
TCLK low to boundary scan
output data valid
J8
TCLK low to boundary scan
output data invalid
0
-
0
-
0
-
0
-
0
0
J9
TCLK low to boundary scan
output high-Z
28
-
32
-
28
-
32
-
-
80
-
-
80
-
ns
ns
ns
J10
J11
TMS, TDI input data setup
time to TCLK rise
3
2
3
2
3
2
3
2
15
8
15
8
TMS, TDI input data hold
time after TCLK rise
-
-
-
-
-
-
J12
J13
TCLK low to TDO data valid
-
28
-
-
32
-
-
28
-
-
32
-
-
80
-
-
80
-
ns
ns
TCLK low to TDO data
invalid
0
0
0
0
0
0
J14
TCLK low to TDO high-Z
-
28
-
32
-
28
-
32
-
80
-
80
ns
Debug modules
J2
J4
J3
J3
TCLK (input)
J4
Figure 32. Test clock input timing
TCLK
J5
J6
Input data valid
Data inputs
J7
J8
Output data valid
Data outputs
Data outputs
J9
Figure 33. Boundary scan (JTAG) timing
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
67
Thermal attributes
TCLK
J10
J11
Input data valid
TDI/TMS
J12
J13
Output data valid
TDO
TDO
J14
Figure 34. Test Access Port timing
7 Thermal attributes
7.1 Description
The tables in the following sections describe the thermal characteristics of the device.
NOTE
Junction temperature is a function of die size, on-chip power
dissipation, package thermal resistance, mounting side (board)
temperature, ambient temperature, air flow, power dissipation
or other components on the board, and board thermal resistance.
7.2 Thermal characteristics
S32K1xx Data Sheet, Rev. 8, 06/2018
68
NXP Semiconductors
Table 41. Thermal characteristics for 32-pin QFN and 48/64/100/144/176-pin LQFP package
Rating
Conditions
Symbol
Package
Values
Unit
S32K116 S32K118 S32K142 S32K144 S32K146 S32K148
Thermal resistance, Junction to Ambient
(Natural Convection)1, 2
Single layer
board (1s)
RθJA
32
48
93
79
NA
71
NA
NA
61
NA
NA
61
NA
NA
59
NA
NA
NA
NA
44
°C/W
64
NA
NA
NA
NA
50
62
100
144
176
32
NA
NA
NA
NA
50
53
52
51
NA
NA
NA
NA
45
NA
NA
NA
NA
45
51
NA
NA
NA
44
42
Thermal resistance, Junction to Ambient
(Natural Convection)1
Two layer
board (1s1p)
RθJA
NA
NA
NA
NA
37
48
58
64
NA
NA
NA
NA
32
46
100
144
176
32
NA
NA
NA
NA
47
42
42
40
NA
NA
NA
NA
43
NA
NA
NA
NA
43
44
NA
NA
NA
41
36
Thermal resistance, Junction to Ambient
(Natural Convection)1, 2
Four layer
board (2s2p)
RθJA
NA
NA
NA
NA
36
48
55
64
NA
NA
NA
NA
77
44
100
144
176
32
NA
NA
NA
NA
58
40
40
39
NA
NA
NA
NA
49
NA
NA
NA
NA
49
42
NA
NA
NA
48
35
Thermal resistance, Junction to Ambient
(@200 ft/min)1, 3
Single layer
board (1s)
RθJMA
NA
NA
NA
NA
36
48
66
64
NA
NA
NA
NA
43
50
100
144
176
32
NA
NA
NA
NA
43
43
42
41
NA
NA
NA
NA
38
NA
NA
NA
NA
38
42
NA
NA
NA
37
34
Thermal resistance, Junction to Ambient
(@200 ft/min)1
Two layer
board (1s1p)
RθJMA
NA
NA
NA
NA
48
51
64
NA
NA
39
100
NA
35
35
34
Table continues on the next page...
Table 41. Thermal characteristics for 32-pin QFN and 48/64/100/144/176-pin LQFP package
(continued)
Rating
Conditions
Symbol
Package
Values
Unit
S32K116 S32K118 S32K142 S32K144 S32K146 S32K148
144
176
32
NA
NA
26
NA
NA
NA
41
NA
NA
NA
NA
36
NA
NA
NA
NA
36
37
NA
NA
NA
35
31
30
Thermal resistance, Junction to Ambient
(@200 ft/min)1, 3
Four layer
board (2s2p)
RθJMA
NA
NA
NA
NA
30
48
48
64
NA
NA
NA
NA
11
37
100
144
176
32
NA
NA
NA
NA
24
34
34
33
NA
NA
NA
NA
25
NA
NA
NA
NA
25
36
NA
NA
NA
23
29
Thermal resistance, Junction to Board4
—
—
—
RθJB
NA
NA
NA
NA
24
48
33
64
NA
NA
NA
NA
NA
23
26
100
144
176
32
NA
NA
NA
NA
19
25
25
24
NA
NA
NA
NA
13
NA
NA
NA
NA
12
30
NA
NA
NA
11
24
Thermal resistance, Junction to Case 5
RθJC
NA
NA
NA
NA
9
48
64
NA
NA
NA
NA
1
14
100
144
176
32
NA
NA
NA
13
12
11
NA
NA
NA
NA
NA
12
NA
9
Thermal resistance, Junction to Case
(Bottom) 6
RθJCBottom
48
NA
64
100
144
176
Table continues on the next page...
Table 41. Thermal characteristics for 32-pin QFN and 48/64/100/144/176-pin LQFP package
(continued)
Rating
Conditions
Symbol
Package
Values
Unit
S32K116 S32K118 S32K142 S32K144 S32K146 S32K148
Thermal resistance, Junction to Package
Top7
Natural
Convection
ψJT
32
48
1
NA
2
NA
NA
2
NA
NA
2
NA
NA
2
NA
NA
NA
NA
1
4
64
NA
NA
NA
NA
2
100
144
176
NA
NA
NA
2
2
2
NA
NA
NA
NA
2
NA
1
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air
flow, power dissipation of other components on the board, and board thermal resistance.
2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.
3. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the
package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
6. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
7. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek
letters are not available, the thermal characterization parameter is written as Psi-JT.
Table 42. Thermal characteristics for the 100 MAPBGA package
Rating
Conditions
Symbol
Values
S32K144
61.0
Unit
S32K146
S32K148
Thermal resistance, Junction to Ambient (Natural
Convection) 1, 2
Single layer board (1s)
RθJA
RθJA
57.2
52.5
°C/W
°C/W
Thermal resistance, Junction to Ambient (Natural
Convection) 1, 2, 3
Four layer board
(2s2p)
32.1
35.6
27.5
Thermal resistance, Junction to Ambient (@200 ft/min) 1, 2, 3 Single layer board (1s)
RθJMA
RθJMA
44.1
27.2
46.6
30.9
39.0
22.8
°C/W
°C/W
Thermal resistance, Junction to Ambient (@200 ft/min)1, 3
Two layer board
(2s2p)
Thermal resistance, Junction to Board4
Thermal resistance, Junction to Case 5
—
—
—
RθJB
RθJC
ψJT
15.3
10.2
0.2
18.9
14.2
0.4
11.2
7.5
°C/W
°C/W
°C/W
Thermal resistance, Junction to Package Top outside
center6
0.2
Thermal resistance, Junction to Package Bottom outside
center7
—
ψJB
12.2
15.9
18.3
°C/W
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air
flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the
package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek
letters are not available, the thermal characterization parameter is written as Psi-JT.
7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12.
When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.
Thermal attributes
7.3 General notes for specifications at maximum junction
temperature
An estimation of the chip junction temperature, TJ, can be obtained from this equation:
where:
• TA = ambient temperature for the package (°C)
• RθJA = junction to ambient thermal resistance (°C/W)
• PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by
a factor of two. Which value is closer to the application depends on the power dissipated
by other components on the board. The value obtained on a single layer board is
appropriate for the tightly packed printed circuit board. The value obtained on the board
with the internal planes is usually appropriate if the board has low power dissipation and
the components are well separated.
When a heat sink is used, the thermal resistance is expressed in the following equation as
the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:
where:
• RθJA = junction to ambient thermal resistance (°C/W)
• RθJC = junction to case thermal resistance (°C/W)
• RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal
environment to change the case to ambient thermal resistance, RθCA. For instance, the
user can change the size of the heat sink, the air flow around the device, the interface
material, the mounting arrangement on printed circuit board, or change the thermal
dissipation on the printed circuit board surrounding the device.
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
73
Dimensions
To determine the junction temperature of the device in the application when heat sinks
are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using this equation:
where:
• TT = thermocouple temperature on top of the package (°C)
• ΨJT = thermal characterization parameter (°C/W)
• PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a
40 gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over
about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
8 Dimensions
8.1 Obtaining package dimensions
Package dimensions are provided in the package drawings.
To find a package drawing, go to http://www.nxp.com and perform a keyword search for
the drawing’s document number:
Package option
32-pin QFN
Document Number
SOT617-3 1
48-pin LQFP
98ASH00962A
98ASS23234W
98ASS23308W
98ASA00802D
98ASS23177W
98ASS23479W
64-pin LQFP
100-pin LQFP
100-pin MAPBGA
144-pin LQFP
176-pin LQFP
1. 5x5 mm package
S32K1xx Data Sheet, Rev. 8, 06/2018
74
NXP Semiconductors
Pinouts
9 Pinouts
9.1 Package pinouts and signal descriptions
For package pinouts and signal descriptions, refer to the Reference Manual.
10 Revision History
The following table provides a revision history for this document.
Table 43. Revision History
Rev. No.
Date
Substantial Changes
1
2
12 Aug 2016
03 March 2017
Initial release
• Updated descpition of QSPI and Clock interfaces in Key Features section
• Updated figure: High-level architecture diagram for the S32K1xx family
• Updated figure: S32K1xx product series comparison
• Added note in section Selecting orderable part number
• Updated figure: Ordering information
• In table: Absolute maximum ratings :
• Added footnote to IINJPAD_DC
• Updated min and max value of IINJPAD_DC
• Updated description, max and min values for IINJSUM
• Updated VIN_TRANSIENT
• In table: Voltage and current operating requirements :
• Renamed VSUP_OFF
• Updated max value of VDD_OFF
• Removed VINA and VIN
• Added VREFH and VREFL
• Updated footnote "Typical conditions assumes VDD = VDDA = VREFH = 5
V ...
• Removed INJSUM_AF
• Updated footnotes in table Table 4
• Updated section Power mode transition operating behaviors
• In table: Power consumption
• Added footnote "With PMC_REGSC[CLKBIASDIS] ... "
• Updated conditions for VLPR
• Removed Idd/MHz for S32K144
• Updated numbers for S32K142 and S32K148
• Removed use case footnotes
• In section Modes configuration :
• Replaced table "Modes configuration" with spreadsheet attachment:
'S32K1xx_Power_Modes _Master_configuration_sheet'
• In table: DC electrical specifications at 3.3 V Range :
• Added footnotes to Vih Input Buffer High Voltage and Vih Input Buffer
Low Voltage
• Added footnote to High drive port pins
• In table: DC electrical specifications at 5.0 V Range :
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
75
Revision History
Rev. No.
Table 43. Revision History
Date
Substantial Changes
• Added footnotes Vih Input Buffer High Voltage and Vih Input Buffer Low
Voltage
• Updated table: AC electrical specifications at 3.3 V range
• Updated table: AC electrical specifications at 5 V range
• In table: Standard input pin capacitance
• Added footnote to Normal run mode (S32K14x series)
• Removed note from 1M ohms Feedback Resistor in figure Oscillator
connections scheme
• In table: External System Oscillator electrical specifications
• Updated typical of IDDOSC Supply current — low-gain mode (low-power
mode) (HGO=0) 1 for 4 and 8 MHz
• Removed rows for Ilk_ext EXTAL/XTAL impedence High-frequency, low-
gain mode (low-power mode) and high-frequency, high-gain mode and
VEXTAL
• Updated Typ. of RS low-gain mode
• Updated description of RF, RS, and VPP
• Removed footnote from RF Feedback resistor
• Updated footnote for C1 C2 and RF
• In table: Table 18
• Removed mention of high-frequency
• Added HGO 0, 1 information
• In table: Fast internal RC Oscillator electrical specifications
• Updated FFIRC
• Updated description of ΔF
• Updated typ and max values of TJIT cycle-to-cycle jitter and TJIT Long
term jitter over 1000 cycles
• Added footnotes to TJIT cycle-to-cycle jitter and TJIT Long term jitter
over 1000 cycles
• Updated naming convention of IDDFIRC Supply current
• Added footnote to IDDFIRC Supply current
• Added footnote to column Parameter
• In table: Slow internal RC oscillator (SIRC) electrical specifications
• Removed VDD Supply current in 2 MHz Mode
• Removed footnote and updated description of ΔF
• Updated footnote to FSIRC and IDDSIRC
• In table: SPLL electrical specifications
• Added row for FSPLL_REF PLL Reference
• Updated naming convention throughout the table
• Updated the max value of TSPLL_LOCK Lock detector detection time
• In table: Flash timing specifications — commands
• Added footnotes:
• All command times assumes ...
• For all EEPROM Emulation terms ...
• 'First time' EERAM writes after a POR ...
• Removed footnote 'Assumes 25 MHz or ...'
• Updated Max of teewr32bers
• Added parameters tquickwr and tquickwrClnup
• In table: Reliability specifications
• Removed Typ. values for all parameters
• Removed footnote 'Typical values represent ... '
• Added footnote 'Any other EEE driver usage ... '
• Updated QuadSPI AC specifications
• Removed topic: Reliability, Safety and Security modules
• In table: 12-bit ADC operating conditions
• Updated VDDA
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
76
NXP Semiconductors
Revision History
Table 43. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Updated values for VREFH and VREFL to add refernce to the section
"voltage and current operating requirments" for Min and Max valaues
• Updated footnote to Typ.
• Removed footnote from RAS Analog source resistance
• Updated figure: ADC input impedance equivalency diagram
• In table: 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL
=
VSS
)
• Removed rows for VTEMP_S and VTEMP25
• Updated footnote to Typ.
• In table: 12-bit ADC characteristics (3 V to 5.5 V)(VREFH = VDDA, VREFL
=
VSS
)
• Removed rows for VTEMP_S and VTEMP25
• Removed number for TUE
• Updated footnote to Typ.
• In table: Comparator with 8-bit DAC electrical specifications
• Updated Typ. of IDDLS Supply current, Low-speed mode
• Updated Typ. of tDLSB Propagation delay, Low-speed mode
• Updated Typ. of tDHSS Propagation delay, High-speed mode
• Updated tDLSS Propagation delay
• Added row for tDDAC Initialization and switching settling time
• Updated footnote
• Updated section LPSPI electrical specifications
• Added section: SAI electrical specifications
• Updated section: Ethernet AC specifications
• Added section: Clockout frequency
• Added section: Trace electrical specifications
• Updated table: Table 41 : Updated numbers for S32K142 and S32K148
• Updated table: Table 42 : Updated numbers for S32K148
• Updated Document number for 32-pin QFN in topic Obtaining package
dimensions
3
14 March 2017
• In Table 2
• Updated min. value of VDD_OFF
• Added parameter IINJSUM_AF
• Updated Power mode transition operating behaviors
• Updated Power consumption
• Updated footnote to TSPLL_LOCK in SPLL electrical specifications
• In 12-bit ADC electrical characteristics
• Updated table: 12-bit ADC characteristics (2.7 V to 3 V) (VREFH =
VDDA, VREFL = VSS)
• Added typ. value to IDDA_ADC, TUE, DNL, and INL
• Added min. value to SMPLTS
• Removed footnote 'All the parameters in this table ... '
• Updated table: 12-bit ADC characteristics (3 V to 5.5 V) (VREFH =
VDDA, VREFL = VSS)
• Added typ. value to IDDA_ADC
• Removed footnote 'All the parameters in this table ... '
• In Flash timing specifications — commands updated Max. value of tvfykey to
33 μs
4
02 June 2017
• In section: Block diagram, added block diagram for S32K11x series.
• Updated figure: S32K1xx product series comparison.
• In section: Selecting orderable part number , added reference to attachement
S32K_Part_Numbers.xlsx.
• In section: Ordering information
• Updated figure: Ordering information.
• In Table 1,
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
77
Revision History
Rev. No.
Table 43. Revision History (continued)
Date
Substantial Changes
• Updated note 'All the limits defined ... '
• Updated parameter 'IINJPAD_DC_ABS', 'VIN_DC', IINJSUM_DC_ABS
• In Table 2,
• Updated parameter IINJPAD_DC_OP and IINJSUM_DC_OP
.
.
• In Table 5, updated TBDs for VLVR_HYST, VLVD_HYST, and VLVW_HYST
• In Power mode transition operating behaviors,
• Added VLPR → VLPS
• Added VLPS → VLPR
• Updated TBDs for VLPS → Asynchronous DMA Wakeup, STOP1 →
Asynchronous DMA Wakeup, and STOP2 → Asynchronous DMA
Wakeup
• In Table 7, updated the specifications for S32K144.
• Updated the attachment S32K1xx_Power_Modes _Configuration.xlsx.
• In Table 15, removed CIN_A
• In Table 17,
.
• Updated specificatins for gmXOSC
• Removed IDDOSC
.
• In Table 19,
• Added parameter ΔF125.
• Removed IDDFIRC
• In Table 20,
• Added parameter ΔF125.
• Removed IDDSIRC
• In Table 21, removed ILPO
• Updated section: Flash memory module (FTFC) electrical specifications
• In section: 12-bit ADC operating conditions,
• Updated TBDs for IDDA_ADC and TUE in Table 28
• Updated TBDs for IDDA_ADC and TUE in Table 29
• In section: QuadSPI AC specifications, updated figure 'QuadSPI output
timing (HyperRAM mode) diagram'.
• In section: 12-bit ADC operating conditions, updated Table 27.
• In section: CMP with 8-bit DAC electrical specifications, added note 'For
comparator IN signals adjacent ... '
• In table: Table 32, minor update in footnote 6.
• In table: Table 41, updated specifications for S32K146.
5
06 Dec 2017
• Removed S32K148 from 'Caution'
• Updated figure: S32K1xx product series comparison for
• 'EEPROM emulated by FlexRAM' of S32K148 (Added content to
footnote)
• Added support for LIN protocol version 2.2 A
• In Absolute maximum ratings :
• Added note 'Unless otherwise ... '
• Added parameter 'Added note 'Tramp_MCU
'
• Updated footnote for 'Tramp
'
• In Voltage and current operating requirements :
• Added footnote 'VDD and VDDA must be shorted ... ' against parameter
'VDD– VDDA
'
• Updated footnote 'VDD and VDDA must be shorted ...'
• In Power and ground pins
• Added diagrams for 32-QFN and 48-LQFP and footnote below the
diagrams.
• Updated footnote 'VDD and VDDA must be shorted ...'
• In Power mode transition operating behaviors :
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
78
NXP Semiconductors
Revision History
Table 43. Revision History
Rev. No.
Date
Substantial Changes
• Added footnote 'For S32K11x – FIRC/SOSC/FIRC/LPO; For S32K14x
– FIRC/SOSC/FIRC/LPO/SPLL' to 'VLPS Mode: All clock sources
disabled'
• Updated numbers for:
• VLPR → VLPS
• VLPS → VLPR
• 'RUN → Compute operation'
• RUN → VLPS
• RUN → VLPR
• In Power consumption :
• Updated specs for S32K142, S32K144, and S32K148
• Updated footnote 'Typical current numbers are indicative ...'
• Updated footnote 'The S32K148 data ...'
• Removed footnote 'Above S32K148 data is preliminary targets only'
• Added new table 'Power consumption at 3.3 V'
• In General AC specifications :
• Updated max value and footnote of WFRST
• Updated symbol for not filtered pulse to 'WNFRST', updated min value,
removed max. value, and added footnote
• Fixed naming conventions to align with DS in DC electrical specifications at
3.3 V Range and DC electrical specifications at 5.0 V Range
• Updated specs for AC electrical specifications at 3.3 V range and AC
electrical specifications at 5 V range
• In Device clock specifications :
• Updated fBUS to 48 for 11x
• Added footnote to fBUS for 14x
• In External System Oscillator frequency specifications :
• Added specs for S32K11x
• Updated 'tdc_extal' for S32K14x
• Added footnote 'Frequecies below ... ' to 'fec_extal' and 'tdc_extal
'
• Splitted Flash timing specifications — commands for S32K14x and S32K11x
• Updated Flash timing specifications — commands for S32K14x
• In Reliability specifications :
• Added footnote 'Data retention period ... ' for 'tnvmretp1k' and
'tnvmretee'
• Minor update in footnote for 'nnvmwree16' 'nnvmwree256'
• In QuadSPI AC specifications :
• Updated 'MCR[SCLKCFG[5]]' value to 0
• Updated 'Data Input Setup Time' HSRUN Internal DQS PAD Loopback
value to 1.6
• Updated 'Data Input Setup Time' DDR External DQS min. value to 2
• Updated 'Data Input Hold Time' DDR External DQS min. value to 20
• Upadted figure 'QuadSPI output timing (SDR mode) diagram' and
'QuadSPI input timing (HyperRAM mode) diagram'
• In 12-bit ADC electrical characteristics :
• Added note 'On reduced pin packages where ... '
• Removed max. value of 'IDDA_ADC
• Added note 'Due to triple ... '
'
• In 12-bit ADC operating conditions, removed parameter 'ΔVDDA
'
• In CMP with 8-bit DAC electrical specifications :
• Updated Typ. and Max. values of 'IDDLS
• Upadted Typ. value of 'tDHSB
'
'
• Updated Typ. value of 'VHYST1' , 'VHYST2', and 'VHYST3
• In LPSPI electrical specifications :
'
• Updated 'fperiph' and 'fop', and 'tSPSCK
'
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
79
Revision History
Rev. No.
Table 43. Revision History (continued)
Date
Substantial Changes
• Updated 3.3 V numbers and added footnote against fop, tSU, ans tV in
HSRUN Mode
• Added footnote to 'tWSPSCK
'
• Updated Thermal characteristics for S32K11x
6
31 Jan 2018
• Changed the representation of ARM trademark throughout.
• Removed S32K142 from 'Caution'
• In 'Key features', added the following note under 'Power management',
'Memory and memory interfaces', and 'Reliability, safety and security':
• No write or erase access to ...
• In High-level architecture diagram for the S32K14x family, added the
following footnote:
• No write or erase access to ...
• In High-level architecture diagram for the S32K11x family :
• Minor editorial update: Fixed the placement of SRAM, under 'Flash
memory controller' block
• Updated figure: S32K1xx product series comparison :
• Updated footnote 1, and added against 'HSRUN' in addition to 'HW
security module (CSEc)' and 'EEPROM emulated by FlexRAM'.
• Updated 'System RAM (including FlexRAM and MTB)' row for
S32K144, S32K146, and S32K148.
• Updated channel count for S32K116 in row '12-bit SAR ADC (1 MSPS
each)'.
• Updated Ordering information
• Updated Flash timing specifications — commands for S32K148, S32K142,
S32K146, S32K116, and S32K118.
7
19 April 2018
• Changed Caution to Notes
• Updated the wordings of Notes and removed S32K146
• Added 'Following two are the available ...'
• In 'Key features' :
• Editorial updates
• Updated the note under Power management, Memory and memory
interfaces, and Safety and security.
• Updated FlexIO under Communications interfaces
• Added ENET and SAI under Communications interfaces
• Updated Cryptographic Services Engine (CSEc) under 'Safety and
security'
• In High-level architecture diagram for the S32K14x family :
• Minor editorial updates
• Updated note 3
• In High-level architecture diagram for the S32K11x family :
• Minor editorial updates
• In figure: S32K1xx product series comparison :
• Editorial updates
• Updated Frequency for S32K14x
• Updated footnote 4
• Added footnote 5
• In Ordering information :
• Renamed section, updated the starting paragraph
• Updated the figure
• In Voltage and current operating requirements, updated the note
• In Power consumption :
• Updated specs for S32K146
• Removed section 'Modes configuration', amd moved its content under
the fisrt paragraph.
• In 12-bit ADC operating conditions :
Table continues on the next page...
S32K1xx Data Sheet, Rev. 8, 06/2018
80
NXP Semiconductors
Revision History
Table 43. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Fixed the typo in RSW1
• In LPSPI electrical specifications :
• Updated tLead and tLag
• Added footnote in Figure: LPSPI slave mode timing (CPHA = 0) and
Figure: LPSPI slave mode timing (CPHA = 1)
• In Thermal characteristics :
• Updated the name of table: Thermal characteristics for 32-pin QFN
and 48/64/100/144/176-pin LQFP package
• Deleted specs for RθJC for 32 QFN package
• Added 'RθJCBottom
'
8
18 June 2018
• In attachement 'S32K1xx_Power_Modes _Configuration':
• Updated VLPR peripherals disabled and Peripherals Enabled use case
#1, using 4 Mhz for System clock, 2 Mhz for bus clock, and 1Mhz for
flash.
• Removed S32K116 from Notes
• In figure: S32K1xx product series comparison :
• Added note 'Availability of peripherals depends on the pin
availability ...'
• Updated 'Ambient Operation Temperature' row
• Updated 'System RAM (including FlexRAM and MTB)' row for
S32K144, S32K146, and S32K148
• In Ordering information :
• Updated figure for 'Y: Optional feature'
• Updated footnote 3
• In Power and ground pins :
• In figure 'Power diagram', updtaed VFlash frequency to 3.3 V
• In Power mode transition operating behaviors :
• Updated footnote for 'VLPS Mode: All clock sources disabled'
• In Power consumption :
• Added IDDs for S32K116
• Added VLPR Peripherals enabled use case 2 at 125 °C/Typicals
• Renamed VLPR 'Peripherals enabled' to 'Peripherals enabled use
case 1'
• Added footnote 'Data collected using RAM' to VLPR 'Peripherals
disabled' and VLPR 'Peripherals enabled use case 1'
• Updated VLPS Peripherals enabled at 25 °C/Typicals for S32K142 and
S32K144 to 40 μA and 42 μA respectively
• Added table 'VLPS additional use-case power consumption at typical
conditions'
• In DC electrical specifications at 3.3 V Range :
• Updated naming conventions
• Added specs for GPIO-FAST pad
• In DC electrical specifications at 5.0 V Range :
• Updated naming conventions
• Added specs for GPIO-FAST pad
• In AC electrical specifications at 3.3 V range :
• Updated naming conventions
• Added specs for GPIO-FAST pad
• In AC electrical specifications at 5 V range :
• Updated naming conventions
• Added specs for GPIO-FAST pad
• In External System Oscillator electrical specifications :
• Clarified description of gmXOSC
• Updated VIL max. to 1.15 V
• In Fast internal RC Oscillator (FIRC) electrical specifications :
S32K1xx Data Sheet, Rev. 8, 06/2018
NXP Semiconductors
81
Revision History
Rev. No.
Table 43. Revision History
Date
Substantial Changes
• Updated specs for TJIT Cycle-to-Cycle jitter to 300 ps
• In QuadSPI AC specifications :
• Updated specs for Tiv Data Output In-Valid Time
• In figure 'QuadSPI output timing (SDR mode) diagram', marked Invalid
area
• In CMP with 8-bit DAC electrical specifications :
• Removed '(VAIO)' from decription of VHYST0
• In LPSPI electrical specifications :
• Added note 'Undefined' in figures 'LPSPI slave mode timing (CPHA =
0)' and 'LPSPI slave mode timing (CPHA = 1)'
S32K1xx Data Sheet, Rev. 8, 06/2018
82
NXP Semiconductors
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Document Number S32K1XX
Revision 8, 06/2018
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