935380028528 [NXP]

RISC Microcontroller;


型号：	935380028528
厂家：	NXP
描述：	RISC Microcontroller 微控制器
文件：	总80页 (文件大小：1242K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Document Number S32K1XX

Rev. 6, 01/2018

NXP Semiconductors

Data Sheet: Product Preview

S32K1XX

S32K1xx Data Sheet

Caution

• Memory and memory interfaces

– Up to 2 MB program flash memory with ECC

– 64 KB FlexNVM for data flash memory with ECC

and EEPROM emulation. Note: No write or erase

access to Security (CSEc) or EEPROM is allowed

when device is running at HSRUN mode (112

MHz).

– Up to 256 KB SRAM with ECC

– Up to 4 KB of FlexRAM for use as SRAM or

EEPROM emulation

• S32K146, S32K116, and S32K118 specific

information is preliminary until these devices are

qualified.

Key Features

• Operating characteristics

– Voltage range: 2.7 V to 5.5 V

– Ambient temperature range: -40 °C to 105 °C for

HSRUN, -40 °C to 125 °C for RUN

– Up to 4 KB Code cache to minimize performance

impact of memory access latencies

– QuadSPI with HyperBus™ support

• Arm™ Cortex-M4F/M0+ core, 32-bit CPU

– Supports up to 112 MHz frequency (HSRUN) with

1.25 Dhrystone MIPS per MHz

• Mixed-signal analog

– Arm Core based on the Armv7 Architecture and

Thumb®-2 ISA

– Integrated Digital Signal Processor (DSP)

– Configurable Nested Vectored Interrupt Controller

(NVIC)

– Up to two 12-bit Analog-to-Digital Converter

(ADC) with up to 32 channel analog inputs per

module

– One Analog Comparator (CMP) with internal 8-bit

Digital to Analog Converter (DAC)

– Single Precision Floating Point Unit (FPU)

• Debug functionality

• Clock interfaces

– Serial Wire JTAG Debug Port (SWJ-DP) combines

– Debug Watchpoint and Trace (DWT)

– Instrumentation Trace Macrocell (ITM)

– Test Port Interface Unit (TPIU)

– 4 - 40 MHz fast external oscillator (SOSC)

– 48 MHz Fast Internal RC oscillator (FIRC)

– 8 MHz Slow Internal RC oscillator (SIRC)

– 128 kHz Low Power Oscillator (LPO)

– Up to 112 MHz (HSRUN) System Phased Lock

Loop (SPLL)

– Flash Patch and Breakpoint (FPB) Unit

• Human-machine interface (HMI)

– Up to 50 MHz DC external square wave input clock

– Real Time Counter (RTC)

– Up to 156 GPIO pins with interrupt functionality

– Non-Maskable Interrupt (NMI)

• Power management

• Communications interfaces

– Low-power Arm Cortex-M4F/M0+ core with

excellent energy efficiency

– Up to three Low Power Universal Asynchronous

Receiver/Transmitter (LPUART) modules with

DMA support and low power availability

– Up to three Low Power Serial Peripheral Interface

(LPSPI) modules with DMA support and low power

availability

– Up to two Low Power Inter-Integrated Circuit

(LPI2C) modules with DMA support and low power

availability

– Power Management Controller (PMC) with multiple

power modes: HSRUN, Run, Stop, VLPR, and

VLPS. Note: No write or erase access to Security

(CSEc) or EEPROM is allowed when device is

running at HSRUN mode (112 MHz).

– Supports peripheral specific clock gating. Only

specific peripherals remain working in low power

modes.

– Up to three FlexCAN modules (with optional CAN-

FD support)

– FlexIO module for flexible and high performance

serial interfaces

This document contains information on a product under development. NXP

reserves the right to change or discontinue this product without notice.

Preliminary

• Reliability, safety and security

– HW Security Engine (CSEc). Note: No write or erase access to Security (CSEc) or EEPROM is allowed when device is

running at HSRUN mode (112 MHz).

– Internal watchdog (WDOG)

– External Watchdog monitor (EWM) module

– Error-Correcting Code (ECC) on flash and SRAM memories

– Cyclic Redundancy Check (CRC) module

– 128-bit Unique Identification (ID) number

– System Memory Protection Unit (System MPU)

• Timing and control

– Up eight independent 16-bit FlexTimers (FTM) module, offering up to 64 standard channels (IC/OC/PWM)

– One 16-bit Low Power Timer (LPTMR) with flexible wake up control

– Two Programmable Delay Blocks (PDB) with flexible trigger system

– One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels

– 32-bit Real Time Counter (RTC)

• I/O and package

– 32-pin QFN, 48-pin LQFP, 64-pin LQFP, 100-pin LQFP, MAPBGA-100, 144-pin LQFP, 176-pin LQFP package

options

• 16 channel DMA with up to 63 request sources using DMAMUX

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Table of Contents

Block diagram.................................................................................... 4

6.2.5 SPLL electrical specifications .....................................31

6.3 Memory and memory interfaces................................................31

6.3.1 Flash memory module (FTFC) electrical

Feature comparison............................................................................ 5

Ordering parts.....................................................................................7

3.1 Determining valid orderable parts ............................................ 7

3.2 Ordering information ................................................................8

General............................................................................................... 9

4.1 Absolute maximum ratings........................................................9

4.2 Voltage and current operating requirements..............................10

4.3 Thermal operating characteristics..............................................11

4.4 Power and ground pins.............................................................. 12

4.5 LVR, LVD and POR operating requirements............................14

4.6 Power mode transition operating behaviors.............................. 15

4.7 Power consumption................................................................... 16

4.7.1 Modes configuration.................................................... 20

4.8 ESD handling ratings.................................................................20

4.9 EMC radiated emissions operating behaviors........................... 21

I/O parameters....................................................................................21

5.1 AC electrical characteristics...................................................... 21

5.2 General AC specifications......................................................... 21

5.3 DC electrical specifications at 3.3 V Range.............................. 22

5.4 DC electrical specifications at 5.0 V Range.............................. 23

5.5 AC electrical specifications at 3.3 V range .............................. 24

5.6 AC electrical specifications at 5 V range ................................. 24

5.7 Standard input pin capacitance.................................................. 25

5.8 Device clock specifications....................................................... 25

Peripheral operating requirements and behaviors..............................26

6.1 System modules.........................................................................26

6.2 Clock interface modules............................................................ 26

6.2.1 External System Oscillator electrical specifications....26

6.2.2 External System Oscillator frequency specifications . 28

6.2.3 System Clock Generation (SCG) specifications..........30

specifications................................................................31

6.3.1.1

Flash timing specifications —

commands................................................ 31

Reliability specifications..........................36

6.3.1.2

6.3.2 QuadSPI AC specifications..........................................37

6.4 Analog modules.........................................................................41

6.4.1 ADC electrical specifications...................................... 41

6.4.1.1

6.4.1.2

12-bit ADC operating conditions.............41

12-bit ADC electrical characteristics....... 43

6.4.2 CMP with 8-bit DAC electrical specifications............ 45

6.5 Communication modules...........................................................49

6.5.1 LPUART electrical specifications............................... 49

6.5.2 LPSPI electrical specifications.................................... 49

6.5.3 LPI2C electrical specifications.................................... 55

6.5.4 FlexCAN electical specifications.................................56

6.5.5 SAI electrical specifications........................................ 56

6.5.6 Ethernet AC specifications.......................................... 58

6.5.7 Clockout frequency......................................................61

6.6 Debug modules.......................................................................... 61

6.6.1 SWD electrical specofications .................................... 61

6.6.2 Trace electrical specifications......................................63

6.6.3 JTAG electrical specifications..................................... 64

Thermal attributes.............................................................................. 67

7.1 Description.................................................................................67

7.2 Thermal characteristics..............................................................67

7.3 General notes for specifications at maximum junction

temperature................................................................................ 72

Dimensions.........................................................................................73

8.1 Obtaining package dimensions .................................................73

Pinouts................................................................................................74

9.1 Package pinouts and signal descriptions....................................74

6.2.3.1

Fast internal RC Oscillator (FIRC)

electrical specifications............................ 30

Slow internal RC oscillator (SIRC)

6.2.3.2

electrical specifications ........................... 30

10 Revision History.................................................................................74

6.2.4 Low Power Oscillator (LPO) electrical specifications

......................................................................................31

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Block diagram

1 Block diagram

Following figures show superset high level architecture block diagrams of S32K14x

series and S32K11x series respectively. Other devices within the family have a subset of

the features. See Feature comparison for chip specific values.

Arm Cortex M4F

MCM

Core

Async

Trace

port

TPIU

PPB

NVIC

ITM

AWIC

JTAG &

SWJ-DP

AHB-AP

Serial Wire

FPU

FPB

Clock generation

DSP DWT

DMA

MUX

SOSC

4-40 MHz

FIRC

48 MHz

SIRC

8 MHz

LPO

128 kHz

8-40 MHz

Mux

SPLL

eDMA

TCD

512B

LMEM

Main SRAM

LMEM

controller

Upper region

Lower region

EIM

Code Cache

ENET

Crossbar switch (AXBS-Lite)

System MPU

Mux

QuadSPI

GPIO

Flash memory

controller

Peripheral bus controller

FlexRAM/

SRAM

Low Power

Timer

LPIT

WDOG

LPI2C

ERM

12-bit ADC

FlexIO

Code flash

memory

Data flash

memory

CMP

8-bit DAC

FlexTimer

FlexCAN

LPUART

LPSPI

QSPI

EWM

CRC

CSEc

SAI

RTC

LPIT

TRGMUX

PDB

1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from

accessing restricted memory regions. This system MPU provides memory protection at the

level of the Crossbar Switch. Each Crossbar master (Core, DMA, Ethernet) can be assigned

different access rights to each protected memory region. The Arm M4 core version in this family

does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory

accesses. In this document, the term MPU refers to NXP’s system MPU.

Device architectural IP

on all S32K devices

Key:

Peripherals present

on all S32K devices

2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"

chapter of the S32K14x Series Reference Manual.

Peripherals present

on selected S32K devices

(see the "Feature Comparison"

section in the RM)

3: No write or erase access to Flash module, including Security (CSEc) and EEPROM commands, are allowed when

device is running at HSRUN mode (112 MHz).

Figure 1. High-level architecture diagram for the S32K14x family

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Feature comparison

IO PORT

Arm Cortex M0+

IO PORT

Clock generation

FIRC

SOSC

4-40 MHz

SIRC

8 MHz

LPO

128 kHz

SW-DP

Serial Wire

NVIC

48 MHz

AHB-AP

AWIC

DMA

MUX

PPB

BPU

MTB+DWT

eDMA

Crossbar switch (AXBS-Lite)

System MPU

EIM

Flash memory

controller

SRAM

FlexRAM/

SRAM

Peripheral bus controller

Code flash

memory

Data flash

memory

Low Power

Timer

LPIT

WDOG

LPI2C

ERM

12-bit ADC

FlexIO

CSEc

CMP

8-bit DAC

FlexTimer

FlexCAN

LPUART

CMU

GPIO

RTC

LPIT

TRGMUX

CRC

PDB

LPSPI

1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from

accessing restricted memory regions. This system MPU provides memory protection at the

level of the Crossbar Switch. Crossbar master (Core, DMA) can be assigned

different access rights to each protected memory region. The Arm M0+ core version in this family

does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory

accesses. In this document, the term MPU refers to NXP’s system MPU.

Device architectural IP

on all S32K devices

Peripherals present

on all S32K devices

Key:

Peripherals present

on selected S32K devices

(see the "Feature Comparison"

section in the RM)

2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"

chapter of the S32K1xx Series Reference Manual.

Figure 2. High-level architecture diagram for the S32K11x family

2 Feature comparison

The following figure summarizes the memory and package options for the S32K product

series and demonstrates where this device fits within the overall series. All devices which

share a common package are pin-to-pin compatible.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Feature comparison

S32K11x

S32K14x

Parameter

K116

K118

K142

K144

K146

K148

Core

Arm Cortex™-M0+

48 MHz

Arm Cortex™-M4F

Frequency

IEEE-754 FPU

up to 112 MHz (HSRUN)

HW security module (CSEc)

CRC module

ISO 26262

capable up to ASIL-B

Peripheral speed

Crossbar

up to 48 MHz

up to 112 MHz (HSRUN)

DMA

EWM

Memory protection unit

FIRC CMU

Watchdog

Low power modes

HSRUN mode¹

Number of I/Os

Single supply voltage

up to 43

up to 58

up to 89

up to 128

up to 156

2.7 - 5.5 V

Operating temperature (T ) Temperature ambient

-40 to +85ºC / +105ºC / +125ºC

Flash

128 KB

256 KB

32 KB

512 KB

1 MB

2 MB

Error correction code (ECC)

System RAM (including FlexRAM and MTB)

FlexRAM (also available as system RAM)

Cache

17 KB

25 KB

48/64 KB

96/128 KB

192/256 KB

2 KB

4 KB

EEPROM emulated by FlexRAM

2 KB (up to 32 KB D-Flash)

4 KB (up to 64 KB D-Flash)

See footnote 3

QuadSPI incl.

HyperBus™

External memory interface

Low power interrupt timer

2x (16)

FlexTimer (16-bit counter) 8 channels

Low power timer (LPTMR)

4x (32)

6x (48)

8x (64)

Real time counter (RTC)

Programmable delay block (PDB)

Trigger mux (TRGMUX)

1x (43)

1x (13)

1x (45)

1x (16)

1x (64)

1x (73)

2x (24)

1x (81)

2x (32)

12-bit SAR ADC (1 MSPS each)

Comparator with 8-bit DAC

2x (16)

100 Mbit IEEE-1588 ethernet MAC

Serial audio interface (AC97, TDM, I2S)

Low power UART/LIN

(Supports LIN protocol versions 1.3, 2.0, 2.1, 2.2A, and SAE J2602)

Low power SPI

Low power I2C

FlexCAN

(CAN-FD ISO/CD 11898-1)

(1x with FD)

(2x with FD)

(3x with FD)

FlexIO (8 pins configurable as UART, SPI, I2C, I2S)

Debug & trace

SWD, JTAG

(ITM, SWV,

SWO), ETM

SWD, JTAG (ITM, SWV, SWO)

SWD, MTB (1 KB), JTAG

Ecosystem

(IDE, compiler, debugger)

NXP S32 Design Studio (GCC) + SDK,

IAR, GHS, COSMIC, Lauterbach, iSystems

NXP S32 Design Studio (GCC) + SDK,

IAR, GHS, COSMIC, Lauterbach, iSystems

LQFP-64

MAPBGA-100

LQFP-100

LQFP-64

LQFP-100

MAPBGA-100

LQFP-144

LQFP-176

QFN-32

LQFP-48

LQFP-64

LQFP-100

Packages

LQFP-144

LEGEND:

Not implemented

Available on the device

1 No write or erase access to Flash module, including Security (CSEc) and EEPROM commands, are allowed when

device is running at HSRUN mode (112MHz) or VLPR mode.

2 Available when EEEPROM, CSEc and Data Flash are not used. Else only up to 1,984 KB is available for Program Flash.

3 4 KB (up to 512 KB D-Flash as a part of 2M Flash). Up to 64 KB of flash is used as EEPROM backup and the remaining 448 KB

of the last 512 KB block can be used as Data flash or Program flash. See chapter FTFC for details.

4 Only for BSR

Figure 3. S32K1xx product series comparison

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Ordering parts

3 Ordering parts

3.1 Determining valid orderable parts

To determine the orderable part numbers for this device, go to www.nxp.com and

perform a part number search. Additionally see the attachment

S32K_Part_Numbers.xlsx .

NOTE

Not all part number combinations exist

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Ordering parts

3.2 Ordering information

F/P S32 K 1 0 0 X Y F0 M LC R

Product status

Product type/brand

Product line

Series/Family

(including generation)

Core platform/

Performance

Memory size

Ordering option 1: Letter

Ordering option 2: Letter

Fab and Mask

rev. letter

Temperature

Package

Tape and Reel

Product status

P: Prototype

F: Qualified ordering P/N

Temperature

Ordering option

X: Speed

B: 48 MHz without DMA (only for S32K11x)

L: 48 MHz with DMA (only for S32K11x)

M: 64 MHz

C: -40C to 85C

V: -40C to 105C

M: -40C to 125C

W: -40C to 150C

Product type/brand

S32: Automotive 32-bit MCU

H: 80 MHz

U¹: 112 MHz (Not valid with M temperature)

Package

Product line

K: Arm Cortex MCUs

LQFP

-EP

Pins

LQFP

QFN

BGA

Y: Optional feature

N: No/None

R: Max. RAM

F: CAN-FD and FlexIO including max. RAM

S¹: Security including max. RAM

A¹: CAN-FD, FlexIO, and Security including max. RAM

E: Ethernet and audio including max. RAM

J¹: CAN FD, FlexIO, Security, Ethernet

and audio including max. RAM

Series/Family

1: 1st product series

2: 2nd product series

100

144

Core platform/Performance

1: Arm Cortex M0+

176

4: Arm Cortex M4F

Tape and Reel

T: Trays and Tubes

R: Tape and Reel

Fab and Mask rev. letter

Fx: ATMC

Tx: GF

Memory size

XX: Flex #

M0+

M4F

32K 64K

128K 256K

x0: 1st fab revision

x1: 2nd fab revision

256K 512K 1M

1. No write or erase access to security and EEPROM allowed when device is running at 112 MHz

Figure 4. Ordering information

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

General

4 General

4.1 Absolute maximum ratings

NOTE

• Functional operating conditions appear in the DC electrical

characteristics. Absolute maximum ratings are stress

ratings only, and functional operation at the maximum

values is not guaranteed. See footnotes in the following

table for specific conditions.

• Stress beyond the listed maximum values may affect device

reliability or cause permanent damage to the device.

• All the limits defined in the datasheet specification must be

honored together and any violation to any one or more will

not guarantee desired operation.

• Unless otherwise specified, all maximum and minimum

values in the datasheet are across process, voltage, and

temperature.

Table 1. Absolute maximum ratings

Symbol

Parameter

Conditions¹

Min

-0.3

-3

Max

5.8 ³

Unit

V_DD

2.7 V - 5. 5V input supply voltage

3.3 V / 5.0 V ADC high reference voltage

—

V_REFH

I_{INJPAD_DC_ABS}

Continuous DC input current (positive /

negative) that can be injected into an I/O

V_{IN_DC}

Continuous DC Voltage on any I/O pin

with respect to V_SS

—

-0.8

—

5.8⁵

I_{INJSUM_DC_ABS}

Sum of absolute value of injected currents

on all the pins (Continuous DC limit)

T_ramp

ECU supply ramp rate

MCU supply ramp rate

Ambient temperature

Storage temperature

—

0.5 V/min

-40

500 V/ms

100 V/ms

125

—

°C

T_{ramp_MCU}

T_A

T_STG

-55

165

6.8 ⁹

V_{IN_TRANSIENT}

Transient overshoot voltage allowed on

I/O pin beyond V_{IN_DC limit}

—

1. All voltages are referred to V_SSunless otherwise specified.

2. As V_DDvaries between the minimum value and the absolute maximum value the analog characteristics of the I/O and the

ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.

3. 60 s lifetime – No restrictions i.e. The part can switch.

10 hours lifetime – Device in reset i.e. The part cannot switch.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

General

4. When input pad voltage levels are close to V_DDor V_SS, practically no current injection is possible.

5. While respecting the maximum current injection limit

6. This is the Electronic Control Unit (ECU) supply ramp rate and not directly the MCU ramp rate. Limit applies to both

maximum absolute maximum ramp rate and typical operating conditions.

7. This is the MCU supply ramp rate and the ramp rate assumes that the S32K1xx HW design guidelines in AN5426 are

followed. Limit applies to both maximum absolute maximum ramp rate and typical operating conditions.

8. T_J(Junction temperature)=135 °C. Assumes T_A=125 °C for RUN mode

T_J(Junction temperature)=125 °C. Assumes TA=105 °C for HSRUN mode

• Assumes maximum θJA for 2s2p board. See Thermal characteristics

9. 60 seconds lifetime; device in reset (no outputs enabled/toggling)

4.2 Voltage and current operating requirements

NOTE

Full functionality/specifications cannot be guaranteed when

voltage drops below 2.7 V.

Table 2. Voltage and current operating requirements 1

Symbol

Description

Min.

2.7³

Max.

5.5

Unit

Notes

V_DD

Supply voltage

V_{DD_OFF}

Voltage allowed to be developed on V_DD

pin when it is not powered from any

external power supply source.

0.1

V_DDA

V_DD– V_DDA

V_REFH

Analog supply voltage

2.7

– 0.1

2.7

5.5

0.1

V_DD-to-V_DDAdifferential voltage

ADC reference voltage high

ADC reference voltage low

Open drain pullup voltage level

V_DDA+ 0.1

0.1

V_REFL

-0.1

V_DD

-3

V_ODPU

V_DD

I_{INJPAD_DC_OP}

Continuous DC input current (positive /

negative) that can be injected into an I/O

I_{INJSUM_DC_OP}

Continuous total DC input current that can

be injected across all I/O pins such that

there's no degradation in accuracy of

analog modules: ADC and ACMP (See

section Analog Modules)

—

1. Typical conditions assumes V_DD= V_DDA= V_REFH= 5 V, temperature = 25 °C and typical silicon process unless otherwise

stated.

2. As V_DDvaries between the minimum value and the absolute maximum value the analog characteristics of the I/O and the

ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.

3. S32K148 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged S32K148 is guaranteed to

operate from 2.97 V. All other S32K family devices operate from 2.7 V in all modes.

4. V_DDand V_DDAmust be shorted to a common source on PCB. The differential voltage between V_DDand V_DDAis for RF-AC

only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for

reference supply design for SAR ADC.

5. V_REFHshould always be equal to or less than V_DDA+ 0.1 V and V_DD+ 0.1 V

6. Open drain outputs must be pulled to V_DD

7. When input pad voltage levels are close to V_DDor V_SS, practically no current injection is possible.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

General

4.3 Thermal operating characteristics

Table 3. Thermal operating characteristics for 64 LQFP, 100 LQFP, and 100 MAP-BGA

packages.

Symbol

Parameter

Value

Typ.

—

Unit

Min.

−40

Max.

85¹

T_{A C-Grade Part}

T_{J C-Grade Part}

T_{A V-Grade Part}

T_{J V-Grade Part}

T_{A M-Grade Part}

T_{J M-Grade Part}

Ambient temperature under bias

Junction temperature under bias

Ambient temperature under bias

Junction temperature under bias

Ambient temperature under bias

Junction temperature under bias

℃

—

105¹

125¹

125²

135²

—

1. Values mentioned are measured at ≤ 112 MHz in HSRUN mode.

2. Values mentioned are measured at ≤ 80 MHz in RUN mode.

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

General

4.4 Power and ground pins

V_DD

V_SS

32 QFN

Package

V_DD

V_SS

V_REFH/V_DDA

VDD

48 LQFP

Package

REFH DDA

V_REFL/V_SSA/V_SS

DEC

V_DD

V_DDA

V_DD

V_SS

V_DD

V_SS

V_DDA

64 LQFP

Package

100 LQFP

Package

V_REFH

V_REFL

V_REFH

V_REFL/V_SSA/V_SS

V_SSA/V_SS

DEC

V_DD

V_SS

V_DD

V_SS

V_DD

V_DDA

V_REFH

V_DDA

V_REFH

V_SS

V_DD

V_SS

V_DD

V_SS

144 LQFP

Package

176 LQFP

Package

V_REFL

V_SSA/V_SS

V_REFL

V_SSA/V_SS

V_DD

V_SS

DEC

NOTE: V_DDand V_DDAmust be shorted to a common source on PCB

Figure 5. Pinout decoupling

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

General

Table 4. Supplies decoupling capacitors 1, 2

Symbol

Description

Min. ³

Typ.

100

Max.

—

Unit

, 4

C_REF

ADC reference high decoupling capacitance

Recommended decoupling capacitance

C_DEC⁵, ⁶, ⁷

—

1. V_DDand V_DDAmust be shorted to a common source on PCB. The differential voltage between V_DDand V_DDAis for RF-AC

only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for

reference supply design for SAR ADC. All V_SSpins should be connected to common ground at the PCB level.

2. All decoupling capacitors must be low ESR ceramic capacitors (for example X7R type).

3. Minimum recommendation is after considering component aging and tolerance.

4. For improved performance, it is recommended to use 10 μF, 0.1 μF and 1 nF capacitors in parallel.

5. All decoupling capacitors should be placed as close as possible to the corresponding supply and ground pins.

6. Contact your local Field Applications Engineer for details on best analog routing practices.

7. The filtering used for decoupling the device supplies must comply with the following best practices rules:

• The protection/decoupling capacitors must be on the path of the trace connected to that component.

• No trace exceeding 1 mm from the protection to the trace or to the ground.

• The protection/decoupling capacitors must be as close as possible to the input pin of the device (maximum 2 mm).

• The ground of the protection is connected as short as possible to the ground plane under the integrated circuit.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

General

OSC

= 3.3 V nominal

FIRC

SIRC

SPLL

SOSC

ADC

CMP

= 1.2 V/1.4 V nominal

CORE

Flash

= 3.6 V nominal

PMC

Pads

System RAM

TCD RAM

I/D Cache

EEE RAM

Flash

LV SOG

GPIO

*Note: VSSA and VSS are shorted at package level

Figure 6. Power diagram

4.5 LVR, LVD and POR operating requirements

Table 5. V_DDsupply LVR, LVD and POR operating requirements

Symbol

V_POR

Description

Min.

1.1

Typ.

1.6

Max.

2.0

Unit

Notes

Rising and falling V_DDPOR detect voltage

V_LVR

LVR falling threshold (RUN, HSRUN, and

STOP modes)

2.50

2.58

2.7

LVR hysteresis

—

V_{LVR_HYST}

V_{LVR_LP}

V_LVD

LVR falling threshold (VLPS/VLPR modes)

Falling low-voltage detect threshold

LVD hysteresis

1.97

2.8

—

2.22

2.875

2.44

—

V_{LVD_HYST}

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

General

Table 5. V_DDsupply LVR, LVD and POR operating requirements (continued)

Symbol

V_LVW

Description

Min.

4.19

—

Typ.

4.305

Max.

4.5

Unit

Notes

Falling low-voltage warning threshold

LVW hysteresis

V_{LVW_HYST}

V_BG

—

Bandgap voltage reference

0.97

1.00

1.03

1. Rising threshold is the sum of falling threshold and hysteresis voltage.

4.6 Power mode transition operating behaviors

All specifications in the following table assume this clock configuration:

• RUN Mode:

• Clock source: FIRC

• SYS_CLK/CORE_CLK = 48 MHz

• BUS_CLK = 48 MHz

• FLASH_CLK = 24 MHz

• HSRUN Mode:

• Clock source: SPLL

• SYS_CLK/CORE_CLK = 112 MHz

• BUS_CLK = 56 MHz

• FLASH_CLK = 28 MHz

• VLPR Mode:

• Clock source: SIRC

• SYS_CLK/CORE_CLK = 4 MHz

• BUS_CLK = 4 MHz

• FLASH_CLK = 1 MHz

• STOP1/STOP2 Mode:

• Clock source: FIRC

• SYS_CLK/CORE_CLK = 48 MHz

• BUS_CLK = 48 MHz

• FLASH_CLK = 24 MHz

• VLPS Mode: All clock sources disabled ¹

Table 6. Power mode transition operating behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

t_POR

After a POR event, amount of time from the point V_DD

reaches 2.7 V to execution of the first instruction

across the operating temperature range of the chip.

—

325

—

μs

Table continues on the next page...

•

For S32K11x – FIRC/SOSC/FIRC/LPO

For S32K14x – FIRC/SOSC/FIRC/LPO/SPLL

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

General

Table 6. Power mode transition operating behaviors (continued)

Symbol

Description

Min.

Typ.

—

Max.

Unit

μs

VLPS → RUN

STOP1 → RUN

0.07

0.075

—

0.08

STOP2 → RUN

VLPR → RUN

VLPR → VLPS

5.1

18.8

0.72

0.3

0.35

0.2

0.3

3.5

105

5.7

6.5

VLPS → VLPR

27.75

0.77

0.35

0.4

RUN → Compute operation

HSRUN → Compute operation

RUN → STOP1

0.75

0.31

0.38

0.23

0.35

3.8

RUN → STOP2

0.25

0.4

RUN → VLPS

RUN → VLPR

VLPS → Asynchronous DMA Wakeup

STOP1 → Asynchronous DMA Wakeup

STOP2 → Asynchronous DMA Wakeup

Pin reset → Code execution

110

1.1

125

1.3

1.1

1.3

—

214

—

NOTE

HSRUN should only be used when frequencies in excess of 80

MHz are required. When using 80 MHz and below, RUN mode

is the recommended operating mode.

4.7 Power consumption

The following table shows the power consumption targets for the device in various mode

of operations.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Table 7. Power consumption (Typicals unless stated otherwise) 1

STOP1

(mA)

STOP2

(mA)

RUN@48

MHz (mA)

RUN@64 MHz RUN@80 MHz HSRUN@112

VLPS (μA)^{2, 3}

VLPR (mA)

(mA)

MHz (mA) ⁴

S32K116

S32K118

S32K142

Typ

Max

1.9

2.5

TBD

105

TBD

125

Typ

Max

1.9

2.5

TBD

105

TBD

125

Typ

Max

Typ

Max

128

335

240

740

1637

137

360

257

791

1694

1.17

1.48

1.87

1.58

2.32

3.1

1.21

1.51

1.89

1.61

2.34

3.21

6.4

7.4

17.3

17.6

24.6

24.9

28.2

25.7

30.2

32.9

24.5

31.3

28.8

29.1

37.5

40.5

41.1

52.2

52.5

55.6

53.1

57.4

360

364

400

373

423

450

31.6

33.5

31.9

35.3

38.8

37.7

8.6

7.6

9.9

12.7

9.4

8.3

10.9

13.7

26.9

25.5

27.8

30.7

105

18.3

23.1

29.8

33.8

41.5

44.9

40.7

43.8

125

S32K144

Typ

Max

29.8

150

359

39.1

159

384

1.48

1.72

2.60

1.50

1.85

2.65

7.7

8.1

9.9

19.7

20.4

23.2

26.9

27.1

29.6

25.1

26.1

29.3

33.3

33.5

36.2

30.2

30.5

34.8

39.6

43.3

43.9

46.3

55.6

56.1

59.7

378

381

435

7.2

9.2

42.1

Table continues on the next page...

Table 7. Power consumption (Typicals unless stated otherwise) 1 (continued)

STOP1

(mA)

STOP2

(mA)

RUN@48

MHz (mA)

RUN@64 MHz RUN@80 MHz HSRUN@112

(mA) (mA)

MHz (mA) ⁴

VLPS (μA)^{2, 3}

VLPR (mA)

105

125

Typ

Max

256

850

273

900

1.80

2.65

3.18

2.10

2.70

3.25

7.8

8.5

20.6

27.4

30.6

33.6

26.6

30.3

33.8

31.2

35.6

38.7

40.5

44.8

47.9

57.1

61.3

390

445

484

10.3

12.9

11.1

13.8

23.9

26.9

37.3

40.3

43.5

46.8

1960

1998

S32K146

Typ

Max

TBD

110

TBD

105

TBD

125

S32K148⁷

Typ

Max

Typ

Max

2.17

2.30

3.48

2.49

4.40

6.00

2.20

2.35

3.55

2.54

4.47

6.08

8.5

9.6

27.6

29.1

34.8

29.8

38.4

44.3

34.9

37.0

43.6

37.8

46.8

52.5

35.5

36.8

41.9

37.6

44.9

50.9

45.3

46.6

53.9

47.5

55.3

61.3

42.1

43.4

48.7

45.2

51.6

57.5

57.7

59.9

65.1

61.5

66.8

71.6

60.3

62.9

70.4

63.8

73.6

83.3

88.7

96.1

89.1

97.4

526

543

609

565

645

719

336

357

10.1

14.5

10.9

18.0

23.4

11.1

15.6

11.9

19.0

24.5

1660

560

1736

577

105

125

2945

3990

2970

4166

1. Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user configuration. Typical conditions assumes

V_DD= V_DDA= V_REFH= 5 V, temperature = 25 °C and typical silicon process unless otherwise stated. All output pins are floating and On-chip pulldown is enabled for

all unused input pins.

2. This is an average based on the use case described in the Comparator section, whereby the analog sampling is taking place periodically, with a mechanism to only

enable the DAC as required. The numbers quoted assumes that only a single ANLCMP is active and the others are disabled

3. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.

4. HSRUN mode must not be used at 125°C. Max ambient temperature for HSRUN mode is 105°C.

5. Values mentioned are measured at RUN@80 MHz with peripherals disabled.

6. With PMC_REGSC[CLKBIASDIS] set to 1. See Reference Manual for details.

7. The S32K148 data points assume that ENET/QuadSPI/SAI etc. are inactive.

General

The following table shows the power consumption targets for S32K148 in various mode

of operations measure at 3.3 V.

Table 8. Power consumption at 3.3 V

Chip/Device

Ambient

Temperature

(°C)

RUN@80 MHz (mA)

HSRUN@112 MHz (mA)¹

Peripherals

enabled +

QSPI

Peripherals

enabled +

Peripherals

enabled +

QSPI

Peripherals

enabled +

ENET + SAI

S32K148

Typ

Max

Typ

Max

67.3

67.4

82.5

68.0

80.3

83.5

79.1

79.2

88.2

79.8

89.1

94.7

89.8

95.6

105.5

105.9

117.4

106.7

119.0

109.7

96.6

105

125

109.0

1. HSRUN mode must not be used at 125°C. Max ambient temperature for HSRUN mode is 105°C.

4.7.1 Modes configuration

Attached S32K1xx_Power_Modes _Configuration.xlsx details the modes used in

gathering the power consumption data stated in the above table Table 7. For full

functionality refer to table: Module operation in available low power modes of the

Reference Manual.

4.8 ESD handling ratings

Symbol

V_HBM

Description

Min.

Max.

Unit

Notes

Electrostatic discharge voltage, human body model

Electrostatic discharge voltage, charged-device model

All pins except the corner pins

− 4000

4000

V_CDM

− 500

− 750

− 100

500

750

100

Corner pins only

I_LAT

Latch-up current at ambient temperature of 125 °C

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

I/O parameters

4.9 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request.

5 I/O parameters

5.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

Figure 7. Input signal measurement reference

5.2 General AC specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

and timers.

Table 9. General switching specifications

Symbol

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5

—

Bus clock

cycles

1, 2

GPIO pin interrupt pulse width (digital glitch filter

—

disabled, passive filter disabled) — Asynchronous path

WFRST

RESET input filtered pulse

—

WNFRST RESET input not filtered pulse

Maximum of

(100 ns, bus

clock period)

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In Stop and VLPS modes, the synchronizer is bypassed so shorter pulses can be recognized in

that case.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

I/O parameters

2. The greater of synchronous and asynchronous timing must be met.

3. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized.

4. Maximum length of RESET pulse which will be filtered by internal filter.

5. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter. This number depends on bus clock

period also. For example, in VLPR mode bus clock is 4 MHz, which make clock period of 250 ns. In this case, minimum

pulse width which will cause reset is 250 ns. For faster bus clock frequencies which have clock period less than 100 ns,

the minimum pulse width not filtered will be 100 ns.

5.3 DC electrical specifications at 3.3 V Range

Table 10. DC electrical specifications at 3.3 V Range

Symbol

Parameter

Value

Typ.

3.3

—

Unit

Notes

Min.

2.7

Max.

V_DD

V_ih

I/O Supply Voltage

V_DD+ 0.3

0.3 × V_DD

—

Input Buffer High Voltage

Input Buffer Low Voltage

Input Buffer Hysteresis

0.7 × V_DD

V_SS− 0.3

0.06 × V_DD

3.5

V_il

—

V_hys

—

Ioh_Standard I/O current source capability measured

when pad V_oh= (V_DD− 0.8 V)

—

Iol_Standard I/O current sink capability measured when

pad V_ol= 0.8 V

—

Ioh_Strong I/O current source capability measured

when pad V_oh= (V_DD− 0.8 V)

—

Iol_Strong

I/O current sink capability measured when

pad V_ol= 0.8 V

—

IOHT

IIN

Output high current total for all ports

100

Input leakage current (per pin) for full temperature range at V_DD= 3.3 V

All pins other than high drive port pins

High drive port pins ⁷

0.005

0.010

0.5

μA

kΩ

R_PU

R_PD

Internal pullup resistors

Internal pulldown resistors

1. S32K148 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged S32K148 is guaranteed to

operate from 2.97 V. All other S32K family devices operate from 2.7 V in all modes.

2. For reset pads, same V_ihlevels are applicable

3. For reset pads, same V_illevels are applicable

4. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard

value given above.

5. The value given is measured at high drive strength mode. For value at low drive strength mode see the Iol_Standard value

given above.

6. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All

other GPIOs are normal drive only. For details refer to S32K144_IO_Signal_Description_Input_Multiplexing.xlsx attached

with the Reference Manual.

7. When using ENET and SAI on S32K148, the overall device limits associated with high drive pin configurations must be

respected i.e. On 144-pin LQFP the general purpose pins: PTA10, PTD0, and PTE4 must be set to low drive.

8. Measured at input V = V_SS

9. Measured at input V = V_DD

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

I/O parameters

5.4 DC electrical specifications at 5.0 V Range

Table 11. DC electrical specifications at 5.0 V Range

Symbol

Parameter

Value

Typ.

Unit

Notes

Min.

Max.

5.5

V_DD

V_ih

I/O Supply Voltage

—

Input Buffer High Voltage

Input Buffer Low Voltage

Input Buffer Hysteresis

0.65 x V_DD

V_SS− 0.3

0.06 x V_DD

V_DD+ 0.3

0.35 x V_DD

—

V_il

V_hys

Ioh_Standard I/O current source capability

—

measured when pad V_oh= (V_DD- 0.8

Iol_Standard I/O current sink capability measured

when pad V_ol= 0.8 V

—

Ioh_Strong I/O current source capability

3, 4

4, 5

measured when pad V_oh= V_DD- 0.8

Iol_Strong I/O current sink capability measured

when pad V_ol= 0.8 V

—

IOHT

IIN

Output high current total for all ports

100

Input leakage current (per pin) for full temperature range at V_DD= 5.5 V

All pins other than high drive port

pins

0.005

0.5

μA

High drive port pins

0.010

0.5

μA

kΩ

R_PU

R_PD

Internal pullup resistors

Internal pulldown resistors

1. For reset pads, same V_ihlevels are applicable

2. For reset pads, same V_illevels are applicable

3. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard

value given above.

4. The strong pad I/O pin is capable of switching a 50 pF load at up to 40 MHz.

5. The value given is measured at high drive strength mode. For value at low drive strength mode see the Iol_Standard value

given above.

6. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All

other GPIOs are normal drive only. For details refer to SK3K144_IO_Signal_Description_Input_Multiplexing.xlsx attached

with the Reference Manual.

7. Measured at input V = V_SS

8. Measured at input V = V_DD

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

I/O parameters

5.5 AC electrical specifications at 3.3 V range

Table 12. AC electrical specifications at 3.3 V Range

Symbol

DSE

Rise time (nS) ¹

Fall time (nS) ¹

Capacitance (pF) ²

Min.

Max.

14.5

23.7

80.0

14.5

23.7

80.0

5.8

Min.

Max.

15.7

26.2

88.4

15.7

26.2

88.4

6.1

Standard

3.2

5.7

3.4

6.0

20.0

3.2

20.8

3.4

200

Strong

5.7

6.0

20.0

1.5

20.8

1.7

200

2.4

8.0

2.6

8.3

6.3

22.0

6.0

23.8

200

1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.

2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be

different, for example for ENET, QSPI etc. . For protocol specific AC specifications, see respective sections.

5.6 AC electrical specifications at 5 V range

Table 13. AC electrical specifications at 5 V Range

Symbol

DSE

Rise time (nS)¹

Fall time (nS) ¹

Capacitance (pF) ²

Min.

Max .

9.4

Min.

Max.

10.7

17.4

59.7

10.7

17.4

59.7

5.0

Standard

2.8

5.0

2.9

5.1

15.7

54.8

9.4

17.3

2.8

17.6

2.9

200

Strong

5.0

15.7

54.8

4.6

5.1

17.3

1.1

17.6

1.1

200

2.0

5.7

2.0

5.8

5.4

16.0

5.0

16.0

200

1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.

2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be

different, for example for ENET, QSPI etc. . For protocol specific AC specifications, see respective sections.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

I/O parameters

5.7 Standard input pin capacitance

Table 14. Standard input pin capacitance

Symbol

Description

Min.

Max.

Unit

C_{IN_D}

Input capacitance: digital pins

—

NOTE

Please refer to External System Oscillator electrical

specifications for EXTAL/XTAL pins.

5.8 Device clock specifications

Table 15. Device clock specifications 1

Symbol

Description

Min.

Max.

Unit

High Speed run mode²

Normal run mode (S32K11x series)

Normal run mode (S32K14x series) ³

VLPR mode⁵

f_SYS

f_BUS

System and core clock

Bus clock

—

112

MHz

f_FLASH

Flash clock

f_SYS

f_BUS

System and core clock

Bus clock

—

MHz

f_FLASH

Flash clock

f_SYS

f_BUS

System and core clock

Bus clock

—

40⁴

MHz

f_FLASH

Flash clock

26.67

f_SYS

f_BUS

f_FLASH

f_ERCLK

System and core clock

Bus clock

—

MHz

Flash clock

External reference clock

1. Refer to the section Feature comparison for the availability of modes and other specifications.

2. Only available on some devices. See section Feature comparison.

3. With SPLL as system clock source.

4. 48 MHz when f_SYSis 48 MHz

5. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any

other module.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Peripheral operating requirements and behaviors

6 Peripheral operating requirements and behaviors

6.1 System modules

There are no electrical specifications necessary for the device's system modules.

6.2 Clock interface modules

6.2.1 External System Oscillator electrical specifications

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Clock interface modules

Single input comparator

(EXTAL WAVE)

ref_clk

Mux

Differential input comparator

(HG/LP mode)

Peak detector

LP mode

Driver

(HG/LP mode)

Pull down resistor (OFF)

ESD PAD

280 ohms

ESD PAD

40 ohms

XTAL pin

EXTAL pin

Series resistor for current

limitation

1M ohms Feedback Resistor

Crystal or resonator

Figure 8. Oscillator connections scheme

Table 16. External System Oscillator electrical specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

g_mXOSCCrystal oscillator transconductance

4-8 MHz

2.2

—

13.7

mA/V

8-40 MHz

V_IL

V_IH

Input low voltage — EXTAL pin in external clock mode

V_SS

0.35 * V_DD

V_DD

Input high voltage — EXTAL pin in external clock

mode

0.7 * V_DD

C₁

C₂

R_F

EXTAL load capacitance

XTAL load capacitance

Feedback resistor

—

Low-gain mode (HGO=0)

—

MΩ

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Clock interface modules

Table 16. External System Oscillator electrical specifications

(continued)

Symbol Description

High-gain mode (HGO=1)

Series resistor

Min.

Typ.

Max.

Unit

Notes

—

MΩ

R_S

Low-gain mode (HGO=0)

—

kΩ

High-gain mode (HGO=1)

V_pp

Peak-to-peak amplitude of oscillation (oscillator mode)

Low-gain mode (HGO=0)

—

1.0

3.3

—

High-gain mode (HGO=1)

1. Crystal oscillator circuit provides stable oscillations when g_mXOSC> 5 * gm_crit. The gm_crit is defined as:

gm_crit = 4 * ESR * (2πF)²* (C₀+ C_L)²

where:

• g_mXOSCis the transconductance of the internal oscillator circuit

• ESR is the equivalent series resistance of the external crystal

• F is the external crystal oscillation frequency

• C₀is the shunt capacitance of the external crystal

• C_Lis the external crystal total load capacitance. C_L= C_s+ [C₁*C₂/(C₁+C₂)]

• C_sis stray or parasitic capacitance on the pin due to any PCB traces

• C₁, C₂external load capacitances on EXTAL and XTAL pins

See manufacture datasheet for external crystal component values

• When low-gain is selected, internal R_Fwill be selected and external R_Fshould not be attached.

• When high-gain is selected, external R_F(1 M Ohm) needs to be connected for proper operation of the crystal. For

external resistor, up to 5% tolerance is allowed.

3. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any

other devices.

6.2.2 External System Oscillator frequency specifications

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Table 17. External System Oscillator frequency specifications

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

S32K14x

S32K11x

S32K14x

S32K11x

S32K14x

S32K11x

f_{osc_hi}

f_{ec_extal}

t_{dc_extal}

t_cst

Oscillator crystal or resonator

frequency

—

MHz

Input clock frequency (external clock

mode)

—

Input clock duty cycle (external clock

mode)

Crystal Start-up Time

8 MHz low-gain mode (HGO=0)

8 MHz high-gain mode (HGO=1)

40 MHz low-gain mode (HGO=0)

40 MHz high-gain mode (HGO=1)

—

1.5

2.5

—

1. Frequencies below 40 MHz can be used for degraded duty cycle upto 40-60%

2. Proper PC board layout procedures must be followed to achieve specifications.

System Clock Generation (SCG) specifications

6.2.3 System Clock Generation (SCG) specifications

6.2.3.1 Fast internal RC Oscillator (FIRC) electrical specifications

Table 18. Fast internal RC Oscillator electrical specifications

Symbol

Parameter¹

Value

Typ.

Unit

Min.

Max.

F_FIRC

FIRC target frequency

—

MHz

ΔF

Frequency deviation across process, voltage, and

temperature < 105°C

—

0.5

%F_FIRC

ΔF125

Frequency deviation across process, voltage, and

temperature < 125°C

1.1

%F_FIRC

T_Startup

Startup time

3.4

250

0.04

µs²

, 3

T_JIT

Cycle-to-Cycle jitter

Long term jitter over 1000 cycles

—

500

0.1

T_JIT

%F_FIRC

1. With FIRC regulator enable

2. Startup time is defined as the time between clock enablement and clock availability for system use.

3. FIRC as system clock

NOTE

Fast internal RC Oscillator is compliant with CAN and LIN

standards.

6.2.3.2 Slow internal RC oscillator (SIRC) electrical specifications

Table 19. Slow internal RC oscillator (SIRC) electrical specifications

Symbol

Parameter

Value

Typ.

Unit

Min.

—

Max.

—

F_SIRC

SIRC target frequency

MHz

ΔF

Frequency deviation across process, voltage, and

temperature < 105°C

—

%F_SIRC

ΔF125

Frequency deviation across process, voltage, and

temperature < 125°C

—

3.3

%F_SIRC

µs¹

T_Startup

Startup time

12.5

1. Startup time is defined as the time between clock enablement and clock availability for system use.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Memory and memory interfaces

6.2.4 Low Power Oscillator (LPO) electrical specifications

Table 20. Low Power Oscillator (LPO) electrical specifications

Symbol

F_LPO

Parameter

Internal low power oscillator frequency

Startup Time

Min.

113

—

Typ.

128

—

Max.

139

Unit

kHz

µs

T_startup

6.2.5 SPLL electrical specifications

Table 21. SPLL electrical specifications

Symbol

Parameter

PLL Reference Frequency Range

PLL Input Frequency

Min.

Typ.

—

Max.

Unit

F_{SPLL_REF}

MHz

F_{SPLL_Input}

F_{VCO_CLK}

F_{SPLL_CLK}

J_{CYC_SPLL}

—

VCO output frequency

180

—

320

160

PLL output frequency

PLL Period Jitter (RMS)³

—

at F_{VCO_CLK}180 MHz

—

120

—

at F_{VCO_CLK}320 MHz

J_{ACC_SPLL}

PLL accumulated jitter over 1µs (RMS)³

at F_{VCO_CLK}180 MHz

—

1350

600

—

at F_{VCO_CLK}320 MHz

—

D_UNL

Lock exit frequency tolerance

T_{SPLL_LOCK}Lock detector detection time⁴

4.47

—

5.97

150 × 10^-6

—

1075(1/F_{SPLL_REF}

)

1. F_{SPLL_REF}is PLL reference frequency range after the PREDIV. For PREDIV and MULT settings refer SCG_SPLLCFG

2. F_{SPLL_Input}is PLL input frequency range before the PREDIV must be limited to the range 8 MHz to 40 MHz. This input

source could be derived from a crystal oscillator or some other external square wave clock source using OSC bypass

mode. For external clock source settings refer SCG_SOSCCFG register of Reference Manual.

3. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each

PCB and results will vary

4. Lock detector detection time is defined as the time between PLL enablement and clock availability for system use.

6.3 Memory and memory interfaces

6.3.1 Flash memory module (FTFC) electrical specifications

This section describes the electrical characteristics of the flash memory module.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Memory and memory interfaces

6.3.1.1 Flash timing specifications — commands

Table 22. Flash command timing specifications for S32K14x

Symbol

Description¹

S32K142

Typ Max

S32K144

Typ Max

S32K146

Typ Max

S32K148

Typ Max Unit Notes

t_rd1blk

Read 1 Block

execution time

32 KB flash

64 KB flash

—

0.5

—

0.5

—

0.5

—

128 KB flash —

256 KB flash —

512 KB flash —

—

1.8

100

t_rd1sec

Read 1 Section 2 KB flash

execution time

—

100

µs

4 KB flash

t_pgmchk

t_pgm8

Program Check

execution time

—

µs

Program Phrase —

execution time

225

t_ersblk

Erase Flash

Block execution

time

32 KB flash

—

64 KB flash 30

128 KB flash —

256 KB flash 250

512 KB flash —

—

550

—

550

—

550

—

2125

—

250

4250

130

250

4250 250

4250

130

t_ersscr

Erase Flash

Sector execution

time

—

130

t_pgmsec1k

Program Section —

execution time

(1KB flash)

—

t_rd1all

Read 1s All

Block execution

time

—

2.8

—

2.3

—

5.2

—

8.2

t_rdonce

t_pgmonce

t_ersall

Read Once

execution time

—

µs

Program Once

execution time

250

—

700

—

Erase All Blocks —

execution time

2800 400

4900

10000 1400 17000 ms

35 35 µs

t_vfykey

Verify Backdoor

Access Key

—

execution time

t_ersallu

Erase All Blocks —

Unsecure

execution time

250

2800 400

4900

—

700

10000 1400 17000 ms

t_pgmpart

Program

32 KB

—

Partition for

EEPROM

backup

execution time

64 KB

—

150

EEPROM

backup

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Memory and memory interfaces

Table 22. Flash command timing specifications for S32K14x (continued)

Symbol

Description¹

S32K142

Typ Max

S32K144

Typ Max

S32K146

Typ Max

S32K148

Typ Max Unit Notes

t_setram

Set FlexRAM

Control

0.08

—

0.08

—

0.08

—

0.08

—

Function

Code 0xFF

execution time

32 KB

0.8

1.2

0.8

1.2

0.8

1.2

—

EEPROM

backup

48 KB

EEPROM

backup

1.5

1.9

1.5

—

1.3

—

64 KB

EEPROM

backup

1.3

385

430

475

385

430

475

360

1.3

1.9

1.3

385

430

475

385

430

475

360

1.9

—

t_eewr8b

Byte write to

FlexRAM

32 KB

EEPROM

backup

1700 385

1850 430

2000 475

1700 385

1850 430

2000 475

2000 360

1700

1850

2000

1700

1850

2000

1700

1850

µs

3^,4

execution time

48 KB

EEPROM

backup

—

64 KB

EEPROM

backup

2000 475

4000

—

t_eewr16b

16-bit write to

FlexRAM

32 KB

EEPROM

backup

1700

1850

—

µs

3^,4

execution time

48 KB

EEPROM

backup

—

64 KB

EEPROM

backup

2000 475

2000 360

4000

2000

t_eewr32bers

32-bit write to

erased FlexRAM

location

—

µs

execution time

t_eewr32b

32-bit write to

FlexRAM

execution time

32 KB

EEPROM

backup

630

720

810

200

2000 630

2125 720

2250 810

2000

2125

2250

630

720

810

2000

2125

—

3^,4

48 KB

EEPROM

backup

—

64 KB

EEPROM

backup

2250 810

4500

t_quickwr

32-bit Quick

Write execution write

time: Time from

CCIF clearing

(start the write)

until CCIF

1st 32-bit

550

200

150

550

200

150

550

200

150

1100

550

µs

4^,5^,6

2nd through 150

Next to Last

(Nth-1) 32-

bit write

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Memory and memory interfaces

Table 22. Flash command timing specifications for S32K14x (continued)

Symbol

Description¹

S32K142

Typ Max

S32K144

Typ Max

S32K146

Typ Max

S32K148

Typ Max Unit Notes

setting (32-bit

Last (Nth)

32-bit write

(time for

write only,

not cleanup)

200

550

200

550

200

550

200

550

write complete,

ready for next

32-bit write)

t_quickwrClnupQuick Write

Cleanup

—

(# of

—

(# of

—

(# of

—

(# of

Quick

Writes

) * 2.0

Quick

Writes )

* 2.0

Quick

Writes

) * 2.0

Quick

Writes

) * 2.0

execution time

1. All command times assumes 25 MHz or greater flash clock frequency (for synchronization time between internal/external

clocks).

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3. For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred. This may

be verified by executing FCCOB Command 0x77, and checking FCCOB number 5 contents show 0x00 - No EEPROM

issues detected.

4. 1st time EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2× the

times shown.

5. Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur

after this point even after a brownout or reset. If power on reset occurs before the Nth write completes, the last valid record

set will still be valid and the new records will be discarded.

6. Quick Write times may take up to 550 µs, as additional cleanup may occur when crossing sector boundaries.

7. Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes,

assuming still powered. Or via SETRAM cleanup execution command is requested at a later point.

Table 23. Flash command timing specifications for S32K11x

Symbol

Description¹

S32K116

Typ Max

S32K118

Max

Typ

Unit

Notes

t_rd1blk

Read 1 Block execution 32 KB flash

—

0.36

—

0.36

—

time

64 KB flash

128 KB flash

256 KB flash

512 KB flash

1.2

—

t_rd1sec

Read 1 Section

execution time

2 KB flash

4 KB flash

—

µs

100

t_pgmchk

t_pgm8

Program Check

execution time

µs

Program Phrase

execution time

—

225

t_ersblk

Erase Flash Block

execution time

32 KB flash

64 KB flash

128 KB flash

256 KB flash

512 KB flash

—

300

—

300

—

120

—

1100

—

250

—

2125

—

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Memory and memory interfaces

Table 23. Flash command timing specifications for S32K11x (continued)

Symbol

Description¹

S32K116

Typ Max

S32K118

Max

Typ

Unit

Notes

t_ersscr

Erase Flash Sector

execution time

—

130

t_pgmsec1k

Program Section

execution time (1 KB

flash)

—

t_rd1all

Read 1s All Block

execution time

—

1.7

—

2.8

µs

t_rdonce

t_pgmonce

t_ersall

Read Once execution

time

—

Program Once execution —

time

—

µs

Erase All Blocks

execution time

—

150

—

1500

230

—

2500

µs

t_vfykey

t_ersallu

t_pgmpart

Verify Backdoor Access

Key execution time

Erase All Blocks

Unsecure execution time

150

1500

—

230

2500

—

Program Partition for

32 KB EEPROM 71

EEPROM execution time backup

64 KB EEPROM

—

backup

t_setram

Set FlexRAM Function

execution time

Control Code

0xFF

0.08

—

0.08

0.8

—

32 KB EEPROM 0.8

backup

1.2

—

1.2

—

48 KB EEPROM

backup

—

64 KB EEPROM

backup

—

t_eewr8b

Byte write to FlexRAM

execution time

32 KB EEPROM 385

backup

1700

—

385

—

1700

—

µs

3^,4

48 KB EEPROM

backup

—

64 KB EEPROM

backup

—

t_eewr16b

16-bit write to FlexRAM 32 KB EEPROM 385

execution time

1700

—

385

—

1700

—

3^,4

backup

48 KB EEPROM

backup

—

64 KB EEPROM

backup

—

t_eewr32bers

32-bit write to erased

FlexRAM location

execution time

—

360

2000

360

2000

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Memory and memory interfaces

Table 23. Flash command timing specifications for S32K11x (continued)

Symbol

Description¹

S32K116

Typ Max

32-bit write to FlexRAM 32 KB EEPROM 630

S32K118

Max

Typ

630

Unit

µs

Notes

3^,4

t_eewr32b

2000

—

2000

execution time

backup

48 KB EEPROM

backup

—

64 KB EEPROM

backup

—

t_quickwr

32-bit Quick Write

1st 32-bit write

200

550

200

150

550

µs

4^,5^,6

execution time: Time

from CCIF clearing (start

the write) until CCIF

setting (32-bit write

complete, ready for next

32-bit write)

2nd through Next 150

to Last (Nth-1)

32-bit write

Last (Nth) 32-bit 200

write (time for

write only, not

cleanup)

550

200

—

550

t_quickwrClnup

Quick Write Cleanup

execution time

—

(# of

(# of Quick

Writes ) * 2.0

Quick

Writes ) *

2.0

1. All command times assume 25 MHz or greater flash clock frequency (for synchronization time between internal/external

clocks).

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3. For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred. This may

be verified by executing FCCOB Command 0x77, and checking FCCOB number 5 contents show 0x00 - No EEPROM

issues detected.

4. 1st time EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2x the

times shown.

5. Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur

after this point even after a brownout or reset. If power on reset occurs before the Nth write completes, the last valid record

set will still be valid and the new records will be discarded.

6. Quick Write times may take up to 550 µs, as additional cleanup may occur when crossing sector boundaries.

7. Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes,

assuming still powered. Or via SETRAM cleanup execution command is requested at a later point.

NOTE

Under certain circumstances FlexMEM maximum times may be

exceeded. In this case the user or application may wait, or assert

reset to the FTFC macro to stop the operation.

6.3.1.2 Reliability specifications

Table 24. NVM reliability specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

When using as Program and Data Flash

t_nvmretp1kData retention after up to 1 K cycles

n_nvmcycpCycling endurance

—

years

1 K

cycles

2, 3

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Memory and memory interfaces

Table 24. NVM reliability specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

When using FlexMemory feature : FlexRAM as Emulated EEPROM

t_nvmreteeData retention

—

years

Write endurance

n_nvmwree16

5, 6, 7

100 K

1.6 M

—

writes

• EEPROM backup to FlexRAM ratio = 16

n_nvmwree256

• EEPROM backup to FlexRAM ratio = 256

1. Data retention period per block begins upon initial user factory programming or after each subsequent erase.

2. Program and Erase for PFlash and DFlash are supported across product temperature specification in Normal Mode (not

supported in HSRUN mode).

3. Cycling endurance is per DFlash or PFlash Sector.

4. Data retention period per block begins upon initial user factory programming or after each subsequent erase. Background

maintenance operations during normal FlexRAM usage extend effective data retention life beyond 5 years.

5. FlexMemory write endurance specified for 16-bit and/or 32-bit writes to FlexRAM and is supported across product

temperature specification in Normal Mode (not supported in HSRUN mode). Greater write endurance may be achieved

with larger ratios of EEPROM backup to FlexRAM.

6. For usage of any EEE driver other than the FlexMemory feature, the endurance spec will fall back to the specified

endurance value of the D-Flash specification (1K).

7. FlexMemory calculator tool is available at NXP web site for help in estimation of the maximum write endurance achievable

at specific EEPROM/FlexRAM ratios. The “In Spec” portions of the online calculator refer to the NVM reliability

specifications section of data sheet. This calculator is only applies to the FlexMemory feature.

6.3.2 QuadSPI AC specifications

The following table describes the QuadSPI electrical characteristics.

• Measurements are with maximum output load of 25 pF, input transition of 1 ns and

pad configured with fastest slew settings (DSE = 1'b1).

• I/O operating voltage ranges from 2.97 V to 3.6 V

• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the

interface should be OFF.

• Add 50 ohm series termination on board in QuadSPI SCK for Flash A to avoid loop

back reflection when using in Internal DQS (PAD Loopback) mode.

• QuadSPI trace length should be 3 inches.

• For non-Quad mode of operation if external device doesn’t have pull-up feature,

external pull-up needs to be added at board level for non-used pads.

• With external pull-up, performance of the interface may degrade based on load

associated with external pull-up.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Table 25. QuadSPI electrical specifications

FLASH PORT

Sym Unit

FLASH A

FLASH B

RUN¹

SDR

HSRUN¹

SDR

RUN/HSRUN²

QuadSPI Mode

SDR

DDR³

Internal

Internal DQS

Internal

Internal DQS

Internal

External DQS

Sampling

PAD

Internal

PAD

Internal

External DQS

Loopback

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

MCR[DDR_EN]

MCR[DQS_EN]

MCR[SCLKCFG[0]]

MCR[SCLKCFG[1]]

MCR[SCLKCFG[2]]

MCR[SCLKCFG[3]]

MCR[SCLKCFG[5]]

SMPR[FSPHS]

SMPR[FSDLY]

SOCCR

[SOCCFG[7:0]]

SOCCR[SOCCFG[15:8]]

FLSHCR[TDH]

0x00

0x01

Timing Parameters

SCK Clock Frequency

SCK Clock Period

f_SCK

t_SCK

MHz

20⁴

50.0

50.0⁴

Table continues on the next page...

Table 25. QuadSPI electrical specifications (continued)

FLASH PORT

Sym Unit

FLASH A

FLASH B

RUN¹

SDR

HSRUN¹

SDR

RUN/HSRUN²

QuadSPI Mode

SDR

DDR³

Internal

Internal DQS

Internal

Internal DQS

Internal

External DQS

Sampling

PAD

Internal

PAD

Internal

External DQS

Loopback

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

SCK Duty Cycle

t_SDC

Data Input Setup Time

Data Input Hold Time

Data Output Valid Time

t_IS

t_IH

2.5

1.6

t_OV

t_IV

4.5

3⁵

Data Output In-Valid

Time

CS to SCK Time ⁶

SCK to CS Time ⁷

Output Load

t_CSSCK

t_SCKCS

1. See Reference Manual for details on mode settings

2. See Reference Manual for details on mode settings

3. Valid for HyperRAM only

4. RWDS(External DQS CLK) frequency

5. For operating frequency ≤ 64 Mhz,Output invalid time is 5 ns.

6. Program register value QuadSPI_FLSHCR[TCSS] = 4`h2

7. Program register value QuadSPI_FLSHCR[TCSH] = 4`h1

Memory and memory interfaces

Clock

t_SCK

t_SDC

SCK

t_IH

t_IS

Data in

Figure 9. QuadSPI input timing (SDR mode) diagram

Clock

SCK

t_SCK

t_SDC

t_SCKCS

t_CSSCK

t_IV

t_OV

Data out

Figure 10. QuadSPI output timing (SDR mode) diagram

TIS

TIH

invalid

TIS– Setup Time

–

old Time

Figure 11. QuadSPI input timing (HyperRAM mode) diagram

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Analog modules

SCK

tIV

tOV

Output Invalid Data

Figure 12. QuadSPI output timing (HyperRAM mode) diagram

6.4 Analog modules

6.4.1 ADC electrical specifications

6.4.1.1 12-bit ADC operating conditions

Table 26. 12-bit ADC operating conditions

Symbol Description

Conditions

Min.

Typ.¹

Max.

Unit Notes

V_REFHADC reference voltage high

See Voltage

and current

operating

V_DDA

See Voltage

and current

operating

requirements

for values

requirements

for values

V_REFLADC reference voltage low

See Voltage

and current

operating

See Voltage mV

and current

operating

requirements

for values

requirements

for values

V_ADINInput voltage

V_REFL

—

V_REFH

R_S

Source impedendance

f_ADCK< 4 MHz

kΩ

R_SW1

Channel Selection Switch

Impedance

—

-0.75

1.2

R_AD

C_P1

C_P2

C_S

Sampling Switch Impedance

Pin Capacitance

—

kΩ

Analog Bus Capacitance

Sampling capacitance

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

ADC electrical specifications

Table 26. 12-bit ADC operating conditions (continued)

Symbol Description

f_ADCKADC conversion clock

frequency

f_CONVADC conversion frequency

Conditions

Min.

Typ.¹

Max.

Unit Notes

Normal usage

MHz

3, 4

No ADC hardware

averaging.⁵Continuous

conversions enabled,

subsequent conversion

time

46.4

1.45

928

1160

Ksps

6, 7

ADC hardware averaging

set to 32. ⁵Continuous

conversions enabled,

subsequent conversion

time

36.25

Ksps

6, 7

1. Typical values assume V_DDA= 5 V, Temp = 25 °C, f_ADCK= 40 MHz, R_AS=20 Ω, and C_AS=10 nF unless otherwise stated.

Typical values are for reference only, and are not tested in production.

2. For packages without dedicated V_REFHand V_REFLpins, V_REFHis internally tied to V_DDA, and V_REFLis internally tied to V_SS

To get maximum performance, reference supply quality should be better than SAR ADC. See application note AN5032 for

details.

3. Clock and compare cycle need to be set according to the guidelines mentioned in the Reference Manual .

4. ADC conversion will become less reliable above maximum frequency.

5. When using ADC hardware averaging, see the Reference Manual to determine the most appropriate setting for AVGS.

6. Numbers based on the minimum sampling time of 275 ns.

7. For guidelines and examples of conversion rate calculation, see the Reference Manual or download the ADC calculator

tool.

Figure 13. ADC input impedance equivalency diagram

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

ADC electrical specifications

6.4.1.2 12-bit ADC electrical characteristics

NOTE

• ADC performance specifications are documented using a

single ADC. For parallel/simultaneous operation of both

ADCs, either for sampling the same channel by both ADCs

or for sampling different channels by each ADC, some

amount of decrease in performance can be expected. Care

must be taken to stagger the two ADC conversions, in

particular the sample phase, to minimize the impact of

simultaneous conversions.

• On reduced pin packages where ADC reference pins are

shared with supply pins, ADC analog performance

characteristics may be impacted. The amount of variation

will be directly impacted by the external PCB layout and

hence care must be taken with PCB routing. See AN5426

for details

Table 27. 12-bit ADC characteristics (2.7 V to 3 V) (V_REFH= V_DDA, V_REFL= V_SS)

Symbol Description

V_DDASupply voltage

Conditions ¹

Min.

2.7

—

Typ.²

Max.

Unit

Notes

—

I_{DDA_ADC}Supply current per ADC

SMPLTS Sample Time

0.6

—

275

Refer to

the

Reference

Manual

TUE⁴

DNL

INL

Total unadjusted error

Differential non-linearity

Integral non-linearity

—

LSB⁵

6, 7, 8, 9

1.0

2.0

1. All accuracy numbers assume the ADC is calibrated with V_REFH=V_DDA=V_DD, with the calibration frequency set to half the

ADC clock frequency.

2. Typical values assume V_DDA= 3 V, Temp = 25 °C, f_ADCK= 40 MHz, R_AS=20 Ω, and C_AS=10 nF.

3. The ADC supply current depends on the ADC conversion rate.

4. Represents total static error, which includes offset and full scale error.

5. 1 LSB = (V_REFH- V_REFL)/2^N

6. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device

use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings

for AVGS.

7. For ADC signals adjacent to V_DD/V_SSor XTAL/EXTAL or high frequency switching pins, some degradation in the ADC

performance may be observed.

8. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the

internal analog parameters, assume minor degradation.

9. All the parameters in the table are given assuming system clock as the clocking source for ADC.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

ADC electrical specifications

Table 28. 12-bit ADC characteristics (3 V to 5.5 V)(V_REFH= V_DDA, V_REFL= V_SS)

Symbol Description

V_DDASupply voltage

Conditions ¹

Min.

Typ.²

Max.

5.5

Unit

Notes

—

I_{DDA_ADC}Supply current per ADC

SMPLTS Sample Time

—

275

—

Refer to

the

Reference

Manual

TUE⁴

DNL

INL

Total unadjusted error

Differential non-linearity

Integral non-linearity

—

LSB⁵

6, 7, 8, 9

0.7

1.0

1. All accuracy numbers assume the ADC is calibrated with V_REFH=V_DDA=V_DD, with the calibration frequency set to half the

ADC clock frequency.

2. Typical values assume V_DDA= 5.0 V, Temp = 25 °C, f_ADCK= 40 MHz, R_AS=20 Ω, and C_AS=10 nF unless otherwise stated.

3. The ADC supply current depends on the ADC conversion rate.

4. Represents total static error, which includes offset and full scale error.

5. 1 LSB = (V_REFH- V_REFL)/2^N

6. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device

use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings

for AVGS.

7. For ADC signals adjacent to V_DD/V_SSor XTAL/EXTAL or high frequency switching pins, some degradation in the ADC

performance may be observed.

8. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the

internal analog parameters, assume minor degradation.

9. All the parameters in the table are given assuming system clock as the clocking source for ADC.

NOTE

• Due to triple bonding in lower pin packages like 32-QFN,

48-LQFP, and 64-LQFP degradation might be seen in ADC

parameters.

• When using high speed interfaces such as the QuadSPI,

SAI0, SAI1 or ENET there may be some ADC degradation

on the adjacent analog input paths. See following table for

details.

Pin name

PTE8

TGATE purpose

CMP0_IN3

PTC3

ADC0_SE11/CMP0_IN4

ADC0_SE10/CMP0_IN5

CMP0_IN6

PTC2

PTD7

PTD6

CMP0_IN7

PTD28

PTD27

ADC1_SE22

ADC1_SE21

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

ADC electrical specifications

6.4.2 CMP with 8-bit DAC electrical specifications

Table 30. Comparator with 8-bit DAC electrical specifications

Symbol

Description

Min.

Typ.

Max.

Unit

I_DDHS

Supply current, High-speed mode¹

μA

-40 - 125 ℃

—

230

300

I_DDLS

Supply current, Low-speed mode¹

-40 - 105 ℃

μA

—

-40 - 125 ℃

V_AIN

V_AIO

Analog input voltage

Analog input offset voltage, High-speed mode

-40 - 125 ℃

0 - V_DDA

V_DDA

-25

-40

—

V_AIO

Analog input offset voltage, Low-speed mode

-40 - 125 ℃

t_DHSB

Propagation delay, High-speed mode²

-40 - 105 ℃

200

300

-40 - 125 ℃

t_DLSB

t_DHSS

t_DLSS

Propagation delay, Low-speed mode²

µs

-40 - 105 ℃

—

0.5

-40 - 125 ℃

Propagation delay, High-speed mode³

-40 - 105 ℃

—

400

500

-40 - 125 ℃

Propagation delay, Low-speed mode³

-40 - 105 ℃

—

-40 - 125 ℃

t_IDHS

Initialization delay, High-speed mode⁴

μs

-40 - 125 ℃

—

1.5

t_IDLS

Initialization delay, Low-speed mode⁴

-40 - 125 ℃

—

V_HYST0

Analog comparator hysteresis, Hyst0 (V_AIO

)

-40 - 125 ℃

V_HYST1

Analog comparator hysteresis, Hyst1, High-speed

mode

-40 - 125 ℃

—

Analog comparator hysteresis, Hyst1, Low-speed

mode

-40 - 125 ℃

V_HYST2

Analog comparator hysteresis, Hyst2, High-speed

mode

-40 - 125 ℃

133

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

ADC electrical specifications

Table 30. Comparator with 8-bit DAC electrical specifications (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

Analog comparator hysteresis, Hyst2, Low-speed

mode

-40 - 125 ℃

—

V_HYST3

Analog comparator hysteresis, Hyst3, High-speed

mode

-40 - 125 ℃

—

200

120

Analog comparator hysteresis, Hyst3, Low-speed

mode

-40 - 125 ℃

—

I_DAC8b

8-bit DAC current adder (enabled)

3.3V Reference Voltage

—

μA

LSB⁶

μs

5V Reference Voltage

—

INL⁵

DNL

t_DDAC

8-bit DAC integral non-linearity

8-bit DAC differential non-linearity

Initialization and switching settling time

–0.75

–0.5

—

0.75

0.5

1. Difference at input > 200mV

2. Applied (100 mV + V_HYST0/1/2/3+ max. of V_AIO) around switch point.

3. Applied (30 mV + 2 × V_HYST0/1/2/3+ max. of V_AIO) around switch point.

4. Applied (100 mV + V_HYST0/1/2/3).

5. Calculation method used: Linear Regression Least Square Method

6. 1 LSB = V_reference/256

NOTE

For comparator IN signals adjacent to V_DD/V_SSor XTAL/

EXTAL or switching pins cross coupling may happen and

hence hysteresis settings can be used to obtain the desired

comparator performance. Additionally, an external capacitor

(1nF) should be used to filter noise on input signal. Also, source

drive should not be weak (Signal with < 50 K pull up/down is

recommended).

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

ADC electrical specifications

Figure 14. Typical hysteresis vs. Vin level (VDDA = 3.3 V, PMODE = 0)

Figure 15. Typical hysteresis vs. Vin level (VDDA = 3.3 V, PMODE = 1)

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

ADC electrical specifications

Figure 16. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 0)

Figure 17. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 1)

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Communication modules

6.5 Communication modules

6.5.1 LPUART electrical specifications

Refer to General AC specifications for LPUART specifications.

6.5.1.1 Supported baud rate

Baud rate = Baud clock / ((OSR+1) * SBR).

For details, see section: 'Baud rate generation' of the Reference Manual.

6.5.2 LPSPI electrical specifications

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus

with master and slave operations. Many of the transfer attributes are programmable. The

following tables provide timing characteristics for classic LPSPI timing modes.

• All timing is shown with respect to 20% V_DDand 80% V_DDthresholds.

• All measurements are with maximum output load of 50 pF, input transition of 1 ns

and pad configured with fastest slew setting ( DSE = 1 ).

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Table 31. LPSPI electrical specifications1

Num Symbol Description

Conditions

Run Mode²

HSRUN Mode²

5.0 V IO 3.3 V IO

VLPR Mode

5.0 V IO 3.3 V IO

Unit

5.0 V IO 3.3 V IO

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

, 3, 4

f_periph

Peripheral

Frequency

Slave

MHz

Master

Loopback⁵

Master

Loopback(slow)⁶

f_op

Frequency of Slave

14 ⁷

MHz

operation

Master

Loopback⁵

Master

Loopback(slow)⁶

t_SPSCKSPSCK

period

Slave

100

500

Master

Loopback⁵

Master

500

Loopback(slow)⁶

t_Lead

Enable lead

Slave

time (PCS to

SPSCK delay)

Master

Loopback⁵

Master

Loopback(slow)⁶

Table continues on the next page...

Table 31. LPSPI electrical specifications1 (continued)

Num Symbol Description

Conditions

Run Mode²

HSRUN Mode²

VLPR Mode

5.0 V IO 3.3 V IO

Min. Max.

Unit

5.0 V IO 3.3 V IO

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

t_Lag

Enable lag

time (After

SPSCK delay)

Slave

Master

Loopback⁵

Master

Loopback(slow)⁶

t_WSPSCKClock(SPSCK Slave

) high or low

time (SPSCK

duty cycle)

Master

Loopback⁵

Master

Loopback(slow)⁶

t_SU

Data setup

time(inputs)

Slave

37¹¹

32 ¹²

Master

Loopback⁵

Master

Loopback(slow)⁶

t_HI

Data hold

time(inputs)

Slave

Master

Loopback⁵

Master

Loopback(slow)⁶

Table continues on the next page...

Table 31. LPSPI electrical specifications1 (continued)

Num Symbol Description

Conditions

Run Mode²

HSRUN Mode²

VLPR Mode

5.0 V IO 3.3 V IO

Unit

5.0 V IO 3.3 V IO

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

t_a

Slave access Slave

time

100

t_dis

Slave MISO

(SOUT)

Slave

100

disable time

t_v

Data valid

(after SPSCK

edge)

Slave

36 ¹¹

31 ¹²

Master

Loopback⁵

Master

Loopback(slow)⁶

t_HO

Data hold

time(outputs)

Slave

Master

-15

-10

-22

-14

-15

-10

-23

-14

-22

-14

-29

-19

Master

Loopback⁵

Master

-15

-22

-15

-22

-21

-27

Loopback(slow)⁶

t_RI/FI

Rise/Fall time Slave

input

Master

Loopback⁵

Master

Loopback(slow)⁶

t_RO/FORise/Fall time Slave

output

Master

Loopback ⁵

Table continues on the next page...

Table 31. LPSPI electrical specifications1 (continued)

Num Symbol Description

Conditions

Run Mode²

HSRUN Mode²

5.0 V IO 3.3 V IO

Min. Max. Min. Max.

VLPR Mode

5.0 V IO 3.3 V IO

Min. Max. Min. Max.

Unit

5.0 V IO 3.3 V IO

Min.

Max.

Min.

Max.

Master

Loopback(slow)

1. Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode.

2. While transitioning from HSRUN mode to RUN mode, LPSPI output clock should not be more than 14 MHz.

3. f_periph= LPSPI peripheral clock

4. t_periph= 1/f_periph

5. Master Loopback mode - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1.

Clock pads used are PTD15 and PTE0. Applicable only for LPSPI0.

6. Master Loopback (slow) - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1.

Clock pad used is PTB2. Applicable only for LPSPI0.

7. This is the maximum operating frequency (f_op) for LPSPI0 with medium PAD type only. Otherwise, the maximum operating frequency (f_op) is 12 Mhz.

8. Set the PCSSCK configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where PCSSCK ranges from 0 to 255.

9. Set the SCKPCS configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where SCKPCS ranges from 0 to 255.

10. While selecting odd dividers, ensure Duty Cycle is meeting this parameter.

11. Maximum operating frequency (f_op) is 12 MHz irrespective of PAD type and LPSPI instance.

12. Applicable for LPSPI0 only with medium PAD type, with maximum operating frequency (f_op) as 14 MHz.

Communication modules

(OUTPUT)

SPSCK

(CPOL=0)

(OUTPUT)

SPSCK

(CPOL=1)

(OUTPUT)

MISO

(INPUT)

BIT 6 . . . 1

MSB IN

LSB IN

MOSI

(OUTPUT)

BIT 6 . . . 1

MSB OUT

LSB OUT

1. If configured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 18. LPSPI master mode timing (CPHA = 0)

(OUTPUT)

SPSCK

(CPOL=0)

(OUTPUT)

SPSCK

(CPOL=1)

(OUTPUT)

MISO

(INPUT)

BIT 6 . . . 1

LSB IN

MSB IN

BIT 6 . . . 1

MOSI

(OUTPUT)

PORT DATA

MASTER MSB OUT

PORT DATA

MASTER LSB OUT

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 19. LPSPI master mode timing (CPHA = 1)

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Communication modules

(INPUT)

SPSCK

(CPOL=0)

(INPUT)

SPSCK

(CPOL=1)

(INPUT)

see

note

SEE

NOTE

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE MSB

SLAVE LSB OUT

MOSI

(INPUT)

LSB IN

MSB IN

BIT 6 . . . 1

Figure 20. LPSPI slave mode timing (CPHA = 0)

(INPUT)

SPSCK

(CPOL=0)

(INPUT)

SPSCK

(CPOL=1)

(INPUT)

SLAVE MSB OUT

see

note

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE LSB OUT

LSB IN

MOSI

(INPUT)

MSB IN

Figure 21. LPSPI slave mode timing (CPHA = 1)

6.5.3 LPI2C electrical specifications

See General AC specifications for LPI2C specifications.

For supported baud rate see section 'Chip-specific LPI2C information' of the Reference

Manual.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Communication modules

6.5.4 FlexCAN electical specifications

For supported baud rate, see section 'Protocol timing' of the Reference Manual.

6.5.5 SAI electrical specifications

The following table describes the SAI electrical characteristics.

• Measurements are with maximum output load of 50 pF, input transition of 1 ns and

pad configured with fastest slew settings (DSE = 1'b1).

• I/O operating voltage ranges from 2.97 V to 3.6 V

• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the

interface should be OFF.

Table 32. Master mode timing specifications

Symbol

—

Description

Operating voltage

Min.

2.97

Max.

3.6

—

Unit

SAI_MCLK cycle time

MCLK period

SAI_MCLK pulse width high/low

SAI_BCLK cycle time

45%

55%

—

SAI_BCLK pulse width high/low

45%

55%

—

BCLK period

SAI_RXD input setup before

SAI_BCLK

SAI_RXD input hold after

SAI_BCLK

—

-2

—

SAI_BCLK to SAI_TXD output

valid

SAI_BCLK to SAI_TXD output

invalid

—

SAI_FS input setup before

SAI_BCLK

S10

S11

S12

SAI_FS input hold after

SAI_BCLK

SAI_BCLK to SAI_FS output

valid

—

-2

SAI_BCLK to SAI_FS output

invalid

—

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Communication modules

SAI_MCLK (output)

SAI_BCLK (output)

SAI_FS (output)

SAI_FS (input)

SAI_TXD

S11

S12

S10

SAI_RXD

Figure 22. SAI Timing — Master modes

Table 33. Slave mode timing specifications

Symbol

—

Description

Min.

2.97

Max.

3.6

Unit

Operating voltage

S13

SAI_BCLK cycle time (input)

—

S14¹

SAI_BCLK pulse width high/low

(input)

45%

55%

BCLK period

S15

S16

S17

S18

S19

SAI_RXD input setup before

SAI_BCLK

—

SAI_RXD input hold after

SAI_BCLK

SAI_BCLK to SAI_TXD output

valid

—

SAI_BCLK to SAI_TXD output

invalid

SAI_FS input setup before

SAI_BCLK

S20

S21

S22

SAI_FS input hold after SAI_BCLK

SAI_BCLK to SAI_FS output valid

—

SAI_BCLK to SAI_FS output

invalid

1. The slave mode parameters (S15 - S22) assume 50% duty cycle on SAI_BCLK input. Any change in SAI_BCLK duty cycle

input must be taken care during the board design or by the master timing.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Communication modules

S13

S14

SAI_BCLK (input)

SAI_FS (output)

SAI_FS (input)

SAI_TXD

S14

S21

S22

S19

S20

S17

S18

S17

S18

S15

S16

SAI_RXD

Figure 23. SAI Timing — Slave modes

6.5.6 Ethernet AC specifications

The following timing specs are defined at the chip I/O pin and must be translated

appropriately to arrive at timing specs/constraints for the physical interface.

The following table describes the MII electrical characteristics.

• Measurements are with maximum output load of 25 pF, input transition of 1 ns and

pad configured with fastest slew settings (DSE = 1'b1).

• I/O operating voltage ranges from 2.97 V to 3.6 V

• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the

interface should be OFF.

Table 34. MII signal switching specifications

Symbol

—

Description

Min.

—

Max.

Unit

RXCLK frequency

MHz

MII1

MII2

MII3

MII4

—

RXCLK pulse width high

35%

65%

—

RXCLK period

RXCLK pulse width low

RXCLK period

RXD[3:0], RXDV, RXER to RXCLK setup

RXCLK to RXD[3:0], RXDV, RXER hold

TXCLK frequency

—

MHz

TXCLK period

MII5

MII6

MII7

MII8

TXCLK pulse width high

35%

65%

—

TXCLK pulse width low

TXCLK to TXD[3:0], TXEN, TXER invalid

TXCLK to TXD[3:0], TXEN, TXER valid

—

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Communication modules

MII2

MII3

MII1

MII4

RXCLK (input)

RXD[n:0]

RXDV

Valid data

RXER

Figure 24. MII receive diagram

MII6

MII5

TXCLK (input)

TXD[n:0]

TXEN

MII8

MII7

Valid data

TXER

Figure 25. MII transmit signal diagram

The following table describes the RMII electrical characteristics.

• Measurements are with maximum output load of 25 pF, input transition of 1 ns and

pad configured with fastest slew settings (DSE = 1'b1).

• I/O operating voltage ranges from 2.97 V to 3.6 V

• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the

interface should be OFF.

Table 35. RMII signal switching specifications

Symbol

Description

Min.

—

Max.

Unit

—

RMII input clock RMII_CLK Frequency

MHz

RMII1, RMII5 RMII_CLK pulse width high

35%

65%

RMII_CLK

period

RMII2, RMII6 RMII_CLK pulse width low

35%

65%

RMII_CLK

period

RMII3

RMII4

RXD[1:0], CRS_DV, RXER to RMII_CLK setup

RMII_CLK to RXD[1:0], CRS_DV, RXER hold

Table continues on the next page...

—

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Communication modules

Table 35. RMII signal switching specifications

(continued)

Symbol

RMII7

Description

Min.

Max.

—

Unit

RMII_CLK to TXD[1:0], TXEN invalid

RMII_CLK to TXD[1:0], TXEN valid

RMII8

—

RMII2

RMII3

RMII1

RMII4

RMII_CLK(input)

RXD[n:0]

Valid data

CRS_DV

RXER

Figure 26. RMII receive diagram

RMII6

RMII5

RMII_CLK (input)

TXD[n:0]

RMII8

RMII7

Valid data

TXEN

Figure 27. RMII transmit diagram

The following table describes the MDIO electrical characteristics.

• Measurements are with maximum output load of 25 pF, input transition of 1 ns and

pad configured with fastest slew settings (DSE = 1'b1).

• I/O operating voltage ranges from 2.97 V to 3.6 V

• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the

interface should be OFF.

• MDIO pin must have external Pull-up.

Table 36. MDIO timing specifications

Symbol

Description

MDC Clock Frequency

Min.

Max.

Unit

—

2.5

MHz

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Debug modules

Table 36. MDIO timing specifications (continued)

Symbol

MDC1

MDC2

MDC3

MDC4

MDC5

Description

MDC pulse width high

Min.

40%

Max.

60%

—

Unit

MDC period

MDC pulse width low

MDC period

MDIO (input) to MDC rising edge setup

MDIO (input) to MDC rising edge hold

—

MDC falling edge to MDIO output valid

(maximum propagation delay)

—

MDC6

MDC falling edge to MDIO output invalid

(minimum propagation delay)

-10

—

MDC1

MDC2

MDC (output)

MDC6

MDIO (output)

MDIO (input)

MDC5

MDC3

MDC4

Figure 28. MII/RMII serial management channel timing diagram

6.5.7 Clockout frequency

Maximum supported clock out frequency for this device is 20 MHz

6.6 Debug modules

6.6.1 SWD electrical specofications

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Table 37. SWD electrical specifications

Symbol

Description

Run Mode

HSRUN Mode

5.0 V IO 3.3 V IO

VLPR Mode

5.0 V IO 3.3 V IO

Min. Max.

Unit

5.0 V IO

Min. Max.

3.3 V IO

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

SWD_CLK frequency of

operation

MHz

SWD_CLK cycle period

1/S1

SWD_CLK clock pulse width

SWD_CLK rise and fall times

SWD_DIO input data setup time

to SWD_CLK rise

S10

S11

S12

S13

SWD_DIO input data hold time

after SWD_CLK rise

SWD_CLK high to SWD_DIO

data valid

SWD_CLK high to SWD_DIO

high-Z

SWD_CLK high to SWD_DIO

data invalid

Debug modules

SWD_CLK (input)

Figure 29. Serial wire clock input timing

SWD_CLK

SWD_DIO

S10

Input data valid

S11

S13

Output data valid

S12

Figure 30. Serial wire data timing

6.6.2 Trace electrical specifications

The following table describes the Trace electrical characteristics.

• Measurements are with maximum output load of 50 pF, input transition of 1 ns and

pad configured with fastest slew settings (DSE = 1'b1).

• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the

interface should be OFF.

Table 38. Trace specifications

Symbol

Description

RUN Mode

HSRUN Mode

112 80

VLPR

Mode

Unit

—

Fsys

System frequency

MHz

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Debug modules

Table 38. Trace specifications (continued)

Symbol

Description

RUN Mode

HSRUN Mode

VLPR

Mode

Unit

f_TRACE

t_DVO

t_DIV

Max Trace frequency

Data Output Valid

Data Output Invalid

74.667

MHz

-10

-2

f_TRACE

t_DVO

t_DIV

Max Trace frequency

Data Output Valid

Data Output Invalid

22.86

22.4

22.86

MHz

-10

-4

Figure 31. TRACE CLKOUT specifications

6.6.3 JTAG electrical specifications

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Table 39. JTAG electrical specifications

Symbol

Description

Run Mode

3.3 V IO

Min. Max.

HSRUN Mode

5.0 V IO 3.3 V IO

VLPR Mode

5.0 V IO 3.3 V IO

Unit

5.0 V IO

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

TCLK frequency of operation

Boundary Scan

JTAG

MHz

TCLK cycle period

TCLK clock pulse width

Boundary Scan

JTAG

1/JI

TCLK rise and fall times

Boundary scan input data

setup time to TCLK rise

Boundary scan input data

hold time after TCLK rise

TCLK low to boundary scan

output data valid

TCLK low to boundary scan

output data invalid

TCLK low to boundary scan

output high-Z

J10

J11

TMS, TDI input data setup

time to TCLK rise

TMS, TDI input data hold

time after TCLK rise

J12

J13

TCLK low to TDO data valid

TCLK low to TDO data

invalid

J14

TCLK low to TDO high-Z

Debug modules

TCLK (input)

Figure 32. Test clock input timing

TCLK

Input data valid

Data inputs

Data outputs

Output data valid

Figure 33. Boundary scan (JTAG) timing

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Thermal attributes

TCLK

J10

J11

Input data valid

TDI/TMS

J12

J13

Output data valid

TDO

J14

Figure 34. Test Access Port timing

7 Thermal attributes

7.1 Description

The tables in the following sections describe the thermal characteristics of the device.

NOTE

Junction temperature is a function of die size, on-chip power

dissipation, package thermal resistance, mounting side (board)

temperature, ambient temperature, air flow, power dissipation

or other components on the board, and board thermal resistance.

7.2 Thermal characteristics

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Table 40. Thermal characteristics for the 32/48/64/100/144/176-pin LQFP package

Rating

Conditions

Symbol

Package

Values

Unit

S32K116 S32K118 S32K142 S32K144 S32K146 S32K148

Thermal resistance, Junction to Ambient

(Natural Convection)^{1, 2}

Single layer

board (1s)

R_θJA

°C/W

100

144

176

Thermal resistance, Junction to Ambient

(Natural Convection)¹

Two layer

board (1s1p)

R_θJA

100

144

176

Thermal resistance, Junction to Ambient

(Natural Convection)^{1, 2}

Four layer

board (2s2p)

R_θJA

100

144

176

Thermal resistance, Junction to Ambient

(@200 ft/min)^{1, 3}

Single layer

board (1s)

R_θJMA

100

144

176

Thermal resistance, Junction to Ambient

(@200 ft/min)¹

Two layer

board (1s1p)

R_θJMA

100

Table continues on the next page...

Table 40. Thermal characteristics for the 32/48/64/100/144/176-pin LQFP package

(continued)

Rating

Conditions

Symbol

Package

Values

Unit

S32K116 S32K118 S32K142 S32K144 S32K146 S32K148

144

176

Thermal resistance, Junction to Ambient

(@200 ft/min)^{1, 3}

Four layer

board (2s2p)

R_θJMA

100

144

176

Thermal resistance, Junction to Board⁴

—

R_θJB

R_θJC

ψ_JT

100

144

176

Thermal resistance, Junction to Case ⁵

100

144

176

Thermal resistance, Junction to Package

Top⁶

Natural

Convection

100

144

176

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air

flow, power dissipation of other components on the board, and board thermal resistance.

2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.

3. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the

package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek

letters are not available, the thermal characterization parameter is written as Psi-JT.

Table 41. Thermal characteristics for the 100 MAPBGA package

Rating

Conditions

Symbol

Values

S32K144

61.0

Unit

S32K146

S32K148

Thermal resistance, Junction to Ambient (Natural

Convection) ^{1, 2}

Single layer board (1s)

R_θJA

57.2

52.5

°C/W

Thermal resistance, Junction to Ambient (Natural

Convection) ^{1, 2, 3}

Four layer board

(2s2p)

32.1

35.6

27.5

Thermal resistance, Junction to Ambient (@200 ft/min) ^{1, 2, 3}Single layer board (1s)

R_θJMA

44.1

27.2

46.6

30.9

39.0

22.8

°C/W

Thermal resistance, Junction to Ambient (@200 ft/min)^{1, 3}

Two layer board

(2s2p)

Thermal resistance, Junction to Board⁴

Thermal resistance, Junction to Case ⁵

—

R_θJB

R_θJC

ψ_JT

15.3

10.2

0.2

18.9

14.2

0.4

11.2

7.5

°C/W

Thermal resistance, Junction to Package Top outside

center⁶

0.2

Thermal resistance, Junction to Package Bottom outside

center⁷

—

ψ_JB

12.2

15.9

18.3

°C/W

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air

flow, power dissipation of other components on the board, and board thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the

package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek

letters are not available, the thermal characterization parameter is written as Psi-JT.

7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12.

When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.

Thermal attributes

7.3 General notes for specifications at maximum junction

temperature

An estimation of the chip junction temperature, T_J, can be obtained from this equation:

where:

• T_A= ambient temperature for the package (°C)

• R_θJA= junction to ambient thermal resistance (°C/W)

• P_D= power dissipation in the package (W)

The junction to ambient thermal resistance is an industry standard value that provides a

quick and easy estimation of thermal performance. Unfortunately, there are two values in

common usage: the value determined on a single layer board and the value obtained on a

board with two planes. For packages such as the PBGA, these values can be different by

a factor of two. Which value is closer to the application depends on the power dissipated

by other components on the board. The value obtained on a single layer board is

appropriate for the tightly packed printed circuit board. The value obtained on the board

with the internal planes is usually appropriate if the board has low power dissipation and

the components are well separated.

When a heat sink is used, the thermal resistance is expressed in the following equation as

the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:

where:

• R_θJA= junction to ambient thermal resistance (°C/W)

• R_θJC= junction to case thermal resistance (°C/W)

• R_θCA= case to ambient thermal resistance (°C/W)

R_θJCis device related and cannot be influenced by the user. The user controls the thermal

environment to change the case to ambient thermal resistance, R_θCA. For instance, the

user can change the size of the heat sink, the air flow around the device, the interface

material, the mounting arrangement on printed circuit board, or change the thermal

dissipation on the printed circuit board surrounding the device.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Dimensions

To determine the junction temperature of the device in the application when heat sinks

are not used, the Thermal Characterization Parameter (Ψ_JT) can be used to determine the

junction temperature with a measurement of the temperature at the top center of the

package case using this equation:

where:

• T_T= thermocouple temperature on top of the package (°C)

• Ψ_JT= thermal characterization parameter (°C/W)

• P_D= power dissipation in the package (W)

The thermal characterization parameter is measured per JESD51-2 specification using a

40 gauge type T thermocouple epoxied to the top center of the package case. The

thermocouple should be positioned so that the thermocouple junction rests on the

package. A small amount of epoxy is placed over the thermocouple junction and over

about 1 mm of wire extending from the junction. The thermocouple wire is placed flat

against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

8 Dimensions

8.1 Obtaining package dimensions

Package dimensions are provided in the package drawings.

To find a package drawing, go to http://www.nxp.com and perform a keyword search for

the drawing’s document number:

Package option

32-pin QFN

Document Number

SOT617-3 ¹

48-pin LQFP

64-pin LQFP

100-pin LQFP

100 MAP BGA

144-pin LQFP

176-pin LQFP

98ASH00962A

98ASS23234W

98ASS23308W

98ASA00802D

98ASS23177W

98ASS23479W

1. 5x5 mm package

NXP Semiconductors

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

Pinouts

9 Pinouts

9.1 Package pinouts and signal descriptions

For package pinouts and signal descriptions, refer to the Reference Manual.

10 Revision History

The following table provides a revision history for this document.

Table 42. Revision History

Rev. No.

Date

Substantial Changes

12 Aug 2016

03 March 2017

Initial release

• Updated descpition of QSPI and Clock interfaces in Key Features section

• Updated figure: High-level architecture diagram for the S32K1xx family

• Updated figure: S32K1xx product series comparison

• Added note in section Determining valid orderable parts

• Updated figure: Ordering information

• In table: Absolute maximum ratings :

• Added footnote to I_{INJPAD_DC}

• Updated min and max value of I_{INJPAD_DC}

• Updated description, max and min values for I_INJSUM

• Updated V_{IN_TRANSIENT}

• In table: Voltage and current operating requirements :

• Renamed V_{SUP_OFF}

• Updated max value of V_{DD_OFF}

• Removed V_INAand V_IN

• Added V_REFHand V_REFL

• Updated footnote "Typical conditions assumes V_DD= V_DDA= V_REFH= 5

V ...

• Removed I_{NJSUM_AF}

• Updated footnotes in table Table 4

• Updated section Power mode transition operating behaviors

• In table: Power consumption

• Added footnote "With PMC_REGSC[CLKBIASDIS] ... "

• Updated conditions for VLPR

• Removed Idd/MHz for S32K144

• Updated numbers for S32K142 and S32K148

• Removed use case footnotes

• In section Modes configuration :

• Replaced table "Modes configuration" with spreadsheet attachment:

'S32K1xx_Power_Modes _Master_configuration_sheet'

• In table: DC electrical specifications at 3.3 V Range :

• Added footnotes to V_ihInput Buffer High Voltage and V_ihInput Buffer

Low Voltage

• Added footnote to High drive port pins

• In table: DC electrical specifications at 5.0 V Range :

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Revision History

Table 42. Revision History

Rev. No.

Date

Substantial Changes

• Added footnotes V_ihInput Buffer High Voltage and V_ihInput Buffer Low

Voltage

• Updated table: AC electrical specifications at 3.3 V range

• Updated table: AC electrical specifications at 5 V range

• In table: Standard input pin capacitance

• Added footnote to Normal run mode (S32K14x series)

• Removed note from 1M ohms Feedback Resistor in figure Oscillator

connections scheme

• In table: External System Oscillator electrical specifications

• Updated typical of I_DDOSCSupply current — low-gain mode (low-power

mode) (HGO=0) 1 for 4 and 8 MHz

• Removed rows for I_{lk_ext}EXTAL/XTAL impedence High-frequency, low-

gain mode (low-power mode) and high-frequency, high-gain mode and

V_EXTAL

• Updated Typ. of R_Slow-gain mode

• Updated description of R_F, R_S, and V_PP

• Removed footnote from R_FFeedback resistor

• Updated footnote for C₁C₂and R_F

• In table: Table 17

• Removed mention of high-frequency

• Added HGO 0, 1 information

• In table: Fast internal RC Oscillator electrical specifications

• Updated F_FIRC

• Updated description of ΔF

• Updated typ and max values of T_JITcycle-to-cycle jitter and T_JITLong

term jitter over 1000 cycles

• Added footnotes to T_JITcycle-to-cycle jitter and T_JITLong term jitter

over 1000 cycles

• Updated naming convention of I_DDFIRCSupply current

• Added footnote to I_DDFIRCSupply current

• Added footnote to column Parameter

• In table: Slow internal RC oscillator (SIRC) electrical specifications

• Removed V_DDSupply current in 2 MHz Mode

• Removed footnote and updated description of ΔF

• Updated footnote to F_SIRCand I_DDSIRC

• In table: SPLL electrical specifications

• Added row for F_{SPLL_REF}PLL Reference

• Updated naming convention throughout the table

• Updated the max value of T_{SPLL_LOCK}Lock detector detection time

• In table: Flash timing specifications — commands

• Added footnotes:

• All command times assumes ...

• For all EEPROM Emulation terms ...

• 'First time' EERAM writes after a POR ...

• Removed footnote 'Assumes 25 MHz or ...'

• Updated Max of t_eewr32bers

• Added parameters t_quickwrand t_quickwrClnup

• In table: Reliability specifications

• Removed Typ. values for all parameters

• Removed footnote 'Typical values represent ... '

• Added footnote 'Any other EEE driver usage ... '

• Updated QuadSPI AC specifications

• Removed topic: Reliability, Safety and Security modules

• In table: 12-bit ADC operating conditions

• Updated V_DDA

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Revision History

Rev. No.

Table 42. Revision History (continued)

Date

Substantial Changes

• Updated values for V_REFHand V_REFLto add refernce to the section

"voltage and current operating requirments" for Min and Max valaues

• Updated footnote to Typ.

• Removed footnote from RAS Analog source resistance

• Updated figure: ADC input impedance equivalency diagram

• In table: 12-bit ADC characteristics (2.7 V to 3 V) (V_REFH= V_DDA, V_REFL

V_SS

)

• Removed rows for V_{TEMP_S}and V_TEMP25

• Updated footnote to Typ.

• In table: 12-bit ADC characteristics (3 V to 5.5 V)(V_REFH= V_DDA, V_REFL

V_SS

)

• Removed rows for V_{TEMP_S}and V_TEMP25

• Removed number for TUE

• Updated footnote to Typ.

• In table: Comparator with 8-bit DAC electrical specifications

• Updated Typ. of I_DDLSSupply current, Low-speed mode

• Updated Typ. of t_DLSBPropagation delay, Low-speed mode

• Updated Typ. of t_DHSSPropagation delay, High-speed mode

• Updated t_DLSSPropagation delay

• Added row for t_DDACInitialization and switching settling time

• Updated footnote

• Updated section LPSPI electrical specifications

• Added section: SAI electrical specifications

• Updated section: Ethernet AC specifications

• Added section: Clockout frequency

• Added section: Trace electrical specifications

• Updated table: Table 40 : Updated numbers for S32K142 and S32K148

• Updated table: Table 41 : Updated numbers for S32K148

• Updated Document number for 32-pin QFN in topic Obtaining package

dimensions

14 March 2017

• In Table 2

• Updated min. value of V_{DD_OFF}

• Added parameter I_{INJSUM_AF}

• Updated Power mode transition operating behaviors

• Updated Power consumption

• Updated footnote to T_{SPLL_LOCK}in SPLL electrical specifications

• In 12-bit ADC electrical characteristics

• Updated table: 12-bit ADC characteristics (2.7 V to 3 V) (VREFH =

VDDA, VREFL = VSS)

• Added typ. value to I_{DDA_ADC}, TUE, DNL, and INL

• Added min. value to SMPLTS

• Removed footnote 'All the parameters in this table ... '

• Updated table: 12-bit ADC characteristics (3 V to 5.5 V) (VREFH =

VDDA, VREFL = VSS)

• Added typ. value to I_{DDA_ADC}

• Removed footnote 'All the parameters in this table ... '

• In Flash timing specifications — commands updated Max. value of t_vfykeyto

33 μs

02 June 2017

• In section: Block diagram, added block diagram for S32K11x series.

• Updated figure: S32K1xx product series comparison.

• In section: Determining valid orderable parts , added reference to

attachement S32K_Part_Numbers.xlsx.

• In section: Ordering information

• Updated figure: Ordering information.

• In Table 1,

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

Revision History

Table 42. Revision History (continued)

Rev. No.

Date

Substantial Changes

• Updated note 'All the limits defined ... '

• Updated parameter 'I_{INJPAD_DC_ABS}', 'V_{IN_DC}', I_{INJSUM_DC_ABS}

• In Table 2,

• Updated parameter I_{INJPAD_DC_OP}and I_{INJSUM_DC_OP}

• In Table 5, updated TBDs for V_{LVR_HYST}, V_{LVD_HYST}, and _{VLVW_HYST}

• In Power mode transition operating behaviors,

• Added VLPR → VLPS

• Added VLPS → VLPR

• Updated TBDs for VLPS → Asynchronous DMA Wakeup, STOP1 →

Asynchronous DMA Wakeup, and STOP2 → Asynchronous DMA

Wakeup

• In Table 7, updated the specifications for S32K144.

• Updated the attachment S32K1xx_Power_Modes _Configuration.xlsx.

• In Table 14, removed C_{IN_A}

• In Table 16,

• Updated specificatins for g_mXOSC

• Removed I_DDOSC

• In Table 18,

• Added parameter ΔF125.

• Removed I_DDFIRC

• In Table 19,

• Added parameter ΔF125.

• Removed I_DDSIRC

• In Table 20, removed I_LPO

• Updated section: Flash memory module (FTFC) electrical specifications

• In section: 12-bit ADC operating conditions,

• Updated TBDs for I_{DDA_ADC}and TUE in Table 27

• Updated TBDs for I_{DDA_ADC}and TUE in Table 28

• In section: QuadSPI AC specifications, updated figure 'QuadSPI output

timing (HyperRAM mode) diagram'.

• In section: 12-bit ADC operating conditions, updated Table 26.

• In section: CMP with 8-bit DAC electrical specifications, added note 'For

comparator IN signals adjacent ... '

• In table: Table 31, minor update in footnote 6.

• In table: Table 40, updated specifications for S32K146.

06 Dec 2017

• Removed S32K148 from 'Caution'

• Updated figure: S32K1xx product series comparison for

• 'EEPROM emulated by FlexRAM' of S32K148 (Added content to

footnote)

• Added support for LIN protocol version 2.2 A

• In Absolute maximum ratings :

• Added note 'Unless otherwise ... '

• Added parameter 'Added note 'T_{ramp_MCU}

• Updated footnote for 'T_ramp

• In Voltage and current operating requirements :

• Added footnote 'V_DDand V_DDAmust be shorted ... ' against parameter

'V_DD– V_DDA

• Updated footnote 'V_DDand V_DDAmust be shorted ...'

• In Power and ground pins

• Added diagrams for 32-QFN and 48-LQFP and footnote below the

diagrams.

• Updated footnote 'V_DDand V_DDAmust be shorted ...'

• In Power mode transition operating behaviors :

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Revision History

Rev. No.

Table 42. Revision History

Date

Substantial Changes

• Added footnote 'For S32K11x – FIRC/SOSC/FIRC/LPO; For S32K14x

– FIRC/SOSC/FIRC/LPO/SPLL' to 'VLPS Mode: All clock sources

disabled'

• Updated numbers for:

• VLPR → VLPS

• VLPS → VLPR

• 'RUN → Compute operation'

• RUN → VLPS

• RUN → VLPR

• In Power consumption :

• Updated specs for S32K142, S32K144, and S32K148

• Updated footnote 'Typical current numbers are indicative ...'

• Updated footnote 'The S32K148 data ...'

• Removed footnote 'Above S32K148 data is preliminary targets only'

• Added new table 'Power consumption at 3.3 V'

• In General AC specifications :

• Updated max value and footnote of WFRST

• Updated symbol for not filtered pulse to 'WNFRST', updated min value,

removed max. value, and added footnote

• Fixed naming conventions to align with DS in DC electrical specifications at

3.3 V Range and DC electrical specifications at 5.0 V Range

• Updated specs for AC electrical specifications at 3.3 V range and AC

electrical specifications at 5 V range

• In Device clock specifications :

• Updated f_BUSto 48 for 11x

• Added footnote to f_BUSfor 14x

• In External System Oscillator frequency specifications :

• Added specs for S32K11x

• Updated 't_{dc_extal}' for S32K14x

• Added footnote 'Frequecies below ... ' to 'f_{ec_extal}' and 't_{dc_extal}

• Splitted Flash timing specifications — commands for S32K14x and S32K11x

• Updated Flash timing specifications — commands for S32K14x

• In Reliability specifications :

• Added footnote 'Data retention period ... ' for 'tnvmretp1k' and

'tnvmretee'

• Minor update in footnote for 'nnvmwree16' 'nnvmwree256'

• In QuadSPI AC specifications :

• Updated 'MCR[SCLKCFG[5]]' value to 0

• Updated 'Data Input Setup Time' HSRUN Internal DQS PAD Loopback

value to 1.6

• Updated 'Data Input Setup Time' DDR External DQS min. value to 2

• Updated 'Data Input Hold Time' DDR External DQS min. value to 20

• Upadted figure 'QuadSPI output timing (SDR mode) diagram' and

'QuadSPI input timing (HyperRAM mode) diagram'

• In 12-bit ADC electrical characteristics :

• Added note 'On reduced pin packages where ... '

• Removed max. value of 'I_{DDA_ADC}

• Added note 'Due to triple ... '

• In 12-bit ADC operating conditions, removed parameter 'ΔV_DDA

• In CMP with 8-bit DAC electrical specifications :

• Updated Typ. and Max. values of 'I_DDLS

• Upadted Typ. value of 't_DHSB

• Updated Typ. value of 'V_HYST1' , 'V_HYST2', and 'V_HYST3

• In LPSPI electrical specifications :

• Updated 'f_periph' and 'f_op', and 't_SPSCK

Table continues on the next page...

S32K1xx Data Sheet, Rev. 6, 01/2018

Preliminary

NXP Semiconductors

Revision History

Table 42. Revision History (continued)

Rev. No.

Date

Substantial Changes

• Updated 3.3 V numbers and added footnote against f_op, t_SU, ans t_Vin

HSRUN Mode

• Added footnote to 't_WSPSCK

• Updated Thermal characteristics for S32K11x

31 Jan 2018

• Changed the representation of ARM trademark throughout.

• Removed S32K142 from 'Caution'

• In 'Key features', added the following note under 'Power management',

'Memory and memory interfaces', and 'Reliability, safety and security':

• No write or erase access to ...

• In High-level architecture diagram for the S32K14x family, added the

following footnote:

• No write or erase access to ...

• In High-level architecture diagram for the S32K11x family :

• Minor editorial update: Fixed the placement of SRAM, under 'Flash

memory controller' block

• Updated figure: S32K1xx product series comparison :

• Updated footnote 1, and added against 'HSRUN' in addition to 'HW

security module (CSEc)' and 'EEPROM emulated by FlexRAM'.

• Updated 'System RAM (including FlexRAM and MTB)' row for

S32K144, S32K146, and S32K148.

• Updated channel count for S32K116 in row '12-bit SAR ADC (1 MSPS

each)'.

• Updated Ordering information

• Updated Flash timing specifications — commands for S32K148, S32K142,

S32K146, S32K116, and S32K118.

S32K1xx Data Sheet, Rev. 6, 01/2018

NXP Semiconductors

Preliminary

How to Reach Us:

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DesignStart, Mali, mbed, NEON, POP, Sensinode, Socrates, ULINK and

Versatile are trademarks of ARM Limited (or its subsidiaries) in the EU and/or

Oracle and/or its affiliates. The Power Architecture and Power.org word marks

and the Power and Power.org logos and related marks are trademarks and

service marks licensed by Power.org.

Document Number S32K1XX

Revision 6, 01/2018

Preliminary

935380028528 [NXP]

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