A2T07D160W04S [NXP]
N--Channel Enhancement--Mode Lateral MOSFET;
| 型号： | A2T07D160W04S |
| 厂家： | 
NXP |
| 描述： | N--Channel Enhancement--Mode Lateral MOSFET |
| 文件： | 总24页 (文件大小：854K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: A2T07D160W04S
Rev. 0, 8/2014
Freescale Semiconductor
Technical Data
RF Power LDMOS Transistor
N--Channel Enhancement--Mode Lateral MOSFET
This 30 W symmetrical Doherty RF power LDMOS transistor is designed for
cellular base station applications requiring very wide instantaneous bandwidth
capability covering the frequency range of 716 to 960 MHz.
A2T07D160W04SR3
780 MHz
Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc,
DQA = 450 mA, VGSB = 1.2 Vdc, Pout = 30 W Avg., Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF.
I
716–960 MHz, 30 W AVG., 28 V
AIRFAST RF POWER LDMOS
TRANSISTOR
G
Output PAR
(dB)
ACPR
(dBc)
ps
D
Frequency
758 MHz
780 MHz
803 MHz
(dB)
22.2
22.1
21.5
(%)
47.7
47.9
48.5
7.3
7.3
7.2
–29.3
–30.1
–31.4
880 MHz
Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc,
IDQA = 450 mA, VGSB = 1.3 Vdc, Pout = 30 W Avg., Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF.
NI--780S--4L
G
Output PAR
(dB)
ACPR
(dBc)
ps
D
Frequency
865 MHz
880 MHz
895 MHz
(dB)
20.5
20.5
20.3
(%)
48.4
48.6
49.2
7.4
7.4
7.3
–31.5
–31.6
–31.6
Carrier
RF /V
3
4
1
2
RF /V
inA GSA
outA DSA
(1)
Features
RF /V
inB GSB
RF /V
outB DSB
Designed for Wide Instantaneous Bandwidth Applications
Greater Negative Gate--Source Voltage Range for Improved Class C
Operation
Able to Withstand Extremely High Output VSWR and Broadband Operating
Conditions
Designed for Digital Predistortion Error Correction Systems
Peaking
(Top View)
Figure 1. Pin Connections
1. Pin connections 1 and 2 are DC coupled
and RF independent.
In Tape and Reel. R3 Suffix = 250 Units, 32 mm Tape Width, 13--inch Reel.
Freescale Semiconductor, Inc., 2014. All rights reserved.
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Vdc
Vdc
Vdc
C
Drain--Source Voltage
V
–0.5, +70
–6.0, +10
32, +0
DSS
Gate--Source Voltage
V
GS
DD
Operating Voltage
V
Storage Temperature Range
Case Operating Temperature Range
T
stg
–65 to +150
–40 to +125
–40 to +225
T
C
C
(1,2)
Operating Junction Temperature Range
T
J
C
CW Operation @ T = 25C
CW
94
W
C
Derate above 25C
0.87
W/C
Table 2. Thermal Characteristics
(2,3)
Characteristic
Symbol
Value
Unit
Thermal Resistance, Junction to Case
R
0.63
C/W
JC
Case Temperature 77C, 30 W W--CDMA, 28 Vdc, I
= 450 mA, V
= 1.2 Vdc, 780 MHz
DQA
GSB
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22--A114)
Machine Model (per EIA/JESD22--A115)
Charge Device Model (per JESD22--C101)
2
A
IV
Table 4. Electrical Characteristics (T = 25C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
(4,5)
Off Characteristics
Zero Gate Voltage Drain Leakage Current
I
I
—
—
—
—
—
—
10
5
Adc
Adc
Adc
DSS
DSS
GSS
(V = 70 Vdc, V = 0 Vdc)
DS
GS
Zero Gate Voltage Drain Leakage Current
(V = 32 Vdc, V = 0 Vdc)
DS
GS
Gate--Source Leakage Current
(V = 5 Vdc, V = 0 Vdc)
I
1
GS
DS
(4,6)
On Characteristics -- Side A
(Carrier)
Gate Threshold Voltage
V
V
1.0
1.7
1.5
2.2
2.0
2.7
0.3
Vdc
Vdc
Vdc
GS(th)
GS(Q)
DS(on)
(V = 10 Vdc, I = 112 Adc)
DS
D
Gate Quiescent Voltage
(V = 28 Vdc, I = 450 mAdc, Measured in Functional Test)
DD
DA
Drain--Source On--Voltage
(V = 10 Vdc, I = 1.12 Adc)
V
0.05
0.14
GS
D
(4,6)
On Characteristics -- Side B
(Peaking)
Gate Threshold Voltage
V
1.0
1.5
0.2
2.0
0.3
Vdc
Vdc
GS(th)
(V = 10 Vdc, I = 112 Adc)
DS
D
Drain--Source On--Voltage
(V = 10 Vdc, I = 1.12 Adc)
V
0.05
DS(on)
GS
D
1. Continuous use at maximum temperature will affect MTTF.
2. MTTF calculator available at http://www.freescale.com/rf. Select Software & Tools/Development Tools/Calculators to access MTTF
calculators by product.
3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf.
Select Documentation/Application Notes -- AN1955.
4. V
and V
must be tied together and powered by a single DC power supply.
DDA
DDB
5. Side A and Side B are tied together for these measurements.
6. Each side of device measured separately.
(continued)
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
2
Table 4. Electrical Characteristics (T = 25C unless otherwise noted) (continued)
A
Characteristic
Symbol
Min
Typ
Max
Unit
(1,2,3)
Functional Tests
(In Freescale Doherty Test Fixture, 50 ohm system) V = 28 Vdc, I
= 450 mA, V
= 1.2 Vdc, P = 30 W Avg.,
DD
DQA
GSB
out
f = 803 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in
3.84 MHz Channel Bandwidth @ 5 MHz Offset.
Power Gain
G
20.2
46.0
6.8
21.5
48.5
7.2
23.2
—
dB
%
ps
D
Drain Efficiency
Output Peak--to--Average Ratio @ 0.01% Probability on CCDF
PAR
—
dB
dBc
Adjacent Channel Power Ratio
ACPR
—
–31.4
–28.0
(3)
Load Mismatch
(In Freescale Doherty Test Fixture, 50 ohm system) I
= 450 mA, V
= 1.2 Vdc, f = 780 MHz
GSB
DQA
VSWR 10:1 at 32 Vdc, 132 W Pulse Output Power
(3 dB Input Overdrive from 85 W Pulse Rated Power)
No Device Degradation
(3)
Typical Performance
(In Freescale Doherty Test Fixture, 50 ohm system) V = 28 Vdc, I
= 450 mA, V = 1.2 Vdc,
GSB
DD
DQA
758 to 803 MHz Bandwidth
P
P
@ 1 dB Compression Point, CW
P1dB
P3dB
—
—
—
79
—
—
—
W
W
out
out
(4)
@ 3 dB Compression Point
186
–18
AM/PM
(Maximum value measured at the P3dB compression point across
the 758–803 MHz frequency range)
VBW Resonance Point
VBW
—
120
—
MHz
res
(IMD Third Order Intermodulation Inflection Point)
Gain Flatness in 45 MHz Bandwidth @ P = 30 W Avg.
G
—
—
0.4
—
—
dB
out
F
Gain Variation over Temperature
G
0.01
dB/C
(–30C to +85C)
Output Power Variation over Temperature
(–30C to +85C)
P1dB
—
0.3
—
dB/C
(5)
1. V
and V
must be tied together and powered by a single DC power supply.
DDB
DDA
2. Part internally matched both on input and output.
3. Measurement made with device in a symmetrical Doherty configuration.
4. P3dB = P
+ 7.0 dB where P
is the average output power measured using an unclipped W--CDMA single--carrier input signal where
avg
avg
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
5. Exceeds recommended operating conditions. See CW operation data in Maximum Ratings table.
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
3
C31
C35
V
DDA
C32
C3
V
GGA
C28
C27
C13
C1
C23
C5
C24
C25
R1
C7
C19
C17
C20
R3
C9
C14
C
P
C10
Z1
C18
C21
C15
C11
C12
C8
R2
C29
C22
C4
C6
C26
C2
C16
C30
V
GGB
C34
V
DDB
C33
D58628
A2T07D160W04S
Rev. 3
C36
--
Note: V
and V
must be tied together and powered by a single DC power supply.
DDB
DDA
Figure 2. A2T07D160W04SR3 Test Circuit Component Layout — 758–803 MHz
Table 5. A2T07D160W04SR3 Test Circuit Component Designations and Values — 758–803 MHz
Part
Description
100 pF Chip Capacitors
Part Number
Manufacturer
ATC
C1, C2, C3, C4, C5, C6
ATC600F101JT250XT
C7, C8
30 pF Chip Capacitors
ATC600F300JT250XT
ATC600F3R3BT250XT
ATC600F4R7BT250XT
ATC600F6R8BT250XT
ATC600F5R6BT250XT
ATC600F3R9BT250XT
ATC600F2R7BT250XT
GRM31CR61H106KA12
GRM31CR72A105KA01L
C5750X7S2A106M230KB
MCRH63V337M13X21--RH
CRCW12062R20JNEA
81A7031--50--5F
ATC
C9, C10, C11, C12
C13, C15
3.3 pF Chip Capacitors
ATC
4.7 pF Chip Capacitors
ATC
C14, C16
6.8 pF Chip Capacitors
ATC
C17, C18
5.6 pF Chip Capacitors
ATC
C19, C20, C21, C22
C23, C24, C25, C26
C27, C30
3.9 pF Chip Capacitors
ATC
2.7 pF Chip Capacitors
ATC
10 F Chip Capacitors
Muruta
Muruta
TDK
C28, C29, C31, C33
C32, C34
1 F Chip Capacitors
10 F Chip Capacitors
C35, C36
330 F, 63 V Electrolytic Capacitors
2.2 , 1/4 W Chip Resistors
50 , 10 W Termination
620–900 MHz Band, 90, 3 dB Hybrid Coupler
Multicomp
Vishay
Florida RF Labs
RN2 Technologies
MTL
R1, R2
R3
Z1
CMX07Q03
PCB
Rogers RO4350B, 0.020, = 3.66
D58628
r
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
4
TYPICAL CHARACTERISTICS — 758–803 MHz
26
25
24
23
22
21
20
19
18
17
16
54
V
= 28 Vdc, P = 30 W (Avg.), I
= 450 mA, V
= 1.2 Vdc
GSB
DD
out
DQA
52
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF
50
D
48
46
G
ps
-- 2 4
-- 2 6
-- 2 8
-- 3 0
-- 3 2
-- 3 4
-- 2
-- 2 . 5
-- 3
PARC
-- 3 . 5
-- 4
ACPR
-- 4 . 5
720
740
760
780
800
820
840
860
880
f, FREQUENCY (MHz)
Figure 3. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 30 Watts Avg.
0
V
V
= 28 Vdc, P = 32 W (PEP), I
= 450 mA
DD
out
DQA
= 1.2 Vdc, Two--Tone Measurements
GSB
-- 1 5
-- 3 0
-- 4 5
-- 6 0
-- 7 5
(f1 + f2)/2 = Center Frequency of 780 MHz
IM3--U
IM3--L
IM5--U
IM5--L
IM7--U
IM7--L
1
10
100
200
TWO--TONE SPACING (MHz)
Figure 4. Intermodulation Distortion Products
versus Two--Tone Spacing
-- 2 0
-- 2 5
-- 3 0
-- 3 5
-- 4 0
-- 4 5
-- 5 0
1
0
23
22.5
22
60
V
= 28 Vdc, I
= 450 mA, V
= 1.2 Vdc
GSB
DD
DQA
f = 780 MHz, Single--Carrier W--CDMA
55
--1 dB = 13.5 W
-- 1
-- 2
50
45
40
35
30
3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
21.5
21
ACPR
-- 3
-- 4
G
ps
--2 dB = 19.9 W
20.5
20
--3 dB = 32.2 W
40
D
PARC
-- 5
10
20
30
50
60
P
, OUTPUT POWER (WATTS)
out
Figure 5. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS — 758–803 MHz
24
60
0
V
= 28 Vdc, I
= 450 mA, V
= 1.2 Vdc
GSB
DD
DQA
Single--Carrier W--CDMA
D
22
20
18
16
14
12
-- 1 0
-- 2 0
-- 3 0
-- 4 0
-- 5 0
-- 6 0
50
40
30
20
10
0
803 MHz
758 MHz 780 MHz
ACPR
803 MHz
780 MHz
758 MHz
780 MHz
803 MHz
758 MHz
G
ps
3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
1
10
100
200
P
, OUTPUT POWER (WATTS) AVG.
out
Figure 6. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
24
Gain
22
20
18
V
P
= 28 Vdc
DD
= 0 dBm
in
I
V
= 450 mA
= 1.2 Vdc
DQA
16
GSB
14
12
600
650
700
750
800
850
900
950
1000
f, FREQUENCY (MHz)
Figure 7. Broadband Frequency Response
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
6
Table 6. Carrier Side Load Pull Performance — Maximum Power Tuning
V
= 28 Vdc, I
= 438 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQA
Max Output Power
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
51.5
53.2
50.0
Gain (dB)
21.1
(dBm)
50.1
(W)
102
112
(MHz)
748
790
806
2.46 – j4.48
3.06 – j5.44
3.32 – j5.90
2.43 + j4.57
2.31 – j4.78
2.02 – j4.88
1.92 – j5.08
–8
–8
–8
3.03 + j5.57
3.30 + j6.00
20.6
50.5
20.2
50.1
103
Max Output Power
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
53.8
56.8
53.3
Gain (dB)
(dBm)
(W)
(MHz)
748
2.46 – j4.48
2.42 + j4.80
2.08 – j5.25
1.94 – j5.25
1.81 – j5.44
18.7
51.3
134
–12
–12
–12
790
806
3.06 – j5.44
3.32 – j5.90
3.04 + j5.81
3.33 + j6.24
18.4
17.9
51.6
51.4
145
137
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Table 7. Carrier Side Load Pull Performance — Maximum Drain Efficiency Tuning
V
= 28 Vdc, I
= 438 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQA
Max Drain Efficiency
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
68.0
69.9
66.9
Gain (dB)
(dBm)
(W)
(MHz)
748
790
806
2.46 – j4.48
3.06 – j5.44
3.32 – j5.90
2.35 + j4.51
8.41 – j2.61
6.20 – j2.16
6.00 – j2.35
24.9
47.4
55
–13
–15
–14
2.96 + j5.51
3.25 + j5.90
24.2
23.9
47.9
47.6
61
58
Max Drain Efficiency
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
71.9
72.7
70.5
Gain (dB)
(dBm)
(W)
(MHz)
748
2.46 – j4.48
2.40 + j4.77
7.65 – j4.43
7.12 – j2.62
6.10 – j3.14
22.5
48.9
78
–18
–21
–19
790
806
3.06 – j5.44
3.32 – j5.90
3.04 + j5.78
3.32 + j6.18
22.4
21.8
48.4
48.8
70
76
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Z
Z
in
Z
load
source
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
7
Table 8. Peaking Side Load Pull Performance — Maximum Power Tuning
V
= 28 Vdc, V
= 1.2 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
GSB
Max Output Power
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
51.7
50.6
50.5
Gain (dB)
16.9
(dBm)
50.0
(W)
99
(MHz)
748
790
806
2.58 – j4.22
2.49 + j4.51
2.39 – j5.81
1.84 – j5.81
1.88 – j5.93
–14
–14
–14
3.29 – j5.33
3.44 – j5.61
3.04 + j5.49
3.33 + j5.94
16.6
50.5
111
16.4
50.3
107
Max Output Power
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
53.5
52.4
53.3
Gain (dB)
(dBm)
(W)
(MHz)
748
2.58 – j4.22
2.51 + j4.76
2.09 – j6.19
1.73 – j6.07
1.81 – j6.16
14.4
51.2
131
–18
–17
–17
790
806
3.29 – j5.33
3.44 – j5.61
3.10 + j5.74
3.40 + j6.19
14.3
14.2
51.5
51.4
142
139
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Table 9. Peaking Side Load Pull Performance — Maximum Drain Efficiency Tuning
V
= 28 Vdc, V
= 1.2 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
GSB
Max Drain Efficiency
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
71.6
72.4
71.4
Gain (dB)
(dBm)
(W)
(MHz)
748
790
806
2.58 – j4.22
2.28 + j4.33
9.57 – j3.66
7.77 – j1.84
7.33 – j2.01
18.8
47.3
54
–21
–20
–18
3.29 – j5.33
3.44 – j5.61
2.80 + j5.22
3.09 + j5.65
18.6
18.4
47.2
47.2
52
53
Max Drain Efficiency
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
72.6
73.8
72.8
Gain (dB)
(dBm)
(W)
(MHz)
748
2.58 – j4.22
2.33 + j4.59
8.90 – j5.28
6.52 – j4.24
6.58 – j4.08
16.6
48.4
69
–24
–22
–21
790
806
3.29 – j5.33
3.44 – j5.61
2.92 + j5.54
3.22 + j5.98
16.6
16.3
49.0
48.9
80
77
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Z
Z
in
Z
load
source
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
8
P1dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 790 MHz
2
0
2
0
-- 2
-- 4
-- 2
-- 4
E
E
46.5
66
64
48.5
47.5
68
49
47
P
2
48
P
2
50
49.5
62
-- 6
-- 8
-- 6
-- 8
60
58
56
54
56
4
4
0
6
8
10
12
0
6
8
10
12
REAL ()
REAL ()
Figure 8. P1dB Load Pull Output Power Contours (dBm)
Figure 9. P1dB Load Pull Efficiency Contours (%)
2
0
2
0
-- 2 0
-- 1 8
-- 1 6
-- 2
-- 4
-- 2
-- 4
E
E
-- 1 4
25
24.5
23.5
P
2
P
24
-- 1 2
22
-- 1 0
23
-- 6
-- 8
-- 6
-- 8
-- 6
-- 8
21
22.5
21.5
-- 4
4
2
4
0
6
8
10
12
0
6
8
10
12
REAL ()
REAL ()
Figure 11. P1dB Load Pull AM/PM Contours ()
Figure 10. P1dB Load Pull Gain Contours (dB)
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
9
P3dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 790 MHz
2
0
2
0
-- 2
-- 4
-- 2
47.5
E
E
48
72
70
-- 4
68
51
P
P
50
49.5
49
66
-- 6
-- 8
-- 6
-- 8
64
50.5
48.5
62
60
56
58
2
4
2
4
0
6
8
10
12
0
6
8
10
12
REAL ()
REAL ()
Figure 12. P3dB Load Pull Output Power Contours (dBm)
Figure 13. P3dB Load Pull Efficiency Contours (%)
2
2
23.5
-- 2 6
0
0
-- 2 4
-- 2 2
23
-- 2
-- 2
E
E
-- 2 0
-- 1 8
-- 4
-- 4
22.5
22
P
P
2
-- 1 6
20
-- 6
-- 8
-- 6
-- 8
-- 1 4
21
21.5
-- 1 2
-- 1 0
19.5 20.5
4
2
4
0
6
8
10
12
0
6
8
10
12
REAL ()
REAL ()
Figure 14. P3dB Load Pull Gain Contours (dB)
Figure 15. P3dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
10
P1dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 790 MHz
2
0
2
0
E
E
-- 2
-- 4
-- 2
-- 4
67
71
72
48.5
49
68
66
69
70
48
50
46.5
65
47
47.5
P
P
-- 6
-- 8
-- 6
-- 8
64
49.5
2
4
2
4
0
6
8
10
12
14
0
6
8
10
12
14
REAL ()
REAL ()
Figure 16. P1dB Load Pull Output Power Contours (dBm)
Figure 17. P1dB Load Pull Efficiency Contours (%)
2
2
-- 2 4
-- 2 6
-- 2 2
0
0
-- 2
-- 4
18
-- 2 0
-- 1 8
E
E
-- 2
-- 4
18.5
-- 1 6
P
P
-- 6
-- 6
-- 8
-- 1 4
18
-- 1 0
-- 1 2
-- 8
2
4
2
4
0
6
8
10
12
14
0
6
8
10
12
14
REAL ()
REAL ()
Figure 18. P1dB Load Pull Gain Contours (dB)
Figure 19. P1dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
11
P3dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 790 MHz
2
0
2
0
68
71
70
67
66
69
-- 2
-- 4
-- 2
47.5
72
-- 4
E
E
73
48
51
-- 6
-- 8
-- 6
-- 8
P
P
50
49
50.5
49.5
48.5
2
4
2
4
0
6
8
10
12
14
0
6
8
10
12
14
REAL ()
REAL ()
Figure 21. P3dB Load Pull Efficiency Contours (%)
Figure 20. P3dB Load Pull Output Power Contours (dBm)
2
2
-- 2 8
-- 2 6
0
0
-- 2
-- 4
16
-- 2 4
-- 2
-- 2 2
16.5
-- 4
E
E
-- 2 0
-- 6
-- 8
-- 6
-- 8
P
P
-- 1 8
16
-- 1 2
-- 1 6
-- 1 4
2
4
2
4
0
6
8
10
12
14
0
6
8
10
12
14
REAL ()
REAL ()
Figure 22. P3dB Load Pull Gain Contours (dB)
Figure 23. P3dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
12
865–895 MHz CHARACTERISTICS
C27
V
DDA
C25
C3
C23
V
GGA
C20
C19
C11
C1
D59371
C17
C5
R1
C7
C15
C13
C14
R3
J1
C9
C8
C
Z1
C10
P
C12
C16
J2
R2
C21
C6
C18
C2
C22
J3
C24
V
GGB
C26
C4
V
DDB
A2T07D160W04S
865–895 MHz
Rev. 1
C28
--
Note: V
and V
must be tied together and powered by a single DC power supply.
DDB
DDA
Figure 24. A2T07D160W04SR3 Test Circuit Component Layout — 865–895 MHz
Table 10. A2T07D160W04SR3 Test Circuit Component Designations and Values — 865–895 MHz
Part
Description
100 pF Chip Capacitors
Part Number
Manufacturer
ATC
C1, C2, C3, C4, C5, C6
ATC600F101JT250XT
C7, C8
30 pF Chip Capacitors
ATC600F300JT250XT
ATC600F3R3BT250XT
ATC600F4R7BT250XT
ATC600F5R6BT250XT
ATC600F2R7BT250XT
GRM31CR61H106KA12
GRM31CR72A105KA01L
C5750X7S2A106M230KB
MCRH63V337M13X21--RH
ATC
C9, C10
3.3 pF Chip Capacitors
4.7 pF Chip Capacitors
5.6 pF Chip Capacitors
2.7 pF Chip Capacitors
10 F Chip Capacitors
ATC
C11, C12
C13, C14, C15, C16
C17, C18
C19, C22
C20, C21, C23, C24
C25, C26
C27, C28
J1, J2, J3
R1, R2
ATC
ATC
ATC
Muruta
Muruta
TDK
1 F Chip Capacitors
10 F Chip Capacitors
330 F, 63 V Electrolytic Capacitors
Copper Foil
Multicomp
2.2 , 1/4 W Chip Resistors
50 , 10 W Termination
620–900 MHz Band, 90, 3 dB Hybrid Coupler
CRCW12062R20JNEA
81A7031--50--5F
CMX07Q03
Vishay
R3
Florida RF Labs
RN2 Technologies
MTL
Z1
PCB
Rogers RO4350B, 0.020, = 3.66
D59371
r
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
13
TYPICAL CHARACTERISTICS — 865–895 MHz
24
54
V
V
= 28 Vdc, P = 30 W (Avg.) I
= 450 mA
DD
out
DQA
52
23
22
21
20
19
18
= 1.3 Vdc Single--Carrier W--CDMA
GSB
50
D
48
46
-- 2 8
-- 2 9
-- 3 0
-- 3 1
-- 3 2
-- 3 3
-- 1
3.84 MHz Channel Bandwidth, Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF
G
ps
-- 1 . 8
-- 2 . 6
-- 3 . 4
-- 4 . 2
-- 5
17
16
PARC
ACPR
15
14
820
840
860
880
900
920
940
960
980
f, FREQUENCY (MHz)
Figure 25. Single--Carrier Output Peak--to--Average Ratio
Compression (PARC) Broadband Performance @ Pout = 30 Watts Avg.
26
60
0
D
V
V
= 28 Vdc, I
GSB
= 450 mA
880 MHz
895 MHz
DD
DQA
= 1.3 Vdc
865 MHz
895 MHz
-- 1 0
-- 2 0
-- 3 0
-- 4 0
-- 5 0
-- 6 0
24
22
20
18
16
14
50
40
30
20
10
0
865 MHz
G
865 MHz
ps
880 MHz
880 MHz
895 MHz
Single--Carrier W--CDMA
ACPR
3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
1
10
100
200
P
, OUTPUT POWER (WATTS) AVG.
out
Figure 26. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
22
Gain
20
18
16
V
P
= 28 Vdc
= 0 dBm
DD
in
14
I
= 450 mA
= 1.3 Vdc
DQA
V
GSB
12
10
660
715
770
825
880
935
990
1045
1100
f, FREQUENCY (MHz)
Figure 27. Broadband Frequency Response
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
14
Table 11. Carrier Side Load Pull Performance — Maximum Power Tuning
V
= 28 Vdc, I
= 434 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQA
Max Output Power
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
55.0
55.6
55.3
Gain (dB)
19.8
(dBm)
50.8
(W)
121
122
(MHz)
865
880
895
4.65 – j7.47
5.83 – j8.00
7.11 – j8.39
5.05 + j7.41
1.80 – j5.49
1.80 – j5.61
1.73 – j5.70
–7
–8
–8
5.80 + j7.75
6.76 + j8.03
19.7
50.9
19.5
50.9
123
Max Output Power
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
57.1
58.1
57.4
Gain (dB)
(dBm)
(W)
(MHz)
865
4.65 – j7.47
5.18 + j7.65
1.74 – j5.86
1.75 – j5.96
1.68 – j6.06
17.5
51.8
152
–11
–11
–11
880
895
5.83 – j8.00
7.11 – j8.39
5.97 + j7.98
6.99 + j8.24
17.4
17.1
51.8
51.8
153
153
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Table 12. Carrier Side Load Pull Performance — Maximum Drain Efficiency Tuning
V
= 28 Vdc, I
= 434 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQA
Max Drain Efficiency
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
71.5
70.8
69.3
Gain (dB)
(dBm)
(W)
(MHz)
865
880
895
4.65 – j7.47
5.83 – j8.00
7.11 – j8.39
5.06 + j7.28
4.56 – j2.53
4.21 – j2.63
4.30 – j3.29
23.4
48.0
64
–17
–17
–15
5.83 + j7.61
6.78 + j7.77
23.2
22.9
48.0
48.2
63
65
Max Drain Efficiency
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
74.3
74.2
72.2
Gain (dB)
(dBm)
(W)
(MHz)
865
4.65 – j7.47
5.27 + j7.55
4.99 – j2.61
4.42 – j3.17
3.97 – j3.55
21.5
48.7
74
–23
–22
–22
880
895
5.83 – j8.00
7.11 – j8.39
6.03 + j7.85
7.02 + j8.06
21.0
20.7
49.1
49.3
81
84
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Z
Z
in
Z
load
source
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
15
Table 13. Peaking Side Load Pull Performance — Maximum Power Tuning
V
= 28 Vdc, V
= 1.2 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
GSB
Max Output Power
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
54.9
53.7
55.6
Gain (dB)
16.2
(dBm)
50.8
(W)
120
125
(MHz)
865
880
895
5.24 – j6.88
5.26 + j7.37
1.82 – j6.25
1.64 – j6.44
1.69 – j6.53
–12
–12
–12
6.04 – j7.55
6.85 – j7.68
6.11 + j7.76
7.15 + j8.00
15.9
51.0
15.9
51.0
127
Max Output Power
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
56.6
56.5
57.1
Gain (dB)
(dBm)
(W)
(MHz)
865
5.24 – j6.88
5.49 + j7.64
1.73 – j6.60
1.68 – j6.73
1.62 – j6.79
13.9
51.8
151
–15
–15
–16
880
895
6.04 – j7.55
6.85 – j7.68
6.38 + j8.00
7.52 + j8.23
13.8
13.7
51.9
52.0
154
158
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Table 14. Peaking Side Load Pull Performance — Maximum Drain Efficiency Tuning
V
= 28 Vdc, V
= 1.2 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
GSB
Max Drain Efficiency
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
75.0
74.3
73.3
Gain (dB)
(dBm)
(W)
(MHz)
865
880
895
5.24 – j6.88
4.85 + j7.03
5.19 – j1.71
4.50 – j2.89
4.17 – j3.30
18.0
47.2
52
–23
–21
–21
6.04 – j7.55
6.85 – j7.68
5.64 + j7.43
6.63 + j7.71
17.9
17.6
47.9
48.1
62
64
Max Drain Efficiency
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
76.0
75.6
74.6
Gain (dB)
(dBm)
(W)
(MHz)
865
5.24 – j6.88
5.14 + j7.35
5.55 – j3.10
4.88 – j3.27
3.95 – j4.44
15.9
48.6
72
–25
–26
–24
880
895
6.04 – j7.55
6.85 – j7.68
5.96 + j7.71
7.09 + j8.01
15.8
15.6
48.7
49.6
74
91
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Z
Z
in
Z
load
source
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
16
P1dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 880 MHz
2
0
2
54
58
56
0
68
-- 2
-- 4
-- 6
-- 8
-- 1 0
-- 2
E
E
62 60
70
66
64
-- 4
-- 6
50
49
50.5
56
P
P
49.5
54
47.5
47
48.5
48
-- 8
47
-- 1 0
2
4
2
4
0
6
8
10
0
6
8
10
REAL ()
REAL ()
Figure 28. P1dB Load Pull Output Power Contours (dBm)
Figure 29. P1dB Load Pull Efficiency Contours (%)
2
0
2
-- 2 2
-- 2 0
-- 1 8
0
-- 2
24
-- 1 6
-- 1 4
-- 1 2
-- 1 0
-- 8
-- 2
-- 4
E
E
23.5
-- 4
23
22.5
P
P
-- 6
-- 6
22
21.5
-- 8
-- 1 0
-- 8
20
21
20.5
-- 6
-- 1 0
2
4
2
4
0
6
8
10
0
6
8
10
REAL ()
REAL ()
Figure 30. P1dB Load Pull Gain Contours (dB)
Figure 31. P1dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
17
P3dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 880 MHz
2
0
2
60
0
-- 2
-- 4
-- 6
-- 8
-- 1 0
-- 2
72
70
62
68
66
64
58
E
E
-- 4
-- 6
60
51.5
P
P
50
51 50.5
49.5
49
48.5
48
-- 8
48
-- 1 0
2
4
2
4
0
6
8
10
0
6
8
10
REAL ()
REAL ()
Figure 32. P3dB Load Pull Output Power Contours (dBm)
Figure 33. P3dB Load Pull Efficiency Contours (%)
2
0
2
0
-- 2 6
-- 2 2
-- 2 0
-- 1 8
-- 2 4
22
21.5
-- 2
-- 2
-- 4
-- 6
-- 8
-- 1 0
E
E
-- 4
21
-- 1 6
20.5
-- 1 4
-- 6
-- 8
P
P
-- 1 2
20
19.5
-- 1 0
18
19
18.5
-- 1 0
2
4
2
4
0
6
8
10
0
6
8
10
REAL ()
REAL ()
Figure 34. P3dB Load Pull Gain Contours (dB)
Figure 35. P3dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
18
P1dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 880 MHz
2
0
2
0
-- 2
-- 4
-- 6
-- 8
-- 1 0
-- 2
68
72
E
74
E
70
66
64
-- 4
-- 6
50
62
P
P
50.5
48
49
60
48.5
47.5
47
49.5
58
-- 8
47.5
48
-- 1 0
2
4
2
4
0
6
8
10
0
6
8
10
REAL ()
REAL ()
Figure 36. P1dB Load Pull Output Power Contours (dBm)
Figure 37. P1dB Load Pull Efficiency Contours (%)
2
2
14.5
15
15.5
16
16.5
17
0
-- 2
0
-- 2
17.5
14
-- 2 2
-- 1 2
-- 2 4
-- 1 8
-- 1 6
-- 2 0
E
E
-- 4
-- 4
-- 1 4
-- 6
-- 6
P
P
-- 8
-- 8
-- 1 0
-- 8
-- 1 0
-- 1 0
2
4
2
4
0
6
8
10
0
6
8
10
REAL ()
REAL ()
Figure 38. P1dB Load Pull Gain Contours (dB)
Figure 39. P1dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
19
P3dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 880 MHz
2
0
2
62
64
0
-- 2
-- 4
-- 6
-- 8
-- 1 0
-- 2
72
70
E
E
-- 4
-- 6
74
66
62
64
60
48.5
68
50.5
51
P
P
51.5
49
50
49.5
48
-- 8
49
-- 1 0
2
4
2
4
0
6
8
10
0
6
8
10
REAL ()
REAL ()
Figure 40. P3dB Load Pull Output Power Contours (dBm)
Figure 41. P3dB Load Pull Efficiency Contours (%)
2
2
12.5
13
13.5
14
14.5
15.5
-- 2 8
-- 2 6
-- 2 4
-- 2 2
15
-- 3 0
12
0
-- 2
0
-- 2
-- 2 0
E
E
-- 1 8
-- 1 6
-- 1 4
-- 4
-- 4
-- 6
-- 6
P
P
-- 8
-- 8
-- 1 0
-- 1 0
2
4
2
4
0
6
8
10
0
6
8
10
REAL ()
REAL ()
Figure 42. P3dB Load Pull Gain Contours (dB)
Figure 43. P3dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
20
PACKAGE DIMENSIONS
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
21
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
22
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
Electromigration MTTF Calculator
RF High Power Model
.s2p File
Development Tools
Printed Circuit Boards
For Software and Tools, do a Part Number search at http://www.freescale.com, and select the “Part Number” link. Go to the
Software & Tools tab on the part’s Product Summary page to download the respective tool.
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
Description
0
Aug. 2014
Initial Release of Data Sheet
A2T07D160W04SR3
RF Device Data
Freescale Semiconductor, Inc.
23
Information in this document is provided solely to enable system and software
implementers to use Freescale products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based on the
information in this document.
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Freescale reserves the right to make changes without further notice to any products
herein. Freescale makes no warranty, representation, or guarantee regarding the
suitability of its products for any particular purpose, nor does Freescale assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in Freescale data sheets and/or
specifications can and do vary in different applications, and actual performance may
vary over time. All operating parameters, including “typicals,” must be validated for
each customer application by customer’s technical experts. Freescale does not convey
any license under its patent rights nor the rights of others. Freescale sells products
pursuant to standard terms and conditions of sale, which can be found at the following
address: freescale.com/SalesTermsandConditions.
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast is a trademark of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners.
E 2014 Freescale Semiconductor, Inc.
Document Number: A2T07D160W04S
Rev. 0, 8/2014
相关型号：
©2020 ICPDF网 联系我们和版权申明