A2T09VD300N [NXP]
N--Channel Enhancement--Mode Lateral MOSFET;
| 型号： | A2T09VD300N |
| 厂家： | 
NXP |
| 描述： | N--Channel Enhancement--Mode Lateral MOSFET |
| 文件： | 总19页 (文件大小：598K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: A2T09VD300N
Rev. 0, 8/2015
Freescale Semiconductor
Technical Data
RF Power LDMOS Transistor
N--Channel Enhancement--Mode Lateral MOSFET
This 79 W RF power LDMOS transistor is designed for cellular base station
applications covering the frequency range of 716 to 960 MHz.
A2T09VD300NR1
900 MHz
Typical Single--Carrier W--CDMA Performance: VDD = 48 Vdc,
IDQ(A+B) = 1200 mA, Pout = 79 W Avg., Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF.
716–960 MHz, 79 W AVG., 48 V
AIRFAST RF POWER LDMOS
TRANSISTOR
G
Output PAR
(dB)
ACPR
(dBc)
IRL
(dB)
ps
D
Frequency
920 MHz
940 MHz
960 MHz
(dB)
21.5
21.6
21.5
(%)
34.4
34.7
34.7
7.1
7.0
6.8
–34.6
–33.5
–33.6
–13
–14
–14
TO--270WB--6A
PLASTIC
800 MHz
Typical Single--Carrier W--CDMA Performance: VDD = 48 Vdc,
DQ(A+B) = 1200 mA, Pout = 79 W Avg., Input Signal PAR = 9.9 dB @ 0.01%
I
Probability on CCDF.
G
Output PAR
(dB)
ACPR
(dBc)
IRL
(dB)
ps
D
Frequency
790 MHz
806 MHz
821 MHz
(dB)
21.4
21.6
21.6
(%)
35.3
35.7
36.0
RF /V
1
2
3
6
5
4
RF /V
outA DSA
inA GSA
7.2
7.1
6.9
–35.1
–34.5
–34.3
–18
–19
–16
GND
RF /V
GND
RF /V
outB DSB
inB GSB
Features
Greater Negative Gate--Source Voltage Range for Improved Class C
Operation
Designed for Digital Predistortion Error Correction Systems
Optimized for Doherty Applications
(Top View)
Note: Exposed backside of the package is
the source terminal for the transistors.
Figure 1. Pin Connections
Freescale Semiconductor, Inc., 2015. All rights reserved.
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Vdc
Vdc
Vdc
C
Drain--Source Voltage
V
–0.5, +105
–6.0, +10
55, +0
DSS
Gate--Source Voltage
V
GS
DD
Operating Voltage
V
Storage Temperature Range
Case Operating Temperature Range
Operating Junction Temperature Range
T
stg
–65 to +150
–40 to +150
–40 to +225
T
C
C
(1,2)
T
J
C
Table 2. Thermal Characteristics
(2,3)
Characteristic
Symbol
Value
Unit
Thermal Resistance, Junction to Case
R
0.66
C/W
JC
Case Temperature 98C, 79 W CW, 48 Vdc, I
= 1200 mA, 940 MHz
DQ(A+B)
Table 3. ESD Protection Characteristics
Test Methodology
Human Body Model (per JESD22--A114)
Class
2
A
Machine Model (per EIA/JESD22--A115)
Charge Device Model (per JESD22--C101)
IV
Table 4. Moisture Sensitivity Level
Test Methodology
Rating
Package Peak Temperature
Unit
Per JESD22--A113, IPC/JEDEC J--STD--020
3
260
C
Table 5. Electrical Characteristics (T = 25C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
(4)
Off Characteristics
Zero Gate Voltage Drain Leakage Current
I
I
—
—
—
—
—
—
10
1
Adc
Adc
Adc
DSS
DSS
GSS
(V = 105 Vdc, V = 0 Vdc)
DS
GS
Zero Gate Voltage Drain Leakage Current
(V = 55 Vdc, V = 0 Vdc)
DS
GS
Gate--Source Leakage Current
I
1
(V = 5 Vdc, V = 0 Vdc)
GS
DS
(4)
On Characteristics
Gate Threshold Voltage
(V = 10 Vdc, I = 116 Adc)
V
V
1.3
1.8
2.3
Vdc
GS(th)
DS
D
Gate Quiescent Voltage
(V = 48 Vdc, I
—
2.5
5.0
—
Vdc
Vdc
Vdc
GS(Q)
GG(Q)
DS(on)
= 1200 mAdc)
DQ(A+B)
DS
(5)
Fixture Gate Quiescent Voltage
(V = 48 Vdc, I
V
4.0
0.1
6.0
0.5
= 1200 mAdc, Measured in Functional Test)
DQ(A+B)
DD
Drain--Source On--Voltage
(V = 10 Vdc, I = 1.16 Adc)
V
0.21
GS
D
1. Continuous use at maximum temperature will affect MTTF.
2. MTTF calculator available at http://www.freescale.com/rf/calculators.
3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf and search for AN1955.
4. Each side of device measured separately.
5. V = 2 V
. Parameter measured on Freescale Test Fixture, due to resistor divider network on the board. Refer to Test Fixture Layout.
GG
GS(Q)
(continued)
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
2
Table 5. Electrical Characteristics (T = 25C unless otherwise noted) (continued)
A
Characteristic
Symbol
Min
Typ
Max
Unit
(1,2)
Functional Tests
(In Freescale Test Fixture, 50 ohm system) V = 48 Vdc, I
= 1200 mA, P = 79 W Avg., f = 920 MHz,
DD
DQ(A+B)
out
Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in 3.84 MHz
Channel Bandwidth @ 5 MHz Offset.
Power Gain
G
20.0
31.5
6.6
—
21.5
34.4
7.1
23.0
—
dB
%
ps
D
Drain Efficiency
Output Peak--to--Average Ratio @ 0.01% Probability on CCDF
Adjacent Channel Power Ratio
Input Return Loss
PAR
ACPR
IRL
—
dB
dBc
dB
–34.6
–13
–32.0
–10
—
Load Mismatch (In Freescale Test Fixture, 50 ohm system) I
= 1200 mA, f = 940 MHz, 12 sec(on), 10% Cycle
DQ(A+B)
VSWR 10:1 at 52 Vdc, 420 W Pulsed CW Output Power
No Device Degradation
(3 dB Input Overdrive from 363 W Pulsed CW Rated Power)
Typical Performance (In Freescale Test Fixture, 50 ohm system) V = 48 Vdc, I
= 1200 mA, 920–960 MHz Bandwidth
DQ(A+B)
DD
P
P
@ 1 dB Compression Point, CW
P1dB
—
—
—
250
398
–19
—
—
—
W
W
out
out
(3)
@ 3 dB Compression Point
P3dB
AM/PM
(Maximum value measured at the P3dB compression point across
the 920–960 MHz frequency range)
VBW Resonance Point
VBW
—
90
—
MHz
res
(IMD Third Order Intermodulation Inflection Point)
Gain Flatness in 40 MHz Bandwidth @ P = 79 W Avg.
G
—
—
0.5
—
—
dB
out
F
Gain Variation over Temperature
G
0.012
dB/C
(–30C to +85C)
Output Power Variation over Temperature
P1dB
—
0.001
—
dB/C
(–30C to +85C)
Table 6. Ordering Information
Device
Tape and Reel Information
Package
A2T09VD300NR1
R1 Suffix = 500 Units, 44 mm Tape Width, 13--inch Reel
TO--270WB--6A
1. Part internally input matched.
2. Measurement made with device in single--ended configuration.
3. P3dB = P + 7.0 dB where P is the average output power measured using an unclipped W--CDMA single--carrier input signal where
avg
avg
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
3
A2T09VD300N
Rev. 0
D60035
V
GG
R1
V
DD
C18
C16
R2
R3
C5
C8
C20
C7
C15
C13
C12
C3
C4
C10
C11
C1
C14
C2
C21
C9
C6
R4
C17
C19
Figure 2. A2T09VD300NR1 Test Circuit Component Layout
Table 7. A2T09VD300NR1 Test Circuit Component Designations and Values
Part
Description
3.3 pF Chip Capacitors
Part Number
Manufacturer
ATC
C1, C3, C4
C2
ATC800B3R3BT500XT
ATC800B2R7BT500XT
ATC800B470JT500XT
2.7 pF Chip Capacitor
ATC
C5, C6, C7, C15, C16, C17
47 pF Chip Capacitors
ATC
C8, C9
C10, C11
C12, C13
C14
1 F Chip Capacitors
C5750X7R2A105K230KM
ATC800B150JT500XT
ATC800B3R0BT500XT
ATC800B5R6BT500XT
C5750X7S2A106M230KB
TDK
15 pF Chip Capacitors
ATC
3 pF Chip Capacitors
ATC
5.6 pF Chip Capacitor
ATC
C18, C19
C20, C21
R1, R2
R3, R4
PCB
10 F Chip Capacitors
TDK
220 F, 100 V Electrolytic Capacitors
1000 , 1/4 W Chip Resistors
10 , 1/4 W Chip Resistors
MCGPR100V227M16X26--RH
CRCW12061K00FKEA
CRCW120610R0JNEA
D60035
Multicomp
Vishay
Vishay
MTL
Rogers RO4350B, 0.020, = 3.66
r
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
4
TYPICAL CHARACTERISTICS
45
40
35
30
25
23
22.5
22
V
= 48 Vdc, P = 79 W (Avg.), I
= 1200 mA
DD
out
DQ(A+B)
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
21.5
21
D
G
ps
Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
5
–2.4
–2.6
–2.8
–3
20.5
20
–33
–34
–35
PARC
ACPR
0
–5
–10
–15
–20
19.5
19
–36
–37
IRL
–3.2
–3.4
18.5
18
820
–38
980
840
860
880
900
920
940
960
f, FREQUENCY (MHz)
Figure 3. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 79 Watts Avg.
–10
V
= 48 Vdc, P = 158 W (PEP)
out
DD
I
= 1200 mA, Two--Tone Measurements
DQ(A+B)
(f1 + f2)/2 = Center Frequency of 940 MHz
–20
IM3--U
–30
–40
IM3--L
IM5--U
IM5--L
IM7--U
–50
–60
IM7--L
1
10
100
200
TWO--TONE SPACING (MHz)
Figure 4. Intermodulation Distortion Products
versus Two--Tone Spacing
23.5
23
1
0
45
–25
–30
–35
–40
–45
–50
–55
V
= 48 Vdc, I
= 1200 mA, f = 940 MHz
DD
DQ(A+B)
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
40
35
30
25
20
15
Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
–1
–2
–3
–4
–5
22.5
22
D
–1 dB = 41.9 W
21.5
21
G
ACPR
ps
–2 dB = 59.7 W
–3 dB = 79.1 W
PARC
20.5
20
40
60
80
100
120
P
, OUTPUT POWER (WATTS)
out
Figure 5. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS
60
50
40
30
20
10
0
26
24
22
20
18
16
14
0
V
= 48 Vdc, I
= 1200 mA, Single--Carrier W--CDMA
DD
DQ(A+B)
3.84 MHz Channel Bandwidth, Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
–10
–20
–30
–40
–50
–60
D
G
ps
940 MHz
960 MHz
940 MHz
920 MHz
960 MHz
920 MHz
ACPR
920 MHz
940 MHz
960 MHz
10
, OUTPUT POWER (WATTS) AVG.
1
100
200
P
out
Figure 6. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
26
24
22
20
18
16
14
5
0
V
P
= 48 Vdc
= 0 dBm
DD
in
I
= 1200 mA
DQ(A+B)
–5
Gain
–10
–15
–20
–25
IRL
600
700
800
900
1000 1100 1200 1300 1400
f, FREQUENCY (MHz)
Figure 7. Broadband Frequency Response
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
6
Table 8. Single Side Load Pull Performance — Maximum Power Tuning
V
= 48 Vdc, I = 582 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQ
Max Output Power
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
60.0
60.3
60.3
Gain (dB)
(dBm)
(W)
(MHz)
920
2.52 – j4.77
2.87 – j5.36
3.52 – j5.36
2.79 + j5.52
2.53 + j0.15
2.46 – j0.13
2.24 – j0.21
20.3
53.1
202
–13
–12
–11
940
960
2.92 + j6.17
2.87 + j6.65
20.3
20.3
53.1
53.0
202
200
Max Output Power
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
61.3
61.5
60.8
Gain (dB)
(dBm)
(W)
(MHz)
920
940
960
2.52 – j4.77
2.58 + j5.79
2.76 – j0.03
2.68 – j0.25
2.60 – j0.48
18.1
53.8
239
–18
–17
–16
2.87 – j5.36
3.52 – j5.36
2.68 + j6.48
2.65 + j7.01
18.2
18.1
53.8
53.7
238
236
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Table 9. Single Side Load Pull Performance — Maximum Drain Efficiency Tuning
V
= 48 Vdc, I = 582 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQ
Max Drain Efficiency
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
70.1
70.8
70.2
Gain (dB)
(dBm)
(W)
(MHz)
920
2.52 – j4.77
2.87 – j5.36
3.52 – j5.36
2.43 + j5.57
1.96 + j2.30
1.89 + j2.08
1.83 + j1.71
22.7
50.9
124
–18
–18
–16
940
960
2.56 + j6.19
2.55 + j6.68
22.8
22.4
50.8
51.0
121
125
Max Drain Efficiency
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
71.6
71.5
71.2
Gain (dB)
(dBm)
(W)
(MHz)
920
940
960
2.52 – j4.77
2.37 + j5.85
2.31 + j1.99
2.15 + j1.71
2.02 + j1.46
20.3
52.3
170
–25
–25
–24
2.87 – j5.36
3.52 – j5.36
2.45 + j6.49
2.42 + j7.01
20.3
20.2
52.2
52.2
167
165
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Z
Z
in
Z
load
source
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
7
P1dB – TYPICAL LOAD PULL CONTOURS — 940 MHz
4
3
2
1
0
4
49.5
50.5
49
56
54
58
50
3
51
E
E
2
1
0
51.5
70
64
62
66
52
68
52.5
60
56
P
P
53
54
–1
–2
–1
–2
4
4
1.5
2
2.5
4.5
5
1.5
2
2.5
4.5
5
1
3
3.5
1
3
3.5
REAL ()
REAL ()
Figure 9. P1dB Load Pull Efficiency Contours (%)
Figure 8. P1dB Load Pull Output Power Contours (dBm)
4
4
–10
23
3
3
2
1
0
23.5
22.5
–14
–12
–22
–20
–16
22
E
E
2
1
0
21.5
21
–18
20.5
P
P
20
–1
–2
–1
–2
19.5
4
4
1.5
2
2.5
4.5
5
1.5
2
2.5
4.5
5
1
3
3.5
1
3
3.5
REAL ()
REAL ()
Figure 10. P1dB Load Pull Gain Contours (dB)
Figure 11. P1dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
8
P3dB – TYPICAL LOAD PULL CONTOURS — 940 MHz
4
3
2
1
0
4
56
62
50
50.5
51
51.5
3
2
58
52
E
E
52.5
70
P
68
1
0
66
64
60
53
P
58
56
–1
–2
–1
–2
53.5
51.5
52
4
4
1.5
2
2.5
4.5
5
1.5
2
2.5
4.5
5
1
3
3.5
1
3
3.5
REAL ()
REAL ()
Figure 13. P3dB Load Pull Efficiency Contours (%)
Figure 12. P3dB Load Pull Output Power Contours (dBm)
4
4
21.5
–14
–16
–18
–22
–24
–20
–26
–28
3
3
2
1
0
20.5
19.5
21
20
2
1
0
E
E
19
18.5
18
P
P
–1
–2
–1
–2
17.5
4
1.5
2
2.5
4.5
5
4
1
3
3.5
1.5
2
2.5
4.5
5
1
3
3.5
REAL ()
REAL ()
Figure 14. P3dB Load Pull Gain Contours (dB)
Figure 15. P3dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
9
A2T09VD300N
Rev. 0
D60035
V
GG
R1
V
DD
C18
C16
R2
R3
C5
C8
C20
C7
C22
C13
C3
C15
C24
C10
C11
C1
C14
C12
C4 C23
C2
C21
C9
C6
R4
C17
C19
Figure 16. A2T09VD300NR1 Test Circuit Component Layout — 790–821 MHz
Table 10. A2T09VD300NR1 Test Circuit Component Designations and Values — 790–821 MHz
Part
Description
3.3 pF Chip Capacitors
Part Number
Manufacturer
ATC
C1, C3, C4, C22, C23
ATC800B3R3BT500XT
C2
3.9 pF Chip Capacitor
ATC800B3R9BT500XT
ATC800B470JT500XT
C5750X7R2A105K230KM
ATC800B180JT500XT
ATC800B3R6BT500XT
ATC800B6R8BT500XT
C5750X7S2A106M230KB
MCGPR100V227M16X26--RH
ATC800B0R5BT500XT
CRCW12061K00FKEA
CRCW120610R0JNEA
D60035
ATC
C5, C6, C7, C15, C16, C17
47 pF Chip Capacitors
1 F Chip Capacitors
ATC
C8, C9
C10, C11
C12, C13
C14
TDK
18 pF Chip Capacitors
3.6 pF Chip Capacitors
6.8 pF Chip Capacitor
ATC
ATC
ATC
C18, C19
C20, C21
C24
10 F Chip Capacitors
220 F, 100 V Electrolytic Capacitors
0.5 pF Chip Capacitor
TDK
Multicomp
ATC
R1, R2
R3, R4
PCB
1000 , 1/4 W Chip Resistors
10 , 1/4 W Chip Resistors
Vishay
Vishay
MTL
Rogers RO4350B, 0.020, = 3.66
r
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
10
TYPICAL CHARACTERISTICS — 790–821 MHz
45
26
25
24
23
22
21
20
19
18
17
16
V
= 48 Vdc, P = 79 W (Avg.), I
= 1200 mA
DD
out
DQ(A+B)
40
35
30
25
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
D
Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
G
ps
0
–2
–28
–30
–32
–4
–2.5
–3
PARC
–8
ACPR
–12
–16
–20
–3.5
–4
–34
–36
IRL
–38
–4.5
760 780 800 820 840 860 880 900 920 940 960
f, FREQUENCY (MHz)
Figure 17. Single--Carrier Output Peak--to--Average Ratio
Compression (PARC) Broadband Performance @ Pout = 79 Watts Avg.
60
50
40
30
20
10
0
26
24
22
20
18
16
14
0
V
= 48 Vdc, I
= 1200 mA, Single--Carrier W--CDMA
DD
DQ(A+B)
3.84 MHz Channel Bandwidth, Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
–10
–20
–30
–40
–50
–60
D
G
ps
790 MHz
806 MHz
821 MHz
790 MHz
821 MHz
806 MHz
ACPR
790 MHz
806 MHz
821 MHz
10
1
100
200
P
, OUTPUT POWER (WATTS) AVG.
out
Figure 18. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
24
22
20
18
16
14
12
5
0
V
P
= 48 Vdc
= 0 dBm
DD
in
I
= 1200 mA
DQ(A+B)
Gain
–5
–10
–15
–20
–25
IRL
500
600
700
800
900
1000 1100 1200 1300
f, FREQUENCY (MHz)
Figure 19. Broadband Frequency Response
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
11
Table 11. Single Side Load Pull Performance — Maximum Power Tuning
V
= 48 Vdc, I = 588 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQ
Max Output Power
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
63.7
62.9
63.3
Gain (dB)
(dBm)
(W)
(MHz)
790
3.02 – j2.72
3.29 – j2.85
3.26 – j3.34
2.66 + j3.14
2.84 + j1.14
2.70 + j1.24
2.65 + j1.27
19.9
53.5
223
–10
–11
–11
806
821
2.58 + j3.43
2.47 + j3.75
20.1
20.3
53.4
53.3
218
215
Max Output Power
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
65.9
64.8
64.3
Gain (dB)
(dBm)
(W)
(MHz)
790
806
821
3.02 – j2.72
2.48 + j3.26
2.94 + j1.04
2.99 + j1.01
2.82 + j0.99
17.9
54.1
259
–14
–14
–14
3.29 – j2.85
3.26 – j3.34
2.42 + j3.58
2.31 + j3.89
18.0
18.0
54.1
54.0
255
253
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Table 12. Single Side Load Pull Performance — Maximum Drain Efficiency Tuning
V
= 48 Vdc, I = 588 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQ
Max Drain Efficiency
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
76.2
74.7
74.1
Gain (dB)
(dBm)
(W)
(MHz)
790
3.02 – j2.72
3.29 – j2.85
3.26 – j3.34
2.12 + j3.24
2.51 + j4.27
2.82 + j3.70
2.83 + j3.42
22.9
50.6
115
–17
–15
–15
806
821
2.22 + j3.55
2.19 + j3.86
22.4
22.3
51.5
51.7
141
148
Max Drain Efficiency
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
74.2
74.5
74.8
Gain (dB)
(dBm)
(W)
(MHz)
790
806
821
3.02 – j2.72
2.29 + j3.37
3.54 + j3.22
3.06 + j3.78
2.96 + j3.63
19.7
52.8
189
–18
–20
–21
3.29 – j2.85
3.26 – j3.34
2.14 + j3.73
2.07 + j4.04
20.3
20.4
52.1
52.2
164
165
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Z
Z
in
Z
load
source
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
12
P1dB – TYPICAL LOAD PULL CONTOURS — 806 MHz
6
6
5
58
50
49.5
5
50.5
60
51
74
4
4
51.5
E
E
3
2
3
72
52
70
68
66
64
62
52.5
53
2
60
P
P
1
1
58
0
0
–1
–1
1.5
2
3
3.5
REAL ()
4
4.5
5
5.5
6
1.5
2
3
3.5
REAL ()
4
4.5
5
5.5
6
1
2.5
1
2.5
Figure 21. P1dB Load Pull Efficiency Contours (%)
Figure 20. P1dB Load Pull Output Power Contours (dBm)
6
5
6
5
–18 –16
22.5
22
23.5
23
4
3
4
E
E
–14
21.5
20
3
21
–12
2
2
20.5
–10
P
P
1
1
19.5
0
0
–1
–1
1.5
2
3
3.5
REAL ()
4
4.5
5
5.5
6
1.5
2
3
3.5
REAL ()
4
4.5
5
5.5
6
1
2.5
1
2.5
Figure 22. P1dB Load Pull Gain Contours (dB)
Figure 23. P1dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
13
P3dB – TYPICAL CARRIER LOAD PULL CONTOURS — 806 MHz
7
6
7
6
50.5
51
50
5
5
51.5
52
4
4
E
E
72
52.5
53
74
3
3
2
70
68
66
64
62
2
60
58
1
1
P
P
3
54
53.5
0
0
–1
–1
2
3
4
6
7
2
4
6
7
1
5
1
5
REAL ()
REAL ()
Figure 24. P3dB Load Pull Output Power Contours (dBm)
Figure 25. P3dB Load Pull Efficiency Contours (%)
7
7
–8
–10
19.5
20
20.5
6
5
6
5
–20
–22
–16
21
–14
–18
–12
–24
21.5
4
4
E
E
19
3
3
18.5
18
2
2
1
1
P
P
17.5
0
0
–1
–1
2
3
4
6
7
2
3
4
6
7
1
5
1
5
REAL ()
REAL ()
Figure 26. P3dB Load Pull Gain Contours (dB)
Figure 27. P3dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
14
PACKAGE DIMENSIONS
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
15
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
16
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
17
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
Electromigration MTTF Calculator
RF High Power Model
s2p File
Development Tools
Printed Circuit Boards
To Download Resources Specific to a Given Part Number:
1. Go to http://www.freescale.com/rf
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
Description
0
Aug. 2015
Initial Release of Data Sheet
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
18
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Document Number: A2T09VD300N
Rev. 0, 8/2015
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