A2T09VD250NR1 [NXP]
N--Channel Enhancement--Mode Lateral MOSFET;
| 型号： | A2T09VD250NR1 |
| 厂家： | 
NXP |
| 描述： | N--Channel Enhancement--Mode Lateral MOSFET |
| 文件： | 总19页 (文件大小：631K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: A2T09VD250N
Rev. 0, 8/2015
Freescale Semiconductor
Technical Data
RF Power LDMOS Transistor
N--Channel Enhancement--Mode Lateral MOSFET
This 65 W RF power LDMOS transistor is designed for cellular base station
applications covering the frequency range of 716 to 960 MHz.
A2T09VD250NR1
900 MHz
Typical Single--Carrier W--CDMA Performance: VDD = 48 Vdc,
IDQ(A+B) = 1000 mA, Pout = 65 W Avg., Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF.
716–960 MHz, 65 W AVG., 48 V
AIRFAST RF POWER LDMOS
TRANSISTOR
G
Output PAR
(dB)
ACPR
(dBc)
IRL
(dB)
ps
D
Frequency
920 MHz
940 MHz
960 MHz
(dB)
22.5
22.7
22.4
(%)
34.8
35.4
35.4
7.5
7.4
7.2
–34.4
–34.2
–34.3
–18
–19
–12
800 MHz
Typical Single--Carrier W--CDMA Performance: VDD = 48 Vdc,
DQ(A+B) = 1000 mA, Pout = 65 W Avg., Input Signal PAR = 9.9 dB @ 0.01%
TO--270WB--6A
PLASTIC
I
Probability on CCDF.
G
Output PAR
(dB)
ACPR
(dBc)
IRL
(dB)
ps
D
Frequency
790 MHz
806 MHz
821 MHz
(dB)
23.0
23.1
22.8
(%)
37.3
37.8
37.0
RF /V
1
2
3
6
5
4
RF /V
outA DSA
7.4
7.2
7.0
–33.0
–33.3
–33.8
–15
–19
–13
inA GSA
GND
RF /V
GND
RF /V
outB DSB
inB GSB
Features
Greater Negative Gate--Source Voltage Range for Improved Class C
Operation
(Top View)
Note: Exposed backside of the package is
the source terminal for the transistors.
Designed for Digital Predistortion Error Correction Systems
Optimized for Doherty Applications
Figure 1. Pin Connections
Freescale Semiconductor, Inc., 2015. All rights reserved.
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Vdc
Vdc
Vdc
C
Drain--Source Voltage
V
–0.5, +105
–6.0, +10
55, +0
DSS
Gate--Source Voltage
V
GS
DD
Operating Voltage
V
Storage Temperature Range
Case Operating Temperature Range
Operating Junction Temperature Range
T
stg
–65 to +150
–40 to +150
–40 to +225
T
C
C
(1,2)
T
J
C
Table 2. Thermal Characteristics
(2,3)
Characteristic
Symbol
Value
Unit
Thermal Resistance, Junction to Case
R
0.56
C/W
JC
Case Temperature 82C, 65 W CW, 48 Vdc, I
= 1000 mA, 940 MHz
DQ(A+B)
Table 3. ESD Protection Characteristics
Test Methodology
Human Body Model (per JESD22--A114)
Class
2
A
Machine Model (per EIA/JESD22--A115)
Charge Device Model (per JESD22--C101)
IV
Table 4. Moisture Sensitivity Level
Test Methodology
Rating
Package Peak Temperature
Unit
Per JESD22--A113, IPC/JEDEC J--STD--020
3
260
C
Table 5. Electrical Characteristics (T = 25C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
(4)
Off Characteristics
Zero Gate Voltage Drain Leakage Current
I
I
—
—
—
—
—
—
10
1
Adc
Adc
Adc
DSS
DSS
GSS
(V = 105 Vdc, V = 0 Vdc)
DS
GS
Zero Gate Voltage Drain Leakage Current
(V = 55 Vdc, V = 0 Vdc)
DS
GS
Gate--Source Leakage Current
I
1
(V = 5 Vdc, V = 0 Vdc)
GS
DS
On Characteristics
(4)
Gate Threshold Voltage
(V = 10 Vdc, I = 96 Adc)
V
V
1.3
—
1.8
2.5
2.3
—
Vdc
Vdc
Vdc
Vdc
GS(th)
GS(Q)
GG(Q)
DS(on)
DS
D
(5)
Gate Quiescent Voltage
(V = 48 Vdc, I
= 1000 mAdc)
DQ(A+B)
DS
(5)
Fixture Gate Quiescent Voltage
V
4.0
0.1
5.0
6.0
0.5
(V = 48 Vdc, I
DD
= 1000 mAdc, Measured in Functional Test)
DQ(A+B)
(4)
Drain--Source On--Voltage
V
0.21
(V = 10 Vdc, I = 0.96 Adc)
GS
D
1. Continuous use at maximum temperature will affect MTTF.
2. MTTF calculator available at http://www.freescale.com/rf/calculators.
3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf and search for AN1955.
4. Each side of device measured separately.
5. Side A and Side B are tied together for this measurement.
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
2
Table 5. Electrical Characteristics (T = 25C unless otherwise noted) (continued)
A
Characteristic
Symbol
Min
Typ
Max
Unit
(1)
Functional Tests (In Freescale Test Fixture, 50 ohm system) V = 48 Vdc, I
= 1000 mA, P = 65 W Avg., f = 920 MHz,
DD
DQ(A+B)
out
Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in 3.84 MHz
Channel Bandwidth @ 5 MHz Offset.
Power Gain
G
21.0
31.0
6.8
—
22.5
34.8
7.5
24.0
—
dB
%
ps
D
Drain Efficiency
Output Peak--to--Average Ratio @ 0.01% Probability on CCDF
Adjacent Channel Power Ratio
Input Return Loss
PAR
ACPR
IRL
—
dB
dBc
dB
–34.4
–18
–31.5
–10
—
Load Mismatch (In Freescale Test Fixture, 50 ohm system) I
= 1000 mA, f = 940 MHz, 12 sec(on), 10% Duty Cycle
DQ(A+B)
VSWR 10:1 at 52 Vdc, 363 W Pulsed CW Output Power
No Device Degradation
(3 dB Input Overdrive from 308 W Pulsed CW Rated Power)
Typical Performance (In Freescale Test Fixture, 50 ohm system) V = 48 Vdc, I
= 1000 mA, 920–960 MHz Bandwidth
DQ(A+B)
DD
P
P
@ 1 dB Compression Point, CW
P1dB
—
—
—
240
326
19
—
—
—
W
W
out
out
(2)
@ 3 dB Compression Point
P3dB
AM/PM
(Maximum value measured at the P3dB compression point across
the 920–960 MHz frequency range)
VBW Resonance Point
VBW
—
90
—
MHz
res
(IMD Third Order Intermodulation Inflection Point)
Gain Flatness in 40 MHz Bandwidth @ P = 65 W Avg.
G
—
—
0.3
—
—
dB
out
F
Gain Variation over Temperature
G
0.013
dB/C
(–30C to +85C)
Output Power Variation over Temperature
P1dB
—
0.007
—
dB/C
(–30C to +85C)
Table 6. Ordering Information
Device
Tape and Reel Information
Package
A2T09VD250NR1
R1 Suffix = 500 Units, 44 mm Tape Width, 13--inch Reel
TO--270WB--6A
1. Part internally input matched.
2. P3dB = P
+ 7.0 dB where P
is the average output power measured using an unclipped W--CDMA single--carrier input signal where
avg
avg
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
3
D69443
A2T09VD250N
Rev. 0
V
GG
R1
V
C18
DD
C16
R2
R3
C5
C8
C20
C7
C23*
C3
C4
C15
C13
C10*
C11*
C1
C14
C12
C22*
C2
C21
C9
C6
R4
R6
C17
C19
R5
*C10, C11, C22 and C23 are mounted vertically.
Figure 2. A2T09VD250NR1 Test Circuit Component Layout
Table 7. A2T09VD250NR1 Test Circuit Component Designations and Values
Part
Description
3.3 pF Chip Capacitor
Part Number
Manufacturer
ATC
C1
ATC800B3R3BT500XT
ATC800B2R7BT500XT
ATC800B4R3BT500XT
ATC800B470JT500XT
C3216X7R2A105M160AA
ATC800B120JT500XT
ATC800B5R1BT500XT
ATC800B4R7BT500XT
ATC800B5R6BT500XT
C5750X7S2A106M230KB
EEVFK2A221M
C2
2.7 pF Chip Capacitor
4.3 pF Chip Capacitors
47 pF Chip Capacitors
1 F Chip Capacitors
ATC
C3, C4
ATC
C5, C6, C7, C15, C16, C17
ATC
C8, C9
C10, C11
C12
TDK
12 pF Chip Capacitors
5.1 pF Chip Capacitor
4.7 pF Chip Capacitor
5.6 pF Chip Capacitor
10 F Chip Capacitors
220 F, 100 V Electrolytic Capacitors
1.7 pF Chip Capacitor
1 k, 1/4 W Chip Resistors
10 , 1/4 W Chip Resistors
ATC
ATC
C13
ATC
C14
ATC
C18, C19
C20, C21
C22, C23
R1, R2, R5, R6
R3, R4
PCB
TDK
Panasonic
ATC
ATC800B1R7BT500XT
WCR1206-1KF
Welwyn
Welwyn
MTL
WCR1206-10RF
Rogers RO4350B, 0.020, = 3.66
D69443
r
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
4
TYPICAL CHARACTERISTICS
45
40
35
30
25
28
27
26
25
24
23
22
21
20
19
18
V
= 48 Vdc, P = 65 W (Avg.), I
= 1000 mA
DD
out
DQ(A+B)
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB @ 0.01%
D
Probability on CCDF
5
–2
–33
–34
–35
G
PARC
ps
0
–2.2
–2.4
–2.6
–2.8
–3
ACPR
–5
–10
–15
–20
–36
–37
IRL
–38
980
820
840
860
880
900
920
940
960
f, FREQUENCY (MHz)
Figure 3. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 65 Watts Avg.
–10
V
= 48 Vdc, P = 130 W (PEP)
out
DD
I
= 1000 mA, Two--Tone Measurements
DQ(A+B)
–20
(f1 + f2)/2 = Center Frequency of 940 MHz
IM3--U
IM3--L
–30
–40
IM5--U
IM5--L
IM7--U
IM7--L
–50
–60
1
10
TWO--TONE SPACING (MHz)
100
200
Figure 4. Intermodulation Distortion Products
versus Two--Tone Spacing
23.5
23
1
0
70
–25
–30
–35
–40
–45
–50
–55
V
= 48 Vdc, I
= 1000 mA
DD
DQ(A+B)
f = 940 MHz, Single--Carrier W--CDMA
60
50
40
30
20
10
ACPR
–1
–2
–3
–4
–5
22.5
22
D
–2 dB = 54.5 W
–1 dB = 38.3 W
G
ps
–3 dB = 72.7 W
21.5
21
3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB
PARC
@ 0.01% Probability on CCDF
20.5
20
40
60
80
100
120
P
, OUTPUT POWER (WATTS)
out
Figure 5. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS
60
50
40
30
20
10
0
26
24
22
20
18
16
14
0
V
= 48 Vdc, I
= 1000 mA, Single--Carrier W--CDMA
DD
DQ(A+B)
3.84 MHz Channel Bandwidth, Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
–10
–20
–30
–40
–50
–60
D
G
ps
940 MHz
960 MHz
920 MHz
940 MHz
960 MHz
920 MHz
ACPR
100
920 MHz
940 MHz
960 MHz
10
, OUTPUT POWER (WATTS) AVG.
1
200
P
out
Figure 6. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
26
24
22
20
18
16
14
5
0
Gain
–5
V
P
= 28 Vdc
= 0 dBm
DD
in
–10
I
= 1000 mA
DQ(A+B)
–15
–20
–25
IRL
600
700
800
900
1000 1100 1200 1300 1400
f, FREQUENCY (MHz)
Figure 7. Broadband Frequency Response
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
6
Table 8. Single Side Load Pull Performance — Maximum Power Tuning
V
= 48 Vdc, I = 500 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQ
Max Output Power
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
61.2
61.8
60.3
Gain (dB)
(dBm)
(W)
(MHz)
920
2.52 – j4.76
2.88 – j5.34
3.53 – j5.36
2.19 + j4.75
3.04 + j0.55
2.93 + j0.37
2.87 + j0.07
21.4
52.5
178
–14
–14
–12
940
960
2.22 + j5.10
2.36 + j5.64
21.4
21.3
52.5
52.4
178
174
Max Output Power
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
62.3
62.2
61.5
Gain (dB)
(dBm)
(W)
(MHz)
920
940
960
2.52 – j4.76
2.01 + j5.09
3.37 + j0.34
3.24 + j0.13
3.19 – j0.10
19.4
53.2
208
–20
–19
–18
2.88 – j5.34
3.53 – j5.36
2.06 + j5.48
2.19 + j6.04
19.3
19.2
53.2
53.1
207
204
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Table 9. Single Side Load Pull Performance — Maximum Drain Efficiency Tuning
V
= 48 Vdc, I = 500 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQ
Max Drain Efficiency
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
71.4
71.9
70.9
Gain (dB)
(dBm)
(W)
(MHz)
920
2.52 – j4.76
2.88 – j5.34
3.53 – j5.36
1.87 + j4.79
2.65 + j2.94
2.40 + j2.86
2.32 + j2.45
23.8
50.8
121
–20
–21
–19
940
960
1.85 + j5.18
1.99 + j5.66
24.0
23.7
50.4
50.5
111
112
Max Drain Efficiency
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
72.0
72.1
71.4
Gain (dB)
(dBm)
(W)
(MHz)
920
940
960
2.52 – j4.76
1.83 + j5.10
3.13 + j2.50
2.80 + j2.46
2.65 + j2.16
21.3
52.1
162
–26
–26
–25
2.88 – j5.34
3.53 – j5.36
1.83 + j5.50
1.95 + j6.05
21.5
21.4
51.7
51.7
149
147
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Z
Z
in
Z
load
source
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
7
P1dB – TYPICAL LOAD PULL CONTOURS — 940 MHz
5
4
5
48.5
49.5
49
56
58
60
4
50
50.5
3
3
E
E
51
70
2
2
51.5
68
66
64
62
1
1
52
60
56
58
P
P
0
0
–1
–2
–1
–2
50
1.5
2
3
3.5
REAL ()
4
4.5
5
5.5
6
1
2.5
1.5
2
3
3.5
REAL ()
4
4.5
5
5.5
6
1
2.5
Figure 8. P1dB Load Pull Output Power Contours (dBm)
Figure 9. P1dB Load Pull Efficiency Contours (%)
5
4
5
4
–12
24
24.5
–24
3
2
3
E
E
23.5
23
–22
2
22.5
22
–20
–16
–18
–14
1
1
P
P
21.5
0
0
21
–1
–2
–1
–2
1.5
2
3
3.5
REAL ()
4
4.5
5
5.5
6
1.5
2
3
3.5
REAL ()
4
4.5
5
5.5
6
1
2.5
1
2.5
Figure 10. P1dB Load Pull Gain Contours (dB)
Figure 11. P1dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
8
P3dB – TYPICAL LOAD PULL CONTOURS — 940 MHz
5
4
5
49
49.5
E
50
50.5
56
4
3
51
51.5
3
E
52
70
2
2
1
52.5
68
66
64
1
62
58
60
56
51.5
53
P
P
0
0
–1
–2
–1
–2
51
1.5
2
3
3.5
REAL ()
4
4.5
5
5.5
6
1
2.5
1.5
2
3
3.5
REAL ()
4
4.5
5
5.5
6
1
2.5
Figure 12. P3dB Load Pull Output Power Contours (dBm)
Figure 13. P3dB Load Pull Efficiency Contours (%)
5
5
–32
–16
–26
–28
21.5
21
–24
–20
4
3
4
3
22
22.5
–30
20.5
–18
–22
E
E
2
2
20
1
1
19.5
P
P
0
0
19
18.5
–1
–2
–1
–2
–16
1.5
2
3
3.5
REAL ()
4
4.5
5
5.5
6
1.5
2
3
3.5
REAL ()
4
4.5
5
5.5
6
1
2.5
1
2.5
Figure 14. P3dB Load Pull Gain Contours (dB)
Figure 15. P3dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
9
D69443
A2T09VD250N
Rev. 0
V
GG
R1
V
DD
C18
C16
R2
R3
C5
C8
C20
C7
C22*
C3
C4
C15
C13
C12
C10*
C11*
C1
C14
C2
C23*
C17
C21
C9
C6
R4
R6
C19
R5
*C10, C11, C22 and C23 are mounted vertically.
Figure 16. A2T09VD250NR1 Test Circuit Component Layout — 790–821 MHz
Table 10. A2T09VD250NR1 Test Circuit Component Designations and Values — 790–821 MHz
Part
Description
3.3 pF Chip Capacitor
Part Number
Manufacturer
ATC
C1
C2
ATC800B3R3BT500XT
3.9 pF Chip Capacitor
ATC800B3R9BT500XT
ATC800B6R8BT500XT
ATC800B470JT500XT
C3216X7R2A105M160AA
ATC800B180JT500XT
ATC800B6R2BT500XT
C5750X7S2A106M230KB
EEVFK2A221M
ATC
C3, C4, C13, C14
C5, C6, C7, C15, C16, C17
C8, C9
6.8 pF Chip Capacitors
47 pF Chip Capacitors
1 F Chip Capacitors
ATC
ATC
TDK
C10, C11
18 pF Chip Capacitors
6.2 pF Chip Capacitor
ATC
C12
ATC
C18, C19
10 F Chip Capacitors
220 F, 100 V Electrolytic Capacitors
0.5 pF Chip Capacitors
1 k, 1/4 W Chip Resistors
10 , 1/4 W Chip Resistors
TDK
C20, C21
Panasonic
ATC
C22, C23
ATC800B0R5BT500XT
WCR1206-1KF
R1, R2, R5, R6
R3, R4
Welwyn
Welwyn
MTL
WCR1206-10RF
PCB
Rogers RO4350B, 0.020, = 3.66
D69443
r
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
10
TYPICAL CHARACTERISTICS — 790–821 MHz
45
26
25
24
23
22
21
20
19
18
17
16
V
= 48 Vdc, P = 65 W (Avg.), I
= 1000 mA
DD
out
DQ(A+B)
40
35
30
25
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
D
G
ps
0
–1.5
–2
–32
–33
–34
ACPR
–4
–8
–2.5
–3
–12
–16
–20
PARC
IRL
–35
–36
–3.5
–4
Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
–37
760 780 800 820 840 860 880 900 920 940 960
f, FREQUENCY (MHz)
Figure 17. Single--Carrier Output Peak--to--Average Ratio
Compression (PARC) Broadband Performance @ Pout = 65 Watts Avg.
60
50
40
30
20
10
0
26
24
22
20
18
16
14
0
V
= 48 Vdc, I
= 1000 mA, Single--Carrier W--CDMA
DD
DQ(A+B)
3.84 MHz Channel Bandwidth, Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
–10
–20
–30
–40
–50
–60
D
G
821 MHz
ps
806 MHz
790 MHz
806 MHz
821 MHz
790 MHz
ACPR
100
790 MHz
806 MHz
821 MHz
1
10
, OUTPUT POWER (WATTS) AVG.
200
P
out
Figure 18. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
24
22
20
18
16
14
12
5
0
V
P
= 48 Vdc
= 0 dBm
Gain
DD
in
I
= 1000 mA
DQ(A+B)
–5
–10
–15
–20
–25
IRL
500
600
700
800
900
1000 1100 1200 1300
f, FREQUENCY (MHz)
Figure 19. Broadband Frequency Response
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
11
Table 11. Single Side Load Pull Performance — Maximum Power Tuning
V
= 48 Vdc, I = 501 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQ
Max Output Power
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
64.9
63.4
63.5
Gain (dB)
(dBm)
(W)
(MHz)
790
3.03 – j2.71
3.30 – j2.82
3.27 – j3.34
2.16 + j2.10
3.38 + j1.69
3.29 + j1.70
3.34 + j1.67
21.3
52.8
193
–12
–11
–12
806
821
2.16 + j2.40
2.10 + j2.70
21.3
21.4
52.7
52.7
187
185
Max Output Power
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
65.9
64.6
65.7
Gain (dB)
(dBm)
(W)
(MHz)
790
806
821
3.03 – j2.71
1.99 + j2.30
3.58 + j1.49
3.66 + j1.41
3.67 + j1.47
19.2
53.4
221
–15
–15
–16
3.30 – j2.82
3.27 – j3.34
2.00 + j2.62
1.94 + j2.93
19.2
19.3
53.4
53.3
217
215
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Table 12. Single Side Load Pull Performance — Maximum Drain Efficiency Tuning
V
= 48 Vdc, I = 501 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQ
Max Drain Efficiency
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
75.8
74.9
74.0
Gain (dB)
(dBm)
(W)
(MHz)
790
3.03 – j2.71
3.30 – j2.82
3.27 – j3.34
1.81 + j2.34
3.66 + j5.16
3.53 + j4.98
3.63 + j4.24
24.0
50.5
113
–17
–17
–15
806
821
1.82 + j2.60
1.86 + j2.84
24.0
23.5
50.6
51.2
114
133
Max Drain Efficiency
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
75.2
74.3
73.8
Gain (dB)
(dBm)
(W)
(MHz)
790
806
821
3.03 – j2.71
1.86 + j2.40
4.26 + j3.66
4.19 + j4.15
4.12 + j3.87
21.0
52.5
177
–19
–20
–20
3.30 – j2.82
3.27 – j3.34
1.84 + j2.75
1.81 + j3.04
21.3
21.2
52.1
52.2
161
166
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Z
Z
in
Z
load
source
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
12
P1dB – TYPICAL LOAD PULL CONTOURS — 806 MHz
7
6
7
60
49.5
50
6
49
48.5
62
74
50.5
5
5
4
E
E
51
72
70
4
68
66
51.5
3
3
52
64
2
2
P
P
52.5
60
62
58
1
1
0
0
–1
–1
2
3
4
6
7
2
3
4
6
7
1
5
1
5
REAL ()
REAL ()
Figure 20. P1dB Load Pull Output Power Contours (dBm)
Figure 21. P1dB Load Pull Efficiency Contours (%)
7
7
23.5
25
24
24.5
E
–18
–24
–22
6
5
6
5
–20
–16
–14
E
–12
23
22.5
4
4
3
3
22
2
2
P
P
–10
21.5
21
1
1
0
0
–1
–1
2
3
4
6
7
2
3
4
6
7
1
5
1
5
REAL ()
REAL ()
Figure 22. P1dB Load Pull Gain Contours (dB)
Figure 23. P1dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
13
P3dB – TYPICAL CARRIER LOAD PULL CONTOURS — 806 MHz
8
7
8
49.5
50
7
6
58
50.5
6
51
5
5
51.5
E
E
4
4
70
68
52
52.5
72
3
3
53
66
62
60
58
64
2
2
P
P
1
1
0
0
52
–1
–2
–1
–2
51 51.5
3
4
5
6
7
8
3
4
5
6
7
8
2
2
REAL ()
REAL ()
Figure 24. P3dB Load Pull Output Power Contours (dBm)
Figure 25. P3dB Load Pull Efficiency Contours (%)
8
7
8
7
6
–18
–20
22.5
21.5
22
6
5
–24
–22
5
21
–26
–16
–14
E
E
4
4
20.5
3
3
20
–12
2
2
P
P
19.5
19
1
1
0
0
18.5
–10
–1
–2
–1
–2
3
4
5
6
7
8
3
4
5
6
7
8
2
2
REAL ()
REAL ()
Figure 26. P3dB Load Pull Gain Contours (dB)
Figure 27. P3dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
14
PACKAGE DIMENSIONS
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
15
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
16
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
17
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
Electromigration MTTF Calculator
RF High Power Model
s2p File
Development Tools
Printed Circuit Boards
To Download Resources Specific to a Given Part Number:
1. Go to http://www.freescale.com/rf
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
Description
0
Aug. 2015
Initial Release of Data Sheet
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
18
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Document Number: A2T09VD250N
Rev. 0, 8/2015
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