BF998WR [NXP]
N-channel dual-gate MOS-FET; N沟道双栅极的MOS- FET的
| 型号： | BF998WR |
| 厂家： | 
NXP |
| 描述： | N-channel dual-gate MOS-FET |
| 文件： | 总12页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
BF998WR
N-channel dual-gate MOS-FET
1997 Sep 05
Product specification
Supersedes data of 1995 Apr 25
File under Discrete Semiconductors, SC07
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
FEATURES
PINNING
PIN
• High forward transfer admittance
SYMBOL
DESCRIPTION
• Short channel transistor with high forward transfer
admittance to input capacitance ratio
1
2
3
4
s, b
d
source
drain
• Low noise gain controlled amplifier up to 1 GHz.
g2
g1
gate 2
gate 1
APPLICATIONS
• VHF and UHF applications with 12 V supply voltage,
such as television tuners and professional
communications equipment.
d
3
4
g
2
DESCRIPTION
g
1
Depletion type field-effect transistor in a plastic
microminiature SOT343R package with source and
substrate interconnected. The transistor is protected
against excessive input voltage surges by integrated
back-to-back diodes between gates and source.
2
1
s,b
Top view
MAM198
CAUTION
Marking code: MB.
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
Fig.1 Simplified outline (SOT343R) and symbol.
QUICK REFERENCE DATA
SYMBOL
VDS
PARAMETER
drain-source voltage
CONDITIONS
MIN.
TYP.
MAX.
12
UNIT
−
−
−
−
−
−
−
−
−
−
−
−
V
ID
drain current
30
300
150
−
mA
mW
°C
Ptot
Tj
total power dissipation
operating junction temperature
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
yfs
24
2.1
25
1
mS
pF
Cig1-s
Crs
F
−
f = 1 MHz
f = 800 MHz
−
fF
−
dB
1997 Sep 05
2
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDS
PARAMETER
drain-source voltage
CONDITIONS
MIN.
MAX.
12
UNIT
−
−
−
−
−
V
ID
drain current
30
mA
mA
mA
mW
°C
IG1
IG2
Ptot
Tstg
Tj
gate 1 current
±10
±10
300
+150
+150
gate 2 current
total power dissipation
storage temperature
operating junction temperature
up to Tamb = 45 °C; see Fig.2; note 1
−65
−
°C
Note
1. Device mounted on a printed-circuit board.
MLD154
400
handbook, halfpage
P
tot
(mW)
300
200
100
0
0
50
100
150
200
o
T
( C)
amb
Fig.2 Power derating curve.
1997 Sep 05
3
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
note 1
note 2; Ts = 90 °C
VALUE
UNIT
K/W
K/W
Rth j-a
Rth j-s
thermal resistance from junction to ambient
thermal resistance from junction to soldering point
350
200
Notes
1. Device mounted on a printed-circuit board.
2. Ts is the temperature at the soldering point of the source lead.
STATIC CHARACTERISTICS
Tj = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
gate 1-source breakdown voltage
gate 2-source breakdown voltage
gate 1-source cut-off voltage
gate 2-source cut-off voltage
drain-source current
CONDITIONS
MIN.
MAX. UNIT
V(BR)G1-SS
V(BR)G2-SS
V(P)G1-S
V(P)G2-S
IDSS
VG2-S = VDS = 0; IG1-S = 10 mA
VG1-S = VDS = 0; IG2-S = 10 mA
VG2-S = 4 V; VDS = 8 V; ID = 20 µA
VG1-S = 0; VDS = 8 V; ID = 20 µA
VG2-S = 4 V; VDS = 8 V; VG1-S = 0
VG2-S = VDS = 0; VG1-S = 5 V
VG1-S = VDS = 0; VG2-S = 5 V
6
6
−
−
2
−
−
20
V
20
V
−2.5
−2
V
V
18
mA
nA
nA
IG1-SS
gate 1 cut-off current
50
IG2-SS
gate 2 cut-off current
50
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 °C; VG2-S = 4 V; ID = 10 mA; VDS = 8 V; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
22
TYP.
25
MAX.
UNIT
yfs
Cig1-s
Cig2-s
Cos
Crs
forward transfer admittance pulsed; Tj = 25 °C
input capacitance at gate 1 f = 1 MHz
input capacitance at gate 2 f = 1 MHz
−
mS
pF
pF
pF
fF
−
−
−
−
−
−
2.1
1.2
2.5
−
drain-source capacitance
reverse transfer capacitance f = 1 MHz
noise figure f = 200 MHz; GS = 2 mS; BS = BSopt
f = 800 MHz; GS = 3.3 mS; BS = BSopt
f = 1 MHz
1.05
25
−
−
F
0.6
1
−
dB
dB
−
1997 Sep 05
4
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
MGC470
MGC471
24
24
3 V
V
=
S
G1
V
= 4 V
S
I
I
G2
0.4 V
D
D
2 V
(mA)
(mA)
0.3 V
0.2 V
16
16
1 V
0.1 V
0 V
8
0
8
0
−0.1 V
−0.2 V
−0.3 V
0 V
−0.4 V
−0.5 V
0
2
4
6
8
10
(V)
1
0
1
V
(V)
S
G1
V
DS
VDS = 8 V.
VG2-S = 4 V.
Tamb = 25 °C.
Tamb = 25 °C.
Fig.3 Transfer characteristics; typical values.
Fig.4 Output characteristics; typical values.
MGC473
MGC472
24
30
4 V
fs
y
I
max
typ
D
(mS)
(mS)
24
3 V
2 V
1 V
16
18
12
min
8
6
0
0.5 V
V
= 0 V
8
G2 − S
0
−1600
−1200
−800
−400
0
V
400
(mV)
0
4
12
16
20
(mA)
I
G1
D
VDS = 8 V; VG2 = 4 V; Tamb = 25 °C.
VDS = 8 V; Tamb = 25 °C.
Fig.5 Drain current as a function of gate 1 voltage;
typical values.
Fig.6 Forward transfer admittance as a function
of drain current; typical values.
1997 Sep 05
5
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
MGC474
MGC475
30
1.5
1.4
V
= 4 V
y
G2
S
C
fs
(mS)
24
os
(pF)
3 V
18
12
1.3
1.2
2 V
I
D =
12 mA
1 V
0 V
10 mA
8 mA
6
0
1.1
1.0
−1
0
1
4
6
8
10
12
14
(V)
V
(V)
V
G1-S
DS
VDS = 8 V; Tamb = 25 °C.
VG2-S = 4 V; f = 1 MHz; Tamb = 25 °C.
Fig.7 Forward transfer admittance as a function
of gate 1 voltage; typical values.
Fig.8 Output capacitance as a function of
drain-source voltage; typical values.
MGC476
MGC477
2.4
2.4
C
C
is
is
(pF)
2.2
(pF)
2.3
2.0
1.8
2.2
2.1
2.0
1.6
1.4
−2.4
−1.6
−0.8
0
V
0.8
(mV)
6
4
2
0
−2
V
(V)
G1-S
G2-S
VDS = 8 V; VG2-S = 4 V; f = 1 MHz; Tamb = 25 °C.
VDS = 8 V; VG1-S = 0 V; f = 1 MHz; Tamb = 25 °C.
Fig.9 Gate 1 input capacitance as a function of
gate 1-source voltage; typical values.
Fig.10 Gate 1 input capacitance as a function of
gate 2-source voltage; typical values.
1997 Sep 05
6
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
MGC466
MGC467
3
2
3
10
10
rs
10
y
y
ϕ
is
rs
(deg)
(mS)
(µS)
b
is
ϕ
rs
2
1
10
10
y
rs
1
10
10
10
g
is
2
1
3
10
1
2
3
2
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 8 V; VG2-S = 4 V.
VDS = 8 V; VG2-S = 4 V.
ID = 10 mA; Tamb = 25 °C.
ID = 10 mA; Tamb = 25 °C.
Fig.11 Input admittance as a function of the
frequency; typical values.
Fig.12 Reverse transfer admittance and phase as
a function of frequency; typical values.
MGC468
MGC469
2
2
10
fs
10
10
y
os
y
ϕ
b
os
os
(mS)
fs
y
fs
(deg)
(mS)
1
10
10
ϕ
fs
g
1
2
10
10
1
1
2
3
2
3
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 8 V; VG2-S = 4 V.
D = 10 mA; Tamb = 25 °C.
VDS = 8 V; VG2-S = 4 V.
ID = 10 mA; Tamb = 25 °C.
I
Fig.13 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.14 Output admittance as a function of the
frequency; typical values.
1997 Sep 05
7
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
V
DD
47 µF
1 nF
1 nF
V
20 µH
AGC
1 nF
1 nF
1.8
kΩ
50 Ω
input
L2
47
kΩ
1 nF
C1
5.5 pF
1 nF
360
50 Ω
input
15 pF
L1
10 pF
Ω
140 kΩ
V
1 nF
DD
330
kΩ
D1
BB405
330
kΩ
D2
BB405
100
kΩ
1 nF
1 nF
V
V
tun
input
tun
output
MGC481
VDD = 12 V; GS = 2 mS; GL = 0.5 mS.
L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm.
L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm.
Tapped at approximately half a turn from the cold side, to adjust GL = 0.5 mS. C1 adjusted for GS = 2 mS.
Fig.15 Gain control testcircuit at f = 200 MHz.
1997 Sep 05
8
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
V
V
AGC
V
DD
DD
1 nF
140
1 nF
L4
kΩ
270
kΩ
1 nF
100 kΩ
L3
1 nF
50 Ω
input
L1
C3
0.5-3.5 pF
C4
4-40 pF
1 nF
1 nF
L2
1 nF
50 Ω
MGC480
input
C1
2-18 pF
C2
0.5-3.5 pF
1.8
kΩ
360
Ω
V
DD
VDD = 12 V; GS = 3.3 mS; GL = 1 mS.
L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm.
L2 = 2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane.
L3 = 2 cm, silvered 0.5 mm copper wire, 4 mm above ground plane.
Fig.16 Gain control test circuit at f = 800 MHz.
MGC479
MGC478
0
0
∆G
∆G
tr
(dB)
tr
(dB)
−10
−10
I
=
DSS
max
typ
min
−20
−30
−20
−30
I
=
−40
−50
−40
−50
DSS
max
typ
min
0
2
4
6
8
V
10
(V)
0
2
4
6
8
V
10
(V)
AGC
AGC
VDD = 12 V; f = 200 MHz; Tamb = 25 °C.
VDD = 12 V; f = 800 MHz; Tamb = 25 °C.
Fig.17 Automaticgaincontrolcharacteristics
measured in circuit of Fig.15.
Fig.18 Automatic gain control characteristics
measured in circuit of Fig.16.
1997 Sep 05
9
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
PACKAGE OUTLINE
1.00
max
0.1
max
0.4
0.2
0.2
A
0.2
B
M
M
0.2
3
4
A
1.35
1.15
2.2
2.0
0.3
0.1
2
1
0.25
0.10
0.7
0.5
1.4
1.2
2.2
1.8
B
MSB367
Dimensions in mm.
Fig.19 SOT343R.
1997 Sep 05
10
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
DEFINITIONS
Data Sheet Status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Sep 05
11
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© Philips Electronics N.V. 1997
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
117067/00/02/pp12
Date of release: 1997 Sep 05
Document order number: 9397 750 02671
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