BF998 [NXP]
Silicon N-channel dual-gate MOS-FETs; 硅N沟道双栅MOS- FET的
| 型号： | BF998 |
| 厂家： | 
NXP |
| 描述： | Silicon N-channel dual-gate MOS-FETs |
| 文件： | 总12页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
BF998; BF998R
Silicon N-channel dual-gate
MOS-FETs
Product specification
1996 Aug 01
Supersedes data of April 1991
File under Discrete Semiconductors, SC07
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
FEATURES
• Short channel transistor with high forward transfer
admittance to input capacitance ratio
handbook, halfpage
d
4
3
2
• Low noise gain controlled amplifier up to 1 GHz.
g
2
g
1
APPLICATIONS
• VHF and UHF applications with 12 V supply voltage,
such as television tuners and professional
communications equipment.
1
s,b
Top view
Marking code: MOp.
MAM039
DESCRIPTION
Depletion type field effect transistor in a plastic
microminiature SOT143 or SOT143R package with source
and substrate interconnected. The transistors are
protected against excessive input voltage surges by
integrated back-to-back diodes between gates and
source.
Fig.1 Simplified outline (SOT143)
and symbol; BF998.
d
handbook, age
3
4
CAUTION
g
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
2
g
1
2
1
PINNING
s,b
MAM040
Top view
PIN
SYMBOL
DESCRIPTION
1
2
3
4
s, b
d
source
drain
Marking code: MOp.
Fig.2 Simplified outline (SOT143R)
and symbol; BF998R.
g2
g1
gate 2
gate 1
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
12
UNIT
VDS
ID
drain-source voltage
drain current
−
V
−
30
200
−
mA
mW
mS
pF
Ptot
yfs
total power dissipation
−
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
24
Cig1-s
Crs
F
2.1
25
1
−
f = 1 MHz
f = 800 MHz
−
fF
−
dB
°C
Tj
operating junction temperature
−
150
1996 Aug 01
2
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDS
PARAMETER
drain-source voltage
drain current
CONDITIONS
MIN.
MAX.
12
UNIT
−
−
−
−
−
−
−
V
ID
30
mA
mA
mA
mW
mW
mW
°C
±IG1
±IG2
Ptot
gate 1 current
10
gate 2 current
10
total power dissipation; BF998
up to Tamb = 60 °C; see Fig.3; note 1
up to Tamb = 50 °C; see Fig.3; note 2
200
200
200
+150
150
Ptot
Tstg
Tj
total power dissipation; BF998R up to Tamb = 50 °C; see Fig.4; note 1
storage temperature
−65
operating junction temperature
−
°C
Notes
1. Device mounted on a ceramic substrate, 8 mm × 10 mm × 0.7 mm.
2. Device mounted on a printed-circuit board.
MLA198
MGA002
handbook, halfpage
200
handbook, halfpage
200
(2)
(1)
P
P
tot max
(mW)
tot max
(mW)
100
100
0
0
0
100
200
0
100
200
o
T
(°C)
T
( C)
amb
amb
(1) Ceramic substrate.
(2) Printed-circuit board.
Fig.3 Power derating curves; BF998.
Fig.4 Power derating curve; BF998R.
1996 Aug 01
3
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth j-a
thermal resistance from junction to ambient in free air; BF998 note 1
note 2
460
500
500
K/W
K/W
K/W
Rth j-a
thermal resistance from junction to ambient in free air; BF998R note 1
Notes
1. Device mounted on a ceramic substrate, 8 mm × 10 mm × 0.7 mm.
2. Device mounted on a printed-circuit board.
STATIC CHARACTERISTICS
Tj = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
±V(BR)G1-SS gate 1-source breakdown voltage
±V(BR)G2-SS gate 2-source breakdown voltage
VG2-S = VDS = 0; IG1-SS = ±10 mA
VG1-S = VDS = 0; IG2-SS = ±10 mA
VG2-S = 4 V; VDS = 8 V; ID = 20 µA
VG1-S = 0; VDS = 8 V; ID = 20 µA
VG2-S = 4 V; VDS = 8 V; VG1-S = 0; note 1
VG2-S = VDS = 0; VG1-S = ±5 V
VG1-S = VDS = 0; VG2-S = ±5 V
6
6
−
−
2
−
−
20
20
2.0
1.5
18
50
50
V
V
−V(P)G1-S
−V(P)G2-S
IDSS
gate 1-source cut-off voltage
gate 2-source cut-off voltage
drain-source current
V
V
mA
nA
nA
±IG1-SS
±IG2-SS
gate 1 cut-off current
gate 2 cut-off current
Note
1. Measured under pulse condition.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 °C; VDS = 8 V; VG2-S = 4 V; ID = 10 mA.
SYMBOL
yfs
PARAMETER
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
output capacitance
CONDITIONS
MIN. TYP. MAX. UNIT
f = 1 kHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
21
−
24
−
mS
pF
pF
pF
fF
Cig1-s
Cig2-s
Cos
2.1
1.2
1.05
25
2.5
−
−
−
−
Crs
reverse transfer capacitance
noise figure
−
−
F
f = 200 MHz; GS = 2 mS; BS = BSopt
f = 800 MHz; GS = 3.3 mS; BS = BSopt
−
0.6
1.0
−
dB
dB
−
−
1996 Aug 01
4
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
MGE815
MGE813
24
24
handbook, halfpage
handbook, halfpage
I
I
D
D
3 V
V
=
G1-S
(mA)
(mA)
V
= 4 V
2 V
G2-S
0.4 V
20
20
16
12
8
1 V
0.3 V
0.2 V
16
12
8
0.1 V
0 V
−0.1 V
−0.2 V
−0.3 V
0 V
4
4
−0.4 V
−0.5 V
0
0
−1
0
1
0
2
4
6
8
10
V
(V)
G1
V
(V)
DS
VG2-S = 4 V; Tamb = 25 °C.
VDS = 8 V; Tamb = 25 °C.
Fig.5 Output characteristics; typical values.
Fig.6 Transfer characteristics; typical values.
MGE814
MGE811
24
30
handbook, halfpage
handbook, halfpage
I
D
4 V
3 V
2 V
|y
|
fs
(mS)
24
(mA)
max
typ
20
16
12
8
1 V
18
12
6
min
4
V
= 0 V
0.5 V
G2-S
4
0
0
−1600
−1200
−800
−400
0
(mV)
400
0
8
12
16
(mA)
20
V
G1
I
D
VDS = 8 V; VG2-S = 4 V; Tamb = 25 °C.
VDS = 8 V; Tamb = 25 °C.
Fig.7 Drain current as a function of gate 1
voltage; typical values.
Fig.8 Forward transfer admittance as a function of
drain current; typical values.
1996 Aug 01
5
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
MGE812
MGE810
30
1.5
handbook, halfpage
handbook, halfpage
V
= 4 V
G2-S
C
|y
|
os
(pF)
fs
(mS)
24
1.4
3 V
2 V
18
12
6
1.3
1.2
1.1
12 mA
1 V
0 V
10 mA
8 mA
0
−1
1.0
4
0
1
6
8
10
12
(V)
14
V
(V)
G1
V
DS
VDS = 8 V; Tamb = 25 °C.
VG2-S = 4 V; f = 1 MHz; Tamb = 25 °C.
Fig.9 Forward transfer admittance as a function of
gate 1 voltage; typical values.
Fig.10 Output capacitance as a function of
drain-source voltage; typical values.
MGE809
MBH479
2.3
2.4
handbook, halfpage
handbook, halfpage
C
is
C
is
(pF)
(pF)
2.1
2.3
1.9
1.7
1.5
1.3
2.2
2.1
2.0
−2.4
−1.6
−0.8
0
0.8
(V)
6
4
2
0
−2
(V)
V
V
G2−S
G1-S
VDS = 8 V; VG2-S = 4 V; f = 1 MHz; Tamb = 25 °C.
VDS = 8 V; VG1-S = 0 V; f = 1 MHz; Tamb = 25 °C.
Fig.11 Gate 1 input capacitance as a function of
gate 1-source voltage; typical values.
Fig.12 Gate 1 input capacitance as a function of
gate 2-source voltage; typical values.
1996 Aug 01
6
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
MGC466
MGC467
3
2
3
10
10
rs
10
y
y
ϕ
is
rs
(deg)
(mS)
(µS)
b
is
ϕ
rs
2
1
10
10
y
rs
1
10
10
10
1
g
is
2
10
1
2
3
2
3
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 °C.
VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 °C.
Fig.13 Input admittance as a function of the
frequency; typical values.
Fig.14 Reverse transfer admittance and phase as a
function of frequency; typical values.
MGC468
MGC469
2
2
10
fs
10
10
y
os
y
ϕ
b
os
os
(mS)
fs
y
fs
(deg)
(mS)
1
10
10
ϕ
fs
g
1
2
10
10
1
1
2
3
2
3
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 °C.
VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 °C.
Fig.15 Forward transfer admittance and phase as a
function of frequency; typical values.
Fig.16 Output admittance as a function of the
frequency; typical values.
1996 Aug 01
7
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
V
DD
47 µF
1 nF
1 nF
V
agc
1 nF
20 µH
1 nF
50 Ω
output
1.8 kΩ
47 kΩ
L2
1 nF
C1
5.5 pF
50 Ω
1 nF
360 Ω
input
15 pF
L1
10 pF
140 kΩ
1 nF
D1
BB405
D2
BB405
V
DD
330 kΩ
330 kΩ
100 kΩ
1 nF
1 nF
V
V
tun
tun
input
MGE802
output
VDD = 12 V; GS = 2 mS; GL = 0.5 mS.
L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm.
L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm.
Tapped at approximately half a turn from the cold side, to adjust GL = 0.5 mS. C1 adjusted for GS = 2 mS.
Fig.17 Gain control test circuit at f = 200 MHz.
1996 Aug 01
8
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
V
V
DD
V
agc
DD
1 nF
1 nF
140 kΩ
1 nF
100 kΩ
L4
270 kΩ
L3
1 nF
1 nF
50 Ω
L1
output
L2
1 nF
50 Ω
input
C3
0.5 to
3.5 pF
C4
4 to 40 pF
1 nF
C1
2 to 18 pF
C2
0.5 to 3.5 pF
MGE801
1.8 kΩ
360 Ω
V
DD
VDD = 12 V; GS = 3.3 mS; GL = 1 mS.
L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm.
L2 = 2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane.
L3 = 2 cm, silvered 0.5 mm copper wire, 4 mm above ground plane.
Fig.18 Gain control test circuit at f = 800 MHz.
1996 Aug 01
9
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
MGE807
MGE808
0
0
handbook, halfpage
handbook, halfpage
∆G
∆G
tr
tr
(dB)
I
(dB)
=
DSS
−10
−20
−30
−40
−50
−10
max
typ
min
−20
−30
I
=
DSS
−40
−50
max
typ
min
0
2
4
6
8
10
0
2
4
6
8
10
V
(V)
V
(V)
agc
agc
VDD = 12 V; f = 200 MHz; Tamb = 25 °C.
VDD = 12 V; f = 800 MHz; Tamb = 25 °C.
Fig.19 Automaticgaincontrolcharacteristics
measured in circuit of Fig.17.
Fig.20 Automatic gain control characteristics
measured in circuit of Fig.18.
1996 Aug 01
10
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
PACKAGE OUTLINES
3.0
2.8
0.150
B
1.9
0.090
A
B
M
0.75
0.2
A
0.60
4
3
0.1
max
o
10
max
2.5
max
1.4
1.2
o
10
max
1
2
1.1
max
o
0.1 M
A B
MBC845
30
max
0
0.1
0
0.1
0.88
0.48
1.7
TOP VIEW
Dimensions in mm.
Fig.21 SOT143.
3.0
2.8
B
0.150
0.090
1.9
A
M
0.2
0.40
0.25
A
3
4
0.1
max
o
10
2.5
max
1.4
1.2
max
o
10
max
2
1
1.1
max
0.48
0.38
0.88
0.78
o
MBC844
30
max
1.7
B
0.1 M
TOP VIEW
Dimensions in mm.
Fig.22 SOT143R.
1996 Aug 01
11
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
DEFINITIONS
Data Sheet Status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Aug 01
12
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