BUK563-48C [NXP]
PowerMOS transistor Voltage clamped logic level FET; 功率MOS晶体管钳位电压逻辑电平FET
| 型号： | BUK563-48C |
| 厂家： | 
NXP |
| 描述： | PowerMOS transistor Voltage clamped logic level FET |
| 文件： | 总8页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
PowerMOS transistor
BUK563-48C
Voltage clamped logic level FET
GENERAL DESCRIPTION
QUICK REFERENCE DATA
Protected N-channel enhancement
mode logic level field-effect power
transistor in a plastic envelope
SYMBOL PARAMETER
MIN. TYP. MAX. UNIT
V(CL)DSR
ID
Drain-source clamp voltage
Drain current (DC)
40
48
58
21
V
A
suitable
for
surface
mount
applications.
Ptot
Tj
WDSRR
Total power dissipation
Junction temperature
Repetitive clamped turn off
energy; Tj = 150˚C
Drain-source on-state
resistance; VGS = 5 V
75
175
50
W
˚C
mJ
The device is intended for use in
automotive applications. It has
built-in zener diodes providing active
drain voltage clamping.
RDS(ON)
85
mΩ
PINNING - SOT404
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
d
mb
gate
2
drain
g
3
source
2
tab drain
s
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDG
±VGS
ID
ID
IDM
Drain-source voltage
continuous
continuous
-
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
-
-
-
-
-
-
30
30
15
21
15
84
V
V
V
A
A
A
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak
value)
Ptot
Tstg
Tj
Total power dissipation
Storage temperature
Junction temperature
Tmb = 25 ˚C
-
-
-
75
175
175
W
˚C
˚C
- 55
- 55
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Rth j-mb
Thermal resistance junction to with heatsink compound
heatsink
-
-
2
K/W
Rth j-a
Thermal resistance junction to minimum footprint,
-
50
-
K/W
ambient
FR4 board (see fig. 18)
February 1996
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
BUK563-48C
Voltage clamped logic level FET
STATIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DG
Drain-gate zener voltage
0.2 < -IG < 0.4 mA;
-55˚C < Tj < 150˚C
VDS = VGS; ID = 1 mA
VDS = 10 V; ID = 10 A;
-55˚C < Tj < 150˚C
38
45
54
V
VGS(TO)
VGS(ON)
Gate threshold voltage
Gate voltage
1.0
2.0
1.5
3.1
2.0
4.0
V
V
IDSS
IGSS
RDS(ON)
Zero gate voltage drain current VDS = 30 V; VGS = 0 V; Tj =150 ˚C
-
-
-
0.01
0.1
65
1.0
10
85
mA
µA
mΩ
Gate source leakage current
Drain-source on-state
resistance
VGS = ±15 V; VDS = 0 V; Tj =150 ˚C
VGS = 5 V; ID = 10 A
DYNAMIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(CL)DSR
Drain source clamp voltage
(peak value)
RG = 10 kΩ; ID = 10 A;
-55 < Tj < 150˚C; Inductive load.
40
48
58
V
gfs
Forward transconductance
VDS = 25 V; ID = 10 A
7
12
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
550
240
100
825
350
160
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 12 V; ID = 5 A;
VGS = 5 V; RG = 10 kΩ;
-
-
-
-
3.5
22
16
18
-
-
-
-
µs
µs
µs
µs
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
-
4.5
7.5
-
-
nH
nH
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IDR
Continuous reverse drain
current
-
-
-
21
A
IDRM
VSD
Pulsed reverse drain current
Diode forward voltage
-
-
-
-
84
1.7
A
V
IF = 21 A ; VGS = 0 V
1.3
February 1996
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
BUK563-48C
Voltage clamped logic level FET
CLAMPED ENERGY LIMITING VALUE
SYMBOL PARAMETER
WDSRS Non-repetitive drain-source
CONDITIONS
MIN.
MAX.
UNIT
Tj = 25˚C prior to clamping;
ID = 10 A; VDD < 16 V; VGS = 5 V;
RG = 10 kΩ; inductive load
-
200
mJ
clamped inductive turn off
energy
WDSRR
Drain-source repetitive clamped Tj = 150˚C prior to clamping;
-
50
mJ
inductive turn off energy
ID = 10 A; VDD < 16 V; VGS = 5 V;
RG = 10 kΩ; inductive load
Normalised Power Derating
PD%
Normalised Current Derating
ID%
120
120
110
100
90
80
70
60
50
40
30
20
10
0
110
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80
Tmb /
100 120 140 160 180
C
0
20
40
60
80
100 120 140 160 180
Tmb /
C
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.3. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
ID / A
Zth j-mb / (K/W)
1E+01
1E+00
1E-01
1E-02
100
tp =
10 us
0.5
RDS(ON) = VDS/ID
0.2
0.1
100 us
10
0.05
1 ms
t
p
DC
t
p
P
0.02
D =
D
T
10 ms
100 ms
0
Self-clamped
t
T
1
1E-07
1E-05
1E-03
t / s
1E-01
1E+01
10
VDS / V
1
100
Fig.2. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
February 1996
3
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
BUK563-48C
Voltage clamped logic level FET
ID / A
ID / A
40
30
20
10
0
40
30
20
10
0
VGS / V = 5
10
4.5
4
3.5
3
Tmb / degC =
150
25
2.5
-55
0
2
4
6
8
10
0
1
2
3
4
5
6
7
VDS / V
VGS / V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.8. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V.
gfs / S
RDS(ON) / Ohm
20
15
10
5
0.5
0.4
0.3
0.2
0.1
0
2.5
3
3.5
VGS / V = 4
4.5
5
Tmb / degC =
150
25
-55
10
0
0
10
20
VDS / V
30
40
0
10
20
Id / A
30
40
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
Fig.9. Typical transconductance.
gfs = f(ID); conditions: VDS = 25 V
V(CL)DSR / V
V(CL)DSR / V
Tmb / degC =
51
50
49
48
47
46
45
44
43
58
56
54
52
50
48
46
44
150
25
-55
Tmb / degC =
150
25
-55
1
10
20
2
5
0
2
4
6
8
10
12
ID / A
RG / kOhm
Fig.7. Typical clamping voltage
V(CL)DSR = f(ID) ; conditions: RG = 10 kΩ
Fig.10. Typical clamping voltgage
V(CL)DSR = f(RG) ; conditions: ID = 10 A.
February 1996
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
BUK563-48C
Voltage clamped logic level FET
VGS(TO) / V
a
Normalised RDS(ON) = f(Tj)
2.0
1.5
1.0
0.5
0
max.
2
1
0
typ.
min.
-60
-20
20
60
Tj /
100
140
180
-60
-20
20
60
Tj /
100
140
180
C
C
Fig.11. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 10 A; VGS = 5 V
Fig.14. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
SUB-THRESHOLD CONDUCTION
ID / A
IS / A
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
40
30
20
10
0
Tmb / degC =
150
25
-55
2 %
98 %
typ
0
0.4
0.8
1.2
VGS / V
1.6
2
2.4
0
0.5
1
1.5
VSDS / V
Fig.12. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.15. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
VGS / V
C / pF
30
7
6
5
4
3
2
1
0
2000
1000
500
VDD / V = 12
Ciss
200
Coss
Crss
100
50
0
5
10
QG / nC
15
20
0.01
0.1
1
10
100
VDS / V
Fig.13. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.16. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 10 A; parameter VDS
February 1996
5
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
BUK563-48C
Voltage clamped logic level FET
I,V
VDD
V
(CL)DSR
Load
5 V
t
: adjust for correct Ic
p
V
DS
ID
VGS
t
D.U.T.
P,E
PDS = ID x VDS
RG
E = PDS dt
V
GE
WDSR
Id measure
0V
0R1
t
Fig.17. Inductive clamping test circuit.
Fig.18. Typical Inductive Clamping waveforms
February 1996
6
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
BUK563-48C
Voltage clamped logic level FET
MECHANICAL DATA
Dimensions in mm
4.5 max
1.4 max
10.3 max
Net Mass: 1.4 g
11 max
15.4
2.5
0.85 max
(x2)
0.5
2.54 (x2)
Fig.19. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.20. SOT404 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
February 1996
7
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
BUK563-48C
Voltage clamped logic level FET
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
February 1996
8
Rev 1.000
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