BUK9610-100B [NXP]
TrenchMOS⑩ logic level FET; 的TrenchMOS ™逻辑电平FET
| 型号： | BUK9610-100B |
| 厂家： | 
NXP |
| 描述： | TrenchMOS⑩ logic level FET |
| 文件： | 总16页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BUK95/9610-100B
TrenchMOS™ logic level FET
Rev. 02 — 8 October 2002
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect power transistor in a plastic package using
Philips High-Performance Automotive TrenchMOS™ technology.
Product availability:
BUK9510-100B in SOT78 (TO-220AB)
BUK9610-100B in SOT404 (D2-PAK).
1.2 Features
■ Very low on-state resistance
■ 175 °C rated
■ Q101 compliant
■ Logic level compatible.
1.3 Applications
■ Automotive systems
■ 12 V, 24 V, and 42 V loads
■ Motors, lamps and solenoids
■ General purpose power switching.
1.4 Quick reference data
■ EDS(AL)S ≤ 629 mJ
■ ID ≤ 75 A
■ RDSon = 8.6 mΩ (typ)
■ Ptot ≤ 300 W.
2. Pinning information
Table 1:
Pinning - SOT78 and SOT404 simplified outlines and symbol
Pin
1
Description
gate (g)
Simplified outline
Symbol
mb
d
mb
[1]
2
drain (d)
3
source (s)
g
mb
mounting base,
connected to
drain (d)
s
MBB076
2
1
3
MBK116
MBK106
1
2 3
SOT78 (TO-220AB)
SOT404 (D2-PAK)
[1] It is not possible to make connection to pin 2 of the SOT404 package.
BUK95/9610-100B
Philips Semiconductors
TrenchMOS™ logic level FET
3. Limiting values
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
100
100
±15
110
75
Unit
V
VDS
VDGR
VGS
ID
drain-source voltage (DC)
-
-
-
-
-
-
-
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
RGS = 20 kΩ
V
V
[1]
[2]
[2]
Tmb = 25 °C; VGS = 5 V;
Figure 2 and 3
A
A
Tmb = 100 °C; VGS = 5 V; Figure 2
75
A
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs;
438
A
Figure 3
Ptot
Tstg
Tj
total power dissipation
storage temperature
junction temperature
Tmb = 25 °C; Figure 1
-
300
W
−55
−55
+175
+175
°C
°C
Source-drain diode
[1]
[2]
IDR
reverse drain current (DC)
Tmb = 25 °C
-
-
-
110
75
A
A
A
IDRM
peak reverse drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs
438
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source avalanche unclamped inductive load; ID = 75 A;
-
629
mJ
energy
VDS ≤ 100 V; VGS = 5 V; RGS = 50 Ω;
starting Tmb = 25 °C
[1] Current is limited by power dissipation chip rating
[2] Continuous current is limited by package
9397 750 10282
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 8 October 2002
2 of 15
BUK95/9610-100B
Philips Semiconductors
TrenchMOS™ logic level FET
03na19
03ng70
120
120
P
Capped at 75 A due to package
I
der
D
(A)
(%)
80
80
40
40
0
0
0
50
100
150
200
(°C)
0
50
100
150
200
(ºC)
T
mb
T
mb
VGS ≥ 5 V
Ptot
Pder
=
× 100%
-----------------------
P
°
tot(25 C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Continuous drain current as a function of
mounting base temperature.
03ng68
3
10
Limit R
DSon
= V /I
DS D
t
= 10 µs
p
I
D
(A)
2
10
10
1
100 µs
1 ms
Capped at 75 A due to package
DC
10 ms
100 ms
2
3
10
1
10
10
V
(V)
DS
Tmb = 25 °C; IDM single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 10282
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 8 October 2002
3 of 15
BUK95/9610-100B
Philips Semiconductors
TrenchMOS™ logic level FET
4. Thermal characteristics
Table 3:
Thermal characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
Rth(j-mb) thermal resistance from junction to
mounting base
Figure 4
-
-
0.5 K/W
Rth(j-a)
thermal resistance from junction to ambient
SOT78
vertical in still air
-
-
60
50
-
-
K/W
K/W
SOT404
mounted on a printed circuit board;
minimum footprint
4.1 Transient thermal impedance
03ng69
1
Z
th(j-mb)
(K/W)
δ = 0.5
-1
0.2
10
0.1
0.05
0.02
-2
10
t
p
P
δ =
T
single shot
t
t
p
T
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
1
t
(s)
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 10282
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 8 October 2002
4 of 15
BUK95/9610-100B
Philips Semiconductors
TrenchMOS™ logic level FET
5. Characteristics
Table 4:
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Static characteristics
V(BR)DSS drain-source breakdown
voltage
Characteristics
Conditions
Min
Typ
Max
Unit
ID = 0.25 mA; VGS = 0 V
Tj = 25 °C
100
89
-
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage ID = 1 mA; VDS = VGS
Figure 9
Tj = 25 °C
;
1.1
0.5
-
1.5
2
V
V
V
Tj = 175 °C
Tj = −55 °C
-
-
-
2.3
IDSS
drain-source leakage current VDS = 100 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
-
-
-
0.02
1
µA
µA
nA
-
500
100
IGSS
gate-source leakage current VGS = ±15 V; VDS = 0 V
2
RDSon
drain-source on-state
resistance
VGS = 5 V; ID = 25 A;
Figure 7 and 8
Tj = 25 °C
-
-
-
-
8.6
-
10
25
11
9.7
mΩ
mΩ
mΩ
mΩ
Tj = 175 °C
VGS = 4.5 V; ID = 25 A
VGS = 10 V; ID = 25 A
-
8.3
Dynamic characteristics
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
VGS = 5 V; VDD = 80 V;
ID = 25 A; Figure 14
-
-
-
-
-
-
-
-
-
-
-
86
-
nC
nC
nC
pF
pF
pF
ns
gate-to-source charge
gate-to-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
16
-
32
-
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Figure 12
8284
676
237
60
11045
811
325
VDD = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG = 10 Ω
-
-
-
-
-
110
250
94
ns
td(off)
tf
turn-off delay time
fall time
ns
ns
Ld
internal drain inductance
from drain lead 6 mm from
package to center of die
4.5
nH
from contact screw on
mounting base to center of
die SOT78
-
-
-
3.5
2.5
7.5
-
-
-
nH
nH
nH
from upper edge of drain
mounting base to center of
die SOT404
Ls
internal source inductance
from source lead to source
bond pad
9397 750 10282
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 8 October 2002
5 of 15
BUK95/9610-100B
Philips Semiconductors
TrenchMOS™ logic level FET
Table 4:
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Source-drain diode
Characteristics…continued
Conditions
Min
Typ
Max
Unit
VSD
source-drain (diode forward) IS = 40 A; VGS = 0 V;
-
0.85
1.2
V
voltage
Figure 15
trr
reverse recovery time
recovered charge
IS = 20 A; dIS/dt = −100 A/µs
VGS = −10 V; VDS = 30 V
-
-
78
-
-
ns
Qr
268
nC
9397 750 10282
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 8 October 2002
6 of 15
BUK95/9610-100B
Philips Semiconductors
TrenchMOS™ logic level FET
03ng65
300
03ng64
10
I
10
D
(A)
4
5
250
200
150
100
50
R
DSon
(mΩ)
9
V
= 3 V
GS
8
7
2.2
0
0
2
4
6
8
10
(V)
0
5
10
15
V
DS
V
(V)
GS
Tj = 25 °C; tp = 300 µs
Tj = 25 °C; ID = 25 A
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Drain-source on-state resistance as a function
of gate-source voltage; typical values.
03ng66
15
03ng41
R
2.5
DSon
(mΩ)
a
2
14
5
10
3.2
4
V
= 3 V
3.4 3.6
GS
13
12
11
10
9
1.5
1
0.5
0
8
0
50
100
150
200
250
300
(A)
-60
0
60
120
180
I
D
T (ºC)
j
Tj = 25 °C
RDSon
a =
----------------------------
RDSon(25 C)
°
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
9397 750 10282
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 8 October 2002
7 of 15
BUK95/9610-100B
Philips Semiconductors
TrenchMOS™ logic level FET
03ng52
03ng53
-1
2.5
10
V
I
GS(th)
(V)
D
(A)
max
-2
2.0
1.5
1.0
0.5
0.0
10
min
typ
max
-3
typ
10
min
-4
-5
-6
10
10
10
-60
0
60
120
180
0
0.5
1
1.5
2
2.5
3
(V)
T (ºC)
j
V
GS
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
03ng67
200
12000
C
(pF)
C
iss
g
(S)
fs
10000
8000
6000
4000
2000
0
150
100
50
0
C
C
oss
rss
-1
10
2
10
0
20
40
60
80
1
10
V
(V)
I
(A)
DS
D
Tj = 25 °C; VDS = 25 V
VGS = 0 V; f = 1 MHz
Fig 11. Forward transconductance as a function of
drain current; typical values.
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
9397 750 10282
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 8 October 2002
8 of 15
BUK95/9610-100B
Philips Semiconductors
TrenchMOS™ logic level FET
100
5
I
V
GS
(V)
D
(A)
80
4
3
2
1
0
V
= 14 V
V
= 80 V
DD
DD
60
40
20
T = 175 ºC
j
T = 25 ºC
j
0
0.0
0.5
1.0
1.5
2.0
2.5
V
3.0
(V)
0
20
40
60
80
Q
100
(nC)
G
GS
VDS = 25 V
Tj = 25 °C; ID = 25 A
Fig 13. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
Fig 14. Gate-source voltage as a function of turn-on
gate charge; typical values.
100
I
S
(A)
80
60
40
20
T = 175 ºC
j
T = 25 ºC
j
0
0.0
0.2
0.4
0.6
0.8
V
1.0
(V)
SD
VGS = 0 V
Fig 15. Reverse diode current as a function of reverse diode voltage; typical values.
9397 750 10282
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 8 October 2002
9 of 15
BUK95/9610-100B
Philips Semiconductors
TrenchMOS™ logic level FET
6. Package outline
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
SOT78
E
p
A
A
1
q
mounting
base
D
1
D
(1)
L
L
2
1
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
b
L
max.
(1)
2
e
A
b
D
E
L
D
L
1
A
c
UNIT
p
q
Q
1
1
1
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
15.0
13.5
3.30
2.79
3.8
3.6
3.0
2.7
2.6
2.2
mm
3.0
2.54
Note
1. Terminals in this zone are not tinned.
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SC-46
00-09-07
01-02-16
SOT78
3-lead TO-220AB
Fig 16. SOT78 (TO-220AB).
9397 750 10282
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 8 October 2002
10 of 15
BUK95/9610-100B
Philips Semiconductors
TrenchMOS™ logic level FET
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads
(one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
99-06-25
01-02-12
SOT404
Fig 17. SOT404 (D2-PAK)
9397 750 10282
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 8 October 2002
11 of 15
BUK95/9610-100B
Philips Semiconductors
TrenchMOS™ logic level FET
7. Soldering
10.85
10.60
10.50
1.50
7.50
7.40
1.70
2.15
1.50
2.25
8.275
8.35
8.15
4.60
0.30
4.85
5.40
7.95
8.075
3.00
0.20
1.20
1.30
1.55
solder lands
solder resist
occupied area
solder paste
5.08
MSD057
Dimensions in mm.
Fig 18. Reflow soldering footprint for SOT404.
9397 750 10282
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 8 October 2002
12 of 15
BUK95/9610-100B
Philips Semiconductors
TrenchMOS™ logic level FET
8. Revision history
Table 5:
Revision history
CPCN
Rev Date
Description
02 20021008
-
Product data (9397 750 10282)
Modifications:
• Description in Section 1 changed from:
N-channel enhancement mode field-effect power transistor in a plastic package using
generation three TrenchMOS™ technology, featuring very low on-state resistance.
to:
N-channel enhancement mode field-effect power transistor in a plastic package using
Philips High-Performance Automotive TrenchMOS™ technology.
01 20020409
-
Product data (9397 750 09497)
9397 750 10282
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 8 October 2002
13 of 15
BUK95/9610-100B
Philips Semiconductors
TrenchMOS™ logic level FET
9. Data sheet status
Level Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
10. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
12. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
11. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
14 of 15
9397 750 10282
Product data
Rev. 02 — 8 October 2002
BUK95/9610-100B
Philips Semiconductors
TrenchMOS™ logic level FET
Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
4
4.1
5
6
7
8
9
10
11
12
© Koninklijke Philips Electronics N.V. 2002.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 8 October 2002
Document order number: 9397 750 10282
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
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NXP
BUK9611-55A/T3
TRANSISTOR 75 A, 55 V, 0.012 ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, D2PAK-3, FET General Purpose Power
NXP
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