BUK962R2-40C [NXP]
N-channel TrenchMOS logic level FET; N沟道的TrenchMOS逻辑电平FET
| 型号： | BUK962R2-40C |
| 厂家： | 
NXP |
| 描述： | N-channel TrenchMOS logic level FET |
| 文件： | 总13页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BUK962R2-40C
N-channel TrenchMOS logic level FET
Rev. 02 — 17 April 2008
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
Low conduction losses due to low
Q101 compliant
on-state resistance
Suitable for logic level gate drive
Suitable for thermally demanding
environments due to 175 °C rating
sources
1.3 Applications
12 V loads
Automotive systems
General purpose power switching
Motors, lamps and solenoids
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min Typ Max Unit
VDS
ID
drain-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
-
-
40
V
A
[1][2]
VGS = 5 V; Tj = 25 °C;
100
see Figure 1 and 4
Ptot
total power dissipation Tmb = 25 °C; see Figure 2
-
-
-
-
333
1.2
W
J
Avalanche ruggedness
EDS(AL)S non-repetitive
drain-source
ID = 100 A; Vsup ≤ 40 V;
RGS = 50 Ω; VGS = 5 V;
Tj(init) = 25 °C; unclamped
avalanche energy
Dynamic characteristics
QGD
gate-drain charge
VGS = 5 V; ID = 25 A;
VDS = 32 V; see Figure 14
-
-
73
2
-
nC
Static characteristics
RDSon drain-source on-state
resistance
VGS = 5 V; ID = 25 A;
Tj = 25 °C; see Figure 12, 11
and 13
2.2
mΩ
[1] Continuous current is limited by package.
[2] Refer to document 9397 750 12572 for further information.
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning
Pin
1
Symbol Description
Simplified outline
Graphic symbol
G
D
S
D
gate
D
mb
2
drain
source
3
G
mb
mounting base;
mbb076
S
connected to drain
2
1
3
SOT404 (D2PAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
BUK962R2-40C
D2PAK
plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead SOT404
cropped)
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
40
Unit
V
VDS
VDGR
VGS
ID
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
RGS = 20 kΩ
-
drain-gate voltage
gate-source voltage
drain current
-
40
V
-15
15
V
[1]
[2][3]
[2][3]
Tmb = 25 °C; VGS = 5 V; see Figure 1
VGS = 5 V; Tj = 100 °C; see Figure 1
VGS = 5 V; Tj = 25 °C; see Figure 1 and 4
Tmb = 25 °C; tp ≤ 10 μs; pulsed; see Figure 4
Tmb = 25 °C; see Figure 2
-
280
100
100
1130
333
175
175
A
-
A
-
A
IDM
Ptot
Tstg
Tj
peak drain current
-
A
total power dissipation
storage temperature
junction temperature
-
W
°C
°C
-55
-55
Avalanche ruggedness
EDS(AL)S non-repetitive
ID = 100 A; Vsup ≤ 40 V; RGS = 50 Ω;
VGS = 5 V; Tj(init) = 25 °C; unclamped
-
-
1.2
-
J
J
drain-source avalanche
energy
[4][5]
[6]
EDS(AL)R repetitive drain-source
avalanche energy
see Figure 3
Source-drain diode
[2][3]
IS
source current
Tmb = 25 °C
-
-
100
A
A
ISM
peak source current
tp ≤ 10 μs; pulsed; Tmb = 25 °C
1130
BUK962R2-40C_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 17 April 2008
2 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
[1] Current is limited by chip power dissipation rating.
[2] Continuous current is limited by package.
[3] Refer to document 9397 750 12572 for further information.
[4] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
[5] Repetitive avalanche rating limited by an average junction temperature of 170 °C.
[6] Refer to application note AN10273 for further information.
03na19
003aac288
120
300
ID
P
der
(A)
(%)
80
200
100
0
40
(1)
0
0
50
100
150
200
0
50
100
150
200
T
mb (°C)
T
mb
(°C)
P
tot
V
5V
GS
P
=
× 100 %
der
P
(
)
tot 25°C
(1) Capped at 100 A due to package.
Fig 1. Continuous drain current as a function of
mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
003aac266
103
IAL
(A)
102
10
(1)
(2)
(3)
1
10-1
10-3
10-2
10-1
1
10
AL (ms)
t
(1) Singleípulse;T = 25 °C.
j
(2) Singleípulse;T = 150 °C.
j
(3) Repetitive.
Fig 3. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time
BUK962R2-40C_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 17 April 2008
3 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aac289
104
ID
(A)
Limit RDSon = VDS / ID
103
102
10
1
tp = 10 μs
100 μs
(1)
DC
1 ms
10 ms
100 ms
10-1
10-1
1
10
102
VDS (V)
T
= 25 °C; I
is single pulse
mb
DM
(1) Capped at 100 A due to package.
Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
BUK962R2-40C_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 17 April 2008
4 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance
from junction to
ambient
minimum footprint; mounted on a
printed circuit
-
50
-
K/W
Rth(j-mb)
thermal resistance
from junction to
mounting base
see Figure 5
-
-
0.45
K/W
003aab020
1
Z
th(j-mb)
δ = 0.5
(K/W)
0.2
−1
10
10
10
0.1
0.05
0.02
t
p
−2
−3
P
δ =
T
single shot
t
t
p
T
−6
−5
−4
−3
−2
−1
10
10
10
10
10
10
1
t
p
(s)
Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage
ID = 250 μA; VGS = 0 V;
Tj = 25 °C
40
36
1
-
-
V
ID = 250 μA; VGS = 0 V;
Tj = -55 °C
-
-
V
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C;
1.5
2
V
voltage
see Figure 9 and 10
ID = 1 mA; VDS = VGS
;
-
-
2.3
-
V
Tj = -55 °C; see Figure 9
ID = 1 mA; VDS = VGS
Tj = 175 °C; see Figure 9
;
0.5
-
-
V
IDSS
drain leakage current VDS = 40 V; VGS = 0 V;
-
500
1
μA
μA
Tj = 175 °C
VDS = 40 V; VGS = 0 V; Tj = 25 °C
-
0.02
BUK962R2-40C_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 17 April 2008
5 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
Table 6.
Symbol
IGSS
Characteristics …continued
Parameter Conditions
Min
Typ
2
Max
100
100
Unit
nA
gate leakage current VDS = 0 V; VGS = 15 V; Tj = 25 °C
-
-
VDS = 0 V; VGS = -15 V;
2
nA
Tj = 25 °C
RDSon
drain-source on-state VGS = 4.5 V; ID = 25 A; Tj = 25 °C
-
-
-
-
2.45
1.9
mΩ
mΩ
mΩ
resistance
VGS = 10 V; ID = 25 A; Tj = 25 °C
1.6
-
VGS = 5 V; ID = 25 A; Tj = 175 °C;
4.2
see Figure 11
VGS = 5 V; ID = 25 A; Tj = 25 °C;
see Figure 12, 11 and 13
-
-
2
2.2
1.2
mΩ
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
0.85
V
see Figure 16
trr
reverse recovery time IS = 25 A; dIS/dt = 100 A/μs;
-
-
70
60
-
-
ns
VGS = 0 V; VDS = 30 V
Qr
recovered charge
nC
Dynamic characteristics
QG(tot)
QGS
QGD
Ciss
total gate charge
ID = 25 A; VDS = 32 V; VGS = 5 V;
see Figure 14
-
-
-
-
-
-
120
30
-
nC
nC
nC
pF
pF
pF
gate-source charge
gate-drain charge
input capacitance
output capacitance
-
73
-
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Tj = 25 °C;
see Figure 15
12487
1323
938
16700
1600
1290
Coss
Crss
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG(ext) = 10 Ω
-
-
-
-
-
130
310
380
250
2.5
-
-
-
-
-
ns
ns
ns
ns
nH
turn-off delay time
fall time
LD
internal drain
inductance
from upper edge of drain
mounting base to centre of die
LS
internal source
inductance
from source lead to source bond
pad
-
7.5
-
nH
BUK962R2-40C_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 17 April 2008
6 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aac256
003aac253
240
300
gfs
ID
(S)
(A)
180
120
60
200
100
0
Tj = 175 °C
25 °C
0
0
20
40
60
0
2
4
V
GS (V)
ID (A)
T = 25 °C;V = 25V
V
= 25V
j
DS
DS
Fig 6. Forward transconductance as a function of
drain current; typical values
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
03aa33
003aac252
2.5
300
VGS(th)
(V)
ID
VGS (V) = 10
3.8
3.6
(A)
2
max
200
100
0
3.2
1.5
1
typ
3
min
2.8
0.5
0
2.6
2.4
-60
0
60
120
180
0
1
2
3
4
5
V
DS (V)
T ( C)
°
j
T = 25 °C
I
= 1 mA;V = V
GS
j
D
DS
Fig 8. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 9. Gate-source threshold voltage as a function of
junction temperature
BUK962R2-40C_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 17 April 2008
7 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa36
03aa27
10-1
ID
2
a
(A)
10-2
1.5
10-3
min
typ
max
1
10-4
10-5
10-6
0.5
0
0
1
2
3
-60
0
60
120
180
T ( C)
°
j
VGS (V)
R
DSon
T = 25 °C;V = V
GS
j
DS
a =
R
(
)
DSon 25°C
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
Fig 11. Normalized drain-source on-state resistance
factor as a function of junction temperature
003aac287
003aac286
6
10
RDSon
VGS (V) = 2.8
RDSon
(mΩ)
8
(mΩ)
3
3.2
5
4
3
2
1
6
4
2
0
3.6
3.8
10
0
5
10
15
0
50
100
150
200
250
VGS (V)
I
D (A)
T = 25 °C
T = 25 °C; I = 25 A
j D
j
Fig 12. Drain-source on-state resistance as a function
of drain current; typical values
Fig 13. Drain-source on-state resistance as a function
of gate-source voltage; typical values
BUK962R2-40C_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 17 April 2008
8 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aac254
003aac255
24000
C
(pF)
10
VGS
(V)
20000
VDS = 14 V
Ciss
8
6
4
2
0
32 V
16000
12000
8000
4000
0
Coss
Crss
10-1
1
10
102
0
50
100
150
200
VDS (V)
Q
G (nC)
T = 25 °C; I = 25 A
V
= 0V; f = 1 MHz
j
D
GS
Fig 14. Gate-source voltage as a function of gate
charge; typical values
Fig 15. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
003aac261
250
IS
(A)
200
150
100
50
Tj = 175 °C
25 °C
0
0
0.5
1
1.5
V
2
SD (V)
V
= 0V
GS
Fig 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values
BUK962R2-40C_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 17 April 2008
9 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
05-02-11
06-03-16
SOT404
Fig 17. Package outline SOT404 (D2PAK)
BUK962R2-40C_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 17 April 2008
10 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BUK962R2-40C_2
Modifications:
20080417
Product data sheet
-
BUK962R2-40C_1
• Table 6: VDS condition for IDSS corrected.
BUK962R2-40C_1
20080328
product data sheet
-
-
BUK962R2-40C_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 17 April 2008
11 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
BUK962R2-40C_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 17 April 2008
12 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
General description . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits. . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . 1
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
9.1
9.2
9.3
9.4
10
11
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 April 2008
Document identifier: BUK962R2-40C_2
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