BUK9830-30 [NXP]
TrenchMOS transistor Logic level FET; 的TrenchMOS晶体管逻辑电平场效应管
| 型号： | BUK9830-30 |
| 厂家： | 
NXP |
| 描述： | TrenchMOS transistor Logic level FET |
| 文件： | 总10页 (文件大小：59K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9830-30
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Drain-source voltage
30
12.8
5.9
8.3
150
30
V
A
A
W
˚C
mΩ
mounting.
Using
’trench’
Drain current (DC) Tsp = 25 ˚C
Drain current (DC) Tamb = 25 ˚C
Total power dissipation
Junction temperature
Drain-source on-state
resistance
technology, the device features very
low on-state resistance and has
integral zener diodes giving ESD
protection up to 2kV. It is intended for
use in automotive and general
purpose switching applications.
Ptot
Tj
RDS(ON)
VGS = 5 V
PINNING - SOT223
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
d
4
gate
2
drain
g
3
source
4
drain (tab)
s
2
3
1
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
Drain-source voltage
-
-
-
-
-
-
-
-
-
30
30
10
12.8
5.9
9
4.1
51
23.6
8.3
1.8
150
V
V
V
A
A
A
A
A
A
Drain-gate voltage
Gate-source voltage
Drain current (DC)
RGS = 20 kΩ
-
Tsp = 25 ˚C
Tamb = 25 ˚C
Tsp = 100 ˚C
Tamb = 100 ˚C
Tsp = 25 ˚C
Tamb = 25 ˚C
Tsp = 25 ˚C
Tamb = 25 ˚C
-
ID
Drain current (DC)
IDM
Drain current (pulse peak value)
Total power dissipation
-
-
-
Ptot
W
W
˚C
Tstg, Tj
Storage & operating temperature
- 55
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-sp
Thermal resistance junction to
solder point
Mounted on any PCB
12
15
K/W
Rth j-amb
Thermal resistance junction to
ambient
Mounted on PCB of Fig.19
-
70
K/W
December 1997
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9830-30
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VC
Electrostatic discharge capacitor
voltage, all pins
Human body model
(100 pF, 1.5 kΩ)
-
2
kV
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA;
30
27
1
0.5
-
-
-
-
-
-
-
-
2
V
V
V
V
Tj = -55˚C
-
1.5
-
VGS(TO)
VDS = VGS; ID = 1 mA
Tj = 150˚C
Tj = -55˚C
-
-
2.3
10
500
1
10
-
IDSS
Zero gate voltage drain current VDS = 30 V; VGS = 0 V;
0.05
-
0.02
µA
µA
µA
µA
V
Tj = 150˚C
Tj = 150˚C
IGSS
Gate source leakage current
VGS = ±5 V; VDS = 0 V
IG = ±1 mA;
±V(BR)GSS
RDS(ON)
Gate-source breakdown
voltage
Drain-source on-state
resistance
10
-
VGS = 5 V; ID = 3.2 A
-
-
24
-
30
51
mΩ
mΩ
Tj = 150˚C
DYNAMIC CHARACTERISTICS
Tsp = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
gfs
Forward transconductance
VDS = 25 V; ID = 5.9 A
7
14
-
S
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 5.9 A; VDD = 24 V; VGS = 5 V
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
24
3
11
-
-
-
nC
nC
nC
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
-
-
-
1050
270
140
-
-
-
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 15 V; ID = 5.9 A;
VGS = 5 V; RG = 5 Ω
Resistive load
-
-
-
-
30
80
95
40
45
130
135
55
ns
ns
ns
ns
Ld
Ld
Ls
Internal drain inductance
Internal drain inductance
Internal source inductance
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
-
-
3.5
4.5
7.5
-
-
-
nH
nH
nH
December 1997
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9830-30
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IDR
Continuous reverse drain
current
-
-
40
A
IDRM
VSD
Pulsed reverse drain current
Diode forward voltage
-
-
-
-
160
1.2
-
A
V
IF = 3.2 A; VGS = 0 V
IF = 5.9 A; VGS = 0 V
0.75
0.85
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 5.9 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 25 V
-
-
100
0.4
-
-
ns
µC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 5.9 A; VDD ≤ 25 V;
-
-
60
mJ
VGS = 10 V; RGS = 50 Ω; Tsp = 25 ˚C
December 1997
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9830-30
Normalised Power Derating
PD%
Zth j-amb / (K/W)
120
110
100
90
80
70
60
50
40
30
20
10
0
1E+02
1E+01
1E+00
1E-01
1E-02
D =
0.5
0.2
0.1
0.05
0.02
tp
tp
P
D =
D
T
t
T
0
0
20
40
60
80
Tmb /
100
120
140
1E-07
1E-05
1E-03
1E-01
1E+01
1E+03
C
t / s
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
ID / A
4.5
120
110
100
90
80
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
10
5
6
4
VGS / V =
3.5
3
2.5
0
20
40
60
80
Tmb /
100
120
140
0
2
4
6
8
10
VDS / V
C
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
ID / A
RDS(ON) / mOhm
4
100
60
50
40
30
20
10
0
3
3.5
10
tp = 10 us
4.5
100 us
5
1
1 ms
DC
10
10 ms
6
0.1
100 ms
VGS / V =
40
0.01
0.1
1
10
VDS / V
100
1000
0
10
20
30
ID / A
50
60
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
December 1997
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9830-30
VGS(TO) / V
max.
ID / A
60
2.5
2
50
Tj / C = 25
typ.
40
30
20
10
0
1.5
1
150
min.
0.5
0
0
1
2
3
4
5
6
-100
-50
0
50
Tj / C
100
150
200
VGS / V
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.10. Gate threshold voltage.
GS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
V
Sub-Threshold Conduction
gfs / S
1E-01
1E-02
1E-03
1E-04
1E-05
1E-05
20
10
0
Tj / C = 25
150
2%
typ
98%
0
10
20
30
ID / A
40
50
60
0
0.5
1
1.5
2
2.5
3
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
C / pF
a
Normalised RDS(ON) = f(Tj)
2
1.5
1
10000
Ciss
1000
0.5
Coss
Crss
0
100
0.1
-50
0
50
Tj / C
100
150
1
10
100
VDS / V
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 3.2 A; VGS = 5 V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
December 1997
5
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9830-30
WDSS%
VGS / V
5
24
120
110
100
90
80
70
60
50
40
30
20
10
0
VDS / V = 6
4
3
2
1
0
20
40
60
80
100
120
140
0
5
10
15
20
25
QG / nC
Tmb /
C
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 5.9 A; parameter VDS
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 5.9 A
IF / A
60
50
40
30
20
10
0
VDD
+
L
VDS
-
VGS
-ID/100
Tj / C = 150
25
T.U.T.
0
R 01
RGS
shunt
0
0.5
1
1.5
2
VSDS / V
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
)
VDD
+
-
RD
VDS
VGS
0
RG
T.U.T.
Fig.17. Switching test circuit.
December 1997
6
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9830-30
MOUNTING INSTRUCTIONS
Dimensions in mm.
3.8
min
1.5
min
2.3
6.3
1.5
min
(3x)
1.5
min
4.6
Fig.18. soldering pattern for surface mounting SOT223.
PRINTED CIRCUIT BOARD
December 1997
7
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9830-30
Dimensions in mm.
36
18
60
4.5
4.6
9
10
7
15
50
Fig.19. PCB for thermal resistance and power rating for SOT223.
PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick).
December 1997
8
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9830-30
MECHANICAL DATA
Dimensions in mm
Net Mass: 0.11 g
6.7
6.3
B
3.1
2.9
0.32
0.24
0.2
M
A
A
4
0.10
0.02
7.3
6.7
3.7
3.3
16
max
13
2
3
1
10
max
1.05
0.85
0.80
0.60
2.3
1.8
max
M
0.1
(4x)
B
4.6
Fig.20. SOT223 surface mounting package.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to surface mounting instructions for SOT223 envelope.
3. Epoxy meets UL94 V0 at 1/8".
December 1997
9
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9830-30
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
December 1997
10
Rev 1.100
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