CBTL03SB212BS,515 [NXP]
CBTL03SB212 - DisplayPort Gen2 sideband signal multiplexer QFN 20-Pin;
| 型号： | CBTL03SB212BS,515 |
| 厂家： | 
NXP |
| 描述： | CBTL03SB212 - DisplayPort Gen2 sideband signal multiplexer QFN 20-Pin |
| 文件： | 总16页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CBTL03SB212
DisplayPort Gen2 sideband signal multiplexer
Rev. 1 — 21 February 2011
Product data sheet
1. General description
The CBTL03SB212 is a sideband signal multiplexer for DisplayPort Gen2 applications. It
provides one differential channel capable of switching or multiplexing (bidirectional and
AC-coupled) DisplayPort 1.2 Fast AUX or AUX signal, using high-bandwidth pass-gate
technology. Additionally, it provides for switching/multiplexing of the Hot Plug Detect signal
as well as the Display Data Channel (DDC) signals, for a total of three channels.
A typical application of CBTL03SB212 is on motherboards where one of two GPU display
sources needs to be selected to connect to a display sink device or connector. A controller
chip selects which path to use by setting a select signal HIGH or LOW. Due to the
non-directional nature of the signal paths (which use high-bandwidth pass-gate
technology), the CBTL03SB212 can also be used in the reverse topology, e.g., to connect
one display source device to one of two display sink devices or connectors.
GND
CBTL03SB212
100 kΩ
AUX1+
AUX1−
AUX2+
AUX2−
AUX+
2 : 1
MUX
AUX−
100 kΩ
+3.3 V
+3.3 V
2 kΩ
GPU1
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_CLK
DDC_DAT
2 : 1
MUX
DDC_DAT2
HPD_1
2 : 1
MUX
HPD
HPD_2
SEL, XSD_N
GPU2
002aag007
Fig 1. CBTL03SB212 application example
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
2. Features and benefits
1 : 2 multiplexing of DisplayPort signals
1 high-speed differential channel for Fast AUX or AUX
1 channel for DDC clock and data
1 channel for HPD
High-bandwidth analog pass-gate technology
Very low intra-pair differential skew (5 ps typical)
Switch/MUX position select
Shutdown mode CMOS input
Shutdown mode minimizes power consumption while switching all channels off
Very low operation current of 0.2 mA typical
Very low shutdown current of < 10 μA
Single 3.3 V power supply
ESD 4 kV HBM, 1 kV CDM
Available in 4 mm × 4 mm HVQFN20 package
3. Applications
Motherboard applications requiring DisplayPort sideband switching/multiplexing
Docking stations
Notebook computers
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
CBTL03SB212BS
HVQFN20
plastic thermal enhanced very thin quad flat package; no leads;
20 terminals; body 4 × 4 × 0.85 mm[1]
SOT917-1
[1] Total height after printed-circuit board mounting = 1 mm (maximum).
CBTL03SB212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
2 of 16
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
5. Functional diagram
AUX1+
AUX1−
AUX+
2 : 1
MUX
AUX−
AUX2+
AUX2−
DDC_CLK1
DDC_DAT1
DDC_CLK
DDC_DAT
2 : 1
MUX
DDC_CLK2
DDC_DAT2
HPD_1
HPD_2
2 : 1
MUX
HPD
SEL, XSD_N
002aag008
Fig 2. Functional diagram
6. Pinning information
6.1 Pinning
terminal 1
index area
1
2
3
4
5
15
14
13
12
11
AUX−
DDC_CLK
DDC_DAT
HPD
XSD_N
AUX2+
CBTL03SB212BS
AUX2−
DDC_CLK1
DDC_DAT1
SEL
002aag009
Transparent top view
Fig 3. Pin configuration for HVQFN20
CBTL03SB212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
3 of 16
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
6.2 Pin description
Table 2.
Symbol
SEL
Pin description
Pin
Type
Description
5
3.3 V CMOS
Selects between two multiplexer/switch paths.
single-ended input
XSD_N
15
3.3 V CMOS
Shutdown pin. Should be driven HIGH or
single-ended input connected to VDD for normal operation. When
LOW, all paths are switched off (non-conducting
high-impedance state), and supply current
consumption is minimized.
AUX+
20
1
differential I/O
differential I/O
differential I/O
differential I/O
single-ended I/O
High-speed differential pair for AUX signals,
right-side.
AUX−
DDC_CLK
DDC_DAT
HPD
2
Pair of single-ended terminals for DDC clock and
data signals, right-side.
3
4
Single-ended channel for the HPD signal,
right-side.
AUX1+
17
16
14
13
12
11
9
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
single-ended I/O
High-speed differential pair for AUX signals, path 1,
left-side.
AUX1−
AUX2+
High-speed differential pair for AUX signals, path 2,
left-side.
AUX2−
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_DAT2
HPD_1
Pair of single-ended terminals for DDC clock and
data signals, path 1, left-side.
Pair of single-ended terminals for DDC clock and
data signals, path 2, left-side.
8
10
Single-ended channel for the HPD signal, path 1,
left-side.
HPD_2
7
single-ended I/O
Single-ended channel for the HPD signal, path 2,
left-side.
VDD
GND[1]
6, 18
19
power supply
ground
3.3 V power supply.
Ground.
[1] HVQFN20 package die supply ground is connected to both GND pin and exposed center pad. GND pin and
the exposed center pad must be connected to supply ground for proper device operation. For enhanced
thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the printed-circuit board in the thermal pad region.
CBTL03SB212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
4 of 16
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
7. Functional description
Refer to Figure 2 “Functional diagram”.
The CBTL03SB212 uses 3.3 V power supply. All signal paths are implemented using
high-bandwidth pass-gate technology, are bidirectional and no clock or reset signal is
needed for the multiplexer to function.
The switch position is selected using the select signal (SEL). The detailed operation is
described in Section 7.1.
7.1 MUX select (SEL) function
The internal multiplexer switch position is controlled by the logic inputs SEL as described
below.
Table 3.
MUX select control
Path 2
SEL
0
Path 1
high-impedance
active
active
1
high-impedance
7.2 Shutdown function
The CBTL03SB212 provides a shutdown function to minimize power consumption when
the application is not active but power to the CBTL03SB212 is provided. Pin XSD_N
(active LOW) puts all channels in Off mode (non-conducting high-impedance state) while
reducing current consumption to near-zero.
Table 4.
Shutdown function
State
XSD_N
0
1
shutdown
active
CBTL03SB212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
5 of 16
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
Parameter
Conditions
Min
−0.3
−40
Max
+5
Unit
V
supply voltage
case temperature
Tcase
for operation within
specification
+85
°C
[1]
[2]
VESD
electrostatic discharge
voltage
HBM
CDM
-
-
4000
1000
V
V
[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -
Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2] Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing,
Charged-Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Conditions
Symbol Parameter
Min
3.0
-
Typ
Max
3.6
Unit
V
VDD
VI
supply voltage
input voltage
3.3
-
-
3.6
V
Tamb
ambient temperature operating in free air
−40
+85
°C
CBTL03SB212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
6 of 16
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
10. Characteristics
10.1 General characteristics
Table 7.
General characteristics
Symbol Parameter
Conditions
Min
Typ
Max
1
Unit
mA
μA
IDD
supply current
operating mode (XSD_N = HIGH); VDD = 3.3 V
shutdown mode (XSD_N = LOW); VDD = 3.3 V
operating mode (XSD_N = HIGH); VDD = 3.3 V
-
-
-
-
0.2
-
-
-
10
5
Ptot
total power dissipation
start-up time
mW
μs
tstartup
supply voltage valid or XSD_N going HIGH to
channel specified operating characteristics
10
trcfg
reconfiguration time
SEL state change to channel specified
operating characteristics
-
-
1
μs
10.2 AUX channel characteristics
Table 8.
AUX channel characteristics
Symbol Parameter
Conditions
Min
Typ
Max
Unit
V
VI
input voltage
−0.3
-
+2.6
2.0
+1.4
-
VIC
VID
DDIL
common-mode input voltage
differential input voltage
differential insertion loss
0
-
-
V
peak-to-peak
-
V
channel is on; f = 100 MHz
channel is on; f = 2.5 GHz
channel is off; 0 Hz ≤ f ≤ 1.0 GHz
channel is on; 0 Hz ≤ f ≤ 1.0 GHz
-
−0.8
dB
dB
dB
dB
dB
-
−3
-
-
-
−30
−10
−40
DDRL
differential return loss
-
-
DDNEXT differential near-end crosstalk adjacent channels are on;
-
-
0 Hz ≤ f ≤ 1.0 GHz
B
bandwidth
−3.0 dB intercept
-
-
2.5
-
-
GHz
ps
tPD
propagation delay
from left-side port to right-side port
or vice versa
100
tsk(dif)
differential skew time
intra-pair
-
5
-
ps
10.3 DDC ports
Table 9.
DDC port characteristics
Symbol Parameter
Conditions
Min
−0.3
-
Typ
-
Max
VDD
-
Unit
V
VI
input voltage
tPD
propagation delay
from left-side port to right-side port
or vice versa
100
ps
CBTL03SB212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
7 of 16
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
10.4 HPD input, HPD output
Table 10. HPD input and output characteristics
Symbol Parameter Conditions
Min
−0.3
-
Typ
-
Max
3.6
-
Unit
V
[1]
VI
input voltage
tPD
propagation delay
from left-side port to right-side port
or vice versa
100
ps
[1] Low-speed input changes state on cable plug/unplug.
10.5 MUX select input
Table 11. SEL, XSD_N input characteristics
Symbol
VIH
Parameter
Conditions
SEL, XSD_N
SEL, XSD_N
Min
2.0
0
Typ
Max
3.6
0.8
10
Unit
V
HIGH-level input voltage
LOW-level input voltage
input leakage current
-
-
-
VIL
V
ILI
measured with input at
VIH(max) and VIL(min)
-
μA
11. Test information
11.1 Switch test fixture requirements
The test fixture for switch S-parameter measurement shall be designed and built to
specific requirements, as described below, to ensure good measurement quality and
consistency.
• The test fixture shall be a FR4-based PCB of the microstrip structure; the dielectric
thickness or stack-up shall be about 4 mils.
• The total thickness of the test fixture PCB shall be 1.57 mm (0.062 in).
• The measurement signals shall be launched into the switch from the top of the test
fixture, capturing the through-hole stub effect.
• Traces between the DUT and measurement ports (SMA or microprobe) should be
uncoupled from each other, as much as possible. Therefore, the traces should be
routed in such a way that traces will diverge from each other exiting from the switch
pin field.
• The trace lengths between the DUT and measurement port shall be minimized. The
maximum trace length shall not exceed 1000 mils. The trace lengths between the
DUT and measurement port shall be equal.
• All of the traces on the test board and add-in card must be held to a characteristic
impedance of 50 Ω with a tolerance of ±7 %.
• SMA connector is recommended for ease of use. The SMA launch structure shall be
designed to minimize the connection discontinuity from SMA to the trace. The
impedance range of the SMA connector seen from a TDR with a 60 ps rise time
should be within 50 Ω ± 7 Ω.
CBTL03SB212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
8 of 16
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
12. Package outline
HVQFN20: plastic thermal enhanced very thin quad flat package; no leads;
20 terminals; body 4 x 4 x 0.85 mm
SOT917-1
B
A
E
D
terminal 1
index area
A
A
1
c
detail X
C
e
1
y
y
v
M
M
C
C
A
B
C
1
e
b
w
6
10
L
11
15
5
1
e
e
E
2
h
terminal 1
index area
20
16
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
(1)
(1)
UNIT
A
b
c
E
h
e
e
e
y
D
D
E
L
v
w
y
1
1
2
h
1
0.05 0.30
0.00 0.18
4.1
3.9
2.45 4.1
2.15 3.9
2.45
2.15
0.6
0.4
mm
0.05
0.1
1
0.2
0.5
2
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
05-10-08
05-10-31
SOT917 -1
- - -
MO-220
- - -
Fig 4. Package outline HVQFN20 (SOT917-1)
CBTL03SB212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
9 of 16
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
CBTL03SB212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
10 of 16
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 5) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 12 and 13
Table 12. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 13. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 5.
CBTL03SB212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
11 of 16
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 5. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Abbreviations
Table 14. Abbreviations
Acronym
AUX
Description
Auxiliary channel in DisplayPort definition
Charged-Device Model
Complementary Metal-Oxide Semiconductor
Display Data Channel
Device Under Test
CDM
CMOS
DDC
DUT
ESD
ElectroStatic Discharge
Fast AUX
FAUX
GPU
HBM
HPD
I/O
Graphics Processor Unit
Human Body Model
Hot Plug Detect
Input/Output
MUX
PCB
Multiplexer
Printed-Circuit Board
SMA
TDR
SubMiniature, version A (connector)
Time-Domain Reflectometry
CBTL03SB212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
12 of 16
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
15. Revision history
Table 15. Revision history
Document ID
Release date
20110221
Data sheet status
Change notice
Supersedes
CBTL03SB212 v.1
Product data sheet
-
-
CBTL03SB212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
13 of 16
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
CBTL03SB212
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
14 of 16
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
CBTL03SB212
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
15 of 16
CBTL03SB212
NXP Semiconductors
DisplayPort Gen2 sideband signal multiplexer
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
7.1
7.2
Functional description . . . . . . . . . . . . . . . . . . . 5
MUX select (SEL) function . . . . . . . . . . . . . . . . 5
Shutdown function . . . . . . . . . . . . . . . . . . . . . . 5
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
10
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 7
General characteristics. . . . . . . . . . . . . . . . . . . 7
AUX channel characteristics. . . . . . . . . . . . . . . 7
DDC ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
HPD input, HPD output. . . . . . . . . . . . . . . . . . . 8
MUX select input . . . . . . . . . . . . . . . . . . . . . . . 8
10.1
10.2
10.3
10.4
10.5
11
11.1
12
Test information. . . . . . . . . . . . . . . . . . . . . . . . . 8
Switch test fixture requirements . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
13
Soldering of SMD packages . . . . . . . . . . . . . . 10
Introduction to soldering . . . . . . . . . . . . . . . . . 10
Wave and reflow soldering . . . . . . . . . . . . . . . 10
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 10
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 11
13.1
13.2
13.3
13.4
14
15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 21 February 2011
Document identifier: CBTL03SB212
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