DAC1401D125HL [NXP]

Dual 14-bit DAC, up to 125 Msps; 双14位DAC ,高达125 MSPS
DAC1401D125HL
型号: DAC1401D125HL
厂家: NXP    NXP
描述:

Dual 14-bit DAC, up to 125 Msps
双14位DAC ,高达125 MSPS

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DAC1401D125  
Dual 14-bit DAC, up to 125 Msps  
Rev. 01 — 13 November 2008  
Product data sheet  
1. General description  
The DAC1401D125 is a dual port, high-speed, 2-channel CMOS Digital-to-Analog  
Converter (DAC), optimized for high dynamic performance with low power dissipation.  
Supporting an update rate of up to 125 Msps, the DAC1401D125 is suitable for Direct IF  
applications.  
Separate write inputs allow data to be written to the two DAC ports independently of one  
another. Two separate clocks control the update rate of each DAC port.  
The DAC1401D125 can interface two separate data ports or one single interleaved  
high-speed data port. In Interleaved mode, the input data stream is demultiplexed into its  
original I and Q data and latched. The I and Q data is then converted by the two DACs and  
updated at half the input data rate.  
Each DAC port has a high-impedance differential current output, suitable for both  
single-ended and differential analog output configurations.  
The DAC1401D125 is pin compatible with the AD9767, DAC2904 and DAC5672.  
2. Features  
I Dual 14-bit resolution  
I Typical 185 mW power dissipation  
I 16 mW power-down  
I 125 Msps update rate  
I Single 3.3 V supply  
I SFDR: 81 dBc; fo = 1 MHz; fs = 52 Msps  
I SFDR: 79 dBc; fo = 10.4 MHz;  
fs = 78 Msps  
I Dual-port or Interleaved data modes  
I 1.8 V, 3.3 V and 5 V compatible digital I SFDR: 75 dBc; fo = 1 MHz;  
inputs  
fs = 52 Msps; 12 dBFS  
I Internal and external reference  
I LQFP48 package  
I 2 mA to 20 mA full-scale output current I Industrial temperature range of  
40 °C to +85 °C  
3. Applications  
I Quadrature modulation  
I Direct digital frequency synthesis  
I Arbitrary waveform generator  
I Medical/test instrumentation  
I Direct IF applications  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
4. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Name  
Description  
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm  
Version  
DAC1401D125HL  
LQFP48  
SOT313-2  
5. Block diagram  
IOUTAP  
IOUTAN  
14  
14  
14  
INPUT A  
LATCH  
DAC A  
LATCH  
DAC  
A
DA13 to DA0  
WRTA/IQWRT  
CLKA/IQCLK  
CLKB/IQRESET  
WRTB/IQSEL  
DB13 to DB0  
REFIO  
REFERENCE  
AVIRES  
BVIRES  
DAC1401D125  
CONTROL  
AMPLIFIER  
GAINCTRL  
PWD  
IOUTBP  
IOUTBN  
14  
14  
14  
INPUT B  
LATCH  
DAC B  
LATCH  
DAC  
B
V
AGND  
V
DGND  
001aah997  
DDA  
DDD  
Fig 1. Block diagram  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
2 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
6. Pinning information  
6.1 Pinning  
1
2
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
DA13  
DA12  
DA11  
DA10  
DA9  
DA8  
DA7  
DA6  
DA5  
DA4  
DA3  
DA2  
DB0  
DB1  
DB2  
DB3  
DB4  
DB5  
DB6  
DB7  
DB8  
DB9  
DB10  
DB11  
3
4
5
6
DAC1401D125HL  
7
8
9
10  
11  
12  
001aah996  
Fig 2. Pin configuration SOT313-2 (LQFP48)  
6.2 Pin description  
Table 2.  
Pin description  
Symbol  
DA13  
DA12  
DA11  
DA10  
DA9  
Pin  
1
Type[1]  
Description  
I
I
I
I
I
I
I
I
I
I
I
I
I
DAC A data input bit 13 (MSB)  
DAC A data input bit 12  
DAC A data input bit 11  
DAC A data input bit 10  
DAC A data input bit 9  
DAC A data input bit 8  
DAC A data input bit 7  
DAC A data input bit 6  
DAC A data input bit 5  
DAC A data input bit 4  
DAC A data input bit 3  
DAC A data input bit 2  
DAC A data input bit 1  
2
3
4
5
DA8  
6
DA7  
7
DA6  
8
DA5  
9
DA4  
10  
11  
12  
13  
DA3  
DA2  
DA1  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
3 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
Table 2.  
Pin description …continued  
Symbol  
DA0  
Pin  
14  
15  
16  
17  
Type[1]  
Description  
I
DAC A data input bit 0 (LSB)  
digital ground  
DGND  
G
S
I
VDDD  
digital supply voltage  
WRTA/IQWRT  
Input write port A  
Input write IQ in Interleaved mode  
Input clock port A  
CLKA/IQCLK  
CLKB/IQRESET  
WRTB/IQSEL  
18  
19  
20  
I
I
I
Input clock IQ in Interleaved mode  
Input clock port B  
reset IQ in Interleaved mode  
Input write port B  
select IQ in Interleaved mode  
digital ground  
DGND  
VDDD  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
G
S
I
digital supply voltage  
DB13  
DB12  
DB11  
DB10  
DB9  
DAC B data input bit 13 (MSB)  
DAC B data input bit 12  
DAC B data input bit 11  
DAC B data input bit 10  
DAC B data input bit 9  
I
I
I
I
DB8  
I
DAC B data input bit 8  
DB7  
I
DAC B data input bit 7  
DB6  
I
DAC B data input bit 6  
DB5  
I
DAC B data input bit 5  
DB4  
I
DAC B data input bit 4  
DB3  
I
DAC B data input bit 3  
DB2  
I
DAC B data input bit 2  
DB1  
I
DAC B data input bit 1  
DB0  
I
DAC B data input bit 0 (LSB)  
Power-down mode  
PWD  
I
AGND  
IOUTBP  
IOUTBN  
BVIRES  
GAINCTRL  
REFIO  
AVIRES  
IOUTAN  
IOUTAP  
VDDA  
G
O
O
I
analog ground  
DAC B current output  
complementary DAC B current output  
adjust DAC B for full-scale output current  
gain control mode  
I
I/O  
I
reference input/output  
adjust DAC A for full-scale output current  
complementary DAC A current output  
DAC A current output  
O
O
S
I
analog supply voltage  
MODE  
select between Dual port mode or Interleaved mode  
[1] Type description: S = Supply; G = Ground; I = Input; O = Output; I/O = Input/Output.  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
4 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
7. Limiting values  
Table 3.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VDDD  
VDDA  
VDD  
VI  
Parameter  
Conditions  
Min  
Max  
+5.0  
+5.0  
+150  
+5.5  
+5.5  
Unit  
V
[1]  
[1]  
digital supply voltage  
analog supply voltage  
supply voltage difference  
input voltage  
0.3  
0.3  
150  
0.3  
0.3  
V
between analog and digital supply voltage  
digital inputs referenced to DGND  
mV  
V
pins REFIO, AVIRES, BVIRES  
referenced to AGND  
V
VO  
output voltage  
pins IOUTAP, IOUTAN, IOUTBP and IOUTBN  
referenced to AGND  
0.3  
VDDA + 0.3 V  
Tstg  
Tamb  
Tj  
storage temperature  
ambient temperature  
junction temperature  
55  
40  
-
+150  
+85  
°C  
°C  
°C  
125  
[1] All supplies are connected together.  
8. Thermal characteristics  
Table 4.  
Symbol  
Rth(j-a)  
Thermal characteristics  
Parameter  
Conditions  
in free air  
in free air  
Typ  
Unit  
K/W  
K/W  
thermal resistance from junction to ambient  
thermal resistance from case to ambient  
89.3  
60.6  
Rth(c-a)  
9. Characteristics  
Table 5.  
Characteristics  
VDDD = VDDA = 3.3 V; AGND and DGND connected together; IO(fs) = 20 mA and Tamb = 40 °C to +85 °C; typical values  
measured at Tamb = 25 °C.  
Symbol  
Supplies  
VDDD  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
digital supply voltage  
analog supply voltage  
digital supply current  
3.0  
3.0  
-
3.3  
3.3  
6
3.65  
3.65  
7
V
VDDA  
V
IDDD  
fs = 65 Msps, fo = 1 MHz,  
mA  
V
DD = 3.0 V to 3.6 V  
fs = 65 Msps, fo = 1 MHz,  
DD = 3.0 V to 3.6 V  
fs = 65 Msps, fo = 1 MHz,  
DD = 3.0 V to 3.6 V  
IDDA  
Ptot  
Ppd  
analog supply current  
total power dissipation  
-
-
-
50  
65  
260  
-
mA  
V
185  
16.5  
mW  
mW  
V
power dissipation in  
power-down mode  
Digital inputs  
VIL  
VIH  
LOW-level input voltage  
HIGH-level input voltage  
DGND  
1.3  
-
-
0.9  
V
V
VDDD  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
5 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
Table 5.  
Characteristics …continued  
VDDD = VDDA = 3.3 V; AGND and DGND connected together; IO(fs) = 20 mA and Tamb = 40 °C to +85 °C; typical values  
measured at Tamb = 25 °C.  
Symbol  
Parameter  
Conditions  
VIL = 0.9 V  
VIH = 1.3 V  
Min  
Typ  
5
Max  
Unit  
µA  
IIL  
IIH  
Ci  
LOW-level input current  
HIGH-level input current  
input capacitance  
-
-
-
-
-
-
5
µA  
[1]  
5
pF  
Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN)  
IO(fs)  
VO  
Ro  
full-scale output current  
output voltage  
differential outputs  
compliance range  
2
1  
-
-
20  
mA  
V
[1]  
[1]  
[1]  
-
+1.25  
output resistance  
output capacitance  
150  
3
-
-
kΩ  
pF  
Co  
-
Reference voltage input/output (REFIO)  
VO(ref)  
IO(ref)  
Vi  
reference output voltage  
reference output current  
input voltage  
1.25  
1.26  
100  
-
1.27  
V
[1]  
-
-
nA  
V
compliance range  
1.0  
-
1.26  
-
Ri  
input resistance  
1
MΩ  
Input timing see Figure 18  
fs  
sampling frequency  
WRT pulse width  
CLK pulse width  
input hold time  
-
-
-
-
-
-
125  
Msps  
ns  
tw(WRT)  
tw(CLK)  
th(i)  
pins WRTA, WRTB  
pins CLKA, CLKB  
2
-
-
-
-
2
ns  
1
ns  
tsu(i)  
input set-up time  
1.8  
ns  
Output timing (IOUTAP, IOUTAN, IOUTBP, IOUTBN)  
td  
tt  
delay time  
1
-
-
ns  
ns  
[1]  
[1]  
transition time  
rising or falling transition  
(10 % to 90 % or 90 % to 10 %)  
-
-
0.6  
ts  
settling time  
±1 LSB  
43  
-
ns  
Static linearity  
INL  
integral non-linearity  
25 °C  
±1.60  
±1.25  
±0.55  
±2.15 ±2.90  
±2.95  
±0.75 ±1.10  
LSB  
LSB  
LSB  
40 °C to +85 °C  
40 °C to +85 °C  
-
DNL  
differential non-linearity  
Static accuracy (relative to full-scale)  
Eoffset  
EG  
offset error  
gain error  
-0.02  
-1.9  
-
+0.02  
+2.5  
+2.9  
%
%
%
%
with external reference  
with internal reference  
between DAC A and DAC B  
±1.5  
±2.1  
-2.9  
G  
gain mismatch  
-0.36  
±0.05 +0.36  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
6 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
Table 5.  
Characteristics …continued  
VDDD = VDDA = 3.3 V; AGND and DGND connected together; IO(fs) = 20 mA and Tamb = 40 °C to +85 °C; typical values  
measured at Tamb = 25 °C.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Dynamic performance  
SFDR  
spurious free dynamic  
B = Nyquist  
range  
fs = 52 Msps; fo = 1 MHz  
0 dBFS  
-
-
-
81  
80  
75  
-
-
-
dBc  
dBc  
dBc  
6 dBFS  
12 dBFS  
fs = 52 Msps; 0 dBFS  
fo = 5.24 MHz  
-
79  
-
dBc  
fs = 78 Msps; 0 dBFS  
fo = 10.4 MHz  
-
-
79  
72  
-
-
dBc  
dBc  
fo = 15.7 MHz  
fs = 100 Msps; 0 dBFS  
fo = 5.04 MHz  
-
77  
69  
-
-
dBc  
dBc  
fo = 20.2 MHz  
61  
fs = 125 Msps; 0 dBFS  
fo = 20.1 MHz  
-
69  
-
dBc  
Within a Window  
fs = 52 Msps; fo = 1 MHz;  
2 MHz span  
-
90  
88  
92  
92  
-
-
-
-
dBc  
dBc  
dBc  
dBc  
fs = 52 Msps; fo = 5.24 MHz;  
10 MHz span  
-
fs = 78 Msps; fo = 5.26 MHz;  
2 MHz span  
-
fs = 125 Msps; fo = 5.04 MHz;  
10 MHz span  
80  
THD  
total harmonic distortion  
multitone power ratio  
fs = 52 Msps; fo = 1 MHz  
-
-
-
-
-
-79  
-76  
-75  
-65  
80  
-
dBc  
dBc  
dBc  
dBc  
dBc  
fs = 78 Msps; fo = 5.26 MHz  
fs = 100 Msps; fo = 5.04 MHz  
fs = 125 Msps; fo = 20.1 MHz  
-
-
-60  
-
MTPR  
fs = 65 Msps;  
2 MHz < fo < 2.99 MHz; 8 tones  
at 110 kHz spacing at 0 dB  
full-scale  
NSD  
noise spectral density  
channel separation  
fs = 100 Msps; fo = 5.04 MHz  
fs = 78 Msps; fo = 10.4 MHz  
fs = 125 Msps; fo = 20.1 MHz  
-
-
-
-149  
88.0  
83.5  
-
-
-
dBm/Hz  
dBc  
αcs  
dBc  
[1] Guaranteed by design.  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
7 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
001aai998  
80  
SFDR  
(dBc)  
(1)  
(2)  
76  
(3)  
(4)  
72  
68  
64  
60  
20  
0
20  
60  
100  
T (°C)  
(1) fo = 5 MHz  
(2) fo = 10 MHz  
(3) fo = 15 MHz  
(4) fo = 20 MHz  
Fig 3. SFDR as a function of the ambient temperature at 125 Msps  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
8 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
001aai985  
0
α
(dBm)  
20  
40  
60  
80  
100  
0
10  
20  
30  
f (MHz)  
a. f = 52 Msps; f = 5.24 MHz; α = 0 dBFS  
s
c
001aai987  
0
α
(dBm)  
20  
40  
60  
80  
100  
0
10  
20  
30  
40  
50  
f (MHz)  
b. f = 100 Msps; f = 20 MHz; α = 0 dBFS  
s
c
Fig 4. 1-tone SFDR  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
9 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
001aai988  
0
α
(dBm)  
20  
40  
60  
80  
100  
0
10  
20  
30  
40  
f (MHz)  
fs = 78 Msps; fc = 9.44 MHz, fc = 10.44 MHz; α = 0 dBFS  
Fig 5. 2-tone SFDR  
001aai989  
0
α
(dBm)  
20  
40  
60  
80  
100  
0
10  
20  
30  
f (MHz)  
fs = 52 Msps; fc = 6.25 MHz, fc = 6.75 MHz; fc = 7.25 MHz, fc = 7.75 MHz; α = 0 dBFS  
Fig 6. 4-tone SFDR  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
10 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
001aai990  
0
α
(dBm)  
20  
40  
60  
80  
100  
0
10  
20  
30  
40  
f (MHz)  
fs = 78 Msps; from fc = 9.5 MHz, 110 kHz spacing; α = 0 dBFS  
Fig 7. 8-tone SFDR  
001aaj004  
4
2
0
INL  
(dB)  
2  
4  
0
2900  
5800  
8700  
11600  
14500  
17400  
input code  
Fig 8. INL as a function of the input code  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
11 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
001aaj003  
0.8  
DNL  
(dB)  
0.4  
0
0.4  
0.8  
0
2964  
5928  
8892  
11856  
14820  
17784  
input code  
Fig 9. DNL as a function of the input code  
001aaj035  
85  
SFDR  
(dBc)  
80  
75  
70  
65  
60  
(1)  
(2)  
(3)  
0
5
10  
15  
20  
f
(MHz)  
o
(1) fo = 0 dBFS  
(2) fo = 6 dBFS  
(3) fo = 12 dBFS  
Fig 10. SFDR full-scale at 78 Msps as a function of the output frequency  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
12 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
001aaj038  
85  
SFDR  
(dBc)  
80  
75  
70  
65  
60  
(1)  
(2)  
(3)  
0
5
10  
15  
20  
25  
f
(MHz)  
o
(1) fo = 0 dBFS  
(2) fo = 6 dBFS  
(3) fo = 12 dBFS  
Fig 11. SFDR full-scale at 125 Msps as a function of the output frequency  
001aai938  
16  
(1)  
(2)  
I
DDD  
(mA)  
12  
(3)  
(4)  
8
4
0
0
0.1  
0.2  
0.3  
0.4  
0.5  
f /f  
o
s
(1) fs = 125 Msps  
(2) fs = 100 Msps  
(3) fs = 78 Msps  
(4) fs = 52 Msps  
Fig 12. Digital supply current as a function of fo/fs  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
13 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
001aaj032  
60  
I
DDA  
(mA)  
40  
20  
0
0
5
10  
15  
20  
l
O
(mA)  
Fig 13. Analog supply current as a function of the output current  
10. Application information  
10.1 General description  
The DAC1401D125 is a dual 14-bit DAC operating up to 125 Msps. Each DAC consists of  
a segmented architecture, comprising a 7-bit thermometer sub-DAC and a 7-bit binary  
weighted sub-DAC.  
Two modes are available for the digital input depending on the status of the pin MODE. In  
Dual port mode, each DAC uses its own data input line at the same frequency as the  
update rate. In Interleaved mode, both DACs use the same data input line at twice the  
update rate.  
Each DAC generates on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN two complementary  
current outputs. This provides a full-scale output current (IO(fs)), up to 20 mA. A single  
common or two independent full-scale current controls can be selected for both channels  
using pin GAINCTRL. An internal reference is available for the reference current which is  
externally adjustable using pin REFIO.  
The DAC1401D125 operates at 3.3 V and has separate digital and analog power supplies.  
Pin PWD is used to power-down the device. The digital input is 1.8 V compliant, 3.3 V  
compliant and 5 V tolerant.  
10.2 Input data  
The DAC1401D125 input follows a straight binary coding where DA13 and DB13 are the  
Most Significant Bits (MSB) and DA0 and DB0 are the Least Significant Bits (LSB).  
The setting applied to pin MODE defines whether the DAC1401D125 operates in Dual  
port mode or in Interleaved mode (see Table 6).  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
14 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
Table 6.  
Mode selection  
DA13 to DA0 DB13 to DB0 Pin 17 Pin 18 Pin 19  
Mode Function  
Pin 20  
0
1
Interleaved mode active  
Dual port mode active  
off  
IQWRT IQCLK IQRESET IQSEL  
active  
WRTA  
CLKA CLKB  
WRTB  
10.2.1 Dual port mode  
The data and clock circuit for Dual port mode operation is shown in Figure 14.  
14  
14  
INPUT A  
LATCH  
DAC A  
LATCH  
DA13 to DA0  
WRTA  
CLKA  
CLKB  
WRTB  
14  
14  
INPUT B  
LATCH  
DAC B  
LATCH  
DB13 to DB0  
001aai823  
Fig 14. Dual port mode operation  
Each DAC has its own independent data and clock inputs. The data enters the input latch  
on the rising edge of the WRTA/WRTB signal and is transferred to the DAC latch. The  
output is updated on the rising edge of the CLKA/CLKB signal.  
DA13 to DA0/  
DB13 to DB0  
N
N+1  
N+2  
N+3  
WRTA/  
WRTB  
CLKA/  
CLKB  
IOUTAP, IOUTAN/  
IOUTBP, IOUTBN  
N2  
N1  
N
N+1  
N+2  
001aai939  
Fig 15. Dual port mode timing  
10.2.2 Interleaved mode  
The data and clock circuit for Interleaved mode operation is illustrated in Figure 16.  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
15 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
14  
14  
14  
14  
INPUT A  
LATCH  
DAC A  
LATCH  
DA13 to DA0  
INPUT B  
LATCH  
DAC B  
LATCH  
IQWRT  
IQSEL  
IQCLK  
IQRESET  
÷ 2  
001aai824  
Fig 16. Interleaved mode  
In Interleaved mode, both DACs use the same data and clock inputs at twice the update  
rate. Data enters the latch on the rising edge of IQWRT. The data is sent to either latch A  
or latch B, depending on the value of IQSEL. The IQSEL transition must occur when  
IQWRT and IQCLK are LOW.  
The IQCLK is divided by 2 internally and the data is transferred to the DAC latch. It is  
updated on its rising edge. When IQRESET is HIGH, IQCLK is disabled, see Figure 17.  
DA13 to DA0/  
DB13 to DB0  
N
N+1  
N+2  
N+3  
N+4  
N+5  
N+6  
N+7  
IQSEL  
IQWRT  
IQCLK  
IQRESET  
N
XX  
N+4  
IOUTAP, IOUTAN  
IOUTBP, IOUTBN  
N+2  
N+3  
N+1  
XX  
N+5  
001aai940  
Fig 17. Interleaved mode timing  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
16 of 25  
DAC1401D125  
NXP Semiconductors  
10.3 Timing  
Dual 14-bit DAC, up to 125 Msps  
The DAC1401D125 can operate at an update rate up to 125 Msps. This generates an  
input data rate of 125 MHz in Dual port mode and 250 MHz in Interleaved mode. The  
timing of the DAC1401D125 is shown in Figure 18.  
t
t
su(i)  
h(i)  
DA13 to DA0/  
DB13 to DB0  
WRTA/  
WRTB  
t
t
d(clk)  
w(WRT)  
CLKA/  
CLKB  
t
t
d
w(CLK)  
90 %  
IOUTAP, IOUTAN/  
IOUTBP, IOUTBN  
10 %  
t
t
t
s
001aai937  
Fig 18. Timing of the DAC1401D125  
The typical performances are measured at 50 % duty cycle but any timing within the limits  
of the characteristics will not alter the performance.  
A configuration resulting in the same timing for the signals WRTA/WRTB and  
CLKA/CLKB, can be achieved either by synchronizing them or by connecting them  
together.  
The rising edge of the CLKA/CLKB signal can also be placed in a range from half a  
period in front of the rising edge of the WRTA/WRTB signal to half a period minus 1 ns  
after the rising edge of the WRTA/WRTB signal.  
A typical set-up time of 0 ns and a hold time of 0.6 ns enable the DAC1405D125 to be  
easily integrated into any application.  
10.4 DAC transfer function  
The full-scale output current for each DAC is the sum of the two complementary current  
outputs:  
IO( fs) = IIOUTP + IIOUTN  
(1)  
The output current depends on the digital input data:  
DATA  
16384  
(16383 DATA)  
-----------------------------------------  
16384  
IIOUTP = IO( fs)  
×
IIOUTN = IO( fs) ×  
---------------  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
17 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
Table 7 shows the output current as a function of the input data, when IO(fs) = 20 mA.  
Table 7.  
Data  
0
DAC transfer function  
DA13/DB13 to DA0/DB0  
00 0000 0000 0000  
...  
IOUTAP/IOUTBP  
IOUTAN/IOUTBN  
0 mA  
...  
20 mA  
...  
...  
8192  
...  
10 0000 0000 0000  
...  
10 mA  
...  
10 mA  
...  
16383  
11 1111 1111 1111  
20 mA  
0 mA  
10.5 Full-scale current adjustment  
The DAC1401D125 integrates one 1.25 V reference and two current sources to adjust the  
full-scale current in both DACs.  
The internal reference configuration is shown in Figure 19.  
AVIRES  
CURRENT  
SOURCE  
R
A
AGND  
REFIO  
1.25 V REFERENCE  
100 nF  
AGND  
BVIRES  
CURRENT  
SOURCE  
R
B
AGND  
001aai822  
Fig 19. Internal reference configuration  
The bias current is generated by the output of the internal regulator connected to the  
inverting input of the internal operational amplifiers. The external resistors RA and RB are  
connected to pins AVIRES and BVIRES, respectively. This configuration is optimal for  
temperature drift compensation because the bandgap can be matched with the voltage on  
the feedback resistors.  
The relationship between full-scale output current (IO(fs)) at the output of channel A or  
channel B and the resistor is:  
24VREFIO  
IO( fs)  
=
(2)  
------------------------  
RA  
The output current of the two DACs is typically fixed at 20 mA when both resistors RA and  
RB are set to 1.5 k. The operational range of DAC1401D125 is from 2 mA to 20 mA.  
It is recommended to decouple pin REFIO using a 100 nF capacitor.  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
18 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
An external reference can also be used for applications requiring higher accuracy or  
precise current adjustment. Due to the high input impedance of pin REFIO, applying an  
external source disables the bandgap.  
10.6 Gain control  
Table 8 shows how to select the different gain control modes.  
Table 8.  
Gain control  
Mode  
GAINCTRL  
DAC A  
DAC B  
full-scale control  
full-scale control  
0
1
independent gain control  
common gain control  
AVIRES  
AVIRES  
BVIRES  
AVIRES  
In Independent gain mode, both full-scale currents can be adjusted independently using  
resistors RA on pin AVIRES and RB on pin BVIRES.  
In Common gain mode, both full-scale currents are adjusted with the same resistor and  
divided by two in both DACs.  
10.7 Analog outputs  
See Figure 20 for the analog output circuit of one DAC. This circuit consists of a parallel  
combination of PMOS current sources and associated switches for each segment.  
IOUTAP/IOUTBP  
IOUTAN/IOUTBN  
R
L
R
L
AGND  
AGND  
001aai821  
Fig 20. Equivalent analog output circuit  
Cascode source configuration enables the output impedance of the source to be  
increased, thus improving the dynamic performance by reducing distortion.  
The DAC1401D125 can be used either with:  
a differential output, coupled to a transformer (or operational amplifier) to reduce  
even-order harmonics and noise  
or a single-ended output for applications requiring unipolar voltage.  
The typical configuration is to use 1 V p-p level on each output IOUTAP/IOUTBP and  
IOUTAN/IOUTBN but several combinations can be used as far as they respect the voltage  
compliance range.  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
19 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
10.7.1 Differential output using transformer  
The use of a differentially coupled transformer output (see Figure 21) provides optimum  
distortion performance. In addition, it helps to match the impedance and provides  
electrical isolation.  
T1-1T  
IOUTAP/  
IOUTBP  
R
diff  
R
load  
IOUTAN/  
IOUTBN  
1:1  
001aai935  
Fig 21. Differential output with transformer  
The center tap is grounded to allow the DC current flow to/from both outputs. If the center  
tap is open, the differential resistor must be replaced by two resistors connected to  
ground.  
10.7.2 Single-ended output  
Using a single load resistor on one current output will provide an unipolar output range,  
typically from 0 V to 0.5 V with a 20 mA full-scale current at a 50 load.  
20 mA  
Z = 50  
IOUTAP/  
IOUTBP  
50 Ω  
25 Ω  
50 Ω  
0 V to 0.5 V  
IOUTAN/  
IOUTBN  
001aai936  
Fig 22. Single-ended output  
The resistor on the other current output is 25 .  
10.8 Power-down function  
The DAC1404D125 has a power-down function to reduce the power consumption when it  
is not active.  
Table 9.  
Power-down  
PWD  
Device function  
active  
Power dissipation (typ)  
185 mW  
0
1
not active  
16.5 mW  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
20 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
10.9 Alternative parts  
The following alternative parts are also available.  
Table 10. Alternative parts  
Pin compatible  
Type number  
DAC1001D125  
DAC1201D125  
Description  
Sampling frequency  
up to 125 Msps  
dual 10-bit DAC  
dual 12-bit DAC  
up to 125 Msps  
10.10 Application diagram  
R
L
R
L
AGND  
AGND  
AGND  
AGND  
100  
1.5  
kΩ  
AGND  
100 Ω  
100  
nF  
1.5  
kΩ  
3.3 V  
AGND  
48 47 46 45 44 43 42 41 40 39 38 37  
DA13  
1
DB0  
DB1  
DB2  
DB3  
DB4  
DB5  
DB6  
DB7  
DB8  
DB9  
DB10  
DB11  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
DA12  
2
DA11  
3
DA10  
4
DA9  
5
DA8  
6
DAC1401D125  
DA7  
7
DA6  
8
DA5  
9
DA4  
10  
DA3  
DA2  
11  
12  
13 14 15 16 17 18 19 20 21 22 23 24  
100 nF  
100 nF  
3.3 V  
3.3 V  
DGND  
DGND  
001aaj063  
Dual port mode (MODE = 1)  
DAC active (PWD = 0)  
Independent channel gain (GAINCTRL = 0)  
Fig 23. Application diagram  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
21 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
11. Package outline  
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm  
SOT313-2  
c
y
X
36  
25  
A
E
37  
24  
Z
E
e
H
E
A
2
A
(A )  
3
A
1
w M  
p
θ
pin 1 index  
b
L
p
L
13  
48  
detail X  
1
12  
Z
v M  
D
A
e
w M  
b
p
D
B
H
v
M
B
D
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.  
7o  
0o  
0.20 1.45  
0.05 1.35  
0.27 0.18 7.1  
0.17 0.12 6.9  
7.1  
6.9  
9.15 9.15  
8.85 8.85  
0.75  
0.45  
0.95 0.95  
0.55 0.55  
1.6  
mm  
0.25  
0.5  
1
0.2 0.12 0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
00-01-19  
03-02-25  
SOT313-2  
136E05  
MS-026  
Fig 24. Package outline SOT313-2 (LQFP48)  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
22 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
12. Abbreviations  
Table 11. Abbreviations  
Acronym  
BW  
Description  
BandWidth  
DNL  
Differential Non-Linearity  
deciBel Full-Scale  
Intermediate Frequency  
Integral Non-Linearity  
Least Significant Bit  
Most Significant Bit  
dBFS  
IF  
INL  
LSB  
MSB  
PMOS  
SFDR  
Positive-channel Metal-Oxide Semiconductor  
Spurious-Free Dynamic Range  
13. Revision history  
Table 12. Revision history  
Document ID  
Release date  
20081113  
Data sheet status  
Change notice  
Supersedes  
DAC1401D125_1  
Product data sheet  
-
-
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
23 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
14. Legal information  
14.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
to result in personal injury, death or severe property or environmental  
14.2 Definitions  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
14.3 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
14.4 Trademarks  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
15. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
DAC1401D125_1  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 01 — 13 November 2008  
24 of 25  
DAC1401D125  
NXP Semiconductors  
Dual 14-bit DAC, up to 125 Msps  
16. Contents  
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
7
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Thermal characteristics. . . . . . . . . . . . . . . . . . . 5  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
10  
10.1  
10.2  
10.2.1  
10.2.2  
10.3  
10.4  
10.5  
10.6  
10.7  
10.7.1  
10.7.2  
10.8  
Application information. . . . . . . . . . . . . . . . . . 14  
General description. . . . . . . . . . . . . . . . . . . . . 14  
Input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Dual port mode. . . . . . . . . . . . . . . . . . . . . . . . 15  
Interleaved mode . . . . . . . . . . . . . . . . . . . . . . 15  
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
DAC transfer function . . . . . . . . . . . . . . . . . . . 17  
Full-scale current adjustment . . . . . . . . . . . . . 18  
Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Analog outputs . . . . . . . . . . . . . . . . . . . . . . . . 19  
Differential output using transformer. . . . . . . . 20  
Single-ended output . . . . . . . . . . . . . . . . . . . . 20  
Power-down function . . . . . . . . . . . . . . . . . . . 20  
Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 21  
Application diagram . . . . . . . . . . . . . . . . . . . . 21  
10.9  
10.10  
11  
12  
13  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 23  
14  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 24  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
14.1  
14.2  
14.3  
14.4  
15  
16  
Contact information. . . . . . . . . . . . . . . . . . . . . 24  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2008.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 13 November 2008  
Document identifier: DAC1401D125_1  

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NXP

DAC1405D650HW

Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
IDT

DAC1405D750

Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
NXP

DAC1405D750HW

Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
NXP