DSP56303VL100R2_技术文档

DSP56303

Rev. 11, 2/2005

Freescale Semiconductor

Technical Data

DSP56303

24-Bit Digital Signal Processor

16

6

3

Memory Expansion Area

The DSP56303 is intended

for use in telecommunication

applications, such as multi-

line voice/data/ fax

Triple

Timer

X Data

RAM

Y Data

RAM

PrograM

RAM

HI08

ESSI

SCI

2048 × 24

4096 × 24

bits

(default)

processing, video

Peripheral

Expansion Area

conferencing, audio

applications, control, and

general digital signal

processing.

YAB

18

Address

External

XAB

PAB

DAB

Generation

Unit

Address

Bus

Address

Switch

Six-Channel

DMA Unit

External

Bus

24-Bit

13

Interface

and Inst.

Cache

Bootstrap

ROM

DSP56300

Core

Control

DDB

YDB

XDB

PDB

GDB

24

External

Data Bus

Switch

Internal

Data

Bus

What’s New?

Rev. 11 includes the following

changes:

Data

Switch

•

Adds lead-free packaging and

part numbers.

Power

EXTAL

XTAL

Management

Clock

Generator

Data ALU

5

Program

Interrupt

Controller

Program

Decode

Program

Address

Generator

+

→

24 × 24 56 56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

JTAG

PLL

2

Controller

OnCE™

DE

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

PINIT/NMI

Figure 1. DSP56303 Block Diagram

The DSP56303 is a member of the DSP56300 core family of programmable CMOS DSPs. Significant architectural

features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The

DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.0–3.6 volts. The DSP56300 core family

offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power to enable

wireless, telecommunications, and multimedia products.

Table of Contents

Data Sheet Conventions.......................................................................................................................................ii

Features...............................................................................................................................................................iii

Target Applications.............................................................................................................................................iv

Product Documentation ......................................................................................................................................iv

Chapter 1

Signals/Connections

1.1

Power ................................................................................................................................................................1-3

Ground ..............................................................................................................................................................1-3

Clock.................................................................................................................................................................1-4

External Memory Expansion Port (Port A) ......................................................................................................1-4

Interrupt and Mode Control ..............................................................................................................................1-7

Host Interface (HI08)........................................................................................................................................1-8

Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-11

Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-12

Serial Communication Interface (SCI) ...........................................................................................................1-14

Timers .............................................................................................................................................................1-15

JTAG and OnCE Interface ..............................................................................................................................1-16

1.2

1.3

1.5

1.6

1.7

1.8

1.9

1.10

1.11

1.12

Chapter 2

Chapter 3

Chapter 4

Specifications

2.1

2.3

2.4

2.5

Maximum Ratings.............................................................................................................................................2-1

Thermal Characteristics ....................................................................................................................................2-2

DC Electrical Characteristics............................................................................................................................2-2

AC Electrical Characteristics............................................................................................................................2-3

Packaging

3.1

3.2

3.3

3.4

TQFP Package Description...............................................................................................................................3-2

TQFP Package Mechanical Drawing................................................................................................................3-9

MAP-BGA Package Description ....................................................................................................................3-10

MAP-BGA Package Mechanical Drawing .....................................................................................................3-18

Design Considerations

4.1

4.2

4.3

4.4

4.5

Thermal Design Considerations........................................................................................................................4-1

Electrical Design Considerations......................................................................................................................4-2

Power Consumption Considerations.................................................................................................................4-3

PLL Performance Issues ...................................................................................................................................4-4

Input (EXTAL) Jitter Requirements .................................................................................................................4-5

Appendix A

Power Consumption Benchmark

Data Sheet Conventions

OVERBAR

Indicates a signal that is active when pulled low (For example, the RESET pin is active when

low.)

“asserted”

Means that a high true (active high) signal is high or that a low true (active low) signal is low

Means that a high true (active high) signal is low or that a low true (active low) signal is high

“deasserted”

Examples:

Signal/Symbol

Logic State

Signal State

Asserted

Voltage

V_IL/V_OL

True

V_IH/V_OH

V_IL/V_OL

False

True

False

Deasserted

Asserted

Deasserted

Note: Values for V , V_OL, V , and V_OHare defined by individual product specifications.

IL

IH

DSP56303 Technical Data, Rev. 11

ii

Freescale Semiconductor

Features

Table 1 lists the features of the DSP56303 device.

Table 1. DSP56303 Features

Feature

Description

•

100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal

Object code compatible with the DSP56000 core with highly parallel instruction set

• Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel multiplier-accumulator (MAC),

56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional

ALU instructions, and 24-bit or 16-bit arithmetic support under software control

• Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for

DSP applications (including immediate offsets), internal instruction cache controller, internal memory-

expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts

High-Performance

DSP56300 Core

•

Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-

, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and

triggering from interrupt lines and all peripherals

• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock

with skew elimination

•

Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG)

test access port (TAP)

•

Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides

glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs

• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows

six-channel home theater)

Internal Peripherals

•

Serial communications interface (SCI) with baud rate generator

• Triple timer module

• Up to thirty-four programmable general-purpose input/output (GPIO) pins, depending on which peripherals

are enabled

•

192 × 24-bit bootstrap ROM

8 K × 24-bit RAM total

Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:

Program RAM Instruction

X Data RAM

Size

Y Data RAM

Size

Instruction

Cache

Switch Mode

Size

Cache Size

Internal Memories

4096 × 24-bit

3072 × 24-bit

2048 × 24-bit

1024 × 24-bit

0

2048 × 24-bit

3072 × 24-bit

2048 × 24-bit

3072 × 24-bit

disabled

enabled

disabled

enabled

disabled

enabled

1024 × 24-bit

0

1024 × 24-bit

• Data memory expansion to two 256 K × 24-bit word memory spaces using the standard external address

lines

• Program memory expansion to one 256 K × 24-bit words memory space using the standard external

address lines

• External memory expansion port

External Memory

Expansion

• Chip select logic for glueless interface to static random access memory (SRAMs)

• Internal DRAM Controller for glueless interface to dynamic random access memory (DRAMs)

•

Very low-power CMOS design

Wait and Stop low-power standby modes

• Fully static design specified to operate down to 0 Hz (dc)

• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-

dependent)

Power Dissipation

Packaging

• 144-pin TQFP package in lead-free or lead-bearing versions

• 196-pin molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

iii

Target Applications

Examples include:

•

Multi-line voice/data/fax processing

Video conferencing

Audio applications

Control

Product Documentation

The documents listed in Table 2 are required for a complete description of the DSP56303 device and are necessary

to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale

semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation

updates, visit the Freescale DSP website. See the contact information on the back cover of this document.

Table 2. DSP56303 Documentation

Name

DSP56303

Description

Order Number

DSP56303UM

Detailed functional description of the DSP56303 memory configuration,

operation, and register programming

User’s Manual

DSP56300 Family Detailed description of the DSP56300 family processor core and instruction set DSP56300FM

Manual

Application Notes Documents describing specific applications or optimized device operation

including code examples

See the DSP56303 product website

DSP56303 Technical Data, Rev. 11

iv

Freescale Semiconductor

Signals/Connections

1

The DSP56303 input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1

diagrams the DSP56303 signals by functional group. The remainder of this chapter describes the signal pins in

each functional group.

Table 1-1. DSP56303 Functional Signal Groupings

Number of Signals

Functional Group

TQFP

MAP-BGA

Power (V_CC

)

18

19

2

18

66

2

Ground (GND)

Clock

PLL

3

Address bus

18

24

13

5

18

24

13

5

Data bus

Port A¹

Bus control

Interrupt and mode control

Host interface (HI08)

Enhanced synchronous serial interface (ESSI)

Serial communication interface (SCI)

Timer

Port B²

Ports C and D³

Port E⁴

16

12

3

16

12

3

OnCE/JTAG Port

6

Notes: 1. Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.

2. Port B signals are the HI08 port signals multiplexed with the GPIO signals.

3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.

4. Port E signals are the SCI port signals multiplexed with the GPIO signals.

5. There are 2 signal connections in the TQFP package and 7 signal connections in the MAP-BGA package that are not used.

These are designated as no connect (NC) in the package description (see Chapter 3).

Note: This chapter refers to a number of configuration registers used to select individual multiplexed signal

functionality. Refer to the DSP56303 User’s Manual for details on these configuration registers.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

1-1

Signals/Connections

After Reset

IRQA

IRQB

IRQC

IRQD

During Reset

MODA

MODB

MODC

MODD

DSP56303

Interrupt/

Mode Control

Power Inputs:

V_CCP

V_CCQ

V_CCA

V_CCD

V_CCC

V_CCH

V_CCS

PLL

4

2

Internal Logic

Address Bus

Data Bus

RESET

Non-Multiplexed Multiplexed

Port B

GPIO

PB[0–7]

PB8

PB9

PB10

PB13

Bus Control

HI08

Bus

H[0–7]

HA0

HA1

Bus

8

HAD[0–7]

HAS/HAS

HA8

HA9

HA10

Double DS

HRD/HRD

HWR/HWR

Double HR

HTRQ/HTRQ PB14

HRRQ/HRRQ PB15

2

ESSI/SCI/Timer

Host

Interface

Grounds⁴:

PLL

HA2

(HI08) Port¹

HCS/HCS

Single DS

HRW

HDS/HDS

Single HR

HREQ/HREQ

HACK/HACK

GND_P

GND_P1

GND_Q

GND_A

GND_D

GND_C

GND_H

GND_S

4

PB11

PB12

Internal Logic

Address Bus

Data Bus

Bus Control

HI08

4

2

ESSI/SCI/Timer

Port C GPIO

PC[0–2]

PC3

PC4

PC5

3

Enhanced

Synchronous Serial

Interface Port 0

(ESSI0)²

SC0[0–2]

SCK0

SRD0

EXTAL

XTAL

Clock

PLL

STD0

CLKOUT

PCAP

Port D GPIO

PD[0–2]

PD3

PD4

PD5

3

Enhanced

Synchronous Serial

Interface Port 1

(ESSI1)²

SC1[0–2]

SCK1

SRD1

After

Reset

NMI

During

Reset

PINIT

STD1

Port A

18

External

Address Bus

A[0–17]

D[0–23]

Port E GPIO

PE0

PE1

Serial

Communications

RXD

TXD

SCLK

24

4

Interface (SCI) Port²

External

Data Bus

PE2

AA0/RAS0–

AA3/RAS3

RD

Timer GPIO

TIO0

TIO1

External

Bus

Control

TIO0

TIO1

TIO2

Timers³

WR

TA

TIO2

BR

BG

BB

CAS

BCLK

TCK

TDI

TDO

TMS

TRST

DE

OnCE/

JTAG Port

Notes: 1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or

double Host Request (HR) configurations. Since each of these modes is configured independently, any combination

of these modes is possible. These HI08 signals can also be configured alternatively as GPIO signals (PB[0–15]).

Signals with dual designations (for example, HAS/HAS) have configurable polarity.

2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals

(PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.

3. TIO[0–2] can be configured as GPIO signals.

4. Ground connections shown in this figure are for the TQFP package. In the MAP-BGA package, in addition to the

GND_Pand GND_P1connections, there are 64 GND connections to a common internal package ground plane.

Figure 1-1. Signals Identified by Functional Group

DSP56303 Technical Data, Rev. 11

1-2

Freescale Semiconductor

Power

1.1 Power

Table 1-2. Power Inputs

Power Name

Description

V_CCP

V_CCQ

V_CCA

V_CCD

V_CCC

V_CCH

V_CCS

PLL Power—V_CCdedicated for PLL use. The voltage should be well-regulated and the input should be provided with

an extremely low impedance path to the V_CCpower rail.

Quiet Power—An isolated power for the core processing logic. This input must be isolated externally from all other chip

power inputs.

Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input must be tied externally

to all other chip power inputs, except V_CCQ

Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all

other chip power inputs, except V_CCQ

Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied externally to all other

chip power inputs, except V_CCQ

Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power

inputs, except V_CCQ

ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied

externally to all other chip power inputs, except V_CCQ

.

Note: The user must provide adequate external decoupling capacitors for all power connections.

1.2 Ground

1

Table 1-3. Grounds

Ground Name

Description

GND_P

PLL Ground—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance

path to ground. V_CCPshould be bypassed to GND_Pby a 0.47 µF capacitor located as close as possible to the chip

package.

GND_P1

PLL Ground 1—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance

path to ground.

2

GND_Q

Quiet Ground—An isolated ground for the internal processing logic. This connection must be tied externally to all other

chip ground connections, except GND_Pand GND_P1. The user must provide adequate external decoupling capacitors.

2

GND_A

Address Bus Ground—An isolated ground for sections of the address bus I/O drivers. This connection must be tied

externally to all other chip ground connections, except GND_Pand GND_P1. The user must provide adequate external

decoupling capacitors.

2

GND_D

Data Bus Ground—An isolated ground for sections of the data bus I/O drivers. This connection must be tied externally

to all other chip ground connections, except GND_Pand GND_P1. The user must provide adequate external decoupling

capacitors.

2

GND_C

Bus Control Ground—An isolated ground for the bus control I/O drivers. This connection must be tied externally to all

other chip ground connections, except GND_Pand GND_P1. The user must provide adequate external decoupling

capacitors.

2

GND_H

Host Ground—An isolated ground for the HI08 I/O drivers. This connection must be tied externally to all other chip

ground connections, except GND_Pand GND_P1. The user must provide adequate external decoupling capacitors.

2

GND_S

ESSI, SCI, and Timer Ground—An isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be

tied externally to all other chip ground connections, except GND_Pand GND_P1. The user must provide adequate external

decoupling capacitors.

GND³

Ground—Connected to an internal device ground plane.

Notes: 1. The user must provide adequate external decoupling capacitors for all GND connections.

2. These connections are only used on the TQFP package.

3. These connections are common grounds used on the MAP-BGA package.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

1-3

Signals/Connections

1.3 Clock

Table 1-4. Clock Signals

State During

Signal Name

Type

Signal Description

Reset

EXTAL

XTAL

Input

Output

Input

External Clock/Crystal Input—Interfaces the internal crystal oscillator input

to an external crystal or an external clock.

Chip-driven

Crystal Output—Connects the internal crystal oscillator output to an external

crystal. If an external clock is used, leave XTAL unconnected.

1.4 PLL

Table 1-5. Phase-Locked Loop Signals

State During

Reset

Signal Name

Type

Output

Signal Description

CLKOUT

Chip-driven

Clock Output—Provides an output clock synchronized to the internal core

clock phase.

If the PLL is enabled and both the multiplication and division factors equal one,

then CLKOUT is also synchronized to EXTAL.

If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.

PCAP

Input

PLL Capacitor—An input connecting an off-chip capacitor to the PLL filter.

Connect one capacitor terminal to PCAP and the other terminal to V_CCP

.

If the PLL is not used, PCAP can be tied to V_CC, GND, or left floating.

PINIT

NMI

Input

PLL Initial—During assertion of RESET, the value of PINIT is written into the

PLL enable (PEN) bit of the PLL control (PCTL) register, determining whether

the PLL is enabled or disabled.

Nonmaskable Interrupt—After RESET deassertion and during normal

instruction processing, this Schmitt-trigger input is the negative-edge-triggered

NMI request internally synchronized to CLKOUT.

Note: PINIT/NMI can tolerate 5 V.

1.5 External Memory Expansion Port (Port A)

Note: When the DSP56303 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-

states the relevant Port A signals: A[0–17], D[0–23], AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS.

1.5.1 External Address Bus

Table 1-6. External Address Bus Signals

State During

Signal Name

Type Reset, Stop, or

Wait

Signal Description

A[0–17]

Output

Tri-stated

Address Bus—When the DSP is the bus master, A[0–17] are active-high outputs that

specify the address for external program and data memory accesses. Otherwise, the

signals are tri-stated. To minimize power dissipation, A[0–17] do not change state when

external memory spaces are not being accessed.

DSP56303 Technical Data, Rev. 11

1-4

Freescale Semiconductor

External Memory Expansion Port (Port A)

1.5.2 External Data Bus

Table 1-7. External Data Bus Signals

State

During

Reset

State

During Stop

or Wait

Signal

Name

Type

Signal Description

D[0–23]

Input/ Output

Ignored Input Last state:

Data Bus—When the DSP is the bus master, D[0–23] are active-high,

Input: Ignored bidirectional input/outputs that provide the bidirectional data bus for external

Output:

program and data memory accesses. Otherwise, D[0–23] are tri-stated.

Tri-stated

1.5.3 External Bus Control

Table 1-8. External Bus Control Signals

Signal

Name

State During Reset,

Stop, or Wait

Type

Signal Description

AA[0–3]

Output

Tri-stated

Address Attribute—When defined as AA, these signals can be used as chip selects or

additional address lines. The default use defines a priority scheme under which only

one AA signal can be asserted at a time. Setting the AA priority disable (APD) bit (Bit

14) of the Operating Mode Register, the priority mechanism is disabled and the lines

can be used together as four external lines that can be decoded externally into 16 chip

select signals.

RAS[0–3]

RD

Output

Row Address Strobe—When defined as RAS, these signals can be used as RAS for

DRAM interface. These signals are tri-statable outputs with programmable polarity.

Tri-stated

Read Enable—When the DSP is the bus master, RD is an active-low output that is

asserted to read external memory on the data bus (D[0–23]). Otherwise, RD is tri-

stated.

WR

TA

Output

Input

Tri-stated

Write Enable—When the DSP is the bus master, WR is an active-low output that is

asserted to write external memory on the data bus (D[0–23]). Otherwise, the signals

are tri-stated.

Ignored Input

Transfer Acknowledge—If the DSP56303 is the bus master and there is no external

bus activity, or the DSP56303 is not the bus master, the TA input is ignored. The TA

input is a data transfer acknowledge (DTACK) function that can extend an external bus

cycle indefinitely. Any number of wait states (1, 2. . .infinity) can be added to the wait

states inserted by the bus control register (BCR) by keeping TA deasserted. In typical

operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion

of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle

completes one clock period after TA is asserted synchronous to CLKOUT. The number

of wait states is determined by the TA input or by the BCR, whichever is longer. The

BCR can be used to set the minimum number of wait states in external bus cycles.

To use the TA functionality, the BCR must be programmed to at least one wait state. A

zero wait state access cannot be extended by TA deassertion; otherwise, improper

operation may result. TA can operate synchronously or asynchronously depending on

the setting of the TAS bit in the Operating Mode Register. TA functionality cannot be

used during DRAM type accesses; otherwise improper operation may result.

BR

Output

Reset: Output

(deasserted)

Bus Request—Asserted when the DSP requests bus mastership. BR is deasserted

when the DSP no longer needs the bus. BR may be asserted or deasserted

independently of whether the DSP56303 is a bus master or a bus slave. Bus “parking”

allows BR to be deasserted even though the DSP56303 is the bus master. (See the

description of bus “parking” in the BB signal description.) The bus request hold (BRH)

bit in the BCR allows BR to be asserted under software control even though the DSP

does not need the bus. BR is typically sent to an external bus arbitrator that controls the

priority, parking, and tenure of each master on the same external bus. BR is affected

State during Stop/Wait

depends on BRH bit

setting:

• BRH = 0: Output,

deasserted

• BRH = 1: Maintains last only by DSP requests for the external bus, never for the internal bus. During hardware

state (that is, if asserted,

remains asserted)

reset, BR is deasserted and the arbitration is reset to the bus slave state.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

1-5

Signals/Connections

Table 1-8. External Bus Control Signals (Continued)

Signal

Type

State During Reset,

Stop, or Wait

Signal Description

Name

BG

Input

Ignored Input

Bus Grant—Asserted by an external bus arbitration circuit when the DSP56303

becomes the next bus master. When BG is asserted, the DSP56303 must wait until BB

is deasserted before taking bus mastership. When BG is deasserted, bus mastership is

typically given up at the end of the current bus cycle. This may occur in the middle of an

instruction that requires more than one external bus cycle for execution.

The default operation of this bit requires a setup and hold time as specified in Table 2-

14. An alternate mode can be invoked: set the asynchronous bus arbitration enable

(ABE) bit (Bit 13) in the Operating Mode Register. When this bit is set, BG and BB are

synchronized internally. This eliminates the respective setup and hold time

requirements but adds a required delay between the deassertion of an initial BG input

and the assertion of a subsequent BG input.

BB

Input/

Output

Ignored Input

Bus Busy—Indicates that the bus is active. Only after BB is deasserted can the

pending bus master become the bus master (and then assert the signal again). The

bus master may keep BB asserted after ceasing bus activity regardless of whether BR

is asserted or deasserted. Called “bus parking,” this allows the current bus master to

reuse the bus without rearbitration until another device requires the bus. BB is

deasserted by an “active pull-up” method (that is, BB is driven high and then released

and held high by an external pull-up resistor).

The default operation of this signal requires a setup and hold time as specified in Table

2-14. An alternative mode can be invoked by setting the ABE bit (Bit 13) in the

Operating Mode Register. When this bit is set, BG and BB are synchronized internally.

See BG for additional information.

Note: BB requires an external pull-up resistor.

CAS

Output

Tri-stated

Column Address Strobe—When the DSP is the bus master, CAS is an active-low

output used by DRAM to strobe the column address. Otherwise, if the Bus Mastership

Enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated.

BCLK

Bus Clock

When the DSP is the bus master, BCLK is active when the Operating Mode Register

Address Trace Enable bit is set. When BCLK is active and synchronized to CLKOUT by

the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle.

BCLK

Output

Tri-stated

Bus Clock Not

When the DSP is the bus master, BCLK is the inverse of the BCLK signal. Otherwise,

the signal is tri-stated.

DSP56303 Technical Data, Rev. 11

1-6

Freescale Semiconductor

Interrupt and Mode Control

1.6 Interrupt and Mode Control

The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. After

RESET is deasserted, these inputs are hardware interrupt request lines.

Table 1-9. Interrupt and Mode Control

State During

Signal Name

RESET

Type

Input

Signal Description

Reset

Schmitt-trigger

Input

Reset—Places the chip in the Reset state and resets the internal phase

generator. The Schmitt-trigger input allows a slowly rising input (such as a

capacitor charging) to reset the chip reliably. When the RESET signal is

deasserted, the initial chip operating mode is latched from the MODA, MODB,

MODC, and MODD inputs. The RESET signal must be asserted after powerup.

Input

Schmitt-trigger

Input

Mode Select A—MODA, MODB, MODC, and MODD select one of 16 initial

chip operating modes, latched into the Operating Mode Register when the

RESET signal is deasserted.

MODA

External Interrupt Request A—After reset, this input becomes a level-

sensitive or negative-edge-triggered, maskable interrupt request input during

normal instruction processing. If the processor is in the STOP or WAIT standby

state and IRQA is asserted, the processor exits the STOP or WAIT state.

IRQA

Input

Schmitt-trigger

Input

Mode Select B—MODA, MODB, MODC, and MODD select one of 16 initial

chip operating modes, latched into the Operating Mode Register when the

RESET signal is deasserted.

MODB

External Interrupt Request B—After reset, this input becomes a level-

sensitive or negative-edge-triggered, maskable interrupt request input during

normal instruction processing. If the processor is in the WAIT standby state and

IRQB is asserted, the processor exits the WAIT state.

IRQB

Input

Schmitt-trigger

Input

Mode Select C—MODA, MODB, MODC, and MODD select one of 16 initial

chip operating modes, latched into the Operating Mode Register when the

RESET signal is deasserted.

MODC

External Interrupt Request C—After reset, this input becomes a level-

sensitive or negative-edge-triggered, maskable interrupt request input during

normal instruction processing. If the processor is in the WAIT standby state and

IRQC is asserted, the processor exits the WAIT state.

IRQC

Input

Schmitt-trigger

Input

Mode Select D—MODA, MODB, MODC, and MODD select one of 16 initial

chip operating modes, latched into the Operating Mode Register when the

RESET signal is deasserted.

MODD

External Interrupt Request D—After reset, this input becomes a level-

sensitive or negative-edge-triggered, maskable interrupt request input during

normal instruction processing. If the processor is in the WAIT standby state and

IRQD is asserted, the processor exits the WAIT state.

IRQD

Note: These signals are all 5 V tolerant.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

1-7

Signals/Connections

1.7 Host Interface (HI08)

The HI08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. The HI08 supports a variety

of standard buses and connects directly to a number of industry-standard microcomputers, microprocessors, DSPs,

and DMA hardware.

1.7.1 Host Port Usage Considerations

Careful synchronization is required when the system reads multiple-bit registers that are written by another

asynchronous system. This is a common problem when two asynchronous systems are connected (as they are in the

Host port). The considerations for proper operation are discussed in Table 1-10.

Table 1-10. Host Port Usage Considerations

Action

Description

Asynchronous read of receive byte

registers

When reading the receive byte registers, Receive register High (RXH), Receive register Middle

(RXM), or Receive register Low (RXL), the host interface programmer should use interrupts or poll

the Receive register Data Full (RXDF) flag that indicates data is available. This assures that the data

in the receive byte registers is valid.

Asynchronous write to transmit byte

registers

The host interface programmer should not write to the transmit byte registers, Transmit register High

(TXH), Transmit register Middle (TXM), or Transmit register Low (TXL), unless the Transmit register

Data Empty (TXDE) bit is set indicating that the transmit byte registers are empty. This guarantees

that the transmit byte registers transfer valid data to the Host Receive (HRX) register.

Asynchronous write to host vector

The host interface programmer must change the Host Vector (HV) register only when the Host

Command bit (HC) is clear. This practice guarantees that the DSP interrupt control logic receives a

stable vector.

1.7.2 Host Port Configuration

HI08 signal functions vary according to the programmed configuration of the interface as determined by the 16 bits

in the HI08 Port Control Register.

Table 1-11. Host Interface

State During

Reset

Signal Name

H[0–7]

Type

Signal Description

1,2

Input/Output

Ignored Input

Host Data—When the HI08 is programmed to interface with a non-multiplexed

host bus and the HI function is selected, these signals are lines 0–7 of the

bidirectional Data bus.

HAD[0–7]

PB[0–7]

Input/Output

Host Address—When the HI08 is programmed to interface with a multiplexed

host bus and the HI function is selected, these signals are lines 0–7 of the

bidirectional multiplexed Address/Data bus.

Input or Output

Port B 0–7—When the HI08 is configured as GPIO through the HI08 Port

Control Register, these signals are individually programmed as inputs or outputs

through the HI08 Data Direction Register.

DSP56303 Technical Data, Rev. 11

1-8

Freescale Semiconductor

Host Interface (HI08)

Table 1-11. Host Interface (Continued)

State During

Reset

Signal Name

HA0

Type

Signal Description

Host Address Input 0—When the HI08 is programmed to interface with a

1,2

Input

Ignored Input

nonmultiplexed host bus and the HI function is selected, this signal is line 0 of

the host address input bus.

HAS/HAS

Input

Host Address Strobe—When the HI08 is programmed to interface with a

multiplexed host bus and the HI function is selected, this signal is the host

address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is

programmable but is configured active-low (HAS) following reset.

PB8

HA1

Input or Output

Input

Port B 8—When the HI08 is configured as GPIO through the HI08 Port Control

Register, this signal is individually programmed as an input or output through the

HI08 Data Direction Register.

Ignored Input

Host Address Input 1—When the HI08 is programmed to interface with a

nonmultiplexed host bus and the HI function is selected, this signal is line 1 of

the host address (HA1) input bus.

HA8

Input

Host Address 8—When the HI08 is programmed to interface with a multiplexed

host bus and the HI function is selected, this signal is line 8 of the host address

(HA8) input bus.

PB9

HA2

Input or Output

Input

Port B 9—When the HI08 is configured as GPIO through the HI08 Port Control

Register, this signal is individually programmed as an input or output through the

HI08 Data Direction Register.

Host Address Input 2—When the HI08 is programmed to interface with a

nonmultiplexed host bus and the HI function is selected, this signal is line 2 of

the host address (HA2) input bus.

HA9

Input

Host Address 9—When the HI08 is programmed to interface with a multiplexed

host bus and the HI function is selected, this signal is line 9 of the host address

(HA9) input bus.

PB10

Input or Output

Input

Port B 10—When the HI08 is configured as GPIO through the HI08 Port Control

Register, this signal is individually programmed as an input or output through the

HI08 Data Direction Register.

HCS/HCS

Host Chip Select—When the HI08 is programmed to interface with a

nonmultiplexed host bus and the HI function is selected, this signal is the host

chip select (HCS) input. The polarity of the chip select is programmable but is

configured active-low (HCS) after reset.

HA10

Input

Host Address 10—When the HI08 is programmed to interface with a

multiplexed host bus and the HI function is selected, this signal is line 10 of the

host address (HA10) input bus.

PB13

HRW

Input or Output

Input

Port B 13—When the HI08 is configured as GPIO through the HI08 Port Control

Register, this signal is individually programmed as an input or output through the

HI08 Data Direction Register.

Ignored Input

Host Read/Write—When the HI08 is programmed to interface with a single-

data-strobe host bus and the HI function is selected, this signal is the Host

Read/Write (HRW) input.

HRD/HRD

PB11

Input

Host Read Data—When the HI08 is programmed to interface with a double-

data-strobe host bus and the HI function is selected, this signal is the HRD

strobe Schmitt-trigger input. The polarity of the data strobe is programmable but

is configured as active-low (HRD) after reset.

Input or Output

Port B 11—When the HI08 is configured as GPIO through the HI08 Port Control

Register, this signal is individually programmed as an input or output through the

HI08 Data Direction Register.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

1-9

Signals/Connections

Table 1-11. Host Interface (Continued)

State During

Reset

Signal Name

Type

Signal Description

1,2

HDS/HDS

Input

Ignored Input

Host Data Strobe—When the HI08 is programmed to interface with a single-

data-strobe host bus and the HI function is selected, this signal is the host data

strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is

programmable but is configured as active-low (HDS) following reset.

HWR/HWR

Input

Host Write Data—When the HI08 is programmed to interface with a double-

data-strobe host bus and the HI function is selected, this signal is the host write

data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is

programmable but is configured as active-low (HWR) following reset.

PB12

Input or Output

Output

Port B 12—When the HI08 is configured as GPIO through the HI08 Port Control

Register, this signal is individually programmed as an input or output through the

HI08 Data Direction Register.

HREQ/HREQ

Ignored Input

Host Request—When the HI08 is programmed to interface with a single host

request host bus and the HI function is selected, this signal is the host request

(HREQ) output. The polarity of the host request is programmable but is

configured as active-low (HREQ) following reset. The host request may be

programmed as a driven or open-drain output.

HTRQ/HTRQ

Output

Transmit Host Request—When the HI08 is programmed to interface with a

double host request host bus and the HI function is selected, this signal is the

transmit host request (HTRQ) output. The polarity of the host request is

programmable but is configured as active-low (HTRQ) following reset. The host

request may be programmed as a driven or open-drain output.

PB14

Input or Output

Input

Port B 14—When the HI08 is configured as GPIO through the HI08 Port Control

Register, this signal is individually programmed as an input or output through the

HI08 Data Direction Register.

HACK/HACK

Ignored Input

Host Acknowledge—When the HI08 is programmed to interface with a single

host request host bus and the HI function is selected, this signal is the host

acknowledge (HACK) Schmitt-trigger input. The polarity of the host

acknowledge is programmable but is configured as active-low (HACK) after

reset.

HRRQ/HRRQ

Output

Receive Host Request—When the HI08 is programmed to interface with a

double host request host bus and the HI function is selected, this signal is the

receive host request (HRRQ) output. The polarity of the host request is

programmable but is configured as active-low (HRRQ) after reset. The host

request may be programmed as a driven or open-drain output.

PB15

Input or Output

Port B 15—When the HI08 is configured as GPIO through the HI08 Port Control

Register, this signal is individually programmed as an input or output through the

HI08 Data Direction Register.

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, the signal is tri-stated.

2. The Wait processing state does not affect the signal state.

3. All inputs are 5 V tolerant.

DSP56303 Technical Data, Rev. 11

1-10

Freescale Semiconductor

Enhanced Synchronous Serial Interface 0 (ESSI0)

1.8 Enhanced Synchronous Serial Interface 0 (ESSI0)

Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication

with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and

peripherals that implement the serial peripheral interface (SPI).

Table 1-12. Enhanced Synchronous Serial Interface 0

State During

Reset

Signal Name

SC00

Type

Signal Description

1,2

Input or Output

Ignored Input

Serial Control 0—For asynchronous mode, this signal is used for the receive

clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used

either for transmitter 1 output or for serial I/O flag 0.

PC0

Input or Output

Port C 0—The default configuration following reset is GPIO input PC0. When

configured as PC0, signal direction is controlled through the Port C Direction

Register. The signal can be configured as ESSI signal SC00 through the Port C

Control Register.

SC01

PC1

Input/Output

Serial Control 1—For asynchronous mode, this signal is the receiver frame

sync I/O. For synchronous mode, this signal is used either for transmitter 2

output or for serial I/O flag 1.

Input or Output

Port C 1—The default configuration following reset is GPIO input PC1. When

configured as PC1, signal direction is controlled through the Port C Direction

Register. The signal can be configured as an ESSI signal SC01 through the Port

C Control Register.

SC02

Input/Output

Serial Control Signal 2—The frame sync for both the transmitter and receiver

in synchronous mode, and for the transmitter only in asynchronous mode. When

configured as an output, this signal is the internally generated frame sync signal.

When configured as an input, this signal receives an external frame sync signal

for the transmitter (and the receiver in synchronous operation).

PC2

Input or Output

Input/Output

Port C 2—The default configuration following reset is GPIO input PC2. When

configured as PC2, signal direction is controlled through the Port C Direction

Register. The signal can be configured as an ESSI signal SC02 through the Port

C Control Register.

SCK0

Ignored Input

Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK0 is a

clock input or output, used by both the transmitter and receiver in synchronous

modes or by the transmitter in asynchronous modes.

Although an external serial clock can be independent of and asynchronous to

the DSP system clock, it must exceed the minimum clock cycle time of 6T (that

is, the system clock frequency must be at least three times the external ESSI

clock frequency). The ESSI needs at least three DSP phases inside each half of

the serial clock.

PC3

Input or Output

Port C 3—The default configuration following reset is GPIO input PC3. When

configured as PC3, signal direction is controlled through the Port C Direction

Register. The signal can be configured as an ESSI signal SCK0 through the Port

C Control Register.

SRD0

PC4

Input

Ignored Input

Serial Receive Data—Receives serial data and transfers the data to the ESSI

Receive Shift Register. SRD0 is an input when data is received.

Input or Output

Port C 4—The default configuration following reset is GPIO input PC4. When

configured as PC4, signal direction is controlled through the Port C Direction

Register. The signal can be configured as an ESSI signal SRD0 through the

Port C Control Register.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

1-11

Signals/Connections

Signal Name

Table 1-12. Enhanced Synchronous Serial Interface 0 (Continued)

State During

Type

Signal Description

1,2

Reset

STD0

PC5

Output

Ignored Input

Serial Transmit Data—Transmits data from the Serial Transmit Shift Register.

STD0 is an output when data is transmitted.

Input or Output

Port C 5—The default configuration following reset is GPIO input PC5. When

configured as PC5, signal direction is controlled through the Port C Direction

Register. The signal can be configured as an ESSI signal STD0 through the Port

C Control Register.

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, the signal is tri-stated.

2. The Wait processing state does not affect the signal state.

3. All inputs are 5 V tolerant.

1.9 Enhanced Synchronous Serial Interface 1 (ESSI1)

Table 1-13. Enhanced Serial Synchronous Interface 1

State During

Reset

Signal Name

SC10

Type

Signal Description

1,2

Input or Output

Ignored Input

Serial Control 0—For asynchronous mode, this signal is used for the receive

clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used

either for transmitter 1 output or for serial I/O flag 0.

PD0

Input or Output

Port D 0—The default configuration following reset is GPIO input PD0. When

configured as PD0, signal direction is controlled through the Port D Direction

Register. The signal can be configured as an ESSI signal SC10 through the Port

D Control Register.

SC11

PD1

Input/Output

Serial Control 1—For asynchronous mode, this signal is the receiver frame

sync I/O. For synchronous mode, this signal is used either for Transmitter 2

output or for Serial I/O Flag 1.

Input or Output

Port D 1—The default configuration following reset is GPIO input PD1. When

configured as PD1, signal direction is controlled through the Port D Direction

Register. The signal can be configured as an ESSI signal SC11 through the Port

D Control Register.

SC12

PD2

Input/Output

Serial Control Signal 2—The frame sync for both the transmitter and receiver

in synchronous mode and for the transmitter only in asynchronous mode. When

configured as an output, this signal is the internally generated frame sync signal.

When configured as an input, this signal receives an external frame sync signal

for the transmitter (and the receiver in synchronous operation).

Input or Output

Port D 2—The default configuration following reset is GPIO input PD2. When

configured as PD2, signal direction is controlled through the Port D Direction

Register. The signal can be configured as an ESSI signal SC12 through the Port

D Control Register.

DSP56303 Technical Data, Rev. 11

1-12

Freescale Semiconductor

Enhanced Synchronous Serial Interface 1 (ESSI1)

Table 1-13. Enhanced Serial Synchronous Interface 1 (Continued)

State During

Reset

Signal Name

SCK1

Type

Signal Description

1,2

Input/Output

Ignored Input

Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK1 is a

clock input or output used by both the transmitter and receiver in synchronous

modes or by the transmitter in asynchronous modes.

Although an external serial clock can be independent of and asynchronous to

the DSP system clock, it must exceed the minimum clock cycle time of 6T (that

is, the system clock frequency must be at least three times the external ESSI

clock frequency). The ESSI needs at least three DSP phases inside each half of

the serial clock.

PD3

Input or Output

Port D 3—The default configuration following reset is GPIO input PD3. When

configured as PD3, signal direction is controlled through the Port D Direction

Register. The signal can be configured as an ESSI signal SCK1 through the Port

D Control Register.

SRD1

PD4

Input

Ignored Input

Serial Receive Data—Receives serial data and transfers the data to the ESSI

Receive Shift Register. SRD1 is an input when data is being received.

Input or Output

Port D 4—The default configuration following reset is GPIO input PD4. When

configured as PD4, signal direction is controlled through the Port D Direction

Register. The signal can be configured as an ESSI signal SRD1 through the

Port D Control Register.

STD1

PD5

Output

Serial Transmit Data—Transmits data from the Serial Transmit Shift Register.

STD1 is an output when data is being transmitted.

Input or Output

Port D 5—The default configuration following reset is GPIO input PD5. When

configured as PD5, signal direction is controlled through the Port D Direction

Register. The signal can be configured as an ESSI signal STD1 through the Port

D Control Register.

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, the signal is tri-stated.

2. The Wait processing state does not affect the signal state.

3. All inputs are 5 V tolerant.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

1-13

Signals/Connections

1.10 Serial Communication Interface (SCI)

The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals

such as modems.

Table 1-14. Serial Communication Interface

State During

Reset

Signal Name

RXD

Type

Signal Description

1,2

Input

Ignored Input

Serial Receive Data—Receives byte-oriented serial data and transfers it to the

SCI Receive Shift Register.

PE0

Input or Output

Port E 0—The default configuration following reset is GPIO input PE0. When

configured as PE0, signal direction is controlled through the Port E Direction

Register. The signal can be configured as an SCI signal RXD through the Port E

Control Register.

TXD

PE1

Output

Ignored Input

Serial Transmit Data—Transmits data from the SCI Transmit Data Register.

Input or Output

Port E 1—The default configuration following reset is GPIO input PE1. When

configured as PE1, signal direction is controlled through the Port E Direction

Register. The signal can be configured as an SCI signal TXD through the Port E

Control Register.

SCLK

PE2

Input/Output

Serial Clock—Provides the input or output clock used by the transmitter and/or

the receiver.

Input or Output

Port E 2—The default configuration following reset is GPIO input PE2. When

configured as PE2, signal direction is controlled through the Port E Direction

Register. The signal can be configured as an SCI signal SCLK through the Port

E Control Register.

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, the signal is tri-stated.

2. The Wait processing state does not affect the signal state.

3. All inputs are 5 V tolerant.

DSP56303 Technical Data, Rev. 11

1-14

Freescale Semiconductor

Timers

1.11 Timers

The DSP56303 has three identical and independent timers. Each timer can use internal or external clocking and can

either interrupt the DSP56303 after a specified number of events (clocks) or signal an external device after

counting a specific number of internal events.

Table 1-15. Triple Timer Signals

State During

Signal Name

TIO0

Type

Signal Description

1,2

Reset

Input or Output

Ignored Input

Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions as an

external event counter or in measurement mode, TIO0 is used as input. When

Timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used

as output.

The default mode after reset is GPIO input. TIO0 can be changed to output or

configured as a timer I/O through the Timer 0 Control/Status Register (TCSR0).

TIO1

TIO2

Input or Output

Timer 1 Schmitt-Trigger Input/Output— When Timer 1 functions as an

external event counter or in measurement mode, TIO1 is used as input. When

Timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used

as output.

The default mode after reset is GPIO input. TIO1 can be changed to output or

configured as a timer I/O through the Timer 1 Control/Status Register (TCSR1).

Input or Output

Timer 2 Schmitt-Trigger Input/Output— When Timer 2 functions as an

external event counter or in measurement mode, TIO2 is used as input. When

Timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used

as output.

The default mode after reset is GPIO input. TIO2 can be changed to output or

configured as a timer I/O through the Timer 2 Control/Status Register (TCSR2).

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, the signal is tri-stated.

2. The Wait processing state does not affect the signal state.

3. All inputs are 5 V tolerant.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

1-15

Signals/Connections

1.12 JTAG and OnCE Interface

The DSP56300 family and in particular the DSP56303 support circuit-board test strategies based on the IEEE®

Std. 1149.1™ test access port and boundary scan architecture, the industry standard developed under the

sponsorship of the Test Technology Committee of IEEE and the JTAG. The OnCE module provides a means to

interface nonintrusively with the DSP56300 core and its peripherals so that you can examine registers, memory, or

on-chip peripherals. Functions of the OnCE module are provided through the JTAG TAP signals. For programming

models, see the chapter on debugging support in the DSP56300 Family Manual.

Table 1-16. JTAG/OnCE Interface

Signal

Name

State During

Reset

Type

Signal Description

TCK

TDI

Input

Test Clock—A test clock input signal to synchronize the JTAG test logic.

Test Data Input—A test data serial input signal for test instructions and data.

TDI is sampled on the rising edge of TCK and has an internal pull-up resistor.

TDO

TMS

Output

Tri-stated

Test Data Output—A test data serial output signal for test instructions and

data. TDO is actively driven in the shift-IR and shift-DR controller states. TDO

changes on the falling edge of TCK.

Input

Test Mode Select—Sequences the test controller’s state machine. TMS is

sampled on the rising edge of TCK and has an internal pull-up resistor.

TRST

DE

Test Reset—Initializes the test controller asynchronously. TRST has an

internal pull-up resistor. TRST must be asserted after powerup.

Input/ Output

(open-drain)

Debug Event—As an input, initiates Debug mode from an external command

controller, and, as an open-drain output, acknowledges that the chip has

entered Debug mode. As an input, DE causes the DSP56300 core to finish

executing the current instruction, save the instruction pipeline information,

enter Debug mode, and wait for commands to be entered from the debug

serial input line. This signal is asserted as an output for three clock cycles

when the chip enters Debug mode as a result of a debug request or as a result

of meeting a breakpoint condition. The DE has an internal pull-up resistor.

This signal is not a standard part of the JTAG TAP controller. The signal

connects directly to the OnCE module to initiate debug mode directly or to

provide a direct external indication that the chip has entered Debug mode. All

other interface with the OnCE module must occur through the JTAG port.

Note: All inputs are 5 V tolerant.

DSP56303 Technical Data, Rev. 11

1-16

Freescale Semiconductor

Specifications

2

The DSP56303 is fabricated in high-density CMOS with transistor-transistor logic (TTL) compatible inputs and outputs.

2.1 Maximum Ratings

CAUTION

This device contains circuitry protecting

against damage due to high static voltage or

electrical fields; however, normal precautions

should be taken to avoid exceeding maximum

voltage ratings. Reliability is enhanced if

unused inputs are tied to an appropriate logic

voltage level (for example, either GND or V ).

CC

In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of

another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case

variation of process parameter values in one direction. The minimum specification is calculated using the worst

case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never

occurs in the same device that has a “minimum” value for another specification; adding a maximum to a minimum

represents a condition that can never exist.

2.2 Absolute Maximum Ratings

1

Table 2-1. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Supply Voltage

V_CC

V_IN

V_IN5

I

−0.3 to +4.0

GND −0.3 to V_CC+ 0.3

GND −0.3 to 5.5

10

V

All input voltages excluding “5 V tolerant” inputs

All “5 V tolerant” input voltages²

V

Current drain per pin excluding V_CCand GND

Operating temperature range

mA

°C

T_J

−40 to +100

Storage temperature

T_STG

−55 to +150

Notes: 1. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the maximum rating may affect device reliability or cause permanent damage to the device.

2. At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V_CCnever exceeds 3.5 V.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-1

Specifications

2.3 Thermal Characteristics

Table 2-2. Thermal Characteristics

3

4

MAP-BGA

Value

Characteristic

Symbol

TQFP Value

Unit

Value

Junction-to-ambient thermal resistance¹

Junction-to-case thermal resistance²

Thermal characterization parameter

R_θJAor θ_JA

R_θJCor θ_JC

56

11

7

57

15

8

28

—

°C/W

Ψ

JT

Notes: 1. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per

JEDEC Specification JESD51-3.

2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that

the cold plate temperature is used for the case temperature.

3. These are simulated values. See note 1 for test board conditions.

4. These are simulated values. The test board has two 2-ounce signal layers and two 1-ounce solid ground planes internal to the

test board.

2.4 DC Electrical Characteristics

6

Table 2-3. DC Electrical Characteristics

Characteristics

Symbol

Min

Typ

Max

Unit

Supply voltage

V_CC

3.0

3.3

3.6

V

Input high voltage

•

D[0–23], BG, BB, TA

V_IH

V_IHP

2.0

—

V_CC

5.25

V

MOD¹/IRQ¹, RESET, PINIT/NMI and all

JTAG/ESSI/SCI/Timer/HI08 pins

EXTAL⁸

•

V_IHX

0.8 × V_CC

—

V_CC

V

Input low voltage

•

D[0–23], BG, BB, TA, MOD¹/IRQ¹, RESET, PINIT

All JTAG/ESSI/SCI/Timer/HI08 pins

EXTAL⁸

V_IL

V_ILP

V_ILX

–0.3

—

0.8

0.2 × V_CC

V

Input leakage current

I_IN

–10

—

10

µA

High impedance (off-state) input current (@ 2.4 V / 0.4 V)

Output high voltage

I_TSI

V_OH

•

TTL (I_OH= –0.4 mA)^5,7

2.4

_CC– 0.01

—

V

CMOS (I_OH= –10 µA)⁵

V

Output low voltage

V_OL

•

TTL (I_OL= 1.6 mA, open-drain pins I_OL= 6.7 mA)^5,7

—

0.4

0.01

V

CMOS (I_OL= 10 µA)⁵

Internal supply current²:

•

In Normal mode

In Wait mode³

In Stop mode⁴

I_CCI

I_CCW

I_CCS

—

127

7.5

100

—

mA

µA

PLL supply current

Input capacitance⁵

—

1

2.5

10

mA

pF

C_IN

—

DSP56303 Technical Data, Rev. 11

2-2

Freescale Semiconductor

AC Electrical Characteristics

6

Table 2-3. DC Electrical Characteristics (Continued)

Characteristics Symbol Min Typ

Notes: 1. Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins.

Max

Unit

2. Section 4.3 provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these

results, all inputs must be terminated (that is, not allowed to float). Measurements are based on synthetic intensive DSP

benchmarks (see Appendix A). The power consumption numbers in this specification are 90 percent of the measured results

of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with V_CC= 3.3 V at T_J=

100°C.

3. In order to obtain these results, all inputs must be terminated (that is, not allowed to float).

4. In order to obtain these results, all inputs that are not disconnected at Stop mode must be terminated (that is, not allowed to

float). PLL and XTAL signals are disabled during Stop state.

5. Periodically sampled and not 100 percent tested.

6.

V_CC= 3.3 V ± 0.3 V; T_J= –40°C to +100 °C, C_L= 50 pF

7. This characteristic does not apply to XTAL and PCAP.

8. Driving EXTAL to the low V_IHXor the high V_ILXvalue may cause additional power consumption (DC current). To minimize

power consumption, the minimum V_IHXshould be no lower than

0.9 × V_CCand the maximum V_ILXshould be no higher than 0.1 × V_CC

.

2.5 AC Electrical Characteristics

The timing waveforms shown in the AC electrical characteristics section are tested with a V maximum of 0.3 V

IL

and a V minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of

IH

the previous table. AC timing specifications, which are referenced to a device input signal, are measured in

production with respect to the 50 percent point of the respective input signal transition. DSP56303 output levels are

measured with the production test machine V and V reference levels set at 0.4 V and 2.4 V, respectively.

OL

OH

Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15

MHz and rated speed.

2.5.1 Internal Clocks

Table 2-4. Internal Clocks, CLKOUT

1, 2

Expression

Characteristics

Symbol

Min

Typ

Max

Internal operation frequency and CLKOUT

with PLL enabled

f

—

(Ef × MF)/

(PDF × DF)

—

Internal operation frequency and CLKOUT

with PLL disabled

—

Ef/2

—

Internal clock and CLKOUT high period

•

With PLL disabled

With PLL enabled and MF ≤4

T_H

—

ET_C

—

0.49 × ET_C

×

0.51 × ET_C×

PDF × DF/MF

0.47 × ET_C

PDF × DF/MF

0.53 × ET_C

PDF × DF/MF

•

With PLL enabled and MF > 4

×

—

×

Internal clock and CLKOUT low period

•

With PLL disabled

With PLL enabled and MF ≤4

T_L

—

ET_C

—

0.49 × ET_C

PDF × DF/MF

0.47 × ET_C

×

0.51 × ET_C

PDF × DF/MF

0.53 × ET_C

×

•

With PLL enabled and MF > 4

×

—

×

PDF × DF/MF

Internal clock and CLKOUT cycle time with

PLL enabled

T_C

—

ET_C× PDF ×

—

DF/MF

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-3

Specifications

Table 2-4. Internal Clocks, CLKOUT (Continued)

Expression

1, 2

Characteristics

Symbol

Min

Typ

Max

Internal clock and CLKOUT cycle time with

PLL disabled

T_C

—

2 × ET_C

—

Instruction cycle time

I_CYC

—

T_C

—

Notes: 1. DF = Division Factor; Ef = External frequency; ET_C= External clock cycle; MF = Multiplication Factor;

PDF = Predivision Factor; T_C= internal clock cycle

2. See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL.

2.5.2 External Clock Operation

The DSP56303 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip

oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; examples are

shown in Figure 2-1.

EXTAL

XTAL

Suggested Component Values:

R

f_OSC= 4 MHz

R = 680 kΩ± 10%

C = 56 pF ± 20%

f_OSC= 20 MHz

R = 680 kΩ ± 10%

C = 22 pF ± 20%

Note: Make sure that in

the PCTL Register:

•

XTLD (bit 16) = 0

If f_OSC> 200 kHz,

XTLR (bit 15) = 0

Calculations were done for a 4/20 MHz crystal

with the following parameters:

C

XTAL1

C

•

C_Lof 30/20 pF,

C₀of 7/6 pF,

series resistance of 100/20 Ω, and

drive level of 2 mW.

Fundamental Frequency

Crystal Oscillator

Figure 2-1. Crystal Oscillator Circuits

If an externally-supplied square wave voltage source is used, disable the internal oscillator circuit during bootup by

setting XTLD (PCTL Register bit 16 = 1—see the DSP56303 User’s Manual). The external square wave source

connects to EXTAL; XTAL is not physically connected to the board or socket. Figure 2-2 shows the relationship

between the EXTAL input and the internal clock and CLKOUT.

V_IHX

Midpoint

EXTAL

ET_H

ET_L

V_ILX

Note:

The midpoint is

0.5 (V_IHX+ V_ILX).

2

3

4

ET_C

5

CLKOUT with

PLL disabled

7

CLKOUT with

PLL enabled

7

6a

6b

Figure 2-2. External Clock Timing

DSP56303 Technical Data, Rev. 11

2-4

Freescale Semiconductor

AC Electrical Characteristics

100 MHz

Table 2-5. Clock Operation

Characteristics

Frequency of EXTAL (EXTAL Pin Frequency)

No.

Symbol

Min

Max

1

2

Ef

0

100.0

The rise and fall time of this external clock should be 3 ns maximum.

EXTAL input high^{1, 2}

•

With PLL disabled (46.7%–53.3% duty cycle⁶)

With PLL enabled (42.5%–57.5% duty cycle⁶)

ET_H

ET_L

ET_C

4.67 ns

4.25 ns

∞

157.0 µs

3

4

EXTAL input low^{1, 2}

•

With PLL disabled (46.7%–53.3% duty cycle⁶)

With PLL enabled (42.5%–57.5% duty cycle⁶)

4.67 ns

4.25 ns

∞

157.0 µs

EXTAL cycle time²

•

With PLL disabled

With PLL enabled

10.00 ns

∞

273.1 µs

5

6

Internal clock change from EXTAL fall with PLL disabled

4.3 ns

0.0 ns

11.0 ns

1.8 ns

a.Internal clock rising edge from EXTAL rising edge with PLL enabled (MF = 1 or 2 or

4, PDF = 1, Ef > 15 MHz)^3,5

b. Internal clock falling edge from EXTAL falling edge with PLL enabled (MF ≤4, PDF ≠

0.0 ns

1.8 ns

1, Ef / PDF > 15 MHz)^3,5

4

7

Instruction cycle time = I_CYC= T_C

I_CYC

(see Table 2-4) (46.7%–53.3% duty cycle)

•

With PLL disabled

With PLL enabled

20.0 ns

10.00 ns

∞

8.53 µs

Notes: 1. Measured at 50 percent of the input transition.

2. The maximum value for PLL enabled is given for minimum VCO frequency (see Table 2-4) and maximum MF.

3. Periodically sampled and not 100 percent tested.

4. The maximum value for PLL enabled is given for minimum VCO frequency and maximum DF.

5. The skew is not guaranteed for any other MF value.

6. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time

required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock

frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time

requirements are met.

2.5.3 Phase Lock Loop (PLL) Characteristics

Table 2-6. PLL Characteristics

100 MHz

Characteristics

Unit

Min

Max

Voltage Controlled Oscillator (VCO) frequency when PLL enabled

30

200

MHz

(MF × E_f× 2/PDF)

1

PLL external capacitor (PCAP pin to V_CCP) (C_PCAP

)

•

@ MF ≤4

@ MF > 4

(580 × MF) −100

830 × MF

(780 × MF) −140

1470 × MF

pF

Note:

C

_PCAPis the value of the PLL capacitor (connected between the PCAP pin and V_CCP) computed using the appropriate expression

listed above.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-5

Specifications

2.5.4 Reset, Stop, Mode Select, and Interrupt Timing

6

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

8

9

Delay from RESET assertion to all pins at reset value³

Required RESET duration⁴

—

26.0

ns

•

Power on, external clock generator, PLL disabled

Power on, external clock generator, PLL enabled

Power on, internal oscillator

During STOP, XTAL disabled (PCTL Bit 16 = 0)

During STOP, XTAL enabled (PCTL Bit 16 = 1)

During normal operation

50 × ET_C

1000 × ET_C

75000 × ET_C

2.5 × T_C

500.0

10.0

0.75

25.0

—

ns

µs

ms

ns

2.5 × T_C

ns

10 Delay from asynchronous RESET deassertion to first external address

output (internal reset deassertion)⁵

•

Minimum

Maximum

3.25 × T_C+ 2.0

20.25 × T_C+ 10

34.5

—

212.5

ns

11 Synchronous reset set-up time from RESET deassertion to CLKOUT

Transition 1

•

Minimum

Maximum

T_C

5.9

—

10.0

ns

12 Synchronous reset deasserted, delay time from the CLKOUT Transition

1 to the first external address output

•

Minimum

Maximum

3.25 × T_C+ 1.0

20.25 × T_C+ 1.0

33.5

—

203.5

ns

13 Mode select setup time

30.0

0.0

—

ns

14 Mode select hold time

15 Minimum edge-triggered interrupt request assertion width

16 Minimum edge-triggered interrupt request deassertion width

6.6

17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external

memory access address out valid

•

Caused by first interrupt instruction fetch

Caused by first interrupt instruction execution

4.25 × T_C+ 2.0

7.25 × T_C+ 2.0

44.5

74.5

—

ns

18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-

purpose transfer output valid caused by first interrupt instruction

execution

10 × T_C+ 5.0

105.0

—

ns

19 Delay from address output valid caused by first interrupt instruction

execute to interrupt request deassertion for level sensitive fast

interrupts^{1, 7, 8}

(WS + 3.75) × T_C– 10.94

(WS + 3.25) × T_C– 10.94

—

Note 8

20 Delay from RD assertion to interrupt request deassertion for level

sensitive fast interrupts^{1, 7, 8}

—

21 Delay from WR assertion to interrupt request deassertion for level

sensitive fast interrupts^{1, 7, 8}

•

DRAM for all WS

SRAM WS = 1

SRAM WS = 2, 3

SRAM WS ≥ 4

(WS + 3.5) × T_C– 10.94

(WS + 3) × T_C– 10.94

(WS + 2.5) × T_C– 10.94

—

Note 8

ns

22 Synchronous interrupt set-up time from IRQA, IRQB, IRQC, IRQD, NMI

assertion to the CLKOUT Transition 2

5.9

T_C

ns

23 Synchronous interrupt delay time from the CLKOUT Transition 2 to the

first external address output valid caused by the first instruction fetch

after coming out of Wait Processing state

•

Minimum

Maximum

8.25 × T_C+ 1.0

24.75 × T_C+ 5.0

83.5

—

252.5

ns

DSP56303 Technical Data, Rev. 11

2-6

Freescale Semiconductor

AC Electrical Characteristics

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing (Continued)

6

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

24 Duration for IRQA assertion to recover from Stop state

5.9

—

ns

25 Delay from IRQA assertion to fetch of first instruction (when exiting

Stop)^{2, 3}

•

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is

enabled (Operating Mode Register Bit 6 = 0)

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not PLC × ET_C× PDF + (23.75 ± 232.5 ns 12.3 ms

enabled (Operating Mode Register Bit 6 = 1)

PLC × ET_C× PDF + (128 K −

PLC/2) × T_C

1.3

9.1

ms

ns

0.5) × T_C

(8.25 ± 0.5) × T_C

PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay)

87.5

97.5

26 Duration of level sensitive IRQA assertion to ensure interrupt service

(when exiting Stop)^{2, 3}

•

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is

enabled (Operating Mode Register Bit 6 = 0)

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not

enabled (Operating Mode Register Bit 6 = 1)

PLC × ET_C× PDF + (128K −

PLC/2) × T_C

13.6

12.3

55.0

—

ms

ns

PLC × ET_C× PDF +

(20.5 ± 0.5) × T_C

5.5 × T_C

PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay)

27 Interrupt Requests Rate

Maximum:

12 × T_C

8 × T_C

12 × T_C

•

HI08, ESSI, SCI, Timer

DMA

IRQ, NMI (edge trigger)

IRQ, NMI (level trigger)

—

120.0

80.0

ns

120.0

28 DMA Requests Rate

Maximum:

6 × T_C

7 × T_C

2 × T_C

3 × T_C

•

Data read from HI08, ESSI, SCI

Data write to HI08, ESSI, SCI

Timer

—

60.0

70.0

20.0

30.0

ns

IRQ, NMI (edge trigger)

29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external

memory (DMA source) access address out valid

Minimum:

4.25 × T_C+ 2.0

30.3

—

ns

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-7

Specifications

6

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing (Continued)

100 MHz

Min Max

No.

Characteristics

Expression

Unit

Notes: 1. When fast interrupts are used and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to

prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended

when fast interrupts are used. Long interrupts are recommended for Level-sensitive mode.

2. This timing depends on several settings:

• For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL

Bit 17 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the

Stop delay (Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set,

it is not recommended, and these specifications do not guarantee timings for that case.

• For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no

stabilization delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored).

• For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time is defined by the

PCTL Bit 17 and Operating Mode Register Bit 6 settings.

• For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked.

The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in

parallel with the stop delay counter, and stop recovery ends when the last of these two events occurs. The stop delay counter

completes count or PLL lock procedure completion.

• PLC value for PLL disable is 0.

• The maximum value for ET_Cis 4096 (maximum MF) divided by the desired internal frequency (that is, for 66 MHz it is 4096/66

MHz = 62 µs). During the stabilization period, T_C, T_H,and T_Lis not constant, and their width may vary, so timing may vary as

well.

3. Periodically sampled and not 100 percent tested.

4. Value depends on clock source:

• For an external clock generator, RESET duration is measured while RESET is asserted, V_CCis valid, and the EXTAL input is

active and valid.

• For an internal oscillator, RESET duration is measured while RESET is asserted and V_CCis valid. The specified timing

reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal

and other components connected to the oscillator and reflects worst case conditions.

• When the V_CCis valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the

device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should

minimize this state to the shortest possible duration.

5. If PLL does not lose lock.

6.

V_CC= 3.3 V ± 0.3 V; T_J= –40°C to +100°C, C_L= 50 pF.

7. WS = number of wait states (measured in clock cycles, number of T_C).

8. Use the expression to compute a maximum value.

V_IH

RESET

9

10

8

All Pins

Reset Value

First Fetch

A[0–17]

Figure 2-3. Reset Timing

DSP56303 Technical Data, Rev. 11

2-8

Freescale Semiconductor

AC Electrical Characteristics

CLKOUT

RESET

11

12

A[0–17]

Figure 2-4. Synchronous Reset Timing

First Interrupt Instruction

Execution/Fetch

A[0–17]

RD

20

21

WR

17

19

IRQA, IRQB,

IRQC, IRQD,

NMI

a) First Interrupt Instruction Execution

General

Purpose

I/O

18

IRQA, IRQB,

IRQC, IRQD,

NMI

b) General-Purpose I/O

Figure 2-5. External Fast Interrupt Timing

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-9

Specifications

IRQA, IRQB,

IRQC, IRQD, NMI

15

16

IRQA, IRQB,

IRQC, IRQD, NMI

Figure 2-6. External Interrupt Timing (Negative Edge-Triggered)

CLKOUT

IRQA, IRQB,

IRQC, IRQD,

NMI

22

23

A[0–17]

Figure 2-7. Synchronous Interrupt from Wait State Timing

V_IH

RESET

13

14

V_IH

MODA, MODB,

MODC, MODD,

PINIT

IRQA, IRQB,

IRQC, IRQD, NMI

V_IL

Figure 2-8. Operating Mode Select Timing

DSP56303 Technical Data, Rev. 11

2-10

Freescale Semiconductor

AC Electrical Characteristics

24

IRQA

25

First Instruction Fetch

A[0–17]

Figure 2-9. Recovery from Stop State Using IRQA

26

IRQA

25

First IRQA Interrupt

Instruction Fetch

A[0–17]

Figure 2-10. Recovery from Stop State Using IRQA Interrupt Service

DMA Source Address

A[0–17]

RD

WR

29

IRQA, IRQB,

IRQC, IRQD,

NMI

First Interrupt Instruction Execution

Figure 2-11. External Memory Access (DMA Source) Timing

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-11

Specifications

2.5.5 External Memory Expansion Port (Port A)

2.5.5.1 SRAM Timing

Table 2-8. SRAM Read and Write Accesses

100 MHz

1

No.

Characteristics

Symbol

Expression

Unit

Min

Max

100 Address valid and AA assertion pulse width²

101 Address and AA valid to WR assertion

102 WR assertion pulse width

t_RC, t_WC

(WS + 1) × T_C−4.0

[1 ≤WS ≤3]

(WS + 2) × T_C−4.0

[4 ≤WS ≤7]

(WS + 3) × T_C−4.0

[WS ≥ 8]

16.0

—

ns

56.0

—

106.0

t_AS

t_WP

t_WR

0.25 × T_C−2.0

[WS = 1]

0.75 × T_C−2.0

[2 ≤WS ≤3]

1.25 × T_C−2.0

[WS ≥ 4]

0.5

5.5

—

ns

10.5

1.5 × T_C−4.0

[WS = 1]

WS × T_C−4.0

[2 ≤WS ≤3]

11.0

16.0

31.0

—

ns

(WS −0.5) × T_C−4.0

[WS ≥ 4]

103 WR deassertion to address not valid

0.25 × T_C−2.0

[1 ≤WS ≤3]

1.25 × T_C−4.0

[4 ≤WS ≤7]

2.25 × T_C−4.0

[WS ≥ 8]

0.5

8.5

—

ns

18.5

104 Address and AA valid to input data valid

105 RD assertion to input data valid

t_AA, t_AC

t_OE

(WS + 0.75) × T_C−5.0

[WS ≥ 1]

—

12.5

7.5

ns

(WS + 0.25) × T_C– 5.0

[WS ≥ 1]

106 RD deassertion to data not valid (data hold time)

107 Address valid to WR deassertion²

t_OHZ

t_AW

0.0

—

ns

(WS + 0.75) × T_C−4.0

[WS ≥ 1]

13.5

108 Data valid to WR deassertion (data setup time)

109 Data hold time from WR deassertion

t_DS(t_DW

t_DH

)

(WS −0.25) × T_C−3.0

[WS ≥ 1]

4.5

—

ns

0.25 × T_C−2.0

[1 ≤WS ≤3]

1.25 × T_C−2.0

[4 ≤WS ≤7]

2.25 × T_C−2.0

[WS ≥ 8]

0.5

—

ns

10.5

20.5

110 WR assertion to data active

—

0.75 × T_C−3.7

[WS = 1]

0.25 × T_C– 3.7

[2 ≤WS ≤3]

–0.25 × T_C−3.7

[WS ≥ 4]

3.8

—

ns

–1.2

–6.2

DSP56303 Technical Data, Rev. 11

2-12

Freescale Semiconductor

AC Electrical Characteristics

Table 2-8. SRAM Read and Write Accesses (Continued)

100 MHz

Unit

1

No.

Characteristics

Symbol

Expression

Min

Max

111 WR deassertion to data high impedance

112 Previous RD deassertion to data active (write)

113 RD deassertion time

—

0.25 × T_C+ 0.2

[1 ≤WS ≤3]

1.25 × TC + 0.2

[4 ≤WS ≤7]

2.25 × T_C+ 0.2

[WS > 8]

—

2.7

ns

—

12.7

22.7

—

1.25 × T_C– 4.0

[1 ≤WS ≤3]

2.25 × T_C– 4.0

[4 ≤WS ≤7]

3.25 × T_C– 4.0

[WS > 8]

8.5

—

ns

18.5

28.5

0.75 × T_C−4.0

[1 ≤WS ≤3]

1.75 × T_C−4.0

[4 ≤WS ≤7]

2.75 × T_C−4.0

[WS ≥ 8]

3.5

—

ns

13.5

23.5

114 WR deassertion time

0.5 × T_C−4.0

[WS = 1]

1.0

6.0

—

ns

T_C−4.0

[2 ≤WS ≤3]

2.5 × T_C−4.0

[4 ≤WS ≤7]

3.5 × T_C−4.0

[WS ≥ 8]

21.0

31.0

115 Address valid to RD assertion

116 RD assertion pulse width

—

0.5 × T_C−4.0

1.0

8.5

0.5

—

ns

(WS + 0.25) × T_C−4.0

117 RD deassertion to address not valid

0.25 × T_C−2.0

[1 ≤WS ≤3]

1.25 × T_C−2.0

[4 ≤WS ≤7]

2.25 × T_C−2.0

[WS ≥ 8]

10.5

20.5

—

ns

118 TA setup before RD or WR deassertion⁴

119 TA hold after RD or WR deassertion

—

0.25 × T_C+ 2.0

4.5

0

—

ns

—

Notes: 1. WS is the number of wait states specified in the BCR. An expression is used to compute the number listed as the minimum or

maximum value, as appropriate.

2. Timings 100, 107 are guaranteed by design, not tested.

3. All timings for 100 MHz are measured from 0.5 × Vcc to 0.5 × Vcc.

4. Timing 118 is relative to the deassertion edge of RD or WR even if TA remains asserted.

5.

V_CC= 3.3 V ± 0.3 V; T_J= –40°C to +100°C, C_L= 50 pF

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-13

Specifications

100

A[0–17]

AA[0–3]

117

106

113

116

RD

105

WR

104

118

119

TA

Data

In

D[0–23]

Note: Address lines A[0–17] hold their state after a

read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-12. SRAM Read Access

100

A[0–17]

AA[0–3]

107

101

102

103

WR

RD

114

119

109

118

TA

108

Data

Out

D[0–23]

Note: Address lines A[0–17] hold their state after a

read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-13. SRAM Write Access

DSP56303 Technical Data, Rev. 11

2-14

Freescale Semiconductor

AC Electrical Characteristics

2.5.5.2 DRAM Timing

The selection guides in Figure 2-14 and Figure 2-17 are for primary selection only. Final selection should be based

on the timing in the following tables. For example, the selection guide suggests that four wait states must be used

for 100 MHz operation with Page Mode DRAM. However, consulting the appropriate table, a designer can evaluate

whether fewer wait states might suffice by determining which timing prevents operation at 100 MHz, running the

chip at a slightly lower frequency (for example, 95 MHz), using faster DRAM (if it becomes available), and

manipulating control factors such as capacitive and resistive load to improve overall system performance.

Note:

This figure should be used for primary selection. For exact

and detailed timings, see the following tables.

DRAM type

(tRAC ns)

100

80

70

60

Chip frequency

(MHz)

50

120

40

66

80

100

1 Wait states

2 Wait states

3 Wait states

4 Wait states

Figure 2-14. DRAM Page Mode Wait State Selection Guide

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-15

Specifications

1,2,3

Table 2-9. DRAM Page Mode Timings, Three Wait States

100 MHz

4

No.

Characteristics

Symbol

Expression

Unit

Min

Max

131 Page mode cycle time for two consecutive accesses of the same

direction

4 × T_C

40.0

—

ns

Page mode cycle time for mixed (read and write) accesses

132 CAS assertion to data valid (read)

t_PC

t_CAC

t_AA

3.5 × T_C

2 × T_C−5.7

3 × T_C−5.7

35.0

—

14.3

24.3

—

ns

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

—

t_OFF

t_RSH

t_RHCP

t_CAS

t_CRP

0.0

2.5 × T_C−4.0

4.5 × T_C−4.0

2 × T_C−4.0

21.0

41.0

16.0

—

138 Last CAS deassertion to RAS assertion⁵

•

BRW[1–0] = 00, 01—not applicable

BRW[1–0] = 10

BRW[1–0] = 11

—

41.5

61.5

—

ns

4.75 × T_C−6.0

6.75 × T_C−6.0

139 CAS deassertion pulse width

t_CP

t_ASC

t_CAH

t_RAL

t_RCS

t_RCH

t_WCH

t_WP

1.5 × T_C−4.0

T_C−4.0

11.0

6.0

—

ns

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

2.5 × T_C−4.0

4 × T_C−4.0

21.0

36.0

8.5

—

1.25 × T_C−4.0

0.75 × T_C−4.0

2.25 × T_C−4.2

3.5 × T_C−4.5

3.75 × T_C−4.3

3.25 × T_C−4.3

0.5 × T_C– 4.5

2.5 × T_C−4.0

1.25 × T_C−4.3

3.5 × T_C−4.0

2.5 × T_C−5.7

—

3.5

—

18.3

30.5

33.2

28.2

0.5

—

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t_RWL

t_CWL

t_DS

—

t_DH

21.0

8.2

—

t_WCS

t_ROH

t_GA

—

31.0

—

19.3

—

154 RD deassertion to data not valid⁶

155 WR assertion to data active

t_GZ

0.0

0.75 × T_C– 1.5

0.25 × T_C

6.0

—

156 WR deassertion to data high impedance

—

2.5

Notes: 1. The number of wait states for Page mode access is specified in the DRAM Control Register.

2. The refresh period is specified in the DRAM Control Register.

3. The asynchronous delays specified in the expressions are valid for the DSP56303.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, t_PCequals 4 ×

_Cfor read-after-read or write-after-write sequences). An expression is used to compute the number listed as the minimum or

T

maximum value listed, as appropriate.

5. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-

access.

6. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

DSP56303 Technical Data, Rev. 11

2-16

Freescale Semiconductor

AC Electrical Characteristics

1,2,3

Table 2-10. DRAM Page Mode Timings, Four Wait States

100 MHz

4

No.

Characteristics

Symbol

Expression

5 × T_C

Unit

Min

Max

131 Page mode cycle time for two consecutive accesses of the same

direction

50.0

—

ns

Page mode cycle time for mixed (read and write) accesses

132 CAS assertion to data valid (read)

t_PC

t_CAC

t_AA

4.5 × T_C

45.0

—

21.8

31.8

—

ns

2.75 × T_C−5.7

3.75 × T_C−5.7

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

—

t_OFF

t_RSH

t_RHCP

t_CAS

t_CRP

0.0

3.5 × T_C−4.0

6 × T_C−4.0

31.0

56.0

21.0

—

2.5 × T_C−4.0

—

138 Last CAS deassertion to RAS assertion⁵

•

BRW[1–0] = 00, 01—Not applicable

BRW[1–0] = 10

BRW[1–0] = 11

—

46.5

66.5

—

ns

5.25 × T_C−6.0

7.25 × T_C−6.0

139 CAS deassertion pulse width

t_CP

t_ASC

t_CAH

t_RAL

t_RCS

t_RCH

t_WCH

t_WP

2 × T_C−4.0

T_C−4.0

16.0

6.0

—

ns

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

3.5 × T_C−4.0

5 × T_C−4.0

31.0

46.0

8.5

—

1.25 × T_C−4.0

1.25 × T_C– 3.7

3.25 × T_C−4.2

4.5 × T_C−4.5

4.75 × T_C−4.3

3.75 × T_C−4.3

0.5 × T_C– 4.5

3.5 × T_C−4.0

1.25 × T_C−4.3

4.5 × T_C−4.0

3.25 × T_C−5.7

—

8.8

—

28.3

40.5

43.2

33.2

0.5

—

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t_RWL

t_CWL

t_DS

—

t_DH

31.0

8.2

—

t_WCS

t_ROH

t_GA

—

41.0

—

26.8

—

154 RD deassertion to data not valid⁶

155 WR assertion to data active

t_GZ

0.0

0.75 × T_C– 1.5

0.25 × T_C

6.0

—

156 WR deassertion to data high impedance

—

2.5

Notes: 1. The number of wait states for Page mode access is specified in the DRAM Control Register.

2. The refresh period is specified in the DRAM Control Register.

3. The asynchronous delays specified in the expressions are valid for the DSP56303.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, t_PCequals 3 ×

_Cfor read-after-read or write-after-write sequences). An expressions is used to calculate the maximum or minimum value

T

listed, as appropriate.

5. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page

access.

6. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-17

Specifications

RAS

CAS

136

131

135

137

139

138

142

140

151

141

Column

Address

Last Column

Address

Column

Address

Row

Add

A[0–17]

144

145

147

148

WR

RD

146

155

156

150

149

D[0–23]

Data Out

Figure 2-15. DRAM Page Mode Write Accesses

RAS

CAS

136

131

135

137

140

139

138

142

141

Last Column

Address

Row

Add

Column

Address

Column

Address

A[0–17]

WR

143

132

133

153

152

RD

134

154

D[0–23]

Data In

Figure 2-16. DRAM Page Mode Read Accesses

DSP56303 Technical Data, Rev. 11

2-18

Freescale Semiconductor

AC Electrical Characteristics

DRAM Type

(tRAC ns)

Note:

This figure should be used for primary selection. For exact and

detailed timings, see the following tables.

100

80

70

60

Chip Frequency

(MHz)

50

120

40

66

80

100

4 Wait States

8 Wait States

11 Wait States

15 Wait States

Figure 2-17. DRAM Out-of-Page Wait State Selection Guide

1,2

Table 2-11. DRAM Out-of-Page and Refresh Timings, Eleven Wait States

100 MHz

3

No.

Characteristics

Symbol

Expression

Unit

Min

Max

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

161 CAS deassertion to data not valid (read hold time)

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t_RC

t_RAC

t_CAC

t_AA

12 × T_C

120.0

—

55.5

30.5

38.0

—

ns

6.25 × T_C−7.0

3.75 × T_C−7.0

4.5 × T_C−7.0

—

t_OFF

t_RP

0.0

4.25 × T_C−4.0

7.75 × T_C−4.0

5.25 × T_C−4.0

6.25 × T_C−4.0

3.75 × T_C−4.0

2.5 × T_C± 4.0

1.75 × T_C± 4.0

5.75 × T_C−4.0

4.25 × T_C– 6.0

4.25 × T_C−4.0

38.5

73.5

48.5

58.5

33.5

21.0

13.5

53.5

36.5

38.5

—

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

—

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

—

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

29.0

21.5

—

171 Row address valid to RAS assertion

t_ASR

—

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-19

Specifications

Table 2-11. DRAM Out-of-Page and Refresh Timings, Eleven Wait States

1,2

(Continued)

100 MHz

3

No.

Characteristics

Symbol

Expression

Unit

Min

Max

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

178 CAS deassertion to WR⁴assertion

179 RAS deassertion to WR⁴assertion

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t_RAH

t_ASC

t_CAH

t_AR

1.75 × T_C−4.0

0.75 × T_C−4.0

5.25 × T_C−4.0

7.75 × T_C−4.0

6 × T_C−4.0

13.5

3.5

—

93.0

—

2.5

ns

48.5

73.5

56.0

26.0

13.8

0.5

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

3.0 × T_C−4.0

1.75 × T_C– 3.7

0.25 × T_C−2.0

5 × T_C−4.2

45.8

70.8

110.5

113.2

98.2

53.5

48.5

73.5

60.7

11.0

23.5

111.0

—

7.5 × T_C−4.2

11.5 × T_C−4.5

11.75 × T_C−4.3

10.25 × T_C−4.3

5.75 × T_C−4.0

5.25 × T_C−4.0

7.75 × T_C−4.0

6.5 × T_C−4.3

1.5 × T_C−4.0

2.75 × T_C−4.0

11.5 × T_C−4.0

10 × T_C−7.0

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

t_DH

t_DHR

t_WCS

t_CSR

t_RPC

t_ROH

t_GA

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

192 RD assertion to data valid

193 RD deassertion to data not valid⁵

194 WR assertion to data active

t_GZ

0.0

0.75 × T_C– 1.5

0.25 × T_C

6.0

195 WR deassertion to data high impedance

—

Notes: 1. The number of wait states for an out-of-page access is specified in the DRAM Control Register.

2. The refresh period is specified in the DRAM Control Register.

3. Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±± .

4. Either t_RCHor t_RRHmust be satisfied for read cycles.

5. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

DSP56303 Technical Data, Rev. 11

2-20

Freescale Semiconductor

AC Electrical Characteristics

1,2

Table 2-12. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States

100 MHz

3

No.

Characteristics

Symbol

Expression

Unit

Min

Max

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

161 CAS deassertion to data not valid (read hold time)

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t_RC

t_RAC

t_CAC

t_AA

16 × T_C

160.0

—

76.8

41.8

49.3

—

ns

8.25 × T_C−5.7

4.75 × T_C−5.7

5.5 × T_C−5.7

0.0

—

t_OFF

t_RP

0.0

6.25 × T_C−4.0

9.75 × T_C−4.0

6.25 × T_C−4.0

8.25 × T_C−4.0

4.75 × T_C−4.0

3.5 × T_C± 2

58.5

93.5

58.5

78.5

43.5

33.0

25.5

73.5

56.5

58.5

23.5

3.5

—

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

—

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

—

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

37.0

29.5

—

2.75 × T_C± 2

7.75 × T_C−4.0

6.25 × T_C– 6.0

6.25 × T_C−4.0

2.75 × T_C−4.0

0.75 × T_C−4.0

6.25 × T_C−4.0

9.75 × T_C−4.0

7 × T_C−4.0

—

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

178 CAS deassertion to WR⁴assertion

179 RAS deassertion to WR⁴assertion

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t_ASR

t_RAH

t_ASC

t_CAH

t_AR

—

58.5

93.5

66.0

46.2

13.8

0.5

—

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

—

5 × T_C−3.8

—

1.75 × T_C– 3.7

0.25 × T_C−2.0

6 × T_C−4.2

—

55.8

90.8

150.5

153.2

138.2

83.5

58.5

93.5

90.7

11.0

43.5

151.0

—

9.5 × T_C−4.2

15.5 × T_C−4.5

15.75 × T_C−4.3

14.25 × T_C−4.3

8.75 × T_C−4.0

6.25 × T_C−4.0

9.75 × T_C−4.0

9.5 × T_C−4.3

1.5 × T_C−4.0

4.75 × T_C−4.0

15.5 × T_C−4.0

14 × T_C−5.7

—

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

—

t_DH

—

t_DHR

t_WCS

t_CSR

t_RPC

t_ROH

t_GA

—

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

192 RD assertion to data valid

—

134.3

—

193 RD deassertion to data not valid⁵

t_GZ

0.0

194 WR assertion to data active

0.75 × T_C– 1.5

0.25 × T_C

6.0

—

195 WR deassertion to data high impedance

—

2.5

Notes: 1. The number of wait states for an out-of-page access is specified in the DRAM Control Register.

2. The refresh period is specified in the DRAM Control Register.

3. Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±± .

4. Either t_RCHor t_RRHmust be satisfied for read cycles.

5. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-21

Specifications

157

163

162

165

RAS

167

168

164

169

170

166

CAS

171

173

174

175

Row Address

172

Column Address

176

A[0–17]

177

179

191

WR

RD

178

160

159

193

158

192

161

Data

In

D[0–23]

Figure 2-18. DRAM Out-of-Page Read Access

DSP56303 Technical Data, Rev. 11

2-22

Freescale Semiconductor

AC Electrical Characteristics

157

162

163

162

165

RAS

167

164

169

168

170

166

CAS

173

172

171

174

176

Row Address

Column Address

A[0–17]

181

175

188

180

182

WR

184

183

187

RD

186

195

185

194

D[0–23]

Data Out

Figure 2-19. DRAM Out-of-Page Write Access

157

162

163

RAS

190

170

177

165

189

CAS

WR

Figure 2-20. DRAM Refresh Access

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-23

Specifications

2.5.5.3 Synchronous Timings

1,2

Table 2-13. External Bus Synchronous Timings

100 MHz

3,4,5

No.

Characteristics

Expression

Unit

Min

Max

198

199

200

201

202

203

204

205

206

207

208

209

210

CLKOUT high to address, and AA valid⁶

CLKOUT high to address, and AA invalid⁶

TA valid to CLKOUT high (set-up time)

CLKOUT high to TA invalid (hold time)

CLKOUT high to data out active

0.25 × T_C+ 4.0

0.25 × T_C

—

2.5

4.0

0.0

2.5

—

6.5

—

ns

—

0.25 × T_C

0.25 × T_C+ 4.0

0.25 × T_C

—

CLKOUT high to data out valid

6.5

—

CLKOUT high to data out invalid

2.5

—

CLKOUT high to data out high impedance

Data in valid to CLKOUT high (set-up)

CLKOUT high to data in invalid (hold)

CLKOUT high to RD assertion

0.25 × T_C

2.5

—

4.0

0.0

6.7

0.0

5.0

—

maximum: 0.75 × T_C+ 2.5

10.0

4.0

9.3

CLKOUT high to RD deassertion

CLKOUT high to WR assertion²

maximum: 0.5 × T_C+ 4.3

for WS = 1 or WS ≥ 4

for 2 ≤WS ≤3

0.0

4.3

3.8

ns

211

CLKOUT high to WR deassertion

Notes: 1. Use external bus synchronous timings only for reference to the clock and not for relative timings.

2. Synchronous Bus Arbitration is not recommended. Use Asynchronous mode whenever possible.

3. WS is the number of wait states specified in the BCR.

4. If WS > 1, WR assertion refers to the next rising edge of CLKOUT.

5. Use the expression to compute the maximum or minimum value listed, as appropriate. For timing 210, the minimum is an

absolute value.

6. T198 and T199 are valid for Address Trace mode if the ATE bit in the Operating Mode Register is set. when this mode is

enabled, use the status of BR (See T212) to determine whether the access referenced by A[0–17] is internal or external.

DSP56303 Technical Data, Rev. 11

2-24

Freescale Semiconductor

AC Electrical Characteristics

198

CLKOUT

A[0–17]

AA[0–3]

199

201

200

TA

211

WR

205

210

203

204

D[0–23]

RD

Data Out

208

202

209

207

206

D[0–23]

Data In

Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state

after a read or write operation.

Figure 2-21. Synchronous Bus Timings 1 WS (BCR Controlled)

CLKOUT

A[0–17]

AA[0–3]

199

201

198

201

200

211

TA

200

WR

210

205

203

202

204

Data Out

D[0–23]

208

209

RD

207

206

Data In

D[0–23]

Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-22. Synchronous Bus Timings 2 WS (TA Controlled)

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-25

Specifications

2.5.5.4 Arbitration Timings

1

Table 2-14. Arbitration Bus Timings

100 MHz

2

No.

Characteristics

Expression

Unit

Min

Max

212

213

214

215

216

217

218

219

220

221

222

223

224

CLKOUT high to BR assertion/deassertion³

BG asserted/deasserted to CLKOUT high (setup)

CLKOUT high to BG deasserted/asserted (hold)

BB deassertion to CLKOUT high (input set-up)

CLKOUT high to BB assertion (input hold)

CLKOUT high to BB assertion (output)

CLKOUT high to BB deassertion (output)

BB high to BB high impedance (output)

CLKOUT high to address and controls active

CLKOUT high to address and controls high impedance

CLKOUT high to AA active

0.0

4.0

0.0

4.0

0.0

—

4.0

—

ns

—

4.0

4.5

—

0.25 × T_C

0.75 × T_C

0.25 × T_C

2.5

—

7.5

—

2.5

2.0

—

CLKOUT high to AA deassertion

maximum: 0.25 × T_C+ 4.0

0.75 × T_C

6.5

7.5

CLKOUT high to AA high impedance

Notes: 1. Synchronous bus arbitration is not recommended. Use Asynchronous mode whenever possible.

2. An expression is used to compute the maximum or minimum value listed, as appropriate. For timing 223, the minimum is an

absolute value.

3. T212 is valid for Address Trace mode when the ATE bit in the Operating Mode Register is set. BR is deasserted for internal

accesses and asserted for external accesses.

DSP56303 Technical Data, Rev. 11

2-26

Freescale Semiconductor

AC Electrical Characteristics

CLKOUT

BR

214

216

212

213

215

BG

BB

217

220

A[0–17]

RD, WR

222

AA[0–3]

Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-23. Bus Acquisition Timings

CLKOUT

BR

214

213

212

BG

219

218

BB

221

A[0–17]

RD, WR

224

223

AA[0–3]

Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-24. Bus Release Timings Case 1 (BRT Bit in Operating Mode Register Cleared)

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-27

Specifications

CLKOUT

BR

212

214

213

BG

BB

219

218

221

A[0–17]

RD, WR

224

223

AA[0–3]

Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-25. Bus Release Timings Case 2 (BRT Bit in Operating Mode Register Set)

DSP56303 Technical Data, Rev. 11

2-28

Freescale Semiconductor

AC Electrical Characteristics

2.5.5.5 Asynchronous Bus Arbitration Timings

1, 2

Table 2-15. Asynchronous Bus Timings

4

100 MHz

3

No.

Characteristics

Expression

Unit

Min

Max

250

251

BB assertion window from BG input deassertion⁵

Delay from BB assertion to BG assertion⁵

2.5 × Tc + 5

2 × Tc + 5

—

30

—

ns

25

Notes: 1. Bit 13 in the Operating Mode Register must be set to enter Asynchronous Arbitration mode.

2. If Asynchronous Arbitration mode is active, none of the timings in Table 2-14 is required.

3. An expression is used to compute the maximum or minimum value listed, as appropriate.

4. Asynchronous Arbitration mode is recommended for operation at 100 MHz.

5. In order to guarantee timings 250, and 251, BG inputs must be asserted to different DSP56300 devices on the same bus in the

non-overlap manner shown in Figure 2-26.

BG1

BB

250

BG2

251

250+251

Figure 2-26. Asynchronous Bus Arbitration Timing

The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs. These

synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this

delay, a DSP56300 part may assume mastership and assert BB, for some time after BG is deasserted. This is the

reason for timing 250.

Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other

DSP56300 components that are potential masters on the same bus. If BG input is asserted before that time, and BG

is asserted and BB is deasserted, another DSP56300 component may assume mastership at the same time.

Therefore, some non-overlap period between one BG input active to another BG input active is required. Timing 251

ensures that overlaps are avoided.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-29

Specifications

2.5.6 Host Interface Timing

1,2,12

Table 2-16. Host Interface Timings

100 MHz

10

No.

Characteristic

Expression

Unit

Min

Max

317 Read data strobe assertion width⁵

HACK assertion width

T_C+ 9.9

19.9

—

ns

318 Read data strobe deassertion width⁵

HACK deassertion width

9.9

—

319 Read data strobe deassertion width⁵after “Last Data Register” reads^8,11, or

between two consecutive CVR, ICR, or ISR reads³

2.5 × T_C+ 6.6

31.6

HACK deassertion width after “Last Data Register” reads^8,11

320 Write data strobe assertion width⁶

—

ns

13.2

321 Write data strobe deassertion width⁸

HACK write deassertion width

•

after ICR, CVR and “Last Data Register” writes

2.5 × T_C+ 6.6

31.8

16.5

—

ns

•

after IVR writes, or

after TXH:TXM:TXL writes (with HLEND= 0), or

after TXL:TXM:TXH writes (with HLEND = 1)

322 HAS assertion width

9.9

0.0

9.9

3.3

—

ns

323 HAS deassertion to data strobe assertion⁴

324 Host data input setup time before write data strobe deassertion⁶

325 Host data input hold time after write data strobe deassertion⁶

326 Read data strobe assertion to output data active from high impedance⁵

HACK assertion to output data active from high impedance

327 Read data strobe assertion to output data valid⁵

HACK assertion to output data valid

—

24.5

9.9

—

ns

328 Read data strobe deassertion to output data high impedance⁵

HACK deassertion to output data high impedance

329 Output data hold time after read data strobe deassertion⁵

Output data hold time after HACK deassertion

3.3

330 HCS assertion to read data strobe deassertion⁵

331 HCS assertion to write data strobe deassertion⁶

332 HCS assertion to output data valid

T_C+ 9.9

19.9

9.9

—

ns

19.3

—

333 HCS hold time after data strobe deassertion⁴

0.0

4.6

3.3

334 Address (HAD[0–7]) setup time before HAS deassertion (HMUX=1)

335 Address (HAD[0–7]) hold time after HAS deassertion (HMUX=1)

—

336 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W setup time before data strobe

assertion⁴

•

Read

Write

0

4.6

—

ns

337 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W hold time after data strobe

deassertion⁴

3.3

—

ns

338 Delay from read data strobe deassertion to host request assertion for “Last Data

Register” read^{5, 7, 8}

T_C+ 5.3

15.3

20.3

339 Delay from write data strobe deassertion to host request assertion for “Last Data

Register” write^{6, 7, 8}

1.5 × T_C+ 5.3

DSP56303 Technical Data, Rev. 11

2-30

Freescale Semiconductor

AC Electrical Characteristics

1,2,12

Table 2-16. Host Interface Timings

(Continued)

100 MHz

Unit

10

No.

Characteristic

Expression

Min

Max

340 Delay from data strobe assertion to host request deassertion for “Last Data

Register” read or write (HROD=0)^{4, 7, 8}

—

19.3

ns

341 Delay from data strobe assertion to host request deassertion for “Last Data

Register” read or write (HROD=1, open drain host request)^{4, 7, 8, 9}

—

300.0

Notes: 1. See the Programmer’s Model section in the chapter on the HI08 in the DSP56303 User’s Manual.

2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.

3. This timing is applicable only if two consecutive reads from one of these registers are executed.

4. The data strobe is Host Read (HRD) or Host Write (HWR) in the Dual Data Strobe mode and Host Data Strobe (HDS) in the

Single Data Strobe mode.

5. The read data strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

6. The write data strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

7. The host request is HREQ in the Single Host Request mode and HRRQ and HTRQ in the Double Host Request mode.

8. The “Last Data Register” is the register at address $7, which is the last location to be read or written in data transfers. This is

RXL/TXL in the Big Endian mode (HLEND = 0; HLEND is the Interface Control Register bit 7—ICR[7]), or RXH/TXH in the

Little Endian mode (HLEND = 1).

9. In this calculation, the host request signal is pulled up by a 4.7 kΩ resistor in the Open-drain mode.

10.

V_CC= 3.3 V ± 0.3 V; T_J= –40°C to +100 °C, C_L= 50 pF

11. This timing is applicable only if a read from the “Last Data Register” is followed by a read from the RXL, RXM, or RXH registers

without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ signal.

12. After the external host writes a new value to the ICR, the HI08 is ready for operation after three DSP clock cycles (3 × Tc).

317

318

HACK

328

327

329

326

H[0–7]

HREQ

Note: The IVR is read only by an MC680xx host processor in non-multiplexed mode.

Figure 2-27. Host Interrupt Vector Register (IVR) Read Timing Diagram

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-31

Specifications

HA[2–0]

336

337

333

337

330

HCS

HRW

HDS

336

317

318

328

332

327

319

329

326

341

H[7–0]

338

340

HREQ (single host request)

HRRQ (double host request)

Figure 2-28. Read Timing Diagram, Non-Multiplexed Bus, Single Data Strobe

HA[2–0]

336

337

333

330

HCS

HRD

317

318

328

332

327

319

329

326

341

H[7–0]

338

340

HREQ (single host request)

HRRQ (double host request)

Figure 2-29. Read Timing Diagram, Non-Multiplexed Bus, Double Data Strobe

DSP56303 Technical Data, Rev. 11

2-32

Freescale Semiconductor

AC Electrical Characteristics

HA[2–0]

336

337

333

337

331

HCS

HRW

HDS

336

320

321

324

325

H[7–0]

339

340

341

HREQ (single host request)

HTRQ (double host request)

Figure 2-30. Write Timing Diagram, Non-Multiplexed Bus, Single Data Strobe

HA[2–0]

336

337

333

331

HCS

320

HWR

321

324

325

H[7–0]

339

340

341

HREQ (single host request)

HTRQ (double host request)

Figure 2-31. Write Timing Diagram, Non-Multiplexed Bus, Double Data Strobe

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-33

Specifications

,

HA[10–8]

336

337

322

HAS

323

336

337

HRW

HDS

317

334

318

319

335

327

328

329

HAD[7–0]

Address

Data

326

338

340

341

HREQ (single host request)

HRRQ (double host request)

Figure 2-32. Read Timing Diagram, Multiplexed Bus, Single Data Strobe

HA[10–8]

336

337

322

HAS

323

317

HRD

334

318

319

335

327

328

329

HAD[7–0]

Address

Data

326

338

340

341

HREQ (single host request)

HRRQ (double host request)

Figure 2-33. Read Timing Diagram, Multiplexed Bus, Double Data Strobe

DSP56303 Technical Data, Rev. 11

2-34

Freescale Semiconductor

AC Electrical Characteristics

HA[10–8]

336

337

322

HAS

HRW

HDS

323

336

320

334

324

321

325

335

HAD[7–0]

Data

340

Address

339

341

HREQ (single host request)

HTRQ (double host request)

Figure 2-34. Write Timing Diagram, Multiplexed Bus, Single Data Strobe

,

HA[10–8]

336

337

322

HAS

323

320

HWR

334

324

321

325

335

HAD[7–0]

Data

340

Address

339

341

HREQ (single host request)

HTRQ (double host request)

Figure 2-35. Write Timing Diagram, Multiplexed Bus, Double Data Strobe

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-35

Specifications

2.5.7 SCI Timing

Table 2-17. SCI Timings

100 MHz

1

No.

Characteristics

Symbol

Expression

Unit

Min

Max

2

400 Synchronous clock cycle

401 Clock low period

t_SCC

8 × T_C

53.3

16.7

8.0

—

ns

t_SCC/2 −10.0

402 Clock high period

t

_SCC/2 −10.0

403 Output data setup to clock falling edge (internal

clock)

t_SCC/4 + 0.5 × T_C−17.0

404 Output data hold after clock rising edge (internal

clock)

t

_SCC/4 −0.5 × T_C

_SCC/4 + 0.5 × T_C+ 25.0

_SCC/4 + 0.5 × T_C−5.5

15.0

50.0

—

ns

405 Input data setup time before clock rising edge

(internal clock)

t

406 Input data not valid before clock rising edge

(internal clock)

t

19.5

32.0

—

407 Clock falling edge to output data valid (external

clock)

—

408 Output data hold after clock rising edge (external

clock)

T_C+ 8.0

18.0

0.0

409 Input data setup time before clock rising edge

(external clock)

—

410 Input data hold time after clock rising edge

(external clock)

9.0

—

3

411 Asynchronous clock cycle

412 Clock low period

t_ACC

64 × T_C

640.0

310.0

290.0

—

ns

t_ACC/2 −10.0

413 Clock high period

414 Output data setup to clock rising edge (internal

clock)

t

_ACC/2 −30.0

415 Output data hold after clock rising edge (internal

clock)

t_ACC/2 −30.0

290.0

—

ns

Notes: 1.

V

t

_CC= 3.3 V ± 0.3 V; T_J= −40°C to +100 °C, C_L= 50 pF.

_SCC= synchronous clock cycle time (for internal clock, t_SCCis determined by the SCI clock control register and T_C).

_ACC= asynchronous clock cycle time; value given for 1X Clock mode (for internal clock, t_ACCis determined by the SCI clock

2.

3.

control register and T_C).

4. An expression is used to compute the number listed as the minimum or maximum value as appropriate.

DSP56303 Technical Data, Rev. 11

2-36

Freescale Semiconductor

AC Electrical Characteristics

400

402

404

401

SCLK

(Output)

403

Data Valid

405

TXD

RXD

406

Data

Valid

a) Internal Clock

400

402

401

SCLK

(Input)

407

408

TXD

RXD

Data Valid

409

410

Data Valid

b) External Clock

Figure 2-36. SCI Synchronous Mode Timing

411

413

415

412

1X SCLK

(Output)

414

TXD

Data Valid

Figure 2-37. SCI Asynchronous Mode Timing

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-37

Specifications

2.5.8 ESSI0/ESSI1 Timing

Table 2-18. ESSI Timings

100 MHz

Min Max

Cond-

ition

4, 5, 7

9

No.

Characteristics

Symbol

Expression

Unit

5

430 Clock cycle¹

t_SSICC

3 × T_C

4 × T_C

30.0

40.0

—

x ck

i ck

ns

431 Clock high period

•

For internal clock

For external clock

2 × T_C- 10.0

1.5 × T_C

10.0

15.0

—

ns

432 Clock low period

•

For internal clock

For external clock

2 × T_C−10.0

1.5 × T_C

10.0

15.0

—

ns

433 RXC rising edge to FSR out (bit-length) high

—

37.0

22.0

x ck

i ck a

ns

434 RXC rising edge to FSR out (bit-length) low

—

37.0

22.0

x ck

i ck a

435 RXC rising edge to FSR out (word-length-relative) high²

436 RXC rising edge to FSR out (word-length-relative) low²

437 RXC rising edge to FSR out (word-length) high

438 RXC rising edge to FSR out (word-length) low

—

39.0

37.0

x ck

i ck a

—

39.0

37.0

x ck

i ck a

—

36.0

21.0

x ck

i ck a

—

37.0

22.0

x ck

i ck a

439 Data in set-up time before RXC (SCK in Synchronous mode)

falling edge

10.0

19.0

—

x ck

i ck

440 Data in hold time after RXC falling edge

5.0

3.0

—

x ck

i ck

441 FSR input (bl, wr)⁷high before RXC falling edge²

442 FSR input (wl)⁷high before RXC falling edge

443 FSR input hold time after RXC falling edge

444 Flags input set-up before RXC falling edge

445 Flags input hold time after RXC falling edge

446 TXC rising edge to FST out (bit-length) high

447 TXC rising edge to FST out (bit-length) low

448 TXC rising edge to FST out (word-length-relative) high²

449 TXC rising edge to FST out (word-length-relative) low²

450 TXC rising edge to FST out (word-length) high

451 TXC rising edge to FST out (word-length) low

452 TXC rising edge to data out enable from high impedance

1.0

23.0

—

x ck

i ck a

3.5

23.0

—

x ck

i ck a

3.0

0.0

—

x ck

i ck a

5.5

19.0

—

x ck

i ck s

6.0

0.0

—

x ck

i ck s

—

29.0

15.0

x ck

i ck

—

31.0

17.0

x ck

i ck

—

31.0

17.0

x ck

i ck

—

33.0

19.0

x ck

i ck

—

30.0

16.0

x ck

i ck

—

31.0

17.0

x ck

i ck

—

31.0

17.0

x ck

i ck

DSP56303 Technical Data, Rev. 11

2-38

Freescale Semiconductor

AC Electrical Characteristics

Table 2-18. ESSI Timings (Continued)

100 MHz

Cond-

4, 5, 7

9

No.

Characteristics

Symbol

Expression

Unit

5

ition

Min

Max

453 TXC rising edge to transmitter 0 drive enable assertion

454 TXC rising edge to data out valid

—

34.0

20.0

20.0⁸

10.0

x ck

i ck

ns

—

x ck

i ck

455 TXC rising edge to data out high impedance³

456 TXC rising edge to Transmitter 0 drive enable deassertion³

457 FST input (bl, wr) set-up time before TXC falling edge²

—

31.0

16.0

x ck

i ck

—

34.0

20.0

x ck

i ck

2.0

21.0

—

x ck

i ck

458 FST input (wl) to data out enable from high impedance

459 FST input (wl) to Transmitter 0 drive enable assertion

460 FST input (wl) set-up time before TXC falling edge

—

27.0

31.0

—

ns

2.5

21.0

—

x ck

i ck

461 FST input hold time after TXC falling edge

462 Flag output valid after TXC rising edge

4.0

0.0

—

x ck

i ck

ns

—

32.0

18.0

x ck

i ck

Notes: 1. For the internal clock, the external clock cycle is defined by Icyc (see Timing 7) and the ESSI Control Register.

2. The word-length-relative frame sync signal waveform operates the same way as the bit-length frame sync signal waveform,

but spreads from one serial clock before the first bit clock (same as the Bit Length Frame Sync signal) until the one before last

bit clock of the first word in the frame.

3. Periodically sampled and not 100 percent tested

4.

V_CC= 3.3 V ± 0.3 V; T_J= −40°C to +100 °C, C_L= 50 pF

5. TXC (SCK Pin) = transmit clock

RXC (SC0 or SCK pin) = receive clock

FST (SC2 pin) = transmit frame sync

FSR (SC1 or SC2 pin) receive frame sync

6. i ck = internal clock

x ck = external clock

i ck a = internal clock, Asynchronous mode

(asynchronous implies that TXC and RXC are two different clocks)

i ck s = Internal Clock, Synchronous mode

(synchronous implies that TXC and RXC are the same clock)

7. bl = bit length; wl = word length; wr = word length relative.

8. If the DSP core writes to the transmit register during the last cycle before causing an underrun error, the delay is 20 ns + (0.5

× T_C).

9. An expression is used to compute the number listed as the minimum or maximum value as appropriate.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-39

Specifications

430

431

432

TXC

(Input/

Output)

446

447

FST (Bit)

Out

450

451

FST (Word)

Out

454

452

454

455

Data Out

First

Last

459

Transmitter 0

Drive

Enable

457

453

456

461

460

FST (Bit) In

458

461

FST (Word)

In

462

See Note

Flags Out

Note:

In Network mode, output flag transitions can occur at the start of each time slot within the

frame. In Normal mode, the output flag state is asserted for the entire frame period.

Figure 2-38. ESSI Transmitter Timing

DSP56303 Technical Data, Rev. 11

2-40

Freescale Semiconductor

AC Electrical Characteristics

430

431

432

RXC

(Input/

Output)

433

434

FSR (Bit)

Out

437

438

FSR

(Word)

Out

440

439

443

Data In

Last Bit

First Bit

441

FSR (Bit)

In

443

445

442

FSR

(Word)

In

444

Flags In

Figure 2-39. ESSI Receiver Timing

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-41

Specifications

2.5.9 Timer Timing

1

Table 2-19. Timer Timing

100 MHz

2

No.

Characteristics

Expression

Unit

Min

Max

480

481

482

2 × T_C+ 2.0

22.0

9.0

—

ns

TIO Low

TIO High

Timer set-up time from TIO (Input) assertion to

CLKOUT rising edge

10.0

483

484

485

Synchronous timer delay time from CLKOUT rising

edge to the external memory access address out valid

caused by first interrupt instruction execution

10.25 × T_C+ 1.0

103.5

—

ns

CLKOUT rising edge to TIO (Output) assertion

•

Minimum

Maximum

0.5 × T_C+ 0.5

0.5 × T_C+ 19.8

5.5

—

24.8

ns

CLKOUT rising edge to TIO (Output) deassertion

•

Minimum

Maximum

0.5 × T_C+ 0.5

0.5 × T_C+ 19.8

5.5

—

24.8

ns

Notes: 1.

V_CC= 3.3 V ± 0.3 V; T_J= −40°C to +100 °C, C_L= 50 pF.

2. An expression is used to compute the number listed as the minimum or maximum value as appropriate.

480

TIO

481

Figure 2-40. TIO Timer Event Input Restrictions

CLKOUT

TIO (Input)

482

Address

483

First Interrupt Instruction Execution

Figure 2-41. Timer Interrupt Generation

CLKOUT

TIO (Output)

484

485

Figure 2-42. External Pulse Generation

DSP56303 Technical Data, Rev. 11

2-42

Freescale Semiconductor

AC Electrical Characteristics

2.5.10 GPIO Timing

Table 2-20. GPIO Timing

100 MHz

Unit

No.

Characteristics

Expression

Min

Max

490

—

0.0

8.5

0.0

67.5

8.5

—

ns

CLKOUT edge to GPIO out valid (GPIO out delay time)

491 CLKOUT edge to GPIO out not valid (GPIO out hold time)

492 GPIO In valid to CLKOUT edge (GPIO in set-up time)

493 CLKOUT edge to GPIO in not valid (GPIO in hold time)

494 Fetch to CLKOUT edge before GPIO change

Minimum: 6.75 × T_C

Note:

V_CC= 3.3 V ± 0.3 V; T_J= −40°C to +100 °C, C_L= 50 pF

CLKOUT

(Output)

490

491

GPIO

(Output)

492

493

GPIO

(Input)

Valid

A[0–17]

494

Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO

and R0 contains the address of the GPIO data register.

Figure 2-43. GPIO Timing

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-43

Specifications

2.5.11 JTAG Timing

Table 2-21. JTAG Timing

All frequencies

Min Max

No.

Characteristics

Unit

500

501

TCK frequency of operation (1/(T_C× 3); maximum 22 MHz)

TCK cycle time in Crystal mode

TCK clock pulse width measured at 1.5 V

TCK rise and fall times

0.0

45.0

20.0

0.0

22.0

—

MHz

ns

502

—

503

3.0

—

504

Boundary scan input data setup time

Boundary scan input data hold time

TCK low to output data valid

5.0

505

24.0

0.0

—

506

40.0

—

507

TCK low to output high impedance

TMS, TDI data setup time

0.0

508

5.0

509

TMS, TDI data hold time

25.0

0.0

—

510

TCK low to TDO data valid

44.0

—

511

TCK low to TDO high impedance

TRST assert time

0.0

512

100.0

40.0

513

TRST setup time to TCK low

—

Notes: 1.

V_CC= 3.3 V ± 0.3 V; T_J= –40°C to +100 °C, C_L= 50 pF.

2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

501

502

V_IH

503

TCK

(Input)

V_M

V_IL

503

Figure 2-44. Test Clock Input Timing Diagram

DSP56303 Technical Data, Rev. 11

2-44

Freescale Semiconductor

AC Electrical Characteristics

V_IH

TCK

(Input)

V_IL

504

505

Data

Inputs

Input Data Valid

506

507

506

Data

Outputs

Output Data Valid

Data

Outputs

Data

Outputs

Output Data Valid

Figure 2-45. Boundary Scan (JTAG) Timing Diagram

V_IH

TCK

(Input)

V_IL

509

508

Input Data Valid

TDI

TMS

(Input)

510

TDO

(Output)

Output Data Valid

511

TDO

(Output)

510

TDO

(Output)

Output Data Valid

Figure 2-46. Test Access Port Timing Diagram

TCK

(Input)

513

TRST

(Input)

512

Figure 2-47. TRST Timing Diagram

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

2-45

Specifications

2.5.12 OnCE Module TimIng

Table 2-22. OnCE Module Timing

Characteristics Expression

No.

Min

Max

Unit

500 TCK frequency of operation

Max 22.0 MHz

1.5 × T_C+ 10.0

5.5 × T_C+ 30.0

0.0

20.0

—

22.0

—

MHz

ns

514 DE assertion time in order to enter Debug mode

515 Response time when DSP56303 is executing NOP instructions from

internal memory

67.0

ns

516 Debug acknowledge assertion time

3 × T_C+ 5.0

25.0

—

ns

Note:

V_CC= 3.3 V ± 0.3 V, V_CC= 1.8 V ± 0.1 V; T_J= –40°C to +100 °C, C_L= 50 pF.

DE

514

515

516

Figure 2-48. OnCE—Debug Request

DSP56303 Technical Data, Rev. 11

2-46

Freescale Semiconductor

Packaging

3

This section includes diagrams of the DSP56303 package pin-outs and tables showing how the signals described in

Chapter 1, are allocated for each package.

The DSP56303 is available in two package types:

•

144-pin Thin Quad Flat Pack (TQFP)

196-pin Molded Array Process-Ball Grid Array (MAP-BGA)

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

3-1

Packaging

3.1 TQFP Package Description

Top and bottom views of the TQFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs.

109

A0

BG

D7

D8

(Top View)

AA0

AA1

RD

WR

V_CCD

GND_D

D9

D10

GND_C

V_CCC

D11

D12

BB

D13

BR

D14

TA

V_CCD

GND_D

D15

D16

D17

BCLK

CLKOUT

GND_C

V_CCC

V_CCQ

EXTAL

GND_Q

XTAL

CAS

D18

D19

V_CCQ

GND_Q

D20

V_CCD

GND_D

D21

AA2

AA3

NC

D22

GND_P1

GND_P

PCAP

V_CCP

D23

MODD

MODC

MODB

MODA

TRST

TDO

TDI

TCK

TMS

SC12

SC11

RESET

HAD0

HAD1

HAD2

HAD3

GND_H

V_CCH

Orientation Mark

HAD4

37

Notes: Because of size constraints in this figure, only one name is shown for multiplexed pins. Refer to Table 3-1 and Table

3-2 for detailed information about pin functions and signal names.

Figure 3-1. DSP56303 Thin Quad Flat Pack (TQFP), Top View

DSP56303 Technical Data, Rev. 11

3-2

Freescale Semiconductor

TQFP Package Description

A0

BG

109

D7

D8

(Bottom View)

V_CCD

GND_D

D9

AA0

AA1

RD

D10

D11

D12

D13

D14

V_CCD

GND_D

D15

D16

D17

D18

WR

GND_C

V_CCC

BB

BR

TA

BCLK

CLKOUT

GND_C

V_CCC

D19

V_CC

Q

V_CCQ

GND_Q

EXTAL

GND_Q

D20

V_CCD

GND_D

D21

D22

XTAL

CAS

AA2

AA3

NC

GND_P1

GND_P

PCAP

V_CCP

RESET

HAD0

HAD1

HAD2

HAD3

GND_H

D23

MODD

MODC

MODB

MODA

TRST

TDO

TDI

TCK

TMS

SC12

Orientation Mark

(on top side)

V_CC

H

SC11

37

HAD4

Notes: Because of size constraints in this figure, only one name is shown for multiplexed pins. Refer to Table 3-1 and Table

3-2 for detailed information about pin functions and signal names.

Figure 3-2. DSP56303 Thin Quad Flat Pack (TQFP), Bottom View

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

3-3

Packaging

Table 3-1. DSP56303 TQFP Signal Identification by Pin Number

No.

Signal Name

1

2

SRD1 or PD4

STD1 or PD5

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

GND_S

TIO2

TIO1

TIO0

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

AA2/RAS2

CAS

3

SC02 or PC2

SC01 or PC1

DE

XTAL

GND_Q

EXTAL

V_CCQ

V_CCC

GND_C

CLKOUT

BCLK

TA

4

5

HCS/HCS, HA10, or PB13

HA2, HA9, or PB10

HA1, HA8, or PB9

HA0, HAS/HAS, or PB8

H7, HAD7, or PB7

H6, HAD6, or PB6

H5, HAD5, or PB5

H4, HAD4, or PB4

V_CCH

6

PINIT/NMI

7

SRD0 or PC4

V_CCS

8

9

GND_S

10

11

12

13

14

15

16

17

18

19

20

21

22

23

STD0 or PC5

SC10 or PD0

SC00 or PC0

RXD or PE0

BR

TXD or PE1

GND_H

BB

SCLK or PE2

SCK1 or PD3

SCK0 or PC3

V_CCQ

H3, HAD3, or PB3

H2, HAD2, or PB2

H1, HAD1, or PB1

H0, HAD0, or PB0

RESET

V_CCC

GND_C

WR

RD

GND_Q

AA1/RAS1

AA0/RAS0

BG

Not Connected (NC), reserved

HDS/HDS, HWR/HWR, or PB12

HRW, HRD/HRD, or PB11

V_CCP

PCAP

GND_P

A0

HACK/HACK,

GND_P1

A1

HRRQ/HRRQ, or PB15

24

25

HREQ/HREQ,

HTRQ/HTRQ, or PB14

49

50

Not Connected (NC), reserved

AA3/RAS3

74

75

V_CCA

V_CCS

GND_A

DSP56303 Technical Data, Rev. 11

3-4

Freescale Semiconductor

TQFP Package Description

Signal Name

Table 3-1. DSP56303 TQFP Signal Identification by Pin Number (Continued)

No.

Signal Name

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

A2

99

A17

122 D16

123 D17

124 D18

125 D19

126 V_CCQ

127 GND_Q

128 D20

129 V_CCD

130 GND_D

131 D21

132 D22

133 D23

A3

100 D0

A4

101 D1

A5

102 D2

V_CCA

GND_A

A6

103 V_CCD

104 GND_D

105 D3

A7

106 D4

A8

107 D5

A9

108 D6

V_CCA

GND_A

A10

A11

GND_Q

V_CCQ

A12

A13

A14

V_CCA

GND_A

A15

A16

109 D7

110 D8

111 V_CCD

112 GND_D

113 D9

134 MODD/IRQD

135 MODC/IRQC

136 MODB/IRQB

137 MODA/IRQA

138 TRST

114 D10

115 D11

116 D12

117 D13

118 D14

119 V_CCD

120 GND_D

121 D15

139 TDO

140 TDI

141 TCK

142 TMS

143 SC12 or PD2

144 SC11 or PD1

Notes: Signal names are based on configured functionality. Most pins supply a single signal. Some pins provide a signal with dual

functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted but act as interrupt lines during

operation. Some signals have configurable polarity; these names are shown with and without overbars, such as HAS/HAS. Some

pins have two or more configurable functions; names assigned to these pins indicate the function for a specific configuration. For

example, Pin 34 is data line H7 in non-multiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7

when the GPIO function is enabled for this pin.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

3-5

Packaging

Table 3-2. DSP56303 TQFP Signal Identification by Name

No.

Signal Name

A0

A1

72

73

88

89

92

93

94

97

98

99

76

77

78

79

82

83

84

85

70

69

51

50

64

60

61

BG

BR

71

D7

109

110

113

5

63

D8

A10

A11

A12

A13

A14

A15

A16

A17

A2

CAS

CLKOUT

D0

52

D9

59

DE

100

101

114

115

116

117

118

121

122

123

124

125

102

128

131

132

133

105

106

107

108

EXTAL

GND_A

GND_C

GND_D

GND_H

GND_P

GND_P1

GND_Q

GND_S

H0

55

D1

75

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D2

81

87

96

58

66

A3

104

112

120

130

39

A4

A5

A6

A7

A8

47

A9

D20

D21

D22

D23

D3

48

AA0

AA1

AA2

AA3

BB

19

54

90

127

9

D4

BCLK

D5

26

D6

43

DSP56303 Technical Data, Rev. 11

3-6

Freescale Semiconductor

TQFP Package Description

Table 3-2. DSP56303 TQFP Signal Identification by Name (Continued)

No.

Signal Name

H1

H2

42

41

40

37

36

35

34

33

32

30

31

32

31

23

43

42

41

40

37

36

35

34

33

30

21

HRD/HRD

HREQ/HREQ

HRRQ/HRRQ

HRW

22

24

PB2

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PC0

PC1

PC2

PC3

PC4

PC5

PCAP

PD0

PD1

PD2

PD3

PD4

PD5

PE0

PE1

PE2

PINIT

41

40

37

36

35

34

33

32

12

4

H3

23

H4

22

H5

HTRQ/HTRQ

HWR/HWR

IRQA

24

H6

21

H7

137

136

135

134

137

136

135

134

20

HA0

IRQB

HA1

IRQC

HA10

HA2

IRQD

MODA

MODB

MODC

MODD

NC

3

HA8

17

7

HA9

HACK/HACK

HAD0

HAD1

HAD2

HAD3

HAD4

HAD5

HAD6

HAD7

HAS/HAS

HCS/HCS

HDS/HDS

10

46

11

144

143

16

1

NMI

6

NC

49

PB0

43

PB1

42

PB10

31

PB11

22

2

PB12

21

13

14

15

6

PB13

30

PB14

24

PB15

23

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

3-7

Packaging

Table 3-2. DSP56303 TQFP Signal Identification by Name (Continued)

No.

Signal Name

RAS0

RAS1

RAS2

RAS3

RD

70

69

51

50

68

44

13

12

4

SRD1

STD0

STD1

TA

1

V_CCC

V_CCD

V_CCH

V_CCP

V_CCQ

V_CCS

WR

57

65

10

2

103

111

119

129

38

62

TCK

TDI

141

140

139

29

RESET

RXD

TDO

TIO0

TIO1

TIO2

TMS

TRST

TXD

V_CCA

SC00

SC01

SC02

SC10

SC11

SC12

SCK0

SCK1

SCLK

SRD0

45

28

18

3

27

56

11

144

143

17

16

15

7

142

138

14

91

126

8

74

25

80

67

86

XTAL

53

95

DSP56303 Technical Data, Rev. 11

3-8

Freescale Semiconductor

TQFP Package Mechanical Drawing

3.2 TQFP Package Mechanical Drawing

0.20 T L-M N

4X

4X 36 TIPS

Pin 1

ident

144

109

1

108

4X

P

J1

M

L

C

L

V

B

X

X=L, M or N

140X

G

B1

V1

View Y

36

73

Notes:

1. Dimensions and tolerancing per ASME

Y14.5, 1994.

2. Dimensions in millimeters.

3. Datums L, M and N tobe determinedat the

seating plane, datum T.

37

72

N

4. Dimensions S and V to be determined at

the seating plane, datum T.

5. Dimensions A and B do not include mold

protrusion. Allowableprotrusionis 0.25per

side. Dimensions A and B do include mold

mismatch and are determined at datum

plane H.

A1

S1

A

S

6. Dimension D does not include dambar

protrusion. Allowable dambar protrusion

shall not cause the D dimension to exceed

0.35.

View AB

C

144X

0.1 T

θ2

Millimeters

MIN

MAX

DIM

A

A1

B

B1

C

Seating

plane

20.00 BSC

10.00 BSC

20.00 BSC

10.00 BSC

θ

2

T

1.40

C1 0.05

C2 1.35

1.60

0.15

1.45

0.27

0.75

0.23

Plating

D

E

F

0.17

0.45

0.17

J

C2

AA

F

— 0.05

G

J

K

P

0.50 BSC

R2

0.09

0.20

θ

0.50 REF

0.25 BSC

R1

R1 0.13

R2 0.13

0.20

S

S1

V

V1

Y

22.00 BSC

11.00 BSC

22.00 BSC

11.00 BSC

0.25 REF

1.00 REF

Base

0.25

Gage plane

metal

D

M

0.08

T L-M N

Z

Section J1-J1

(K)

E

AA 0.09

θ

θ1

θ2

0.16

(rotated 90)

144 PL

C1

0°

7°

13°

θ1

(Y)

View AB

11°

(Z)

CASE 918-03

ISSUE C

Figure 3-3. DSP56303 Mechanical Information, 144-pin TQFP Package

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

3-9

Packaging

3.3 MAP-BGA Package Description

Top and bottom views of the MAP-BGA package are shown in Figure 3-4 and Figure 3-5 with

their pin-outs.

Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

A

B

NC

SC11

TMS

TDO MODB

D23

V_CCD

D19

D16

D14

D11

D9

D7

NC

SRD1 SC12

SC02 STD1

PINIT SC01

TDI

TRST MODD D21

D20

V_CCQ

GND

NC

D17

D18

D15

V_CCD

GND

D13

D12

D10

V_CCD

GND

WR

D8

D6

D5

D3

NC

D4

TCK MODA MODC D22

C

DE

GND

PB0

GND

V_CCP

GND

EXTAL

CAS

GND

BCLK

D1

D2

V_CCD

D

E

F

STD0 V_CCSSRD0 GND

A17

V_CCA

A13

V_CCA

A8

A16

A14

V_CCQ

A10

A7

D0

RXD

SC10 SC00

GND

A15

A12

A11

A9

G

SCK1 SCLK

TXD

NC

V_CCQSCK0 GND

H

J

HACK HRW

HDS

GND

V_CCH

H2

K

V_CCSHREQ TIO2

V_CCA

RD

A5

A6

HCS

HA1

H6

TIO1

HA2

H7

TIO0

HA0

H4

A3

A4

L

CLK

OUT

M

A1

A2

N

P

RESET GND_P

AA3

V_CCQBCLK

BR

V_CCC

AA1

AA0

BG

A0

NC

H5

H3

H1

PCAP GND_P1AA2

XTAL

V_CCC

TA

BB

NC

Figure 3-4. DSP56303 Molded Array Process-Ball Grid Array (MAP-BGA), Top View

DSP56303 Technical Data, Rev. 11

3-10

Freescale Semiconductor

MAP-BGA Package Description

Bottom View

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A

B

NC

D7

D9

D11

D14

D16

D19

V_CCD

D23

MODB TDO

MODD TRST

TMS

SC11

NC

D4

D5

D3

D8

D6

D10

V_CCD

GND

WR

D13

D12

D15

V_CCD

GND

D17

D18

D20

V_CCQ

GND

NC

D21

D22

TDI

SC12 SRD1

STD1 SC02

SC01 PINIT

MODC MODA TCK

C

V_CCD

D2

D1

GND

BCLK

GND

EXTAL

CAS

GND

V_CCP

GND

PB0

GND

DE

D

E

F

D0

A16

A14

V_CCQ

A10

A7

A17

V_CCA

A13

V_CCA

A8

GND SRD0 V_CCSSTD0

A15

A12

A11

A9

GND SC00 SC10

RXD

G

GND

TXD

SCLK SCK1

GND SCK0 V_CCQ

NC

H

J

GND

V_CCH

H2

HDS

HRW HACK

K

A6

A5

V_CCA

RD

TIO2 HREQ V_CCS

A4

A3

TIO0

HA0

H4

TIO1

HA2

H7

HCS

HA1

H6

L

CLK

OUT

M

A2

A1

N

P

A0

AA0

BG

V_CCC

AA1

BR

BCLK V_CCQ

AA3

GND_PRESET

NC

BB

TA

V_CCC

XTAL

AA2 GND_P1PCAP

H1

H3

H5

NC

Figure 3-5. DSP56303 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

3-11

Packaging

Table 3-3. DSP56303 MAP-BGA Signal Identification by Pin Number

No.

Signal Name

A1

A2

Not Connected (NC), reserved

B12

B13

B14

C1

D8

D5

D9

D10

D11

D12

D13

D14

E1

GND

SC11 or PD1

TMS

A3

NC

GND

A4

TDO

SC02 or PC2

STD1 or PD5

TCK

D1

A5

MODB/IRQB

D23

C2

D2

A6

C3

V_CCD

A7

V_CCD

C4

MODA/IRQA

MODC/IRQC

D22

STD0 or PC5

V_CCS

A8

D19

C5

E2

A9

D16

C6

E3

SRD0 or PC4

GND

A10

A11

A12

A13

A14

B1

D14

C7

V_CCQ

E4

D11

C8

D18

E5

GND

D9

C9

V_CCD

E6

GND

D7

C10

C11

C12

C13

C14

D1

D12

E7

GND

NC

V_CCD

E8

GND

SRD1 or PD4

SC12 or PD2

TDI

D6

E9

GND

B2

D3

E10

E11

E12

E13

E14

F1

GND

B3

D4

GND

B4

TRST

MODD/IRQD

D21

PINIT/NMI

SC01 or PC1

DE

A17

B5

D2

A16

B6

D3

D0

B7

D20

D4

GND

RXD or PE0

SC10 or PD0

SC00 or PC0

GND

B8

D17

D5

GND

F2

B9

D15

D6

GND

F3

B10

B11

D13

D7

GND

F4

D10

D8

GND

F5

GND

DSP56303 Technical Data, Rev. 11

3-12

Freescale Semiconductor

MAP-BGA Package Description

Signal Name

Table 3-3. DSP56303 MAP-BGA Signal Identification by Pin Number (Continued)

No.

Signal Name

F6

F7

F8

GND

H3

H4

H5

SCK0 or PC3

GND

J14

K1

K2

A9

V_CCS

GND

HREQ/HREQ,

HTRQ/HTRQ, or PB14

F9

F10

F11

F12

F13

F14

G1

GND

H6

H7

GND

V_CCA

A10

K3

K4

TIO2

GND

V_CCA

GND

H8

K5

V_CCA

H9

K6

A14

H10

H11

H12

H13

H14

J1

K7

A15

K8

SCK1 or PD3

SCLK or PE2

TXD or PE1

GND

K9

G2

K10

K11

K12

G3

A11

G4

HACK/HACK,

HRRQ/HRRQ, or PB15

G5

G6

GND

A13

J2

J3

HRW, HRD/HRD, or PB11

K13

K14

L1

A5

HDS/HDS, HWR/HWR, or PB12

A6

G7

J4

GND

HCS/HCS, HA10, or PB13

G8

J5

GND

L2

TIO1

G9

J6

GND

L3

TIO0

G10

G11

G12

G13

G14

H1

J7

GND

L4

GND

J8

GND

L5

GND

J9

GND

L6

V_CCQ

A12

J10

J11

J12

J13

M13

M14

N1

N2

GND

L7

GND

L8

GND

NC

A8

L9

GND

H2

V_CCQ

GND

V_CCA

A3

A7

L10

P1

P2

P3

P4

GND

L11

L12

L13

L14

A1

NC

A2

H5, HAD5, or PB5

H3, HAD3, or PB3

H1, HAD1, or PB1

H6, HAD6, or PB6

H7, HAD7, or PB7

A4

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

3-13

Packaging

Table 3-3. DSP56303 MAP-BGA Signal Identification by Pin Number (Continued)

No.

Signal Name

M1

M2

HA1, HA8, or PB9

N3

N4

H4, HAD4, or PB4

H2, HAD2, or PB2

RESET

GND_P

P5

P6

PCAP

GND_P1

AA2/RAS2

XTAL

V_CCC

HA2, HA9, or PB10

M3

HA0, HAS/HAS, or PB8

N5

P7

M4

V_CCH

H0, HAD0, or PB0

V_CCP

N6

P8

M5

N7

AA3/RAS3

CAS

P9

M6

N8

P10

P11

P12

P13

P14

TA

M7

NC

N9

V_CCQ

BB

M8

EXTAL

CLKOUT

BCLK

N10

N11

N12

N13

N14

BCLK

AA1/RAS1

BG

M9

BR

M10

M11

M12

V_CCC

NC

WR

AA0/RAS0

A0

RD

Notes: Signal names are based on configured functionality. Most connections supply a single signal. Some connections

provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is

deasserted but act as interrupt lines during operation. Some signals have configurable polarity; these names are

shown with and without overbars, such as HAS/HAS. Some connections have two or more configurable functions;

names assigned to these connections indicate the function for a specific configuration. For example, connection N2

is data line H7 in non-multiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7

when the GPIO function is enabled for this pin. Unlike in the TQFP package, most of the GND pins are connected

internally in the center of the connection array and act as heat sink for the chip. Therefore, except for GND and

P

GND that support the PLL, other GND signals do not support individual subsystems in the chip.

P1

DSP56303 Technical Data, Rev. 11

3-14

Freescale Semiconductor

MAP-BGA Package Description

Table 3-4. DSP56303 MAP-BGA Signal Identification by Name

No.

Signal Name

A0

A1

N14

M13

H13

H14

G14

G12

F13

F14

E13

E12

M14

L13

L14

K13

K14

J13

J12

J14

N13

P12

P7

BG

BR

P13

N11

N8

D7

D8

A13

B12

A12

D3

A10

A11

A12

A13

A14

A15

A16

A17

A2

CAS

CLKOUT

D0

D9

M9

DE

E14

D12

B11

A11

C10

B10

A10

B9

EXTAL

GND

M8

D4

D1

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D2

D5

D6

D7

D8

D9

A3

D10

D11

E4

A4

A9

A5

B8

A6

C8

E5

A7

A8

E6

A8

D13

B7

E7

A9

D20

D21

D22

D23

D3

E8

AA0

AA1

AA2

AA3

BB

B6

E9

C6

E10

E11

F4

A6

N7

C13

C14

B13

C12

P11

M10

N10

D4

F5

BCLK

D5

F6

D6

F7

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

3-15

Packaging

Table 3-4. DSP56303 MAP-BGA Signal Identification by Name (Continued)

No.

Signal Name

GND

F8

F9

GND

GND_P

GND_P1

H0

J9

J10

J11

K4

K5

K6

K7

K8

K9

K10

K11

L4

H4

H5

N3

P2

N1

N2

M3

M1

L1

F10

F11

G4

G5

G6

G7

G8

G9

G10

G11

H4

H5

H6

H7

H8

H9

H10

H11

J4

H6

H7

HA0

HA1

HA10

HA2

M2

M1

M2

J1

HA8

HA9

HACK/HACK

HAD0

M5

P4

N4

P3

N3

P2

N1

N2

M3

L1

L5

HAD1

L6

HAD2

L7

HAD3

L8

HAD4

L9

HAD5

L10

L11

N6

P6

M5

P4

N4

P3

HAD6

HAD7

HAS/HAS

HCS/HCS

HDS/HDS

HRD/HRD

HREQ/HREQ

HRRQ/HRRQ

J5

J3

J6

H1

J2

J7

H2

K2

J1

J8

H3

DSP56303 Technical Data, Rev. 11

3-16

Freescale Semiconductor

MAP-BGA Package Description

Table 3-4. DSP56303 MAP-BGA Signal Identification by Name (Continued)

No.

Signal Name

HRW

HTRQ/HTRQ

HWR/HWR

IRQA

IRQB

IRQC

IRQD

MODA

MODB

MODC

MODD

NC

J2

K2

J3

PB14

PB15

PB2

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PC0

PC1

PC2

PC3

PC4

PC5

PCAP

PD0

PD1

PD2

PD3

PD4

PD5

PE0

PE1

K2

J1

PE2

PINIT

RAS0

RAS1

RAS2

RAS3

RD

G2

D1

N13

P12

P7

N7

M12

N5

F1

N4

P3

N3

P2

N1

N2

M3

M1

F3

D2

C1

H3

E3

E1

P5

F2

A2

B2

G1

B1

C2

F1

G3

C4

A5

C5

B5

C4

A5

C5

B5

A1

A14

B14

H1

M7

P1

P14

D1

M5

P4

M2

J2

RESET

RXD

SC00

SC01

SC02

SC10

SC11

SC12

SCK0

SCK1

SCLK

SRD0

SRD1

STD0

STD1

TA

F3

D2

C1

F2

NC

A2

B2

H3

G1

G2

E3

B1

E1

C2

P10

C3

B3

NC

NMI

PB0

PB1

PB10

PB11

PB12

PB13

J3

TCK

L1

TDI

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

3-17

Packaging

Table 3-4. DSP56303 MAP-BGA Signal Identification by Name (Continued)

No.

Signal Name

TDO

TIO0

TIO1

TIO2

TMS

TRST

TXD

A4

L3

V_CCA

V_CCC

V_CCD

V_CCH

K12

L12

N12

P9

V_CCP

V_CCQ

V_CCS

WR

M6

C7

L2

G13

H2

K3

A3

A7

N9

B4

C9

E2

G3

F12

H12

C11

D14

M4

K1

V_CCA

M11

P8

XTAL

3.4 MAP-BGA Package Mechanical Drawing

Figure 3-6. DSP56303 Mechanical Information, 196-pin MAP-BGA Package

DSP56303 Technical Data, Rev. 11

3-18

Freescale Semiconductor

Design Considerations

4

This section describes various areas to consider when incorporating the DSP56303 device into a system design.

4.1 Thermal Design Considerations

An estimate of the chip junction temperature, T , in ° C can be obtained from this equation:

J

Equation 1: T_J= T_A+ (P_D× R_θJA

±

Where:

T

=

ambient temperature °C

A

R

package junction-to-ambient thermal resistance °C/W

power dissipation in package

θJA

P

D

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-

to-ambient thermal resistance, as in this equation:

Equation 2: R_θJA= R_θJC+ R_θCA

Where:

R

=

package junction-to-ambient thermal resistance °C/W

package junction-to-case thermal resistance °C/W

package case-to-ambient thermal resistance °C/W

θJA

θJC

θCA

R

is device-related and cannot be influenced by the user. The user controls the thermal environment to change

θJC

the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around the device, add

θCA

a heat sink, change the mounting arrangement on the printed circuit board (PCB) or otherwise change the thermal

dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages

with heat sinks; some 90 percent of the heat flow is dissipated through the case to the heat sink and out to the

ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case

and an alternate path through the PCB, analysis of the device thermal performance may need the additional

modeling capability of a system-level thermal simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the

package is mounted. Again, if the estimates obtained from R

do not satisfactorily answer whether the thermal

θJA

performance is adequate, a system-level model may be appropriate.

A complicating factor is the existence of three common ways to determine the junction-to-case thermal resistance

in plastic packages.

•

To minimize temperature variation across the surface, the thermal resistance is measured from the junction

to the outside surface of the package (case) closest to the chip mounting area when that surface has a

proper heat sink.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

4-1

Design Considerations

•

To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is

measured from the junction to the point at which the leads attach to the case.

If the temperature of the package case (T ) is determined by a thermocouple, thermal resistance is

T

computed from the value obtained by the equation (T – T )/P .

J

T

D

As noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using the first

definition. From a practical standpoint, that value is also suitable to determine the junction temperature from a case

thermocouple reading in forced convection environments. In natural convection, the use of the junction-to-case

thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will

yield an estimate of a junction temperature slightly higher than actual temperature. Hence, the new thermal metric,

thermal characterization parameter or Ψ , has been defined to be (T – T )/P . This value gives a better estimate of

JT

J

T

D

the junction temperature in natural convection when the surface temperature of the package is used. Remember that

surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the

sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-

gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

4.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to

guard against damage due to high static

voltage or electrical fields. However, normal

precautions are advised to avoid application

of any voltages higher than maximum rated

voltages to this high-impedance circuit.

Reliability of operation is enhanced if unused

inputs are tied to an appropriate logic voltage

level (for example, either GND or V ).

CC

Use the following list of recommendations to ensure correct DSP operation.

•

Provide a low-impedance path from the board power supply to each V_CCpin on the DSP and from the

board ground to each GND pin.

Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the four sides of the

package to connect the V_CCpower source to GND.

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V_CCand GND pins

are less than 0.5 inch per capacitor lead.

•

Use at least a four-layer PCB with two inner layers for V_CCand GND.

Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This

recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQC, IRQD,

TA, and BG pins. Maximum PCB trace lengths on the order of 6 inches are recommended.

DSP56303 Technical Data, Rev. 11

4-2

Freescale Semiconductor

Power Consumption Considerations

•

Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate

capacitance. This is especially critical in systems with higher capacitive loads that could create higher

transient currents in the V_CCand GND circuits.

All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins with

internal pull-up resistors (TRST, TMS, DE).

•

Take special care to minimize noise levels on the V_CCP, GND , and GND_P1pins.

P

The following pins must be asserted after power-up: RESET and TRST.

If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies due

to synchronous operation of the devices.

•

RESET must be asserted when the chip is powered up. A stable EXTAL signal should be supplied before

deassertion of RESET.

At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V never

CC

exceeds 3.5 V.

4.3 Power Consumption Considerations

Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current consumption

are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is

charging and discharging the capacitances of the pins and internal nodes.

Current consumption is described by this formula:

Equation 3: I = C × V × f

Where:

C

V

f

=

node/pin capacitance

voltage swing

frequency of node/pin toggle

Example 4-1. Current Consumption

For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33

MHz), the current consumption is expressed in Equation 4.

Equation 4: I = 50 × 10^–12× 3.3 × 33 × 10⁶= 5.48 mA

The maximum internal current (I max) value reflects the typical possible switching of the internal buses on best-

CCI

case operation conditions—not necessarily a real application case. The typical internal current (I

reflects the average switching of the internal buses on typical operating conditions.

) value

CCItyp

Perform the following steps for applications that require very low current consumption:

1. Set the EBD bit when you are not accessing external memory.

2. Minimize external memory accesses, and use internal memory accesses.

3. Minimize the number of pins that are switching.

4. Minimize the capacitive load on the pins.

5. Connect the unused inputs to pull-up or pull-down resistors.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

4-3

Design Considerations

6. Disable unused peripherals.

7. Disable unused pin activity (for example, CLKOUT, XTAL).

One way to evaluate power consumption is to use a current-per-MIPS measurement methodology to minimize

specific board effects (that is, to compensate for measured board current not caused by the DSP). A benchmark

power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current

measurements, and the following equation to derive the current-per-MIPS value.

Equation 5: I ⁄ MIPS = I ⁄ MHz = (I_typF2– I_typF1± ⁄ (F2 – F1±

Where:

I

=

current at F2

current at F1

typF2

typF1

F2

F1

=

high frequency (any specified operating frequency)

low frequency (any specified operating frequency lower than F2)

Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The

degree of difference between F1 and F2 determines the amount of precision with which the current rating

can be determined for an application.

4.4 PLL Performance Issues

The following explanations should be considered as general observations on expected PLL behavior. There is no

test that replicates these exact numbers. These observations were measured on a limited number of parts and were

not verified over the entire temperature and voltage ranges.

4.4.1 Phase Skew Performance

The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and CLKOUT for a

given capacitive load on CLKOUT, over the entire process, temperature and voltage ranges. As defined in Figure 2-

2, External Clock Timing, on page 2-5 for input frequencies greater than 15 MHz and the MF ≤4, this skew is

greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10

and input frequencies greater than 10 MHz, this skew is between −1.4 ns and +3.2 ns.

4.4.2 Phase Jitter Performance

The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and CLKOUT

for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on CLKOUT. These

variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz and MF ≤4, this

jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies

greater than 10 MHz, this jitter is less than ±2 ns.

4.4.3 Frequency Jitter Performance

The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF < 10)

this jitter is smaller than 0.5 percent. For mid-range MF (10 < MF < 500) this jitter is between 0.5 percent and

approximately 2 percent. For large MF (MF > 500), the frequency jitter is 2–3 percent.

DSP56303 Technical Data, Rev. 11

4-4

Freescale Semiconductor

Input (EXTAL) Jitter Requirements

4.5 Input (EXTAL) Jitter Requirements

The allowed jitter on the frequency of EXTAL is 0.5 percent. If the rate of change of the frequency of EXTAL is slow

(that is, it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is

fast (that is, it does not stay at an extreme value for a long time), then the allowed jitter can be 2 percent. The phase

and frequency jitter performance results are valid only if the input jitter is less than the prescribed values.

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

4-5

Design Considerations

DSP56303 Technical Data, Rev. 11

4-6

Freescale Semiconductor

Power Consumption Benchmark A

The following benchmark program evaluates DSP56303 power use in a test situation. It enables the PLL, disables

the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP

application data to emulate intensive sustained DSP operation.

;**************************************************************************

;*

*

CHECKS

Typical Power Consumption

;**************************************************************************

page

200,55,0,0,0

nolist

I_VEC EQU $000000; Interrupt vectors for program debug only

START EQU $8000; MAIN (external) program starting address

INT_PROG EQU $100 ; INTERNAL program memory starting address

INT_XDAT EQU $0; INTERNAL X-data memory starting address

INT_YDAT EQU $0; INTERNAL Y-data memory starting address

INCLUDE "ioequ.asm"

INCLUDE "intequ.asm"

list

org

P:START

;

movep #$0243FF,x:M_BCR ;; BCR: Area 3 = 2 w.s (SRAM)

; Default: 2w.s (SRAM)

;

movep #$0d0000,x:M_PCTL

; XTAL disable

; PLL enable

; CLKOUT disable

;

; Load the program

;

move

do

move

nop

#INT_PROG,r0

#PROG_START,r1

#(PROG_END-PROG_START),PLOAD_LOOP

p:(r1)+,x0

x0,p:(r0)+

PLOAD_LOOP

;

; Load the X-data

;

move

do

#INT_XDAT,r0

#XDAT_START,r1

#(XDAT_END-XDAT_START),XLOAD_LOOP

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

A-1

Power Consumption Benchmark

move

p:(r1)+,x0

x0,x:(r0)+

XLOAD_LOOP

;

; Load the Y-data

;

move

do

move

#INT_YDAT,r0

#YDAT_START,r1

#(YDAT_END-YDAT_START),YLOAD_LOOP

p:(r1)+,x0

x0,y:(r0)+

YLOAD_LOOP

;

jmp

INT_PROG

PROG_START

move

#$0,r0

#$0,r4

#$3f,m0

#$3f,m4

move

;

clr

a

clr

b

move

bset

#$0,x0

#$0,x1

#$0,y0

#$0,y1

#4,omr

; ebd

;

sbr

dor

mac

add

mac

move

#60,_end

x0,y0,ax:(r0)+,x1

x1,y1,ax:(r0)+,x0

a,b

x0,y0,ax:(r0)+,x1

x1,y1,a

y:(r4)+,y1

y:(r4)+,y0

b1,x:$ff

_end

bra

nop

sbr

PROG_END

nop

XDAT_START

;

org

dc

x:0

$262EB9

$86F2FE

$E56A5F

$616CAC

$8FFD75

$9210A

$A06D7B

$CEA798

$8DFBF1

$A063D6

DSP56303 Technical Data, Rev. 11

A-2

Freescale Semiconductor

dc

$6C6657

$C2A544

$A3662D

$A4E762

$84F0F3

$E6F1B0

$B3829

$8BF7AE

$63A94F

$EF78DC

$242DE5

$A3E0BA

$EBAB6B

$8726C8

$CA361

$2F6E86

$A57347

$4BE774

$8F349D

$A1ED12

$4BFCE3

$EA26E0

$CD7D99

$4BA85E

$27A43F

$A8B10C

$D3A55

$25EC6A

$2A255B

$A5F1F8

$2426D1

$AE6536

$CBBC37

$6235A4

$37F0D

$63BEC2

$A5E4D3

$8CE810

$3FF09

$60E50E

$CFFB2F

$40753C

$8262C5

$CA641A

$EB3B4B

$2DA928

$AB6641

$28A7E6

$4E2127

$482FD4

$7257D

$E53C72

$1A8C3

$E27540

XDAT_END

YDAT_START

;

org

dc

y:0

$5B6DA

$C3F70B

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

A-3

Power Consumption Benchmark

dc

$6A39E8

$81E801

$C666A6

$46F8E7

$AAEC94

$24233D

$802732

$2E3C83

$A43E00

$C2B639

$85A47E

$ABFDDF

$F3A2C

$2D7CF5

$E16A8A

$ECB8FB

$4BED18

$43F371

$83A556

$E1E9D7

$ACA2C4

$8135AD

$2CE0E2

$8F2C73

$432730

$A87FA9

$4A292E

$A63CCF

$6BA65C

$E06D65

$1AA3A

$A1B6EB

$48AC48

$EF7AE1

$6E3006

$62F6C7

$6064F4

$87E41D

$CB2692

$2C3863

$C6BC60

$43A519

$6139DE

$ADF7BF

$4B3E8C

$6079D5

$E0F5EA

$8230DB

$A3B778

$2BFE51

$E0A6B6

$68FFB7

$28F324

$8F2E8D

$667842

$83E053

$A1FD90

$6B2689

$85B68E

$622EAF

DSP56303 Technical Data, Rev. 11

A-4

Freescale Semiconductor

dc

$6162BC

$E4A245

YDAT_END

;**************************************************************************

;

EQUATES for DSP56303 I/O registers and ports

Last update: June 11 1995

;**************************************************************************

page

opt

132,55,0,0,0

mex

ioequ

ident

1,0

;------------------------------------------------------------------------

;

EQUATES for I/O Port Programming

;------------------------------------------------------------------------

Register Addresses

;

M_HDR EQU $FFFFC9

M_HDDR EQU $FFFFC8

M_PCRC EQU $FFFFBF

M_PRRC EQU $FFFFBE

M_PDRC EQU $FFFFBD

M_PCRD EQU $FFFFAF

M_PRRD EQU $FFFFAE

M_PDRD EQU $FFFFAD

M_PCRE EQU $FFFF9F

M_PRRE EQU $FFFF9E

M_PDRE EQU $FFFF9D

M_OGDB EQU $FFFFFC

; Host port GPIO data Register

; Host port GPIO direction Register

; Port C Control Register

; Port C Direction Register

; Port C GPIO Data Register

; Port D Control register

; Port D Direction Data Register

; Port D GPIO Data Register

; Port E Control register

; Port E Direction Register

; Port E Data Register

; OnCE GDB Register

;------------------------------------------------------------------------

;

EQUATES for Host Interface

;------------------------------------------------------------------------

Register Addresses

;

M_HCR EQU $FFFFC2

M_HSR EQU $FFFFC3

M_HPCR EQU $FFFFC4

M_HBAR EQU $FFFFC5

M_HRX EQU $FFFFC6

M_HTX EQU $FFFFC7

; Host Control Register

; Host Status Register

; Host Polarity Control Register

; Host Base Address Register

; Host Receive Register

; Host Transmit Register

;

HCR bits definition

M_HRIE EQU $0

M_HTIE EQU $1

M_HCIE EQU $2

M_HF2 EQU $3

M_HF3 EQU $4

; Host Receive interrupts Enable

; Host Transmit Interrupt Enable

; Host Command Interrupt Enable

; Host Flag 2

; Host Flag 3

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

A-5

Power Consumption Benchmark

;

HSR bits definition

M_HRDF EQU $0

M_HTDE EQU $1

M_HCP EQU $2

M_HF0 EQU $3

M_HF1 EQU $4

; Host Receive Data Full

; Host Receive Data Empty

; Host Command Pending

; Host Flag 0

; Host Flag 1

;

HPCR bits definition

M_HGEN EQU $0

M_HA8EN EQU $1

M_HA9EN EQU $2

M_HCSEN EQU $3

M_HREN EQU $4

M_HAEN EQU $5

M_HEN EQU $6

M_HOD EQU $8

M_HDSP EQU $9

M_HASP EQU $A

M_HMUX EQU $B

M_HD_HS EQU $C

M_HCSP EQU $D

M_HRP EQU $E

M_HAP EQU $F

; Host Port GPIO Enable

; Host Address 8 Enable

; Host Address 9 Enable

; Host Chip Select Enable

; Host Request Enable

; Host Acknowledge Enable

; Host Enable

; Host Request Open Drain mode

; Host Data Strobe Polarity

; Host Address Strobe Polarity

; Host Multiplexed bus select

; Host Double/Single Strobe select

; Host Chip Select Polarity

; Host Request Polarity

; Host Acknowledge Polarity

;------------------------------------------------------------------------

;

EQUATES for Serial Communications Interface (SCI)

;------------------------------------------------------------------------

;

Register Addresses

M_STXH EQU $FFFF97

M_STXM EQU $FFFF96

M_STXL EQU $FFFF95

M_SRXH EQU $FFFF9A

M_SRXM EQU $FFFF99

M_SRXL EQU $FFFF98

M_STXA EQU $FFFF94

M_SCR EQU $FFFF9C

M_SSR EQU $FFFF93

M_SCCR EQU $FFFF9B

; SCI Transmit Data Register (high)

; SCI Transmit Data Register (middle)

; SCI Transmit Data Register (low)

; SCI Receive Data Register (high)

; SCI Receive Data Register (middle)

; SCI Receive Data Register (low)

; SCI Transmit Address Register

; SCI Control Register

; SCI Status Register

; SCI Clock Control Register

;

SCI Control Register Bit Flags

M_WDS EQU $7

M_WDS0 EQU 0

M_WDS1 EQU 1

M_WDS2 EQU 2

M_SSFTD EQU 3

M_SBK EQU 4

M_WAKE EQU 5

M_RWU EQU 6

M_WOMS EQU 7

M_SCRE EQU 8

M_SCTE EQU 9

M_ILIE EQU 10

; Word Select Mask (WDS0-WDS3)

; Word Select 0

; Word Select 1

; Word Select 2

; SCI Shift Direction

; Send Break

; Wakeup Mode Select

; Receiver Wakeup Enable

; Wired-OR Mode Select

; SCI Receiver Enable

; SCI Transmitter Enable

; Idle Line Interrupt Enable

DSP56303 Technical Data, Rev. 11

A-6

Freescale Semiconductor

M_SCRIE EQU 11

M_SCTIE EQU 12

M_TMIE EQU 13

M_TIR EQU 14

M_SCKP EQU 15

M_REIE EQU 16

; SCI Receive Interrupt Enable

; SCI Transmit Interrupt Enable

; Timer Interrupt Enable

; Timer Interrupt Rate

; SCI Clock Polarity

; SCI Error Interrupt Enable (REIE)

;

SCI Status Register Bit Flags

M_TRNE EQU 0

M_TDRE EQU 1

M_RDRF EQU 2

M_IDLE EQU 3

M_OR EQU 4

M_PE EQU 5

M_FE EQU 6

M_R8 EQU 7

; Transmitter Empty

; Transmit Data Register Empty

; Receive Data Register Full

; Idle Line Flag

; Overrun Error Flag

; Parity Error

; Framing Error Flag

; Received Bit 8 (R8) Address

;

SCI Clock Control Register

M_CD EQU $FFF

M_COD EQU 12

M_SCP EQU 13

M_RCM EQU 14

M_TCM EQU 15

; Clock Divider Mask (CD0-CD11)

; Clock Out Divider

; Clock Prescaler

; Receive Clock Mode Source Bit

; Transmit Clock Source Bit

;------------------------------------------------------------------------

;

EQUATES for Synchronous Serial Interface (SSI)

;------------------------------------------------------------------------

;

Register Addresses Of SSI0

M_TX00 EQU $FFFFBC

M_TX01 EQU $FFFFBB

M_TX02 EQU $FFFFBA

M_TSR0 EQU $FFFFB9

M_RX0 EQU $FFFFB8

M_SSISR0 EQU $FFFFB7

M_CRB0 EQU $FFFFB6

M_CRA0 EQU $FFFFB5

M_TSMA0 EQU $FFFFB4

M_TSMB0 EQU $FFFFB3

M_RSMA0 EQU $FFFFB2

M_RSMB0 EQU $FFFFB1

; SSI0 Transmit Data Register 0

; SSIO Transmit Data Register 1

; SSIO Transmit Data Register 2

; SSI0 Time Slot Register

; SSI0 Receive Data Register

; SSI0 Status Register

; SSI0 Control Register B

; SSI0 Control Register A

; SSI0 Transmit Slot Mask Register A

; SSI0 Transmit Slot Mask Register B

; SSI0 Receive Slot Mask Register A

; SSI0 Receive Slot Mask Register B

;

Register Addresses Of SSI1

M_TX10 EQU $FFFFAC

M_TX11 EQU $FFFFAB

M_TX12 EQU $FFFFAA

M_TSR1 EQU $FFFFA9

M_RX1 EQU $FFFFA8

M_SSISR1 EQU $FFFFA7

M_CRB1 EQU $FFFFA6

M_CRA1 EQU $FFFFA5

M_TSMA1 EQU $FFFFA4

M_TSMB1 EQU $FFFFA3

M_RSMA1 EQU $FFFFA2

M_RSMB1 EQU $FFFFA1

; SSI1 Transmit Data Register 0

; SSI1 Transmit Data Register 1

; SSI1 Transmit Data Register 2

; SSI1 Time Slot Register

; SSI1 Receive Data Register

; SSI1 Status Register

; SSI1 Control Register B

; SSI1 Control Register A

; SSI1 Transmit Slot Mask Register A

; SSI1 Transmit Slot Mask Register B

; SSI1 Receive Slot Mask Register A

; SSI1 Receive Slot Mask Register B

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

A-7

Power Consumption Benchmark

;

SSI Control Register A Bit Flags

M_PM EQU $FF

M_PSR EQU 11

; Prescale Modulus Select Mask (PM0-PM7)

; Prescaler Range

M_DC EQU $1F000

M_ALC EQU 18

; Frame Rate Divider Control Mask (DC0-DC7)

; Alignment Control (ALC)

M_WL EQU $380000

M_SSC1 EQU 22

; Word Length Control Mask (WL0-WL7)

; Select SC1 as TR #0 drive enable (SSC1)

;

SSI Control Register B Bit Flags

M_OF EQU $3

M_OF0 EQU 0

; Serial Output Flag Mask

; Serial Output Flag 0

M_OF1 EQU 1

; Serial Output Flag 1

M_SCD EQU $1C

M_SCD0 EQU 2

M_SCD1 EQU 3

M_SCD2 EQU 4

M_SCKD EQU 5

M_SHFD EQU 6

M_FSL EQU $180

M_FSL0 EQU 7

M_FSL1 EQU 8

M_FSR EQU 9

M_FSP EQU 10

M_CKP EQU 11

M_SYN EQU 12

M_MOD EQU 13

M_SSTE EQU $1C000

M_SSTE2 EQU 14

M_SSTE1 EQU 15

M_SSTE0 EQU 16

M_SSRE EQU 17

M_SSTIE EQU 18

M_SSRIE EQU 19

M_STLIE EQU 20

M_SRLIE EQU 21

M_STEIE EQU 22

M_SREIE EQU 23

; Serial Control Direction Mask

; Serial Control 0 Direction

; Serial Control 1 Direction

; Serial Control 2 Direction

; Clock Source Direction

; Shift Direction

; Frame Sync Length Mask (FSL0-FSL1)

; Frame Sync Length 0

; Frame Sync Length 1

; Frame Sync Relative Timing

; Frame Sync Polarity

; Clock Polarity

; Sync/Async Control

; SSI Mode Select

; SSI Transmit enable Mask

; SSI Transmit #2 Enable

; SSI Transmit #1 Enable

; SSI Transmit #0 Enable

; SSI Receive Enable

; SSI Transmit Interrupt Enable

; SSI Receive Interrupt Enable

; SSI Transmit Last Slot Interrupt Enable

; SSI Receive Last Slot Interrupt Enable

; SSI Transmit Error Interrupt Enable

; SI Receive Error Interrupt Enable

;

SSI Status Register Bit Flags

M_IF EQU $3

M_IF0 EQU 0

M_IF1 EQU 1

M_TFS EQU 2

M_RFS EQU 3

M_TUE EQU 4

M_ROE EQU 5

M_TDE EQU 6

M_RDF EQU 7

; Serial Input Flag Mask

; Serial Input Flag 0

; Serial Input Flag 1

; Transmit Frame Sync Flag

; Receive Frame Sync Flag

; Transmitter Underrun Error FLag

; Receiver Overrun Error Flag

; Transmit Data Register Empty

; Receive Data Register Full

;

SSI Transmit Slot Mask Register A

M_SSTSA EQU $FFFF

; SSI Transmit Slot Bits Mask A (TS0-TS15)

;

SSI Transmit Slot Mask Register B

M_SSTSB EQU $FFFF

; SSI Transmit Slot Bits Mask B (TS16-TS31)

DSP56303 Technical Data, Rev. 11

A-8

Freescale Semiconductor

;

SSI Receive Slot Mask Register A

M_SSRSA EQU $FFFF

; SSI Receive Slot Bits Mask A (RS0-RS15)

; SSI Receive Slot Bits Mask B (RS16-RS31)

;

SSI Receive Slot Mask Register B

M_SSRSB EQU $FFFF

;------------------------------------------------------------------------

;

EQUATES for Exception Processing

;------------------------------------------------------------------------

;

Register Addresses

M_IPRC EQU $FFFFFF

M_IPRP EQU $FFFFFE

; Interrupt Priority Register Core

; Interrupt Priority Register Peripheral

;

Interrupt Priority Register Core (IPRC)

M_IAL EQU $7

; IRQA Mode Mask

M_IAL0 EQU 0

M_IAL1 EQU 1

M_IAL2 EQU 2

; IRQA Mode Interrupt Priority Level (low)

; IRQA Mode Interrupt Priority Level (high)

; IRQA Mode Trigger Mode

M_IBL EQU $38

M_IBL0 EQU 3

M_IBL1 EQU 4

; IRQB Mode Mask

; IRQB Mode Interrupt Priority Level (low)

; IRQB Mode Interrupt Priority Level (high)

; IRQB Mode Trigger Mode

M_IBL2 EQU 5

M_ICL EQU $1C0

M_ICL0 EQU 6

M_ICL1 EQU 7

; IRQC Mode Mask

; IRQC Mode Interrupt Priority Level (low)

; IRQC Mode Interrupt Priority Level (high)

; IRQC Mode Trigger Mode

M_ICL2 EQU 8

M_IDL EQU $E00

M_IDL0 EQU 9

; IRQD Mode Mask

; IRQD Mode Interrupt Priority Level (low)

; IRQD Mode Interrupt Priority Level (high)

; IRQD Mode Trigger Mode

M_IDL1 EQU 10

M_IDL2 EQU 11

M_D0L EQU $3000

M_D0L0 EQU 12

M_D0L1 EQU 13

M_D1L EQU $C000

M_D1L0 EQU 14

M_D1L1 EQU 15

M_D2L EQU $30000

M_D2L0 EQU 16

M_D2L1 EQU 17

M_D3L EQU $C0000

M_D3L0 EQU 18

M_D3L1 EQU 19

M_D4L EQU $300000

M_D4L0 EQU 20

M_D4L1 EQU 21

M_D5L EQU $C00000

M_D5L0 EQU 22

M_D5L1 EQU 23

; DMA0 Interrupt priority Level Mask

; DMA0 Interrupt Priority Level (low)

; DMA0 Interrupt Priority Level (high)

; DMA1 Interrupt Priority Level Mask

; DMA1 Interrupt Priority Level (low)

; DMA1 Interrupt Priority Level (high)

; DMA2 Interrupt priority Level Mask

; DMA2 Interrupt Priority Level (low)

; DMA2 Interrupt Priority Level (high)

; DMA3 Interrupt Priority Level Mask

; DMA3 Interrupt Priority Level (low)

; DMA3 Interrupt Priority Level (high)

; DMA4 Interrupt priority Level Mask

; DMA4 Interrupt Priority Level (low)

; DMA4 Interrupt Priority Level (high)

; DMA5 Interrupt priority Level Mask

; DMA5 Interrupt Priority Level (low)

; DMA5 Interrupt Priority Level (high)

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

A-9

Power Consumption Benchmark

;

Interrupt Priority Register Peripheral (IPRP)

M_HPL EQU $3

M_HPL0 EQU 0

M_HPL1 EQU 1

M_S0L EQU $C

M_S0L0 EQU 2

M_S0L1 EQU 3

M_S1L EQU $30

M_S1L0 EQU 4

M_S1L1 EQU 5

M_SCL EQU $C0

M_SCL0 EQU 6

M_SCL1 EQU 7

M_T0L EQU $300

M_T0L0 EQU 8

M_T0L1 EQU 9

; Host Interrupt Priority Level Mask

; Host Interrupt Priority Level (low)

; Host Interrupt Priority Level (high)

; SSI0 Interrupt Priority Level Mask

; SSI0 Interrupt Priority Level (low)

; SSI0 Interrupt Priority Level (high)

; SSI1 Interrupt Priority Level Mask

; SSI1 Interrupt Priority Level (low)

; SSI1 Interrupt Priority Level (high)

; SCI Interrupt Priority Level Mask

; SCI Interrupt Priority Level (low)

; SCI Interrupt Priority Level (high)

; TIMER Interrupt Priority Level Mask

; TIMER Interrupt Priority Level (low)

; TIMER Interrupt Priority Level (high)

;------------------------------------------------------------------------

;

EQUATES for TIMER

;------------------------------------------------------------------------

Register Addresses Of TIMER0

;

M_TCSR0 EQU $FFFF8F

M_TLR0 EQU $FFFF8E

M_TCPR0 EQU $FFFF8D

M_TCR0 EQU $FFFF8C

; Timer 0 Control/Status Register

; TIMER0 Load Reg

; TIMER0 Compare Register

; TIMER0 Count Register

;

Register Addresses Of TIMER1

M_TCSR1 EQU $FFFF8B

M_TLR1 EQU $FFFF8A

M_TCPR1 EQU $FFFF89

M_TCR1 EQU $FFFF88

; TIMER1 Control/Status Register

; TIMER1 Load Reg

; TIMER1 Compare Register

; TIMER1 Count Register

;

Register Addresses Of TIMER2

M_TCSR2 EQU $FFFF87

M_TLR2 EQU $FFFF86

M_TCPR2 EQU $FFFF85

M_TCR2 EQU $FFFF84

M_TPLR EQU $FFFF83

M_TPCR EQU $FFFF82

; TIMER2 Control/Status Register

; TIMER2 Load Reg

; TIMER2 Compare Register

; TIMER2 Count Register

; TIMER Prescaler Load Register

; TIMER Prescalar Count Register

;

Timer Control/Status Register Bit Flags

M_TE EQU 0

; Timer Enable

M_TOIE EQU 1

M_TCIE EQU 2

M_TC EQU $F0

M_INV EQU 8

M_TRM EQU 9

M_DIR EQU 11

; Timer Overflow Interrupt Enable

; Timer Compare Interrupt Enable

; Timer Control Mask (TC0-TC3)

; Inverter Bit

; Timer Restart Mode

; Direction Bit

DSP56303 Technical Data, Rev. 11

A-10

Freescale Semiconductor

M_DI EQU 12

M_DO EQU 13

M_PCE EQU 15

M_TOF EQU 20

M_TCF EQU 21

; Data Input

; Data Output

; Prescaled Clock Enable

; Timer Overflow Flag

; Timer Compare Flag

;

Timer Prescaler Register Bit Flags

M_PS EQU $600000

M_PS0 EQU 21

; Prescaler Source Mask

M_PS1 EQU 22

;

Timer Control Bits

M_TC0 EQU 4

M_TC1 EQU 5

M_TC2 EQU 6

M_TC3 EQU 7

; Timer Control 0

; Timer Control 1

; Timer Control 2

; Timer Control 3

;------------------------------------------------------------------------

;

EQUATES for Direct Memory Access (DMA)

;------------------------------------------------------------------------

;

Register Addresses Of DMA

M_DSTR EQU FFFFF4

M_DOR0 EQU $FFFFF3

M_DOR1 EQU $FFFFF2

M_DOR2 EQU $FFFFF1

M_DOR3 EQU $FFFFF0

; DMA Status Register

; DMA Offset Register 0

; DMA Offset Register 1

; DMA Offset Register 2

; DMA Offset Register 3

;

Register Addresses Of DMA0

M_DSR0 EQU $FFFFEF

M_DDR0 EQU $FFFFEE

M_DCO0 EQU $FFFFED

M_DCR0 EQU $FFFFEC

; DMA0 Source Address Register

; DMA0 Destination Address Register

; DMA0 Counter

; DMA0 Control Register

;

Register Addresses Of DMA1

M_DSR1 EQU $FFFFEB

M_DDR1 EQU $FFFFEA

M_DCO1 EQU $FFFFE9

M_DCR1 EQU $FFFFE8

; DMA1 Source Address Register

; DMA1 Destination Address Register

; DMA1 Counter

; DMA1 Control Register

;

Register Addresses Of DMA2

M_DSR2 EQU $FFFFE7

M_DDR2 EQU $FFFFE6

M_DCO2 EQU $FFFFE5

M_DCR2 EQU $FFFFE4

; DMA2 Source Address Register

; DMA2 Destination Address Register

; DMA2 Counter

; DMA2 Control Register

;

Register Addresses Of DMA4

M_DSR3 EQU $FFFFE3

M_DDR3 EQU $FFFFE2

M_DCO3 EQU $FFFFE1

M_DCR3 EQU $FFFFE0

; DMA3 Source Address Register

; DMA3 Destination Address Register

; DMA3 Counter

; DMA3 Control Register

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

A-11

Power Consumption Benchmark

;

Register Addresses Of DMA4

M_DSR4 EQU $FFFFDF

M_DDR4 EQU $FFFFDE

M_DCO4 EQU $FFFFDD

M_DCR4 EQU $FFFFDC

; DMA4 Source Address Register

; DMA4 Destination Address Register

; DMA4 Counter

; DMA4 Control Register

;

Register Addresses Of DMA5

M_DSR5 EQU $FFFFDB

M_DDR5 EQU $FFFFDA

M_DCO5 EQU $FFFFD9

M_DCR5 EQU $FFFFD8

; DMA5 Source Address Register

; DMA5 Destination Address Register

; DMA5 Counter

; DMA5 Control Register

;

DMA Control Register

M_DSS EQU $3

M_DSS0 EQU 0

M_DSS1 EQU 1

M_DDS EQU $C

M_DDS0 EQU 2

M_DDS1 EQU 3

M_DAM EQU $3f0

M_DAM0 EQU 4

M_DAM1 EQU 5

M_DAM2 EQU 6

M_DAM3 EQU 7

M_DAM4 EQU 8

M_DAM5 EQU 9

M_D3D EQU 10

M_DRS EQU $F800

M_DCON EQU 16

M_DPR EQU $60000

M_DPR0 EQU 17

M_DPR1 EQU 18

M_DTM EQU $380000

M_DTM0 EQU 19

M_DTM1 EQU 20

M_DTM2 EQU 21

M_DIE EQU 22

M_DE EQU 23

; DMA Source Space Mask (DSS0-Dss1)

; DMA Source Memory space 0

; DMA Source Memory space 1

; DMA Destination Space Mask (DDS-DDS1)

; DMA Destination Memory Space 0

; DMA Destination Memory Space 1

; DMA Address Mode Mask (DAM5-DAM0)

; DMA Address Mode 0

; DMA Address Mode 1

; DMA Address Mode 2

; DMA Address Mode 3

; DMA Address Mode 4

; DMA Address Mode 5

; DMA Three Dimensional Mode

; DMA Request Source Mask (DRS0-DRS4)

; DMA Continuous Mode

; DMA Channel Priority

; DMA Channel Priority Level (low)

; DMA Channel Priority Level (high)

; DMA Transfer Mode Mask (DTM2-DTM0)

; DMA Transfer Mode 0

; DMA Transfer Mode 1

; DMA Transfer Mode 2

; DMA Interrupt Enable bit

; DMA Channel Enable bit

;

DMA Status Register

M_DTD EQU $3F

M_DTD0 EQU 0

M_DTD1 EQU 1

M_DTD2 EQU 2

M_DTD3 EQU 3

M_DTD4 EQU 4

M_DTD5 EQU 5

; Channel Transfer Done Status MASK (DTD0-DTD5)

; DMA Channel Transfer Done Status 0

; DMA Channel Transfer Done Status 1

; DMA Channel Transfer Done Status 2

; DMA Channel Transfer Done Status 3

; DMA Channel Transfer Done Status 4

; DMA Channel Transfer Done Status 5

; DMA Active State

M_DACT EQU

M_DCH EQU $E00

M_DCH0 EQU

8

; DMA Active Channel Mask (DCH0-DCH2)

; DMA Active Channel 0

9

M_DCH1 EQU 10

M_DCH2 EQU 11

; DMA Active Channel 1

; DMA Active Channel 2

;------------------------------------------------------------------------

DSP56303 Technical Data, Rev. 11

A-12

Freescale Semiconductor

;

EQUATES for Phase Locked Loop (PLL)

;------------------------------------------------------------------------

Register Addresses Of PLL

M_PCTL EQU $FFFFFD

;

; PLL Control Register

;

PLL Control Register

M_MF EQU $FFF

M_DF EQU $7000

M_XTLR EQU 15

M_XTLD EQU 16

M_PSTP EQU 17

M_PEN EQU 18

; Multiplication Factor Bits Mask (MF0-MF11)

; Division Factor Bits Mask (DF0-DF2)

; XTAL Range select bit

; XTAL Disable Bit

; STOP Processing State Bit

; PLL Enable Bit

M_PCOD EQU 19

M_PD EQU $F00000

; PLL Clock Output Disable Bit

; PreDivider Factor Bits Mask (PD0-PD3)

;------------------------------------------------------------------------

;

EQUATES for BIU

;------------------------------------------------------------------------

;

Register Addresses Of BIU

M_BCR EQU $FFFFFB

M_DCR EQU $FFFFFA

M_AAR0 EQU $FFFFF9

M_AAR1 EQU $FFFFF8

M_AAR2 EQU $FFFFF7

M_AAR3 EQU $FFFFF6

M_IDR EQU $FFFFF5

; Bus Control Register

; DRAM Control Register

; Address Attribute Register 0

; Address Attribute Register 1

; Address Attribute Register 2

; Address Attribute Register 3

; ID Register

;

Bus Control Register

M_BA0W EQU $1F

M_BA1W EQU $3E0

M_BA2W EQU $1C00

M_BA3W EQU $E000

M_BDFW EQU $1F0000

M_BBS EQU 21

; Area 0 Wait Control Mask (BA0W0-BA0W4)

; Area 1 Wait Control Mask (BA1W0-BA14)

; Area 2 Wait Control Mask (BA2W0-BA2W2)

; Area 3 Wait Control Mask (BA3W0-BA3W3)

; Default Area Wait Control Mask (BDFW0-BDFW4)

; Bus State

M_BLH EQU 22

; Bus Lock Hold

M_BRH EQU 23

; Bus Request Hold

;

DRAM Control Register

M_BCW EQU $3

M_BRW EQU $C

M_BPS EQU $300

M_BPLE EQU 11

M_BME EQU 12

M_BRE EQU 13

M_BSTR EQU 14

M_BRF EQU $7F8000

; In Page Wait States Bits Mask (BCW0-BCW1)

; Out Of Page Wait States Bits Mask (BRW0-BRW1)

; DRAM Page Size Bits Mask (BPS0-BPS1)

; Page Logic Enable

; Mastership Enable

; Refresh Enable

; Software Triggered Refresh

; Refresh Rate Bits Mask (BRF0-BRF7)

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

A-13

Power Consumption Benchmark

M_BRP EQU 23

; Refresh prescaler

;

Address Attribute Registers

M_BAT EQU $3

M_BAAP EQU 2

M_BPEN EQU 3

M_BXEN EQU 4

M_BYEN EQU 5

M_BAM EQU 6

; Ext. Access Type and Pin Def. Bits Mask (BAT0-BAT1)

; Address Attribute Pin Polarity

; Program Space Enable

; X Data Space Enable

; Y Data Space Enable

; Address Muxing

M_BPAC EQU 7

M_BNC EQU $F00

M_BAC EQU $FFF000

; Packing Enable

; Number of Address Bits to Compare Mask (BNC0-BNC3)

; Address to Compare Bits Mask (BAC0-BAC11)

;

control and status bits in SR

M_CP EQU $c00000

M_CA EQU 0

M_V EQU 1

; mask for CORE-DMA priority bits in SR

; Carry

; Overflow

M_Z EQU 2

; Zero

M_N EQU 3

; Negative

M_U EQU 4

; Unnormalized

M_E EQU 5

; Extension

M_L EQU 6

; Limit

M_S EQU 7

; Scaling Bit

M_I0 EQU 8

M_I1 EQU 9

M_S0 EQU 10

M_S1 EQU 11

M_SC EQU 13

M_DM EQU 14

M_LF EQU 15

M_FV EQU 16

M_SA EQU 17

M_CE EQU 19

M_SM EQU 20

M_RM EQU 21

M_CP0 EQU 22

M_CP1 EQU 23

; Interupt Mask Bit 0

; Interupt Mask Bit 1

; Scaling Mode Bit 0

; Scaling Mode Bit 1

; Sixteen_Bit Compatibility

; Double Precision Multiply

; DO-Loop Flag

; DO-Forever Flag

; Sixteen-Bit Arithmetic

; Instruction Cache Enable

; Arithmetic Saturation

; Rounding Mode

; bit 0 of priority bits in SR

; bit 1 of priority bits in SR

;

control and status bits in OMR

M_CDP EQU $300

; mask for CORE-DMA priority bits in OMR

; Operating Mode A

; Operating Mode B

; Operating Mode C

; Operating Mode D

M_MA

M_MB

M_MC

M_MD

equ0

equ1

equ2

equ3

M_EBD EQU 4

M_SD EQU 6

M_MS EQU 7

M_CDP0 EQU 8

M_CDP1 EQU 9

; External Bus Disable bit in OMR

; Stop Delay

; Memory Switch bit in OMR

; bit 0 of priority bits in OMR

; bit 1 of priority bits in OMR

; Burst Enable

M_BEN

EQU 10

M_TAS EQU 11

M_BRT EQU 12

M_ATE EQU 15

M_XYS EQU 16

M_EUN EQU 17

M_EOV EQU 18

M_WRP EQU 19

; TA Synchronize Select

; Bus Release Timing

; Address Tracing Enable bit in OMR.

; Stack Extension space select bit in OMR.

; Extensed stack UNderflow flag in OMR.

; Extended stack OVerflow flag in OMR.

; Extended WRaP flag in OMR.

DSP56303 Technical Data, Rev. 11

A-14

Freescale Semiconductor

M_SEN EQU 20

; Stack Extension Enable bit in OMR.

;*************************************************************************

;

EQUATES for DSP56303 interrupts

Last update: June 11 1995

;*************************************************************************

page

opt

132,55,0,0,0

mex

intequ ident

if

1,0

@DEF(I_VEC)

;leave user definition as is.

else

I_VEC EQU $0

endif

;------------------------------------------------------------------------

; Non-Maskable interrupts

;------------------------------------------------------------------------

I_RESET EQU I_VEC+$00

I_STACK EQU I_VEC+$02

I_ILL EQU I_VEC+$04

I_DBG EQU I_VEC+$06

I_TRAP EQU I_VEC+$08

I_NMI EQU I_VEC+$0A

; Hardware RESET

; Stack Error

; Illegal Instruction

; Debug Request

; Trap

; Non Maskable Interrupt

;------------------------------------------------------------------------

; Interrupt Request Pins

;------------------------------------------------------------------------

I_IRQA EQU I_VEC+$10

I_IRQB EQU I_VEC+$12

I_IRQC EQU I_VEC+$14

I_IRQD EQU I_VEC+$16

; IRQA

; IRQB

; IRQC

; IRQD

;------------------------------------------------------------------------

; DMA Interrupts

;------------------------------------------------------------------------

I_DMA0 EQU I_VEC+$18

I_DMA1 EQU I_VEC+$1A

I_DMA2 EQU I_VEC+$1C

I_DMA3 EQU I_VEC+$1E

I_DMA4 EQU I_VEC+$20

I_DMA5 EQU I_VEC+$22

; DMA Channel 0

; DMA Channel 1

; DMA Channel 2

; DMA Channel 3

; DMA Channel 4

; DMA Channel 5

;------------------------------------------------------------------------

; Timer Interrupts

;------------------------------------------------------------------------

I_TIM0C EQU I_VEC+$24

I_TIM0OF EQU I_VEC+$26

I_TIM1C EQU I_VEC+$28

; TIMER 0 compare

; TIMER 0 overflow

; TIMER 1 compare

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

A-15

Power Consumption Benchmark

I_TIM1OF EQU I_VEC+$2A

I_TIM2C EQU I_VEC+$2C

I_TIM2OF EQU I_VEC+$2E

; TIMER 1 overflow

; TIMER 2 compare

; TIMER 2 overflow

;------------------------------------------------------------------------

; ESSI Interrupts

;------------------------------------------------------------------------

I_SI0RD EQU I_VEC+$30

I_SI0RDE EQU I_VEC+$32

I_SI0RLS EQU I_VEC+$34

I_SI0TD EQU I_VEC+$36

I_SI0TDE EQU I_VEC+$38

I_SI0TLS EQU I_VEC+$3A

I_SI1RD EQU I_VEC+$40

I_SI1RDE EQU I_VEC+$42

I_SI1RLS EQU I_VEC+$44

I_SI1TD EQU I_VEC+$46

I_SI1TDE EQU I_VEC+$48

I_SI1TLS EQU I_VEC+$4A

; ESSI0 Receive Data

; ESSI0 Receive Data w/ exception Status

; ESSI0 Receive last slot

; ESSI0 Transmit data

; ESSI0 Transmit Data w/ exception Status

; ESSI0 Transmit last slot

; ESSI1 Receive Data

; ESSI1 Receive Data w/ exception Status

; ESSI1 Receive last slot

; ESSI1 Transmit data

; ESSI1 Transmit Data w/ exception Status

; ESSI1 Transmit last slot

;------------------------------------------------------------------------

; SCI Interrupts

;------------------------------------------------------------------------

I_SCIRD EQU I_VEC+$50

I_SCIRDE EQU I_VEC+$52

I_SCITD EQU I_VEC+$54

I_SCIIL EQU I_VEC+$56

I_SCITM EQU I_VEC+$58

; SCI Receive Data

; SCI Receive Data With Exception Status

; SCI Transmit Data

; SCI Idle Line

; SCI Timer

;------------------------------------------------------------------------

; HOST Interrupts

;------------------------------------------------------------------------

I_HRDF EQU I_VEC+$60

I_HTDE EQU I_VEC+$62

I_HC EQU I_VEC+$64

; Host Receive Data Full

; Host Transmit Data Empty

; Default Host Command

;-----------------------------------------------------------------------

; INTERRUPT ENDING ADDRESS

;------------------------------------------------------------------------

I_INTEND EQU I_VEC+$FF

; last address of interrupt vector space

DSP56303 Technical Data, Rev. 11

A-16

Freescale Semiconductor

Ordering Information

Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.

Core

Frequency

(MHz)

Supply

Voltage

Count

Part

Package Type

Solder Spheres

Order Number

DSP56303

3.3 V

Thin Quad Flat Pack (TQFP)

144

196

100

Lead-free

Lead-bearing

Lead-free

DSP56303AG100

DSP56303PV100

DSP56303VL100

DSP56303VF100

Molded Array Process-Ball Grid

Array (MAP-BGA)

100

Lead-bearing

Information in this document is provided solely to enable system and software implementers to

use Freescale Semiconductor products. There are no express or implied copyright licenses

granted hereunder to design or fabricate any integrated circuits or integrated circuits based on

the information in this document.

How to Reach Us:

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Document Order No.: DSP56303

Rev. 11

2/2005


型号：	DSP56303VL100R2
厂家：	NXP
描述：	24-BIT, 100 MHz, OTHER DSP, PBGA196, MOLDED ARRAY PROCESS, BGA-196 时钟外围集成电路
文件：	总108页 (文件大小：1898K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DSP56303VL100R2 [NXP]

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