GTL2010PW,112 [NXP]
GTL2010 - 10-bit bidirectional low voltage translator TSSOP2 24-Pin;
| 型号： | GTL2010PW,112 |
| 厂家： | 
NXP |
| 描述： | GTL2010 - 10-bit bidirectional low voltage translator TSSOP2 24-Pin 光电二极管 接口集成电路 |
| 文件： | 总20页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GTL2010
10-bit bidirectional low voltage translator
Rev. 06 — 3 March 2008
Product data sheet
1. General description
The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide
high-speed voltage translation with low ON-state resistance and minimal propagation
delay. The GTL2010 provides 10 NMOS pass transistors (Sn and Dn) with a common gate
(GREF) and a reference transistor (SREF and DREF). The device allows bidirectional
voltage translations between 1.0 V and 5.0 V without use of a direction pin.
When the Sn or Dn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn
port, when the Dn port is HIGH the voltage on the Sn port is limited to the voltage set by
the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by
the pull-up resistors. This functionality allows a seamless translation between higher and
lower voltages selected by the user, without the need for directional control.
All transistors have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are identical, SREF and DREF can be
located on any of the other ten matched Sn/Dn transistors, allowing for easier board
layout. The translator's transistors provide excellent ESD protection to lower voltage
devices and at the same time protect less ESD-resistant devices.
2. Features
I 10-bit bidirectional low voltage translator
I Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V
buses, which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
I Provides bidirectional voltage translation with no direction pin
I Low 6.5 Ω ON-state resistance (Ron) between input and output pins (Sn/Dn)
I Supports hot insertion
I No power supply required: will not latch up
I 5 V tolerant inputs
I Low standby current
I Flow-through pinout for ease of printed-circuit board trace routing
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Packages offered: TSSOP24, HVQFN24
GTL2010
NXP Semiconductors
10-bit bidirectional low voltage translator
3. Applications
I Any application that requires bidirectional or unidirectional voltage level translation
from any voltage from 1.0 V to 5.0 V to any voltage from 1.0 V to 5.0 V
I The open-drain construction with no direction pin is ideal for bidirectional low voltage
(for example, 1.0 V, 1.2 V, 1.5 V or 1.8 V) processor I2C-bus port translation to the
normal 3.3 V and/or 5.0 V I2C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL
signal levels
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
GTL2010PW
GTL2010BS
TSSOP24
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
HVQFN24
plastic thermal enhanced very thin quad flat package; SOT616-1
no leads; 24 terminals; body 4 × 4 × 0.85 mm
4.1 Ordering options
Table 2.
Ordering options
Type number
GTL2010PW
GTL2010BS
Topside mark
GTL2010
2010
Temperature range
−40 °C to +85 °C
−40 °C to +85 °C
5. Functional diagram
DREF
GREF
D1
D10
SREF
S1
S10
002aac059
Fig 1. Functional diagram
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
2 of 20
GTL2010
NXP Semiconductors
10-bit bidirectional low voltage translator
6. Pinning information
6.1 Pinning
1
2
24
23
22
21
20
19
18
17
16
15
14
13
GND
SREF
S1
GREF
DREF
D1
terminal 1
index area
3
4
S2
D2
1
2
3
4
5
6
18
17
16
15
14
13
S2
S3
S4
S5
S6
S7
D2
D3
D4
D5
D6
D7
5
S3
D3
6
S4
D4
GTL2010PW
GTL2010BS
7
S5
D5
8
S6
D6
9
S7
D7
10
11
12
S8
D8
S9
D9
002aac058
S10
D10
002aac057
Transparent top view
Fig 2. Pin configuration for TSSOP24
Fig 3. Pin configuration for HVQFN24
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
TSSOP24
HVQFN24
22[1]
GND
1
2
ground (0 V)
SREF
23
source of reference transistor
S1 to S10
3, 4, 5, 6, 7, 8, 9, 24, 1, 2, 3, 4, 5, 6, Port S1 to Port S10
10, 11, 12 7, 8, 9
D1 to D10
22, 21, 20, 19, 18, 19, 18, 17, 16, 15, Port D1 to Port D10
17, 16, 15, 14, 13 14, 13, 12, 11, 10
DREF
GREF
23
24
20
21
drain of reference transistor
gate of reference transistor
[1] HVQFN24 package die supply ground is connected to both GND pin and exposed center pad. GND pin
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper heat conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
3 of 20
GTL2010
NXP Semiconductors
10-bit bidirectional low voltage translator
7. Functional description
Refer also to Figure 1 “Functional diagram”.
7.1 Function selection
Table 4.
Function selection, HIGH-to-LOW translation
Assumes Dn is at the higher voltage level.
H = HIGH voltage level; L = LOW voltage level; X = Don’t care
GREF[1]
DREF
SREF[2]
Input Dn
Output Sn
Transistor
H
H
H
L
H
H
H
L
0 V
X
H
L
X
off
on
on
off
[3]
VT
VT
L[4]
VT
0 V − VT
X
X
[1] GREF should be at least 1.5 V higher than SREF for best translator operation.
[2] VT is equal to the SREF voltage.
[3] Sn is not pulled up or pulled down.
[4] Sn follows the Dn input LOW.
Table 5.
Function selection, LOW-to-HIGH translation
Assumes Dn is at the higher voltage level.
H = HIGH voltage level; L = LOW voltage level; X = Don’t care
GREF[1]
DREF
SREF[2]
Input Sn
Output Dn
Transistor
H
H
H
L
H
H
H
L
0 V
X
X
off
VT
VT
L
H[3]
L[4]
X
nearly off
VT
on
off
0 V − VT
X
[1] GREF should be at least 1.5 V higher than SREF for best translator operation.
[2] VT is equal to the SREF voltage.
[3] Dn is pulled up to VCC through an external resistor.
[4] Dn follows the Sn input LOW.
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
4 of 20
GTL2010
NXP Semiconductors
10-bit bidirectional low voltage translator
8. Application design-in information
8.1 Bidirectional translation
For the bidirectional clamping configuration, higher voltage to lower voltage or lower
voltage to higher voltage, the GREF input must be connected to DREF and both pins
pulled to HIGH side VCC through a pull-up resistor (typically 200 kΩ). A filter capacitor on
DREF is recommended. The processor output can be totem pole or open-drain (pull-up
resistors may be required) and the chip set output can be totem pole or open-drain
(pull-up resistors are required to pull the Dn outputs to VCC). However, if either output is
totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs
must be controlled by some direction control mechanism to prevent HIGH-to-LOW
contentions in either direction. If both outputs are open-drain, no direction control is
needed. The opposite side of the reference transistor (SREF) is connected to the
processor core power supply voltage. When DREF is connected through a 200 kΩ resistor
to a 3.3 V to 5.5 V VCC supply and SREF is set between 1.0 V to (VCC − 1.5 V), the output
of each Sn has a maximum output voltage equal to SREF and the output of each Dn has
a maximum output voltage equal to VCC
.
1.8 V
1.5 V
1.2 V
1.0 V
5 V
200 kΩ
totem pole or
open-drain I/O
GND
SREF
S1
GREF
DREF
D1
V
V
CORE
CC
CPU I/O
CHIPSET I/O
S2
D2
increase bit size
by using 10-bit GTL2010
or 22-bit GTL2000
3.3 V
V
CC
S3
S4
S5
Sn
D3
D4
D5
Dn
CHIPSET I/O
002aac060
Typical bidirectional voltage translation.
Fig 4. Bidirectional translation to multiple higher voltage levels such as an I2C-bus
application
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
5 of 20
GTL2010
NXP Semiconductors
10-bit bidirectional low voltage translator
8.2 Unidirectional down translation
For unidirectional clamping, higher voltage to lower voltage, the GREF input must be
connected to DREF and both pins pulled to the higher side VCC through a pull-up resistor
(typically 200 kΩ). A filter capacitor on DREF is recommended. Pull-up resistors are
required if the chip set I/Os are open-drain. The opposite side of the reference transistor
(SREF) is connected to the processor core supply voltage. When DREF is connected
through a 200 kΩ resistor to a 3.3 V to 5.5 V VCC supply and SREF is set between 1.0 V
to (VCC − 1.5 V), the output of each Sn has a maximum output voltage equal to SREF.
1.8 V
1.5 V
1.2 V
1.0 V
5 V
200 kΩ
easy migration to lower voltage
as processor geometry shrinks
GND
SREF
S1
GREF
DREF
D1
V
V
CORE
CC
CPU I/O
CHIPSET I/O
S2
D2
totem pole I/O
002aac061
Typical unidirectional HIGH-to-LOW voltage translation.
Fig 5. Unidirectional down translation to protect low voltage processor pins
8.3 Unidirectional up translation
For unidirectional up translation, lower voltage to higher voltage, the reference transistor is
connected the same as for a down translation. A pull-up resistor is required on the higher
voltage side (Dn or Sn) to get the full HIGH level, since the GTL-TVC device will only pass
the reference source (SREF) voltage as a HIGH when doing an up translation. The driver
on the lower voltage side only needs pull-up resistors if it is open-drain.
1.8 V
1.5 V
1.2 V
1.0 V
5 V
200 kΩ
easy migration to lower voltage
as processor geometry shrinks
GND
SREF
S1
GREF
DREF
D1
V
V
CORE
CC
CPU I/O
CHIPSET I/O
S2
D2
totem pole I/O
or open-drain
002aac062
Typical unidirectional LOW-to-HIGH voltage translation.
Fig 6. Unidirectional down translation to protect low voltage processor pins
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
6 of 20
GTL2010
NXP Semiconductors
10-bit bidirectional low voltage translator
8.4 Sizing pull-up resistor
The pull-up resistor value needs to limit the current through the pass transistor when it is
in the ‘on’ state to about 15 mA. This will guarantee a pass voltage of 260 mV to 350 mV.
If the current through the pass transistor is higher than 15 mA, the pass voltage will also
be higher in the ‘on’ state. To set the current through each pass transistor at 15 mA, the
pull-up resistor value is calculated as shown in Equation 1:
pull-up voltage (V) – 0.35 V
resistor value (Ω) =
(1)
-------------------------------------------------------------------------------
0.015 A
Table 6 summarizes resistor values for various reference voltages and currents at 15 mA
and also at 10 mA and 3 mA. The resistor value shown in the + 10 % column or a larger
value should be used to ensure that the pass voltage of the transistor would be 350 mV or
less. The external driver must be able to sink the total current from the resistors on both
sides of the GTL-TVC device at 0.175 V, although the 15 mA only applies to current
flowing through the GTL-TVC device. See application note AN10145, “Bi-directional low
voltage translators” for more information.
Table 6.
Voltage
Pull-up resistor values
Pull-up resistor value (Ω)[1]
15 mA[2]
10 mA[2]
3 mA[2]
Nominal
Nominal
310
197
143
97
+ 10 %[3]
Nominal
465
+ 10 %[3]
+ 10 %[3]
1705
1082
788
5.0 V
3.3 V
2.5 V
1.8 V
1.5 V
1.2 V
341
217
158
106
85
512
1550
983
717
483
383
283
295
325
215
237
145
160
532
77
115
127
422
57
63
85
94
312
[1] Calculated for VOL = 0.35 V.
[2] Assumes output driver VOL = 0.175 V at stated current.
[3] + 10 % to compensate for VCC range and resistor tolerance.
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
7 of 20
GTL2010
NXP Semiconductors
10-bit bidirectional low voltage translator
9. Limiting values
Table 7.
Limiting values[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions
Min
−0.5
−0.5
−0.5
−0.5
−0.5
-
Max
+7.0
+7.0
+7.0
+7.0
+7.0
−50
Unit
V
[2]
[2]
[2]
[2]
[2]
VSREF
VDREF
VGREF
VSn
voltage on pin SREF
voltage on pin DREF
voltage on pin GREF
voltage on port Sn
voltage on port Dn
V
V
V
VDn
V
IREFK
ISK
diode current on reference pins VI < 0 V
mA
mA
mA
mA
diode current Port Sn
diode current Port Dn
clamp current per channel
VI < 0 V
VI < 0 V
-
−50
IDK
-
−50
IMAX
channel in
ON-state
-
±128
Tstg
storage temperature
−65
+150
°C
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 150 °C.
[2] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
10. Recommended operating conditions
Table 8.
Recommended operating conditions
Symbol Parameter
Conditions
Min
0
Typ
Max
5.5
5.5
5.5
5.5
64
Unit
V
VI/O
voltage on an input/output pin Sn, Dn
-
-
-
-
-
-
[1]
VSREF
VDREF
VGREF
IPASS
Tamb
voltage on pin SREF
voltage on pin DREF
voltage on pin GREF
pass transistor current
ambient temperature
0
V
0
V
0
V
-
mA
°C
operating in free air
−40
+85
[1]
VSREF ≤ VDREF − 1.5 V for best results in level shifting applications.
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
8 of 20
GTL2010
NXP Semiconductors
10-bit bidirectional low voltage translator
11. Static characteristics
Table 9.
Static characteristics
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
LOW-level output voltage VCC = 3.0 V; VSREF = 1.365 V;
Sn or VDn = 0.175 V; Iclamp = 15.2 mA
II = −18 mA; VGREF = 0 V
Conditions
Min
Typ[1]
Max
Unit
VOL
-
260
350
mV
V
VIK
input clamping voltage
-
-
-
-
-
−1.2
V
ILI(G)
Cig
gate input leakage current VI = 5 V; VGREF = 0 V
input capacitance at gate VI = 3 V or 0 V
-
5
-
µA
pF
pF
56
7.4
Cio(off)
off-state input/output
capacitance
VO = 3 V or 0 V; VGREF = 0 V
-
Cio(on)
Ron
on-state input/output
capacitance
VO = 3 V or 0 V; VGREF = 3 V
-
18.6
-
pF
[2]
ON-state resistance
VI = 0 V; IO = 64 mA
VGREF = 4.5 V
-
-
-
-
-
-
-
-
3.5
4.4
5.5
67
9
5
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VGREF = 3 V
7
VGREF = 2.3 V
9
VGREF = 1.5 V
115
15
10
80
70
[2]
[2]
[2]
[2]
VI = 0 V; IO = 30 mA; VGREF = 1.5 V
VI = 2.4 V; IO = 15 mA; VGREF = 4.5 V
VI = 2.4 V; IO = 15 mA; VGREF = 3 V
VI = 1.7 V; IO = 15 mA; VGREF = 2.3 V
7
58
50
[1] All typical values are measured at Tamb = 25 °C.
[2] Measured by the voltage drop between the Sn and the Dn terminals at the indicated current through the switch. ON-state resistance is
determined by the lowest voltage of the two (Sn or Dn) terminals.
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
9 of 20
GTL2010
NXP Semiconductors
10-bit bidirectional low voltage translator
12. Dynamic characteristics
12.1 Dynamic characteristics for translator-type application
Table 10. Dynamic characteristics
Tamb = −40 °C to +85 °C; Vref = 1.365 V to 1.635 V; VCC1 = 3.0 V to 3.6 V; VCC2 = 2.36 V to 2.64 V; GND = 0 V; tr = tf ≤ 3.0 ns;
unless otherwise specified. Refer to Figure 9.
Symbol
tPLH
Parameter
Conditions
Min
0.5
0.5
Typ[1]
1.5
Max
5.5
Unit
ns
[2][3]
[2][3]
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
Sn to Dn; Dn to Sn
Sn to Dn; Dn to Sn
tPHL
1.5
5.5
ns
[1] All typical values are measured at VCC1 = 3.3 V, VCC2 = 2.5 V, Vref = 1.5 V and Tamb = 25 °C.
[2] Propagation delay guaranteed by characterization.
[3] Cio(on)(max) of 30 pF and Cio(off)(max) of 15 pF is guaranteed by design.
V
I
input
V
V
M
M
GND
t
t
PLH0
PHL0
V
V
V
V
CC2
test jig output
HIGH-to-LOW
LOW-to-HIGH
V
M
V
M
OL
t
t
PLH
PHL
t
t
PLH1
PHL1
CC2
DUT output
HIGH-to-LOW
LOW-to-HIGH
V
V
M
M
OL
002aac063
VM = 1.5 V; VI = GND to 3.0 V
Fig 7. The input (Sn) to output (Dn) propagation delays
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
10 of 20
GTL2010
NXP Semiconductors
10-bit bidirectional low voltage translator
12.2 Dynamic characteristics for CBT-type application
Table 11. Dynamic characteristics
Tamb = −40 °C to +85 °C; VGREF = 5 V ± 0.5 V; GND = 0 V; CL = 50 pF; unless otherwise specified. Refer to Figure 10.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
tPD
propagation delay
-
-
250
ps
[1] This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
3.0 V
input
1.5 V
1.5 V
0 V
V
t
t
PHL
PLH
OH
output
1.5 V
1.5 V
V
OL
002aab664
tPD = the maximum of tPLH or tPHL
.
VM = 1.5 V; VI = GND to 3.0 V.
Fig 8. Input (Sn) to output (Dn) propagation delays
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
11 of 20
GTL2010
NXP Semiconductors
10-bit bidirectional low voltage translator
13. Test information
V
V
V
V
CC1
200 kΩ
CC2
150 Ω
CC2
CC2
150 Ω
150 Ω
DREF
SREF
GREF
D1
S1
D10
S10
DUT
test jig
V
ref
pulse
generator
002aac064
Fig 9. Load circuit for translator-type applications
R
L
7 V
S1
from output under test
open
GND
500 Ω
C
50 pF
R
L
500 Ω
L
002aab667
Test data are given in Table 12.
CL = load capacitance; includes jig and probe capacitance.
RL = load resistance.
Fig 10. Load circuit for CBT-type application
Table 12. Test data
Test
Load
CL
Switch
RL
tPD
50 pF
50 pF
50 pF
500 Ω
500 Ω
500 Ω
open
7 V
tPLZ, tPZL
tPHZ, tPZH
open
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
12 of 20
GTL2010
NXP Semiconductors
10-bit bidirectional low voltage translator
14. Package outline
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT355-1
MO-153
Fig 11. Package outline SOT355-1 (TSSOP24)
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
13 of 20
GTL2010
NXP Semiconductors
10-bit bidirectional low voltage translator
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
SOT616-1
B
A
D
terminal 1
index area
A
A
1
E
c
detail X
e
1
C
1/2 e
y
y
C
1
e
v
M
M
C
C
A
B
b
7
12
w
L
13
6
e
e
E
h
2
1/2 e
1
18
terminal 1
index area
24
19
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
mm
A
b
c
E
e
e
e
2
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.5
0.3
0.05
0.1
1
0.2
0.5
2.5
2.5
0.1 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-08-08
02-10-22
SOT616-1
- - -
MO-220
- - -
Fig 12. Package outline SOT616-1 (HVQFN24)
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15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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Product data sheet
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15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 13) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 13 and 14
Table 13. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 14. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 13.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 13. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16. Abbreviations
Table 15. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
GTL
Gunning Transceiver Logic
Human Body Model
HBM
I2C-bus
LVTTL
MM
Inter IC bus
Low Voltage Transistor-Transistor Logic
Machine Model
NMOS
TTL
Negative-channel Metal Oxide Semiconductor
Transistor-Transistor Logic
Transceiver Voltage Clamps
TVC
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17. Revision history
Table 16. Revision history
Document ID
GTL2010_6
Release date
Data sheet status
Change notice
Supersedes
20080303
Product data sheet
-
GTL2010_5
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Table 7 “Limiting values[1]”: deleted (old) table note [1] (statement is now in Section 18.3
“Disclaimers”)
• Table 9 “Static characteristics”:
–
Ron maximum value for condition VI = 0 V; IO = 64 mA; VGREF = 1.5 V changed from 105 Ω to
115 Ω
–
Symbol “IIH, gate input leakage” changed to “ILI(G), gate input leakage current”
GTL2010_5
(9397 750 13854)
20040728
20030502
20030401
20000830
19990405
Product data sheet
-
GTL2010_4
GTL2010_3
GTL2010_2
GTL2010_1
-
GTL2010_4
(9397 750 11458)
Product data
853-2153 29981 of
2003 May 01
GTL2010_3
(9397 750 11352)
Product data
853-2153 29603 of
2003 Feb 28
GTL2010_2
(9397 750 07462)
Product specification
Product specification
853-2153 24452 of
2000 Aug 30
GTL2010_1
-
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18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
18.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
18.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet
Rev. 06 — 3 March 2008
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20. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
3
4
4.1
5
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 4
7.1
Function selection. . . . . . . . . . . . . . . . . . . . . . . 4
8
Application design-in information . . . . . . . . . . 5
Bidirectional translation. . . . . . . . . . . . . . . . . . . 5
Unidirectional down translation. . . . . . . . . . . . . 6
Unidirectional up translation . . . . . . . . . . . . . . . 6
Sizing pull-up resistor . . . . . . . . . . . . . . . . . . . . 7
8.1
8.2
8.3
8.4
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 8
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
10
11
12
12.1
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Dynamic characteristics for translator-type
application. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Dynamic characteristics for CBT-type
12.2
application. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13
14
Test information. . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
15
Soldering of SMD packages . . . . . . . . . . . . . . 15
Introduction to soldering . . . . . . . . . . . . . . . . . 15
Wave and reflow soldering . . . . . . . . . . . . . . . 15
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16
15.1
15.2
15.3
15.4
16
17
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 March 2008
Document identifier: GTL2010_6
相关型号：
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