GTL2012DP,118 [NXP]
GTL2012 - 2-bit LVTTL to GTL transceiver TSSOP 8-Pin;
| 型号： | GTL2012DP,118 |
| 厂家： | 
NXP |
| 描述： | GTL2012 - 2-bit LVTTL to GTL transceiver TSSOP 8-Pin 光电二极管 接口集成电路 |
| 文件： | 总14页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GTL2012
2-bit LVTTL to GTL transceiver
Rev. 01 — 9 August 2007
Product data sheet
1. General description
The GTL2012 is a 2-bit translating transceiver designed for 3.3 V system interface with a
GTL−/GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling
receiver or as an LVTTL-to-GTL interface.
The GTL2012 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or
5 V CMOS inputs.
2. Features
I Operates as a 2-bit GTL−/GTL/GTL+ sampling receiver or as an LVTTL to
GTL−/GTL/GTL+ driver
I 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
I GTL input and output 3.6 V tolerant
I Vref adjustable from 0.5 V to 0.5VCC
I Partial power-down permitted
I Latch-up protection exceeds 500 mA per JESD78
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-CC101
I Package offered: TSSOP8 (MSOP8) and VSSOP8
3. Quick reference data
Table 1.
Quick reference data
Recommended operating conditions; Tamb = 25 °C
Symbol
Ci
Parameter
Conditions
Min
Typ[1] Max Unit
input capacitance
input/output capacitance
control inputs; VI = 3.0 V or 0 V
A port; VO = 3.0 V or 0 V
B port; VO = VTT or 0 V
-
-
-
2
2.5
6
pF
pF
pF
Cio
4.6
3.4
4.3
GTL; Vref = 0.8 V; VTT = 1.2 V
tPLH
tPHL
tPLH
tPHL
LOW-to-HIGH propagation delay
An to Bn; see Figure 4
An to Bn; see Figure 4
Bn to An; see Figure 5
Bn to An; see Figure 5
-
-
-
-
2.8
3.4
5.2
4.9
5
7
8
7
ns
ns
ns
ns
HIGH-to-LOW propagation delay
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
GTL2012
NXP Semiconductors
2-bit LVTTL to GTL transceiver
4. Ordering information
Table 2.
Ordering information
Tamb = −40 °C to +85 °C
Type number
Topside mark
Package
Name
Description
Version
GTL2012DP
GTL2012DC
012P
012C
TSSOP8[1]
plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
VSSOP8
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
[1] Also known as MSOP8.
5. Functional diagram
GTL2012
&
B0
A0
&
B1
A1
002aab605
VREF
DIR
Fig 1. Logic diagram of GTL2012
GTL2012_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 9 August 2007
2 of 14
GTL2012
NXP Semiconductors
2-bit LVTTL to GTL transceiver
6. Pinning information
6.1 Pinning
1
2
3
4
8
7
6
5
A0
A1
V
CC
1
2
3
4
8
7
6
5
A0
A1
V
CC
VREF
B0
VREF
B0
GTL2012DP
GTL2012DC
DIR
GND
DIR
GND
B1
B1
002aab606
002aac398
Fig 2. Pin configuration for TSSOP8
(MSOP8)
Fig 3. Pin configuration for VSSOP8
6.2 Pin description
Table 3.
Pin description
Symbol
A0
Pin
1
Description
data inputs/outputs (A side, LVTTL)
A1
2
DIR
GND
B1
3
direction control input (LVTTL)
ground (0 V)
4
5
data inputs/outputs (B side, GTL)
B0
6
VREF
VCC
7
GTL reference voltage
positive supply voltage
8
7. Functional description
Refer to Figure 1 “Logic diagram of GTL2012”.
7.1 Function table
Table 4.
Function table
H = HIGH voltage level; L = LOW voltage level.
Input
DIR
H
Input/output
A (LVTTL)
inputs
B (GTL)
Bn = An
inputs
L
An = Bn
GTL2012_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 9 August 2007
3 of 14
GTL2012
NXP Semiconductors
2-bit LVTTL to GTL transceiver
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
-
Max
+4.6
−50
+7.0
+4.6
−50
+7.0
+4.6
32
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
[1]
VI
A port
−0.5
−0.5
-
B port
V
IOK
VO
output clamping current
output voltage
VO < 0 V
mA
V
[1]
[1]
output in OFF or HIGH state; A port
−0.5
−0.5
-
output in OFF or HIGH state; B port
V
IOL
LOW-level output current[2]
A port
B port
A port
mA
mA
mA
°C
-
80
IOH
HIGH-level output current[3]
storage temperature
-
−32
+150
[4]
Tstg
−60
[1] The input and output negative voltage ratings may be exceeded if the input and output clamping current ratings are observed.
[2] Current into any output in the LOW state.
[3] Current into any output in the HIGH state.
[4] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
9. Recommended operating conditions
Table 6.
Unused inputs must be held HIGH or LOW to prevent them from floating.
Recommended operating conditions[1]
Symbol
VCC
Parameter
Conditions
Min
Typ
-
Max
3.6
Unit
V
supply voltage
termination voltage[2]
3.0
VTT
GTL−
0.85
0.9
1.2
1.5
2⁄3VTT
0.6
0.8
1.0
VTT
3.3
-
0.95
1.26
1.65
0.5VCC
0.63
0.84
1.10
3.6
V
GTL
1.14
V
GTL+
1.35
V
Vref
reference voltage
overall
0.5
V
GTL−
0.5
V
GTL
0.76
V
GTL+
0.87
V
VI
input voltage
B port
0
V
[3]
except B port
B port
0
5.5
V
VIH
VIL
IOH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
Vref + 0.050
-
V
except B port
B port
2
-
-
-
V
-
Vref − 0.050
V
except B port
A port
-
-
0.8
V
-
-
−16
mA
GTL2012_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 9 August 2007
4 of 14
GTL2012
NXP Semiconductors
2-bit LVTTL to GTL transceiver
Table 6.
Recommended operating conditions[1] …continued
Unused inputs must be held HIGH or LOW to prevent them from floating.
Symbol
Parameter
Conditions
B port
Min
Typ
Max
40
Unit
mA
mA
°C
IOL
LOW-level output current
-
-
-
-
A port
-
16
Tamb
ambient temperature
operating in free-air
−40
+85
[1] Unused inputs must be held HIGH or LOW to prevent them from floating.
[2] VTT maximum of 3.6 V with resistor sized so IOL maximum is not exceeded.
[3] A0, A1 VI(max) is 3.6 V if configured as outputs (DIR = L).
10. Static characteristics
Table 7.
Static characteristics
Recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = −40 °C to +85 °C.
Symbol Parameter
VOH HIGH-level output
Conditions
Min
Typ[1]
-
Max
-
Unit
V
[2]
[2]
[2]
[2]
[2]
[2]
A port; VCC = 3.0 V to 3.6 V; IOH = −100 µA
A port; VCC = 3.0 V; IOH = −16 mA
B port; VCC = 3.0 V; IOL = 40 mA
A port; VCC = 3.0 V; IOL = 8 mA
A port; VCC = 3.0 V; IOL = 12 mA
A port; VCC = 3.0 V; IOL = 16 mA
VCC − 0.2
voltage
2.0
-
-
V
VOL
LOW-level output
voltage
-
-
-
-
-
0.23
0.28
0.40
0.55
-
0.4
0.4
0.55
0.8
±1
V
V
V
V
II
input current
control inputs; VCC = 3.6 V;
VI = VCC or GND
µA
B port; VCC = 3.6 V; VI = VTT or GND
A port; VCC = 0 V or 3.6 V; VI = 5.5 V
A port; VCC = 3.6 V; VI = VCC
-
-
-
-
-
-
-
-
-
-
±1
µA
µA
µA
µA
µA
10
±1
A port; VCC = 3.6 V; VI = 0 V
−5
IOZ
ICC
off-state output
current
A port; VCC = 0 V; VI or VO = 0 V to 3.6 V
±100
supply current
A port; VCC = 3.6 V; VI = VCC or GND;
IO = 0 mA
-
-
-
4
4
-
10
mA
mA
µA
B port; VCC = 3.6 V; VI = VTT or GND;
IO = 0 mA
10
[3]
∆ICC
additional supply
current
per input; A port or control inputs;
500
VCC = 3.6 V; VI = VCC − 0.6 V
Ci
input capacitance
control inputs; VI = 3.0 V or 0 V
A port; VO = 3.0 V or 0 V
B port; VO = VTT or 0 V
-
-
-
2
2.5
6
pF
pF
pF
Cio
input/output
capacitance
4.6
3.4
4.3
[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
[2] The input and output voltage ratings my be exceeded if the input and output current ratings are observed.
[3] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
GTL2012_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 9 August 2007
5 of 14
GTL2012
NXP Semiconductors
2-bit LVTTL to GTL transceiver
11. Dynamic characteristics
Table 8.
Dynamic characteristics
VCC = 3.3 V ± 0.3 V
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
GTL−; Vref = 0.6 V; VTT = 0.9 V
tPLH
tPHL
tPLH
tPHL
LOW-to-HIGH propagation delay
An to Bn; see Figure 4
An to Bn; see Figure 4
Bn to An; see Figure 5
Bn to An; see Figure 5
-
-
-
-
2.8
3.3
5.3
5.2
5
7
8
8
ns
ns
ns
ns
HIGH-to-LOW propagation delay
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
GTL; Vref = 0.8 V; VTT = 1.2 V
tPLH
tPHL
tPLH
tPHL
LOW-to-HIGH propagation delay
An to Bn; see Figure 4
An to Bn; see Figure 4
Bn to An; see Figure 5
Bn to An; see Figure 5
-
-
-
-
2.8
3.4
5.2
4.9
5
7
8
7
ns
ns
ns
ns
HIGH-to-LOW propagation delay
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
GTL+; Vref = 1.0 V; VTT = 1.5 V
tPLH
tPHL
tPLH
tPHL
LOW-to-HIGH propagation delay
An to Bn; see Figure 4
An to Bn; see Figure 4
Bn to An; see Figure 5
Bn to An; see Figure 5
-
-
-
-
2.8
3.4
5.1
4.7
5
7
8
7
ns
ns
ns
ns
HIGH-to-LOW propagation delay
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
[1] All typical values are at VCC = 3.3 V and Tamb = 25 °C.
11.1 Waveforms
VM = 1.5 V at VCC ≥ 3.0 V; VM = 0.5VCC at VCC ≤ 2.7 V for A ports and control pins;
VM = Vref for B ports.
3.0 V
0 V
input
1.5 V
1.5 V
t
t
PHL
PLH
t
p
V
3.0 V
0 V
OH
output
V
V
ref
ref
V
V
M
M
V
OL
002aab141
002aab140
VM = 1.5 V for B port and Vref for
A port
B port to A port
a. Pulse duration
b. Propagation delay times
Fig 4. Voltage waveforms
GTL2012_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 9 August 2007
6 of 14
GTL2012
NXP Semiconductors
2-bit LVTTL to GTL transceiver
3.0 V
0 V
input
V
V
ref
ref
t
t
PHL
PLH
V
V
OH
OL
output
1.5 V
1.5 V
002aab163
PRR ≤ 10 MHz; Zo = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns
Fig 5. Propagation delay, An to Bn
12. Test information
V
CC
V
V
O
I
PULSE
GENERATOR
DUT
R
500 Ω
C
L
50 pF
L
R
T
002aab006
Fig 6. Load circuitry for switching times
V
TT
V
CC
25 Ω
V
V
O
I
PULSE
GENERATOR
DUT
C
30 pF
L
R
T
002aab143
Fig 7. Load circuit for B outputs
RL — Load resistor.
CL — Load capacitance; includes jig and probe capacitance.
RT — Termination resistance; should be equal to Zo of pulse generators.
GTL2012_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 9 August 2007
7 of 14
GTL2012
NXP Semiconductors
2-bit LVTTL to GTL transceiver
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
A
(A )
2
A
3
A
1
pin 1 index
θ
L
p
L
1
4
detail X
e
w M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.05
0.95
0.80
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
5.1
4.7
0.7
0.4
0.70
0.35
6°
0°
mm
1.1
0.65
0.25
0.94
0.1
0.1
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-04-09
03-02-18
SOT505-1
Fig 8. Package outline SOT505-1 (TSSOP8)
GTL2012_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 9 August 2007
8 of 14
GTL2012
NXP Semiconductors
2-bit LVTTL to GTL transceiver
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 9. Package outline SOT765-1 (VSSOP8)
GTL2012_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 9 August 2007
9 of 14
GTL2012
NXP Semiconductors
2-bit LVTTL to GTL transceiver
14. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus PbSn soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
GTL2012_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 9 August 2007
10 of 14
GTL2012
NXP Semiconductors
2-bit LVTTL to GTL transceiver
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 10) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Table 9.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
220
< 2.5
235
220
≥ 2.5
220
Table 10. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 10.
GTL2012_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 9 August 2007
11 of 14
GTL2012
NXP Semiconductors
2-bit LVTTL to GTL transceiver
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 10. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 11. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal Oxide Silicon
Device Under Test
ESD
ElectroStatic Discharge
Gunning Transceiver Logic
Human Body Model
GTL
HBM
LVTTL
MM
Low Voltage Transistor-Transistor Logic
Machine Model
PRR
Pulse Repetition Rate
TTL
Transistor-Transistor Logic
16. Revision history
Table 12. Revision history
Document ID
Release date
20070809
Data sheet status
Change notice
Supersedes
GTL2012_1
Product data sheet
-
-
GTL2012_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 9 August 2007
12 of 14
GTL2012
NXP Semiconductors
2-bit LVTTL to GTL transceiver
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
17.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
18. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
GTL2012_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 9 August 2007
13 of 14
GTL2012
NXP Semiconductors
2-bit LVTTL to GTL transceiver
19. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 3
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test information. . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
9
10
11
11.1
12
13
14
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Introduction to soldering . . . . . . . . . . . . . . . . . 10
Wave and reflow soldering . . . . . . . . . . . . . . . 10
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 10
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 11
14.1
14.2
14.3
14.4
15
16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 August 2007
Document identifier: GTL2012_1
相关型号：
GTL2018PW/Q900
IC SPECIALTY INTERFACE CIRCUIT, PDSO24, 4.40 MM, PLASTIC, MO-153, SOT355-1, TSSOP-24, Interface IC:Other
NXP
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