HEC40106BT [NXP]

IC HEX 1-INPUT INVERT GATE, PDSO14, PLASTIC, SOT-108-1, SO-14, Gate;
HEC40106BT
型号: HEC40106BT
厂家: NXP    NXP
描述:

IC HEX 1-INPUT INVERT GATE, PDSO14, PLASTIC, SOT-108-1, SO-14, Gate

栅 输入元件 光电二极管 逻辑集成电路
文件: 总7页 (文件大小:85K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
The IC04 LOCMOS HE4000B Logic  
Family Specifications HEF, HEC  
The IC04 LOCMOS HE4000B Logic  
Package Outlines/Information HEF, HEC  
HEF40106B  
gates  
Hex inverting Schmitt trigger  
January 1995  
Product specification  
File under Integrated Circuits, IC04  
Philips Semiconductors  
Product specification  
HEF40106B  
gates  
Hex inverting Schmitt trigger  
DESCRIPTION  
Each circuit of the HEF40106B functions as an inverter  
with Schmitt-trigger action. The Schmitt-trigger switches at  
different points for the positive and negative-going input  
signals. The difference between the positive-going voltage  
(VP) and the negative-going voltage (VN) is defined as  
hysteresis voltage (VH).  
This device may be used for enhanced noise immunity or  
to “square up” slowly changing waveforms.  
Fig.2 Pinning diagram.  
HEF40106BP(N): 14-lead DIL; plastic  
(SOT27-1)  
HEF40106BD(F): 14-lead DIL; ceramic (cerdip)  
(SOT73)  
HEF40106BT(D): 14-lead SO; plastic  
(SOT108-1)  
( ): Package Designator North America  
Fig.1 Functional diagram.  
Fig.3 Logic diagram (one inverter).  
FAMILY DATA, IDD LIMITS category GATES  
See Family Specifications  
January 1995  
2
Philips Semiconductors  
Product specification  
HEF40106B  
gates  
Hex inverting Schmitt trigger  
DC CHARACTERISTICS  
VSS = 0 V; Tamb = 25 °C  
VDD  
V
SYMBOL  
MIN.  
TYP.  
MAX.  
Hysteresis  
voltage  
5
10  
15  
5
0,5  
0,7  
0,9  
2
0,8  
1,3  
1,8  
3,0  
5,8  
8,3  
2,2  
4,5  
6,5  
V
V
V
V
V
V
V
V
V
VH  
Switching levels  
positive-going  
input voltage  
negative-going  
input voltage  
3,5  
7
10  
15  
5
VP  
VN  
3,7  
4,9  
1,5  
3
11  
3
10  
15  
6,3  
10,1  
4
Fig.5 Waveforms showing definition of  
VP, VN and VH, where VN and VP are  
between limits of 30% and 70%.  
Fig.4 Transfer characteristic.  
January 1995  
3
Philips Semiconductors  
Product specification  
HEF40106B  
gates  
Hex inverting Schmitt trigger  
AC CHARACTERISTICS  
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns  
VDD  
V
TYPICAL EXTRAPOLATION  
FORMULA  
SYMBOL  
TYP. MAX.  
Propagation delays  
In On  
HIGH to LOW  
5
90  
35  
30  
75  
35  
30  
60  
30  
20  
60  
30  
20  
180  
70  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
63 ns + (0,55 ns/pF) CL  
24 ns + (0,23 ns/pF)  
10  
15  
5
tPHL  
tPLH  
tTHL  
tTLH  
60  
22 ns + (0,16 ns/pF) CL  
48 ns + (0,55 ns/pF) CL  
24 ns + (0,23 ns/pF) CL  
22 ns + (0,16 ns/pF) CL  
10 ns + (1,0 ns/pF) CL  
9 ns + (0,42 ns/pF) CL  
6 ns + (0,28 ns/pF) CL  
10 ns + (1,0 ns/pF) CL  
9 ns + (0,42 ns/pF) CL  
6 ns + (0,28 ns/pF) CL  
150  
70  
LOW to HIGH  
10  
15  
5
60  
Output transition times  
HIGH to LOW  
120  
60  
10  
15  
5
40  
120  
60  
LOW to HIGH  
10  
15  
40  
VDD  
V
TYPICAL FORMULA FOR P (µW)  
2
Dynamic power  
dissipation per  
package (P)  
5
2 300 fi + ∑ (foCL) × VDD  
where  
2
10  
15  
9 000 fi + ∑ (foCL) × VDD  
fi = input freq. (MHz)  
fo = output freq. (MHz)  
CL = load capacitance (pF)  
(foCL) = sum of outputs  
2
20 000 fi + ∑ (foCL) × VDD  
VDD = supply voltage (V)  
January 1995  
4
Philips Semiconductors  
Product specification  
HEF40106B  
gates  
Hex inverting Schmitt trigger  
Fig.6 Typical drain current as a function of input  
Fig.7 Typical drain current as a function of input  
voltage; VDD = 5 V; Tamb = 25 °C.  
voltage; VDD =10 V; Tamb = 25 °C.  
Fig.8 Typical drain current as a function of input  
voltage; VDD = 15 V; Tamb = 25 °C.  
January 1995  
5
Philips Semiconductors  
Product specification  
HEF40106B  
gates  
Hex inverting Schmitt trigger  
Fig.9 Typical switching levels as a function of supply voltage VDD; Tamb = 25 °C.  
Fig.10 Schmitt trigger driven via a high impedance (R > 1 k).  
If a Schmitt trigger is driven via a high impedance (R > 1 k) then it is necessary to incorporate a capacitor C of such  
V
DD VSS  
C
Cp  
------ ---------------------------  
>
value that:  
, otherwise oscillation can occur on the edges of a pulse.  
VH  
Cp is the external parasitic capacitance between input and output; the value depends on the circuit board layout.  
January 1995  
6
Philips Semiconductors  
Product specification  
HEF40106B  
gates  
Hex inverting Schmitt trigger  
APPLICATION INFORMATION  
Some examples of applications for the HEF40106B are:  
Wave and pulse shapers  
Astable multivibrators  
Monostable multivibrators.  
Fig.11 The HEF40106B used as an astable multivibrator.  
January 1995  
7

相关型号:

HEC40106BT,118

IC 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDSO14, PLASTIC, SOT-108-1, SO-14, Gate
NXP

HEC4011

gates Quadruple 2-input NAND gate
NXP

HEC4011B

gates Quadruple 2-input NAND gate
NXP

HEC4011BD

IC 4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, CDIP14, Gate
NXP

HEC4011BDB

IC 4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, CDIP14, Gate
NXP

HEC4012BD

4000/14000/40000 SERIES, DUAL 4-INPUT NAND GATE, CDIP14
NXP

HEC4012BDB

4000/14000/40000 SERIES, DUAL 4-INPUT NAND GATE, CDIP14
NXP

HEC4013BD

IC 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14, FF/Latch
NXP

HEC4013BT

Dual D-type flip-flop
NXP

HEC4013BT,118

IC 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, SOT-108, SO-14, FF/Latch
NXP

HEC4014

8-bit static shift register
NXP

HEC4014BD

IC 4000/14000/40000 SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, Shift Register
NXP