HEC4013BT,118 [NXP]
IC 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, SOT-108, SO-14, FF/Latch;
| 型号： | HEC4013BT,118 |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, SOT-108, SO-14, FF/Latch 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总15页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HEF4013B
Dual D-type flip-flop
Rev. 05 — 19 June 2009
Product data sheet
1. General description
The HEF4013B is a dual D-type flip-flop that features independent set-direct input (SD),
clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is
LOW and is transferred to the output on the positive-going edge of the clock. The active
HIGH asynchronous CD and SD inputs are independent and override the D or CP inputs.
The outputs are buffered for best system performance. The clock input’s Schmitt-trigger
action makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input. The
device is suitable for use over both the industrial (−40 °C to +85 °C) and automotive
(−40 °C to +125 °C) temperature ranges.
2. Features
I Tolerant of slow clock rise and fall times
I Fully static operation
I 5 V, 10 V, and 15 V parametric ratings
I Standardized symmetrical output characteristics
I Operates across the automotive temperature range from −40 °C to +125 °C
I Complies with JEDEC standard JESD 13-B
3. Applications
I Automotive and industrial
I Counters and dividers
I Registers
I Toggle flip-flops
4. Ordering information
Table 1.
Ordering information
All types operate from −40 °C to +125 °C
Type number
Package
Name
Description
Version
HEF4013BP
HEF4013BT
HEF4013BTT
DIP14
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads; body width 3.9 mm
plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT27-1
SOT108-1
SOT402-1
SO14
TSSOP14
HEF4013B
NXP Semiconductors
Dual D-type flip-flop
5. Functional diagram
6
5
1SD
1D
SD
1
2
D
Q
Q
1Q
1Q
FF1
3
1CP
CP
CD
4
8
1CD
2SD
SD
9
13
12
2D
D
Q
Q
2Q
2Q
FF2
11
10
2CP
2CD
CP
CD
001aag084
Fig 1. Functional diagram
CP
C
C
Q
C
C
C
C
C
C
D
Q
C
C
SD
CD
001aag086
Fig 2. Logic diagram (one flip-flop)
HEF4013B_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 19 June 2009
2 of 15
HEF4013B
NXP Semiconductors
Dual D-type flip-flop
6. Pinning information
6.1 Pinning
1
2
3
4
5
6
7
14
13
12
11
10
9
1Q
1Q
V
DD
2Q
1CP
1CD
1D
2Q
HEF4013B
2CP
2CD
2D
1SD
8
V
SS
2SD
001aag085
Fig 3. Pin configuration
6.2 Pin description
Table 2.
Symbol
1Q, 2Q
1Q, 2Q
1CP, 2CP
1CD, 2CD
1D, 2D
1SD, 2SD
VSS
Pin description
Pin
Description
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
true output
complement output
clock input (LOW to HIGH edge-triggered)
asynchronous clear-direct input (active HIGH)
data input
asynchronous set-direct input (active HIGH)
ground (0 V)
VDD
14
supply voltage
7. Functional description
Table 3.
Function table[1]
Control
Input
nD
X
Output
nSD
H
nCD
L
nCP
X
nQ
H
L
nQ
L
L
H
X
X
H
H
H
L
H
H
X
X
H
L
L
L
↑
L
L
L
↑
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition.
HEF4013B_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 19 June 2009
3 of 15
HEF4013B
NXP Semiconductors
Dual D-type flip-flop
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
VDD
IIK
Parameter
Conditions
Min
−0.5
-
Max
+18
Unit
V
supply voltage
input clamping current
input voltage
VI < −0.5 V or VI > VDD + 0.5 V
VO < −0.5 V or VO > VDD + 0.5 V
±10
mA
V
VI
−0.5
-
VDD + 0.5
±10
IOK
output clamping current
input/output current
supply current
mA
mA
mA
°C
II/O
-
±10
IDD
-
50
Tstg
Tamb
Ptot
storage temperature
ambient temperature
total power dissipation
−65
−40
+150
+125
°C
Tamb = −40 °C to +125 °C
DIP14
[1]
[2]
[3]
-
-
-
-
750
500
500
100
mW
mW
mW
mW
SO14
TSSOP14
P
power dissipation
per output
[1] For DIP14 packages: above Tamb = 70 °C, Ptot derates linearly with 12 mW/K.
[2] For SO14 packages: above Tamb = 70 °C, Ptot derates linearly with 8 mW/K.
[3] For TSSOP14 packages: above Tamb = 60 °C, Ptot derates linearly with 5.5 mW/K.
9. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Max
15
Unit
V
supply voltage
3
VI
input voltage
0
VDD
+125
3.75
0.5
V
Tamb
ambient temperature
input transition rise and fall rate
−40
°C
∆t/∆V
VDD = 5 V
VDD = 10 V
VDD = 15 V
-
-
-
ns/V
ns/V
ns/V
0.08
HEF4013B_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 19 June 2009
4 of 15
HEF4013B
NXP Semiconductors
Dual D-type flip-flop
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = −40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit
Min
3.5
7.0
11.0
-
Max
Min
3.5
7.0
11.0
-
Max
Min
3.5
7.0
11.0
-
Max
Min
3.5
7.0
11.0
-
Max
VIH
HIGH-level
input voltage
|IO| < 1 µA
5 V
10 V
15 V
5 V
-
-
-
-
V
-
-
-
-
V
-
-
-
-
V
VIL
LOW-level
input voltage
|IO| < 1 µA
|IO| < 1 µA
|IO| < 1 µA
1.5
1.5
1.5
1.5
V
10 V
15 V
5 V
-
3.0
-
3.0
-
3.0
-
3.0
V
-
4.0
-
4.0
-
4.0
-
4.0
V
VOH
VOL
IOH
HIGH-level
output voltage
4.95
9.95
14.95
-
-
4.95
9.95
14.95
-
-
4.95
9.95
14.95
-
-
4.95
9.95
14.95
-
-
V
10 V
15 V
5 V
-
-
-
-
V
-
-
-
-
V
LOW-level
output voltage
0.05
0.05
0.05
0.05
V
10 V
15 V
5 V
-
0.05
-
0.05
-
0.05
-
0.05
V
-
0.05
-
0.05
-
0.05
-
0.05
V
HIGH-level
output current
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
−1.7
−0.64
−1.6
−4.2
0.64
1.6
4.2
-
-
−1.4
−0.5
−1.3
−3.4
0.5
1.3
3.4
-
-
−1.1
−0.36
−0.9
−2.4
0.36
0.9
2.4
-
-
−1.1
−0.36
−0.9
−2.4
0.36
0.9
2.4
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
5 V
-
-
-
10 V
-
-
-
VO = 13.5 V 15 V
-
-
-
IOL
LOW-level
output current
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
5 V
10 V
15 V
15 V
-
-
-
-
-
-
-
-
-
II
input leakage
current
±0.1
±0.1
±1.0
±1.0 µA
IDD
supply current all valid input
combinations;
5 V
10 V
15 V
-
-
-
-
-
1.0
2.0
4.0
-
-
-
-
-
1.0
2.0
4.0
7.5
-
-
-
-
30
60
120
-
-
-
-
-
30
60
µA
µA
|IO| = 0 A
120 µA
pF
CI
input
-
capacitance
HEF4013B_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 19 June 2009
5 of 15
HEF4013B
NXP Semiconductors
Dual D-type flip-flop
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Tamb = 25 °C; unless otherwise specified. For test circuit see Figure 6.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula Min
Typ Max Unit
[1]
[1]
[1]
[1]
[1]
[1]
[1]
tPHL
HIGH to LOW
nCP to nQ, nQ;
see Figure 4
83 + 0.55 × CL
34 + 0.23 × CL
22 + 0.16 × CL
73 + 0.55 × CL
29 + 0.23 × CL
22 + 0.16 × CL
73 + 0.55 × CL
29 + 0.23 × CL
22 + 0.16 × CL
68 + 0.55 × CL
29 + 0.23 × CL
22 + 0.16 × CL
48 + 0.55 × CL
24 + 0.23 × CL
17 + 0.16 × CL
33 + 0.55 × CL
19 + 0.23 × CL
12 + 0.16 × CL
10 + 1.00 × CL
9 + 0.42 × CL
6 + 0.28 × CL
-
110 220 ns
propagation delay
10 V
15 V
5 V
-
45
30
90 ns
60 ns
-
nSD to nQ
nCD to nQ
-
100 200 ns
10 V
15 V
5 V
-
40
30
80 ns
60 ns
-
-
100 200 ns
10 V
15 V
5 V
-
40
30
80 ns
60 ns
-
tPLH
LOW to HIGH
nCP to nQ, nQ;
see Figure 4
-
95 190 ns
propagation delay
10 V
15 V
5 V
-
40
30
80 ns
60 ns
-
nSD to nQ
nCD to nQ
see Figure 4
-
75 150 ns
10 V
15 V
5 V
-
35
25
70 ns
50 ns
-
-
60 120 ns
10 V
15 V
5 V
-
30
20
60 ns
40 ns
-
tt
transition time
set-up time
hold time
-
60 120 ns
10 V
15 V
5 V
-
30
20
20
10
5
60 ns
40 ns
ns
-
tsu
nD to nCP;
see Figure 4
40
25
15
20
20
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10 V
15 V
5 V
ns
ns
th
nD to nCP;
see Figure 4
0
ns
10 V
15 V
5 V
0
ns
0
ns
tW
pulse width
nCP input LOW;
see Figure 4
60
30
15
10
25
12
10
25
12
10
ns
10 V
15 V
5 V
30
20
50
24
20
50
24
20
ns
ns
nSD input HIGH;
see Figure 5
ns
10 V
15 V
5 V
ns
ns
nCD input HIGH;
see Figure 5
ns
10 V
15 V
ns
ns
HEF4013B_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 19 June 2009
6 of 15
HEF4013B
NXP Semiconductors
Dual D-type flip-flop
Table 7.
Dynamic characteristics …continued
Tamb = 25 °C; unless otherwise specified. For test circuit see Figure 6.
Symbol Parameter
trec recovery time
Conditions
VDD
5 V
Extrapolation formula Min
Typ Max Unit
nSD input;
see Figure 5
+15
15
15
40
25
25
7
−5
0
-
-
-
-
-
-
-
-
-
ns
10 V
15 V
5 V
ns
0
ns
nCD input;
see Figure 5
25
10
10
14
28
40
ns
10 V
15 V
5 V
ns
ns
fclk(max) maximum clock
frequency
see Figure 4
MHz
MHz
MHz
10 V
15 V
14
20
[1] Typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas. CL is given in pF.
Table 8.
Dynamic power dissipation
VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol Parameter
VDD Typical formula
Where
PD
dynamic power dissipation
5 V PD = 850 × fi + Σ(fo × CL) × VDD2 µW fi = input frequency in MHz;
10 V PD = 3600 × fi + Σ(fo × CL) × VDD2 µW
15 V PD = 9000 × fi + Σ(fo × CL) × VDD2 µW
fo = output frequency in MHz;
CL = output load capacitance in pF;
Σ(fo × CL) = sum of the outputs;
VDD = supply voltage in V.
12. Waveforms
1/f
t
W
clk(max)
V
I
V
input nCP
M
0 V
t
t
su
su
t
t
r
f
t
t
h
h
V
I
V
input nD
M
0 V
t
t
PHL
PLH
t
t
t
t
V
OH
V
Y
V
output nQ
M
V
X
V
OL
001aah016
Set-up and hold times are shown as positive values but may be specified as negative values.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 9.
Fig 4. Set-up time, hold time, minimum clock pulse width, propagation delays and transition times
HEF4013B_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 19 June 2009
7 of 15
HEF4013B
NXP Semiconductors
Dual D-type flip-flop
V
I
input nCP
0 V
V
M
t
t
rec
rec
V
I
input nSD
0 V
V
M
t
W
V
I
V
input nCD
0 V
M
t
W
V
OH
output nQ
001aag088
V
OL
Recovery times are shown as positive values but may be specified as negative values.
Measurement points are given in Table 9.
Fig 5. nSD, nCD recovery time and pulse width
Table 9.
Measurement points
Supply voltage
VDD
Input
VM
Output
VM
VX
VY
5 V to 15 V
0.5VDD
0.5VDD
0.1VDD
0.9VDD
V
DD
V
V
O
I
G
DUT
C
L
R
T
001aag182
Test and measurement data is given in Table 10;
Definitions test circuit:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 6. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VDD
Input
Load
CL
VI
tr, tf
5 V to 15 V
VSS or VDD
≤ 20 ns
50 pF
HEF4013B_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 19 June 2009
8 of 15
HEF4013B
NXP Semiconductors
Dual D-type flip-flop
13. Application information
D
D
Q
Q
D
Q
Q
D
Q
Q
Q
FF
1
FF
2
FF
n
CP
CP
CP
clock
001aag089
Fig 7. N-stage shift register
D
Q
Q
D
Q
Q
D
Q
Q
FF
1
FF
2
FF
n
clock
CP
CP
CP
Q
T-type flip-flop
001aag090
Fig 8. Binary ripple up-counter; divide-by-2n
D
Q
Q
D
Q
D
Q
Q
FF
1
FF
2
FF
n
CP
CP
Q
CP
Q
clock
001aag091
Fig 9. Modified ring counter; divide-by-(n + 1)
HEF4013B_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 19 June 2009
9 of 15
HEF4013B
NXP Semiconductors
Dual D-type flip-flop
14. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
14
8
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
Z
A
A
A
2
(1)
(1)
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2.2
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT27-1
050G04
MO-001
SC-501-14
Fig 10. Package outline SOT27-1 (DIP14)
HEF4013B_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 19 June 2009
10 of 15
HEF4013B
NXP Semiconductors
Dual D-type flip-flop
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 11. Package outline SOT108-1 (SO14)
HEF4013B_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 19 June 2009
11 of 15
HEF4013B
NXP Semiconductors
Dual D-type flip-flop
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 12. Package outline SOT402-1 (TSSOP14)
HEF4013B_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 19 June 2009
12 of 15
HEF4013B
NXP Semiconductors
Dual D-type flip-flop
15. Revision history
Table 11. Revision history
Document ID
HEF4013B_5
Modifications:
Release date
20090619
Data sheet status
Change notice
Supersedes
Product data sheet
-
HEF4013B_4
• Section 2 “Features” ESD (ElectroStatic Discharge) values removed.
• Table 4 “Limiting values” the conditions values of VI and VI for IIK and IOK modified.
• Abbreviations section removed.
• Section 16 “Legal information” export control statement added.
HEF4013B_4
20080515
19950101
19950101
Product data sheet
Product specification
Product specification
-
-
-
HEF4013B_CNV_3
HEF4013B_CNV_3
HEF4013B_CNV_2
HEF4013B_CNV_2
-
HEF4013B_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 19 June 2009
13 of 15
HEF4013B
NXP Semiconductors
Dual D-type flip-flop
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4013B_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 19 June 2009
14 of 15
HEF4013B
NXP Semiconductors
Dual D-type flip-flop
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application information. . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 19 June 2009
Document identifier: HEF4013B_5
相关型号：
HEC4014BD
IC 4000/14000/40000 SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, Shift Register
NXP
HEC4014BDB
IC 4000/14000/40000 SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, Shift Register
NXP
HEC4015BD
IC 4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, Shift Register
NXP
HEC4016BD
IC QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, CDIP14, CERDIP-14, Multiplexer or Switch
NXP
HEC40174BD
IC 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, FF/Latch
NXP
HEC40174BDB
IC 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, FF/Latch
NXP
HEC40175BD
4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
NXP
©2020 ICPDF网 联系我们和版权申明