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HEF40193BP,652 [NXP]

HEF40193B - 4-bit up/down binary counter DIP 16-Pin;
HEF40193BP,652
型号： HEF40193BP,652
厂家： NXP    NXP
描述：

HEF40193B - 4-bit up/down binary counter DIP 16-Pin

光电二极管 输出元件 逻辑集成电路 触发器
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HEF40193B  
4-bit up/down binary counter  
Rev. 8 — 18 November 2011  
Product data sheet  
1. General description  
The HEF40193B is a 4-bit synchronous up/down binary counter. The counter has a  
count-up clock input (CPU), a count-down clock input (CPD), an asynchronous parallel  
load input (PL), four parallel data inputs (D0 to D3), an asynchronous master reset input  
(MR), four counter outputs (Q0 to Q3), an active LOW terminal count-up (carry) output  
(TCU), and an active LOW terminal count-down (borrow) output (TCD).  
The counter outputs change state on the LOW-to-HIGH transition of either clock input.  
However, for correct counting, both clock inputs cannot be LOW simultaneously. The  
outputs TCU and TCD are normally HIGH. When the circuit has reached the maximum  
count state of ‘15’, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.  
TCU will stay LOW until CPU goes HIGH again. Likewise, output TCD will go LOW when  
the circuit is in the zero state and CPD goes LOW. When PL is LOW, the information on  
D0 to D3 is asynchronously loaded into the counter. A HIGH on MR resets the counter  
independent of all other input conditions. The counter stages are of a static toggle type  
flip-flop.  
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS  
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.  
2. Features and benefits  
Fully static operation  
5 V, 10 V, and 15 V parametric ratings  
Standardized symmetrical output characteristics  
Specified from 40 C to +85 C  
Complies with JEDEC standard JESD 13-B  
3. Ordering information  
Table 1.  
Ordering information  
All types operate from 40 C to +85 C.  
Type number  
Package  
Name  
Description  
Version  
HEF40193BP  
HEF40193BT  
DIP16  
SO16  
plastic dual in-line package; 16 leads (300 mil)  
plastic small outline package; 16 leads; body width 3.9 mm  
SOT38-4  
SOT109-1  
 
 
 
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
4. Functional diagram  
15  
D0  
1
10  
D2  
9
D1  
D3  
PL  
11  
PARALLEL LOAD CIRCUITRY  
CD/SD  
CPU  
CPD  
MR  
TCU  
TCD  
5
4
12  
13  
UP/DOWN  
COUNTER  
14  
CD  
Q0  
Q1  
Q2  
Q3  
3
2
6
7
001aae580  
Fig 1. Functional diagram  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
2 of 19  
 
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx  
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
D0  
PL  
D1  
D2  
D3  
CPD  
CPU  
SD  
SD  
SD  
SD  
Q
Q
Q
Q
Q
Q
Q
FF1  
FF2  
FF3  
FF4  
CD  
T
T
T
T
TCU TCD  
Q
CD  
CD  
CD  
MR  
Q0  
Q1  
Q2  
Q3  
001aak069  
Fig 2. Logic diagram  
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
5. Pinning information  
5.1 Pinning  
HEF40193B  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
D1  
Q1  
V
DD  
D0  
Q0  
MR  
TCD  
TCU  
PL  
CPD  
CPU  
Q2  
Q3  
D2  
V
SS  
D3  
001aae581  
Fig 3. Pin configuration  
5.2 Pin description  
Table 2.  
Symbol  
D0 to D3  
CPU  
Pin description  
Pin  
Description  
parallel data input  
15, 1, 10, 9  
5
count-up clock pulse input (LOW-to-HIGH, edge-triggered)  
count-down clock pulse input (LOW-to-HIGH, edge-triggered)  
parallel load input (active LOW)  
CPD  
4
PL  
11  
MR  
14  
master reset input (asynchronous)  
Q0 to Q3  
TCU  
3, 2, 6, 7  
buffered counter output  
12  
13  
16  
8
buffered terminal count-up (carry) output (active LOW)  
buffered terminal count-down (borrow) output (active LOW)  
supply voltage  
TCD  
VDD  
VSS  
ground supply voltage  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
4 of 19  
 
 
 
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
6. Functional description  
Table 3.  
Function table [1]  
MR  
H
L
PL  
X
CPU  
X
CPD  
X
Mode  
reset (asynchronous)  
parallel load  
count-up  
L
X
X
L
H
H
H
L
H
count-down  
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = positive-going transition.  
MR  
PL  
D0  
D1  
D2  
D3  
CPU  
CPD  
Q0  
Q1  
Q2  
Q3  
TCU  
TCD  
COUNT  
0
13  
14  
15  
0
1
2
1
0
15  
14  
13  
001aae586  
Fig 4. Timing diagram  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
5 of 19  
 
 
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
0
1
2
3
4
15  
14  
13  
12  
5
6
7
8
11  
10  
9
count up  
count down  
001aae584  
Logic equations for terminal count:  
TCU = Q0 Q1 Q2 Q3 CPU  
TCD = Q0 Q1 Q2 Q3 CPD  
Fig 5. State diagram  
7. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VDD  
IIK  
Parameter  
Conditions  
Min  
Max  
+18  
Unit  
V
supply voltage  
0.5  
input clamping current  
input voltage  
VI < 0.5 V or VI > VDD + 0.5 V  
VO < 0.5 V or VO > VDD + 0.5 V  
-
10  
mA  
V
VI  
0.5  
VDD + 0.5  
10  
IOK  
output clamping current  
input/output current  
supply current  
-
mA  
mA  
mA  
C  
II/O  
-
10  
IDD  
-
50  
Tstg  
Tamb  
Ptot  
storage temperature  
ambient temperature  
total power dissipation  
65  
+150  
+85  
40  
C  
[1]  
[2]  
DIP16 package  
SO16 package  
per output  
-
-
-
750  
mW  
mW  
mW  
500  
P
power dissipation  
100  
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.  
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.  
8. Recommended operating conditions  
Table 5.  
Symbol  
VDD  
Recommended operating conditions  
Parameter  
Conditions  
Min  
3
Typ  
Max  
Unit  
supply voltage  
input voltage  
-
-
-
15  
V
VI  
0
VDD  
+85  
V
Tamb  
ambient temperature  
in free air  
40  
C  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
6 of 19  
 
 
 
 
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
Table 5.  
Symbol  
t/V  
Recommended operating conditions …continued  
Parameter  
Conditions  
VDD = 5 V  
Min  
Typ  
Max  
3.75  
0.5  
Unit  
s/V  
s/V  
s/V  
input transition rise and fall rate  
-
-
-
-
-
-
VDD = 10 V  
VDD = 15 V  
0.08  
9. Static characteristics  
Table 6.  
Static characteristics  
VSS = 0 V; VI = VSS or VDD unless otherwise specified.  
Symbol Parameter  
Conditions  
VDD  
Tamb = 40 C Tamb = 25 C Tamb = 85 C Unit  
Min  
Max  
-
Min  
Max  
-
Min  
Max  
VIH  
HIGH-level input voltage  
|IO| < 1 A  
5 V  
10 V  
15 V  
5 V  
3.5  
3.5  
3.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
7.0  
-
7.0  
-
7.0  
11.0  
-
11.0  
-
11.0  
-
VIL  
LOW-level input voltage  
IO< 1 A  
-
1.5  
3.0  
4.0  
-
-
1.5  
3.0  
4.0  
-
-
1.5  
3.0  
4.0  
-
10 V  
15 V  
5 V  
-
-
-
-
-
-
VOH  
VOL  
IOH  
HIGH-level output voltage IO< 1 A  
4.95  
4.95  
4.95  
10 V  
15 V  
5 V  
9.95  
-
9.95  
-
9.95  
-
14.95  
-
14.95  
-
14.95  
-
LOW-level output voltage  
HIGH-level output current  
IO< 1 A  
-
0.05  
0.05  
0.05  
1.7  
0.52  
1.3  
3.6  
-
-
0.05  
0.05  
0.05  
1.4  
0.44  
1.1  
3.0  
-
-
0.05  
0.05  
0.05  
10 V  
15 V  
5 V  
-
-
-
-
-
-
VO = 2.5 V  
VO = 4.6 V  
VO = 9.5 V  
VO = 13.5 V  
VO = 0.4 V  
VO = 0.5 V  
VO = 1.5 V  
-
-
-
1.1 mA  
0.36 mA  
0.9 mA  
2.4 mA  
5 V  
-
-
-
10 V  
15 V  
5 V  
-
-
-
-
-
-
IOL  
LOW-level output current  
0.52  
0.44  
0.36  
-
-
-
mA  
mA  
mA  
10 V  
15 V  
15 V  
5 V  
1.3  
-
1.1  
-
0.9  
3.6  
-
3.0  
-
2.4  
II  
input leakage current  
supply current  
-
-
-
-
-
0.3  
20  
40  
80  
-
-
-
-
-
-
0.3  
20  
40  
80  
7.5  
-
-
-
-
-
1.0 A  
150 A  
300 A  
600 A  
IDD  
IO = 0 A  
10 V  
15 V  
-
CI  
input capacitance  
-
pF  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
7 of 19  
 
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
10. Dynamic characteristics  
Table 7.  
Dynamic characteristics  
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified.  
Symbol Parameter  
Conditions  
VDD  
5 V  
Extrapolation formula[1] Min  
Typ  
210  
85  
Max  
415  
165  
120  
425  
170  
125  
250  
100  
70  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPHL  
HIGH to LOW  
CPU to Qn;  
see Figure 6  
183 ns + (0.55 ns/pF)CL  
74 ns + (0.23 ns/pF)CL  
52 ns + (0.16 ns/pF)CL  
183 ns + (0.55 ns/pF)CL  
74 ns + (0.23 ns/pF)CL  
57 ns + (0.16 ns/pF)CL  
98 ns + (0.55 ns/pF)CL  
39 ns + (0.23 ns/pF)CL  
27 ns + (0.16 ns/pF)CL  
113 ns + (0.55 ns/pF)CL  
44 ns + (0.23 ns/pF)CL  
32 ns + (0.16 ns/pF)CL  
168 ns + (0.55 ns/pF)CL  
69 ns + (0.23 ns/pF)CL  
52 ns + (0.16 ns/pF)CL  
338 ns + (0.55 ns/pF)CL  
119 ns + (0.23 ns/pF)CL  
92 ns + (0.16 ns/pF)CL  
158 ns + (0.55 ns/pF)CL  
64 ns + (0.23 ns/pF)CL  
47 ns + (0.16 ns/pF)CL  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
propagation delay  
10 V  
15 V  
5 V  
60  
CPD to Qn;  
see Figure 6  
210  
85  
10 V  
15 V  
5 V  
60  
CPU to TCU;  
see Figure 6  
125  
50  
10 V  
15 V  
5 V  
35  
CPD to TCD;  
see Figure 6  
140  
55  
280  
110  
80  
10 V  
15 V  
5 V  
40  
MR to Qn;  
see Figure 6  
195  
80  
390  
160  
120  
730  
265  
205  
360  
150  
110  
10 V  
15 V  
5 V  
60  
MR to TCD  
365  
130  
100  
185  
75  
10 V  
15 V  
5 V  
PL Qn  
10 V  
15 V  
55  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
8 of 19  
 
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
Table 7.  
Dynamic characteristics …continued  
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified.  
Symbol Parameter  
Conditions  
VDD  
5 V  
Extrapolation formula[1] Min  
Typ  
170  
70  
50  
170  
70  
50  
95  
40  
30  
100  
40  
30  
145  
60  
45  
145  
60  
45  
60  
30  
20  
5
Max  
340  
140  
100  
340  
140  
100  
185  
80  
60  
195  
85  
65  
285  
115  
90  
290  
120  
90  
120  
60  
40  
-
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MHz  
MHz  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPLH  
LOW to HIGH  
CPU to Qn;  
see Figure 6  
143 ns + (0.55 ns/pF)CL  
59 ns + (0.23 ns/pF)CL  
42 ns + (0.16 ns/pF)CL  
143 ns + (0.55 ns/pF)CL  
59 ns + (0.23 ns/pF)CL  
42 ns + (0.16 ns/pF)CL  
68 ns + (0.55 ns/pF)CL  
29 ns + (0.23 ns/pF)CL  
22 ns + (0.16 ns/pF)CL  
73 ns + (0.55 ns/pF)CL  
29 ns + (0.23 ns/pF)CL  
22 ns + (0.16 ns/pF)CL  
118 ns + (0.55 ns/pF)CL  
49 ns + (0.23 ns/pF)CL  
37 ns + (0.16 ns/pF)CL  
118 ns + (0.55 ns/pF)CL  
49 ns + (0.23 ns/pF)CL  
37 ns + (0.16 ns/pF)CL  
10 ns + (1.00 ns/pF)CL  
9 ns + (0.42 ns/pF)CL  
6 ns + (0.28 ns/pF)CL  
-
propagation delay  
10 V  
15 V  
5 V  
-
-
CPD to Qn;  
see Figure 6  
-
10 V  
15 V  
5 V  
-
-
CPU to TCU;  
see Figure 6  
-
10 V  
15 V  
5 V  
-
-
CPD to TCD;  
see Figure 6  
-
10 V  
15 V  
5 V  
-
-
MR to TCU  
PL to Qn  
-
10 V  
15 V  
5 V  
-
-
-
10 V  
15 V  
5 V  
-
-
tt  
transition time  
see Figure 6  
-
10 V  
15 V  
5 V  
-
-
fmax  
maximum frequency see Figure 6  
2.5  
7
10 V  
15 V  
5 V  
14  
18  
75  
25  
20  
90  
35  
30  
60  
20  
15  
65  
35  
25  
45  
15  
10  
-
9
-
tW  
pulse width  
CPU or CPD LOW;  
minimum width;  
see Figure 6  
150  
50  
35  
180  
70  
60  
120  
45  
30  
125  
70  
50  
90  
35  
25  
-
10 V  
15 V  
5 V  
-
-
MR input HIGH;  
minimum width;  
see Figure 6  
-
10 V  
15 V  
5 V  
-
-
PL input LOW;  
minimum width;  
see Figure 6  
-
10 V  
15 V  
5 V  
-
-
trec  
recovery time  
MR input;  
see Figure 6  
-
10 V  
15 V  
5 V  
-
-
PL input  
see Figure 6  
-
10 V  
15 V  
-
-
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
9 of 19  
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
Table 7.  
Dynamic characteristics …continued  
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified.  
Symbol Parameter  
Conditions  
VDD  
5 V  
Extrapolation formula[1] Min  
Typ  
80  
Max  
Unit  
ns  
tsu  
set-up time  
hold time  
Dn to PL;  
see Figure 6  
160  
60  
-
-
-
-
-
-
10 V  
15 V  
5 V  
30  
ns  
50  
25  
ns  
th  
Dn to PL;  
see Figure 6  
+10  
+5  
70  
25  
20  
ns  
10 V  
15 V  
ns  
+5  
ns  
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).  
Table 8.  
Dynamic power dissipation PD  
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.  
Symbol Parameter  
VDD  
5 V  
Typical formula for PD (W)  
PD = 600 fi + (fo CL) VDD  
where:  
2
PD  
dynamic power dissipation  
fi = input frequency in MHz,  
fo = output frequency in MHz,  
CL = output load capacitance in pF,  
VDD = supply voltage in V,  
(fo CL) = sum of the outputs.  
2
2
10 V  
15 V  
PD = 2700 fi + (fo CL) VDD  
PD = 7500 fi + (fo CL) VDD  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
10 of 19  
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
11. Waveforms  
V
I
MR input  
0 V  
V
I
CPU or CPD  
input  
V
M
0 V  
t
t
PLH  
PHL  
V
I
TCU input  
TCD input  
Qn output  
0 V  
t
PHL  
V
I
0 V  
t
t
t
PHL  
PLH  
PHL  
V
OH  
90 %  
V
10 %  
M
V
OL  
t
t
t
t
001aak070  
a. Propagation delays and output transition times  
t
W
V
CPU or CPD  
input  
I
V
M
0 V  
t
t
rec  
W
V
I
PL input  
V
M
0 V  
t
t
h
su  
V
I
Dn input  
V
M
0 V  
t
W
t
rec  
V
I
MR input  
V
M
0 V  
001aae585  
b. PL and MR recovery times, CPU, CPD, PL and MR minimum pulse widths, and Dn to PL set-up and hold times  
VOH and VOL are typical output voltage levels that occur with the output load.  
Set-up and hold times are shown as positive values but may be specified as negative values.  
The shaded area is where the data can change for predictable performance.  
Measurement points are given in Table 9.  
Fig 6.  
Waveforms showing switching times  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
11 of 19  
 
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
t
W
V
I
90 %  
90 %  
negative  
pulse  
V
V
V
M
M
10 %  
10 %  
0 V  
t
t
r
f
t
t
f
r
V
I
90 %  
90 %  
positive  
pulse  
V
M
M
10 %  
10 %  
0 V  
t
W
001aaj781  
a. Input waveforms  
V
DD  
V
V
O
I
G
DUT  
C
L
R
T
001aag182  
b. Test circuit  
Test data is given in Table 9.  
Definitions for test circuit:  
CL = Load capacitance including jig and probe capacitance;  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
Fig 7. Test circuit for switching times  
Table 9.  
Measurement points and test data  
Supply voltage  
Input  
VI  
Load  
CL  
VM  
tr, tf  
5 V to 15 V  
VDD  
0.5VI  
20 ns  
50 pF  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
12 of 19  
 
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
12. Application information  
Some examples of applications for the HEF40193B are:  
• Up/down difference counting  
• Multistage ripple counting  
• Multistage synchronous counting  
D0 D1 D2 D3  
D0 D1 D2 D3  
clock up  
CARRY  
CPU  
CPD  
TCU  
TCD  
CPU  
CPD  
TCU  
TCD  
HEF40193B  
HEF40193B  
clock down  
BORROW  
Q0 Q1 Q2 Q3 MR PL  
Q0 Q1 Q2 Q3 MR PL  
MR  
PL  
001aae587  
Fig 8. Example of cascaded HEF40193B ICs  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
13 of 19  
 
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
13. Package outline  
DIP16: plastic dual in-line package; 16 leads (300 mil)  
SOT38-4  
D
M
E
A
2
A
A
1
L
c
e
w M  
Z
b
1
(e )  
1
b
b
2
16  
9
M
H
pin 1 index  
E
1
8
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
(1)  
A
A
A
2
(1)  
(1)  
Z
1
w
UNIT  
mm  
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.  
min.  
max.  
max.  
1.73  
1.30  
0.53  
0.38  
1.25  
0.85  
0.36  
0.23  
19.50  
18.55  
6.48  
6.20  
3.60  
3.05  
8.25  
7.80  
10.0  
8.3  
4.2  
0.51  
3.2  
2.54  
0.1  
7.62  
0.3  
0.254  
0.01  
0.76  
0.068 0.021 0.049 0.014  
0.051 0.015 0.033 0.009  
0.77  
0.73  
0.26  
0.24  
0.14  
0.12  
0.32  
0.31  
0.39  
0.33  
inches  
0.17  
0.02  
0.13  
0.03  
Note  
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
95-01-14  
03-02-13  
SOT38-4  
Fig 9. Package outline SOT38-4 (DIP16)  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
14 of 19  
 
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
SO16: plastic small outline package; 16 leads; body width 3.9 mm  
SOT109-1  
D
E
A
X
c
y
H
v
M
A
E
Z
16  
9
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
8
e
w
M
detail X  
b
p
0
2.5  
scale  
5 mm  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
10.0  
9.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.05  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.39  
0.014 0.0075 0.38  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.020  
0.028  
0.012  
inches  
0.069  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT109-1  
076E07  
MS-012  
Fig 10. Package outline SOT109-1 (SO16)  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
15 of 19  
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
14. Revision history  
Table 10. Revision history  
Document ID  
HEF40193B v.8  
Modifications:  
Release date  
20111118  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
HEF40193B v.7  
• Legal pages updated.  
• Changes in “General description” and “Features and benefits”.  
• Section “Applications” removed.  
HEF40193B v.7  
20110914  
20091222  
20090615  
20090505  
19950101  
19950101  
Product data sheet  
Product data sheet  
Product data sheet  
Product data sheet  
Product specification  
Product specification  
-
-
-
-
-
-
HEF40193B v.6  
HEF40193B v.5  
HEF40193B v.4  
HEF40193B_CNV v.3  
HEF40193B_CNV v.2  
-
HEF40193B v.6  
HEF40193B v.5  
HEF40193B v.4  
HEF40193B_CNV v.3  
HEF40193B_CNV v.2  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
16 of 19  
 
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
15. Legal information  
15.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of an NXP Semiconductors product can reasonably be expected  
15.2 Definitions  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
15.3 Disclaimers  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
17 of 19  
 
 
 
 
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
non-automotive qualified products in automotive equipment or applications.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
15.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
16. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
HEF40193B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 8 — 18 November 2011  
18 of 19  
 
 
HEF40193B  
NXP Semiconductors  
4-bit up/down binary counter  
17. Contents  
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 1  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
5
5.1  
5.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4  
6
Functional description . . . . . . . . . . . . . . . . . . . 5  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Recommended operating conditions. . . . . . . . 6  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Application information. . . . . . . . . . . . . . . . . . 13  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16  
7
8
9
10  
11  
12  
13  
14  
15  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
15.1  
15.2  
15.3  
15.4  
16  
17  
Contact information. . . . . . . . . . . . . . . . . . . . . 18  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2011.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 18 November 2011  
Document identifier: HEF40193B  
 

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