HEF4020BT [NXP]
14-stage binary counter; 14级二进制计数器
| 型号： | HEF4020BT |
| 厂家： | 
NXP |
| 描述： | 14-stage binary counter |
| 文件： | 总7页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4020B
MSI
14-stage binary counter
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4020B
MSI
14-stage binary counter
DESCRIPTION
The HEF4020B is a 14-stage binary ripple counter with a
clock input (CP), an overriding asynchronous master reset
input (MR) and twelve fully buffered outputs (O0, O3 to
O13). The counter advances on the HIGH to LOW
transition of CP. A HIGH on MR clears all counter stages
and forces all outputs LOW, independent of the state of
CP. Each counter stage is a static toggle flip-flop. A feature
of the HEF4020B is: high speed (typ. 35 MHz at
VDD = 15 V).
Fig.1 Functional diagram.
HEF4020BP(N):
16-lead DIL; plastic
(SOT38-1)
HEF4020BD(F):
HEF4020BT(D):
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
Fig.2 Pinning diagram.
CP
clock input (HIGH to LOW edge
triggered)
MR
master reset input (active HIGH)
parallel outputs
O0, O3 to O13
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4020B
MSI
14-stage binary counter
Fig.3 Logic diagram.
January 1995
3
Philips Semiconductors
Product specification
HEF4020B
MSI
14-stage binary counter
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
MAX.
Propagation delays
CP → Ο0
HIGH to LOW
5
105
45
30
105
50
35
80
30
20
70
25
20
180
90
70
60
30
20
60
30
20
25
15
10
65
50
45
60
35
25
10
25
35
210
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
78 ns + (0,55 ns/pF) CL
34 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
78 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
53 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
43 ns + (0,55 ns/pF) CL
14 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
153 ns + (0,55 ns/pF) CL
79 ns + (0,23 ns/pF) CL
62 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10
15
5
tPHL
tPLH
tPHL
tPLH
tPHL
tTHL
tTLH
65
210
95
LOW to HIGH
10
15
5
70
On → On + 1
160
60
HIGH to LOW
10
15
5
40
140
50
LOW to HIGH
10
15
5
40
MR → On
360
180
140
120
60
HIGH to LOW
10
15
5
Output transition times
HIGH to LOW
10
15
5
40
120
60
LOW to HIGH
10
15
5
40
Minimum clock
50
pulse width; HIGH
10
15
5
tWCPH
tWMRH
tRMR
25
20
130
95
90
115
65
55
5
Minimum MR
pulse width; HIGH
10
15
5
Recovery time
for MR
10
15
5
Maximum clock
pulse frequency
10
15
fmax
13
18
January 1995
4
Philips Semiconductors
Product specification
HEF4020B
MSI
14-stage binary counter
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
600 fi + ∑ (fo CL) × VDD
where
2
2 800 fi + ∑ (fo CL) × VDD
fi = input freq. (MHz)
2
8 200 fi + ∑ (fo CL) × VDD
fo = output freq. (MHz)
CL = load cap. (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
Fig.4 Waveforms showing propagation delays for MR to On and CP to O0, minimum MR and CP pulse widths.
January 1995
5
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Fig.5 Timing diagram.
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