HEF4025BTD [NXP]
Triple 3-input NOR gate; 三路3输入NOR门
| 型号： | HEF4025BTD |
| 厂家： | 
NXP |
| 描述： | Triple 3-input NOR gate |
| 文件： | 总3页 (文件大小：29K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4025B
gates
Triple 3-input NOR gate
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4025B
gates
Triple 3-input NOR gate
DESCRIPTION
The HEF4025B provides the positive triple 3-input NOR
function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
Fig.2 Pinning diagram.
HEF4025BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4025BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4025BT(D): 14-lead SO; plastic
(SOT108-1)
Fig.1 Functional diagram.
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4025B
gates
Triple 3-input NOR gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
TYP.
MAX.
Propagation delays
In → On
HIGH to LOW
5
70
25
20
60
25
15
60
30
20
60
30
20
135
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
43 ns
14 ns
12 ns
33 ns
14 ns
7 ns
+
+
+
+
+
+
+
+
+
+
+
+
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
10
15
5
tPHL
tPLH
tTHL
tTLH
40
120
50
LOW to HIGH
10
15
5
35
Output transition times
HIGH to LOW
120
60
10 ns
9 ns
10
15
5
40
6 ns
120
60
10 ns
9 ns
LOW to HIGH
10
15
40
6 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
900 fi + ∑ (foCL) × VDD
where
2
4000 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
10 900 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
V
DD = supply voltage (V)
January 1995
3
相关型号：
HEF4027BPB
IC 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, PLASTIC, DIP-16, FF/Latch
NXP
©2020 ICPDF网 联系我们和版权申明