HEF4027B [NXP]
Dual JK flip-flop; 双JK触发器
NXP 
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4027B
flip-flops
Dual JK flip-flop
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4027B
flip-flops
Dual JK flip-flop
DESCRIPTION
FUNCTION TABLES
INPUTS
The HEF4027B is a dual JK flip-flop which is
OUTPUTS
edge-triggered and features independent set direct
(SD), clear direct (CD), clock (CP) inputs and outputs
(O,O). Data is accepted when CP is LOW, and transferred
to the output on the positive-going edge of the clock. The
active HIGH asynchronous clear-direct (CD) and set-direct
(SD) are independent and override the J, K, and CP inputs.
The outputs are buffered for best system performance.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
SD
CD
CP
J
K
O
O
H
L
L
H
H
X
X
X
X
X
X
X
X
X
H
L
L
H
H
H
H
INPUTS
CP
OUTPUTS
SD
L
CD
L
J
L
K
L
On + 1
On + 1
no change
L
L
H
L
L
H
L
L
H
L
L
H
H
L
L
H
On
On
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
On + 1 = state after clock positive transition
PINNING
J,K
CP
SD
CD
O
synchronous inputs
clock input (L to H edge-triggered)
asynchronous set-direct input (active HIGH)
asynchronous clear-direct input (active HIGH)
true output
O
complement output
Fig.1 Functional diagram.
HEF4027BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4027BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4027BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category FLIP-FLOPS
See Family Specifications
Fig.2 Pinning diagram.
January 1995
2
Philips Semiconductors
Product specification
HEF4027B
flip-flops
Dual JK flip-flop
Fig.3 Logic diagram (one flip-flop).
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
MAX.
Propagation delays
CP → O, O
HIGH to LOW
5
10
15
5
105
40
30
85
35
30
70
30
25
120
45
35
140
55
40
210 ns
78 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
58 ns + (0,55 ns/pF) CL
27 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
43 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
93 ns + (0,55 ns/pF) CL
33 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
113 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
tPHL
tPLH
tPLH
tPHL
tPHL
80 ns
60 ns
170 ns
70 ns
60 ns
140 ns
60 ns
50 ns
240 ns
90 ns
70 ns
280 ns
110 ns
80 ns
LOW to HIGH
10
15
5
SD → O
LOW to HIGH
10
15
5
CD → O
HIGH to LOW
10
15
5
SD → O
HIGH to LOW
10
15
January 1995
3
Philips Semiconductors
Product specification
HEF4027B
flip-flops
Dual JK flip-flop
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
MAX.
150 ns
CD → O
5
10
15
5
75
35
25
60
30
20
60
30
20
25
10
5
48 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
LOW to HIGH
tPLH
70 ns
50 ns
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
ns
Output transition times
HIGH to LOW
10
15
5
tTHL
LOW to HIGH
10
15
5
tTLH
Set-up time
50
J,K → CP
10
15
5
tsu
30
20
25
20
15
80
30
24
90
40
30
20
15
10
4
ns
ns
Hold time
0
ns
J,K → CP
10
15
5
thold
0
ns
5
ns
Minimum clock
40
15
12
45
20
15
−15
−10
−5
8
ns
see also waveforms
Figs 4 and 5
pulse width; LOW
10
15
5
tWCPL
ns
ns
Minimum SD, CD
pulse width; HIGH
ns
tWSDH,
tWCDH
10
15
5
ns
ns
Recovery time
for SD, CD
ns
tRSD,
tRCD
10
15
5
ns
ns
Maximum clock
pulse frequency
J = K = HIGH
MHz
see also waveforms
Fig.4
10
15
fmax
12
15
25
30
MHz
MHz
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
900 fi + ∑ (foCL) × VDD
where
2
4 500 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
2
13 200 fi + ∑ (foCL) × VDD
V
DD = supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
HEF4027B
flip-flops
Dual JK flip-flop
Fig.4 Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are
shown as positive values but may be specified as negative values.
Fig.5 Waveforms showing recovery times for SD and CD; minimum SD and CD pulse widths.
APPLICATION INFORMATION
Some examples of applications for the HEF4027B are:
• Registers
• Counters
• Control circuits
January 1995
5
相关型号：
HEF4027BPB
IC 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, PLASTIC, DIP-16, FF/Latch
NXP
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