HEF4511BTD-T [NXP]
IC 4000/14000/40000 SERIES, SEVEN SEGMENT DECODER/DRIVER, TRUE OUTPUT, PDSO16, PLASTIC, SO-16, Decoder/Driver;型号: | HEF4511BTD-T |
厂家: | NXP |
描述: | IC 4000/14000/40000 SERIES, SEVEN SEGMENT DECODER/DRIVER, TRUE OUTPUT, PDSO16, PLASTIC, SO-16, Decoder/Driver 驱动 光电二极管 输出元件 逻辑集成电路 |
文件: | 总19页 (文件大小:153K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HEF4511B
BCD to 7-segment latch/decoder/driver
Rev. 06 — 7 December 2009
Product data sheet
1. General description
The HEF4511B is a BCD to 7-segment latch/decoder/driver with four address inputs
(D0 to D3), an active HIGH latch enable input (LE), an active LOW ripple blanking input
(BL), an active LOW lamp test input (LT), and seven active HIGH NPN bipolar transistor
segment outputs (Qa to Qg).
When LE is LOW and BL is HIGH, the state of the segment outputs (Qa to Qg) is
determined by the data on D0 to D3. When LE goes HIGH, the last data present on D0 to
D3 is stored in the latches and the segment outputs remain unchanged. When LT is LOW,
all of the segment outputs are HIGH independent of all other input conditions. With LT
HIGH, a LOW on BL forces all segment outputs LOW. The inputs LT and BL do not affect
the latch circuit.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is
also suitable for use over the industrial (−40 °C to +85 °C) and automotive (−40 °C to
+125 °C) temperature ranges.
2. Features
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the automotive temperature range −40 °C to +125 °C
Complies with JEDEC standard JESD 13-B
3. Applications
Automotive and industrial
4. Ordering information
Table 1.
Ordering information
All types operate from −40 °C to +125 °C.
Type number
Package
Name
Description
Version
HEF4511BP
HEF4511BT
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
SOT38-4
SOT109-1
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
5. Functional diagram
7
1
2
6
D0
D1
D2
D3
5
4
3
LE
LATCHES
DECODER
DRIVERS
BL
LT
Qg
14
Qf
15
Qe
9
Qd
10
Qc
11
Qb
12
Qa
13
001aae675
Fig 1. Functional diagram
V
DD
driver
logic
I
OH
+
V
OH
−
V
SS
001aae677
Fig 2. Schematic diagram of output stage
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
2 of 19
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D0
D1
D2
D3
BL
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
latch
1
latch
2
latch
3
latch
4
CP
CP
CP
CP
LE
LT
Qg
Qf
Qe
Qd
Qc
Qb
Qa
001aae679
Fig 3. Logic diagram
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
6. Pinning information
6.1 Pinning
HEF4511B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D1
D2
LT
BL
LE
D3
D0
V
DD
Qf
Qg
Qa
Qb
Qc
Qd
Qe
V
SS
001aae676
Fig 4. Pin configuration DIP16 and SO16
6.2 Pin description
Table 2.
Symbol
LT
Pin description
Pin
Description
3
lamp test input (active LOW)
ripple blanking input (active LOW)
latch enable input (active HIGH)
address (data) input
BL
4
LE
5
D0 to D3
VSS
7, 1, 2, 6
8
ground supply voltage
segment output
Qa to Qg
VDD
13, 12, 11, 10, 9, 15, 14
16
supply voltage
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
4 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
7. Functional description
Table 3.
Function table[1]
Inputs
Outputs
Display
LE
X
X
L
BL
X
LT
L
D3
X
X
L
D2
X
X
L
D1
X
X
L
D0
X
X
L
Qa
H
L
Qb
Qc
H
Qd
H
L
Qe
H
L
Qf
H
L
Qg
H
L
H
L
8
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
blank
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
L
H
L
H
L
L
0
L
L
L
L
H
L
H
L
1
L
L
L
H
H
L
H
H
L
L
H
H
L
H
L
L
H
H
H
H
H
L
2
L
L
L
H
L
H
L
3
L
L
H
H
H
H
L
H
L
H
H
H
L
4
L
L
L
H
L
H
L
H
H
H
L
L
5
L
L
H
H
L
L
H
H
L
6
L
L
H
L
H
H
H
L
H
H
H
L
H
7
L
H
H
H
H
X
H
H
L
H
L
H
H
L
H
H
L
8
L
L
L
H
X
X
X
H
9
L
L
H
X
X
L
L
L
blank
blank
N.C.
L
H
X
L
L
L
L
L
L
L
H
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; N.C. = no change.
a
g
f
b
e
c
d
001aaj494
Fig 5. Seven segment digital display with segment designation
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
5 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
−0.5
-
Max
+18
Unit
V
supply voltage
input clamping current
input voltage
VI < −0.5 V or VI > VDD + 0.5 V
VO < −0.5 V or VO > VDD + 0.5 V
±10
mA
V
VI
−0.5
-
VDD + 0.5
±10
IOK
output clamping current
input/output current
HIGH-level output current
supply current
mA
mA
mA
mA
°C
II/O
-
±10
[1]
IOH
−25
-
-
IDD
50
Tstg
Tamb
Ptot
storage temperature
ambient temperature
total power dissipation
−65
−40
+150
+125
°C
Tamb = 125 °C
DIP16 package
SO16 package
per output
[2]
[3]
-
-
-
750
500
100
mW
mW
mW
P
power dissipation
[1] A destructive high current mode may occur if VI and VO are not constrained to the range VSS ≤ VI or VO ≤ VDD
[2] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
.
[3] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
9. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
15
Unit
supply voltage
3
-
-
-
-
-
-
V
VI
input voltage
0
VDD
+125
3.75
0.5
V
Tamb
ambient temperature
input transition rise and fall rate
in free air
−40
°C
Δt/ΔV
VDD = 5 V
VDD = 10 V
VDD = 15 V
-
-
-
μs/V
μs/V
μs/V
0.08
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
6 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit
Min
Max
Min
Max
Min
Max
Min
Max
VIH
HIGH-level
input voltage
|IO| < 1 μA
|IO| < 1 μA
5 V
10 V
15 V
5 V
3.5
-
-
3.5
-
-
3.5
-
-
3.5
-
-
V
V
V
V
V
V
-
7.0
7.0
7.0
7.0
11.0
-
11.0
-
11.0
-
11.0
-
VIL
LOW-level
input voltage
-
-
-
-
1.5
3.0
4.0
-
-
-
-
-
1.5
3.0
4.0
-
-
-
-
-
1.5
3.0
4.0
-
-
-
-
-
1.5
3.0
4.0
-
10 V
15 V
-
VOH
VOL
HIGH-level
output voltage
see Table 7
LOW-level
output voltage
|IO| < 1 μA
5 V
10 V
15 V
5 V
-
-
0.05
-
0.05
-
-
0.05
-
-
0.05
V
0.05
-
0.05
0.05
0.05
V
-
0.05
-
0.05
-
0.05
-
0.05
V
IOH
HIGH-level
output current
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
−1.7
−0.64
−1.6
−4.2
0.64
1.6
4.2
-
-
−1.4
−0.5
−1.3
−3.4
0.5
1.3
3.4
-
-
−1.1
−0.36
−0.9
−2.4
0.36
0.9
2.4
-
-
−1.1
−0.36
−0.9
−2.4
0.36
0.9
2.4
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
5 V
-
-
-
10 V
-
-
-
VO = 13.5 V 15 V
-
-
-
IOL
LOW-level
output current
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
5 V
10 V
15 V
15 V
-
-
-
-
-
-
-
-
-
II
input leakage
current
±0.1
±0.1
±1.0
±1.0 μA
IDD
supply current IO = 0 A
5 V
10 V
15 V
-
-
-
-
-
5
10
20
-
-
-
-
-
5
-
-
-
-
150
300
600
-
-
-
-
-
150
300
600
-
μA
μA
μA
pF
10
20
7.5
CI
input
capacitance
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
7 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
Table 7.
Static characteristics for VOH
VSS = 0 V.
Symbol Parameter
IOH
mA
0
VDD
V
Tamb = −40 °C
Tamb = +25 °C
Tamb = +85 °C
Tamb = +125 °C Unit
Min
Min
4.10
9.10
Typ
4.40
9.90
Min
Min
VOH
HIGH-level
5 V
4.10
4.10
4.10
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
output voltage
10 V
15 V
5 V
9.10
9.10
9.10
14.10
14.10 14.40
14.10
14.10
5
10
15
20
25
-
-
4.30
9.30
-
-
10 V
15 V
5 V
-
-
-
-
-
-
14.30
4.25
-
-
3.60
3.60
8.75
3.30
3.20
10 V
15 V
5 V
8.75
9.25
8.45
8.35
13.75
13.75 14.30
13.45
13.35
-
-
4.20
9.20
-
-
10 V
15 V
5 V
-
-
-
-
-
-
14.20
4.20
-
-
2.80
2.80
8.10
2.50
2.30
10 V
15 V
5 V
8.10
9.20
7.80
7.60
13.10
13.10 14.20
12.80
12.60
-
-
-
-
-
-
4.15
9.20
-
-
-
-
-
-
10 V
15 V
14.20
11. Dynamic characteristics
Table 8.
Dynamic characteristics
VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula[1]
128 ns + (0.55 ns/pF)CL
49 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
133 ns + (0.55 ns/pF)CL
49 ns + (0.23 ns/pF)CL
37 ns + (0.16 ns/pF)CL
93 ns + (0.55 ns/pF)CL
39 ns + (0.23 ns/pF)CL
27 ns + (0.16 ns/pF)CL
52 ns + (0.55 ns/pF)CL
19 ns + (0.23 ns/pF)CL
12 ns + (0.16 ns/pF)CL
Min
Typ
Max
310
120
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPHL
HIGH to LOW
Dn → Qn;
see Figure 6
-
-
-
-
-
-
-
-
-
-
-
-
155
60
propagation delay
10 V
15 V
5 V
40
LE → Qn;
see Figure 6
160
60
320
120
90
10 V
15 V
5 V
45
BL → Qn;
see Figure 6
120
50
240
100
70
10 V
15 V
5 V
35
LT → Qn;
see Figure 6
80
160
60
10 V
15 V
30
20
40
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
8 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
Table 8.
Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula[1]
108 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
133 ns + (0.55 ns/pF)CL
59 ns + (0.23 ns/pF)CL
42 ns + (0.16 ns/pF)CL
78 ns + (0.55 ns/pF)CL
29 ns + (0.23 ns/pF)CL
22 ns + (0.16 ns/pF)CL
33 ns + (0.55 ns/pF)CL
19 ns + (0.23 ns/pF)CL
17 ns + (0.16 ns/pF)CL
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
20 ns + (1.00 ns/pF)CL
13 ns + (0.06 ns/pF)CL
10 ns + (0.06 ns/pF)CL
Min
Typ
135
55
40
160
70
50
105
40
30
60
30
25
60
30
20
25
16
13
25
12
9
Max
270
110
80
320
140
100
210
80
60
120
60
50
120
60
40
50
32
26
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPLH
LOW to HIGH
Dn → Qn;
see Figure 6
-
propagation delay
10 V
15 V
5 V
-
-
LE → Qn;
see Figure 6
-
10 V
15 V
5 V
-
-
BL → Qn;
see Figure 6
-
10 V
15 V
5 V
-
-
LT → Qn;
see Figure 6
-
10 V
15 V
5 V
-
-
tTHL
tTLH
tsu
HIGH to LOW output see Figure 6
transition time
-
10 V
15 V
5 V
-
-
LOW to HIGH output see Figure 6
transition time
-
10 V
15 V
5 V
-
-
set-up time
hold time
Dn → LE;
see Figure 7
50
25
20
60
30
25
80
40
35
10 V
15 V
5 V
-
-
th
Dn → LE;
see Figure 7
30
15
12
40
20
17
-
10 V
15 V
5 V
-
-
tW
pulse width
LE input LOW;
minimum width;
see Figure 7
-
10 V
15 V
-
-
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 9.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (μW)
PD = 1000 × fi + Σ(fo × CL) × VDD
PD = 4000 × fi + Σ(fo × CL) × VDD
where:
2
2
PD
dynamic power
dissipation
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
10 V
15 V
2
PD = 10000 × fi + Σ(fo × CL) × VDD
VDD = supply voltage in V;
Σ(fo × CL) = sum of the outputs.
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
9 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
12. Waveforms
V
I
LE
D2
LT
BL
V
V
M
M
V
V
V
V
SS
V
I
V
M
SS
V
I
SS
t
PHL
V
I
V
M
SS
t
t
t
t
PLH
PLH
PLH
PLH
t
t
t
PHL
PHL
PHL
V
OH
90 %
THL
V
Qg
M
10 %
V
OL
t
t
TLH
001aaj495
Conditions: D3 = LOW and D0 = D1 = HIGH.
Measurement points are given in Table 10.
Fig 6. Propagation delays and output transition times
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
10 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
V
I
V
M
LE input
V
SS
t
W
V
I
V
M
D2 input
V
SS
t
su
t
h
V
OH
Qg output
V
OL
001aae682
The shaded area indicates where the input is permitted to change for predictable output performance.
Conditions: D3 = LOW and D0 = D1 = BL = LT = HIGH.
Measurement points are given in Table 10.
Fig 7. Waveforms showing minimum LE pulse width, set-up, and hold time for Dn to LE
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
11 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
0 V
t
t
r
f
t
r
t
f
V
I
90 %
positive
pulse
M
M
10 %
0 V
t
W
001aaj781
a. Input waveforms
V
DD
V
I
V
O
G
DUT
C
L
R
T
001aag182
b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 8. Test circuit for measuring switching times
Table 10. Measurement points and test data
Supply voltage
Input
VI
Load
CL
VM
tr, tf
5 V to 15 V
VDD
0.5VI
≤ 20 ns
50 pF
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
12 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
13. Application information
• Driving LED displays
• Driving incandescent displays
• Driving fluorescent displays
• Driving LCD displays
• Driving gas discharge displays
common anode
LED
V
DD
V
DD
≈ 1.7 V
common cathode
LED
≈ 1.7 V
V
SS
V
SS
001aae683
001aae684
Fig 9. Connection to common cathode LED display
readout
Fig 10. Connection to common anode LED display
readout
V
DD
V
DD
V
DD
direct
(low brightness)
(1)
to
filament
supply
V
SS
V
SS
V
SS
001aae685
001aae686
(1) A filament pre-warm resistor is recommended to
reduce filament thermal shock and increase the effective
cold resistance of the filament.
Fig 11. Connection to incandescent display readout
Fig 12. Connection to fluorescent display readout
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
13 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
exitation
appropriate
voltage
V
DD
V
DD
(square wave;
V
V
SS to DD)
1/4 HEF4070B
V
SS
V
SS
001aae687
001aae688
Direct DC drive of LCDs not recommended for life of
LCD readouts.
Fig 13. Connection to gas discharge display readout
Fig 14. Connection to LCD readout
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
14 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
14. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 15. Package outline SOT38-4 (DIP16)
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
15 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 16. Package outline SOT109-1 (SO16)
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
16 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
15. Revision history
Table 11. Revision history
Document ID
HEF4511B_6
Release date
20091207
Data sheet status
Change notice
Supersedes
Product data sheet
-
HEF4511B_5
Modifications:
• Section 9 “Recommended operating conditions”: Δt/ΔV values updated.
HEF4511B_5
20090813
20090305
19950101
19950101
Product data sheet
Product data sheet
Product specification
Product specification
-
-
-
-
HEF4511B_4
HEF4511B_CNV_3
HEF4511B_CNV_2
-
HEF4511B_4
HEF4511B_CNV_3
HEF4511B_CNV_2
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
17 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4511B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 7 December 2009
18 of 19
HEF4511B
NXP Semiconductors
BCD to 7-segment latch/decoder/driver
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Application information. . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 December 2009
Document identifier: HEF4511B_6
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