ISP1161BD_技术文档

ISP1161

Full-speed Universal Serial Bus single-chip host and device

controller

Rev. 01 — 3 July 2001

Product data

1. General description

The ISP1161 is a single-chip Universal Serial Bus (USB) Host Controller (HC) and

Device Controller (DC) which complies with Universal Serial Bus Speciﬁcation

Rev 1.1. These two USB controllers, the HC and the DC, share the same

microprocessor bus interface. They have the same data bus, but different I/O

locations. They also have separate interrupt request output pins, separate DMA

channels that include separate DMA request output pins and DMA acknowledge

input pins. This makes it possible for a microprocessor to control both the USB HC

and the USB DC at the same time.

ISP1161 provides two downstream ports for the USB HC and one upstream port for

the USB DC. Each downstream port has its own overcurrent (OC) detection input pin

and power supply switching control output pin. The upstream port has its own V_BUS

detection input pin. ISP1161 also provides separate wakeup input pins and

suspended status output pins for the USB HC and the USB DC, respectively. This

makes power management ﬂexible. The downstream ports for the HC can be

connected with any USB compliant USB devices and USB hubs that have USB

upstream ports. The upstream port for the DC can be connected to any USB

compliant USB host and USB hubs that have USB downstream ports.

c

The DC is compliant with most device class speciﬁcations such as Imaging Class,

Mass Storage Devices, Communication Devices, Printing Devices and Human

Interface Devices.

c

ISP1161 is well suited for embedded systems and portable devices that require a

USB host only, a USB device only, or a combined and conﬁgurable USB host and

USB device capabilities. ISP1161 brings high ﬂexibility to the systems that have it

built-in. For example, a system that has ISP1161 built-in allows it not only to be

connected to a PC or USB hub that has a USB downstream port, but also to be

connected to a device that has a USB upstream port such as a USB printer, USB

camera, USB keyboard, USB mouse, among others. ISP1161 enables peer-to-peer

connectivity between embedded systems. An interesting application example is to

connect a ISP1161 HC with a ISP1161 DC.

Let us see an example of ISP1161 being used in a Digital Still Camera (DSC) design.

Figure 1 shows ISP1161 being used as a USB DC. Figure 2 shows ISP1161 being

used as a USB HC. Figure 3 shows ISP1161 being used as a USB HC and a USB

DC at the same time.

ISP1161

Full-speed USB single-chip host and device controller

Philips Semiconductors

EMBEDDED SYSTEM

µP SYSTEM

MEMORY

µP

µP bus I/F

PC

(host)

ISP1161

HOST/

DEVICE

USB cable

USB I/F

USB device

DSC

MGT926

Fig 1. ISP1161 operating as a USB device.

EMBEDDED SYSTEM

µP SYSTEM

MEMORY

µP

µP bus I/F

PRINTER

(device)

ISP1161

HOST/

DEVICE

USB cable

USB I/F

USB host

DSC

MGT927

Fig 2. ISP1161 operating as a stand-alone USB host.

9397 750 08313

Product data

Rev. 01 — 3 July 2001

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ISP1161

Full-speed USB single-chip host and device controller

Philips Semiconductors

EMBEDDED SYSTEM

µP SYSTEM

MEMORY

µP

µP bus I/F

PC

(host)

PRINTER

(device)

DSC

ISP1161

HOST/

DEVICE

USB cable

USB I/F

USB device

USB host

MGT928

Fig 3. ISP1161 operating as both USB host and device simultaneously.

2. Features

■ Complies with Universal Serial Bus Speciﬁcation Rev 1.1

■ Combines HC and DC in a single chip

■ On-chip DC complies with most Device Class speciﬁcations

■ Both HC and DC can be accessed by an external microprocessor via separate I/O

port addresses

■ Selectable one or two downstream ports for HC and one upstream port for DC

■ High speed parallel interface to most of the generic microprocessors and

Reduced Instruction Set Computer (RISC) processors (Hitachi SH-3 and SH-4,

MIPS-based RISC, ARM7/9, StrongARM, etc.). Maximum 15 Mbyte/s data

transfer rate between microprocessor and the HC, 11.1 Mbyte/s data transfer rate

between microprocessor and the DC

■ Supports single-cycle burst mode and multiple-cycle burst mode DMA operations

■ Up to 14 programmable USB endpoints with 2 ﬁxed control IN/OUT endpoints for

the DC

■ Built in separate FIFO buffer RAM for HC (4 kbytes) and DC (2462 bytes)

■ Endpoints with double buffering to increase throughput and ease real-time data

transfer for both DC transfers and HC isochronous (ISO) transactions

■ 6 MHz crystal oscillator with integrated PLL for low EMI

■ Controllable LazyClock (24 kHz) output during ‘suspend’

■ Clock output with programmable frequency (3 to 48 MHz)

■ Software controlled connection to the USB bus (SoftConnect) on upstream port

for the DC

■ Good USB connection indicator that blinks with trafﬁc (GoodLink) for the DC

■ Built-in software selectable internal 15 kΩ pull-down resistors for HC downstream

ports

■ Dedicated pins for suspend sensing output and wakeup control input for ﬂexible

applications

■ Global hardware reset input pin and separate internal software reset circuits for

HC and DC

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ISP1161

Full-speed USB single-chip host and device controller

Philips Semiconductors

■ Operation at either +5 V or +3.3 V power supply input

■ 8 kV in-circuit ESD protection

■ Operating temperature range −40 to +85 °C

■ Available in two LQFP64 packages (SOT314-2 and SOT414-1).

3. Applications

■ Personal Digital Assistant (PDA)

■ Digital camera

■ Third-generation (3-G) phone

■ Set-top box (STB)

■ Information Appliance (IA)

■ Photo printer

■ MP3 jukebox

■ Game console.

4. Ordering information

Table 1: Ordering information

Type number

Package

Name

Description

Version

ISP1161BD

ISP1161BM

LQFP64

Plastic low proﬁle quad ﬂat package; 64 leads; body 10 x 10 x 1.4 mm

Plastic low proﬁle quad ﬂat package; 64 leads; body 7 x 7 x 1.4 mm

SOT314-2

SOT414-1

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ISP1161

Full-speed USB single-chip host and device controller

Philips Semiconductors

POWER-ON

RESET

Memory block

Philips sHC core

USB Interface

USB

ATL RAM

STATE

clock

recovery

ITL0 RAM ITL1 RAM

µP interface

DMA

HANDLER

PHILIPS

SIE

FRAME

MANAGE-

MENT

MEMORY

MANAGEMENT

UNIT

Host

bus I/F

USB bus

REGISTER

ACCESS

H_DP1

H_DM1

H_DP2

H_DM2

µP

HANDLER

PDT_LIST

PROCESS

USB

TRANSCEIVER

Host controller sub-blocks

MGT930

Fig 5. Host controller sub block diagram.

3.3 V

POWER-ON

RESET

SoftConnect

INTEGRATED

RAM

DMA HANDLER

USB bus

D_DP

D_DM

Device

bus I/F

MEMORY

MANAGEMENT UNIT

USB

TRANSCEIVER

µP HANDLER

PHILIPS SIE

BUS I/F

clock recovery

EP HANDLER

GoodLink

Device controller sub-blocks

MGT931

Fig 6. Device controller sub block diagram.

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ISP1161

Full-speed USB single-chip host and device controller

Philips Semiconductors

6. Pinning information

6.1 Pinning

DGND

D2

1

2

3

4

5

6

7

8

9

48 D_DM

H_PSW2

47

D3

46 H_PSW1

45 DGND

44 XTAL2

D4

D5

D6

43

42

XTAL1

D7

H_SUSPEND

DGND

D8

41 CLKOUT

ISP1161BD

ISP1161BM

40

39

38

H_WAKEUP

D_VBUS

GL

D9 10

D10 11

D11 12

37 D_WAKEUP

D12

D13

D_SUSPEND

DGND

13

14

15

16

36

35

34

33

DGND

D14

EOT

NDP_SEL

MGT932

Fig 7. Pin conﬁguration LQFP64.

6.2 Pin description

Table 2: Pin description for LQFP64

Symbol^[1]

DGND

D2

1

Type

-

Description

digital ground

2

I/O

bit 2 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D3

D4

D5

3

4

5

I/O

bit 3 of bidirectional data; slew-rate controlled; TTL input;

three-state output

bit 4 of bidirectional data; slew-rate controlled; TTL input;

three-state output

bit 5 of bidirectional data; slew-rate controlled; TTL input;

three-state output

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ISP1161

Full-speed USB single-chip host and device controller

Philips Semiconductors

Table 2: Pin description for LQFP64 …continued

Symbol^[1]

Type

Description

D6

6

I/O

bit 6 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D7

7

I/O

bit 7 of bidirectional data; slew-rate controlled; TTL input;

three-state output

DGND

D8

8

9

-

digital ground

I/O

bit 8 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D9

10

11

12

13

14

I/O

bit 9 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D10

D11

D12

D13

bit 10 of bidirectional data; slew-rate controlled; TTL input;

three-state output

bit 11 of bidirectional data; slew-rate controlled; TTL input;

three-state output

bit 12 of bidirectional data; slew-rate controlled; TTL input;

three-state output

bit 13 of bidirectional data; slew-rate controlled; TTL input;

three-state output

DGND

D14

15

16

-

digital ground

I/O

bit 14 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D15

17

I/O

bit 15 of bidirectional data; slew-rate controlled; TTL input;

three-state output

DGND

V_hold1

18

19

-

digital ground

voltage holding pin; this pin is internally connected to the

V_reg(3.3)and V_hold2pins. When the V_CCpin is connected to

+5 V, this pin will output 3.3 V, hence it should not be

connected to +5 V. When the V_CCpin is connected to

+3.3 V, this pin can either be connected to +3.3 V or left

unconnected. In all cases this pin should be decoupled to

DGND.

n.c.

CS

20

21

22

23

24

-

I

-

no connection

chip select input

read strobe input

write strobe input

RD

WR

V_hold2

voltage holding pin; this pin is internally connected to the

V_reg(3.3)and V_hold1pins. When the V_CCpin is connected to

+5 V, this pin will output 3.3 V, hence it should not be

connected to +5 V. When the V_CCpin is connected to

+3.3 V, this pin can either be connected to +3.3 V or left

unconnected. In all cases this pin should be decoupled to

DGND.

DREQ1

25

O

HC’s DMA request output (programmable polarity); signals

to the DMA controller that the ISP1161 wants to start a

DMA transfer; see HcHardwareConﬁguration register

(20H/A0H)

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ISP1161

Full-speed USB single-chip host and device controller

Philips Semiconductors

Table 2: Pin description for LQFP64 …continued

Symbol^[1]

Type

Description

DREQ2

26

O

DC’s DMA request output (programmable polarity); signals

to the DMA controller that the ISP1161 wants to start a

DMA transfer; see DC’s hardware conﬁguration register

(BAH/BBH)

DACK1

DACK2

INT1

27

28

29

I

HC’s DMA acknowledge input. Active level programmable.

See the HcHardwareConﬁguration register (20H/A0H)

I

DC’s DMA acknowledge input. Active level programmable.

See DC’s hardware conﬁguration register (BAH/BBH)

O

HC’s interrupt output; programmable level, edge triggered

and polarity; see HcHardwareConﬁguration register (20H,

A0H)

INT2

30

O

DC’s interrupt output; programmable level, edge triggered

and polarity; see DC’s hardware conﬁguration register

(BAH, BBH)

TEST

31

32

O

I

Test output; this pin is used for test purposes only.

RESET

reset input (Schmitt trigger); a LOW level produces an

asynchronous reset

NDP_SEL

33

I

number of downstream ports:

0 — select 1 downstream port

1 — select 2 downstream ports

only changes the value of the NDP ﬁeld in the

HcRhDescriptorA register; there will always be two ports

present in the UsbSlaveHost

EOT

34

35

DMA master device to inform ISP1161 of end of DMA

transfer (Active level is programmable), see

HcHardwareConﬁguration register (20H/A0H)

DGND

-

digital ground

D_SUSPEND 36

O

DC’s suspend’ state indicator output; active level

programmable

D_WAKEUP

GL

37

38

I

DC’s wake-up input (edge triggered); a LOW-to-HIGH

transition generates a remote wake-up from ‘suspend’

state

O

GoodLink LED indicator output (open-drain); the LED is

default ON, blinks OFF upon USB trafﬁc; blinking can be

disabled by setting bit 1 of MODE register to a 1

D_VBUS

39

40

I

DC’s USB upstream port V_BUSsensing input

H_WAKEUP

HC’s wake-up input (edge triggered); a LOW-to-HIGH

transition generates a remote wake-up from ‘suspend’

state

CLKOUT

41

O

programmable clock output (3 to 48 MHz); default 12 MHz

H_SUSPEND 42

HC’s suspend’ state indicator output; active level

programmable

XTAL1 43

I

crystal oscillator input (6 MHz); connect a fundamental

mode or third-overtone, parallel-resonant crystal or an

external clock source (leaving pin XTAL2 unconnected)

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ISP1161

Full-speed USB single-chip host and device controller

Philips Semiconductors

Table 2: Pin description for LQFP64 …continued

Symbol^[1]

Type

Description

XTAL2

44

O

crystal oscillator output (6 MHz); connect a fundamental

mode or third-overtone, parallel-resonant crystal; leave this

pin open when using an external clock source on pin

XTAL1

DGND

45

46

-

digital ground

H_PSW1

O

power switching control output for downstream port 1; open

drain output

H_PSW2

47

O

power switching control output for downstream port 2; open

drain output

D_DM

D_DP

48

49

50

51

52

53

54

55

56

AI/O

I

USB D- data line for DC’s upstream port

USB D+ data line for DC’s upstream port

H_DM1

H_DP1

H_DM2

H_DP2

H_OC1

H_OC2

V_CC

USB D- data line for HC’s downstream port 1

USB D+ data line for HC’s downstream port 1

USB D- data line for HC’s downstream port 2

USB D+ data line for HC’s downstream port 2

overcurrent sensing input for HC’s downstream port 1

overcurrent sensing input for HC’s downstream port 2

I

-

digital power supply voltage input (3.0 to 3.6 V or

4.75 to 5.25 V). This pin connects to the internal 3.3 V

regulator input. When connected to +5 V, the internal

regulator will output 3.3 V to pins V_reg(3.3), V_hold1and V_hold2

When connected to 3.3 V, it will bypass the internal

regulator.

.

AGND

57

58

-

analog ground

V_reg(3.3)

internal 3.3 V regulator output; When the V_CCpin is

connected to +5 V, this pin outputs 3.3 V. When the V_CCpin

is connected to +3.3 V, then this pin should also be

connected to +3.3 V.

A0

A1

59

60

I

address input; selects command (A0 = 1) or data (A0 = 0)

address input; selects AutoMux switching to DC (A1 = 1) or

AutoMux switching to HC (A1 = 0); see Table 3

n.c.

61

62

63

-

no connection

digital ground

DGND

D0

-

I/O

bit 0 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D1

64

I/O

bit 1 of bidirectional data; slew-rate controlled; TTL input;

three-state output

[1] Symbol names with an overscore (e.g. NAME) represent active LOW signals.

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ISP1161

Full-speed USB single-chip host and device controller

Philips Semiconductors

7. Functional description

7.1 PLL clock multiplier

A 6 to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This

allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external

components are required for the operation of the PLL.

7.2 Bit clock recovery

The bit clock recovery circuit recovers the clock from the incoming USB data stream

using a 4× over-sampling principle. It is able to track jitter and frequency drift as

speciﬁed by the USB Speciﬁcation Rev. 1.1.

7.3 Analog transceivers

Three sets of transceiver are embedded in the chip: two are used for downstream

ports with USB connector type A; one is used for upstream port with USB connector

type B.The integrated transceivers are compliant with the Universal Serial Bus

Speciﬁcation Rev 1.1. They interface directly with the USB connectors and cables

through external termination resistors.

7.4 Philips Serial Interface Engine (SIE)

The Philips SIE implements the full USB protocol layer. It is completely hardwired for

speed and needs no ﬁrmware intervention. The functions of this block include:

synchronization pattern recognition, parallel/serial conversion, bit (de)stufﬁng, CRC

checking/generation, Packet IDentiﬁer (PID) veriﬁcation/generation, address

recognition, handshake evaluation/generation. There are separate SIE in both the HC

and the DC.

7.5 SoftConnect (in DC)

The connection to the USB is accomplished by bringing D+ (for high-speed USB

devices) HIGH through a 1.5 kΩ pull-up resistor. In the ISP1161 the 1.5 kΩ pull-up

resistor is integrated on-chip and is not connected to V_CCby default. The connection

is established through a command sent by the external/system microcontroller. This

allows the system microcontroller to complete its initialization sequence before

deciding to establish connection with the USB. Re-initialization of the USB connection

can also be performed without disconnecting the cable.

The ISP1161 DC will check for USB V_BUSavailability before the connection can be

established. V_BUSsensing is provided through pin D_VBUS.

Remark: Note that the tolerance of the internal resistors is 25%. This is higher than

the 5% tolerance speciﬁed by the USB speciﬁcation. However, the overall V_SEvoltage

speciﬁcation for the connection can still be met with a good margin. The decision to

make use of this feature lies with the USB equipment designer.

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ISP1161

Full-speed USB single-chip host and device controller

Philips Semiconductors

7.6 GoodLink (in DC)

Indication of a good USB connection is provided at pin GL through GoodLink

technology. During enumeration the LED indicator will blink on momentarily. When

the ISP1161 has been successfully enumerated (the device address is set), the LED

indicator will remain permanently on. Upon each successful packet transfer (with

ACK) to and from the ISP1161 the LED will blink off for 100 ms. During ‘suspend’

state the LED will remain off.

This feature provides a user-friendly indicator of the status of the USB device, the

connected hub and the USB trafﬁc. It is a useful ﬁeld diagnostics tool for isolating

faulty equipment. It can therefore help to reduce ﬁeld support and hotline overhead.

7.7 Suspend and wakeup (in DC)

ISP1161’s DC also can be put into suspended state by toggling bit 5, GOSUSP, of the

Mode Register. Pin D_SUSPEND is used for the DC’s suspended state sensing

output. The polarity of D_SUSPEND pin can be changed by setting bit 2, PWROFF,

of the Hardware Conﬁguration Register.

GOSUSP

WAKEUP

2 ms

0.5 ms

SUSPEND

MGS782

Fig 8. ISP1161 DC’s suspend and wakeup.

There are some ways to resume ISP1161’s DC from the suspended state:

By USB host, drivers a K-state on the USB bus (global resume)

By pin D_WAKEUP or CS.

•

Figure 8 shows the timing relationship for DC going into suspended state, and

resuming from the suspended state.

8. Microprocessor bus interface

8.1 I/O addressing mode

ISP1161 provides I/O addressing mode for external microprocessors to access its

internal control registers and FIFO buffer RAM. I/O addressing mode has the

advantage of reducing the pin count for address lines and so occupying less

microprocessor resources. ISP1161 uses only two address lines: A1 and A0 to

access the internal control registers and FIFO buffer RAM. Therefore, ISP1161

occupies only four I/O ports or four memory locations of a microprocessor. External

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ISP1161

Full-speed USB single-chip host and device controller

Philips Semiconductors

microprocessors can read or write ISP1161’s internal control registers and FIFO

buffer RAM through the parallel I/O (PIO) operating mode. Figure 9 shows the parallel

I/O interface between a microprocessor and ISP1161.

µP bus I/F

[

]

[

]

D 15:0

RD

WR

CS

A1

RD

WR

CS

A2

MICRO-

PROCESSOR

ISP1161

A0

A1

INT1

INT2

IRQ1

IRQ2

MGT933

Fig 9. Parallel I/O interface between microprocessor and ISP1161.

8.2 DMA mode

ISP1161 also provides DMA mode for external microprocessors to access its internal

FIFO buffer RAM. Data can be transferred by DMA operation between a

microprocessor’s system memory and ISP1161’s internal FIFO buffer RAM. Note: the

DMA operation must be controlled by the external microprocessor system’s DMA

controller (Master). Figure 10 shows the DMA interface between a microprocessor

system and ISP1161. ISP1161 provides two DMA channels: DMA channel 1

(controlled by DREQ1, DACK1 signals) is for the DMA transfer between a

microprocessor’s system memory and ISP1161 HC’s internal FIFO buffer RAM. DMA

channel 2 (controlled by DREQ2, DACK2 signals) is for the DMA transfer between a

microprocessor’s system memory and ISP1161 DC’s internal FIFO buffer RAM. The

EOT signal is an external end-of-transfer signal used to terminate the DMA transfer.

Some microprocessors may not have this signal. In this case, ISP1161 provides an

internal EOT signal to terminate the DMA transfer as well. Setting the

HcDMAConﬁguration register (21H - Read, A1H - Write) enables ISP1161’s HC

internal DMA counter for DMA transfer. When the DMA counter reaches the value

that is set in the HcTransferCounter (22H - Read, A2H - Write) register to be used as

the byte count of the DMA transfer, the internal EOT signal will be generated to

terminate the DMA transfer.

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ISP1161

Full-speed USB single-chip host and device controller

Philips Semiconductors

µP bus I/F

[

]

[

]

D 15:0

RD

WR

MICRO-

PROCESSOR

DACK1

DREQ1

DACK1

DREQ1

ISP1161

DACK2

DREQ2

DACK2

DREQ2

EOT

MGT934

Fig 10. DMA interface between microprocessor and ISP1161.

8.3 Microprocessor read/write ISP1161’s internal control registers by

PIO mode

8.3.1 I/O port addressing

Table 3 shows ISP1161’s I/O port addressing. Complete decoding of the I/O port

address should include the chip select signal CS and the address lines A1 and A0.

However, the direction of the access of the I/O ports is controlled by the RD and WR

signals. When RD is LOW, the microprocessor reads data from ISP1161’s data port.

When WR is LOW, the microprocessor writes a command to the command port, or

writes data to the data port.

Table 3: I/O port addressing

Port

CS

[A1:A0]

(Bin)

Access

Data bus width

(bits)

Description

0

1

2

3

0

00

01

10

11

R/W

W

16

HC data port

HC command port

DC data port

R/W

W

DC command port

Figure 11 and Figure 12 illustrate how an external microprocessor accesses

ISP1161’s internal control registers.

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ISP1161

Full-speed USB single-chip host and device controller

Philips Semiconductors

AUTOMUX

DC/HC

Host bus I/F

0

µP bus I/F

Device bus I/F

1

A1

MGT935

When A1 = 0, microprocessor accesses the HC.

When A1 = 1, microprocessor accesses the DC.

Fig 11. A microprocessor accessing a HC or a DC via an automux switch.

CMD/DATA

SWITCH

1

command port

data port

Host or Device

bus I/F

Commands

0

Command register

.

A0

MGT936

Control registers

When A0 = 0, microprocessor accesses the data port.

When A0 = 1, microprocessor accesses the command port.

Fig 12. Access to internal control registers.

8.3.2 Register access phases

ISP1161’s register structure is a command-data register pair structure. A complete

register access cycle comprises a command phase followed by a data phase. The

command (also known as the index of a register) points the ISP1161 to the next

register to be accessed. A command is 8 bits long. On a microprocessor’s 16-bit data

bus, a command occupies the lower byte, with the upper byte ﬁlled with zeros.

Figure 13 shows a complete 16-bit register access cycle for ISP1161. The

microprocessor writes a command code to the command port, and then reads from or

writes the data word to the data port. Take the example of a microprocessor

attempting to read a chip’s ID, which is saved in the HC’s HcChipID register (27H,

read only) where its command code is 27H, read only. The 16-bit register access

cycle is therefore:

1. Microprocessor writes the command code of 27H (0027H in 16-bit width) to

ISP1161’s HC command port

2. Microprocessor reads the data word of the chip’s ID (6110H) from ISP1161’s HC

data port.

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ISP1161

Full-speed USB single-chip host and device controller

Philips Semiconductors

For ISP1161’s ES1 (engineering sample: version one), the chip’s ID is 6110H, where

the upper byte of 61H stands for ISP1161, and the lower byte of 10H stands for the

ﬁrst version of the IC chip.

16-bit register access cycle

write command

(16 bits)

read/write data

(16 bits)

t

MGT937

Fig 13. 16-bit register access cycle.

Most of ISP1161’s internal control registers are 16 bits wide. Some of the internal

control registers, however, have 32-bit width. Figure 14 shows how ISP1161’s 32-bit

internal control register is accessed. The complete cycle of accessing a 32-bit

register consists of a command phase followed by two data phases. In the two data

phases, the microprocessor should ﬁrst read or write the lower 16-bit data, followed

by the upper 16-bit data.

32-bit register access cycle

write command

(16 bits)

read/write data

(lower 16 bits)

read/write data

(upper 16 bits)

t

MGT938

Fig 14. 32-bit register access cycle.

To further describe the complete access cycles of ISP1161’s internal control

registers, the status of some pin signals of the microprocessor bus interface are

shown in Figure 15 and Figure 16 for the HC and the DC respectively.

Signals

Valid status

0

CS

01

00

A1, A0

RD = 1,

WR = 0

RD = 0 (read) or

WR = 0 (write)

RD = 0 (read) or

WR = 0 (write)

RD, WR

data bus

Register data

(lower word)

Register data

(upper word)

Command code

MGT939

Fig 15. Accessing ISP1161 HC control registers.

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Signals

Valid status

0

CS

11

10

A1, A0

RD = 0 (read) or

WR = 0 (write)

RD = 0 (read) or

WR = 0 (write)

RD = 1,

WR = 0

RD, WR

data bus

Register data

(lower word)

Register data

(upper word)

Command code

MGT940

Fig 16. Accessing ISP1161 DC control registers.

8.4 Microprocessor read/write ISP1161’s internal FIFO buffer RAM by

PIO mode

Since ISP1161’s internal memory is structured as a FIFO buffer RAM, the FIFO buffer

RAM is mapped to dedicated register ﬁelds. Therefore, accessing ISP1161’s internal

FIFO buffer RAM is just like accessing the internal control registers in multiple data

phases.

FIFO buffer RAM access cycle (transfer counter = 2N)

write command

(16 bits)

read/write data

#1 (16 bits)

read/write data

#2 (16 bits)

read/write data

#N (16 bits)

t

MGT941

Fig 17. ISP1161’s internal FIFO buffer RAM access cycle.

Figure 17 shows a complete access cycle of ISP1161’s internal FIFO buffer RAM. For

a write cycle, the microprocessor ﬁrst writes the FIFO buffer RAM’s command code to

the command port, and then writes the data words one by one to the data port until

half of the transfer’s byte count is reached. The HcTransferCounter register (22H -

Read, A2H - Write) is used to specify the byte count of a FIFO buffer RAM’s read

cycle or write cycle. Every access cycle must be in the same access direction. The

read cycle procedure is similar to the write cycle.

For ISP1161 DC’s FIFO buffer RAM access, see Section 11.

8.5 Microprocessor read/write ISP1161’s internal FIFO buffer RAM by

DMA mode

The DMA interface between a microprocessor and ISP1161 is shown in Figure 10.

When doing a DMA transfer, at the beginning of every burst the ISP1161 outputs a

DMA request to the microprocessor via the DREQ pin (DREQ1 for HC, DREQ2 for

DC). After receiving this signal, the microprocessor will reply with a DMA

acknowledge to ISP1161 via the DACK pin (DACK1 for HC, DACK2 for DC), and at

the same time, do the DMA transfer through the data bus. For normal DMA mode, the

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microprocessor must still issue a RD or WR signal to ISP1161’s RD or WR pin.

(DACK Only mode does not need the RD or WR signal.) ISP1161 will repeat the DMA

cycles until it receives an EOT signal to terminate the DMA transfer.

ISP1161 supports both external EOT and internal EOT signals. The external EOT

signal is received as input from ISP1161’s EOT pin: it generally comes from the

external microprocessor. The internal EOT signal is generated by ISP1161 internally.

To select either, set the DMA conﬁguration registers. For example, for the HC, setting

bit 2 of the HcDMAConﬁguration register (21H - Read, A1H - Write) to 1 will enable

the DMA counter for DMA transfer. When the DMA counter reaches the value of

HcTransferCounter register, the internal EOT signal will be generated to terminate the

DMA transfer.

ISP1161 supports either single-cycle burst mode DMA operation or multiple-cycle

burst mode DMA operation.

DREQ

DACK

RD or WR

[

]

D 15:0

data #1

data #2

data #N

EOT

MGT942

N = 1/2 byte count of transfer data.

Fig 18. DMA transfer for single-cycle burst mode.

DREQ

DACK

RD or WR

[

]

D 15:0

data #1

data #K

data #(K+1)

data #2K

data #(N−K+1)

data #N

EOT

MGT943

N = 1/2 byte count of transfer data, K = number of cycles/burst.

Fig 19. DMA transfer for multi-cycle burst mode.

In both ﬁgures, the DMA transfer is conﬁgured such that DREQ is active HIGH and

DACK is active LOW.

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8.6 Interrupts

ISP1161 has separate interrupt request pins for the USB HC (INT1) and the USB DC

(INT2).

8.6.1 Pin conﬁguration

The interrupt output signals have four conﬁguration modes:

Level trigger, active LOW

Level trigger, active HIGH

Edge trigger, active LOW

Edge trigger, active HIGH.

•

Figure 20 shows these four interrupt conﬁguration modes. They are programmable

through register settings, which are also used to disable or enable the signals.

clear or disable INT

INT active

INT

(1) INT is level triggered, active LOW

clear or disable INT

INT active

(2) INT is level triggered, active HIGH

INT active

167 ns

(3) INT is edge triggered, active LOW

INT active

INT

MGT944

167 ns

(4) INT is edge triggered, active HIGH

Fig 20. Interrupt pin operating modes.

8.6.2 HC’s interrupt output pin (INT1)

To program the four conﬁguration modes of the HC’s interrupt output signal (INT1),

set bits 1 and 2 of the HcHardwareConﬁguration register (20H - Read, A0H - Write).

Bit 0 is used as the master enable setting for pin INT1.

INT1 has many interrupt events. The relationship between pin INT1 and its interrupt

events is shown as in Figure 21.

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HcInterruptStatus

register

HcuPInterrupt

register

SO

SOF/ITL

ATL

SF

RD

X

All EOT

UE

OPR Reg

HcSuspend

ClkReady

FNO

RHSC

PULSE

GENERATOR

INT Enable

INT Trigger

INT Polarity

SO IE

SF IE

SOF/ITL IE

ATL IE

X

1

0

RD IE

.

All EOT IE

UE IE

OPR Reg IE

HcSuspend IE

ClkReady IE

FNO IE

RHSC IE

HcHardwareConfiguration

register

HcInterruptEnable

register

INT1

HcuPInterruptEnable

register

MGT945

Fig 21. HC interrupt logic.

The interrupt events of the HcµPInterrupt register (24H - Read, A4H - Write) changes

the status of pin INT1 when the corresponding bits of the HcµPInterruptEnable

register (25H - Read, A5H - Write) and pin INT1’s global enable bit (bit 0 of the

HcHardwareConﬁguration register) are all set to enable status.

However, events that come from the HcInterruptStatus register (03H - Read, 83H -

Write) affect only the OPR_Reg bit of the HcµPInterrupt register. They cannot directly

change the status of pin INT1.

8.6.3 DC’s interrupt output pin (INT2)

The DC’s interrupt output pin INT2’s four conﬁguration modes can also be

programmed by setting bit 0 (INTPOL) and bit 1 (INTLVL) of the DC’s hardware

conﬁguration register (BBH - Read, BAH - Write). Bit 3 (INTENA) of the DC’s mode

register (B9H - Read, B8H - Write) is used as pin INT2’s global enable setting.

Figure 22 shows the relationship between the interrupt events and pin INT2.

Each of the indicated USB events is logged in a status bit of the Interrupt Register.

Corresponding bits in the Interrupt Enable Register determine whether or not an

event will generate an interrupt.

Interrupts can be masked globally by means of the INTENA bit of the Mode Register

(see Table 80).

The active level and signalling mode of the INT output is controlled by the INTPOL

and INTLVL bits of the Hardware Conﬁguration Register (see Table 82). Default

settings after reset are active LOW and level mode. When pulse mode is selected, a

pulse of 166 ns is generated when the OR-ed combination of all interrupt bits

changes from logic 0 to logic 1.

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Bits RESET, RESUME, EOT and SOF are cleared upon reading the Interrupt

Register. The endpoint bits (EP0OUT to EP14) are cleared by reading the associated

Endpoint Status Register.

Bit BUSTATUS follows the USB bus status exactly, allowing the ﬁrmware to get the

current bus status when reading the Interrupt Register.

SETUP and OUT token interrupts are generated after ISP1161’s DC has

acknowledged the associated data packet. In bulk transfer mode, the ISP1161’s DC

will issue interrupts for every ACK received for an OUT token or transmitted for an IN

token.

In isochronous mode, an interrupt is issued upon each packet transaction. The

ﬁrmware must take care of timing synchronization with the host. This can be done via

the Pseudo Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the Interrupt

Enable Register. If a Start-Of-Frame is lost, PSOF interrupts are generated every

1 ms. This allows the ﬁrmware to keep data transfer synchronized with the host. After

3 missed SOF events the ISP1161’s DC will enter ‘suspend’ state.

An alternative way of handling isochronous data transfer is to enable both the SOF

and the PSOF interrupts and disable the interrupt for each isochronous endpoint.

DC Interrupt register

RESET

SUSPND

RESUME

.

SOF

.

EP14

...

EP0IN

EP0OUT

EOT

.

DC Device Mode register

INTENA

IERST

IESUSP

IERESM

IESOF

IEP14

...

PULSE

GENERATOR

.

1

0

DC Hardware Configuration

register

INTLVL

INTPOL

IEP0IN

IEP0OUT

IEEOT

INT2

MGT946

DC Interrupt Enable register

Fig 22. DC interrupt logic.

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9. The USB host controller (HC)

9.1 The HC’s four USB states

ISP1161’s USB HC has four USB states−USB Operational, USB Reset, USB

Suspend, and USB Resume− that deﬁne the HC’s USB signaling and bus states

responsibilities. The signals are visible to the HC (software) Driver via ISP1161 USB

HC’s control registers.

USB_OPERATIONAL

USB_RESET write

USB_OPERATIONAL write

USB_RESET write

USB_OPERATIONAL write

USB_RESUME

USB_RESET

USB_SUSPEND write

hardware reset

USB_RESUME write

or

remote wake-up

USB_RESET write

MGT947

USB_SUSPEND

software reset

Fig 23. ISP1161 HC’s USB states.

The USB states are reﬂected in the HostControllerFunctionalState ﬁeld of the

HcControl register (01H - Read, 81H - Write), which is located at bits 7 and 6 of the

register.

The HC Driver can perform only the USB state transitions shown in Figure 23.

Remark: The Software Reset in Figure 23 is not caused by the HcSoftwareReset

command. It is caused by the HostControllerReset ﬁeld of the HcCommandStatus

register (02H - Read, 82H - Write).

9.2 Generating USB trafﬁc

USB trafﬁc can be generated only when the ISP1161 USB HC is under the USB

Operational State. Therefore, the HC Driver must set the

HostControllerFunctionalState ﬁeld of the HcControl register before generating USB

trafﬁc.

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A simplistic ﬂow diagram showing when and how to generate USB trafﬁc is shown in

Figure 24. For greater accuracy, refer to both the Universal Serial Bus Speciﬁcation

Revision 1.1 about the protocol and ISP1161 USB HC’s register usage.

Reset

Exit

no

HC state =

USB_Operational

yes

Need

USB traffic?

Prepare PTD data in

µP system RAM

Transfer PTD data into

HC FIFO buffer RAM

Initialize

HC

HC informs HCD of

USB traffic results

HC performs USB transactions

via USB bus I/F

HC interprets

PTD data

Entry

MGT948

Fig 24. ISP1161 HC operating ﬂow.

Reset

•

This includes hardware reset by pin RESET and software reset by the

HcSoftwareReset command (A9H). The reset function will clear all the HC’s

internal control registers to their reset status. After reset, the HC Driver must

initialize the ISP1161 USB HC by setting some registers.

Initialize HC

It includes:

•

– Setting the physical size for the HC’s internal FIFO buffer RAM by setting the

HcITLBufferLength register (2AH - Read, AAH - Write) and the

HcATLBufferLength register (2BH - Read, ABH - Write)

– Setting the HcHardwareConﬁguration register according to requirements

– Clearing interrupt events, if required

– Enabling interrupt events, if required

– Setting the HcFmInterval register (0DH - Read, 8DH - Write)

– Setting the HC’s root hub registers

– Setting the HcControl register to move the HC into USB Operational state

See also Section 9.5.

Entry

•

The normal entry point. The microprocessor returns to this point when there are

HC requests.

Need USB Trafﬁc

USB devices need the HC to generate USB trafﬁc when they have USB trafﬁc

requests such as:

– Connecting to or disconnecting from the downstream ports

– Issuing the Resume signal to the HC

To generate USB trafﬁc, the HC Driver must enter the USB transaction loop.

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Prepare PTD Data in µP System RAM

•

The communication channel between the HC Driver and ISP1161’s USB HC is in

the form of Philips Transfer Descriptor (PTD) data. The PTD data provides USB

trafﬁc information about the commands, status, and USB data packets.

The physical storage media of PTD data for the HC Driver is the microprocessor’s

system RAM. For ISP1161’s USB HC, it is the ISP1161’s internal FIFO buffer

RAM.

The HC Driver prepares PTD data in the microprocessor’s system RAM for transfer

to ISP1161’s HC internal FIFO buffer RAM.

Transfer PTD Data into HC’s FIFO Buffer RAM

•

When PTD data is ready in the microprocessor’s system RAM, the HC Driver must

transfer the PTD data from the microprocessor’s system RAM into ISP1161’s

internal FIFO buffer RAM.

HC Interprets PTD Data

The HC determines what USB transactions are required based on the PTD data

that have been transferred into the internal FIFO buffer RAM.

•

HC Performs USB Transactions via USB Bus Interface

The HC performs the USB transactions with the speciﬁed USB device endpoint

through the USB bus interface.

HC Informs HCD the USB Trafﬁc Results

The USB transaction status and the feedback from the speciﬁed USB device

endpoint will be put back into the ISP1161’s HC internal FIFO buffer RAM in PTD

data format. The HC Driver can read back the PTD data from the internal FIFO

buffer RAM.

9.3 PTD data structure

The Philips Transfer Descriptor (PTD) data structure provides a communication

channel between the HC Driver and the ISP1161’s USB HC. PTD data contains

information required by the USB trafﬁc. PTD data consists of a PTD followed by its

payload data, as shown in Figure 25.

FIFO buffer RAM

top

PTD

PTD data #1

payload data

PTD

PTD data #2

payload data

PTD

PTD data #N

payload data

bottom

MGT949

Fig 25. PTD data in FIFO buffer RAM.

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The PTD data structure is used by the HC to deﬁne a buffer of data that will be moved

to or from an endpoint in the USB device. This data buffer is set up for the current

frame (1 ms frame) by the ﬁrmware, the HC Driver. The payload data for every

transfer in the frame must have a PTD as a header to describe the characteristic of

the transfer. PTD data is DWORD aligned.

9.3.1 PTD data header deﬁnition

The PTD forms the header of the PTD data. It tells the HC the transfer type, where

the payload data should go, and the payload data’s actual size. A PTD is an 8-byte

data structure that is very important for HC Driver programming.

Table 4: Philips Transfer Descriptor (PTD): bit allocation

Bit

7

6

5

4

3

2

1

0

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Byte 7

ActualBytes[7:0]

Active

CompletionCode[3:0]

EndpointNumber[3:0]

Toggle

Speed

ActualBytes[9:8]

MaxPacketSize[9:8]

TotalBytes[9:8]

MaxPacketSize[7:0]

Last

TotalBytes[7:0]

DirectionPID[1:0]

FunctionAddress[6:0]

Format

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Table 5: Philips Transfer Descriptor (PTD): bit description

Symbol

Access

R/W

Description

ActualBytes[9:0]

CompletionCode[3:0]

Contains the number of bytes that were transferred for this PTD

R/W

0000 NoError

General TD or isochronous data packet processing

completed with no detected errors.

0001 CRC

Last data packet from endpoint contained a CRC error.

0010 BitStufﬁng

Last data packet from endpoint contained a bit stufﬁng

violation.

0011 DataToggleMismatch

0100 Stall

Last packet from endpoint had data toggle PID that did

not match the expected value.

TD was moved to the Done queue because the

endpoint returned a STALL PID.

0101 DeviceNotResponding Device did not respond to token (IN) or did not provide a

handshake (OUT).

0110 PIDCheckFailure

0111 UnexpectedPID

1000 DataOverrun

Check bits on PID from endpoint failed on data PID (IN)

or handshake (OUT)

Received PID was not valid when encountered or PID

value is not deﬁned.

The amount of data returned by the endpoint exceeded

either the size of the maximum data packet allowed

from the endpoint (found in MaximumPacketSize ﬁeld of

ED) or the remaining buffer size.

1001 DataUnderrun

The endpoint returned is less than MaximumPacketSize

and that amount was not sufﬁcient to ﬁll the speciﬁed

buffer.

1010 reserved

-

1011 reserved

1100 BufferOverrun

During an IN, the HC received data from an endpoint

faster than it could be written to system memory.

1101 BufferUnderrun

During an OUT, the HC could not retrieve data from the

system memory fast enough to keep up with the USB

data rate.

Active

R/W

Set to logic 1 by ﬁrmware to enable the execution of transactions by the HC. When the

transaction associated with this descriptor is completed, the HC sets this bit to logic 0,

indicating that a transaction for this element should not be executed when it is next

encountered in the schedule.

Toggle

R/W

R

Used to generate or compare the data PID value (DATA0 or DATA1). It is updated after

each successful transmission or reception of a data packet.

MaxPacketSize[9:0]

The maximum number of bytes that can be sent to or received from the endpoint in a

single data packet.

EndpointNumber[3:0]

Last(PTD)

R

USB address of the endpoint within the function.

Last PTD of a list (ITL or ATL). A logic 1 indicates that the PTD is the last PTD.

Speed of the endpoint:

(Low)Speed

S = 0 — full speed

S = 1 — low speed

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Table 5: Philips Transfer Descriptor (PTD): bit description…continued

Symbol

Access

Description

TotalBytes[9:0]

R

Speciﬁes the total number of bytes to be transferred with this data structure. For Bulk and

Control only, this can be greater than MaximumPacketSize.

DirectionPID[1:0]

R

00

01

10

11

SETUP

OUT

IN

reserved

Format

R

The format of this data structure. If this is a Control, Bulk or Interrupt endpoint, then

Format = 0. If this is an Isochronous endpoint, then Format = 1.

FunctionAddress[6:0]

The is the USB address of the function containing the endpoint that this PTD refers to.

9.4 HC’s internal FIFO buffer RAM structure

9.4.1 Partitions

According to the Universal Serial Bus Speciﬁcation Rev 1.1, there are four types of

USB data transfers: Control, Bulk, Interrupt and Isochronous.

The HC’s internal FIFO buffer RAM is of a physical size of 4 kbytes. This internal

FIFO buffer RAM is used for transferring data between the microprocessor and USB

peripheral devices. This on-chip buffer RAM can be partitioned into two areas:

Acknowledged Transfer List (ATL) buffer and Isochronous (ISO)Transfer List (ITL)

buffer. The ITL buffer is a Ping-pong structured FIFO buffer RAM that is used to keep

the payload data and their PTD header for Isochronous transfers. The ATL buffer is a

non Ping-pong structured FIFO buffer RAM that is used for the other three types of

transfers.

For the ITL buffer, it can be further partitioned into ITL0 and ITL1 for the Ping-Pong

structure. The ITL0 buffer and ITL1 buffer always have the same size. The

microprocessor can put ISO data into either the ITL0 buffer or the ITL1 buffer. When

the microprocessor accesses an ITL buffer, the HC can take over another ITL buffer

at the same time. This architecture can improve the ISO transfer performance.

The Host Controller Driver can assign the logical size for ATL buffer and ITL buffers at

any time, but normally at initialization after power-on reset, by setting the

HcATLBufferLength register (2BH - Read, ABH - Write) and HcITLBufferLength

register (2AH - Read, AAH - Write), respectively. However, the total length (ATL buffer

+ ITL buffer) should not exceed 4 kbytes, the maximum RAM size. Figure 26 shows

the partitions of the internal FIFO buffer RAM. When assigning buffer RAM sizes,

follow this formula:

ATL buffer length + 2 × (ITL buffer size) ≤ 1000H (that is, 4 kbytes)

where: ITL buffer size = ITL0 buffer length = ITL1 buffer length

The following assignments are examples of legal uses of the internal FIFO buffer

RAM:

ATL buffer length = 800H, ITL buffer length = 400H.

This is the maximum use of the internal FIFO buffer RAM.

•

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ATL buffer length = 400H, ITL buffer length = 200H.

This is insufﬁcient use of the internal FIFO buffer RAM.

•

ATL buffer length = 1000H, ITL buffer length = 0H.

This will use the internal FIFO buffer RAM for only ATL transfers.

ATL buffer length = 0H, ITL buffer length = 800H.

This will use the internal FIFO buffer RAM for only ISO transfers.

FIFO buffer RAM

top

ITL0

ISO data A

ISO data B

ITL buffer

ATL buffer

ITL1

programmable

sizes

control/bulk/interrupt

data

ATL

not used

bottom

4 kbytes

MGT950

Fig 26. HC Internal FIFO buffer RAM partitions.

The actual requirement for the buffer RAM may not reach the maximum size. You can

make your selection based on your application.

The following are some calculations of the ISO_A or ISO_B space for a frame of data:

Maximum number of useful data sent during one USB frame is 1280 bytes (20 ISO

packets of 64 bytes). Total RAM size needed for this is 20 × 8 + 1280 = 1440 bytes.

Maximum number of packets for different endpoints sent during one USB frame is

150 (150 ISO packets of 1 byte). Total RAM size needed is

•

150 × 8 + 150 × 1 = 1350 bytes.

The Ping buffer RAM (ITL0) and the Pong buffer RAM (ITL1) have a maximum size

of 2 kbytes each. All data needed for one frame can be stored in the Ping or the

Pong buffer RAM.

•

When the embedded system wants to initiate a transfer to the USB bus, the data

needed for one frame is transferred to the ATL buffer or ITL buffer. The

microprocessor detects the buffer status through the interrupt routines. When the

HcBufferStatus register (2CH - Read only) indicates that buffer is empty, then the

microprocessor can write data into the buffer. When the HcBufferStatus register

indicates that buffer is full, that is data is ready on the buffer, the microprocessor

needs to read data from the buffer.

During every 1 ms, there might be many events to generate interrupt requests to the

microprocessor for data transfer or status retrieval. However, each of the interrupt

types deﬁned in this speciﬁcation can be enabled or disabled by setting the

HcµPInterruptEnable register bits accordingly.

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The data transfer can be done via PIO mode or DMA mode. The data transfer rate

can go up to 15 Mbyte/s. In DMA operation, single-cycle or multi-cycle burst modes

are supported. For the multi-cycle burst mode, 1, 4, or 8 cycles per burst is supported

for ISP1161.

9.4.2 Data organization

PTD data is used for every data transfer between a microprocessor and the USB bus,

and the PTD data resides in the buffer RAM. For an OUT or SETUP transfer, the

payload data is placed just after the PTD, after which the next PTD is placed. For an

IN transfer, some RAM space is reserved for receiving a number of bytes that is equal

to the total bytes of the transfer. After this, the next PTD and its payload data are

placed (see Figure 27).

Remark: The PTD is deﬁned for both ATL and ITL type data transfer. For ITL, the

PTD data should be put into ITL buffer RAM, the ISP1161 takes care of the

Ping-Pong action for the ITL buffer RAM access.

RAM buffer

top

000H

PTD of OUT transfer

payload data of OUT transfer

PTD of IN transfer

empty space for IN total data

PTD of OUT transfer

payload data of OUT transfer

bottom

7FFH

MGT952

Fig 27. Buffer RAM data organization.

The PTD data (PTD header and its payload data) is a structure of DWORD (double-

word or 4-byte) alignment. This means that the memory address is organized in steps

of 4 bytes. Therefore, the ﬁrst byte of every PTD and the ﬁrst byte of every payload

data are located at an address which is a multiple of 4. Figure 28 illustrates an

example in which the ﬁrst payload data is 14 bytes long, meaning that the last byte of

the payload data is at the location 15H. The next addresses (16H and 17H) are not

multiples of 4. Therefore, the ﬁrst byte of the next PTD will be located at the next

multiple-of-four address, 18H.

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RAM buffer

top

00H

08H

PTD

(8 bytes)

payload data

(14 bytes)

15H

18H

PTD

(8 bytes)

20H

payload data

MGT953

Fig 28. PTD data with DWORD alignment in buffer RAM.

9.4.3 Operation & C Program Example

Figure 29 shows the block diagram for internal FIFO buffer RAM operations by PIO

mode. ISP1161 provides one register as the access port for each buffer RAM. For the

ITL buffer RAM, the access port is the ITLBufferPort register (40H - Read, C0H -

Write). For the ATL buffer RAM, the access port is the ATLBufferPort register (41H -

Read, C1H - Write). The buffer RAM is an array of bytes (8 bits) while the access port

is a 16-bit register. Therefore, each read/write operation on the port accesses two

consecutive memory locations, incrementing the pointer of the internal buffer RAM by

two.

The lower byte of the access port register corresponds to the data byte at the even

location of the buffer RAM, and the higher byte in the access port register

corresponds to the other data byte at the odd location of the buffer RAM. Regardless

of the number of data bytes to be transferred, the command code must be issued

merely once, and it will be followed by a number of accesses of the data port (see

Section 8.4).

When the pointer of the buffer RAM reaches the value of the HcTransferCounter

register, an internal EOT signal will be generated to set bit 2, AllEOTInterrupt, of the

HcµPinterrupt register and update the HcBufferStatus register, to indicate that the

whole data transfer has been completed.

For ITL buffer RAM, every start of frame (SOF) signal (1 ms) will cause toggling

between ITL0 and ITL1 but this depends on the buffer status. If both ITL0BufferFull

and ITL1BufferFull of the HcBufferStatus register are already logic 1, meaning that

both ITL0 and ITL1 buffer RAMs are full, the toggling will not happen. In this case, the

microprocessor will always have access to ITL1.

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Following is an example of a C program that shows how to write data into the ATL

buffer RAM. The total number of data bytes to be transferred is 80 (decimal) which

will be set into the HcTransferCounter register as 50H. The data consists of four types

of PTD data:

1. The ﬁrst PTD header (IN) is 8 bytes, followed by 16 bytes of space reserved for its

payload data;

2. The second PTD header (IN) is also 8 bytes, followed by 8 bytes of space

reserved for its payload data;

3. The third PTD header (OUT) is 8 bytes, followed by 16 bytes of payload data with

values beginning from 0H to FH incrementing by 1;

4. The fourth PTD header (OUT) is also 8 bytes, followed by 8 bytes of payload data

with values beginning from 0H to EH incrementing by 2.

In all PTD’s, we assign device address 5 and endpoint 1. ActualBytes is always zero

(0). TotalBytes equals the number of payload data bytes. The following table shows

the results after running this program.

Table 6: Run results of the C program example

Observed items

HC not initialized and not

under Operational state

HC initialized and under Comments

Operational state

HcµPinterrupt Register

Bit 1 (ATLInt)

0

1

microprocessor must read ATL

Bit 2 (AllEOTInterrupt)

HcBufferStatus Register

Bit 2 (ATLBufferFull)

Bit 5 (ATLBufferDone)

USB Trafﬁc on USB Bus

transfer completed

1

0

1

transfer completed

PTD data processed by HC

OUT packets can be seen

No

Yes

However, if communication with a peripheral USB device is desired, the device should

be connected to the downstream port and pass enumeration.

//The example program for writing ATL buffer RAM

#include <conio.h>

#include <stdio.h>

#include <dos.h>

//Define register commands

#define wHcTransferCounter 0x22

#define wHcuPInterrupt 0x24

#define wHcATLBufferLength 0x2b

#define wHcBufferStatus 0x2c

// Define I/O Port Address for HC

#define HcDataPort 0x290

#define HcCmdPort 0x292

//Declare external functions to be used

unsigned int HcRegRead(unsigned int wIndex);

void HcRegWrite(unsigned int wIndex,unsigned int wValue);

void main(void)

{

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unsigned int i;

unsigned int wCount,wData;

// Prepare PTD data to be written into HC ATL buffer RAM:

unsigned int PTDData[0x28]=

{

0x0800,0x1010,0x0810,0x0005, //PTD header for IN token #1

//Reserved space for payload data of IN token #1

0x0000,0x0000,0x0000,0x0000, 0x0000,0x0000,0x0000,0x0000,

0x0800,0x1008,0x0808,0x0005, //PTD header for IN token #2

//Reserved space for payload data of IN token #2

0x0000,0x0000,0x0000,0x0000,

0x0800,0x1010,0x0410,0x0005, //PTD header for OUT token #1

0x0100,0x0302,0x0504,0x0706, //Payload data for OUT token #1

0x0908,0x0b0a,0x0d0c,0x0f0e,

0x0800,0x1808,0x0408,0x0005, //PTD header for OUT token #2

0x0200,0x0604,0x0a08,0x0e0c //Payload data for OUT token #2

};

HcRegWrite(wHcuPInterrupt,0x04); //Clear EOT interrupt bit

//HcRegWrite(wHcITLBufferLength,0x0);

HcRegWrite(wHcATLBufferLength,0x1000); //RAM full use for ATL

//Set the number of bytes to be transferred

HcRegWrite(wHcTransferCounter,0x50);

wCount = 0x28; //Get word count outport

(HcCmdPort,0x00c1); //Command for ATL buffer write

//write 80 (0x50) bytes of data into ATL buffer RAM

for (i=0;i<wCount;i++)

{

outport(HcDataPort,PTDData[i]);

};

//Check EOT interrupt bit

wData = HcRegRead(wHcuPInterrupt);

printf("\n HC Interrupt Status = %xH.\n",wData);

//Check Buffer status register

wData = HcRegRead(wHcBufferStatus);

printf("\n HC Buffer Status = %xH.\n",wData);

}

//

// Read HC 16-bit registers

//

unsigned int HcRegRead(unsigned int wIndex)

{ unsigned int wValue;

outport(HcCmdPort,wIndex & 0x7f);

wValue = inport(HcDataPort);

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return(wValue);

}

//

// Write HC 16-bit registers

//

void HcRegWrite(unsigned int wIndex,unsigned int wValue)

{

outport(HcCmdPort,wIndex | 0x80);

outport(HcDataPort,wValue);

}

command port

data port

1

0

Host bus I/F

Control registers

Commands

Command register

A0

TransferCounter

22H/A2H

24H/A4H

EOT

2

1

0

µPInterrupt

=

internal EOT

2CH

40H/C0H

41H/C1H

BufferStatus

ITLBufferPort

ATLBufferPort

(16-bit width)

toggle

T

SOF

BufferStatus

Pointer

000H

001H

000H

001H

automatically

increments by 2

001H

3FFH

7FFH

ITL0 buffer RAM

(8-bit width)

ITL1 buffer RAM

(8-bit width)

ATL buffer RAM

(8-bit width)

MGT951

Fig 29. PIO access to Internal FIFO buffer RAM.

9.5 HC’s operational model

Upon power up, the HC Driver sets up all operational registers (32-bit). The

FSLargestDataPacket ﬁeld (bits 30 to 16) of the HcFmInterval register (0DH - Read,

8DH - write) and the HcLSThreshold register (11H - Read, 91H - Write) determine the

end of the frame for full-speed and low-speed packets. By programming these ﬁelds,

the effective USB bus usage can be changed. Furthermore, the size of the ITL buffers

(HcITLBufferLength, 2AH - Read, AAH - Write) is programmed.

In the case when a USB frame contains both ISO and AT packets, two interrupts will

be generated per frame.

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One interrupt is issued concurrently with the SOF. This interrupt (the ITLint is set in

the HcµPInterrupt register) triggers reading and writing of the ITL by the

microprocessor, after which the interrupt is cleared by the microprocessor.

Next the programmable AT Interrupt (the ATLint is set in the HcµPInterrupt Register)

is issued, which triggers reading and writing of the ITL by the microprocessor, after

which the interrupt is cleared by the microprocessor. If the microprocessor cannot

handle the ISO interrupt before the next ISO interrupt, disrupted ISO trafﬁc can result.

To be able to send more than one packet to the same Control or Bulk endpoint in the

same frame, an active bit and a ’TotalBytes of transfer’ ﬁeld are introduced (see

Table 5). The active bit is cleared only if all data of the Philips Transfer Descriptor

(PTD) are transferred or if a transaction at that endpoint contained a fatal error. If all

PTD of the ATL are serviced once and the frame is not over yet, the HC starts looking

for a PTD with the active bit still set. If such a PTD is found and there is still enough

time in this frame, another transaction is started on the USB bus for this endpoint.

For ISO processing, the Host Controller Driver has also to take care of the

BufferStatus register (2CH, Read only) for the ITL buffer RAM operations. After the

Host Controller Driver writes ISO data into ITL buffer RAM, the ITL0BufferFull or

ITL1BufferFull bit (depends if it is ITL0 or ITL1) will be set to logic 1.

After the HC processes the ISO data in the ITL buffer RAM then the corresponding

ITL0BufferDone or ITL1BufferDone bit will automatically be set to logic 1.

The Host Controller Driver can clear the buffer status bits by a read of the ITL buffer

RAM, and this must be done within the 1 ms frame from which the ITL0BufferDone or

ITL1BufferDone was set. Failure to do so will cause the ISO processing to stop and a

power on reset or software reset will have to be applied to the HC, a USB reset to the

USB bus must not be made.

For example, in the ﬁrst frame, for the HCD doing a write of ISO-A data into the ITL0

buffer. This will cause the BufferStatus register to show that the ITL0 buffer is full by

setting the ITL0BufferFull bit to logic 1. At this stage the Host Controller Driver cannot

write ISO data into the ITL0 buffer RAM again.

In the second frame, the Host Controller will process the ISO-A data in the ITL0

buffer. At the same time, the HCD can write ISO-B data into ITL1 buffer. When the

next SOF comes (the beginning of the third frame), both the ITL1BufferFull and

ITL0BufferDone are automatically set to logic 1. In the third frame the HCD has to

read ITL0 buffer at least two bytes (one word) to clear both the ITL0BufferFull and

ITL0BufferDone bits. If both are not cleared, when the next SOF comes (the

beginning of the fourth frame) the ITL0BufferDone bit will be cleared automatically,

but the ITL0BufferFull bit remains at logic 1 and the ITL0BufferFull bit will be unable

to be cleared. This condition will disable the HCD from writing ISO data into the ITL0

buffer again and ISO processing be unable to be carried on. This also applies to the

ITL1 buffer because the ITL0 and ITL1 are Ping-Pong structured buffers. To recover

from this state the power on reset or software reset will have to be applied on the HC.

Time domain behavior

In the ﬁrst example the CPU is fast enough to read back and download a scenario

before the next interrupt. Note that on the ISO interrupt of frame N:

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The ISO packet for frame N + 1 will be written;

•

The AT packet for frame N + 1 will be written.

AT

interrupt

traffic

on USB

SOF

(frame N)

(frame N + 1)

(frame N + 2)

(frame N + 3)

MGT954

ISO

interrupt

read ISO_A(N − 1) write ISO_A(N + 1)

read AT(N)

write AT(N + 1)

Fig 30. HC time domain behavior: example 1.

In the next example, the microprocessor is still busy transferring the AT data when the

ISO interrupt of the next frame (N + 1) is raised. As a result, there will be no AT trafﬁc

in frame N + 1. The HC should not raise an AT interrupt in frame N + 1. The AT part is

simply postponed until frame N + 2. On the AT N + 2 interrupt the transfer mechanism

is back to normal operation. This simple mechanism ensures, among other things,

that Control transfers are not dropped systematically from the USB in case of an

overloaded microprocessor.

(frame N)

(frame N + 1)

(frame N + 2)

(frame N + 3)

MGT955

Fig 31. HC time domain behavior: example 2.

In the following example the ISO part is still being written while the Start of Frame

(SOF) of the next frame has occurred. This will result in undeﬁned behaviour for the

ISO data on the USB bus in frame N + 1 (depending on the exact timing data is

corrupted or not). The HC should not raise an AT interrupt in frame N + 1.

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(frame N)

(frame N + 1)

(frame N + 2)

(frame N + 3)

MGT956

Fig 32. HC time domain behavior: example 3.

Control Transaction Limitations

The different phases of a Control transfer (SETUP, Data and Status) should never be

put in the same ATL.

9.6 Microprocessor loading

The maximum amount of data that can be transferred for an endpoint during one

frame is 1023 bytes. The number of USB packets that are needed for this batch of

data depends on the Maximum Packet Size that is speciﬁed.

The HC Driver has to schedule the transactions in a frame. On the other hand, the

microprocessor must have the ability to handle the interrupts coming from HC every

1 ms. It must also be able to do the scheduling for the next frame, reading the frame

information from and writing the next frame information to the buffer RAM in the time

between the end of the current frame and the start of the next frame.

9.7 Internal 15 kΩ pull-down resistors for downstream ports

There are four internal 15 kΩ pull-down resistors built in ISP1161 for the two

downstream ports: two resistors for each port. These resistors are software

selectable by programming bit 12 of the HcHardwareConﬁguration register (20H -

Read, A0H - Write). When bit 12 is cleared to logic 0, it means that external 15 kΩ

pull-down resistors should be used. Bit 12 is set to logic 1 that indicates the internal

built in 15 kΩ pull-down resistors will be used instead of external ones. See

Figure 33.

This feature is a cost-saving option. However, the power on reset default value is

logic 0. If you want to use the internal resistors, the HC Driver must check this bit

status after every reset, because a reset action will clear this bit regardless of it being

a hardware reset or a software reset.

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V

BUS

USB

connector

ISP1161

22 Ω

D−

D+

22 Ω

bit 12

HcHardware

Configuration

47 pF

(2×)

external

15 kΩ

(2×)

internal

15 kΩ

(2×)

MGT957

Using either internal or external 15 kΩ resistors.

Fig 33. Use of 15 kΩ pull-down resistors on downstream ports.

9.8 Overcurrent detection and power switching control

A downstream port provides +5 V power supply to the V_BUS. The ISP1161 has built-in

hardware functions to monitor the downstream ports loading conditions and control

their power switching. These hardware functions are implemented by the internal

power switching control circuit and overcurrent detection circuit. H_PSW1 and

H_PSW2 are power switching control output pins (active LOW, open drain) for

downstream port 1 and 2, respectively. H_OC1 and H_OC2 are overcurrent detection

input pins for downstream ports 1 and 2, respectively. Let H_PSWn denote either

H_PSW1 or H_PSW2 and H_OCn denote either H_OC1 or H_OC2.

Figure 34 shows the ISP1161 downstream port power management scheme.

regulator

HC CORE

HcHardware

V

CC

(+5 V or +3.3 V)

OC detect

Configuration

OC select

1

bit 10

≥

H_OCn

0

Reg

PSW

H_PSWn

C/L

ISP1161

MGT959

Fig 34. Downstream port power management scheme.

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9.8.1 Using internal OC detection circuit

The internal OC detection circuit can be used only when V_CC(pin 56) is connected to

a +5 V power supply. The HC Driver must set AnalogOCEnable, bit 10 of the

HcHardwareConﬁguration register, to logic 1.

An application using the internal OC detection circuit and internal 15 kΩ pull-down

resistors is shown in Figure 35, where H_DMn denotes either pin H_DM1 or H_DM2,

while H_DPn denotes either pin H_DP1 or H_DP2. In this example, the HC Driver

must set both AnalogOCEnable and the DownstreamPort15KresistorSel to logic 1.

They are bit 10 and bit 12 of the HcHardwareConﬁguration register, respectively.

When H_OCn detects an overcurrent status on a downstream port, H_PSWn will

output HIGH, a logic 1 to turn off the +5 V power supply to the downstream port V_BUS

.

When there is no such detection, H_PSWn will output LOW, a logic 0 to turn on the

+5 V power supply to the downstream port V_BUS

.

In general applications, we can use a P-channel MOSFET (such as PHP109) as the

power switch for V_BUS. Connect the +5 V power supply to the drain pole of the

P-channel MOSFET, V_BUSto the source pole, and H_PSWn to the gate pole. We call

the voltage drop (∆V) across the drain and source poles the overcurrent trip voltage.

For the internal overcurrent detection circuit, a voltage comparator has been

designed-in, with a nominal voltage threshold of 75 mV. Therefore, when the

overcurrent trip voltage (∆V) exceeds the voltage threshold, H_PSWn will output a

HIGH level, logic 1 to turn off the P-channel MOSFET. If the P-channel MOSFET has

a R_DSonof 150 mΩ, the overcurrent threshold will be 500 mA. The selection of a

P-channel MOSFET with a different R_DSonwill result in a different overcurrent

threshold.

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regulator

P-Ch

HC CORE

MOSFET

(PHP109)

V

CC

HcHardware

Configuration

+

5 V

OC detect

OC select

1

bit 10

≥

+

∆V = 5 V − V

BUS

H_OCn

0

Reg

V

BUS

PSW

H_PSWn

C/L

USB

downstream

port

connector

22 Ω

H_DMn

ATX

SIE

H_DPn

bit 12

47 pF

(2×)

HcHardware

Configuration

15 kΩ

(2×)

ISP1161

MGT960

Fig 35. Using internal OC detection circuit.

9.8.2 Using external OC detection circuit

When V_CC(pin 56) is connected to the +3.3 V power supply instead of the +5 V

power supply, then the internal OC detection circuit cannot be used. An external OC

detection circuit must be used instead. Nevertheless, regardless of V_CC’s

connections, an external OC detection circuit can be used from time to time. To use

an external OC detection circuit, AnalogOCEnable, bit 10 of the

HcHardwareConﬁguration register, should be set to logic 0. By default after reset, this

bit is already set to logic 0; therefore, the HC Driver does not need to clear this bit.

Figure 36 shows how to use an external OC detection circuit.

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+

3.3 V or 5 V

regulator

HC CORE

V

CC

HcHardware

Configuration

V

+

5 V

BUS

OC detect

OC select

1

external

OC detect

bit 10

≥

V

i

H_OCn

o

0

Reg

OC

EN

PSW

H_PSWn

C/L

USB

downstream

port

connector

22 Ω

H_DMn

H_DPn

ATX

SIE

22 Ω

bit 12

47 pF

(2×)

HcHardware

Configuration

15 kΩ

(2×)

ISP1161

MGT961

Fig 36. Using external OC detection circuit.

10. Suspend and wakeup (in HC)

10.1 HC suspended state

The HC can be put into suspended state by setting the HcControl register (01H -

Read, 81H - Write). See Figure 23 for the HC’s ﬂow of USB states changes.

XOSC_6MHz

(to DC PLL)

HC_ClkOk

PLL_Lock

HC PLL

PLL_ClkOut

DIGITAL

CLOCK

SWITCH

XOSC

On

HC_Clk48MOut

HC_RawClk48M

On

HC

CORE

HC_EnableClock

HcHardware Configuration

bit 11 (SuspendClkNotStop)

On

HC_NeedClock

VOLTAGE

REGULATOR

H_Wakeup (pin)

CS (pin)

MGT958

DC_EnableClock

Fig 37. ISP1161 suspend and resume clock scheme.

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With the device in a suspended state it will consume considerably less power by

turning off the internal 48 MHz clock, PLL and crystal, and setting the internal

regulator to power-down mode. The ISP1161 suspend and resume clock scheme is

shown in Figure 37.

Remark: ISP1161 can be put into a fully suspended mode only after both the HC and

the DC go into the suspended mode, when the crystal can be turned off and the

internal regulator can be put into power-down mode.

Pin H_SUSPEND is the sensing output pin for HC’s suspended state. When the HC

goes into SUSPEND state, this pin will output a HIGH level (logic 1). This pin is

cleared to LOW (logic 0) level only when the HC is put into a RESET state or

OPERATIONAL state (refer to the HcControl register bits 7 to 6, 01H - Read, 81H -

Write). By setting bit 11, SuspendClkNotStop, of the HcHardwareConﬁguration

register (20H - Read, A0H - Write), you can also deﬁne such that when the HC goes

into SUSPEND state, its internal clock is stopped or kept running. After HC enters the

SUSPEND State for 1.3 ms, the internal clock will be stopped if bit

SuspendClkNotStop is logic 0.

10.2 HC wakeup from suspended state

There are three methods to wake up the HC from the USB SUSPEND state:

hardware wakeup, software wakeup, and USB bus resume. They are described as

follows:

10.2.1 Wakeup by pin H_WAKEUP

Pins H_SUSPEND and H_WAKEUP provide hardware wakeup, a way of remote

wakeup control for the HC without the need to access the HC internal registers.

H_WAKEUP is an external wakeup control input pin for the HC. After the HC goes

into SUSPEND state, it can be woken up by sending a HIGH level pulse to pin

H_WAKEUP. This will turn on the HC’s internal clock, and set bit 6, ClkReady, of the

HcµPInterrupt register (24H - Read, A4H - Write). Under the SUSPEND state, once

pin H_WAKEUP goes HIGH, after 160 µs, the internal clock will be up. After the

internal clock is up, it will be kept running at least 1.14 ms depending on the status of

pin H_WAKEUP. If pin H_WAKEUP is HIGH, then the internal clock will be kept

running. If pin H_WAKEUP is LOW, then the internal clock can be kept running for

1.14 ms only, unless the microprocessor sets the HC into OPERATIONAL state

during this time.

10.2.2 Wakeup by pin CS (software wakeup)

During the SUSPEND state, an external microprocessor issues the chip select signal

through pin CS to ISP1161. This method of access to ISP1161 internal registers is a

software wakeup.

10.2.3 Wakeup by USB devices

For the USB bus resume, a USB device attached to the root hub port issues a

resume signal to the HC through the USB bus, switching the HC from SUSPEND

state to RESUME State. This will also set the ResumeDetected bit, bit 3 of the

HcInterruptStatus register (03H - Read, 83H - Write).

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No matter which method is used to wake up the HC from SUSPEND state, you must

enable the corresponding interrupt bits before the HC goes into SUSPEND state so

that the microprocessor can receive the correct interrupt request to wake up the HC.

11. The USB device controller (DC)

The Device Controller (DC) in ISP1161 originates from Philips ISP1181 USB

Full-Speed Interface Device IC. The functionality is same as ISP1181 in 16-bit bus

mode. The command and register sets are also the same. Refer also to the ISP1181

datasheet for a description of the operation of ISP1161’s DC. If there is any difference

found in ISP1181 and ISP1161 datasheet in terms of the DC’s functionality, the

ISP1161 datasheet supersedes the content in ISP1181 datasheet.

In general the DC in ISP1161 provides 16 endpoints for USB device implementation.

Each endpoint can be allocated an amount of RAM space in the on-chip Ping-Pong

Buffer RAM. Note: the Ping-Pong buffer RAM for the DC is independent of the buffer

RAM in the HC. When the buffer RAM is full, the DC will transfer the data in the buffer

RAM to the USB bus. When the buffer RAM is empty, an interrupt is generated to

notify the microprocessor to feed in the data. The transfer of data between the

microprocessor and the DC can be done in Parallel I/O (PIO) mode or in DMA mode.

11.1 DC data transfer operation

The following session explains how the DC of ISP1161 handles an IN data transfer

and an OUT data transfer. In Device mode, ISP1161 acts as a USB device: an IN

data transfer means transfer from ISP1161 to an external USB Host (through the

upstream port) and an OUT transfer means transfer from external USB Host to

ISP1161.

11.1.1 IN data transfer

The arrival of the IN token is detected by the SIE by decoding the PID.

•

The SIE also checks for the device number and endpoint number and veriﬁes

whether they are ok.

If the endpoint is enabled, the SIE checks the contents of the Endpoint Status

register. If the endpoint is full, the contents of the FIFO are sent during the data

phase, else a NAK handshake is sent.

•

After the data phase, the SIE expects a handshake (ACK) from the host (except for

ISO endpoints).

•

On receiving the handshake (ACK), the SIE updates the interrupt register

contents, which in turn generates an interrupt to the microprocessor. The Last

Transaction Register (LTR) status is updated and the buffer is set to zero in the

Endpoint Status Register. If it fails to get a handshake, a timeout error is generated

and the LTR status is updated accordingly. For ISO endpoints, the interrupt and

LTR status are updated as soon as data are sent, since there is no handshake

phase.

On receiving an interrupt, the microprocessor reads the interrupt register. It will

know which endpoint has generated the interrupt and reads the contents of the

corresponding Endpoint Status register. If the buffer is empty, it ﬁlls up the buffer,

so that data can be sent by the SIE at the next IN token phase.

•

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11.1.2 OUT data transfer

The arrival of the OUT token is detected by the SIE by decoding the PID.

•

The SIE also checks for the device number and endpoint number and veriﬁes

whether they are ok.

If the endpoint is enabled, the SIE checks the contents of the Endpoint Status

register. If the endpoint is empty, the data from USB is stored to FIFO during the

data phase, else a NAK handshake is sent.

•

After the data phase, the SIE sends a handshake (ACK) to the host (except for ISO

endpoints).

•

The SIE updates the contents of the interrupt register, which in turn generates an

interrupt to the microprocessor. The LTR status is updated and the buffer is set to

full in the Endpoint Status Register. For ISO endpoints, interrupt and LTR status

are updated as soon as data is received successfully, since there is no handshake

phase.

On receiving interrupt, the microprocessor reads the interrupt register. It will know

which endpoint has generated the interrupt and reads the content of the

corresponding Endpoint Status register. If the buffer is full, it empties the buffer, so

that data can be received by the SIE at the next OUT token phase.

•

11.2 Device DMA transfer

11.2.1 For OUT endpoint (external USB host to ISP1161’s DC)

When the internal DMA handler is enabled and at least one buffer (Ping or Pong) is

free, the DREQ2 line is asserted. The external DMA controller then starts negotiating

for the bus with ISP1161. As soon as it has access, it asserts the DACK2 line and

starts writing data. The burst length is programmable. When the number of bytes

equal to the burst length has been written, the DREQ2 line is deasserted. As a result,

the DMA controller deasserts the DACK2 line and releases the bus. At that moment

the whole cycle restarts for the next burst.

When the buffer is full, the DREQ2 line will be de-asserted and the buffer is validated

(which means that it will be sent to the host when the next IN token comes in). When

the DMA controller terminates the DMA transfer by asserting EOT, the buffer is also

validated (even if it is not full). In Auto-reload mode, the DMA handler will

automatically restart by asserting its DREQ2 line as soon as a new buffer is available.

If the Auto-reload mode is off, then the DMA handler will be disabled automatically.

For the next DMA transfer, the DMA handler must be reenabled.

11.2.2 For IN endpoint (ISP1161’s DC to external USB host)

When the internal DMA handler is enabled and at least one buffer is full, the DREQ2

line is asserted. The external DMA controller then starts negotiating for the bus with

other parties and as soon as it has access, it asserts the DACK2 line and starts

reading the data. The burst length is programmable. When the number of bytes equal

to the burst length has been read, the DREQ2 line is deasserted. As a result, the

DMA controller deasserts the DACK2 line and releases the bus. At that moment the

whole cycle restarts for the next burst. When all data are read, the DREQ2 line will be

deasserted and the buffer is cleared (which means that it can be overwritten when a

new packet comes in).

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When the DMA controller terminates the DMA transfer by asserting EOT and

Auto-reload mode is off, the buffer is also cleared (even if not all data are read) and

the DMA handler is disabled automatically. For the next DMA transfer, the DMA

controller as well as the DMA handler must be re-enabled. However in Auto-reload

mode, the DMA handler will automatically restart by reasserting the DREQ2 line,

without any loss of data.

11.3 Endpoint descriptions

11.3.1 Endpoints with programmable FIFO size

Each USB device is logically composed of several independent endpoints. An

endpoint acts as a terminus of a communication ﬂow between the host and the

device. At design time each endpoint is assigned a unique number (endpoint

identiﬁer, see Table 7). The combination of the device address (given by the host

during enumeration), the endpoint number and the transfer direction allows each

endpoint to be uniquely referenced.

The ISP1161 has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 conﬁgurable

endpoints, which can be individually deﬁned as interrupt/bulk/isochronous, IN or OUT.

Each enabled endpoint has an associated FIFO, which can be accessed either via

the parallel I/O interface or via DMA.

11.3.2 Endpoint access

Table 7 lists the endpoint access modes and programmability. All endpoints support

I/O mode access. Endpoints 1 to 14 also support DMA access. FIFO DMA access is

selected and enabled via bits EPIDX[3:0] and DMAEN of the DMA Conﬁguration

Register. A detailed description of the DMA operation is given in Section 12.

Table 7: Endpoint access and programmability

Endpoint

identiﬁer

FIFO size (bytes)

Double

buffering

I/O mode

access

DMA mode

access

Endpoint type

0

64 (ﬁxed)

no

yes

no

control OUT^[1]

control IN^[1]

0

64 (ﬁxed)

no

yes

no

1

programmable

supported

programmable

2

3

4

5

6

7

8

9

10

11

12

13

14

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[1] IN: input for the USB host (ISP1161 transmits); OUT: output from the USB host (ISP1161 receives).

[2] The data ﬂow direction is determined by bit EPDIR in the Endpoint Conﬁguration Register.

[3] The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes.

11.3.3 Endpoint FIFO size

The size of the FIFO determines the maximum packet size that the hardware can

support for a given endpoint. Only enabled endpoints are allocated space in the

shared FIFO storage, disabled endpoints have zero bytes. Table 8 lists the

programmable FIFO sizes.

The following bits in the Endpoint Conﬁguration Register (ECR) affect FIFO

allocation:

Endpoint enable bit (FIFOEN)

•

Size bits of an enabled endpoint (FFOSZ[3:0])

Isochronous bit of an enabled endpoint (FFOISO).

Remark: Register changes that affect the allocation of the shared FIFO storage

among endpoints must not be made while valid data is present in any FIFO of the

enabled endpoints. Such changes will render all FIFO contents undeﬁned.

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Table 8: Programmable FIFO size

FFOSZ[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Non-isochronous

8 bytes

Isochronous

16 bytes

32 bytes

64 bytes

reserved

32 bytes

48 bytes

64 bytes

96 bytes

128 bytes

160 bytes

192 bytes

256 bytes

320 bytes

384 bytes

512 bytes

640 bytes

768 bytes

896 bytes

1023 bytes

Each programmable FIFO can be conﬁgured independently via its ECR, but the total

physical size of all enabled endpoints (IN plus OUT) must not exceed 2462 bytes

(512 bytes for non-isochronous FIFOs).

Table 9 shows an example of a conﬁguration ﬁtting in the maximum available space of

2462 bytes. The total number of logical bytes in the example is 1311. The physical

storage capacity used for double buffering is managed by the device hardware and is

transparent to the user.

Table 9: Memory conﬁguration example

Physical size

(bytes)

Logical size

(bytes)

Endpoint description

64

control IN (64 byte ﬁxed)

64

control OUT (64 byte ﬁxed)

double-buffered 1023-byte isochronous endpoint

16-byte interrupt OUT

2046

16

1023

16

16-byte interrupt IN

128

64

double-buffered 64-byte bulk OUT

double-buffered 64-byte bulk IN

64

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11.3.4 Endpoint initialization

In response to the standard USB request Set Interface, the ﬁrmware must program all

16 ECRs of the ISP1161 in sequence (see Table 7), whether the endpoints are

enabled or not. The hardware will then automatically allocate FIFO storage space.

If all endpoints have been conﬁgured successfully, the ﬁrmware must return an empty

packet to the control IN endpoint to acknowledge success to the host. If there are

errors in the endpoint conﬁguration, the ﬁrmware must stall the control IN endpoint.

When reset by hardware or via the USB bus, the ISP1161 DC disables all endpoints

and clears all ECRs, except for the control endpoint which is ﬁxed and always

enabled.

Endpoint initialization can be done at any time; however, it is valid only after

enumeration.

11.3.5 Endpoint I/O mode access

When an endpoint event occurs (a packet is transmitted or received), the associated

endpoint interrupt bits (EPn) of the Interrupt Register (IR) will be set by the SIE. The

ﬁrmware then responds to the interrupt and selects the endpoint for processing.

The endpoint interrupt bit will be cleared by reading the Endpoint Status Register

(ESR). The ESR also contains information on the status of the endpoint buffer.

For an OUT (= receive) endpoint, the packet length and packet data can be read from

ISP1161 using the Read Buffer command. When the whole packet has been read,

the ﬁrmware sends a Clear Buffer command to enable the reception of new packets.

For an IN (= transmit) endpoint, the packet length and data to be sent can be written

to ISP1161 DC using the Write Buffer command. When the whole packet has been

written to the buffer, the ﬁrmware sends a Validate Buffer command to enable data

transmission to the host.

11.3.6 Special actions on control endpoints

Control endpoints require special ﬁrmware actions. The arrival of a SETUP packet

ﬂushes the IN buffer and disables the Validate Buffer and Clear Buffer commands for

the control IN and OUT endpoints. The microcontroller needs to re-enable these

commands by sending an Acknowledge Setup command to both control endpoints.

This ensures that the last SETUP packet stays in the buffer and that no packets can

be sent back to the host until the microcontroller has explicitly acknowledged that it

has seen the SETUP packet.

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12. DMA transfer for the Device Controller

Direct Memory Access (DMA) is a method to transfer data from one location to

another in a computer system, without intervention of the Central Processor Unit

(CPU). Many different implementations of DMA exist. The ISP1161 DC supports two

methods:

8237 compatible mode: based on the DMA subsystem of the IBM personal

computers (PC, AT and all its successors and clones); this architecture uses the

Intel 8237 DMA controller and has separate address spaces for memory and I/O

•

DACK-only mode: based on the DMA implementation in some embedded RISC

processors, which has a single address space for both memory and I/O.

•

The ISP1161 DC supports DMA transfer for all 14 conﬁgurable endpoints (see

Table 7). Only one endpoint at a time can be selected for DMA transfer. The DMA

operation of the ISP1161 DC can be interleaved with normal I/O mode access to

other endpoints.

The following features are supported:

Single-cycle or burst transfers (up to 16 bytes per cycle)

Programmable transfer direction (read or write)

•

Multiple End-Of-Transfer (EOT) sources: external pin, internal conditions,

short/empty packet

Programmable signal levels on pins DREQ2, DACK2 and EOT.

•

12.1 Selecting an endpoint for DMA transfer

The target endpoint for DMA access is selected via bits EPDIX[3:0] in the DMA

Conﬁguration Register, as shown in Table 10. The transfer direction (read or write) is

automatically set by bit EPDIR in the associated ECR, to match the selected endpoint

type (OUT endpoint: read; IN endpoint: write).

Asserting input DACK2 automatically selects the endpoint speciﬁed in the DMA

Conﬁguration Register, regardless of the current endpoint used for I/O mode access.

Table 10: Endpoint selection for DMA transfer

Endpoint

identiﬁer

EPIDX[3:0]

Transfer direction

EPDIR = 0

EPDIR = 1

IN: write

1

2

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

OUT: read

3

4

5

6

7

8

9

10

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Table 10: Endpoint selection for DMA transfer…continued

Endpoint

identiﬁer

EPIDX[3:0]

Transfer direction

EPDIR = 0

EPDIR = 1

IN: write

11

12

13

14

1100

1101

1110

1111

OUT: read

12.2 8237 compatible mode

The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware

Conﬁguration Register (see Table 81). The pin functions for this mode are shown in

Table 11.

Table 11: 8237 compatible mode: pin functions

Symbol

DREQ2

DACK2

Description

I/O

O

I

Function

DC’s DMA request

ISP1161 DC requests a DMA transfer

DMA controller conﬁrms the transfer

DC’s DMA

acknowledge

EOT

RD

end of transfer

read strobe

I

DMA controller terminates the transfer

instructs ISP1161 DC to put data on the

bus

WR

write strobe

I

instructs ISP1161 DC to get data from the

bus

The DMA subsystem of an IBM compatible PC is based on the Intel 8237 DMA

controller. It operates as a ‘ﬂy-by’ DMA controller: the data is not stored in the DMA

controller, but it is transferred between an I/O port and a memory address. A typical

example of ISP1161 DC in 8237 compatible DMA mode is given in Figure 38.

The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and

DACK (DMA Acknowledge). General control signals are HRQ (Hold Request), HLDA

(Hold Acknowledge) and EOP (End-Of-Process). The bus operation is controlled via

MEMR (Memory Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write).

MEMR

RAM

D0 to D15

MEMW

DMA

CONTROLLER

8237

ISP1161

DEVICE

CPU

CONTROLLER

DREQ2

DACK2

DREQ

HRQ

HLDA

DACK

HLDA

RD

IOR

WR

IOW

004aaa009

Fig 38. ISP1161’s device controller in 8237 compatible DMA mode.

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The following example shows the steps which occur in a typical DMA transfer:

1. ISP1161 DC receives a data packet in one of its endpoint FIFOs; the packet must

be transferred to memory address 1234H.

2. ISP1161 DC asserts the DREQ2 signal requesting the 8237 for a DMA transfer.

3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.

4. After completing the current instruction cycle, the CPU places the bus control

signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and

asserts HLDA to inform the 8237 that it has control of the bus.

5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR

control signals.

6. The 8237 asserts DACK to inform the ISP1161 DC that it will start a DMA

transfer.

7. The ISP1161 DC now places the word to be transferred on the data bus lines,

because its RD signal was asserted by the 8237.

8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This

latches and stores the word at the desired memory location. It also informs the

ISP1161 DC that the data on the bus lines has been transferred.

9. The ISP1161 DC de-asserts the DREQ2 signal to indicate to the 8237 that DMA

is no longer needed. In Single cycle mode this is done after each word, in Burst

mode following the last transferred word of the DMA cycle.

10. The 8237 de-asserts the DACK output indicating that the ISP1161 must stop

placing data on the bus.

11. The 8237 places the bus control signals (MEMR, MEMW, IOR and IOW) and the

address lines in three-state and de-asserts the HRQ signal, informing the CPU

that it has released the bus.

12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating

the bus control lines (MEMR, MEMW, IOR and IOW) and the address lines, the

CPU resumes the execution of instructions.

For a typical bulk transfer the above process is repeated, once for each byte. After

each byte the address register in the DMA controller is incremented and the byte

counter is decremented. When using 16-bit DMA the number of transfers is 32 and

address incrementing and byte counter decrementing is done by 2 for each word.

12.3 DACK-only mode

The DACK-only DMA mode is selected by setting bit DAKOLY in the Hardware

Conﬁguration Register (see Table 81). The pin functions for this mode are shown in

Table 12. A typical example of ISP1161 DC in DACK-only DMA mode is given in

Figure 39.

Table 12: DACK-only mode: pin functions

Symbol

DREQ2

DACK2

Description

I/O

O

I

Function

DC’s DMA request

ISP1161 DC requests a DMA transfer

DC’s DMA

acknowledge

DMA controller conﬁrms the transfer;

also functions as data strobe

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Table 12: DACK-only mode: pin functions…continued

Symbol

Description

End-Of-Transfer

read strobe

I/O

Function

EOT

RD

I

DMA controller terminates the transfer

not used

WR

write strobe

In DACK-only mode the ISP1161 DC uses the DACK2 signal as a data strobe. Input

signals RD and WR are ignored. This mode is used in CPU systems that have a

single address space for memory and I/O access. Such systems have no separate

MEMW and MEMR signals: the RD and WR signals are also used as memory data

strobes.

ISP1161

DEVICE

CONTROLLER

DMA

CONTROLLER

CPU

DREQ2

DACK2

DREQ

DACK

HRQ

HLDA

RD

RAM

D0 to D15

WR

004aaa010

Fig 39. ISP1161’s device controller in DACK-only DMA mode.

12.4 End-Of-Transfer conditions

12.4.1 Bulk endpoints

A DMA transfer to/from a bulk endpoint can be terminated by any of the following

conditions (bit names refer to the DMA Conﬁguration Register, see Table 85):

An external End-Of-Transfer signal occurs on input EOT

•

The internal DMA Counter Register reaches zero (CNTREN = 1)

A short/empty packet is received on an enabled OUT endpoint (SHORTP = 1)

DMA operation is disabled by clearing bit DMAEN.

External EOT: When reading from an OUT endpoint, an external EOT will stop the

DMA operation and clear any remaining data in the current FIFO. For a double-

buffered endpoint the other (inactive) buffer is not affected.

When writing to an IN endpoint, an EOT will stop the DMA operation and the data

packet in the FIFO (even if it is smaller than the maximum packet size) will be sent to

the USB host at the next IN token.

DMA Counter Register zero: An EOT from the DMA Counter Register is enabled by

setting bit CNTREN in the DMA Conﬁguration Register. The ISP1161 has a 16-bit

DMA Counter Register, which speciﬁes the number of bytes to be transferred. When

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DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from

the DMA Counter Register. When the internal counter reaches zero an EOT condition

is generated and the DMA operation stops.

Short/empty packet: Normally, the transfer byte count must be set via a control

endpoint before any DMA transfer takes place. When a short/empty packet has been

enabled as EOT indicator (SHORTP = 1), the transfer size is determined by the

presence of a short/empty packet in the data. This mechanism permits the use of a

fully autonomous data transfer protocol.

When reading from an OUT endpoint, reception of a short/empty packet at an OUT

token will stop the DMA operation after transferring the data bytes of this packet.

When writing to an IN endpoint, a short packet transferred at an IN token will stop the

DMA operation after all bytes have been transferred. If the number of bytes in the

buffer is zero, ISP1161 DC will automatically send an empty packet.

Table 13: Summary of EOT conditions for a bulk endpoint

EOT condition

EOT input

OUT endpoint

IN endpoint

EOT is active

DMA Counter Register

Short packet

counter reaches zero

short packet is received and counter reaches zero in the

transferred middle of the buffer

empty packet is received and empty packet is automatically

Empty packet

transferred

appended when needed^[1]

DMAEN bit in DMA

DMAEN = 0

Conﬁguration Register

[1] If short/empty packet EOT is enabled (SHORTP = 1 in DMA Conﬁguration Register) and DMA

Counter Register is zero.

12.4.2 Isochronous endpoints

A DMA transfer to/from an isochronous endpoint can be terminated by any of the

following conditions (bit names refer to the DMA Conﬁguration Register, see

Table 85):

An external End-Of-Transfer signal occurs on input EOT

The internal DMA Counter Register reaches zero (CNTREN = 1)

An End-Of-Packet (EOP) signal is detected

•

DMA operation is disabled by clearing bit DMAEN.

Table 14: Recommended EOT usage for isochronous endpoints

EOT condition

OUT endpoint

do not use

preferred

IN endpoint

preferred

EOT input active

DMA Counter Register zero

End-Of-Packet

preferred

do not use

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13. HC registers

The HC contains a set of on-chip control registers. These registers can be read or

written by the Host Controller Driver (HCD). The Control and Status register sets,

Frame Counter register sets, and Root Hub register sets are grouped under the

category of HC Operational Registers (32 bits). These operational registers are made

compatible to OpenHCI (Host Controller Interface) Operational Registers. This makes

a provision that the OpenHCI HCD can be ported to ISP1161 easily.

Reserved bits may be deﬁned in future releases of this speciﬁcation. To ensure

interoperability, the HCD that does not use a reserved ﬁeld must not assume that the

reserved ﬁeld contains logic 0. Furthermore, the HCD must always preserve the

values of the reserved ﬁeld. When a R/W register is modiﬁed, the HCD must ﬁrst read

the register, modify the bits desired, and then write the register with the reserved bits

still containing the read value. Alternatively, the HCD can maintain an in-memory

copy of previously written values that can be modiﬁed and then written to the HC

register. When a write to set or clear the register is written, bits written to reserved

ﬁelds must be logic 0.

As shown in Table 15, the offset locations (the commands for reading registers) of

these Operational Registers (the 32-bit registers) are similar to those deﬁned in the

OHCI speciﬁcation, however, the addresses are equal to offset DIV 4:

Table 15: HC Control Register summary

Command (Hex) Register

Width Functionality

Read

00

01

02

03

04

05

0D

0E

0F

11

12

13

14

15

16

20

21

22

24

25

Write

N/A

81

HcRevision

32

16

HC Control and Status Registers

HcControl

82

HcCommandStatus

HcInterruptStatus

HcInterruptEnable

HcInterruptDisable

HcFmInterval

83

84

85

8D

N/A

91

HC Frame Counter Registers

HC Root Hub Registers

HcFmRemaining

HcFmNumber

HcLSThreshold

HcRhDescriptorA

HcRhDescriptorB

HcRhStatus

92

93

94

95

HcRhPortStatus[1]

HcRhPortStatus[2]

HcHardwareConﬁguration

HcDMAConﬁguration

HcTransferCounter

HcµPInterrupt

96

A0

A1

A2

A4

A5

HC DMA and Interrupt Control

Registers

HcµPInterruptEnable

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Table 15: HC Control Register summary…continued

Command (Hex) Register Width Functionality

Read

Write

N/A

A8

27

HcChipID

16

HC Miscellaneous Registers

28

HcScratch

N/A

2A

2B

2C

2D

2E

40

A9

HcSoftwareReset

HcITLBufferLength

HcATLBufferLength

HcBufferStatus

AA

HC Buffer RAM Control Registers

AB

N/A

C0

HcReadBackITL0Length

HcReadBackITL1Length

HcITLBufferPort

HcATLBufferPort

41

C1

13.1 HC control and status registers

13.1.1 HcRevision Register

Table 16: HcRevision Register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

00H

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

00H

R

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

00H

R

7

6

5

4

3

2

1

0

Symbol

Reset

Access

REV

1

0

1

0

0-

R

Table 17: HcRevision Register: bit description

Bit

Symbol

−

Description

31 to 8

7 to 0

Reserved

REV[7:0]

Revision: This read-only ﬁeld contains the BCD representation of

the version of the HCI speciﬁcation that is implemented by this HC.

For example, a value of 11H corresponds to version 1.1. All HC

implementations that are compliant with this speciﬁcation will have

a value of 10H.

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Code (Hex): 00 — read only

13.1.2 HcControl Register

The HcControl register deﬁnes the operating modes for the HC. Most ﬁelds are

modiﬁed only by the HCD, except for HostControllerFunctionalState (HCFS) and

RemoteWakeupConnected (RWC).

Table 18: HcControl Register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

00H

R/W

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

00H

R/W

10

R/W

9

R/W

15

14

13

12

11

8

Symbol

Reset

Access

Bit

reserved

RWE

0

RWC

0

reserved

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

0

R/W

2

R/W

1

Symbol

Reset

Access

HCFS[1:0]

reserved

0

R/W

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Table 19: HcControl Register: bit description

Bit

Symbol

-

Description

31 to 11

10

reserved

RWE

RemoteWakeupEnable: This bit is used by the HCD to enable or

disable the remote wakeup feature upon the detection of upstream

resume signaling. When this bit is set and the ResumeDetected bit

in HcInterruptStatus is set, a remote wakeup is signaled to the host

system. Setting this bit has no impact on the generation of

hardware interrupt.

9

RWC

RemoteWakeupConnected: This bit indicates whether the HC

supports remote wakeup signaling. If remote wakeup is supported

and used by the system, it is the responsibility of system ﬁrmware

to set this bit during POST. The HC clears the bit upon a hardware

reset but does not alter it upon a software reset. Remote wakeup

signaling of the host system is host-bus-speciﬁc and is not

described in this speciﬁcation.

8

-

reserved

7 to 6

HCFS

HostControllerFunctionalState for USB:

00B — USBRESET

01B — USBRESUME

10B — USBOPERATIONAL

11B — USBSUSPEND

A transition to USBOPERATIONAL from another state causes

start-of-frame (SOF) generation to begin 1 ms later. The HCD may

determine whether the HC has begun sending SOFs by reading

the StartofFrame ﬁeld of HcInterruptStatus.

This ﬁeld may be changed by the HC only when in the

USBSUSPEND state. The HC may move from the USBSUSPEND

state to the USBRESUME state after detecting the resume

signaling from a downstream port.

The HC enters USBSUSPEND after a software reset; it enters

USBRESET after a hardware reset. The latter also resets the Root

Hub and asserts subsequent reset signaling to downstream ports.

5 to 0

-

reserved

Code (Hex): 01 — read

Code (Hex): 81 — write

13.1.3 HcCommandStatus Register

The HcCommandStatus register is used by the HC to receive commands issued by

the HCD, and it also reﬂects the HC’s current status. To the HCD, it appears to be a

‘write to set’ register. The HC must ensure that bits written as logic 1 become set in

the register while bits written as logic 0 remain unchanged in the register. The HCD

may issue multiple distinct commands to the HC without concern for corrupting

previously issued commands. The HCD has normal read access to all bits.

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The SchedulingOverrunCount ﬁeld indicates the number of frames with which the HC

has detected the scheduling overrun error. This occurs when the Periodic list does

not complete before EOF. When a scheduling overrun error is detected, the HC

increments the counter and sets the SchedulingOverrun ﬁeld in the HcInterruptStatus

register.

Table 20: HcCommandStatus Register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

00H

R

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

Symbol

Reset

Access

Bit

reserved

R

SOC[1:0]

R

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

00H

R/W

7

6

5

4

3

2

1

0

HCR

0

Symbol

Reset

Access

reserved

0

R/W

Table 21: HcCommandStatus Register: bit description

Bit

Symbol

-

Description

31 to 18

17 to 16

reserved

SOC[1:0]

SchedulingOverrunCount: The ﬁeld is incremented on each

scheduling overrun error. It is initialized to 00B and wraps around

at 11B. It will be incremented when a scheduling overrun is

detected even if SchedulingOverrun in HcInterruptStatus has

already been set. This is used by HCD to monitor any persistent

scheduling problems.

15 to 1

0

-

reserved

HCR

HostControllerReset: This bit is set by HCD to initiate a software

reset of HC. Regardless of the functional state of HC, it moves to

the USBSUSPEND state in which most of the operational registers

are reset except those stated otherwise; e.g., the InterruptRouting

ﬁeld of HcControl, and no Host bus accesses are allowed. This bit

is cleared by HC upon the completion of the reset operation. The

reset operation must be completed within 10 s. This bit, when set,

should not cause a reset to the Root Hub and no subsequent reset

signaling should be asserted to its downstream ports.

Code (Hex): 02 — read

Code (Hex): 82 — write

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13.1.4 HcInterruptStatus Register

This register provides the status of the events that cause hardware interrupts. When

an event occurs, the HC sets the corresponding bit in this register. When a bit

becomes set, a hardware interrupt is generated if the interrupt is enabled in the

HcInterruptEnable register (see Section 13.1.5) and the MasterInterruptEnable bit is

set. The HCD may clear speciﬁc bits in this register by writing logic1 to the bit

positions to be cleared. The HCD may not set any of these bits. The HC will not clear

the bit.

Table 22: HcInteruptStatus Register: bit allocation

Bit

31

23

15

30

22

14

29

21

13

28

20

12

27

19

11

26

18

10

25

17

9

24

16

8

Symbol

Reset

Access

Bit

reserved

00H

R/W

Symbol

Reset

Access

Bit

reserved

00H

R/W

Symbol

Reset

Access

Bit

reserved

00H

R/W

7

reserved

0

6

RHSC

0

5

FNO

0

4

UE

0

3

RD

0

2

SF

0

1

reserved

0

SO

0

Symbol

Reset

Access

R/W

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Table 23: HcInterruptStatus Register: bit description

Bit

Symbol

Description

31 to 8

reserved

7

6

reserved

RHSC

−

RootHubStatusChange: This bit is set when the content of

HcRhStatus or the content of any of

HcRhPortStatus[NumberofDownstreamPort] has changed.

5

4

FNO

UE

FrameNumberOverﬂow: This bit is set when the MSB of

HcFmNumber (bit 15) changes value, from logic 0 to 1 or from

logic 1 to 0.

UnrecoverableError: This bit is set when the HC detects a

system error not related to USB. The HC should not proceed with

any processing nor signaling before the system error has been

corrected. The HCD clears this bit after HC has been reset.

PHCI: Always set to logic 0.

3

2

RD

SF

ResumeDetected: This bit is set when the HC detects that a

device on the USB is asserting resume signaling. It is the transition

from no resume signaling to resume signaling causing this bit to be

set. This bit is not set when HCD sets the USBRESUME state.

StartOfFrame: At the start of each frame, this bit is set by the HC

and an SOF generated.

1

0

-

reserved

SO

SchedulingOverrun: This bit is set when USB schedules for

current frame overruns. A scheduling overrun will also cause the

SchedulingOverrunCount of HcCommandStatus to be

incremented.

Code (Hex): 03 — read

Code (Hex): 83 — write

13.1.5 HcInterruptEnable Register

Each enable bit in the HcInterruptEnable register corresponds to an associated

interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used

to control which events generate a hardware interrupt. When these three conditions

occur:

A bit is set in the HcInterruptStatus register

•

The corresponding bit in the HcInterruptEnable register is set

The MasterInterruptEnable bit is set

then a hardware interrupt is requested on the host bus.

Writing a logic1 to a bit in this register sets the corresponding bit, whereas writing a

logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the

current value of this register is returned.

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Table 24: HcInterruptEnable Register: bit allocation

Bit

31

MIE

0

30

29

28

0

27

reserved

0

26

0

25

0

24

0

Symbol

Reset

Access

Bit

0

R/W

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

00H

R/W

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

00H

R/W

7

reserved

0

6

RHSC

0

5

FNO

0

4

UE

0

3

RD

0

2

SF

0

1

reserved

0

SO

0

Symbol

Reset

Access

R/W

Table 25: HcInterruptEnable Register: bit description

Bit

Symbol

Description

31

MIE

MasterInterruptEnable by the HCD: A logic 0 is ignored by the

HC. A logic 1 enables interrupt generation by events speciﬁed in

other bits of this register.

30 to 8

-

reserved

7

6

-

reserved

RHSC

0 — ignore

1 — enable interrupt generation due to Root Hub Status Change

5

4

3

2

FNO

UE

0 — ignore

1 — enable interrupt generation due to frame Number Overﬂow

0 — ignore

1 — enable interrupt generation due to Unrecoverable Error

RD

SF

0 — ignore

1 — enable interrupt generation due to Resume Detect

0 — ignore

1 — enable interrupt generation due to Start of frame

1

0

-

reserved

SO

0 — ignore

1 — enable interrupt generation due to Scheduling Overrun

Code (Hex): 04 — read

Code (Hex): 84 — write

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13.1.6 HcInterruptDisable Register

Each disable bit in the HcInterruptDisable register corresponds to an associated

interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is

coupled with the HcInterruptEnable register. Thus, writing a logic 1 to a bit in this

register clears the corresponding bit in the HcInterruptEnable register, whereas

writing a logic 0 to a bit in this register leaves the corresponding bit in the

HcInterruptEnable register unchanged. On a read, the current value of the

HcInterruptEnable register is returned.

Table 26: HcInterruptDisable Register: bit allocation

Bit

31

MIE

0

30

29

28

0

27

reserved

0

26

0

25

0

24

0

Symbol

Reset

Access

Bit

0

R/W

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

00H

R/W

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

00H

R/W

7

reserved

0

6

RHSC

0

5

FNO

0

4

UE

0

3

RD

0

2

SF

0

1

reserved

0

SO

0

Symbol

Reset

Access

R/W

Table 27: HcInterruptDisable Register: bit description

Bit

Symbol

Description

31

MIE

A logic 0 is ignored by the HC. A logic 1 disables interrupt

generation due to events speciﬁed in other bits of this register. This

ﬁeld is set after a hardware or software reset.

30 to 8

-

reserved

7

6

-

reserved

RHSC

0 — ignore

1 — disable interrupt generation due to Root Hub Status Change

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Table 27: HcInterruptDisable Register: bit description…continued

Bit

Symbol

Description

5

FNO

0 — ignore

1 — disable interrupt generation due to frame Number Overﬂow

4

3

2

UE

RD

SF

0 — ignore

1 — disable interrupt generation due to Unrecoverable Error

0 — ignore

1 — disable interrupt generation due to Resume Detect

0 — ignore

1 — disable interrupt generation due to Start of frame

1

0

-

reserved

SO

0 — ignore

1 — disable interrupt generation due to Scheduling Overrun

Code (Hex): 05 — read

Code (Hex): 85 — write

13.2 HC frame counter registers

13.2.1 HcFmInterval Register

The HcFmInterval register contains a 14-bit value which indicates the bit time interval

in a frame (that is, between two consecutive SOFs), and a 15-bit value indicating the

full-speed maximum packet size that the HC may transmit or receive without causing

a scheduling overrun. The HCD may carry out minor adjustments on the

FrameInterval by writing a new value over the present one at each SOF. This provides

the programmability necessary for the HC to synchronize with an external clocking

resource and to adjust any unknown local clock offset.

Table 28: HcFmInterval Register: bit allocation

Bit

31

FIT

0

30

29

28

0

27

26

0

25

0

24

0

Symbol

Reset

Access

Bit

FSMPS[14:8]

0

R/W

23

R/W

19

22

0

21

0

20

18

0

17

0

16

0

Symbol

Reset

Access

Bit

FSMPS[7:0]

0

15

0

12

0

R/W

14

0

13

1

11

1

10

1

9

8

Symbol

Reset

Access

Bit

reserved

R/W

FI[13:8]

R/W

1

0

7

6

5

4

3

2

1

0

Symbol

Reset

Access

FI[7:0]

R/W

1

0

1

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Table 29: HcFmInterval Register: bit description

Bit

Symbol

Description

31

FIT

FrameIntervalToggle: The HCD toggles this bit whenever it loads

a new value to FrameInterval.

30 to 16

FSMPS

[14:0]

FSLargestDataPacket: Speciﬁes a value which is loaded into the

Largest Data Packet Counter at the beginning of each frame. The

counter value represents the largest amount of data in bits which

can be sent or received by the HC in a single transaction at any

given time without causing a scheduling overrun. The ﬁeld value is

calculated by the HCD.

15 to 14

13 to 0

-

reserved

FI[13:0]

FrameInterval: Speciﬁes the interval between two consecutive

SOFs in bit times. The nominal value is set to be 11999. The HCD

must store the current value of this ﬁeld before resetting the HC.

By setting the HostControllerReset bit 0 ﬁeld of

HcCommandStatus register will cause the HC to reset this ﬁeld to

its nominal value. HCD may choose to restore the stored value

upon completing the Reset sequence.

Code (Hex): 0D — read

Code (Hex): 8D — write

13.2.2 HcFmRemaining Register

The HcFmRemaining register is a 14-bit down counter showing the bit time remaining

in the current frame.

Table 30: HcFmRemaining Register: bit allocation

Bit

31

FRT

0

30

29

28

0

27

26

0

25

0

24

0

Symbol

Reset

Access

Bit

reserved

0

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

00H

R

15

0

14

0

13

0

12

0

11

0

10

0

9

0

1

0

8

0

Symbol

Reset

Access

Bit

reserved

R

FR[13:8]

R

7

6

5

4

3

2

Symbol

Reset

Access

FR[7:0]

R

0

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Table 31: HcFmRemaining Register: bit description

Bit

Symbol

Description

31

FRT

FrameRemainingToggle: This bit is loaded from the

FrameIntervalToggle ﬁeld of HcFmInterval whenever

FrameRemaining reaches 0. This bit is used by the Host Controller

Driver (HCD) for synchronization between FrameInterval and

FrameRemaining.

30 to 14

13 to 0

-

reserved

FR[13:0]

FrameRemaining: This counter is decremented at each bit time.

When it reaches zero, it is reset by loading the FrameInterval value

speciﬁed in HcFmInterval at the next bit time boundary. When

entering the USBOPERATIONAL state, the HC reloads it with the

content of the FrameInterval part of the HcFmInterval register and

uses the updated value from the next SOF.

Code (Hex): 0E — read

13.2.3 HcFmNumber Register

The HcFmNumber register is a 16-bit counter. It provides a timing reference for

events happening in the HC and the HCD. The HCD may use the 16-bit value

speciﬁed in this register and generate a 32-bit frame number without requiring

frequent access to the register.

Table 32: HCFmNumber Register: bit allocation

Bit

31

30

29

28

20

27

19

26

18

25

17

24

16

Symbol

Reset

Access

Bit

reserved

00H

R

23

22

21

Symbol

Reset

Access

Bit

reserved

00H

R

15

0

14

0

13

0

12

0

11

0

10

0

9

0

1

0

8

0

Symbol

Reset

Access

Bit

FN[15:8]

R

FN[7:0]

R

7

6

5

4

3

2

Symbol

Reset

Access

0

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Table 33: HcFmNumber Register: bit description

Bit

Symbol

−

Description

31 to 16

15 to 0

reserved

FN[15:0]

FrameNumber: This is incremented when HcFmRemaining is

reloaded. It will be rolled over to 0H after FFFFH. When the

USBOPERATIONAL state is entered, this will be incremented

automatically. HC will set the StartofFrame in HcInterruptStatus.

Code (Hex): 0F — read

13.2.4 HcLSThreshold Register

The HcLSThreshold register contains an 11-bit value used by the HC to determine

whether to commit to the transfer of a maximum of 8-byte LS packet before EOF.

Neither the HC nor the HCD is allowed to change this value.

Table 34: HcLSThreshold Register: bit allocation

Bit

31

30

29

28

20

27

19

26

18

25

17

24

16

Symbol

Reset

Access

Bit

reserved

00H

R/W

23

22

21

Symbol

Reset

Access

Bit

reserved

00H

R/W

15

0

14

0

13

reserved

0

12

0

11

0

10

1

9

LST[10:8]

1

8

0

Symbol

Reset

Access

Bit

R/W

LST[7:0]

R/W

7

6

5

4

3

2

1

Symbol

Reset

Access

0

1

0

1

0

Table 35: HcLSThreshold Register: bit description

Bit

Symbol

Description

reserved

31 to 16

15 to 11

10 to 0

−

reserved

LST[10:0]

LSThreshold: Contains a value that is compared to the

FrameRemaining ﬁeld before a low-speed transaction is initiated.

The transaction is started only if FrameRemaining ≥ this ﬁeld. The

value is calculated by the HCD, which considers transmission and

setup overhead.

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Code (Hex): 11 — read

Code (Hex): 91 — write

13.3 HC Root Hub registers

All registers included in this partition are dedicated to the USB Root Hub, which is an

integral part of the HC although it is a functionally separate entity. The Host Controller

Driver (HCD) emulates USBD accesses to the Root Hub via a register interface. The

HCD maintains many USB-deﬁned hub features that are not required to be supported

in hardware. For example, the Hub’s Device, Conﬁguration, Interface, and Endpoint

Descriptors are maintained only in the HCD as well as some static ﬁelds of the Class

Descriptor. The HCD also maintains and decodes the Root Hub’s device address as

well as other trivial operations that they are better suited to software than to

hardware.

The Root Hub registers are developed to maintain the similarity of bit organization

and operation to typical hubs found in the system.

Four registers are deﬁned as follows:

HcRhDescriptorA

HcRhDescriptorB

HcRhStatus

•

HcRhPortStatus[1:NDP]

Each register is read and written as a Dword. These registers are only written during

initialization to correspond with the system implementation. The HcRhDescriptorA

and HcRhDescriptorB registers should be implemented such that they are writeable

regardless of the HCs USB states. HcRhStatus and HcRhPortStatus must be

writeable during the USBOPERATIONAL state.

13.3.1 HcRhDescriptorA Register

The HcRhDescriptorA register is the ﬁrst register of two describing the characteristics

of the Root Hub. Reset values are implementation-speciﬁc (IS). The descriptor length

(11), descriptor type and hub controller current (0) ﬁelds of the hub Class Descriptor

are emulated by the HCD. All other ﬁelds are located in the registers

HcRhDescriptorA and HcRhDescriptorB.

Remark: IS denotes an implementation-speciﬁc reset value for that ﬁeld.

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Table 36: HcRhDescriptorA Register: bit description

Bit

31

23

30

22

29

28

27

26

18

25

17

24

16

Symbol

Reset

Access

Bit

POTPGT[7:0]

IS

R/W

21

20

12

19

Symbol

Reset

Access

Bit

reserved

00H

R/W

15

0

14

13

0

11

OCPM

IS

10

DT

0

9

NPS

IS

8

PSM

IS

Symbol

Reset

Access

Bit

reserved

NOCP

IS

0

R/W

6

R/W

4

R/W

3

R

R/W

1

R/W

0

7

5

2

Symbol

Reset

Access

NDP[7:0]

IS

R

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Table 37: HcRhDescriptorA Register: bit description

Bit

Symbol

Description

31 to 24

POTPGT

[7:0]

PowerOnToPowerGoodTime: This byte speciﬁes the duration

HCD has to wait before accessing a powered-on port of the Root

Hub. It is implementation-speciﬁc (IS). The unit of time is 2 ms.

The duration is calculated as POTPGT × 2 ms.

23 to 13

12

-

reserved

NOCP

NoOverCurrentProtection: This bit describes how the

overcurrent status for the Root Hub ports are reported. When this

bit is cleared, the OverCurrentProtectionMode ﬁeld speciﬁes

global or per-port reporting.

0 — overcurrent status is reported collectively for all downstream

ports

1 — no overcurrent protection supported

11

OCPM

OverCurrentProtectionMode: This bit describes how the

overcurrent status for the Root Hub ports is reported. At reset, this

ﬁeld should reﬂect the same mode as PowerSwitchingMode. This

ﬁeld is valid only if the NoOverCurrentProtection ﬁeld is cleared.

0 — overcurrent status is reported collectively for all downstream

ports

1 — overcurrent status is reported on a per-port basis

10

9

DT

DeviceType: This bit speciﬁes that the Root Hub is not a

compound device—it is not permitted. This ﬁeld should always

read/write 0.

NPS

NoPowerSwitching: These bits are used to specify whether

power switching is supported or ports are always powered. It is

implementation-speciﬁc. When this bit is cleared, the bit

PowerSwitchingMode speciﬁes global or per-port switching.

0 — ports are power switched

1 — ports are always powered on when the HC is powered on

8

PSM

PowerSwitchingMode: This bit is used to specify how the power

switching of the Root Hub ports is controlled. It is

implementation-speciﬁc. This ﬁeld is valid only if the

NoPowerSwitching ﬁeld is cleared.

0 — all ports are powered at the same time

1 — each port is powered individually. This mode allows port

power to be controlled by either the global switch or per-port

switching. If the bit PortPowerControlMask is set, the port

responds to only port power commands (Set/ClearPortPower). If

the port mask is cleared, then the port is controlled only by the

global power switch (Set/ClearGlobalPower).

7 to 0

NDP[7:0]

NumberDownstreamPorts: These bits specify the number of

downstream ports supported by the Root Hub. It is

implementation-speciﬁc. The minimum number of ports is 1. The

maximum number of ports supported by OpenHCI is 2.

Code (Hex): 12 — read

Code (Hex): 92 — write

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13.3.2 HcRhDescriptorB Register

The HcRhDescriptorB register is the second register of two describing the

characteristics of the Root Hub. These ﬁelds are written during initialization to

correspond with the system implementation. Reset values are

implementation-speciﬁc (IS).

Table 38: HcRhDescriptorB Register: bit allocation

Bit

31

23

15

7

30

22

14

6

29

21

13

5

28

27

26

18

10

2

25

17

9

24

16

8

Symbol

Reset

Access

Bit

PPCM[15:8]

IS

R/W

20

12

4

19

11

3

Symbol

Reset

Access

Bit

PPCM[7:0]

IS

R/W

Symbol

Reset

Access

Bit

DR[15:8]

IS

R/W

1

0

Symbol

Reset

Access

DR[7:0]

IS

R/W

Table 39: HcRhDescriptorB Register: bit description

Bit

Symbol

Description

31 to 16

PPCM

[15:0]

PortPowerControlMask: Each bit indicates whether a port is

affected by a global power control command when

PowerSwitchingMode is set. When set, the port’s power state is

only affected by per-port power control (Set/ClearPortPower).

When cleared, the port is controlled by the global power switch

(Set/ClearGlobalPower). If the device is conﬁgured to global

switching mode (PowerSwitchingMode = 0), this ﬁeld is not valid.

Bit 0 — reserved

Bit 1 — Ganged-power mask on Port #1

Bit 2 — Ganged-power mask on Port #2

...

Bit 15 — Ganged-power mask on Port #15

15 to 0

DR

[15:0]

DeviceRemovable: Each bit is dedicated to a port of the Root

Hub. When cleared, the attached device is removable. When set,

the attached device is not removable.

Bit 0 — reserved

Bit 1 — Device attached to Port #1

Bit 2 — Device attached to Port #2

...

Bit 15 — Device attached to Port #15

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Code (Hex): 13 — read

Code (Hex): 93 — write

13.3.3 HcRhStatus Register

The HcRhStatus register is divided into two parts. The lower word of a Dword

represents the Hub Status ﬁeld and the upper word represents the Hub Status

Change ﬁeld. Reserved bits should always be written as logic 0.

Table 40: HcRhStatus Register: bit allocation

Bit

31

CRWE

N/A

W

30

29

28

27

reserved

N/A

26

25

24

Symbol

Reset

Access

Bit

N/A

23

22

21

20

19

18

17

CCIC

0

16

LPSC

0

Symbol

Reset

Access

Bit

reserved

N/A

R/W

9

R/W

8

15

DRWE

0

14

0

13

0

12

0

11

10

0

Symbol

Reset

Access

Bit

reserved

0

-

0

R/W

7

6

5

4

3

2

1

OCI

0

Symbol

Reset

Access

reserved

N/A

LPS

0

R

R/W

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Table 41: HcRhStatus Register: bit description

Bit

Symbol

Description

31

CRWE

On write—ClearRemoteWakeupEnable: Writing a logic 1 clears

DeviceRemoveWakeupEnable. Writing a logic 0 has no effect.

30 to 18

17

-

reserved

CCIC

OverCurrentIndicatorChange: This bit is set by hardware when a

change has occurred to the OCI ﬁeld of this register. The HCD

clears this bit by writing a logic 1. Writing a logic 0 has no effect.

16

LPSC

On read—LocalPowerStatusChange: The Root Hub does not

support the local power status feature. Therefore, this bit is always

read as logic 0.

On write—SetGlobalPower: In global power mode

(PowerSwitchingMode=0), this bit is written to logic 1 to turn on

power to all ports (clear PortPowerStatus). In per-port power

mode, it sets PortPowerStatus only on ports whose bit

PortPowerControlMask is not set. Writing a logic 0 has no effect.

15

DRWE

On read—DeviceRemoteWakeupEnable: This bit enables the bit

ConnectStatusChange as a resume event, causing a state

transition USBSUSPEND to USBRESUME and setting the

ResumeDetected interrupt.

0 — ConnectStatusChange is not a remote wakeup event

1 — ConnectStatusChange is a remote wakeup event

On write—SetRemoteWakeupEnable: Writing a logic 1 sets

DeviceRemoveWakeupEnable. Writing a logic 0 has no effect.

14 to 2

1

-

reserved

OCI

OverCurrentIndicator: This bit reports overcurrent conditions

when global reporting is implemented. When set, an overcurrent

condition exists. When clear, all power operations are normal. If

per-port overcurrent protection is implemented this bit is always

logic 0.

0

LPS

On read—LocalPowerStatus: The Root Hub does not support the

local power status feature. Therefore, this bit is always read as

logic 0.

On write—ClearGlobalPower: In global power mode

(PowerSwitchingMode = 0), this bit is written to logic 1 to turn off

power to all ports (clear PortPowerStatus). In per-port power

mode, it clears PortPowerStatus only on ports whose

PortPowerControlMask bit is not set. Writing a logic 0 has no

effect.

Code (Hex): 14 — read

Code (Hex): 94 — write

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13.3.4 HcRhPortStatus[1:2]

The HcRhPortStatus[1:2] register is used to control and report port events on a

per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus

registers that are implemented in hardware. The lower word is used to reﬂect the port

status, whereas the upper word reﬂects the status change bits. Some status bits are

implemented with special write behavior. If a transaction (token through handshake)

is in progress when a write to change port status occurs, the resulting port status

change must be postponed until the transaction completes. Reserved bits should

always be written logic 0.

Table 42: HcRhPortStatus[1:2] Register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

00H

R/W

23

0

22

reserved

0

21

0

20

19

OCIC

0

18

PSSC

0

17

PESC

0

16

CSC

0

Symbol

Reset

Access

Bit

PRSC

0

R/W

14

R/W

12

R/W

11

R/W

10

R/W

9

R/W

8

15

13

Symbol

Reset

Access

Bit

reserved

LSDA

X

PPS

0

N/A

R/W

1

R/W

0

7

6

reserved

0

5

4

3

POCI

0

2

Symbol

Reset

Access

PRS

0

PSS

0

PES

0

CCS

0

R/W

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Table 43: HcRhPortStatus[1:2] Register: bit description

Bit

Symbol

-

Description

31 to 21

20

reserved

PRSC

PortResetStatusChange: This bit is set at the end of the 10 ms

port reset signal. The HCD writes a logic 1 to clear this bit. Writing

a logic 0 has no effect.

0 — port reset is not complete

1 — port reset is complete

19

18

OCIC

PSSC

PortOverCurrentIndicatorChange: This bit is valid only if

overcurrent conditions are reported on a per-port basis. This bit is

set when Root Hub changes the PortOverCurrentIndicator bit. The

HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect.

0 — no change in PortOverCurrentIndicator

1 — PortOverCurrentIndicator has changed

PortSuspendStatusChange: This bit is set when the full resume

sequence has been completed. This sequence includes the 20 s

resume pulse, LS EOP, and 3 ms re-synchronization delay. The

HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect.

This bit is also cleared when ResetStatusChange is set.

0 — resume is not completed

1 — resume is completed

17

16

PESC

CSC

PortEnableStatusChange: This bit is set when hardware events

cause the PortEnableStatus bit to be cleared. Changes from HCD

writes do not set this bit. The HCD writes a logic 1 to clear this bit.

Writing a logic 0 has no effect.

0 — no change in PortEnableStatus

1 — change in PortEnableStatus

ConnectStatusChange: This bit is set whenever a connect or

disconnect event occurs. The HCD writes a logic 1 to clear this bit.

Writing a logic 0 has no effect. If CurrentConnectStatus is cleared

when a SetPortReset, SetPortEnable, or SetPortSuspend write

occurs, this bit is set to force the driver to re-evaluate the

connection status since these writes should not occur if the port is

disconnected.

0 — no change in CurrentConnectStatus

1 — change in CurrentConnectStatus

Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only

after a Root Hub reset to inform the system that the device is

attached.

15 to 10

9

-

reserved

LSDA

(read) LowSpeedDeviceAttached: This bit indicates the speed of

the device attached to this port. When set, a low-speed device is

attached to this port. When clear, a full-speed device is attached to

this port. This ﬁeld is valid only when the CurrentConnectStatus is

set.

0 — full-speed device attached

1 — low-speed device attached

(write) ClearPortPower: The HCD clears the PortPowerStatus bit

by writing a logic 1 to this bit. Writing a logic 0 has no effect.

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Table 43: HcRhPortStatus[1:2] Register: bit description…continued

Bit

Symbol

Description

8

PPS

(read) PortPowerStatus: This bit reﬂects the port power status,

regardless of the type of power switching implemented. This bit is

cleared if an overcurrent condition is detected.

The HCD sets this bit by writing SetPortPower or SetGlobalPower.

The HCD clears this bit by writing ClearPortPower or

ClearGlobalPower. Which power control switches are enabled is

determined by PowerSwitchingMode.

In the global switching mode (PowerSwitchingMode = 0), only

Set/ClearGlobalPower controls this bit. In per-port power switching

(PowerSwitchingMode = 1), if the PortPowerControlMask[NDP] bit

for the port is set, only Set/ClearPortPower commands are

enabled. If the mask is not set, only Set/ClearGlobalPower

commands are enabled.

When port power is disabled, CurrentConnectStatus,

PortEnableStatus, PortSuspendStatus, and PortResetStatus

should be reset.

0 — port power is off

1 — port power is on

(write) SetPortPower: The HCD writes a logic 1 to set the

PortPowerStatus bit. Writing a logic 0 has no effect.

Remark: This bit always reads logic 1 if power switching is not

supported.

7 to 5

4

-

reserved

PRS

(read) PortResetStatus: When this bit is set by a write to

SetPortReset, port reset signaling is asserted. When reset is

completed, this bit is cleared when PortResetStatusChange is set.

This bit cannot be set if CurrentConnectStatus is cleared.

0 — port reset signal is not active

1 — port reset signal is active

(write) SetPortReset: The HCD sets the port reset signaling by

writing a 1 to this bit. Writing a 0 has no effect. If

CurrentConnectStatus is cleared, this write does not set

PortResetStatus but instead sets ConnectStatusChange. This

informs the driver that it attempted to reset a disconnected port.

3

POCI

(read) PortOverCurrentIndicator: This bit is valid only when the

Root Hub is conﬁgured in such a way that overcurrent conditions

are reported on a per-port basis. If per-port overcurrent reporting

is not supported, this bit is set to logic 0. If cleared, all power

operations are normal for this port. If set, an overcurrent condition

exists on this port. This bit always reﬂects the overcurrent input

signal

0 — no overcurrent condition

1 — overcurrent condition detected

(write) ClearSuspendStatus: The HCD writes a logic 1 to initiate

a resume. Writing a logic 0 has no effect. A resume is initiated only

if PortSuspendStatus is set.

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Table 43: HcRhPortStatus[1:2] Register: bit description…continued

Bit

Symbol

Description

2

PSS

(read) PortSuspendStatus: This bit indicates whether the port is

suspended or in the resume sequence. It is set by a

SetSuspendState write and cleared when

PortSuspendStatusChange is set at the end of the resume

interval. This bit cannot be set if CurrentConnectStatus is cleared.

This bit is also cleared when PortResetStatusChange is set at the

end of the port reset or when the HC is placed in the

USBRESUME state. If an upstream resume is in progress, it

should propagate to the HC.

0 — port is not suspended

1 — port is suspended

(write) SetPortSuspend: The HCD sets the PortSuspendStatus

bit by writing a logic 1 to this bit. Writing a logic 0 has no effect. If

CurrentConnectStatus is cleared, this write does not set

PortSuspendStatus; instead it sets ConnectStatusChange. This

informs the driver that it attempted to suspend a disconnected

port.

1

PES

(read) PortEnableStatus: This bit indicates whether the port is

enabled or disabled. The Root Hub may clear this bit when an

overcurrent condition, disconnect event, switched-off power, or

operational bus error such as babble is detected. This change also

causes PortEnabledStatusChange to be set. The HCD sets this bit

by writing SetPortEnable and clears it by writing ClearPortEnable.

This bit cannot be set when CurrentConnectStatus is cleared. This

bit is also set, if it is not already, at the completion of a port reset

when ResetStatusChange is set or port suspend when

SuspendStatusChange is set.

0 — port is disabled

1 — port is enabled

(write) SetPortEnable: The HCD sets PortEnableStatus by writing

a logic 1. Writing a logic 0 has no effect. If CurrentConnectStatus is

cleared, this write does not set PortEnableStatus, but instead sets

ConnectStatusChange. This informs the driver that it attempted to

enable a disconnected port.

0

CCS

(read) CurrentConnectStatus: This bit reﬂects the current state

of the downstream port.

0 — no device connected

1 — device connected

(write) ClearPortEnable: The HCD writes a logic 1 to this bit to

clear the PortEnableStatus bit. Writing a logic 0 has no effect.

CurrentConnectStatus is not affected by any write.

Remark: This bit always reads logic 1 when the attached device is

nonremovable (DeviceRemoveable[NDP]).

Code (Hex): [1] = 15, [2] = 16 — read

Code (Hex): [1] = 95, [2] = 96 — write

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13.4 HC DMA and interrupt control registers

13.4.1 HcHardwareConﬁguration Register

Table 44: HcHardwareConﬁguration Register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved

2_Down

streamPort ClkNotStop

Suspend

AnalogOC

Enable

reserved DACKMode

15K

resistorsel

Reset

Access

Bit

0

R/W

6

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

7

5

Symbol

EOTInput

Polarity

DACKInput DREQOut

DataBusWidth

InterruptOut InterruptPi InterruptPin

Polarity

putPolarity

nTrigger

Enable

Reset

0

1

0

Access

R/W

Table 45: HcHardwareConﬁguration Register: bit description

Bit

Symbol

Description

reserved

15 to 13

12

-

2_DownstreamPort15KresistorSel

0 — use external 15 kΩ resistors for downstream ports

1 — use built-in resistors for downstream ports

0 — Clk can be stopped

11

10

SuspendClkNotStop

AnalogOCEnable

1 — clock can not be stopped

0 — use external OC detection. Digital input

1 — use on-chip OC detection. Analog input

reserved

9

8

-

DACKMode

0 — normal operation. DACK1 is used with read and write signals.

Power-up value.

1 — reserved

7

EOTInputPolarity

0 — active LOW. Power-up value

1 — active HIGH

6

DACKInputPolarity

DREQOutputPolarity

DataBusWidth[1:0]

InterruptOutputPolarity

InterruptPinTrigger

InterruptPinEnable

0 — active LOW. Power-up value

1 — active HIGH

5

0 — active LOW

1 — active HIGH. Power-up value

01 — 16 bits

4 to 3

Others — reserved

2

1

0

0 — active LOW. Power-up value

1 — active HIGH

0 — interrupt is level-triggered. Power-up value

1 — Interrupt is edge-triggered.

0 — power-up value

1 — pin Global Interrupt INT1 is enabled

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Code (Hex): 20 — read

Code (Hex): A0 — write

Remark:

1. Bit 0, InterruptPinEnable, is used as pin INT1’s master interrupt enable. This bit

should be used together with the register HcµPInterruptEnable to enable pin

INT1.

2. Bits 4:3 are ﬁxed at the value 01B for ISP1161.

13.4.2 HcDMAConﬁguration Register

Table 46: HcDMAConﬁguration Register: bit allocation

Bit

15

14

13

12

11

3

10

2

9

8

Symbol

Reset

Access

Bit

reserved

00H

R/W

7

6

5

4

1

0

Symbol

reserved

BurstLen[1:0]

DMA

Enable

reserved

DMACount

erSelect

ITL_ATL_

DataSelect WriteSelect

DMARead

Reset

0

Access

R/W

Table 47: HcDMAConﬁguration Register: bit description

Bit

Symbol

Description

reserved

15 to 8

7

-

reserved

6 to 5

BurstLen[1:0] 00B — single-cycle burst DMA

01B — 4-cycle burst DMA

10B — 8-cycle burst DMA

11B — reserved

4

DMAEnable

-

0 — DMA is terminated

1 — DMA is enabled

This bit will be reset to zero when DMA transfer is completed

3

2

reserved

DMACounter 0 — DMA counter not used. External EOT must be used

Select

1 — Enables the DMA counter for DMA transfer.

HcTransferCounter register must be ﬁlled with non-zero values for

DREQ1 to be raised after bit DMA Enable is set

1

0

ITL_ATL_

DataSelect

0 — ITL buffer RAM selected for ITL data

1 — ATL buffer RAM selected for ATL data

0 — read from ISP1161 HC’s FIFO buffer RAM

1 — write to ISP1161 HC’s FIFO buffer RAM

DMARead

WriteSelect

Code (Hex): 21 — read

Code (Hex): A1 — write

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13.4.3 HcTransferCounter Register

This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer,

the number of bytes being read or written to the (Isochronous Transfer List) ITL or

(Acknowledged Transfer List) ATL buffer RAM must be written into this register. For a

DMA transfer, the number of bytes must be written into this register as well. However,

for this counter to be read into the DMA counter, the HCD must set bit 2 of the

HcDMAConﬁguration register. The counter value for ATL must not be greater than

1000H, and for ITL it must not be greater than 800H. When the byte count of the data

transfer reaches this value, the HC will generate an internal EOT signal to set bit 2

AllEOInterrupt, of the HcµPInterrupt register, and also update the HcBufferStatus

register.

Table 48: HcTransferCounter Register: bit allocation

Bit

15

14

13

12

11

0

10

0

9

0

1

0

8

0

Symbol

Reset

Access

Bit

Counter value

0

R/W

7

6

5

4

3

2

Symbol

Reset

Access

Counter value

0

R/W

Table 49: HcTransferCounter Register: bit description

Bit

Symbol

Description

The number of data bytes to be read to or written from RAM

15 to 0

Counter

value

Code (Hex): 22 — read

Code (Hex): A2 — write

13.4.4 HcµPInterrupt Register

All the bits in this register will be active on power-on reset. However, none of the

active bits will cause an interrupt on the interrupt pin (INT1) unless they are set by the

respective bits in the HcµPInterruptEnable register, and together with bit 0 of the

HcHardwareConﬁguration register.

After this register (24H Read) is read, the bits that are active will not be reset, until

logic 1 is written to the bits in this register (A4H - Write) to clear it.

The bits in this register are cleared only when you write to this register indicating the

bits to be cleared. To clear all the enabled bits in this register, the HCD must write

FFH to this register.

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Table 50: HcµPInterrupt Register: bit allocation

Bit

15

14

13

12

4

11

10

9

8

Symbol

Reset

Access

Bit

reserved

00H

R/W

7

6

5

3

2

1

0

Symbol

reserved

ClkReady

HC

OPR_Reg

reserved

AllEOT

ATLInt

SOFITLInt

Suspended

Interrupt

Reset

0

Access

R/W

Table 51: HcµPInterrupt Register: bit description

Bit

Symbol

Description

reserved

15 to 8

-

7

6

-

reserved

ClkReady

0 — no event

1 — clock is ready. (After a wakeup is sent, there is a wait for clock

ready. Maximum is 1 ms, and typical is 160 µs)

5

HCSuspen 0 — no event

ded

1 — the HC has been suspended and no USB activity is sent from

the microprocessor for each ms. When the microprocessor wants

to suspend the HC, the microprocessor must write to the

HcControl register. And when all downstream devices are

suspended, then the HC stops sending SOF; the HC is suspended

by having the HcControl register written into.

4

OPR_Reg read HcControl and HcInterrupt registers to detect type of interrupt

on the HC (if the HC requires the Operational register to be

updated)

3

2

-

reserved

AllEOTInter 0 — no event

rupt

1 — implies that data transfer has been ﬁnished via PIO transfer or

DMA transfer. Occurrence of internal or external EOT will set this

bit.

1

0

ATLInt

0 — no event

1 — implies that the microprocessor must read ATL data from the

HC. This requires that the HcBufferStatus register must ﬁrst be

read. The time for this interrupt depends on the number of clocks

bit set for USB activities in each ms.

SOFITLInt 0 — no event

1 — implies that SOF indicates the 1 ms mark. The ITL buffer that

the HC has handled must be read. To know the ITL buffer status,

the HcBufferStatus Register must ﬁrst be read. This is for

microprocessor to get ISO data to or from the HC. For more

information, see Section 9.5 on page 33 6th paragraph.

Code (Hex): 24 — read

Code (Hex): A4 — write

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13.4.5 HcuPInterruptEnable Register

The bits 6:0 in this register are the same as those in the HcµPInterrupt register. They

are used together with bit 0 of the HcHardwareConﬁguration register to enable or

disable the bits in the HcµPInterrupt register.

On power-on, all bits in this register are masked with 0. This means no interrupt

request output on the interrupt pin INT1 can be generated.

When the bit is set to 1, the interrupt for the bit is not masked but enabled.

Table 52: HcµPInterruptEnable Register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

00H

R/W

7

6

5

4

3

2

1

0

Symbol

reserved

ClkReady

HC

Suspended

Enable

OPR

Interrupt

Enable

reserved

0

EOT

Interrupt

Enable

ATL

Interrupt

Enable

SOF

Interrupt

Enable

Reset

0

Access

R/W

Table 53: HcµPInterruptEnable Register: bit description

Bit

Symbol

Description

15 to 8

-

reserved

7

6

-

reserved

ClkReady

0 — power-up value

1 — enables Clkready interrupt

0 — power-up value

5

HC

Suspended

Enable

1 — enables HC suspended interrupt. When the microprocessor

wants to suspend the HC, the microprocessor must write to the

HcControl register. And when all downstream devices are

suspended, then the HC stops sending SOF; the HC is suspended

by having the HcControl register written into.

4

OPR

0 — power-up value

Interrupt

Enable

1 — enables the 32-bit Operational register’s interrupt (if the HC

requires the Operational register to be updated)

3

2

-

reserved

EOT

0 — power-up value

Interrupt

Enable

1 — enables the EOT interrupt which indicates an end of a

Read/Write transfer

1

0

ATL

Interrupt

Enable

0 — power-up value

1 — enables ATL interrupt. The time for this interrupt depends on

the number of clock bits set for USB activities in each ms.

SOF

0 — power-up value

Interrupt

Enable

1 — enables the interrupt bit due to SOF (for the microprocessor

DMA to get ISO data from the HC by ﬁrst accessing the

HcDMAConﬁguration register)

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Code (Hex): 25 — read

Code (Hex): A5 — write

13.5 HC miscellaneous registers

13.5.1 HcChipID Register

Read this register to get the ID of the ISP1161 silicon chip. The high byte stands for

the product name (here 61H stands for ISP1161). The low byte indicates the revision

number of the product including engineering samples (here 10H means revision 1,

that is ES1 of ISP1161).

Table 54: HcChipID Register: bit allocation

Bit

15

14

13

1

12

11

0

10

0

9

0

1

0

8

1

0

Symbol

Reset

Access

Bit

ChipID[15:8]

0

1

0

4

0

R

ChipID[7:0]

R

7

6

5

3

2

Symbol

Reset

Access

0

Table 55: HcChipID Register: bit description

Bit

Symbol

Description

15 to 0

ChipID

[15:0]

ISP1161’s chip ID

Code (Hex): 27 — read

13.5.2 HcScratch Register

This register is for the HCD to save and restore values when required.

Table 56: HcScratch Register: bit allocation

Bit

15

14

13

12

11

0

10

0

9

0

1

0

8

0

Symbol

Reset

Access

Bit

Scratch[15:8]

0

4

0

R/W

7

6

5

3

2

Symbol

Reset

Access

Scratch[7:0]

R/W

0

Table 57: HcScratch Register: bit description

Bit

Symbol

Description

15 to 0

Scratch

[15:0]

Scratch register value

Code (Hex): 28 — read

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Code (Hex): A8 — write

13.5.3 HcSoftwareReset Register

This is a soft reset command. The microprocessor writes A9H to ISP1161’s

command port, resetting all the HC’s internal registers except for the internal FIFO

buffer RAM.

Table 58: HcSoftwareReset Register: bit allocation

Bit

15

X

7

14

X

6

13

X

5

12

11

X

3

10

X

2

9

X

1

8

X

0

Symbol

Reset

Access

Bit

Reset[15:8]

X

4

1

W

Reset[7:0]

W

Symbol

Reset

Access

1

0

1

Table 59: HcSoftwareReset Register: bit description

Bit

Symbol

Description

15 to 0

Reset[15:0] Soft reset command

Code (Hex): A9 — write

13.6 HC buffer RAM control registers

13.6.1 HcITLBufferLength Register

Write to this register to assign the ITL buffer size in bytes for both ITL0 and ITL1

simultaneously. Thus, the ITL0 and ITL1 always have the same size.

Must follow the formula:

ATL buffer length + 2 × (ITL buffer size) ≤ 1000H (that is, 4 kbytes)

where: ITL buffer size = ITL0 buffer length = ITL1 buffer length

Table 60: HcITLBufferLength Register: bit allocation

Bit

15

14

13

12

11

10

0

9

0

1

0

8

0

Symbol

Reset

Access

Bit

ITLBufferLength[15:8]

0

R/W

7

6

5

4

3

2

Symbol

Reset

Access

ITLBufferLength[7:0]

0

R/W

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Table 61: HcITLBufferLength Register: bit description

Bit

Symbol

Description

15 to 0 ITLBufferLength

[15:0]

Assign ITL buffer length

Code (Hex): 2A — read

Code (Hex): AA — write

13.6.2 HcATLBufferLength Register

Write to this register to assign ATL buffer size.

Table 62: HcATLBufferLength Register: bit allocation

Bit

15

14

13

12

11

10

0

9

0

1

0

8

0

Symbol

Reset

Access

Bit

ATLBufferLength[15:8]

0

R/W

7

6

5

4

3

2

Symbol

Reset

Access

ATLBufferLength[7:0]

0

R/W

Table 63: HcATLBufferLength Register: bit description

Bit

Symbol

Description

15 to 0 ATLBufferLength

[15:0]

Assign ATL buffer length

Code (Hex): 2B — read

Code (Hex): AB — write

Remark: The maximum total RAM size is 1000H (4096 in decimal) bytes. That

means ITL0 (length) + ITL1 (length) + ATL (length) ≤ 1000H bytes. For example: If

ATL buffer length has been set to be 800H, then the maximum ITL buffer length can

only be set as 400H.

13.6.3 HcBufferStatus Register

Table 64: HcBufferStatus Register: bit allocation

Bit

15

14

13

12

11

10

2

9

8

Symbol

Reset

Access

Bit

reserved

00H

R

7

6

5

4

3

1

0

Symbol

reserved

R

ATLBuffer

Done

ITL1Buffer ITL0Buffer

ATLBuffer

Full

ITL1Buffer ITL0Buffer

Done

Full

Reset

0

Access

R

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Table 65: HcBufferStatus Register: bit description

Bit

Symbol

Description

15 to 8

7 to 6

5

-

reserved

ATLBuffer

Done

0 — ATL Buffer not read by HC yet

1 — ATL Buffer read by HC

4

3

2

1

0

ITL1Buffer 0 — ITL1 Buffer not read by HC yet

Done

1 — ITL1 Buffer read by HC

ITL0Buffer 0 — 1TL0 Buffer not read by HC yet

Done

1 — 1TL0 Buffer read by HC

ATLBuffer

Full

0 — ATL Buffer is empty

1 — ATL Buffer is full

ITL1Buffer 0 — 1TL1 Buffer is empty

Full

1 — 1TL1 Buffer is full

ITL0Buffer 0 — ITL0 Buffer is empty

Full

1 — ITL0 Buffer is full

Code (Hex): 2C — read

13.6.4 HcReadBackITL0Length Register

This register’s value stands for the current number of data bytes inside an ITL0 buffer

to be read back by the microprocessor. The HCD must set the HcTransferCounter

equivalent to this value before reading back the ITL0 buffer RAM.

Table 66: HcReadBackITL0Length Register: bit allocation

Bit

15

14

13

12

11

10

0

9

0

1

0

8

0

Symbol

Reset

Access

Bit

RdITL0BufferLength[15:8]

0

R

7

6

5

4

3

2

Symbol

Reset

Access

RdITL0BufferLength[7:0]

0

R

Table 67: HcReadBackITL0Length Register: bit description

Bit Symbol Description

15 to 0 RdITL0BufferLength The number of bytes for ITL0 data to be read back by the

[15:0]

microprocessor

Code (Hex): 2D — read

13.6.5 HcReadBackITL1Length Register

This register’s value stands for the current number of data bytes inside the ITL1 buffer

to be read back by the microprocessor. The HCD must set the HcTransferCounter

equivalent to this value before reading back the ITL1 buffer RAM.

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Table 68: HcReadBackITL1Length Register: bit allocation

Bit

15

14

13

12

11

10

0

9

0

1

0

8

0

Symbol

Reset

Access

Bit

RdITL1BufferLength[15:8]

0

R

7

6

5

4

3

2

Symbol

Reset

Access

RdITL1BufferLength[7:0]

0

R

Table 69: HcReadBackITL1Length Register: bit description

Bit Symbol Description

15 to 0 RdITL1BufferLength The number of bytes for ITL1 data to be read back by the

[15:0]

microprocessor

Code (Hex): 2E — read

13.6.6 HcITLBufferPort Register

This is the ITL buffer RAM read/write port. The bits 15:8 contain the data byte that

comes from the ITL buffer RAM’s even address. The bits 7:0 contain the data byte

that comes from the ITL buffer RAM’s odd address.

Table 70: HcITLBufferPort Register: bit allocation

Bit

15

14

13

12

11

10

0

9

0

1

0

8

0

Symbol

Reset

Access

Bit

DataWord[15:8]

0

R/W

7

6

5

4

3

2

Symbol

Reset

Access

DataWord[7:0]

0

R/W

Table 71: HcITLBufferPort Register: bit description

Bit Symbol Description

Read/Write ITL buffer RAM’s two data bytes.

15 to 0 DataWord[15:0]

Code (Hex): 40 — read

Code (Hex): C0 — write

The HCD must set the byte count into the HcTransferCounter register and check the

HcBufferStatus register before reading from or writing to the buffer. The HCD must

write the command (40H for read, C0H for write) once only, and then read or write all

the data bytes in word. After every read/write, the pointer of ITL buffer RAM will be

automatically increased by two to point to the next data word until it reaches the value

of HcTransferCounter register; otherwise, an internal EOT signal is not generated to

set the bit 2 AllEOTInterrupt, of the HcµPInterrupt register and update the

HcBufferStatus register.

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The HCD must take care of the difference that the internal buffer RAM is organized in

bytes. The HCD must write the byte count into the HcTransferCounter register, but the

HCD reads or writes the buffer RAM by 16 bits (by 1 word).

13.6.7 HcATLBufferPort Register

This is the ATL buffer RAM read/write port. The bits 15:8 contain the data byte that

comes from the Acknowledged Transfer List (ATL) buffer RAM’s even address. The

bits 7:0 contain the data byte that comes from the ATL buffer RAM’s odd address.

Table 72: HcATLBufferPort Register: bit allocation

Bit

15

14

13

12

11

10

0

9

0

1

0

8

0

Symbol

Reset

Access

Bit

DataWord[15:8]

0

R/W

7

6

5

4

3

2

Symbol

Reset

Access

DataWord[7:0]

0

R/W

Table 73: HcATLBufferPort Register: bit description

Bit Symbol Description

Read/Write ATL buffer RAM’s two data bytes.

15 to 0 DataWord[15:0]

Code (Hex): 41 — read

Code (Hex): C1 — write

The HCD must set the byte count into the HcTransferCounter register and check the

HcBufferStatus register before reading from or writing to the buffer. The HCD must

write the command (41H for read, C1H for write) once only, and then read or write all

the data bytes in word. After every read/write, the pointer of ATL buffer RAM will be

automatically increased by two to point to the next data word until it reaches the value

of HcTransferCounter register; otherwise, an internal EOT signal is not generated to

set the bit 2 AllEOTInterrupt, of the HcµPInterrupt register and update the

HcBufferStatus register.

The HCD must take care of the difference: the internal buffer RAM is organized in

bytes, so the HCD must write the byte count into the HcTransferCounter register, but

the HCD reads or writes the buffer RAM by 16 bits (by 1 word).

14. DC commands and registers

The functions and registers of ISP1161 are accessed via commands, which consist

of a command code followed by optional data bytes (read or write action). An

overview of the available commands and registers is given in Table 74.

A complete access consists of two phases:

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1. Command phase: when address bit A0 = 1, the DC interprets the data on the

lower byte of the bus (bits D7 to D0) as a command code. Commands without a

data phase are executed immediately.

2. Data phase (optional): when address bit A0 = 0, the DC transfers the data on

the bus to or from a register or endpoint FIFO. Multi-byte registers are accessed

least signiﬁcant byte/word ﬁrst.

As the ISP1161 DC’s data bus is 16 bits wide:

The upper byte (bits D15 to D8) in command phase or the undeﬁned byte in data

phase is ignored.

•

The access of registers is word-aligned: byte access is not allowed.

•

If the packet length is odd, the upper byte of the last word in an IN endpoint buffer

is not transmitted to the host. When reading from an OUT endpoint buffer, the

upper byte of the last word must be ignored by the ﬁrmware. The packet length is

stored in the ﬁrst 2 bytes of the endpoint buffer.

Table 74: Command and register summary

Name

Destination

Code (Hex)

Transaction^[1]

Initialization commands

Write Control OUT Conﬁguration

Endpoint Conﬁguration Register

endpoint 0 OUT

20

write 1 word

read 1 word

Write Control IN Conﬁguration

Endpoint Conﬁguration Register

endpoint 0 IN

21

Write Endpoint n Conﬁguration

(n = 1 to 14)

Endpoint Conﬁguration Register

endpoint 1 to 14

22 to 2F

30

Read Control OUT Conﬁguration

Endpoint Conﬁguration Register

endpoint 0 OUT

Read Control IN Conﬁguration

Endpoint Conﬁguration Register

endpoint 0 IN

31

Read Endpoint n Conﬁguration

(n = 1 to 14)

Endpoint Conﬁguration Register

endpoint 1 to 14

32 to 3F

Write/Read Device Address

Write/Read Mode Register

Address Register

Mode Register

B6/B7

B8/B9

BA/BB

C2/C3

write/read 1 word

write/read 2 words

Write/Read Hardware Conﬁguration Hardware Conﬁguration Register

Write/Read Interrupt Enable

Register

Interrupt Enable Register

Write/Read DMA Conﬁguration

Write/Read DMA Counter

Reset Device

DMA Conﬁguration Register

DMA Counter Register

resets all registers

F0/F1

F2/F3

F6

write/read 1 word

-

Data ﬂow commands

Write Control OUT Buffer

Write Control IN Buffer

illegal: endpoint is read-only

FIFO endpoint 0 IN

(00)

-

01

N ≤ 64 bytes

Write Endpoint n Buffer

(n = 1 to 14)

FIFO endpoint 1 to 14

(IN endpoints only)

02 to 0F

isochronous: N ≤ 1023 bytes

interrupt/bulk: N ≤ 64 bytes

N ≤ 64 bytes

Read Control OUT Buffer

Read Control IN Buffer

FIFO endpoint 0 OUT

10

illegal: endpoint is write-only

(11)

-

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Table 74: Command and register summary…continued

Name

Destination

Code (Hex)

Transaction^[1]

Read Endpoint n Buffer

(n = 1 to 14)

FIFO endpoint 1 to 14

(OUT endpoints only)

12 to 1F

isochronous:

N ≤ 1023 bytes^[6]

interrupt/bulk: N ≤ 64 bytes

Stall Control OUT Endpoint

Stall Control IN Endpoint

Endpoint 0 OUT

Endpoint 0 IN

40

-

41

Stall Endpoint n

(n = 1 to 14)

Endpoint 1 to 14

42 to 4F

Read Control OUT Status

Endpoint Status Register

endpoint 0 OUT

50

read 1 word

Read Control IN Status

Endpoint Status Register

endpoint 0 IN

51

Read Endpoint n Status

(n = 1 to 14)

Endpoint Status Register n

endpoint 1 to 14

52 to 5F

Validate Control OUT Buffer

Validate Control IN Buffer

illegal: IN endpoints only^[2]

FIFO endpoint 0 IN^[2]

(60)

-

61

none

Validate Endpoint n Buffer

(n = 1 to 14)

FIFO endpoint 1 to 14

(IN endpoints only)^[2]

62 to 6F

Clear Control OUT Buffer

Clear Control IN Buffer

FIFO endpoint 0 OUT

illegal^[3]

70

none

-

(71)

Clear Endpoint n Buffer

(n = 1 to 14)

FIFO endpoint 1 to 14

(OUT endpoints only)^[3]

72 to 7F

none

Unstall Control OUT Endpoint

Unstall Control IN Endpoint

Endpoint 0 OUT

Endpoint 0 IN

80

-

81

Unstall Endpoint n

(n = 1 to 14)

Endpoint 1 to 14

82 to 8F

Check Control OUT Status^[4]

Endpoint Status Image Register

endpoint 0 OUT

D0

read 1 word

none

Check Control IN Status^[4]

Endpoint Status Image Register

endpoint 0 IN

D1

Check Endpoint n Status

(n = 1 to 14)^[4]

Endpoint Status Image Register n

endpoint 1 to 14

D2 to DF

F4

Acknowledge Setup

Endpoint 0 IN and OUT

General commands

[5]

Read Control OUT Error Code

Error Code Register

endpoint 0 OUT

A0

read 1 word

[5]

Read Control IN Error Code

Error Code Register

endpoint 0 IN

A1

read 1 word

[5]

Read Endpoint n Error Code

(n = 1 to 14)

Error Code Register

endpoint 1 to 14

A2 to AF

read 1 word

Unlock Device

all registers with write access

Scratch Register

B0

write 1 word

Write/Read Scratch Register

Read frame Number

B2/B3

B4

write/read 1 word

read 1 word

Frame Number Register

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Table 74: Command and register summary…continued

Name

Destination

Code (Hex)

Transaction^[1]

read 1 word

Read Chip ID

Read Interrupt Register

Chip ID Register

Interrupt Register

B5

C0

read 2 words

[1] With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) DIV 2.

[2] Validating an OUT endpoint buffer causes unpredictable behavior of ISP1161’s DC.

[3] Clearing an IN endpoint buffer causes unpredictable behavior of ISP1161’s DC.

[4] Reads a copy of the Status Register: executing this command does not clear any status bits or interrupt bits.

[5] When accessing an 8-bit register in 16-bit mode, the upper byte is invalid.

[6] During isochronous transfer in 16-bit mode, because N ≤ 1023, the ﬁrmware must take care of the upper byte.

14.1 Initialization commands

Initialization commands are used during the enumeration process of the USB

network. These commands are used to conﬁgure and enable the embedded

endpoints. They also serve to set the USB assigned address of ISP1161’s DC and to

perform a device reset.

14.1.1 Write/Read Endpoint Conﬁguration

This command is used to access the Endpoint Conﬁguration Register (ECR) of the

target endpoint. It deﬁnes the endpoint type (isochronous or bulk/interrupt), direction

(OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The

register bit allocation is shown in Table 75. A bus reset will disable all endpoints.

The allocation of FIFO memory only takes place after all 16 endpoints have been

conﬁgured in sequence (from endpoint 0 OUT to endpoint 14). Although the control

endpoints have ﬁxed conﬁgurations, they must be included in the initialization

sequence and be conﬁgured with their default values (see Table 7). Automatic FIFO

allocation starts when endpoint 14 has been conﬁgured.

Remark: If any change is made to an endpoint conﬁguration which affects the

allocated memory (size, enable/disable), the FIFO memory contents of all endpoints

becomes invalid. Therefore, all valid data must be removed from enabled endpoints

before changing the conﬁguration.

Code (Hex): 20 to 2F — write (control OUT, control IN, endpoint 1 to 14)

Code (Hex): 30 to 3F — read (control OUT, control IN, endpoint 1 to 14)

Transaction — write/read 1 word

Table 75: Endpoint Conﬁguration Register: bit allocation

Bit

7

FIFOEN

0

6

EPDIR

0

5

DBLBUF

0

4

FFOISO

0

3

2

1

0

Symbol

Reset

Access

FFOSZ[3:0]

0

R/W

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Table 76: Endpoint Conﬁguration Register: bit description

Bit

Symbol

Description

7

FIFOEN

A logic 1 indicates an enabled FIFO with allocated memory.

A logic 0 indicates a disabled FIFO (no bytes allocated).

6

EPDIR

This bit deﬁnes the endpoint direction (0 = OUT, 1 = IN); it also

determines the DMA transfer direction (0 = read, 1 = write)

5

4

DBLBUF

FFOISO

A logic 1 indicates that this endpoint has double buffering.

A logic 1 indicates an isochronous endpoint. A logic 0 indicates

a bulk or interrupt endpoint.

3 to 0

FFOSZ[3:0]

Selects the FIFO size according to Table 8

14.1.2 Write/Read Device Address

This command is used to set the USB assigned address in the Address Register and

enable the USB device. The Address Register bit allocation is shown in Table 77.

A USB bus reset sets the device address to 00H (internally) and enables the device.

The value of the Address Register (accessible by the microcontroller) is not altered by

the bus reset. In response to the standard USB request Set Address the ﬁrmware

must issue a Write Device Address command, followed by sending an empty packet

to the host. The new device address is activated when the host acknowledges the

empty packet.

Code (Hex): B6/B7 — write/read Address Register

Transaction — write/read 1 word

Table 77: Address Register: bit allocation

Bit

7

DEVEN

0

6

5

4

3

2

1

0

Symbol

Reset

Access

DEVADR[6:0]

0

R/W

Table 78: Address Register: bit description

Bit

7

Symbol

Description

A logic 1 enables the device.

DEVEN

6 to 0

DEVADR[6:0] This ﬁeld speciﬁes the USB device address.

14.1.3 Write/Read Mode Register

This command is used to access the ISP1161’s DC Mode Register, which consists of

1 byte (bit allocation: see Table 78). In 16-bit bus mode the upper byte is ignored.

The Mode Register controls the DMA bus width, resume and suspend modes,

interrupt activity and SoftConnect operation. It can be used to enable debug mode,

where all errors and Not Acknowledge (NAK) conditions will generate an interrupt.

Code (Hex): B8/B9 — write/read Mode Register

Transaction — write/read 1 word

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Table 79: Mode Register: bit allocation

Bit

7

DMAWD

0^[1]

6

reserved

0

5

GOSUSP

0

4

reserved

0

3

INTENA

0^[1]

2

DBGMOD

0^[1]

1

reserved

0^[1]

0

SOFTCT

0^[1]

Symbol

Reset

Access

R/W

[1] Unchanged by a bus reset.

Table 80: Mode Register: bit description

Bit

Symbol

Description

7

DMAWD

A logic 1 selects 16-bit DMA bus width (bus conﬁguration modes

0 and 2). A logic 0 selects 8-bit DMA bus width. Bus reset value:

unchanged.

6

5

-

reserved

GOSUSP

Writing a logic 1 followed by a logic 0 will activate ‘suspend’

mode.

4

3

2

-

reserved

INTENA

DBGMOD

A logic 1 enables all interrupts. Bus reset value: unchanged.

A logic 1 enables debug mode. where all NAKs and errors will

generate an interrupt. A logic 0 selects normal operation, where

interrupts are generated on every ACK (bulk endpoints) or after

every data transfer (isochronous endpoints). Bus reset value:

unchanged.

1

0

-

reserved

SOFTCT

A logic 1 enables SoftConnect (see Section 7.5). This bit is

ignored if EXTPUL = 1 in the Hardware Conﬁguration Register

(see Table 81). Bus reset value: unchanged.

14.1.4 Write/Read Hardware Conﬁguration

This command is used to access the Hardware Conﬁguration Register, which

consists of 2 bytes. The ﬁrst (lower) byte contains the device conﬁguration and

control values, the second (upper) byte holds the clock control bits and the clock

division factor. The bit allocation is given in Table 81. A bus reset will not change any

of the programmed bit values.

The Hardware Conﬁguration Register controls the connection to the USB bus, clock

activity and power supply during ‘suspend’ state, output clock frequency, DMA

operating mode and pin conﬁgurations (polarity, signalling mode).

Code (Hex): BA/BB — write/read Hardware Conﬁguration Register

Transaction — write/read 1 word

Table 81: Hardware Conﬁguration Register: bit allocation

Bit

15

reserved

0

14

EXTPUL

0

13

NOLAZY

1

12

CLKRUN

0

11

10

9

8

Symbol

Reset

Access

CKDIV[3:0]

0

1

R/W

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Bit

7

DAKOLY

0

6

DRQPOL

1

5

DAKPOL

0

4

EOTPOL

0

3

WKUPCS

0

2

PWROFF

0

1

INTLVL

0

INTPOL

0

Symbol

Reset

Access

R/W

Table 82: Hardware Conﬁguration Register: bit description

Bit

15

14

Symbol

-

Description

reserved

EXTPUL

A logic 1 indicates that an external 1.5 kΩ pull-up resistor is

used on pin D+ and that SoftConnect is not used. Bus reset

value: unchanged.

13

12

NOLAZY

CLKRUN

A logic 1 disables output on pin CLKOUT of the LazyClock

frequency (115 kHz ±10 %) during ‘suspend’ state. A logic 0

causes pin CLKOUT to switch to LazyClock output after

approximately 2 ms delay, following the setting of bit GOSUSP

in the Mode Register. Bus reset value: unchanged.

A logic 1 indicates that the internal clocks are always running,

even during ‘suspend’ state. A logic 0 switches off the internal

oscillator and PLL, when they are not needed. During ‘suspend’

state this bit must be made logic 0 to meet the suspend current

requirements. The clock is stopped after a delay of

approximately 2 ms, following the setting of bit GOSUSP in the

Mode Register. Bus reset value: unchanged.

11 to 8

CKDIV[3:0]

This ﬁeld speciﬁes the clock division factor N, which controls the

clock frequency on output CLKOUT. The output frequency in

MHz is given by 48 / (N + 1). The clock frequency range is

3 to 48 MHz (N = 0 to 15). with a reset value of 12 MHz (N = 3).

The hardware design guarantees no glitches during frequency

change. Bus reset value: unchanged.

7

6

5

4

3

2

DAKOLY

DRQPOL

DAKPOL

EOTPOL

WKUPCS

PWROFF

A logic 1 selects DACK-only DMA mode. A logic 0 selects 8237

compatible DMA mode. Bus reset value: unchanged.

Selects DREQ2 pin signal polarity (0 = active LOW, 1 = active

HIGH). Bus reset value: unchanged.

Selects DACK2 pin signal polarity (0 = active LOW, 1 = active

HIGH). Bus reset value: unchanged.

Selects EOT pin signal polarity (0 = active LOW, 1 = active

HIGH). Bus reset value: unchanged.

A logic 1 enables remote wake-up via a LOW level on input pin

CS. Bus reset value: unchanged.

A logic 1 enables powering-off during ‘suspend’ state. Output

D_SUSPEND pin is conﬁgured as a power switch control signal

for external devices (HIGH during ‘suspend’). This value should

always be initialized to logic 1. Bus reset value: unchanged.

1

0

INTLVL

Selects the interrupt signalling mode on output pin INT2

(0 = level, 1 = pulsed). In pulsed mode an interrupt produces an

166 ns pulse. See Section 8.6.3 for details. Bus reset value:

unchanged.

INTPOL

Selects INT2 pin signal polarity (0 = active LOW, 1 = active

HIGH). Bus reset value: unchanged.

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14.1.5 Write/Read Interrupt Enable Register

This command is used to individually enable/disable interrupts from all endpoints, as

well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend,

resume, reset). A bus reset will not change any of the programmed bit values.

The command accesses the Interrupt Enable Register, which consists of 4 bytes. The

bit allocation is given in Table 83.

Code (Hex): C2/C3 — write/read Interrupt Enable Register

Transaction — write/read 2 words

Table 83: Interrupt Enable Register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R/W

23

0

R/W

22

0

R/W

21

0

R/W

19

0

R/W

18

0

R/W

17

0

R/W

16

R/W

20

Symbol

Reset

Access

Bit

IEP14

0

IEP13

0

IEP12

0

IEP11

0

IEP10

0

IEP9

0

IEP8

0

IEP7

0

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

R/W

9

R/W

8

Symbol

Reset

Access

Bit

IEP6

0

IEP5

0

IEP4

0

IEP3

0

IEP2

0

IEP1

0

IEP0IN

0

IEP0OUT

0

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

Symbol

Reset

Access

reserved

0

reserved

0

IEPSOF

0

IESOF

0

IEEOT

0

IESUSP

0

IERESM

0

IERST

0

R/W

Table 84: Interrupt Enable Register: bit description

Bit

Symbol

Description

reserved; must write logic 0

31 to 24

-

23 to 10

IEP14 to IEP1 A logic 1 enables interrupts from the indicated endpoint.

9

IEP0IN

IEP0OUT

-

A logic 1 enables interrupts from the control IN endpoint.

A logic 1 enables interrupts from the control OUT endpoint.

reserved

8

7, 6

5

IEPSOF

A logic 1 enables 1 ms interrupts upon detection of Pseudo

SOF.

4

3

2

1

0

IESOF

IEEOT

A logic 1 enables interrupt upon SOF detection.

A logic 1 enables interrupt upon EOT detection.

IESUSP

IERESM

IERST

A logic 1 enables interrupt upon detection of ‘suspend’ state.

A logic 1 enables interrupt upon detection of a ‘resume’ state.

A logic 1 enables interrupt upon detection of a bus reset.

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14.1.6 Write/Read DMA Conﬁguration

This command deﬁnes the DMA conﬁguration of ISP1161’s DC and enables/disables

DMA transfers. The command accesses the DMA Conﬁguration Register, which

consists of 2 bytes. The bit allocation is given in Table 85. A bus reset will clear bit

DMAEN (DMA disabled), all other bits remain unchanged.

Code (Hex): F0/F1 — write/read DMA Conﬁguration

Transaction — write/read 1 word

Table 85: DMA Conﬁguration Register: bit allocation

Bit

15

CNTREN

0^[1]

14

SHORTP

0^[1]

13

reserved

0^[1]

12

reserved

0^[1]

11

reserved

0^[1]

10

reserved

0^[1]

9

reserved

0^[1]

8

reserved

0^[1]

Symbol

Reset

Access

Bit

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

7

6

Symbol

Reset

Access

EPDIX[3:0]

DMAEN

0

reserved

0

BURSTL[1:0]

0^[1]

R/W

[1] Unchanged by a bus reset.

Table 86: DMA Conﬁguration Register: bit description

Bit

Symbol

Description

15

CNTREN

A logic 1 enables the generation of an EOT condition, when the

DMA Counter Register reaches zero. Bus reset value:

unchanged.

14

SHORTP

A logic 1 enables short/empty packet mode. When receiving

(OUT endpoint) a short/empty packet an EOT condition is

generated. When transmitting (IN endpoint) this bit should be

cleared. Bus reset value: unchanged.

13 to 8

7 to 4

3

-

reserved

EPDIX[3:0]

DMAEN

Indicates the destination endpoint for DMA, see Table 10.

Writing a logic 1 enables DMA transfer, a logic 0 forces the end

of an ongoing DMA transfer and generates an EOT interrupt.

Reading this bit indicates whether DMA is enabled (0 = DMA

stopped, 1 = DMA enabled). This bit is cleared by a bus reset.

2

-

reserved

1 to 0

BURSTL[1:0] Selects the DMA burst length:

00 — single-cycle mode (1 byte)

01 — burst mode (4 bytes)

10 — burst mode (8 bytes)

11 — burst mode (16 bytes).

Bus reset value: unchanged.

For selecting an endpoint for device DMA transfer, see Section 11.2.

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14.1.7 Write/Read DMA Counter

This command accesses the DMA Counter Register. The bit allocation is given in

Table 87. Writing to the register sets the number of bytes for a DMA transfer. Reading

the register returns the number of remaining bytes in the current transfer. A bus reset

will not change the programmed bit values.

The internal DMA counter is automatically reloaded from the DMA Counter Register

when DMA is re-enabled (DMAEN = 1). See Section 14.1.6 for more details.

Code (Hex): F2/F3 — write/read DMA Counter Register

Transaction — write/read 1 word

Table 87: DMA Counter Register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

DMACR[15:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

DMACR[7:0]

0

R/W

Table 88: DMA Counter Register: bit description

Bit

Symbol

Description

15 to 0

DMACR[15:0] DMA Counter Register

14.1.8 Reset Device

This command resets the ISP1161 DC in the same way as an external hardware

reset via input RESET. All registers are initialized to their ‘reset’ values.

Code (Hex): F6 — reset the device

Transaction — none

14.2 Data ﬂow commands

Data ﬂow commands are used to manage the data transmission between the USB

endpoints and the system microprocessor. Much of the data ﬂow is initiated via an

interrupt to the microprocessor. The data ﬂow commands are used to access the

endpoints and determine whether the endpoint FIFOs contain valid data.

Remark: The IN buffer of an endpoint contains input data for the host, the OUT buffer

receives output data from the host.

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14.2.1 Write/Read Endpoint Buffer

This command is used to access endpoint FIFO buffers for reading or writing. First,

the buffer pointer is reset to the beginning of the buffer. Following the command, a

maximum of (M + 1) words can be written or read, with M given by (N + 1) DIV 2, N

representing the size of the endpoint buffer. After each read/write action the buffer

pointer is automatically incremented by 2.

In DMA access the ﬁrst word (the packet length) is skipped: transfers start at the

second word of the endpoint buffer. When reading, the ISP1161 DC can detect the

last word via the End of Packet (EOP) condition. When writing to a bulk/interrupt

endpoint, the endpoint buffer must be completely ﬁlled before sending the data to the

host. Exception: when a DMA transfer is stopped by an external EOT condition, the

current buffer content (full or not) is sent to the host.

Remark: Reading data after a Write Endpoint Buffer command or writing data after a

Read Endpoint Buffer command will cause unpredictable behavior of the ISP1161

DC.

Code (Hex): 01 to 0F — write (control IN, endpoint 1 to 14)

Code (Hex): 10, 12 to 1F — read (control OUT, endpoint 1 to 14)

Transaction — write/read maximum (M + 1) words (isochronous endpoint: N ≤ 1023,

bulk/interrupt endpoint: N ≤ 32)

The data in the endpoint FIFO must be organized as shown in Table 89. An example

of endpoint FIFO access is given Table 90.

Table 89: Endpoint FIFO organization

Word #

Description

0 (lower byte)

0 (upper byte)

1 (lower byte)

1 (upper byte)

…

packet length (lower byte)

packet length (upper byte)

data byte 1

data byte 2

…

M = (N + 1) DIV 2

data byte N

Table 90: Example of endpoint FIFO access

A0

Phase

Bus lines

D[7:0]

Word #

Description

1

command

-

command code (00H to 1FH)

D[15:8]

D[15:0]

…

-

ignored

0

data

…

0

1

2

…

packet length

0

data word 1 (data byte 2, data byte 1)

data word 2 (data byte 4, data byte 3)

…

0

…

Remark: There is no protection against writing or reading past a buffer’s boundary or

against writing into an OUT buffer or reading from an IN buffer. Any of these actions

could cause an incorrect operation. Data residing in an OUT buffer are only

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meaningful after a successful transaction. Exception: during DMA access of a

double-buffered endpoint, the buffer pointer automatically points to the secondary

buffer after reaching the end of the primary buffer.

14.2.2 Read Endpoint Status

This command is used to read the status of an endpoint FIFO. The command

accesses the Endpoint Status Register, the bit allocation of which is shown in

Table 91. Reading the Endpoint Status Register will clear the interrupt bit set for the

corresponding endpoint in the Interrupt Register (see Table 106).

All bits of the Endpoint Status Register are read-only. Bit EPSTAL is controlled by the

Stall/Unstall commands and by the reception of a SETUP token (see Section 14.2.3).

Code (Hex): 50 to 5F — read (control OUT, control IN, endpoint 1 to 14)

Transaction — read 1 word

Table 91: Endpoint Status Register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

EPSTAL

EPFULL1

EPFULL0

DATA_PID

OVER

SETUPT

CPUBUF

reserved

WRITE

Reset

0

Access

R

Table 92: Endpoint Status Register: bit description

Bit

Symbol

Description

7

EPSTAL

This bit indicates whether the endpoint is stalled or not

(1 = stalled, 0 = not stalled).

Set to logic 1 by a Stall Endpoint command, cleared to logic 0 by

an Unstall Endpoint command. The endpoint is automatically

unstalled upon reception of a SETUP token.

6

5

4

EPFULL1

EPFULL0

DATA_PID

A logic 1 indicates that the secondary endpoint buffer is full.

A logic 1 indicates that the primary endpoint buffer is full.

This bit indicates the data PID of the present packet (0 = DATA

PID, 1 = DATA1 PID).

3

OVERWRITE This bit is set by hardware, a logic 1 indicating that a new Setup

packet has overwritten the previous setup information, before it

was acknowledged or before the endpoint was stalled. This bit is

cleared by reading, if writing the setup data has ﬁnished.

Firmware must check this bit before sending an Acknowledge

Setup command or stalling the endpoint. Upon reading a logic 1

the ﬁrmware must stop ongoing setup actions and wait for a new

Setup packet.

2

1

SETUPT

CPUBUF

A logic 1 indicates that the buffer contains a Setup packet.

This bit indicates which buffer is currently selected for CPU

access (0 = primary buffer, 1 = secondary buffer).

0

-

reserved

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14.2.3 Stall Endpoint/Unstall Endpoint

These commands are used to stall or unstall an endpoint. The commands modify the

content of the Endpoint Status Register (see Table 91).

A stalled control endpoint is automatically unstalled when it receives a SETUP token,

regardless of the packet content. If the endpoint should stay in its stalled state, the

microprocessor can re-stall it with the Stall Endpoint command.

When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by

receiving a SETUP token), it is also re-initialized. This ﬂushes the buffer: in and if it is

an OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.

Code (Hex): 40 to 4F — stall (control OUT, control IN, endpoint 1 to 14)

Code (Hex): 80 to 8F — unstall (control OUT, control IN, endpoint 1 to 14)

Transaction — none

14.2.4 Validate Endpoint Buffer

This command signals the presence of valid data for transmission to the USB host, by

setting the Buffer Full ﬂag of the selected IN endpoint. This indicates that the data in

the buffer is valid and can be sent to the host, when the next IN token is received. For

a double-buffered endpoint this command switches the current FIFO for CPU access.

Remark: For special aspects of the control IN endpoint see Section 11.3.6.

Code (Hex): 61 to 6F — validate endpoint buffer (control IN, endpoint 1 to 14)

Transaction — none

14.2.5 Clear Endpoint Buffer

This command unlocks and clears the buffer of the selected OUT endpoint, allowing

the reception of new packets. Reception of a complete packet causes the Buffer Full

ﬂag of an OUT endpoint to be set. Any subsequent packets are refused by returning a

NAK condition, until the buffer is unlocked using this command. For a double-buffered

endpoint this command switches the current FIFO for CPU access.

Remark: For special aspects of the control OUT endpoint see Section 11.3.6.

Code (Hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoint 1 to 14)

Transaction — none

14.2.6 Check Endpoint Status

This command is used to check the status of the selected endpoint FIFO without

clearing any status or interrupt bits. The command accesses the Endpoint Status

Image Register, which contains a copy of the Endpoint Status Register. The bit

allocation of the Endpoint Status Image Register is shown in Table 93.

Code (Hex): D0 to DF — check status (control OUT, control IN, endpoint 1 to 14)

Transaction — write/read 1 word

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Table 93: Endpoint Status Image Register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

EPSTAL

EPFULL1

EPFULL0

DATA_PID

OVER

SETUPT

CPUBUF

reserved

WRITE

Reset

0

Access

R

Table 94: Endpoint Status Image Register: bit description

Bit

Symbol

Description

7

EPSTAL

This bit indicates whether the endpoint is stalled or not

(1 = stalled, 0 = not stalled).

6

5

4

EPFULL1

EPFULL0

DATA_PID

A logic 1 indicates that the secondary endpoint buffer is full.

A logic 1 indicates that the primary endpoint buffer is full.

This bit indicates the data PID of the present packet (0 = DATA

PID, 1 = DATA1 PID).

3

OVERWRITE This bit is set by hardware, a logic 1 indicating that a new Setup

packet has overwritten the previous setup information, before it

was acknowledged or before the endpoint was stalled. This bit is

cleared by reading, if writing the setup data has ﬁnished.

Firmware must check this bit before sending an Acknowledge

Setup command or stalling the endpoint. Upon reading a logic 1

the ﬁrmware must stop ongoing setup actions and wait for a new

Setup packet.

2

1

SETUPT

CPUBUF

A logic 1 indicates that the buffer contains a Setup packet.

This bit indicates which buffer is currently selected for CPU

access (0 = primary buffer, 1 = secondary buffer).

0

-

reserved

14.2.7 Acknowledge Setup

This command acknowledges to the host that a SETUP packet was received. The

arrival of a SETUP packet disables the Validate Buffer and Clear Buffer commands

for the control IN and OUT endpoints. The microprocessor needs to re-enable these

commands by sending an Acknowledge Setup command, see Section 11.3.6.

Remark: The Acknowledge Setup command must be sent to both control endpoints

(IN and OUT).

Code (Hex): F4 — acknowledge setup

Transaction — none

14.3 General commands

14.3.1 Read Endpoint Error Code

This command returns the status of the last transaction of the selected endpoint, as

stored in the Error Code Register. Each new transaction overwrites the previous

status information. The bit allocation of the Error Code Register is shown in Table 95.

Code (Hex): A0 to AF — read error code (control OUT, control IN, endpoint 1 to 14)

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Transaction — read 1 word

Table 95: Error Code Register: bit allocation

Bit

7

6

5

4

3

2

1

0

RTOK

0

Symbol

Reset

Access

UNREAD

DATA01

reserved

ERROR[3:0]

0

R

Table 96: Error Code Register: bit description

Bit

Symbol

Description

7

UNREAD

A logic 1 indicates that a new event occurred before the

previous status was read.

6

DATA01

This bit indicates the PID type of the last successfully received

or transmitted packet (0 = DATA0 PID, 1 = DATA1 PID).

5

-

reserved

4 to 1

0

ERROR[3:0]

RTOK

Error code. For error description, see Table 97.

A logic 1 indicates that data was received or transmitted

successfully.

Table 97: Transaction error codes

Error code

(Binary)

Description

0000

0001

0010

0011

no error

PID encoding error; bits 7 to 4 are not the inverse of bits 3 to 0

PID unknown; encoding is valid, but PID does not exist

unexpected packet; packet is not of the expected type (token, data, or

acknowledge), or is a SETUP token to a non-control endpoint

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

token CRC error

data CRC error

time-out error

babble error

unexpected end-of-packet

sent or received NAK (Not AcKnowledge)

sent Stall; a token was received, but the endpoint was stalled

overﬂow; the received packet was larger than the available buffer space

sent empty packet (ISO only)

bit stufﬁng error

sync error

wrong (unexpected) toggle bit in DATA PID; data was ignored

14.3.2 Unlock Device

This command unlocks ISP1161’s DC from write-protection mode after a ‘resume’. In

‘suspend’ state all registers and FIFOs are write-protected to prevent data corruption

by external devices during a ‘resume’. Register access for reading is not blocked.

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After waking up from ‘suspend’ state, the ﬁrmware must unlock the registers and

FIFOs via this command, by writing the unlock code (AA37H) into the Lock Register.

The bit allocation of the Lock Register is given in Table 98.

Code (Hex): B0 — unlock the device

Transaction — write 1 word (unlock code)

Table 98: Lock Register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

UNLOCKH[7:0] = AAH

1

W

7

0

W

6

1

W

5

0

W

4

1

W

3

0

W

2

1

W

1

0

W

0

Symbol

Reset

Access

UNLOCKL[7:0] = 37H

0

1

0

1

W

Table 99: Lock Register: bit description

Bit

Symbol

Description

15 to 0

UNLOCK[15:0] Sending data AA37H unlocks the internal registers and FIFOs

for writing, following a ‘resume’.

14.3.3 Write/Read Scratch Register

This command accesses the 16-bit Scratch Register, which can be used by the

ﬁrmware to save and restore information, e.g., the device status before powering

down in ‘suspend’ state. The register bit allocation is given in Table 100.

Code (Hex): B2/B3 — write/read Scratch Register

Transaction — write/read 1 word

Table 100:Scratch Information Register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

SFIRH[6:0]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

SFIRL[7:0]

0

R/W

Table 101:Scratch Information Register: bit description

Bit

Symbol

-

Description

15

reserved; must be logic 0

Scratch Information Register

14 to 0

SFIR[14:0]

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14.3.4 Read Frame Number

This command returns the frame number of the last successfully received SOF. It is

followed by reading one word from the Frame Number Register, containing the frame

number. The Frame Number Register is shown in Table 102.

Remark: After a bus reset, the value of the frame Number Register is undeﬁned.

Code (Hex): B4 — read frame number

Transaction — read 1 word

Table 102:Frame Number Register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset^[1]

Access

Bit

reserved

SOFRH[2:0]

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset^[1]

Access

SOFRL[7:0]

0

R

[1] Reset value undeﬁned after a bus reset.

Table 103:Example of Frame Number Register access

A0

Phase

Bus lines

D[7:0]

Word #

Description

1

command

-

command code (B4H)

ignored

D[15:8]

D[15:0]

-

0

data

0

frame number

14.3.5 Read Chip ID

This command reads the chip identiﬁcation code and hardware version number. The

ﬁrmware must check this information to determine the supported functions and

features. This command accesses the Chip ID Register, which is shown in Table 104.

Code (Hex): B5 — read chip ID

Transaction — read 1 word

Table 104:Chip ID Register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

CHIPIDH[7:0]

0

R

7

1

R

6

1

R

5

0

R

4

0

R

3

0

R

2

0

R

1

R

0

Symbol

Reset

Access

CHIPIDL[7:0]

X0H

R

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Table 105:Chip ID Register: bit description

Bit

Symbol

Description

15 to 8

7 to 0

CHIPIDH[7:0] chip ID code (61H)

CHIPIDL[7:0] silicon version (XXH, with XX representing the BCD encoded

version number)

14.3.6 Read Interrupt Register

This command indicates the sources of interrupts as stored in the 4-byte Interrupt

Register. Each individual endpoint has its own interrupt bit. The bit allocation of the

Interrupt Register is shown in Table 106. Bit BUSTATUS is used to verify the current

bus status in the interrupt service routine. Interrupts are enabled via the Interrupt

Enable Register, see Section 14.1.5.

While reading the interrupt register, please read both 2 bytes completely.

Code (Hex): C0 — read interrupt register

Transaction — read 2 words

Table 106:Interrupt Register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R

0

R

0

R

0

R

23

22

21

EP12

0

20

EP11

0

19

EP10

0

18

17

16

Symbol

Reset

Access

Bit

EP14

EP13

EP9

EP8

EP7

0

R

15

14

13

EP4

0

12

EP3

0

11

EP2

0

10

9

8

Symbol

Reset

Access

Bit

EP6

EP5

EP1

EP0IN

EP0OUT

0

R

7

6

5

4

3

2

1

0

Symbol

Reset

Access

BUSTATUS

reserved

PSOF

0

SOF

0

EOT

0

SUSPND

RESUME

RESET

0

R

Table 107: Interrupt Register: bit description

Bit

Symbol

Description

31 to 24

-

reserved

23 to 10

EP14 to EP1 A logic 1 indicates the interrupt source(s): endpoint 14 to 1

9

8

7

6

EP0IN

EP0OUT

BUSTATUS

-

A logic 1 indicates the interrupt source: control IN endpoint

A logic 1 indicates the interrupt source: control OUT endpoint

Monitors the current USB bus status (0 = awake, 1 = suspend).

reserved

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Table 107: Interrupt Register: bit description…continued

Bit

Symbol

Description

5

PSOF

A logic 1 indicates that an interrupt is issued every 1 ms

because of the Pseudo SOF; after 3 missed SOFs ‘suspend’

state is entered.

4

3

SOF

EOT

A logic 1 indicates that a SOF condition was detected.

A logic 1 indicates that an internal EOT condition was generated

by the DMA Counter reaching zero.

2

SUSPND

A logic 1 indicates that an ‘awake’ to ‘suspend’ change of state

was detected on the USB bus.

1

0

RESUME

RESET

A logic 1 indicates that a ‘resume’ state was detected.

A logic 1 indicates that a bus reset condition was detected.

15. Reset

Pin RESET is the hardware reset input of ISP1161. It is active LOW. To reset all

internal logic, the minimum timing requirement is 200 ns.

V

CC

ISP1161

reset from µP

or

RESET

not connected

MGT962

Fig 40. RESET pin usage.

16. Power supply

ISP1161 can operate at either +5 V or +3.3 V.

When using +5 V as ISP1161’s power supply input: Only V_CC(pin 56) can be

connected to the +5 V power supply. An application with a +5 V power supply input is

shown in Figure 41. ISP1161 has an internal DC/DC regulator to provide +3.3 V for

its internal core. This internal +3.3 V can also be obtained from V_reg(3.3)(pin 58) to

supply the 1.5 kΩ pull-up resistor of the DC side upstream port signal D_DP. The

signal D_DP is connected to the standard USB upstream port connector’s pin D+.

When using +3.3 V as the power supply input, the internal DC/DC regulator will be

bypassed. All four power supply pins (V_CC, V_reg(3.3), V_hold1and V_hold2) can be used as

power supply input.

The best case is to connect all four power supply pins to the +3.3 V power supply, as

shown in Figure 42. If, however you do not want to connect all four, you must at least,

connect the V_CCand the V_reg(3.3)to the 3.3 V power supply.

For both +3.3 V and 5 V operation, all four power supply pins should be connected to

a decoupling capacitor.

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+3.3 V

ISP1161

+5 V

ISP1161

1.5 kΩ

V

CC

to USB

upstream

port

to USB

upstream

port

connector

V

reg(3.3)

D_DP

reg(3.3)

connector

V

hold1

V

hold2

GND

MGT963

MGT964

Fig 41. Using a +5 V supply.

Fig 42. Using a +3.3 V supply.

17. External clock input

The ISP1161 has a crystal oscillator designed for a 6 MHz parallel-resonant crystal

(fundamental). A typical circuit is shown in Figure 43. Alternatively, an external clock

signal of 6 MHz can be applied to in put XTAL1, while leaving output XTAL2 open.

See Figure 44.

V

CC

6 MHz

ISP1161

CLKOUT

Out

CLKOUT

18 pF

6 MHz

18 pF

OSC

XTAL2

XTAL1

n.c.

XTAL2

XTAL1

MGT966

MGT965

Fig 43. Oscillator circuit with external crystal.

Fig 44. Oscillator circuit using external oscillator.

The 6 MHz oscillator frequency is multiplied to 48 MHz by an internal PLL. This

frequency is used to generate a programmable clock output signal at pin CLKOUT,

ranging from 3 to 48 MHz.

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18. Limiting values

Table 108:Absolute maximum ratings

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC(5V)

V_CC(3.3V)

V_I

Parameter

Conditions

Min

−0.5

-

Max

+6.0

+4.6

+6.0

100

Unit

V

supply voltage to V_CCpin

supply voltage to V_reg(3.3)pin

input voltage

V

I_latchup

V_esd

latchup current

V_I< 0 or V_I> V_CC

mA

V

[1][2]

electrostatic discharge voltage

storage temperature

I_LI< 10 µA

-

±2000

+150

T_stg

−60

°C

[1] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ resistor (Human Body Model).

[2] Values are given for device only; in-circuit V_esd(max)= ±8000 V.

Table 109:Recommended operating conditions

Symbol Parameter

Conditions

Min

Typ

Max

5.5

Unit

V

V_CC

supply voltage

with internal regulator

internal regulator bypass

4.0

3.0

0

5.0

3.3

3.6

5.5^[1]

V

V_I

input voltage

V_CC

V

V_{I(A I/O)}

V_O(od)

T_amb

input voltage on analog I/O pins (D+ / D−)

open-drain output pull-up voltage

operating ambient temperature

0

-

3.6

V

0

V_CC

+85

V

−40

°C

[1] 5 V tolerant.

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19. Static characteristics

Table 110:Static characteristics; supply pins

V_CC= 3.0 to 3.6 V or 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

V_CC= +5 V

V_reg(3.3)

I_CC

Parameter

Conditions

Min

Typ

Max

Unit

internal regulator output

operating supply current

suspend supply current

3.0^[1]

3.3

47

40

22

18

3.6

V

-

mA

µA

mA

I_CC(susp

)

500

I_CC(HC

)

operating supply current for HC DC is suspended

operating supply current for DC HC is suspended

-

I_CC(DC

V_CC= +3.3 V

I_CC

operating supply current

-

50

-

mA

µA

I_CC(susp

)

suspend supply current

150

22

I_CC(HC

)

operating supply current for HC DC is suspended

operating supply current for DC HC is suspended

mA

I_CC(DC

18

[1] In suspend mode, the minimum voltage is 2.7 V.

Table 111:Static characteristics: digital pins

V_CC= 3.0 to 3.6 V or 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Input levels

V_IL

Parameter

Conditions

Min

Typ

Max

Unit

LOW-level input voltage

HIGH-level input voltage

-

0.8

-

V

V_IH

2.0

Schmitt trigger inputs

V_th(LH)positive-going threshold

1.4

0.9

0.4

-

1.9

1.5

0.7

V

voltage

V_th(HL)

negative-going threshold

voltage

V_hys

hysteresis voltage

Output levels

V_OL

LOW-level output voltage

HIGH-level output voltage

I_OL= rated drive

I_OL= 20 µA

-

0.4

0.1

-

V

-

[1]

V_OH

I_OH= rated drive

I_OH= 20 µA

2.4

V

_reg(3.3)− 0.1

-

Leakage current

I_LI

input leakage current

pin capacitance

-

±5

µA

C_IN

pin to GND

5

pF

Open-drain outputs

I_OZ

OFF-state output current

-

±5

µA

[1] Not applicable for open-drain outputs.

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Table 112:Static characteristics: analog I/O pins (D+, D−)

V_CC= 3.0 to 3.6 V or 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Input levels

V_DI

Parameter

Conditions

Min

Typ

Max

Unit

[1]

differential input sensitivity

|V_I(D+)− V_I(D−)

|

0.2

0.8

-

V

V_CM

differential common mode

voltage

includes V_DIrange

2.5

V_IL

LOW-level input voltage

HIGH-level input voltage

-

0.8

-

V

V_IH

2.0

Output levels

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

R_L= 1.5 kΩ to +3.6 V

R_L= 15 kΩ to GND

-

0.3

3.6

V

2.8

Leakage current

I_LZ

OFF-state leakage current

-

±10

10

µA

pF

kΩ

Capacitance

C_IN

transceiver capacitance

pin to GND

-

Resistance

R_PD

pull-down resistance on HC’s

DP/DM

enable internal

resistors

11

19

R_PU

pull-up resistance on D_DP

driver output impedance

input impedance

SoftConnect = ON

steady-state drive

1.1

29

10

-

1.9

44

-

kΩ

Ω

[2]

Z_DRV

Z_INP

MΩ

Termination

V_TERM

termination voltage for

3.0^[3]

-

3.6

V

upstream port pull-up (R_PU

)

[1] D+ is the USB positive data pin; D− is the USB negative data pin.

[2] Includes external resistors of 18 Ω ±1% on both H_D+ and H_D−.

[3] In suspend mode, the minimum voltage is 2.7 V.

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20. Dynamic characteristics

Table 113:Dynamic characteristics

V_CC= 3.0 to 3.6 V or 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Reset

Parameter

Conditions

Min

Typ

Max

Unit

t_W(RESET)

pulse width on input RESET

crystal oscillator running

50

-

µs

[1]

crystal oscillator

stopped

ms

Crystal oscillator

f_XTAL

crystal frequency

-

6

-

MHz

[1] Dependent on the crystal oscillator start-up time.

Table 114:Dynamic characteristics: analog I/O pins (D+, D−)^[1]

V_CC= 3.0 to 3.6 V or 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; C_L= 50 pF; R_PU= 1.5 kΩ ±5% on D+ to V_TERM; unless

otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

t_FR

rise time

C_L= 50 pF;

10 to 90% of

4

-

20

ns

|V_OH− V_OL

|

t_FF

fall time

C_L= 50 pF;

90 to 10% of

4

-

20

ns

|V_OH− V_OL

|

[2]

FRFM

V_CRS

differential rise/fall time

90

-

111.11

2.0

%

V

matching (t_FR/t_FF

)

[2][3]

output signal crossover voltage

1.3

[1] Test circuit; see Figure 57.

[2] Excluding the ﬁrst transition from Idle state.

[3] Characterized only, not tested. Limits guaranteed by design.

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20.1 Timing symbols

Table 115:Legend for timing characteristics

Symbol

Description

Time symbols

t

time

T

cycle time (periodic signal)

Signal names

A

address;

DMA acknowledge (DACK)

clock;

C

D

command

data input;

data

E

G

I

chip enable

output enable

instruction (program memory content);

input (general)

L

address latch enable (ALE)

program store enable (PSEN, active LOW);

propagation delay

data output

P

Q

R

read signal (RD, active LOW);

read (action);

DMA request (DREQ)

chip select

S

W

write signal (WR, active LOW);

write (action);

pulse width

U

undeﬁned

Y

output (general)

Logic levels

H

L

logic HIGH

logic LOW

P

S

V

X

Z

stop, not active (OFF)

start, active (ON)

valid logic level

invalid logic level

high-impedance (ﬂoating, three-state)

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20.2 Parallel I/O timing

Table 116:Dynamic characteristics: parallel interface timing

Symbol

Parameter

Conditions

16-bit bus

Min

Unit

Max

Read timing

t_SHSL

ﬁrst RD/WR after CMD

CS LOW to RD LOW

RD HIGH to CS HIGH

RD LOW pulse width

RD HIGH to next RD LOW

RD cycle

300

0

-

ns

t_SLRL

t_RHSH

t_RL

t_RHRL

t_RC

t_RHDZ

t_RLDV

0

33

110

143

3

RD data hold time

RD LOW to data valid

32

Write timing

t_WL

WR LOW pulse width

WR HIGH to next WR LOW

WR cycle

26

110

136

0

-

ns

t_WHWL

t_WC

t_SLWL

CS LOW to WR LOW

WR HIGH to CS HIGH

WR data setup time

WR data hold time

t_WHSH

t_WDSU

t_WDH

0

5

8

CS

A0

t

SLWL

SLRL

t

SHSL

t

WHSH

RHSH

t

RHRL

t

RL

RC

RD

t

RLDV

t

RHDZ

data

[

]

D 15:0

data

valid

data

valid

data

valid

t

WHWL

t

WL

WC

WR

t

WDSU

WDH

data

valid

data

valid

data

valid

data

valid

data

valid

D[15:0]

MGT969

Fig 45. 16-bit microprocessor parallel I/O interface timing.

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20.3 DMA interface timing

20.3.1 HC single-cycle burst mode DMA timing

Table 117:Dynamic characteristics: HC single-cycle burst mode DMA timing

Symbol

Parameter

Conditions

16-bit bus

Min

Unit

Max

Read/write timing

t_RL

RD pulse width

33

-

ns

t_RLDV

t_RHDZ

t_WSU

t_WHD

t_AHRH

t_ALRL

t_DC

read process data setup time

read process data hold time

write process data setup time

write process data hold time

DACK1 HIGH to DREQ1 HIGH

DACK1 LOW to DREQ1 LOW

DREQ1 cycle

26

-

0

-

5

-

0

-

62 to 81

-

21

-

[1]

t_SHAH

t_RHAL

t_DS

RD/WR HIGH to DACK1 HIGH

DREQ1 HIGH to DACK1 LOW

DREQ1 pulse spacing

> 0

-

> 0

-

125 to 146

-

[1] t_RHAL+ t_DS+ t_ALRL

.

t

DC

DREQ1

DACK1

t

DS

t

ALRL

t

SHAH

t

RHAL

t

AHRH

t

RHDZ

RLDV

[

]

D 15:0

data

valid

(read)

[

D 15:0

data

valid

(write)

t

WSU

RD or WR

MGT970

t

WHD

Fig 46. HC single-cycle burst mode DMA timing.

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20.3.2 HC multi-cycle burst mode DMA timing

Table 118:Dynamic characteristics: HC multi-cycle burst mode DMA timing

Symbol Parameter Conditions

16-bit bus

Min

Unit

Max

Read/write timing (for 4-cycle and 8-cycle burst mode)

t_RL

WR/RD LOW pulse width

42

60

-

ns

t_RHRL

WR/RD HIGH to next WR/RD

LOW

t_RC

WR/RD cycle

102

22

-

ns

t_SLRL

RD/WR LOW to DREQ1 LOW

RD/WR HIGH to DACK1 HIGH

DREQ1 HIGH to DACK1 LOW

DREQ1 cycle

64

-

t_SHAH

t_RHAL

> 0

[1]

t_DC

-

ns

t_DS(read)

t_DS(write)

DREQ1 pulse spacing (read)

DREQ1 pulse spacing (write)

4-cycle burst mode

8-cycle burst mode

4-cycle burst mode

8-cycle burst mode

105

150

62 to 84

150 to 167

ns

[1] t_SLAL+ (4 or 8)t_RC+ t_DS

.

t

DS

DREQ1

t

SLRL

RHSH

t

SLAL

DACK1

t

SHAH

RHRL

t

RL

RD or WR

MGT971

t

RC

Fig 47. HC multi-cycle burst mode DMA timing.

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20.3.3 External EOT timing for HC single-cycle burst mode DMA

DREQ1

DACK1

RD or WR

EOT

MGT972

t

> 0 ns

EL

Fig 48. External EOT timing for HC single-cycle burst mode DMA.

20.3.4 External EOT timing for HC multi-cycle burst mode DMA

DREQ1

DACK1

RD or WR

EOT

MGT973

t

> 0 ns

EL

Fig 49. External EOT timing for HC multi-cycle burst mode DMA.

20.3.5 DC single-cycle DMA timing (8237 mode)

Table 119:Dynamic characteristics: DC single-cycle DMA timing (8237 mode)

Symbol

t_ALRL

Parameter

Conditions

Min

Typ

Max

40

Unit

ns

DACK2 ON to DREQ2 OFF

DACK2 OFF to DREQ2 ON

-

t_AHRH

22

ns

t

AHRH

ALRL

DREQ2

DACK2

MGT974

Fig 50. DC single-cycle DMA timing (8237 mode).

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20.3.6 DC single-cycle DMA timing (DACK-only mode)

Table 120:Dynamic characteristics: DC single-cycle DMA timing (DACK-only mode)

Symbol

t_ALRL

Parameter

Conditions

Min

Typ

Max

40

22

3

Unit

ns

DACK2 ON to DREQ2 OFF

DACK2 OFF to DREQ2 ON

DACK2 ON to data valid

DACK2 OFF to data invalid

-

t_AHRH

t_ALDV

ns

t_AHDZ

ns

t

AHRH

ALRL

DREQ2

DACK2

t

ALDV

AHDZ

[

]

D 15:0

MGT975

Fig 51. DC single-cycle DMA timing (DACK-only mode).

20.3.7 EOT timing for DC single-cycle DMA timing

Table 121:Dynamic characteristics: EOT timing for DC single-cycle DMA timing

Symbol

t_RHSH

t_AHRH

t_SHAH

t_EL

Parameter

Conditions

Min

22

-

Typ

Max

Unit

ns

DREQ2 ON to RD/WR OFF

DACK2 OFF to DREQ2 ON

RD/WR OFF to DACK2 OFF

EOT pulse width

-

22

-

ns

0

ns

22

-

ns

t

AHRH

t

RHSH

DREQ2

t

SHAH

DACK2

RD or WR

t

EL

EOT

MGT976

Fig 52. EOT timing for DC single-cycle DMA timing.

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20.3.8 DC multi-cycle burst mode DMA timing

Table 122:Dynamic characteristics: DC multi-cycle burst mode DMA timing

Symbol

t_RHSH

t_SLRL

Parameter

Conditions

Min

22

-

Typ

Max

Unit

ns

DREQ2 ON to ﬁrst RD/WR OFF

last RD/WR ON to DREQ2 OFF

last RD/WR OFF to DACK2 OFF

DMA burst repeat interval

-

60

-

ns

t_SHAH

t_RHRL

0

ns

180

-

ns

t

SLRL

RHSH

DREQ2

DACK2

t

SHAH

t

RHRL

RD or WR

MGT977

Fig 53. DC multi-cycle burst mode DMA timing.

20.3.9 DMA terminated by EOT

Table 123:Dynamic characteristics: DMA terminated by EOT

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_ELRL

EOT ON to DREQ2 OFF

-

40

ns

t

ELRL

DREQ2

DACK2

RD or WR

EOT

MGT978

Fig 54. DMA terminated by EOT.

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21. Application information

21.1 Typical interface circuit

V

+

3.3 V

+

5 V

5 V 3.3 V

DD

MOSFET

(2×)

SH7709

ISP1161

Vbus_DN2 Vbus_DN1

V

CC

[

]

[

]

D 15:0

+

3.3 V

5 V

H_OC1

H_OC2

A1

A2

A0

A1

FB1

FB2

H_PSW2

H_PSW1

22 Ω

(2×)

USB

downstream

port #1

CS5

RD

RD/WR

CS

RD

WR

H_DM1

H_DP1

H_DM2

H_DP2

47 pF

(2×)

DREQ0

DACK0

DREQ1

DACK1

DREQ1

DACK1

DREQ2

DACK2

EOT

D_DM

D_DP

V

+

reg

3.3 V

+

5 V

FB3

V

reg(3.3)

22 Ω

(2×)

USB

downstream

port #2

CLKOUT

EXTAL

XTAL

IRQ2

IRQ3

INT1

INT2

V

DD

V

hold1

hold2

V

DD

PTC0

PTC1

PTC2

PTC3

H_WAKEUP

H_SUSPEND

D_WAKEUP

D_SUSPEND

47 pF

(2×)

LED

FB4

1 kΩ

NDP_SEL

GL

EXTAL2

XTAL2

GND

Vbus_UP

FB5

RSTOUT

RESET

32

kHz

D_VBUS

CLKOUT

XTAL2

XTAL1

V

reg

CLKOUT

6 MHz

USB

upstream

port

22 Ω

(2×)

1.5 kΩ

7

FB6

DGND

AGND

22 pF

47 pF

(2×)

MGT979

For MOSFET, R_DSon= 150 mΩ.

Fig 55. Typical interface circuit to Hitachi SH-3 (SH7709) RISC processor.

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21.2 Interfacing a ISP1161 with a SH7709 RISC processor

This section shows a typical interface circuit between ISP1161 and a RISC

processor. The Hitachi SH-3 series RISC processor SH7709 is used as the example.

The main ISP1161 signals to be taken into consideration for connecting to a SH7709

RISC processor are:

A 16-bit data bus: D15-D0 for ISP1161. ISP1161 is ‘little endian‘ compatible.

•

Two address lines A1 and A0 are needed for a complete addressing of the

ISP1161 internal registers:

– A1 = 0 and A0 = 0 will select the Data Port of the Host Controller

– A1 = 0 and A0 = 1 will select the Command Port of the Host Controller

– A1 = 1 and A0 = 0 will select the Data Port of the Device Controller

– A1 = 1 and A0 = 1 will select the Command Port of the Device Controller

The CS line is used for chip selection of ISP1161 in a certain address range of the

RISC system. This signal is active LOW.

•

RD and WR are common read and write signals. These signals are active LOW.

There are two DMA channel standard control lines:

– DREQ1 and DACK1

•

– DREQ2 and DACK2

(in each case one channel is used by the host controller and the other channel is

used by the device controller). These signals have programmable active levels.

Two interrupt lines: INT1 (used by the host controller) and INT2 (used by the

device controller). Both have programmable level/edge and polarity (active HIGH

or LOW).

•

The internal 15kΩ pull-down resistors are used for the HCs two USB downstream

ports.

•

The RESET signal is active LOW.

Remark: SH7709’s system clock input is for reference only. Please refer to SH7709’s

speciﬁcation for its actual use.

ISP1161 can work under either +3.3 V or +5.0 V power supply; however, its internal

core actually works at +3.3 V. When using +5 V as the power supply input, the

internal DC/DC regulator will be bypassed. It is best to connect all four power supply

pins (V_CC, V_reg(3.3), V_hold1and V_hold2) to the 3.3 V power supply (for more information

see Section 16). All of the ISP1161’s I/O pins are +5 V-tolerant. This feature allows

the ISP1161 the ﬂexibility to be used in an embedded system under either a +3.3 V or

a +5 V power supply.

A typical SH7709 interface circuit is shown in Figure 55.

21.3 Typical software model

This section shows a typical software requirement for an embedded system that

incorporates ISP1161. The software model for a digital still camera (DSC) is used as

the example for illustration (as shown in Figure 56). Two components of system

software are required to make full use of the features in ISP1161: the host stack and

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the device stack. The device stack provides API directly to the application task for

device function; the host stack provides API for Class driver and device driver, both of

which provide API for application tasks for host function.

Application

MECHANISM CONTROL TASK

layer

IMAGE PROCESSING TASKS

FILE MANAGEMENT

PRINTER UI/CONTROL

FILE TRANSFER

OS

DEVICE DRIVERS

Class

driver

PC

MASS STORAGE CLASS DRIVER

PRINTING CLASS DRIVER

USB

host/device

stack

HOST STACK

DEVICE STACK

ISP1161 HAL

USB Upstream

Printer

RISC

ROM

RAM

ISP1161

LEN

CONTROL

Flash card

Reader/

Writer

USB Downstream

MGT980

Digital Still Camera

Fig 56. ISP1161 software model for DSC application.

22. Test information

The dynamic characteristics of the analog I/O ports (D+ and D−) as listed in

Table 114 were determined using the circuit shown in Figure 57.

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test point

22 Ω

D.U.T.

C

L

15 kΩ

50 pF

MGT967

Load capacitance:

C_L= 50 pF (full-speed mode).

Speed:

full-speed mode only: internal 1.5 kΩ pull-up resistor on D_DP.

Fig 57. Load impedance for D_DP and D_DM pins.

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23. Package outline

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.60

mm

0.25

0.5

1.0

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

99-12-27

00-01-19

SOT314-2

136E10

MS-026

Fig 58. LQFP64 (SOT314-2) package outline.

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LQFP64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm

SOT414-1

y

X

A

48

33

49

32

Z

E

e

A

2

A

H

E

(A )

3

A

1

w M

p

θ

b

pin 1 index

L

p

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

θ

1

2

3

p

E

p

D

E

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.23 0.20 7.1

0.13 0.09 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.64 0.64

0.36 0.36

1.6

mm

0.25

0.4

1.0

0.2 0.08 0.08

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

99-12-27

00-01-19

SOT414-1

136E06

MS-026

Fig 59. LQFP64 (SOT414-1) package outline.

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24. Soldering

24.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account

of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne

pitch SMDs. In these situations reﬂow soldering is recommended.

24.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling

or pressure-syringe dispensing before package placement.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 to 250 °C. The top-surface

temperature of the packages should preferable be kept below 220 °C for thick/large

packages, and below 235 °C small/thin packages.

24.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging

and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal

results:

Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

•

For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must

incorporate solder thieves downstream and at the side corners.

•

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During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time is 4 seconds at 250 °C. A mildly-activated ﬂux will eliminate the

need for removal of corrosive residues in most applications.

24.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low

voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time

must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

24.5 Package related soldering information

Table 124:Suitability of surface mount IC packages for wave and reﬂow soldering

methods

Package

Soldering method

Wave

Reﬂow^[1]

suitable

BGA, HBGA, LFBGA, SQFP, TFBGA

not suitable

not suitable^[2]

HBCC, HLQFP, HSQFP, HSOP, HTQFP,

HTSSOP, HVQFN, SMS

PLCC^[3], SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO

suitable

not recommended^{[3] [4]}

not recommended^[5]

[1] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal

or external package cracks may occur due to vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

[2] These packages are not suitable for wave soldering as a solder joint between the printed-circuit board

and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top

version).

[3] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[4] Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger

than 0.8 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[5] Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

25. Revision history

Table 125:Revision history

Rev Date

CPCN

-

Description

01 20010703

Product data; initial version.

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26. Data sheet status

[1]

[2]

Data sheet status

Product status

Deﬁnition

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips Semiconductors

reserves the right to change the speciﬁcation in any manner without notice.

Preliminary data

Product data

Qualiﬁcation

Production

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published at a

later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to

improve the design and supply the best possible product.

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the right to

make changes at any time in order to improve the design, manufacturing and supply. Changes will be

communicated according to the Customer Product/Process Change Notiﬁcation (CPCN) procedure

SNW-SQ-650A.

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

27. Deﬁnitions

28. Disclaimers

Short-form speciﬁcation — The data in

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

a

short-form speciﬁcation is

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Right to make changes — Philips Semiconductors reserves the right to

make changes, without notice, in the products, including circuits, standard

cells, and/or software, described or contained herein in order to improve

design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products

are free from patent, copyright, or mask work right infringement, unless

otherwise speciﬁed.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

29. Trademarks

GoodLink — is a trademark of Koninklijke Philips Electronics N.V.

Hitachi — is a registered trademark of Hitachi Ltd.

ARM — is a trademark of ARM Holdings PLC.

StrongARM — is a trademark of ARM Holdings PLC.

SoftConnect — is a trademark of Koninklijke Philips Electronics N.V.

9397 750 08313

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Philips Semiconductors - a worldwide company

Argentina: see South America

Netherlands: Tel. +31 40 278 2785, Fax. +31 40 278 8399

New Zealand: Tel. +64 98 49 4160, Fax. +64 98 49 7811

Norway: Tel. +47 22 74 8000, Fax. +47 22 74 8341

Philippines: Tel. +63 28 16 6380, Fax. +63 28 17 3474

Poland: Tel. +48 22 5710 000, Fax. +48 22 5710 001

Portugal: see Spain

Australia: Tel. +61 2 9704 8141, Fax. +61 2 9704 8139

Austria: Tel. +43 160 101, Fax. +43 160 101 1210

Belarus: Tel. +375 17 220 0733, Fax. +375 17 220 0773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Tel. +359 268 9211, Fax. +359 268 9102

Canada: Tel. +1 800 234 7381

Romania: see Italy

Russia: Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

China/Hong Kong: Tel. +852 2 319 7888, Fax. +852 2 319 7700

Colombia: see South America

Czech Republic: see Austria

Slovenia: see Italy

Denmark: Tel. +45 3 288 2636, Fax. +45 3 157 0044

Finland: Tel. +358 961 5800, Fax. +358 96 158 0920

France: Tel. +33 1 4728 6600, Fax. +33 1 4728 6638

Germany: Tel. +49 40 23 5360, Fax. +49 402 353 6300

Hungary: Tel. +36 1 382 1700, Fax. +36 1 382 1800

India: Tel. +91 22 493 8541, Fax. +91 22 493 8722

Indonesia: see Singapore

South Africa: Tel. +27 11 471 5401, Fax. +27 11 471 5398

South America: Tel. +55 11 821 2333, Fax. +55 11 829 1849

Spain: Tel. +34 33 01 6312, Fax. +34 33 01 4107

Sweden: Tel. +46 86 32 2000, Fax. +46 86 32 2745

Switzerland: Tel. +41 14 88 2686, Fax. +41 14 81 7730

Taiwan: Tel. +886 22 134 2451, Fax. +886 22 134 2874

Thailand: Tel. +66 23 61 7910, Fax. +66 23 98 3447

Turkey: Tel. +90 216 522 1500, Fax. +90 216 522 1813

Ukraine: Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Tel. +44 208 730 5000, Fax. +44 208 754 8421

United States: Tel. +1 800 234 7381

Ireland: Tel. +353 17 64 0000, Fax. +353 17 64 0200

Israel: Tel. +972 36 45 0444, Fax. +972 36 49 1007

Italy: Tel. +39 039 203 6838, Fax +39 039 203 6800

Japan: Tel. +81 33 740 5130, Fax. +81 3 3740 5057

Korea: Tel. +82 27 09 1412, Fax. +82 27 09 1415

Malaysia: Tel. +60 37 50 5214, Fax. +60 37 57 4880

Mexico: Tel. +9-5 800 234 7381

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: Tel. +381 11 3341 299, Fax. +381 11 3342 553

Middle East: see Italy

For all other countries apply to: Philips Semiconductors,

Marketing Communications,

Internet: http://www.semiconductors.philips.com

Building BE, P.O. Box 218, 5600 MD EINDHOVEN,

The Netherlands, Fax. +31 40 272 4825

(SCA72)

9397 750 08313

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Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

12.4

End-Of-Transfer conditions. . . . . . . . . . . . . . . 51

13

HC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

HC control and status registers. . . . . . . . . . . . 54

HC frame counter registers. . . . . . . . . . . . . . . 62

HC Root Hub registers . . . . . . . . . . . . . . . . . . 66

HC DMA and interrupt control registers . . . . . 76

HC miscellaneous registers . . . . . . . . . . . . . . 81

HC buffer RAM control registers. . . . . . . . . . . 82

13.1

13.2

13.3

13.4

13.5

13.6

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 7

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

14

DC commands and registers . . . . . . . . . . . . . 86

Initialization commands. . . . . . . . . . . . . . . . . . 89

Data flow commands . . . . . . . . . . . . . . . . . . . 96

General commands. . . . . . . . . . . . . . . . . . . . 100

7

Functional description . . . . . . . . . . . . . . . . . . 11

PLL clock multiplier. . . . . . . . . . . . . . . . . . . . . 11

Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . 11

Analog transceivers . . . . . . . . . . . . . . . . . . . . 11

Philips Serial Interface Engine (SIE). . . . . . . . 11

SoftConnect (in DC) . . . . . . . . . . . . . . . . . . . . 11

GoodLink (in DC) . . . . . . . . . . . . . . . . . . . . . . 12

Suspend and wakeup (in DC). . . . . . . . . . . . . 12

14.1

14.2

14.3

7.1

7.2

7.3

7.4

7.5

7.6

7.7

15

16

17

18

19

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 105

External clock input. . . . . . . . . . . . . . . . . . . . 106

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . 107

Static characteristics. . . . . . . . . . . . . . . . . . . 108

8

Microprocessor bus interface. . . . . . . . . . . . . 12

I/O addressing mode . . . . . . . . . . . . . . . . . . . 12

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Microprocessor read/write ISP1161’s

internal control registers by PIO mode . . . . . 14

Microprocessor read/write ISP1161’s

internal FIFO buffer RAM by PIO mode. . . . . 17

Microprocessor read/write ISP1161’s

internal FIFO buffer RAM by DMA mode. . . . 17

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.1

8.2

8.3

20

Dynamic characteristics . . . . . . . . . . . . . . . . 111

Timing symbols. . . . . . . . . . . . . . . . . . . . . . . 112

Parallel I/O timing . . . . . . . . . . . . . . . . . . . . . 113

DMA interface timing. . . . . . . . . . . . . . . . . . . 114

20.1

20.2

20.3

8.4

8.5

8.6

21

21.1

21.2

Application information. . . . . . . . . . . . . . . . . 119

Typical interface circuit . . . . . . . . . . . . . . . . . 119

Interfacing a ISP1161 with a SH7709

RISC processor . . . . . . . . . . . . . . . . . . . . . . 120

Typical software model . . . . . . . . . . . . . . . . . 120

21.3

22

9

The USB host controller (HC) . . . . . . . . . . . . . 22

The HC’s four USB states. . . . . . . . . . . . . . . . 22

Generating USB traffic . . . . . . . . . . . . . . . . . . 22

PTD data structure . . . . . . . . . . . . . . . . . . . . . 24

HC’s internal FIFO buffer RAM structure . . . . 27

HC’s operational model . . . . . . . . . . . . . . . . . 33

Microprocessor loading. . . . . . . . . . . . . . . . . . 36

Internal 15 kW pull-down resistors for

Test information. . . . . . . . . . . . . . . . . . . . . . . 121

Package outline . . . . . . . . . . . . . . . . . . . . . . . 123

9.1

9.2

9.3

9.4

9.5

9.6

9.7

23

24

24.1

Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 125

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 125

Manual soldering. . . . . . . . . . . . . . . . . . . . . . 126

Package related soldering information . . . . . 126

24.2

24.3

24.4

24.5

downstream ports . . . . . . . . . . . . . . . . . . . . . 36

Overcurrent detection and power switching

9.8

control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

25

26

27

28

29

Revision history . . . . . . . . . . . . . . . . . . . . . . . 126

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 127

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 127

10

10.1

10.2

Suspend and wakeup (in HC) . . . . . . . . . . . . . 40

HC suspended state . . . . . . . . . . . . . . . . . . . . 40

HC wakeup from suspended state . . . . . . . . . 41

11

The USB device controller (DC) . . . . . . . . . . . 42

DC data transfer operation . . . . . . . . . . . . . . . 42

Device DMA transfer. . . . . . . . . . . . . . . . . . . . 43

Endpoint descriptions . . . . . . . . . . . . . . . . . . . 44

11.1

11.2

11.3

12

DMA transfer for the Device Controller . . . . . 48

Selecting an endpoint for DMA transfer . . . . . 48

8237 compatible mode . . . . . . . . . . . . . . . . . . 49

DACK-only mode . . . . . . . . . . . . . . . . . . . . . . 50

12.1

12.2

12.3

Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 3 July 2001

Document order number: 9397 750 08313


型号：	ISP1161BD
厂家：	NXP
描述：	Full-speed Universal Serial Bus single-chip host and device controller 全速通用串行总线单片主机和设备控制器控制器
文件：	总127页 (文件大小：2519K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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