ISP1705AET,118_技术文档

ISP1705

ULPI Hi-Speed USB transceiver

Rev. 01 — 13 June 2008

Product data sheet

1. General description

The ISP1705 is a UTMI+ Low Pin Interface (ULPI) Hi-Speed Universal Serial Bus (USB)

transceiver that is fully compliant with Universal Serial Bus Speciﬁcation Rev. 2.0,

On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.3 and UTMI+ Low Pin

Interface (ULPI) Speciﬁcation Rev. 1.1.

The ISP1705 can transmit and receive USB data at high speed (480 Mbit/s), full speed

(12 Mbit/s) and low speed (1.5 Mbit/s), and provides a pin-optimized, physical layer

front-end attachment to the USB host, peripheral or OTG controller with Single Data Rate

(SDR) or Dual Data Rate (DDR) ULPI link. The ISP1705 can transparently transmit and

receive UART signaling.

It is ideal for use in portable electronic devices, such as mobile phones, digital still

cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio

players. It allows USB Application-Speciﬁc Integrated Circuits (ASICs), Programmable

Logic Devices (PLDs) or any system chip set to interface with the physical layer of the

USB through an 8-pin (DDR) or 12-pin (SDR) interface.

The ISP1705 can interface to devices with digital I/O voltages in the range of 3.0 V to

3.6 V.

The ISP1705 is available in HVQFN36 and TFBGA36 packages.

2. Features

I Fully complies with:

N USB: Universal Serial Bus Speciﬁcation Rev. 2.0

N OTG: On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.3

N ULPI: UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

I Interfaces to USB host, peripheral or OTG cores; optimized for portable devices or

system ASICs with built-in ULPI link

I Complete Hi-Speed USB physical front-end solution that supports high speed

(480 Mbit/s), full speed (12 Mbit/s) and low speed (1.5 Mbit/s)

N Integrated 45 Ω ± 10 % high-speed termination resistors, 1.5 kΩ ± 5 % full-speed

device pull-up resistor, and 15 kΩ ± 5 % host termination resistors

N Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive

N USB clock and data recovery to receive USB data up to ±500 ppm

N Insertion of stuff bits during transmit and discarding of stuff bits during receive

N Non-Return-to-Zero Inverted (NRZI) encoding and decoding

N Supports bus reset, suspend, resume and high-speed detection handshake (chirp)

ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

I Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP)

and Session Request Protocol (SRP)

N Supports external charge pump or external V_BUSpower switch

N Complete control over USB termination resistors

N Data line and V_BUSpulsing session request methods

N Integrated V_BUSvoltage comparators

N Integrated cable (ID) detector

I Flexible system integration and very low power consumption, optimized for portable

devices

N 3.0 V to 4.5 V supply voltage input range

N Internal voltage regulator supplies 2.7 V or 3.3 V and 1.8 V

N Supports interfacing I/O voltage of 3.0 V to 3.6 V; separate I/O voltage supply pins

minimize crosstalk

N Power down internal regulators in Power-down mode when V_CC(I/O)is not present

or when the chip is not selected

N Typical operating current of 13 mA to 32 mA, depending on the USB speed and

bus utilization

N Typical current consumption I_CCis 70 µA in suspend mode and 0.5 µA in

Power-down mode

N 3-state ULPI interface by the CHIP_SEL or CHIP_SEL_N pin, allowing bus reuse

by other applications

I Highly optimized ULPI compliant

N 60 MHz, 8-pin or 12-pin interface between the core and the transceiver, including a

4-bit DDR bus or an 8-bit SDR bus

N DDR or SDR interface selectable by pin

N Supports 60 MHz output clock conﬁguration

N Integrated Phase-Locked Loop (PLL) supporting input clock frequencies of

13 MHz, 19.2 MHz, 24 MHz or 26 MHz

N Crystal or clock frequency selectable by pin

N Fully programmable ULPI-compliant register set

N 3-pin or 6-pin full-speed or low-speed serial mode

N Internal Power-On Reset (POR) circuit

I UART interface:

N Supports transparent UART signaling on DP and DM pins for the UART accessory

application

N 2.7 V UART signaling on DP and DM pins

N Entering UART mode by register setting

N Exiting UART mode by asserting STP or by toggling the CHIP_SEL or

CHIP_SEL_N pin

I Full industrial grade operating temperature range from −40 °C to +85 °C

I ESD compliance:

N JESD22-A114D 2 kV contact Human Body Model (HBM)

N JESD22-A115-A 200 V Machine Model (MM)

N JESD22-C101-C 500 V Charged Device Model (CDM)

N IEC 61000-4-2 8 kV contact on the DP and DM pins

ISP1705_1

Product data sheet

Rev. 01 — 13 June 2008

2 of 89

ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

I Available in small HVQFN36 and TFBGA36 Restriction of Hazardous Substances

(RoHS) compliant, halogen-free and lead-free packages

3. Applications

I Digital still camera

I Digital TV

I Digital Video Disc (DVD) recorder

I External storage device, for example:

N Magneto-Optical (MO) drive

N Optical drive (CD-ROM, CD-RW, CD-DVD)

N Zip drive

I Mobile phone

I MP3 player

I PDA

I Printer

I Scanner

I Set-Top Box (STB)

I Video camera

4. Ordering information

Table 1.

Ordering information

Type number Package

Name

Description

Version

ISP1705HN

HVQFN36 plastic thermal enhanced very thin quad ﬂat package; SOT818-1

no leads; 36 terminals; body 5 × 5 × 0.85 mm

ISP1705AET TFBGA36

plastic thin ﬁne-pitch ball grid array package; 36 balls; SOT912-1

body 3.5 × 3.5 × 0.8 mm

5. Marking

Table 2.

Marking codes

Type number

ISP1705HN

ISP1705AET

Marking code^[1]

1705

705A

[1] The package marking is the ﬁrst line of text on the IC package and can be used for IC identiﬁcation.

ISP1705_1

Product data sheet

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3 of 89

ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

6. Block diagram

29

CLOCK

1, 2, 24,

25, 27, 28,

30, 36

USB DATA

SERIALIZER

6

ULPI

INTERFACE

CONTROLLER

DP

8

HI-SPEED

USB ATX

DATA

[7:0]

ULPI

INTERFACE

19

22

23

DIR

TERMINATION

RESISTORS

5

USB DATA

DESERIALIZER

REGISTER

MAP

DM

STP

NXT

DATA0

UART

BUFFER

DATA1

7

DDR OR SDR

SELECTION

CFG0

OTG MODULE

ISP1705

34

CHIP_SEL_N

CHIP_SEL

ID

9

ID

DETECTOR

35

31

32

CLOCK

FREQUENCY

SELECTION

CFG1

CFG2

V

BUS

COMPARATORS

13

V

BUS

SRP CHARGE

AND DISCHARGE

RESISTORS

GLOBAL

CLOCKS

PLL

16

XTAL1

XTAL2

CRYSTAL

OSCILLATOR

17

14

10

PORT

POWER

CONTROL

3, 21, 26, 33

PSW_N

FAULT

interface voltage

internal power

V

CC(I/O)

18

12

20

4

POWER-ON

RESET

RESET_N

RREF

REG1V8

REG3V3

POR

BAND GAP

REFERENCE

VOLTAGE

V

REF

8

VOLTAGE

REGULATOR

V

CC

15

11

004aaa994

GND

n.c.

This ﬁgure shows the HVQFN pinout. For the TFBGA ballout, see Table 3.

Fig 1. Block diagram

ISP1705_1

Product data sheet

Rev. 01 — 13 June 2008

4 of 89

ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

7. Pinning information

7.1 Pinning

terminal 1

index area

DATA1

DATA0

1

2

3

4

5

6

7

8

9

27 DATA5

26

V

CC(I/O)

V

25 DATA6

24 DATA7

23 NXT

CC(I/O)

RREF

DM

DP

ISP1705HN

22 STP

CFG0

21 V

CC(I/O)

V

CC

20 RESET_N

19 DIR

ID

004aaa995

Transparent top view

Fig 2. Pin conﬁguration HVQFN36

ball A1

index area

ISP1705AET

1

2

3

4

5

6

A

B

C

D

E

F

004aab094

Transparent top view

Fig 3. Pin conﬁguration TFBGA36

ISP1705_1

Product data sheet

Rev. 01 — 13 June 2008

5 of 89

ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

7.2 Pin description

Table 3.

Pin description

Symbol^[1]

Type^[2]Description^[3]

HVQFN36

TFBGA36

(ISP1705HN) (ISP1705AET)

DATA1

DATA0

1

2

A1

B1

I/O

ULPI data pin 1

3-state output; plain input

ULPI data pin 0

3-state output; plain input

V_CC(I/O)

RREF

DM

3

4

5

B2

C2

C1

P

input I/O supply voltage; 3.0 V to 3.6 V; a 0.1 µF decoupling

capacitor is recommended

AI/O

resistor reference; connect through a 12 kΩ ± 1 % resistor to

GND

connect to the D− pin of the USB connector

• USB mode: D− input or output

• UART mode: TXD output

DP

6

7

D1

E1

AI/O

connect to the D+ pin of the USB connector

• USB mode: D+ input or output

• UART mode: RXD input

During UART mode, an internal 125 kΩ ± 20 % pull-up resistor is

present on this pin.

CFG0

I

select SDR or DDR ULPI interface:

• SDR: connect this pin to GND

• DDR: connect this pin to REG3V3

plain input; TTL

V_CC

8

F3

D3

E2

P

I

input supply voltage or battery source; 3.0 V to 4.5 V

Remark: Below 3.0 V, USB full-speed and low-speed

transactions are not guaranteed to work, though some devices

may work with the ISP1705 at these voltages.

ID

9

identiﬁcation (ID) pin of the micro-USB connector; if this pin is not

in use, connect it directly to the REG3V3 pin (an internal 400 kΩ

pull-up resistor is present on this pin)

plain input; TTL

FAULT

10

I

input for the V_BUSdigital overcurrent or fault detector signal; if this

pin is not in use, connect it to GND

plain input, 5 V tolerant

not connected

n.c.

11

12

F1, F2

E3

-

REG3V3

P

3.3 V regulator output for USB mode or 2.7 V regulator output for

UART mode; requires parallel 0.1 µF and 4.7 µF capacitors;

internally powers ATX and other analog circuits; must not be used

to power external circuits

V_BUS

13

14

F4

D4

AI/O

OD

connect to the V_BUSpin of the USB connector; if this pin is not in

use, leave it open (R_{I(idle)(VBUS)}is present on this pin)

PSW_N

active-LOW external V_BUSpower switch or external charge pump

enable

open-drain output, 4 mA current sinking capability, 5 V tolerant

ground

GND

15

C5, D2, E4

-

ISP1705_1

Product data sheet

Rev. 01 — 13 June 2008

6 of 89

ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

Table 3.

Pin description …continued

Symbol^[1]

Type^[2]Description^[3]

HVQFN36

TFBGA36

(ISP1705HN) (ISP1705AET)

XTAL1

16

17

18

F5

F6

E6

AI/O

P

crystal oscillator or clock input; 1.8 V peak input allowed;

frequency depends on status on the CFG1 pin

XTAL2

crystal oscillator output; when a crystal oscillator is used, leave

this pin open

REG1V8

1.8 V regulator output; requires parallel 0.1 µF and 4.7 µF

capacitors; internally powers the digital core; must not be used to

power external circuits

DIR

19

20

E5

C4

O

I

ULPI direction signal

3-state output

RESET_N

active-LOW, asynchronous reset input

plain input

V_CC(I/O)

STP

21

22

B5

D6

P

I

input I/O supply voltage; 3.0 V to 3.6 V; a 0.1 µF decoupling

capacitor is recommended

ULPI stop signal

plain input

NXT

23

24

25

D5

C6

B6

O

ULPI next signal

3-state output

DATA7

DATA6

I/O

ULPI data pin 7

3-state output; plain input

ULPI data pin 6

3-state output; plain input

V_CC(I/O)

DATA5

26

27

-

P

input I/O supply voltage; 3.0 V to 3.6 V; a 0.1 µF decoupling

capacitor is recommended

A6

I/O

ULPI data pin 5

3-state output; plain input

ULPI data pin 4

DATA4

28

29

A5

A4

I/O

O

3-state output; plain input

CLOCK

60 MHz clock output when crystal is attached or clock is applied

on the XTAL1 pin

3-state output

DATA3

CFG1

CFG2

V_CC(I/O)

30

31

32

33

A3

B4

B3

I/O

ULPI data pin 3

3-state output; plain input

I

select crystal or clock frequency with CFG2; see Table 6

plain input

select crystal or clock frequency with CFG1; see Table 6

plain input

-

P

I

input I/O supply voltage; 3.0 V to 3.6 V; a 0.1 µF decoupling

capacitor is recommended

CHIP_SEL_N 34

C3

active-LOW chip select input; when this pin is not in use, connect

it to GND

plain input

ISP1705_1

Product data sheet

Rev. 01 — 13 June 2008

7 of 89

ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

Table 3.

Pin description …continued

Symbol^[1]

Type^[2]Description^[3]

HVQFN36

TFBGA36

(ISP1705HN) (ISP1705AET)

CHIP_SEL

35

-

I

active-HIGH chip select input; when this pin is not in use, connect

it to V_CC(I/O)

plain input

DATA2

GND

36

A2

-

I/O

P

ULPI data pin 2

3-state output; plain input

ground

exposed die

pad

[1] Symbol names ending with underscore N (for example, NAME_N) indicate active-LOW signals.

[2] I = input; O = output; I/O = digital input/output; OD = open-drain output; AI/O = analog input/output; P = power supply or ground pin.

[3] A detailed description of these pins can be found in Section 8.12.

ISP1705_1

Product data sheet

Rev. 01 — 13 June 2008

8 of 89

ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

8. Functional description

8.1 ULPI interface controller

The ISP1705 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface

(ULPI) Speciﬁcation Rev. 1.1. This interface must be connected to a USB link.

The ULPI interface controller provides the following functions:

• ULPI-compliant interface and register set

• Allows full control over the USB peripheral or host functionality

• Parses the USB transmit and receive data

• Prioritizes the USB receive data, USB transmit data, interrupts and register operations

• Low-power mode

• Transparent UART mode

• 3-pin serial mode

• 6-pin serial mode

• Generates RXCMDs (status updates)

• Maskable interrupts

For more information on the ULPI protocol, see Section 10.

8.2 USB serializer and deserializer

The USB data serializer prepares data to transmit on the USB bus. To transmit data, the

USB link sends a transmit command and data on the ULPI bus. The serializer performs

parallel-to-serial conversion, bit stufﬁng and NRZI encoding. For packets with a PID, the

serializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the end

of the packet. When the serializer is busy and cannot accept any more data, the ULPI

interface controller deasserts NXT.

The USB data deserializer decodes data received from the USB bus. When data is

received, the deserializer strips the SYNC and EOP patterns, and then performs

serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data

payload. The ULPI interface controller sends data to the USB link by asserting DIR, and

then asserting NXT whenever a byte is ready. The deserializer also detects various

receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and

byte-alignment errors.

8.3 Hi-Speed USB (USB 2.0) ATX

The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to

transmit, receive and terminate the USB bus in high speed, full speed and low speed, for

USB peripheral, host or OTG implementations. The following circuitry is included:

• Differential drivers to transmit data at high speed, full speed and low speed

• Differential and single-ended receivers to receive data at high speed, full speed and

low speed

• Squelch circuit to detect high-speed bus activity

ISP1705_1

Product data sheet

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ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

• High-speed disconnect detector

• 45 Ω high-speed bus terminations on pins DP and DM

• 1.5 kΩ pull-up resistor on pin DP

• 15 kΩ bus terminations on pins DP and DM

For details on controlling resistor settings, see Table 15.

8.4 Voltage regulator

The ISP1705 contains a built-in voltage regulator that conditions the V_CCsupply for use

inside the ISP1705. The voltage regulator:

• Supports input supply range 3.0 V < V_CC< 4.5 V.

• Can be supplied from a battery with the voltage range mentioned above.

• Supplies internal digital circuitry with 1.8 V and analog circuitry with 3.3 V or 2.7 V.

• In USB mode, automatically bypasses the internal 3.3 V regulator when V_CC< 3.5 V:

the internal analog circuitry directly draws power from the V_CCpin. In UART mode, the

bypass switch will be disabled.

• Will be shut down when V_CC(I/O)is not present or when chip select is deasserted.

8.5 Crystal oscillator and PLL

The ISP1705 has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock

generation. When a crystal is in use, the built-in crystal oscillator generates a square wave

clock for internal use. A square wave clock of the same frequency can also be driven

directly into the XTAL1 pin. Using an existing square wave clock can save the cost of a

crystal and also reduce the board space. The crystal or clock frequencies supported are

13 MHz, 19.2 MHz, 24 MHz and 26 MHz.

The PLL takes the square wave clock from the crystal oscillator and multiplies or divides it

into various frequencies for internal use.

The PLL produces the following frequencies, irrespective of the clock source:

• 1.5 MHz for low-speed USB data

• 12 MHz for full-speed USB data

• 60 MHz clock for the ULPI interface controller

• 480 MHz for high-speed USB data

• Other internal frequencies for data conversion and data recovery

8.6 UART buffer

The UART buffer includes circuits to support the transparent UART signaling between the

DATA0 or DATA1 pin and the DM or DP pin.

When the ISP1705 is put into UART mode, it acts as a voltage level shifter between the

following pins:

• From DATA0 (V_CC(I/O)level) to DM (2.7 V level) for the UART TXD signaling path.

• From DP (2.7 V level) to DATA1 (V_CC(I/O)level) for the UART RXD signaling path.

ISP1705_1

Product data sheet

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ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

8.7 OTG module

This module contains several sub-blocks that provide all the functionality required by the

USB OTG speciﬁcation. Speciﬁcally, it provides the following circuits:

• The ID detector to sense the ID pin of the micro-USB cable. The ID pin dictates which

device is initially conﬁgured as a host and which as a peripheral.

• V_BUScomparators to determine the V_BUSvoltage level. This is required for the V_BUS

detection, SRP and HNP.

• Resistors to temporarily charge and discharge V_BUS. This is required for SRP.

8.7.1 ID detector

The ID detector detects which end of the micro-USB cable is plugged in. The ID detector

must ﬁrst be enabled by setting the ID_PULLUP register bit to logic 1. If the ISP1705

senses a state of the ID pin that is different from the previously reported state, an RXCMD

status update will be sent to the USB link, or an interrupt will be asserted.

• If the micro-B end of the cable is plugged in (or nothing is plugged in), the ISP1705

will report that ID_GND is logic 1. The USB link must be in the B-device state.

• If the micro-A end of the cable is plugged in, the ISP1705 will report that ID_GND is

logic 0. The USB link must be in the A-device state.

The ID pin has a weak pull-up resistor (R_weakPU(ID)) permanently enabled to avoid the

ﬂoating condition.

8.7.2 V_BUScomparators

The ISP1705 provides three comparators to detect the V_BUSvoltage level. The

comparators are explained in the following subsections.

8.7.2.1 V_BUSvalid comparator

This comparator is used by hosts and A-devices to determine whether the voltage on

V_BUSis at a valid level for operation. The ISP1705 minimum threshold for the V_BUSvalid

comparator is 4.4 V. Any voltage on V_BUSbelow this threshold is considered invalid.

During power-up, it is expected that the comparator output will be ignored.

8.7.2.2 Session valid comparator

The session valid comparator is a TTL-level input that determines when V_BUSis high

enough for a session to start. Peripherals, A-devices and B-devices use this comparator to

detect when a session is started. The A-device also uses this comparator to determine

when a session is completed. The session valid threshold of the ISP1705 is between

0.8 V to 2.0 V.

8.7.2.3 Session end comparator

The session end comparator determines when V_BUSis below the B-device session end

threshold of 0.2 V to 0.8 V. The B-device uses this threshold to determine when a session

has ended.

ISP1705_1

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ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

8.7.3 SRP charge and discharge resistors

The ISP1705 provides on-chip resistors for short-term charging and discharging of V_BUS

.

These are used by the B-device to request a session, prompting the A-device to restore

the V_BUSvoltage. First, the B-device makes sure that V_BUSis fully discharged from the

previous session by setting the DISCHRG_VBUS register bit to logic 1 and waiting for

SESS_END to be logic 1. Then the B-device charges V_BUSby setting the CHRG_VBUS

register bit to logic 1. The A-device sees that V_BUSis charged above the session valid

threshold and starts a session by turning on the V_BUSvoltage.

8.8 Port power control

For an OTG or host application, the ISP1705 uses the PSW_N pin to control the external

power switch for the V_BUS5 V supply. The overcurrent detector output of the external

power switch can be connected to the FAULT pin of the ISP1705 to indicate to the ULPI

link the V_BUSovercurrent status. For the connection scheme, see Figure 4.

When the FAULT pin is not used, connect it to GND.

+5 V

POWER

SWITCH

WITH

FAULT

PSW_N

FAULT

V

BUS

INDICATOR

ISP1705

V

BUS

001aai189

Fig 4. Digital overcurrent detection scheme

8.9 Band gap reference voltage

The band gap circuit provides a stable internal voltage reference to bias the analog

circuitry. This band gap circuit requires an accurate external reference resistor. Connect a

12 kΩ ± 1 % resistor between the RREF pin and GND.

8.10 Power-On Reset (POR)

An internal POR pulse is generated when REG1V8 rises above V_POR(trip). The internal

POR pulse will be generated whenever REG1V8 drops below V_POR(trip)for more than

t_{w(REG1V8_L)}

.

To give a better view of the functionality, Figure 5 shows a possible curve of REG1V8. The

internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip

level so that a POR pulse is generated to reset all internal circuits. If REG1V8 dips from t2

to t3 for greater than t_{w(REG1V8_L)}, another POR pulse is generated. If the dip from t4 to t5

is less than t_{w(REG1V8_L)}, the internal POR pulse will not be generated and will remain

LOW.

ISP1705_1

Product data sheet

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ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

REG1V8

V

POR(trip)

t4

t3

t5

t0

t1

t2

POR

004aab023

Fig 5. Internal power-on reset timing

8.11 Power-up, reset and bus idle sequence

Figure 6 shows a typical start-up sequence.

On power-up, the ISP1705 performs an internal power-on reset and asserts DIR to

indicate to the link that the ULPI bus cannot be used. When the internal PLL is stable, the

ISP1705 deasserts DIR and drives a 60 MHz clock on the CLOCK pin. The power-up time

depends on the V_CCsupply rise time, the crystal start-up time, and the PLL start-up time

t_startup(PLL). When DIR is deasserted, the link must drive the data bus to a valid level. By

default, the link must drive data to LOW. Before beginning USB packets, the link must set

the RESET bit in the FUNC_CTRL register (see Section 11.5) to reset the ISP1705. After

the RESET bit is set, the ISP1705 will assert DIR until the internal reset completes. The

ISP1705 will automatically deassert DIR and clear the RESET bit when the reset has

completed. After every reset, an RXCMD is sent to the link to update USB status

information. After this sequence, the ULPI bus is ready for use and the link can start USB

operations.

If chip select is non-active, the ISP1705 will be kept in Power-down mode. In Power-down

mode, all ULPI interface pins will be put in 3-state, the internal regulator will be shut down,

and the total current consumption in Power-down mode will be less than that in low-power

mode.

The link can do a hardware reset to the ISP1705 by toggling chip select. The

recommended sequence is:

1. De-activate chip select.

2. Wait for at least t_PWRDN

3. Activate chip select.

.

If the low-power mode is entered when V_CC(I/O)is lost, see Table 9.

The recommended power-up sequence for the link is:

1. Apply the V_CCand V_CC(I/O)voltage.

2. Activate chip select.

3. The link waits for at least t_PWRUP, ignoring all the ULPI pin statuses.

4. The link may start to detect the DIR status level. If DIR is detected LOW, the link may

send a RESET command.

The ULPI interface is ready for use.

ISP1705_1

Product data sheet

Rev. 01 — 13 June 2008

13 of 89

ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

V

CC

V

CC(I/O)

CHIP_SEL_N

REG1V8

t

PWRUP

Internal

POR

XTAL1

bus idle

internal clocks stable

RESET command

t

+ t

d(det)clk(osc) startup(PLL)

CLOCK

(output)

DATA[7:0]

TXCMD

D

RXCMD

internal reset

update

DIR

STP

NXT

t1 t2

t3

t4

t5

t6

004aaa987

t1 = V_CCis applied to the ISP1705.

t2 = V_CC(I/O)is turned on. ULPI interface pins CLOCK, DATA[7:0], DIR and NXT are in 3-state as long as chip select is

non-active.

t3 = Chip select turns from non-active to active. The ISP1705 regulator starts to turn on. ULPI pads are not in 3-state and may

drive to either LOW or HIGH. It is recommended that the link ignores ULPI pins status during t_PWRUP

.

t4 = Power-on reset threshold is reached and the POR pulse is generated. After the POR pulse, ULPI pins are driven to a

deﬁned level. DIR is driven to HIGH and the other pins are driven to LOW.

t5 = The PLL is stabilized after t_{d(det)clk(osc)}+ t_startup(PLL). The CLOCK pin starts to output 60 MHz. The DIR pin will transition

from HIGH to LOW. The link must drive DATA[7:0] and STP to LOW as the idle state. The link will then issue a reset command

to initialize the ISP1705.

t6 = The power-up sequence is completed and the ULPI bus interface is ready for use.

Fig 6. Power-up and reset sequence required before the ULPI bus is ready for use

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8.11.1 Interface protection

By default, the ISP1705 enables a weak pull-up resistor on STP. If the STP pin is

unexpectedly HIGH at any time, the ISP1705 will protect the ULPI interface by enabling

weak pull-down resistors on DATA[7:0].

The interface protect feature prevents unwanted activity of the ISP1705 whenever the

ULPI interface is not correctly driven by the link. For example, when the link powers up

more slowly than the ISP1705.

The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.

8.11.2 Interface behavior with respect to RESET_N

The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), all logic in

the ISP1705 will be reset, including the analog circuitry and ULPI registers. During reset,

the link must drive DATA[7:0] and STP to LOW; otherwise undeﬁned behavior may result.

When RESET_N is deasserted (HIGH), 60 MHz clock will start. Figure 7 shows the ULPI

interface behavior when RESET_N is asserted (LOW), and subsequently deasserted

(HIGH). The behavior of Figure 7 applies only when chip select is asserted. If RESET_N

is not used, it must be connected to V_CC(I/O)

.

CLOCK

RESET_N

DATA[7:0]

Hi-Z (input)

Hi-Z (link must drive)

Hi-Z (input)

DIR

Hi-Z (input)

STP

NXT

004aab065

Fig 7. Interface behavior with respect to RESET_N

8.11.3 Interface behavior with respect to chip select

The use of chip select as a power-down control signal is optional. When chip select is

deasserted, the ISP1705 will 3-state ULPI pins and power-down the internal circuitry. If

chip select is not used as a power-down control signal, CHIP_SEL_N must be connected

to LOW. Figure 8 shows the ULPI interface behavior when chip select is asserted and

subsequently deasserted.

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t

PWRDN

Hi-Z (ignored)

CLOCK

CHIP_SEL_N

DATA[7:0]

DIR

Hi-Z (input)

Hi-Z (ignored)

Hi-Z

Hi-Z (ignored)

Hi-Z

Hi-Z (input)

STP

NXT

004aaa988

Fig 8. Interface behavior with respect to chip select

8.12 Detailed description of pins

8.12.1 DATA[7:0]

Bidirectional data bus pins. The USB link must drive DATA[7:0] to LOW when the ULPI bus

is idle. When the link has data to transmit to the PHY, it drives a nonzero value. Weak

pull-down resistors are incorporated into DATA[7:0] pins as part of the interface protect

feature. For details, see Section 8.11.1.

DATA[7:0] pins can also be 3-stated when chip select is deasserted.

These pins can be reconﬁgured to carry various data types when the chip is not in

synchronous mode. For details, see Section 9.2.

8.12.2 V_CC(I/O)

The input supply power pin that sets the I/O voltage level. A 0.1 µF decoupling capacitor is

recommended on each V_CC(I/O)pin. V_CC(I/O)powers the on-chip pads of the following pins:

• CFG1

• CFG2

• CHIP_SEL

• CHIP_SEL_N

• CLOCK

• DATA[7:0]

• DIR

• NXT

• STP

• RESET_N

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8.12.3 RREF

ULPI Hi-Speed USB transceiver

Resistor reference analog I/O pin. A 12 kΩ ± 1 % resistor must be connected between the

RREF pin and GND. This provides an accurate voltage reference that biases internal

analog circuitry. Less accurate resistors cannot be used. It will affect the biasing current

for analog circuits, thus the USB signal quality.

8.12.4 DP and DM

When the ISP1705 is in USB mode, the DP pin functions as the USB data plus line, and

the DM pin functions as the USB data minus line.

When the ISP1705 is in transparent UART mode, the DP pin functions as the UART RXD

input pin, and the DM pin functions as the UART TXD output pin.

The DP and DM pins must be connected to the D+ and D− pins of the USB receptacle.

8.12.5 CFG0

This input pin is used to select the SDR or DDR interface. For the SDR interface, connect

this pin to GND. For the DDR interface, connect this pin to REG3V3.

8.12.6 V_CC

Main input supply voltage for the ISP1705. The ISP1705 operates correctly when V_CCis

between 3.0 V and 4.5 V. A 0.1 µF decoupling capacitor is recommended.

8.12.7 ID

For OTG applications, the ID (identiﬁcation) pin is connected to the ID pin of the micro-AB

receptacle. As deﬁned in On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.3,

the ID pin dictates the initial role of the link. If ID is detected as HIGH, the link must

assume the role of a peripheral. If ID is detected as LOW, the link must assume a host

role. Roles can be swapped at a later time by using HNP.

The ISP1705 provides an internal pull-up resistor (R_UP(ID)) to sense the state of the ID pin.

The pull-up resistor must ﬁrst be enabled by setting the ID_PULLUP register bit to logic 1.

If the state of ID has changed, the ISP1705 will send an RXCMD or interrupt to the link. If

the link does not receive any RXCMD or interrupt by time t_ID, then the ID state has not

changed.

The ISP1705 also provides an internal weak pull-up resistor (R_weakPU(ID)). This weak

pull-up resistor is always enabled to avoid a possible ﬂoating condition on the ID pin.

8.12.8 FAULT

This pin is used to detect the V_BUSfault condition. If the function is not used, this pin must

be connected to ground to avoid ﬂoating input.

If an external V_BUSovercurrent or fault detection circuit is used, the output fault indicator of

that circuit can be connected to the FAULT input pin. The USE_EXT_VBUS_IND bit in the

OTG_CTRL register (see Section 11.7) and the IND_PASSTHRU bit in the INTF_CTRL

register (see Section 11.6) must be set to logic 1. The ISP1705 will inform the link of V_BUS

fault events by sending RXCMDs on the ULPI bus.

The FAULT input pin is mapped to the A_VBUS_VLD bit in RXCMD. Any changes to the

FAULT input will trigger RXCMD carrying the FAULT condition with A_VBUS_VLD.

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For details, see Section 10.3.2 and Section 10.3.3.

8.12.9 REG3V3 and REG1V8

These are output voltage pins from the internal regulator. These supplies are used

internally to power digital and analog circuits.

For proper operation of the regulator, pins REG3V3 and REG1V8 must each be

connected to a 0.1 µF capacitor in parallel with a 4.7 µF low ESR capacitor.

REG3V3 powers on-chip pads of the following pins:

• CFG0

• DM

• DP

• FAULT

• ID

• PSW_N

• RREF

8.12.10 V_BUS

This I/O pin acts as an input to V_BUScomparators, and also as a power supply pin for SRP

charge and discharge resistors. For details, see Figure 9.

The V_BUSpin requires a capacitive load. Table 4 provides the recommended capacitor

values for various applications.

Table 4.

Recommended V_BUScapacitor value

Application

OTG

V_BUScapacitor (C_VBUS

1 µF to 6.5 µF, 10 V

120 µF ± 20 %, 10 V

1 µF to 10 µF, 10 V

)

Standard host

Standard peripheral

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REG3V3

CHRG_VBUS

ISP1705

R

UP(VBUS)

V

BUS

comparators

V

BUS

R

DN(VBUS)

I(idle)(VBUS)

DISCHRG_

VBUS

004aab045

Fig 9. V_BUSpin internal pull-up and pull-down scheme

8.12.11 PSW_N

The PSW_N pin is an active-LOW open-drain output pin. It is used to control external

charge pumps or V_BUSpower switches to supply V_BUS. When in use, an external pull-up

resistor is required. This allows for per-port or ganged power control.

To enable the external power source by driving PSW_N to LOW, the link must set the

DRV_VBUS_EXT bit in the OTG_CTRL register (see Section 11.7) to logic 1.

Table 5 summarizes settings to drive 5 V on V_BUS

.

Table 5.

OTG_CTRL register power control bits

DRV_VBUS_EXT

Power source used

0

1

external 5 V V_BUSpower source disabled (PSW_N = HIGH)

external 5 V V_BUSpower source enabled (PSW_N = LOW)

8.12.12 XTAL1 and XTAL2

XTAL1 is the crystal oscillator input, and XTAL2 is the crystal oscillator output. The

allowed crystal or clock frequency on the XTAL1 pin is selectable by the CFG1 and CFG2

pins, as shown in Table 6.

Table 6.

Pin CFG1

LOW

Allowed crystal or clock frequency on the XTAL1 pin

Pin CFG2

LOW

Allowed crystal or clock frequency on the XTAL1 pin

19.2 MHz

26 MHz

24 MHz

13 MHz

LOW

HIGH

LOW

HIGH

When a clock is driven into XTAL1, XTAL2 must be left open.

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If a crystal is attached, it requires a capacitor on each terminal of the crystal to GND. The

recommended crystal speciﬁcation and required external capacitors are given in Table 7

and Table 8.

Table 7.

External capacitor values for 13 MHz or 19.2 MHz clock frequency

Load capacitance C_Lof the

crystal^[1]

Maximum series resistance R_Sof

the crystal^[1]

External capacitor

_XTALvalue

C

10 pF

20 pF

< 180 Ω

< 100 Ω

18 pF

39 pF

[1] Speciﬁed by the crystal manufacturer.

Table 8.

External capacitor values for 24 MHz or 26 MHz clock frequency

Load capacitance C_Lof the

crystal^[1]

Maximum series resistance R_Sof

the crystal^[1]

External capacitor

_XTALvalue

C

10 pF

20 pF

< 140 Ω

< 60 Ω

18 pF

39 pF

[1] Speciﬁed by the crystal manufacturer.

8.12.13 DIR

ULPI direction output pin. Synchronous to the rising edge of CLOCK. Controls the

direction of the data bus. By default, the ISP1705 holds DIR at LOW, causing the data bus

to be an input. When DIR is LOW, the ISP1705 listens for data from the link. The ISP1705

pulls DIR to HIGH only when it has data to send to the link, which is for one of two

reasons:

• To send data (USB receive or register reads) and RXCMD status updates to the link.

• To block the link from driving the data bus during power-up, reset and low power

(suspend) mode.

This pin can be 3-stated when chip select is deasserted.

8.12.14 RESET_N

An active-LOW asynchronous reset pin that resets all circuits in the ISP1705. The

ISP1705 contains an internal power-on reset circuit, and therefore using the RESET_N

pin is optional. If RESET_N is not used, it must be connected to V_CC(I/O)

.

For details on using RESET_N, see Section 8.11.2.

8.12.15 STP

ULPI stop input pin. Synchronous to the rising edge of CLOCK. The link must assert STP

to signal the end of a USB transmit packet or a register write operation. When DIR is

asserted, the link can optionally assert STP for one clock cycle to abort the ISP1705,

causing it to deassert DIR in the next clock cycle.

8.12.16 NXT

ULPI next data output pin. Synchronous to the rising edge of CLOCK. The ISP1705 holds

NXT at LOW, by default. When DIR is LOW and the link is sending data to the ISP1705,

NXT will be asserted to notify the link to provide the next data byte. When DIR is HIGH

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and the ISP1705 is sending data to the link, NXT will be asserted to notify the link that

another valid byte is on the bus. NXT is not used for register read data or the RXCMD

status update.

This pin can be 3-stated when chip select is deasserted.

8.12.17 CLOCK

A 60 MHz interface clock to synchronize the ULPI bus. All ULPI pins are synchronous to

the rising edge of CLOCK.

The ISP1705 provides two clocking options:

• A crystal is attached between the XTAL1 and XTAL2 pins.

• A clock is driven into the XTAL1 pin, with the XTAL2 pin left unconnected.

8.12.18 CFG1, CFG2

These input pins are used to select the crystal or clock frequency. For details, see Table 6.

8.12.19 CHIP_SEL, CHIP_SEL_N

When chip select is deasserted, ULPI pins DATA[7:0], CLOCK, DIR and NXT are 3-stated

and the STP input is ignored; internal circuits are powered-down as well.

When chip select is asserted, the ISP1705 will operate normally.

Both the CHIP_SEL and CHIP_SEL_N pins must be asserted for the chip select to

function. If any of the two is deasserted, the chip will enter Power-down mode.

8.12.20 GND

Global ground signal. To ensure the correct operation of the ISP1705, GND must be

soldered to the cleanest available ground.

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9. Modes of operation

9.1 Power modes

When both V_CC(I/O)and V_CCare not powered, there will be no leakage from the V_BUSpin

to all the remaining pins, including V_CCand V_CC(I/O). Applying V_BUSwithin the normal

range will not damage the ISP1705 chip.

When both V_CCand V_CC(I/O)are powered and are within the operating voltage range, the

ISP1705 will be fully functional as in normal mode.

When V_CC(I/O)is powered and the V_CCvoltage is below the operating range of the

ISP1705, the application system must detect the low voltage condition and set chip select

to deassert (that is, put the ISP1705 in Power-down mode). This is to protect the ULPI and

USB interfaces from driving wrong levels. Under this condition, the V_CC(I/O)voltage will not

leak to USB pins (V_BUS, DP, DM and ID) and the V_CCpin. All the digital pins (see

Section 8.12.2) powered by V_CC(I/O)are conﬁgured as high-impedance inputs. These pins

must be driven to a deﬁned state or terminated by using pull-up or pull-down resistors to

avoid a ﬂoating input condition. Other pins (see Section 8.12.9) are not powered.

9.1.1 Normal mode

In normal mode, both V_CCand V_CC(I/O)are powered. Chip select is asserted. The ISP1705

is fully functional.

9.1.2 Power-down mode

When V_CC(I/O)is not present or when chip select is deasserted, the ISP1705 is put into

Power-down mode. In this mode, internal regulators are powered down to keep the V_CC

current to a minimum. The voltage on the V_CCpin will not leak to the V_CC(I/O)and/or V_BUS

pins. In this mode, the ISP1705 pin states are given in Table 9.

Table 9.

Pin states in Power-down mode

Pin name^[1]

Pin state when

_CC(I/O)is not

present

Pin state when V_CC(I/O)is

present and chip select

is not active

V

V_CC

3.0 V to 4.5 V

not powered^[2]

3.0 V to 4.5 V

3.0 V to 3.6 V

HIGH

V_CC(I/O)

CHIP_SEL, CHIP_SEL_N

CFG1, CFG2, RESET_N, CLOCK, STP, NXT,

DIR, DATA[7:0]

3.0 V to 3.3 V

CFG0, DP, DM, V_BUS, ID, REG1V8, REG3V3,

XTAL1, XTAL2, RREF, PSW_N, FAULT

not powered^[2]

[1] When I/O pins are not powered, the input buffer is disabled and will ignore the external input level. The input

pins, however, should not be driven by another voltage source to prevent leakage.

[2] These pins must not be externally driven to HIGH. Otherwise, the ISP1705 behavior is undeﬁned and

leakage current will occur.

When V_CC(I/O)is not present, all the digital pins (see Section 8.12.2) that are powered by

V_CC(I/O)are not powered. Other pins (see Section 8.12.9) are also not powered.

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When the ISP1705 is put into Power-down mode by disabling chip select, all the digital

pins (see Section 8.12.2) that are powered by V_CC(I/O)are conﬁgured as high-impedance

inputs. These pins must be driven to deﬁned states or terminated by using pull-up or

pull-down resistors to avoid a ﬂoating input condition. Other pins (see Section 8.12.9) are

not powered. In this mode, minimum current will be drawn by V_CC(I/O)to detect the chip

select status.

9.2 ULPI modes

The ISP1705 ULPI interface can be programmed to operate in ﬁve modes. In each mode,

the signals on the data bus are reconﬁgured as described in the following subsections.

Setting more than one mode will lead to undeﬁned behavior.

9.2.1 Synchronous mode

This is default mode. On power-up, and when CLOCK is stable, the ISP1705 will enter

synchronous mode.

In synchronous mode, the link must synchronize all ULPI signals to CLOCK, meeting the

set-up and hold times as deﬁned in Section 15.

This mode is used by the link to perform the following tasks:

• High-speed detection handshake (chirp)

• Transmit and receive USB packets

• Read from and write to registers

• Receive USB status updates (RXCMDs) from the ISP1705

For more information on various synchronous mode protocols, see Section 10.

Table 10. ULPI signal description

Signal name Direction on

the ISP1705^[1]

Signal description

CLOCK

O

60 MHz interface clock: When a crystal is attached or a clock is driven into the XTAL1

pin, the ISP1705 will drive a 60 MHz output clock.

During low-power, serial and UART modes, the clock can be turned off to save power.

DATA[7:0]

I/O

8-bit data bus: In synchronous mode, the link drives DATA[7:0] to LOW by default. The

link initiates transfers by sending a nonzero data pattern called a TXCMD (transmit

command). In synchronous mode, the direction of DATA[7:0] is controlled by DIR.

Contents of DATA[7:0] lines must be ignored for exactly one clock cycle whenever DIR

changes state. This is called a turnaround cycle.

Data lines have ﬁxed directions and different meanings in low-power, 3-pin serial and

UART modes.

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Table 10. ULPI signal description …continued

Signal name Direction on

the ISP1705^[1]

Signal description

DIR

O

Direction: Controls the direction of data bus DATA[7:0].

In synchronous mode, the ISP1705 drives DIR to LOW by default, making the data bus an

input so the ISP1705 can listen for TXCMD from the link. The ISP1705 drives DIR to

HIGH only when it has data for the link. When DIR and NXT are HIGH, the byte on the

data bus contains decoded USB data. When DIR is HIGH and NXT is LOW, the byte

contains status information called an RXCMD (receive command). The only exception to

this rule is when the PHY returns register read data, where NXT is also LOW, replacing

the usual RXCMD byte. Every change in DIR causes a turnaround cycle on the data bus,

during which DATA[7:0] is not valid and must be ignored by the link.

DIR is always asserted during low-power, serial and UART modes.

STP

NXT

I

Stop: In synchronous mode, the link drives STP to HIGH for one cycle after the last byte

of data is sent to the ISP1705. The link can optionally assert STP to force DIR to be

deasserted.

In low-power, serial and UART modes, the link holds STP at HIGH to wake up the

ISP1705, causing the ULPI bus to return to synchronous mode.

O

Next: In synchronous mode, the ISP1705 drives NXT to HIGH to throttle data. If DIR is

LOW, the ISP1705 asserts NXT to notify the link to place the next data byte on DATA[7:0]

in the following clock cycle. If DIR is HIGH, the ISP1705 asserts NXT to notify the link that

a valid USB data byte is on DATA[7:0] in the current cycle. The ISP1705 always drives an

RXCMD when DIR is HIGH and NXT is LOW, unless register read data is to be returned

to the link in the current cycle.

NXT is not used in low-power, serial and UART modes.

[1] I = input; O = output.

9.2.2 Low-power mode

When the USB bus is idle, the link can place the ISP1705 into low-power mode (also

called suspend mode). In low-power mode, the data bus deﬁnition changes to that shown

in Table 11. To enter low-power mode, the link sets the SUSPENDM bit in the

FUNC_CTRL register (see Section 11.5) to logic 0. To exit low-power mode, the link

asserts the STP signal. After exiting low-power mode, the ISP1705 will send an RXCMD

to the link if a change was detected in any interrupt source, and the change still exists. An

RXCMD may not be sent if the interrupt condition is removed before exiting.

The ISP1705 will draw only suspend current from the V_CCsupply; see Table 53.

During low-power mode, the clock on XTAL1 may be stopped. The clock must be started

again before asserting STP to exit low-power mode.

For more information on low-power mode enter and exit protocols, refer to UTMI+ Low Pin

Interface (ULPI) Speciﬁcation Rev. 1.1.

Table 11. Signal mapping during low-power mode

Signal

Maps to

Direction^[1]Description

LINESTATE0

DATA0

O

combinatorial LINESTATE0 directly driven by

the analog receiver

LINESTATE1

DATA1

O

combinatorial LINESTATE1 directly driven by

the analog receiver

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Table 11. Signal mapping during low-power mode …continued

Signal

Maps to

Direction^[1]Description

Reserved

DATA2

O

reserved; the ISP1705 will drive this pin to

LOW

INT

DATA3

O

active-HIGH interrupt indication; will be

asserted and latched whenever any

unmasked interrupt occurs

Reserved

DATA[7:4]

O

reserved; the ISP1705 will drive these pins to

LOW

[1] I = input; O = output.

9.2.3 6-pin full-speed or low-speed serial mode

If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed

USB data, it can set the ISP1705 to 6-pin serial mode. In 6-pin serial mode, the data bus

deﬁnition changes to that shown in Table 12. To enter 6-pin serial mode, the link sets the

6PIN_FSLS_SERIAL bit in the INTF_CTRL register (see Section 11.6) to logic 1. To exit

6-pin serial mode, the link asserts the STP signal. This is provided primarily for links that

contain legacy full-speed or low-speed functionality, providing a more cost-effective

upgrade path to high-speed functionality. An interrupt pin is also provided to inform the link

of USB events. If the link requires CLOCK to be running during 6-pin serial mode, the

CLOCK_SUSPENDM register bit must be set to logic 1 before entering 6-pin serial mode.

For more information on 6-pin serial mode enter and exit protocols, refer to UTMI+ Low

Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

Table 12. Signal mapping for 6-pin serial mode

Signal

Maps to

Direction^[1]Description

TX_ENABLE DATA0

I

active-HIGH transmit enable

TX_DAT

TX_SE0

INT

DATA1

DATA2

DATA3

I

transmit differential data on DP and DM

transmit single-ended zero on DP and DM

I

O

active-HIGH interrupt indication; will be asserted and

latched whenever any unmasked interrupt occurs

RX_DP

DATA4

DATA5

DATA6

DATA7

O

single-ended receive data from DP

RX_DM

RX_RCV

Reserved

single-ended receive data from DM

differential receive data from DP and DM

reserved; the ISP1705 will drive this pin to LOW

[1] I = input; O = output.

9.2.4 3-pin full-speed or low-speed serial mode

If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed

USB data, it can set the ISP1705 to 3-pin serial mode. In 3-pin serial mode, the data bus

deﬁnition changes to that shown in Table 13. To enter 3-pin serial mode, the link sets the

3PIN_FSLS_SERIAL bit in the INTF_CTRL register (see Section 11.6) to logic 1. To exit

3-pin serial mode, the link asserts the STP signal. This is provided primarily for links that

contain legacy full-speed or low-speed functionality, providing a more cost-effective

upgrade path to high-speed functionality. An interrupt pin is also provided to inform the link

of USB events. If the link requires CLOCK to be running during 3-pin serial mode, the

CLOCK_SUSPENDM register bit must be set to logic 1 before entering 3-pin serial mode.

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For more information on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low

Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

Table 13. Signal mapping for 3-pin serial mode

Signal

Maps to

Direction^[1]Description

TX_ENABLE DATA0

I

active-HIGH transmit enable

DAT

SE0

DATA1

DATA2

I/O

transmit differential data on DP and DM when

TX_ENABLE is HIGH

receive differential data from DP and DM when

TX_ENABLE is LOW

I/O

transmit single-ended zero on DP and DM when

TX_ENABLE is HIGH

receive single-ended zero from DP and DM when

TX_ENABLE is LOW

INT

DATA3

O

active-HIGH interrupt indication; will be asserted

and latched whenever any unmasked interrupt

occurs

Reserved

DATA[7:4]

reserved; the ISP1705 will drive these pins to LOW

[1] I = input; O = output.

9.2.5 Transparent UART mode

In transparent UART mode, the ISP1705 functions as a voltage level shifter between

following pins:

• From pin DATA0 (V_CC(I/O)level) to pin DM (2.7 V level).

• From pin DP (2.7 V level) to pin DATA1 (V_CC(I/O)level).

The USB transceiver is used to drive the UART transmitting signal on the DM line. The

rise time and the fall time of the transmitting signal is determined by whether a full-speed

or low-speed transceiver is in use. It is recommended to use a low-speed transceiver if the

UART bit rate is below 921 kbit/s for better EMI performance. If the UART bit rate is equal

to or above 921 kbit/s, a full-speed transceiver can be used.

In transparent UART mode, data bus deﬁnitions change to that shown in Table 14.

Table 14. UART signal mapping

Signal

TXD

Maps to

DATA0

DATA1

Direction^[1]Description

I

UART TXD signal that is routed to the DM pin

RXD

O

UART RXD signal that is routed from the DP pin

Reserved DATA2

reserved; the ISP1705 will drive this pin to LOW in UART

mode

INT DATA3

O

active-HIGH interrupt indication; will be asserted and

latched whenever any unmasked interrupt occurs

Reserved DATA[7:4]

[1] I = input; O = output.

reserved; the ISP1705 will drive these pins to LOW in

UART mode

Transparent UART mode is entered by setting some register bits in ULPI registers. The

recommended sequence is:

ISP1705_1

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1. Set the XCVRSELECT[1:0] bits in the FUNC_CTRL register (see Section 11.5) to 10b

(low speed) or 01b (full speed). This setting affects the rise time and the fall time of

the UART transmitting signal on the DM line.

2. Set the DP_PULLDOWN and DM_PULLDOWN bits in the OTG_CTRL register (see

Section 11.7) to logic 0.

3. Set the TERMSELECT bit in the FUNC_CTRL register (see Section 11.5) to logic 0

(power-on default value).

Remark: Mandatory when a full-speed driver is used and optional for a low-speed

driver.

4. Set the TXD_EN and RXD_EN bits in the CARKIT_CTRL register (see Section 11.14)

to logic 1. These two bits must be set together in one TXCMD.

5. Set the CARKIT_MODE bit in the INTF_CTRL register (see Section 11.6) to logic 1.

Remark: The CARKIT_MODE, TXD_EN and RXD_EN bits must be set to logic 1.

The sequence of setting these register bits is ignored.

After the register conﬁguration is complete:

1. A weak pull-up resistor will be enabled on the DP and DATA0 pins. This is to avoid the

possible ﬂoating condition on these input pins when UART mode is enabled.

2. The 39 Ω serial termination resistors on the DP and DM pins will be enabled.

3. One clock cycle after DIR goes from LOW to HIGH, the ISP1705 will drive the data

bus for ﬁve clock cycles. This is to charge the DATA0 pin to a HIGH level for a slow

link. However, the link can start driving DATA0 to HIGH immediately after the

turnaround cycle.

4. UART buffers between DATA0 or DATA1 and DM or DP are enabled. Transparent

UART mode is entered.

Remark: The DP pin will be slowly charged up to HIGH by the weak pull-up resistor.

The time needed depends on the capacitive loading on DP.

By default, the clock is powered down when the ISP1705 enters UART mode. If the link

requires CLOCK to be running in UART mode, it can set the CLOCK_SUSPENDM bit in

the INTF_CTRL register (see Section 11.6) to logic 1 before entering UART mode.

Transparent UART mode is exited by asserting the STP pin to HIGH or by toggling chip

select.

The INT pin (DATA3) is asserted and latched whenever an unmasked interrupt event

occurs. When the link detects INT as HIGH, it must wake up the PHY from transparent

UART mode by asserting STP. When the PHY is in synchronous mode, the link can read

the USB_INTR_L register (see Section 11.11) to determine the source of the interrupt.

Note that the ISP1705 does not implement the optional Carkit Interrupt registers.

An alternative way to exit UART mode is to set chip select to non-active for more than

t_PWRDNand then set it to active. A power-on reset will be generated and the ULPI bus will

be put in default synchronous mode.

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(1)

(2)

CLOCK

turnaround

TXCMD

(REGW)

DATA[7:0]

0001 0001

UART mode signals

DATA

DIR

STP

NXT

UART

mode

004aaa865

(1) Clock remains powered when the CLOCK_SUSPENDM register bit is set to logic 1.

(2) Clock is powered down when the CLOCK_SUSPENDM register bit is logic 0 (default).

Fig 10. Interface behavior when entering UART mode

(1)

CLOCK

(2)

CLOCK

turnaround

synchronous

mode signals

UART mode signals

0000 0000

DATA[7:0]

DIR

STP

NXT

UART

mode

004aaa867

(1) Clock remains powered when the CLOCK_SUSPENDM register bit is set to logic 1.

(2) Clock is powered down when the CLOCK_SUSPENDM register bit is logic 0 (default).

Fig 11. Interface behavior when exiting UART mode

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9.3 USB state transitions

A Hi-Speed USB peripheral, host or OTG device handles more than one electrical state as

deﬁned in Universal Serial Bus Speciﬁcation Rev. 2.0 and On-The-Go Supplement to the

USB 2.0 Speciﬁcation Rev. 1.3. The ISP1705 accommodates various states through

register settings of the XCVRSELECT[1:0], TERMSELECT, OPMODE[1:0],

DP_PULLDOWN and DM_PULLDOWN bits.

Table 15 summarizes operating states. The values of register settings in Table 15 will

force resistor settings as also given in Table 15. Resistor setting signals are deﬁned as

follows:

• RPU_DP_EN enables the 1.5 kΩ pull-up resistor on DP

• RPD_DP_EN enables the 15 kΩ pull-down resistor on DP

• RPD_DM_EN enables the 15 kΩ pull-down resistor on DM

• HSTERM_EN enables the 45 Ω termination resistors on DP and DM

It is up to the link to set the desired register settings.

Table 15. Operating states and their corresponding resistor settings

Signaling mode

Register settings

Internal resistor settings

XCVR

SELECT

[1:0]

TERM

SELECT [1:0]

OPMODE

DP_

PULL PULL

DOWN DOWN

DM_

RPU_

DP_EN

RPD_

DP_EN

RPD_

DM_EN EN

HSTERM_

General settings

3-state drivers

XXb

01b

Xb

0b

01b

00b

Xb

1b

Xb

1b

0b

1b

0b

1b

0b

Power up or

V_BUS< V_{B_SESS_END}

Host settings

Host chirp

00b

X1b

01b

0b

1b

10b

00b

1b

0b

1b

0b

Host high-speed

Host full-speed

Host high-speed or

full-speed suspend

Host high-speed or

full-speed resume

01b

1b

10b

1b

0b

1b

0b

Host low-speed

10b

1b

00b

1b

0b

1b

0b

Host low-speed

suspend

Host low-speed

resume

10b

1b

0b

10b

1b

0b

1b

0b

1b

Host Test J or Test K 00b

Peripheral settings

Peripheral chirp

00b

1b

0b

10b

00b

0b

1b

0b

1b

Peripheral high

speed

Peripheral full speed 01b

1b

00b

0b

1b

0b

ISP1705_1

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Table 15. Operating states and their corresponding resistor settings …continued

Signaling mode

Register settings

Internal resistor settings

XCVR

SELECT

[1:0]

TERM

SELECT [1:0]

OPMODE

DP_

PULL PULL

DOWN DOWN

DM_

RPU_

DP_EN

RPD_

DP_EN

RPD_

DM_EN EN

HSTERM_

Peripheral high

speed or full speed

suspend

01b

1b

0b

00b

10b

0b

1b

0b

1b

Peripheral high

speed or full speed

resume

01b

Peripheral Test J or 00b

Test K

OTG settings

OTG device

peripheral chirp

00b

1b

0b

10b

00b

0b

1b

0b

1b

0b

1b

OTG device

peripheral high

speed

OTG device

peripheral full speed

01b

1b

00b

0b

1b

0b

1b

0b

OTG device

peripheral high

speed and full speed

suspend

OTG device

01b

00b

1b

0b

10b

0b

1b

0b

1b

0b

1b

peripheral high

speed and full speed

resume

OTG device

peripheral Test J or

Test K

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10. Protocol description

10.1 ULPI references

The ISP1705 provides a 12-pin ULPI interface to communicate with the link. It is highly

recommended that users of the ISP1705 read UTMI+ Speciﬁcation Rev. 1.0 and UTMI+

Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

Commands between the ISP1705 and the link are described in the following subsections.

10.2 TXCMD

By default, the link must drive the ULPI bus to its idle state of 00h. To send commands and

USB packets, the link drives a nonzero value on DATA[7:0] to the ISP1705 by sending a

byte called TXCMD. Commands include USB packet transmissions, and register reads

and writes. Once the TXCMD is interpreted and accepted by the ISP1705, the NXT signal

is asserted and the link can follow up with the required number of data bytes. The TXCMD

byte format is given in Table 16. Any values other than those in Table 16 are illegal and will

result in undeﬁned behavior.

Various TXCMD packet and register sequences are given in later sections.

Table 16. TXCMD byte format

Command Command Command

type name code payload

DATA[7:6] DATA[5:0]

Command Command description

name

Idle

00b

00 0000b

NOOP

NOPID

No operation. 00h is the idle value of the

data bus. The link must drive NOOP by

default.

Packet

transmit

01b

00 0000b

Transmit USB data that does not have a

PID, such as chirp and resume signaling.

The ISP1705 starts transmitting only

after accepting the next data byte.

00 XXXXb

10 1111b

PID

Transmit USB packet. DATA[3:0]

indicates USB packet identiﬁer PID[3:0].

Register

write

10b

11b

EXTW

Extended register write command

(optional). The 8-bit address must be

provided after the command is accepted.

XX XXXXb

10 1111b

REGW

EXTR

Register write command with 6-bit

immediate address.

Register

read

Extended register read command

(optional). The 8-bit address must be

provided after the command is accepted.

XX XXXXb

REGR

Register read command with 6-bit

immediate address.

10.3 RXCMD

The ISP1705 communicates status information to the link by asserting DIR and sending

an RXCMD byte on the data bus. The RXCMD data byte format follows UTMI+ Low Pin

Interface (ULPI) Speciﬁcation Rev. 1.1 and is given in Table 17.

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The ISP1705 will automatically send an RXCMD whenever there is a change in any of the

RXCMD data ﬁelds. The link must be able to accept an RXCMD at any time; including

single RXCMDs, back-to-back RXCMDs, and RXCMDs at any time during USB receive

packets when NXT is LOW. An example is shown in Figure 12. For details and diagrams,

refer to UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

Table 17. RXCMD byte format

DATA

Name

Description and value

1 to 0

LINESTATE LINESTATE signals: For a deﬁnition of LINESTATE, see Section 10.3.1.

DATA0 — LINESTATE0

DATA1 — LINESTATE1

3 to 2

V_BUSstate

Encoded V_BUSvoltage state: For an explanation of the V_BUSstate,

see Section 10.3.2.

5 to 4

RxEvent

ID

Encoded USB event signals: For an explanation of RxEvent,

see Section 10.3.4.

6

7

Reﬂects the state of the ID pin. Valid 50 ms after ID_PULLUP is set to

logic 1.

ALT_INT

By default, this signal is not used and is not needed in typical designs.

Optionally, the link can enable the BVALID_RISE and/or BVALID_FALL

bits in the PWR_CTRL register (see Section 11.15). Corresponding

changes in BVALID will cause an RXCMD to be sent to the link with the

ALT_INT bit asserted.

CLOCK

Single RXCMD

turnaround

Back-to-back RXCMDs

RXCMD RXCMD

turnaround

RXCMD

[

]

DATA 7:0

DIR

STP

NXT

004aaa695

Fig 12. Single and back-to-back RXCMDs from the ISP1705 to the link

10.3.1 Linestate encoding

LINESTATE[1:0] reﬂects the current state of DP and DM. Whenever the ISP1705 detects

a change in DP or DM, an RXCMD will be sent to the link with the new LINESTATE[1:0]

value. The value given on LINESTATE[1:0] depends on the setting of various registers.

Table 18 shows the LINESTATE[1:0] encoding for upstream facing ports, which applies to

peripherals. Table 19 shows the LINESTATE[1:0] encoding for downstream facing ports,

which applies to host controllers. Dual-role devices must choose the correct table,

depending on whether it is in peripheral or host mode.

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Table 18. LINESTATE[1:0] encoding for upstream facing ports: peripheral

DP_PULLDOWN = 0.^[1]

Mode

Value

Full speed

01, 11

1

High speed

00

Chirp

00

XCVRSELECT[1:0]

TERMSELECT

LINESTATE[1:0]

0

1

00

01

SE0

squelch

!squelch

squelch

FS-J

!squelch and

HS_Differential_Receiver_Output

10

11

FS-K

SE1

invalid

!squelch and

!HS_Differential_Receiver_Output

invalid

[1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive

HS_Differential_Receiver_Output.

Table 19. LINESTATE[1:0] encoding for downstream facing ports: host

DP_PULLDOWN and DM_PULLDOWN = 1.^[1]

Mode

Value Low

Full

High speed Chirp

speed speed

XCVRSELECT[1:0]

TERMSELECT

OPMODE[1:0]

10

01, 11 00

00

0

1

0

X

00, 01 or 11 10

LINESTATE[1:0]

00

01

SE0

LS-K

SE0

FS-J

squelch

!squelch

squelch

!squelch and

HS_Differential_Receiver_Output

10

11

LS-J

SE1

FS-K

SE1

invalid

!squelch and

!HS_Differential_Receiver_Output

invalid

[1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive

HS_Differential_Receiver_Output.

10.3.2 V_BUSstate encoding

USB devices must monitor the V_BUSvoltage for purposes such as overcurrent detection,

starting a session and SRP. The V_BUSstate ﬁeld in the RXCMD is an encoding of the

voltage level on V_BUS

.

The SESS_END and SESS_VLD indicators in the V_BUSstate are directly taken from the

internal comparators built-in to the ISP1705, and encoded as shown in Table 17 and

Table 20.

Table 20. Encoded V_BUSvoltage state

Value V_BUSvoltage

SESS_END SESS_VLD A_VBUS_VLD

00

01

10

11

V_BUS< V_{B_SESS_END}

1

0

X

0

1

X

0

1

V_{B_SESS_END}≤ V_BUS< V_{A_SESS_VLD}

V_{A_SESS_VLD}≤ V_BUS< V_{A_VBUS_VLD}

V_BUS≥ V_{A_VBUS_VLD}

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The A_VBUS_VLD indicator in the V_BUSstate provides several options and must be

conﬁgured based on current draw requirements. A_VBUS_VLD can input from one or

more V_BUSvoltage indicators, as shown in Figure 13.

A description on how to use and select the V_BUSstate encoding is given in Section 10.3.3.

A_VBUS_VLD comparator

internal A_VBUS_VLD

V

BUS

(0, X)

(1, 0)

RXCMD

A_VBUS_VLD

complement

output

FAULT indicator

FAULT

(1, 1)

IND_COMPL

USE_EXT_VBUS_IND,

IND_PASSTHRU

004aaa698

Fig 13. RXCMD A_VBUS_VLD indicator source

10.3.3 Using and selecting the V_BUSstate encoding

The V_BUSstate encoding is shown in Table 20. The ISP1705 will send an RXCMD to the

link whenever there is a change in the V_BUSstate. To receive V_BUSstate updates, the link

must ﬁrst enable the corresponding interrupts in the USB_INTR_EN_R and

USB_INTR_EN_F registers.

The link can use the V_BUSstate to monitor V_BUSand take appropriate actions. Table 21

shows the recommended usage for typical applications.

Table 21. V_BUSindicators in RXCMD required for typical applications

Application

A_VBUS_VLD

SESS_VLD

SESS_END

Standard host

Standard peripheral

OTG A-device

OTG B-device

yes

no

yes

no

10.3.3.1 Standard USB host controllers

For standard hosts, the system must be able to provide 500 mA on V_BUSin the range of

4.75 V to 5.25 V. An external circuit must be used to detect overcurrent conditions. If the

external overcurrent detector provides a digital fault signal, then the fault signal must be

connected to the ISP1705 FAULT input pin, and the link must do the following:

1. Set the IND_COMPL bit in the INTF_CTRL register (see Section 11.6) to logic 0 or

logic 1, depending on the polarity of the external fault signal.

2. Set the USE_EXT_VBUS_IND bit in the OTG_CTRL register (see Section 11.7) to

logic 1.

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3. If it is not necessary to qualify the fault indicator with the internal A_VBUS_VLD

comparator, set the IND_PASSTHRU bit in the INTF_CTRL register (see

Section 11.6) to logic 1.

10.3.3.2 Standard USB peripheral controllers

Standard peripherals must be able to detect when V_BUSis at a sufﬁcient level for

operation. SESS_VLD must be enabled to detect the start and end of USB peripheral

operations. Detection of A_VBUS_VLD and SESS_END thresholds is not needed for

standard peripherals.

10.3.3.3 OTG devices

When an OTG device is conﬁgured as an OTG A-device, it must be able to provide a

minimum of 8 mA on V_BUS. If the OTG A-device provides less than 100 mA, then there is

no need for an overcurrent detection circuit because the internal A_VBUS_VLD

comparator is sufﬁcient. If the OTG A-device provides more than 100 mA on V_BUS, an

overcurrent detector must be used and Section 10.3.3.1 applies. The OTG A-device also

uses SESS_VLD to detect when an OTG B-device is initiating V_BUSpulsing SRP.

When an OTG device is conﬁgured as an OTG B-device, SESS_VLD must be used to

detect when V_BUSis at a sufﬁcient level for operation. SESS_END must be used to detect

when V_BUShas dropped to a LOW level, allowing the B-device to safely initiate V_BUS

pulsing SRP.

10.3.4 RxEvent encoding

The RxEvent ﬁeld (see Table 22) of the RXCMD informs the link of information related

packets received on the USB bus. RxActive and RxError are deﬁned in USB 2.0

Transceiver Macrocell Interface (UTMI) Speciﬁcation Ver. 1.05. HostDisconnect is deﬁned

in UTMI+ Speciﬁcation Rev. 1.0. A short deﬁnition is also given in the following

subsections.

Table 22. Encoded USB event signals

Value

00

RxActive

RxError

HostDisconnect

0

1

X

0

1

X

0

1

01

11

10

10.3.4.1 RxActive

When the ISP1705 has detected a SYNC pattern on the USB bus, it signals an RxActive

event to the link. An RxActive event can be communicated using two methods. The ﬁrst

method is for the ISP1705 to simultaneously assert DIR and NXT. The second method is

for the ISP1705 to send an RXCMD to the link with the RxActive ﬁeld in the RxEvent bits

set to logic 1. The link must be capable of detecting both methods. RxActive frames the

receive packet from the ﬁrst byte to the last byte.

The link must assume that RxActive is set to logic 0 when indicated in an RXCMD or when

DIR is deasserted, whichever occurs ﬁrst.

The link uses RxActive to time high-speed packets and ensure that bus turnaround times

are met. For more information on the USB packet timing, see Section 10.6.1.

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10.3.4.2 RxError

When the ISP1705 has detected an error while receiving a USB packet, it deasserts NXT

and sends an RXCMD with the RxError ﬁeld set to logic 1. The received packet is no

longer valid and must be dropped by the link.

10.3.4.3 HostDisconnect

HostDisconnect is encoded into the RxEvent ﬁeld of the RXCMD. HostDisconnect is valid

only when the ISP1705 is conﬁgured as a host (both DP_PULLDOWN and

DM_PULLDOWN are set to logic 1), and indicates to the host controller when a peripheral

is connected (0b) or disconnected (1b). The host controller must enable HostDisconnect

by setting the HOST_DISCON_R and HOST_DISCON_F bits in the USB_INTR_EN_R

and USB_INTR_EN_F registers, respectively. Changes in HostDisconnect will cause the

PHY to send an RXCMD to the link with the updated value.

10.4 Register read and write operations

Figure 14 shows register read and write sequences. The ISP1705 supports immediate

addressing and extended addressing register operations. Extended register addressing is

optional for links. Note that register operations will be aborted if the ISP1705 asserts DIR

during the operation. When a register operation is aborted, the link must retry until

successful. For more information on register operations, refer to UTMI+ Low Pin Interface

(ULPI) Speciﬁcation Rev. 1.1.

CLOCK

TXCMD

(REGW) D

TXCMD

(REGR)

TXCMD

(EXTW) AD

TXCMD

(EXTW) AD

D

DATA[7:0]

immediate

register write

extended

register write

immediate

register read

extended

register read

DIR

STP

NXT

004aaa710

AD indicates the address byte, and D indicates the data byte.

Fig 14. Example of register write, register read, extended register write and extended register read

10.5 USB reset and high-speed detection handshake (chirp)

Figure 15 shows the sequence of events for USB reset and high-speed detection

handshake (chirp). The sequence is shown for hosts and peripherals. Figure 15 does not

show all RXCMD updates, and timing is not to scale. The sequence is as follows:

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1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and

as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow

the remainder of this protocol. If a host detects a full-speed peripheral, it resets the

peripheral by writing to the FUNC_CTRL register (see Section 11.5) and setting

XCVRSELECT[1:0] = 00b (high speed) and TERMSELECT = 0b that drives SE0 on

the bus (DP and DM connected to ground through 45 Ω). The host also sets

OPMODE[1:0] = 10b for correct chirp transmit and receive. The start of SE0 is labeled

t0.

Remark: To receive chirp signaling, the host must also consider the high-speed

differential receiver output. The host controller must interpret LINESTATE as shown in

Table 19.

2. High-speed detection handshake (chirp)

a. Peripheral chirp: After detecting SE0 for no less than 2.5 µs, if the peripheral is

capable of high speed, it sets XCVRSELECT[1:0] to 00b (high speed) and

OPMODE[1:0] to 10b (chirp). The peripheral immediately follows this with a

TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more

than 7 ms after reset time t0. If the peripheral is in low-power mode, it must wake

up its clock within 5.6 ms, leaving 200 µs for the link to start transmitting the

Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock).

b. Host chirp: If the host does not detect the peripheral chirp, it must continue

asserting SE0 until the end of reset. If the host detects the peripheral Chirp K for

no less than 2.5 µs, then no more than 100 µs after the bus leaves the Chirp K

state, the host sends a TXCMD (NOPID) with an alternating sequence of Chirp Ks

and Js. Each Chirp K or Chirp J must last no less than 40 µs and no longer than

60 µs.

c. High speed idle: The peripheral must detect a minimum of Chirp K-J-K-J-K-J. Each

Chirp K and Chirp J must be detected for at least 2.5 µs. The peripheral sets

TERMSELECT = 0b and OPMODE[1:0] = 00b after seeing the minimum chirp

sequence. The peripheral is now in high-speed mode and sees !squelch (01b on

LINESTATE). When the peripheral sees squelch (10b on LINESTATE), it knows

that the host has completed chirp and waits for Hi-Speed USB trafﬁc to begin. After

transmitting the chirp sequence, the host changes OPMODE[1:0] to 00b and

begins sending USB packets.

For more information, refer to UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

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USB reset

high-speed detection handshake (chirp)

t0

peripheral chirp

host chirp

HS idle

TXCMD

(REGW)

TXCMD

(REGW)

TXCMD

NOPID

SE0

K

00

K

...

J

K

J

DATA

[7:0]

DIR

STP

NXT

00 (HS)

01 (FS)

XCVR

SELECT

TERM

SELECT

00 (normal)

J (01b)

01 (chirp)

OP

MODE

squelch

(00b)

SE0 (00b)

host chirp K (10b) or chirp J (01b)

peripheral chirp K (10b)

squelch (00b)

LINE

STATE

RXCMDs

TXCMD

(REGW)

TXCMD

NOPID

(REGW)

00

K

J

K

J

00

SE0

K

...

K

J

DATA

[7:0]

DIR

STP

NXT

01 (FS)

00 (HS)

XCVR

SELECT

TERM

SELECT

00 (normal)

10 (chirp)

00 (normal)

OP

MODE

squelch

(00b)

!squelch

(01b)

squelch (00b)

peripheral chirp K (10b)

J (01b)

SE0 (00b)

host chirp K or J (10b or 01b)

LINE

STATE

DP

DM

001aai188

Timing is not to scale.

Fig 15. USB reset and high-speed detection handshake (chirp) sequence

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10.6 USB packet transmit and receive

An example of a packet transmit and receive is shown in Figure 16. For details on USB

packets, refer to UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

ISP1705

deasserts

DIR, causing

ISP1705

asserts DIR,

causing

turnaround

cycle

link sends

the next data;

ISP1705

sends

RXCMD

(NXT LOW)

ISP1705

sends

ISP1705

accepts

TXCMD

link sends

TXCMD

link signals ULPI bus

end of data is idle

USB data turnaround

accepts

(NXT HIGH)

cycle

CLOCK

turnaround RXCMD

DATA

turnaround

[

]

TXCMD

DATA

DATA 7:0

DIR

STP

NXT

004aab046

Fig 16. Example of using the ISP1705 to transmit and receive USB data

10.6.1 USB packet timing

10.6.1.1 ISP1705 pipeline delays

The ISP1705 delays (in clock cycles) are shown in Table 23. For detailed description, refer

to UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1, Section 3.8.2.6.2.

Table 23. PHY pipeline delays

Parameter name

High-speed PHY

delay

Full-speed PHY

delay

Low-speed PHY

delay

RXCMD delay (J and K)

RXCMD delay (SE0)

TX start delay

4

4 to 6

16 to 18

1 to 2

3 to 4

6 to 9

5 to 6

6 to 10

74 to 75

TX end delay (packets)

TX end delay (SOF)

RX start delay

not applicable

17 to 18

not applicable

122 to 123

RX end delay

10.6.1.2 Allowed link decision time

The amount of clock cycles allocated to the link to respond to a received packet and

correctly receive back-to-back packets is given in Table 24. Link designs must follow the

values given in Table 24 for correct USB system operation. Examples of high-speed

packet sequences and timing are shown in Figure 17 and Figure 18. For details, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1, Section 3.8.2.6.3.

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Table 24. Link decision times

Packet sequence High-speed Full-speed Low-speed Deﬁnition

link delay

link delay link delay

Transmit-Transmit 15 to 24

(host only)

7 to 18 77 to 247

Number of clock cycles a host link must wait before driving

the TXCMD for the second packet.

In high speed, the link starts counting from the assertion of

STP for the ﬁrst packet.

In full speed, the link starts counting from the RXCMD,

indicating LINESTATE has changed from SE0 to J for the ﬁrst

packet. The timing given ensures inter-packet delays of 2 bit

times to 6.5 bit times.

Receive-Transmit

(host or peripheral)

1 to 14

7 to 18

77 to 247

Number of clock cycles the link must wait before driving the

TXCMD for the transmit packet.

In high speed, the link starts counting from the end of the

receive packet; deassertion of DIR or an RXCMD indicating

RxActive is LOW.

In full speed or low speed, the link starts counting from the

RXCMD, indicating LINESTATE has changed from SE0 to J

for the receive packet. The timing given ensures inter-packet

delays of 2 bit times to 6.5 bit times.

Receive-Receive

(peripheral only)

1

Minimum number of clock cycles between consecutive

receive packets. The link must be capable of receiving both

packets.

Transmit-Receive

(host or peripheral)

92

80

718

Host or peripheral transmits a packet and will time-out after

this number of clock cycles if a response is not received. Any

subsequent transmission can occur after this time.

USB interpacket delay (88 to 192 high-speed bit times)

DP or

DM

IDLE

EOP

SYNC

D0

DATA

CLOCK

D

N−1

D

N

D1

TXCMD

DATA

[7:0]

DIR

STP

NXT

link decision time (15 to 24 clocks)

TX start delay

TX end delay (two to five clocks)

(one to two clocks)

004aaa712

Fig 17. High-speed transmit-to-transmit packet timing

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USB interpacket delay (8 to 192 high-speed bit times)

IDLE

DP or

DM

EOP

SYNC

DATA

CLOCK

D

N

D

N−4

D

N−2

D0

D1

TXCMD

DATA

[7:0]

turnaround

D

N−3

D

N−1

DIR

STP

NXT

link decision time (1 to 14 clocks)

RX end delay

(three to eight clocks)

TX start delay

(one to two clocks)

004aaa713

Fig 18. High-speed receive-to-transmit packet timing

10.7 Preamble

Preamble packets are headers to low-speed packets that must travel over a full-speed

bus, between a host and a hub. To enter preamble mode, the link sets

XCVRSELECT[1:0] = 11b in the FUNC_CTRL register (see Section 11.5). When in

preamble mode, the ISP1705 operates just as in full-speed mode, and sends all data with

the full-speed rise time and fall time. Whenever the link transmits a USB packet in

preamble mode, the ISP1705 will automatically send a preamble header at full-speed bit

rate before sending the link packet at low-speed bit rate. The ISP1705 will ensure a

minimum gap of four full-speed bit times between the last bit of the full-speed PRE PID

and the ﬁrst bit of the low-speed packet SYNC. The ISP1705 will drive a J for at least one

full-speed bit time after sending the PRE PID, after which the pull-up resistor can hold the

J state on the bus. An example transmit packet is shown in Figure 19.

In preamble mode, the ISP1705 can also receive low-speed packets from the full-speed

bus.

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CLOCK

D1

D0

TXCMD (low-speed packet ID)

DATA[7:0]

DIR

STP

NXT

FS

PRE ID

IDLE (min

4 FS bits)

LS D0

LS D1

LS SYNC

LS PID

FS SYNC

DP or DM

004aaa714

DP and DM timing is not to scale.

Fig 19. Preamble sequence

10.8 USB suspend and resume

10.8.1 Full-speed or low-speed host-initiated suspend and resume

Figure 20 illustrates how a host or a hub places a full-speed or low-speed peripheral into

suspend and sometime later initiates resume signaling to wake-up the downstream

peripheral. Note that Figure 20 timing is not to scale, and does not show all RXCMD

LINESTATE updates.

The sequence of events for a host and a peripheral, both with ISP1705, is as follows:

1. Idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ pull-down

resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and 45 Ω

terminations are disabled (TERMSELECT is set to 1b). The peripheral has the 1.5 kΩ

pull-up resistor connected to DP for full speed or DM for low speed (TERMSELECT is

set to 1b).

2. Suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend

state. The peripheral link places the PHY into low-power mode by clearing the

SUSPENDM bit in the FUNC_CTRL register (see Section 11.5), causing the PHY to

draw only suspend current. The host may or may not be powered down.

3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE[1:0] to

10b and transmits a K for at least 20 ms. The peripheral link sees the resume K on

LINESTATE, and asserts STP to wake up the PHY.

4. EOP: When STP is asserted, the ISP1705 on the host side automatically appends an

EOP of two bits of SE0 at low-speed bit rate, followed by one bit of J. The ISP1705 on

the host side knows to add the EOP because DP_PULLDOWN and DM_PULLDOWN

are set to 1b for a host. After the EOP is completed, the host link sets OPMODE[1:0]

to 00b for normal operation. The peripheral link sees the EOP and also resumes

normal operation.

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EOP

idle

suspend

resume K

TXCMD

(REGW)

TXCMD

NOPID

K

...

K

TXCMD

K

DATA

[

]

7:0

DIR

STP

NXT

OPMODE

10b

00b

LINE

STATE

K

SE0

J

CLOCK

TXCMD

(REGW)

LINESTATE J

LINESTATE K

SE0

J

DATA

[

]

7:0

DIR

STP

NXT

00b

OPMODE

10b

00b

SUSPENDM

LINE

STATE

K

SE0

J

DP

DM

004aab123

Timing is not to scale.

Fig 20. Full speed suspend and resume

10.8.2 High speed suspend and resume

Figure 21 illustrates how a host or a hub places a high-speed enabled peripheral into

suspend and then initiates resume signaling. The high-speed peripheral will wake up and

return to high-speed operations. Note that Figure 21 timing is not to scale, and does not

show all RXCMD LINESTATE updates.

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The sequence of events related to a host and a peripheral, both with ISP1705, is as

follows:

1. High speed idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ

pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b)

and 45 Ω terminations enabled (TERMSELECT is set to 0b). The peripheral has its

45 Ω terminations enabled (TERMSELECT is set to 0b).

2. Full speed suspend: When the peripheral sees no bus activity for 3 ms, it enters the

suspend state. The peripheral link places the ISP1705 into full-speed mode

(XCVRSELECT is set to 01b), removes 45 Ω terminations, and enables the 1.5 kΩ

pull-up resistor on DP (TERMSELECT is set to 1b). The peripheral link then places

the ISP1705 into low-power mode by clearing SUSPENDM, causing the ISP1705 to

draw only suspend current. The host also changes the ISP1705 to full speed,

(XCVRSELECT is set to 01b), removes 45 Ω terminations (TERMSELECT is set to

1b), and then may or may not be powered down.

3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE to 10b

and transmits a full-speed K for at least 20 ms. The peripheral link sees the resume K

(10b) on LINESTATE, and asserts STP to wake up the ISP1705.

4. High-speed trafﬁc: The host link sets high speed (XCVRSELECT is set to 00b), and

enables its 45 Ω terminations (TERMSELECT is set to 0b). The peripheral link sees

SE0 on LINESTATE and also sets high speed (XCVRSELECT is set to 00b), and

enables its 45 Ω terminations (TERMSELECT is set to 0b). The host link sets

OPMODE to 00b for normal high-speed operation.

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FS suspend

resume K

HS idle

TXCMD

(REGW)

TXCMD

(REGW)

TXCMD

(REGW)

TXCMD

NOPID

K

...

K

DATA

[

]

7:0

DIR

STP

NXT

XCVR

01b

00b

SELECT

TERM

SELECT

OP

10b

00b

MODE

!SQUELCH

(01b)

!SQUELCH SQUELCH

FS J (01b)

FS K (10b)

SQUELCH (00b)

(01b)

(00b)

LINE

STATE

CLOCK

TXCMD

(REGW)

TXCMD

(REGW)

LINESTATE K

LINESTATE J

SE0

DATA

[

]

7:0

DIR

STP

NXT

XCVR

SELECT

01b

00b

TERM

SELECT

OP

MODE

00b

10b

00b

SUSPENDM

!SQUELCH

(01b)

!SQUELCH

(01b)

SQUELCH

(00b)

FS K (10b)

SQUELCH (00b)

FS J (01b)

LINE

STATE

DP

DM

004aab124

Timing is not to scale.

Fig 21. High speed suspend and resume

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10.8.3 Remote wake-up

The ISP1705 supports peripherals that initiate remote wake-up resume. When placed into

USB suspend, the peripheral link remembers at what speed it was originally operating.

Depending on the original speed, the link follows one of the protocols detailed here. In

Figure 22, timing is not to scale, and not all RXCMD LINESTATE updates are shown.

The sequence of events related to a host and a peripheral, both with ISP1705, is as

follows:

1. Both the host and the peripheral are assumed to be in low-power mode.

2. The peripheral begins remote wake-up by re-enabling its clock and setting its

SUSPENDM bit to 1b.

3. The peripheral begins driving K on the bus to signal resume. Note that the peripheral

link must assume that LINESTATE is K (01b) while transmitting because it will not

receive any RXCMDs.

4. The host recognizes the resume, re-enables its clock and sets its SUSPENDM bit.

5. The host takes over resume driving within 1 ms of detecting the remote wake-up.

6. The peripheral stops driving resume.

7. The peripheral sees the host continuing to drive the resume.

8. The host stops driving resume and the ISP1705 automatically adds the EOP to the

end of the resume. The peripheral recognizes the EOP as the end of resume.

9. Both the host and the peripheral revert to normal operation by writing 00b to

OPMODE. If the host or the peripheral was previously in high-speed mode, it must

revert to high speed before the SE0 of the EOP is completed. This can be achieved by

writing XCVRSELECT[1:0] = 00b and TERMSELECT = 0b after LINESTATE indicates

SE0.

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TXCMD

NOPID

TXCMD

REGW

TXCMD

REGW

00h

LINESTATE

DATA

[

]

7:0

DIR

STP

NXT

XCVR

SELECT

01b (FS), 10b (LS)

00b (HS only)

TERM

SELECT

0b (HS only)

00b

OP

MODE

10b

TXCMD

REGW

TXCMD

REGW

TXCMD

NOPID

LINESTATE

00h

RXCMD

DATA

[

]

7:0

DIR

STP

NXT

00b (HS only)

0b (HS only)

XCVR

SELECT

00b (HS), 01b (FS), 10b (LS)

TERM

SELECT

OP

MODE

10b

00b

004aaa718

Timing is not to scale.

Fig 22. Remote wake-up from low-power mode

10.9 No automatic SYNC and EOP generation (optional)

This setting allows the link to turn off the automatic SYNC and EOP generation, and must

be used for high-speed packets only. It is provided for backwards compatibility with legacy

controllers that include SYNC and EOP bytes in the data payload when transmitting

packets. The ISP1705 will not automatically generate SYNC and EOP patterns when

OPMODE[1:0] is set to 11b. The ISP1705 will still NRZI encode data and perform bit

stufﬁng. An example of a sequence is shown in Figure 23. The link must always send

packets using the TXCMD (NOPID) type. The ISP1705 does not provide a mechanism to

control bit stufﬁng in individual bytes, but will automatically turn off bit stufﬁng for EOP

when STP is asserted with data set to FEh. If data is set to 00h when STP is asserted, the

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PHY will not transmit any EOP. The ISP1705 will also detect if the PID byte is A5h,

indicating an SOF packet, and automatically send a long EOP when STP is asserted. To

transmit chirp and resume signaling, the link must set OPMODE to 10b.

CLOCK

... ...

TXCMD

00h

00h 00h 80h PID D1 D2 D3

D

N − 1

D

N

FEh

DATA

[7:0]

DIR

STP

NXT

TXVALID

TXREADY

TXBIT

STUFF

ENABLE

IDLE

SYNC

PID

DATA PAYLOAD

EOP

IDLE

DP, DM

004aab125

Fig 23. Transmitting USB packets without automatic SYNC and EOP generation

10.10 On-The-Go operations

On-The-Go (OTG) is a supplement to Universal Serial Bus Speciﬁcation Rev. 2.0 that

allows a portable USB device to assume the role of a limited USB host by deﬁning

improvements, such as a small connector and low power. Non-portable devices, such as

standard hosts and embedded hosts, can also beneﬁt from OTG features.

The ISP1705 OTG PHY is designed to support all the tasks speciﬁed in the OTG

supplement. The ISP1705 provides the front end analog support for Host Negotiation

Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices. The

supporting components include:

• Voltage comparators

– A_VBUS_VLD

– SESS_VLD (session valid, can be used for both A-session and B-session valid)

– SESS_END (session end)

• Pull-up and pull-down resistors on DP and DM

• ID detector indicates if micro-A or micro-B plug is inserted

• Charge and discharge resistors on V_BUS

The following subsections describe how to use the ISP1705 OTG components.

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10.10.1 OTG comparators

The ISP1705 provides comparators that conform to On-The-Go Supplement to the

USB 2.0 Speciﬁcation Rev. 1.3 requirements of V_{A_VBUS_VLD}, V_{A_SESS_VLD}, V_{B_SESS_VLD}

and V_{B_SESS_END}. In this data sheet, V_{A_SESS_VLD}and V_{B_SESS_VLD}are combined into

V_{A_SESS_VLD}. Comparators are described in Section 8.7.2. Changes in comparator values

are communicated to the link by RXCMDs as described in Section 10.3.2. Control over

comparators is described in Section 11.8 to Section 11.11.

10.10.2 Pull-up and pull-down resistors

The USB resistors on DP and DM can be used to initiate data-line pulsing SRP. The link

must set the required bus state using the mode settings in Table 15.

10.10.3 ID detection

The ISP1705 provides an internal pull-up resistor to sense the state of the ID pin. The

pull-up resistor must ﬁrst be enabled by setting the ID_PULLUP register bit to logic 1. If

the state of pin ID has changed, the ISP1705 will send an RXCMD or interrupt to the link

by time t_ID. If the link does not receive any RXCMD or interrupt by t_ID, then the ID state has

not changed.

10.10.4 V_BUScharge and discharge resistors

A pull-up resistor, R_UP(VBUS), is provided to perform V_BUSpulsing SRP. A B-device is

allowed to charge V_BUSabove the session valid threshold to request the host to turn on

the V_BUSvoltage.

A pull-down resistor, R_DN(VBUS), is provided for a B-device to discharge V_BUS. This is done

whenever the A-device turns off the V_BUSvoltage; the B-device can use the pull-down

resistor to ensure V_BUSis below V_{B_SESS_END}before starting a session.

For details, refer to On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.3.

10.11 Serial modes

The ISP1705 supports both 6-pin serial mode and 3-pin serial mode, controlled by

bits 6PIN_FSLS_SERIAL and 3PIN_FSLS_SERIAL of the INTF_CTRL register (see

Section 11.6). For details, refer to UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1,

Section 3.10.

Figure 24 and Figure 25 provide examples of 6-pin serial mode and 3-pin serial mode,

respectively.

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TRANSMIT

DATA

RECEIVE

SYNC

DATA

EOP

DATA0

(TX_ENABLE)

DATA1

(TX_DAT)

DATA2

(TX_SE0)

DATA4

(RX_DP)

DATA5

(RX_DM)

DATA6

(RX_RCV)

DP

DM

004aaa692

Fig 24. Example of transmit followed by receive in 6-pin serial mode

TRANSMIT

RECEIVE

DATA

SYNC

EOP

DATA0

(TX_ENABLE)

DATA1

(TX_DAT/

RX_RCV)

DATA2

(TX_SE0/

RX_SE0)

DP

DM

004aaa693

Fig 25. Example of transmit followed by receive in 3-pin serial mode

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10.12 Aborting transfers

The ISP1705 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low

Pin Interface (ULPI) Speciﬁcation Rev. 1.1, Section 3.8.4.

10.13 Avoiding contention on the ULPI data bus

Because the ULPI data bus is bidirectional, avoid situations in which both the link and the

PHY simultaneously drive the data bus.

The following points must be considered while implementing the data bus drive control on

the link.

After power-up and clock stabilization, default states are as follows:

• The ISP1705 drives DIR to LOW.

• The data bus is input to the ISP1705.

• The ULPI link data bus is output, with all data bus lines driven to LOW.

When the ISP1705 wants to take control of the data bus to initiate a data transfer, it

changes the DIR state from LOW to HIGH.

At this point, the link must disable its output buffers. This must be as fast as possible so

the link must use a combinational path from DIR.

The ISP1705 will not immediately enable its output buffers, but will delay the enabling of

its buffers until the next clock edge, avoiding bus contention.

When the data transfer is no longer required by the ISP1705, it changes DIR from HIGH to

LOW and starts to immediately turn off its output drivers. The link senses the change of

DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle,

avoiding data bus contention.

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11. Register map

Table 25. Register map

Field name

Size (bit)

Address (6 bit)

R^[1]

References

W^[2]

S^[3]

-

C^[4]

-

VENDOR_ID_LOW

VENDOR_ID_HIGH

PRODUCT_ID_LOW

PRODUCT_ID_HIGH

FUNC_CTRL

8

00h

-

Section 11.1 on page 52

Section 11.2 on page 52

Section 11.3 on page 53

Section 11.4 on page 53

Section 11.5 on page 53

Section 11.6 on page 55

Section 11.7 on page 56

Section 11.8 on page 58

Section 11.9 on page 58

Section 11.10 on page 59

Section 11.11 on page 59

Section 11.12 on page 60

Section 11.13 on page 61

Section 11.14 on page 61

-

01h

-

02h

-

03h

-

04h to 06h

07h to 09h

0Ah to 0Ch

0Dh to 0Fh

10h to 12h

13h

04h

07h

0Ah

0Dh

10h

-

05h

08h

0Bh

0Eh

11h

-

06h

09h

0Ch

0Fh

12h

-

INTF_CTRL

OTG_CTRL

USB_INTR_EN_R

USB_INTR_EN_F

USB_INTR_STAT

USB_INTR_L

14h

-

DEBUG

15h

-

SCRATCH

16h to 18h

19h to 1Bh

1Ch to 3Ch

3Dh to 3Fh

16h

19h

-

17h

1Ah

-

18h

1Bh

-

CARKIT_CTRL

Reserved

PWR_CTRL

3Dh

3Eh

3Fh

Section 11.15 on page 62

[1] Read (R): A register can be read. Read-only if this is the only mode given.

[2] Write (W): The pattern on the data bus will be written over all bits of a register.

[3] Set (S): The pattern on the data bus is OR-ed with and written to a register.

[4] Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero

(cleared).

11.1 VENDOR_ID_LOW register

Table 26 shows the bit description of the register.

Table 26. VENDOR_ID_LOW - Vendor ID low register (address R = 00h) bit description

Legend: * reset value

Bit

Symbol

Access Value

CCh*

Description

7 to 0 VENDOR_

ID_LOW[7:0]

R

Vendor ID low: Lower byte of the NXP vendor ID

supplied by USB-IF; ﬁxed value of CCh

11.2 VENDOR_ID_HIGH register

Table 27 shows the bit description of the register.

Table 27. VENDOR_ID_HIGH - Vendor ID high register (address R = 01h) bit description

Legend: * reset value

Bit

Symbol

Access Value

04h*

Description

7 to 0 VENDOR_

ID_HIGH[7:0]

R

Vendor ID high: Upper byte of the NXP vendor ID

supplied by USB-IF; ﬁxed value of 04h

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ISP1705

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ULPI Hi-Speed USB transceiver

11.3 PRODUCT_ID_LOW register

The bit description of the register is given in Table 28.

Table 28. PRODUCT_ID_LOW - Product ID low register (address R = 02h) bit description

Legend: * reset value

Bit

Symbol

Access Value

05h*

Description

7 to 0 PRODUCT_ID_

LOW[7:0]

R

Product ID low: Lower byte of the NXP product

ID number; ﬁxed value of 05h

11.4 PRODUCT_ID_HIGH register

The bit description of the register is given in Table 29.

Table 29. PRODUCT_ID_HIGH - Product ID high register (address R = 03h) bit description

Legend: * reset value

Bit

Symbol

Access Value

17h*

Description

7 to 0 PRODUCT_ID_

HIGH[7:0]

R

Product ID high: Upper byte of the NXP product

ID number; ﬁxed value of 17h

11.5 FUNC_CTRL register

This register controls UTMI function settings of the PHY. The bit allocation of the register

is given in Table 30.

Table 30. FUNC_CTRL - Function control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved SUSPENDM

RESET

OPMODE[1:0]

TERM

XCVRSELECT[1:0]

SELECT

Reset

0

1

0

1

Access

R/W/S/C

Table 31. FUNC_CTRL - Function control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit

description

Bit

7

Symbol

Description

-

reserved

6

SUSPENDM

Suspend: Active-LOW PHY suspend.

Places the PHY into low-power mode. The PHY will power down all blocks, except the

full-speed receiver, OTG comparators and ULPI interface pins.

To come out of low-power mode, the link must assert STP. The PHY will automatically clear

this bit when it exits low-power mode.

0b — Low-power mode

1b — Powered

5

RESET

Reset: Active-HIGH transceiver reset.

After the link sets this bit, the PHY will assert DIR and reset the digital core. This does not

reset the ULPI interface or the ULPI register set.

When the reset is completed, the PHY will deassert DIR and automatically clear this bit,

followed by an RXCMD update to the link.

The link must wait for DIR to be deasserted before using the ULPI bus.

0b — Do not reset

1b — Reset

ISP1705_1

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ISP1705

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ULPI Hi-Speed USB transceiver

Table 31. FUNC_CTRL - Function control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit

description …continued

Bit

Symbol

Description

4 to 3

OPMODE[1:0]

Operation mode: Selects the required bit-encoding style during transmit.

00b — Normal operation

01b — Non-driving

10b — Disable bit-stufﬁng and NRZI encoding

11b — Do not automatically add SYNC and EOP when transmitting; must be used only for

high-speed packets

2

TERMSELECT

Termination select: Controls the internal 1.5 kΩ full-speed pull-up resistor and 45 Ω

high-speed terminations. Control over bus resistors changes, depending on

XCVRSELECT[1:0], OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in

Table 15.

1 to 0

XCVRSELECT[1:0] Transceiver select: Selects the required transceiver speed.

00b — Enable the high-speed transceiver

01b — Enable the full-speed transceiver

10b — Enable the low-speed transceiver

11b — Enable the full-speed transceiver for low-speed packets (full-speed preamble is

automatically preﬁxed)

ISP1705_1

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ISP1705

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ULPI Hi-Speed USB transceiver

11.6 INTF_CTRL register

The INTF_CTRL register enables alternative interfaces. All of these modes are optional

features provided for legacy link cores. Setting more than one of these ﬁelds results in

undeﬁned behavior. Table 32 provides the bit allocation of the register.

Table 32. INTF_CTRL - Interface control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

INTF_

PROT_DIS

IND_PASS

THRU

IND_

COMPL

reserved

CLOCK_

SUSPENDM

CARKIT_

MODE

3PIN_

FSLS_

SERIAL

6PIN_

FSLS_

SERIAL

Reset

0

Access

R/W/S/C

Table 33. INTF_CTRL - Interface control register (address R = 07h to 09h, W = 07h, S = 08h,

C = 09h) bit description

Bit Symbol

Description

7

INTF_PROT_DIS

Interface protect disable: Controls circuitry built into the ISP1705

to protect the ULPI interface when the link 3-states STP and

DATA[7:0]. When this bit is enabled, the ISP1705 will automatically

detect when the link stops driving STP.

0b — Enables the interface protect circuit. The ISP1705 attaches

a weak pull-up resistor on STP. If STP is unexpectedly HIGH, the

ISP1705 attaches weak pull-down resistors on DATA[7:0],

protecting data inputs

1b — Disables the interface protect circuit, detaches weak

pull-down resistors on DATA[7:0], and a weak pull-up resistor on

STP

6

5

IND_PASSTHRU

Indicator pass-through: Controls whether the complement output

is qualiﬁed with the internal A_VBUS_VLD comparator before

being used in the V_BUSstate in RXCMD.

0b — The complement output signal is qualiﬁed with the internal

A_VBUS_VLD comparator

1b — The complement output signal is not qualiﬁed with the

internal A_VBUS_VLD comparator

IND_COMPL

Indicator complement: Informs the PHY to invert the FAULT input

signal, generating the complement output.

0b — The ISP1705 will not invert the FAULT signal

1b — The ISP1705 will invert the FAULT signal

reserved

4

3

-

CLOCK_SUSPENDM Clock suspend: Active-LOW clock suspend.

Powers down the internal clock circuitry only. By default, the clock

will not be powered in 6-pin serial mode or 3-pin serial mode.

Valid only in 6-pin serial mode and 3-pin serial mode. Valid only

when SUSPENDM is set to logic 1, otherwise this bit is ignored.

0b — Clock will not be powered in 3-pin or 6-pin serial mode or

UART mode

1b — Clock will be powered in 3-pin and 6-pin serial mode or

UART mode

ISP1705_1

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ISP1705

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ULPI Hi-Speed USB transceiver

Table 33. INTF_CTRL - Interface control register (address R = 07h to 09h, W = 07h, S = 08h,

C = 09h) bit description …continued

Bit Symbol

Description

2

CARKIT_MODE

Carkit mode: Changes the ULPI interface to the carkit interface

(UART mode). Bits TXD_EN and RXD_EN in the CARKIT_CTRL

register (see Section 11.14) must change as well. The PHY must

automatically clear this bit when carkit mode is exited.

0b — Disable carkit mode

1b — Enable carkit mode

1

3PIN_FSLS_SERIAL

6PIN_FSLS_SERIAL

3-pin full-speed low-speed serial mode: Changes the ULPI

interface to a 3-bit serial interface. The ISP1705 will automatically

clear this bit when 3-pin serial mode is exited.

0b — Full-speed or low-speed packets are sent using the parallel

interface

1b — Full-speed or low-speed packets are sent using the 3-pin

serial interface

0

6-pin full-speed low-speed serial mode: Changes the ULPI

interface to a 6-bit serial interface. The ISP1705 will automatically

clear this bit when 6-pin serial mode is exited.

0b — Full-speed or low-speed packets are sent using the parallel

interface

1b — Full-speed or low-speed packets are sent using the 6-pin

serial interface

11.7 OTG_CTRL register

This register controls various OTG functions of the ISP1705. The bit allocation of the

OTG_CTRL register is given in Table 34.

Table 34. OTG_CTRL - OTG control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

USE_EXT_

VBUS_IND VBUS_EXT

DRV_

reserved

CHRG_

VBUS

DISCHRG_ DM_PULL

DP_PULL

DOWN

ID_PULL

UP^[1]

VBUS

DOWN

Reset

0

1

0

Access

R/W/S/C

[1] A weak pull-up, which can detect ID correctly, is present when the ID_PULLUP bit is disabled. It is, however, mandatory that the link

enables ID_PULLUP.

ISP1705_1

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ISP1705

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ULPI Hi-Speed USB transceiver

Table 35. OTG_CTRL - OTG control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh,

C = 0Ch) bit description

Bit Symbol

Description

7

USE_EXT_

Use external V_BUSindicator: Informs the PHY to use an external

VBUS_IND

V_BUSovercurrent indicator.

0b — Use the internal OTG comparator

1b — Use the external V_BUSvalid indicator signal input from the

FAULT pin

6

DRV_VBUS_EXT

Drive V_BUSexternal: Controls the external charge pump or 5 V supply

by the PSW_N pin.

0b — PSW_N is HIGH

1b — PSW_N to LOW

5

4

reserved

-

CHRG_VBUS

Charge V_BUS: Charges V_BUSthrough a resistor. Used for the V_BUS

pulsing of SRP. The link must ﬁrst check that V_BUSis discharged (see

bit DISCHRG_VBUS), and that both the DP and DM data lines have

been LOW (SE0) for 2 ms.

0b — Do not charge V_BUS

1b — Charge V_BUS

3

DISCHRG_VBUS

Discharge V_BUS: Discharges V_BUSthrough a resistor. If the link sets

this bit to logic 1, it waits for an RXCMD indicating that SESS_END

has changed from logic 0 to logic 1, and then resets this bit to logic 0

to stop the discharge.

0b — Do not discharge V_BUS

1b — Discharge V_BUS

2

1

0

DM_PULLDOWN

DP_PULLDOWN

ID_PULLUP

DM pull down: Enables the 15 kΩ pull-down resistor on DM.

0b — pull-down resistor is not connected to DM

1b — pull-down resistor is connected to DM

DP pull down: Enables the 15 kΩ pull-down resistor on DP.

0b — Pull-down resistor is not connected to DP

1b — Pull-down resistor is connected to DP

ID pull up: Connects a pull-up to the ID line and enables sampling of

the ID level. Disabling the ID line sampler will reduce the PHY power

consumption.

0b — Disable sampling of the ID line

1b — Enable sampling of the ID line

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ISP1705

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ULPI Hi-Speed USB transceiver

11.8 USB_INTR_EN_R register

The bits in this register enable interrupts and RXCMDs to be sent when the corresponding

bits in the USB_INTR_STAT register change from logic 0 to logic 1. By default, all

transitions are enabled. Table 36 shows the bit allocation of the register.

Table 36. USB_INTR_EN_R - USB interrupt enable rising register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,

C = 0Fh) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved

ID_GND_R

SESS_

END_R

SESS_

VALID_R

VBUS_

VALID_R DISCON_R

HOST_

Reset

0

1

Access

R/W/S/C

Table 37. USB_INTR_EN_R - USB interrupt enable rising register (address R = 0Dh to 0Fh,

W = 0Dh, S = 0Eh, C = 0Fh) bit description

Bit

7 to 5

4

Symbol

Description

-

reserved

ID_GND_R

ID ground rise: Enables interrupts and RXCMDs for logic 0 to

logic 1 transitions on ID_GND

3

2

1

SESS_END_R

SESS_VALID_R

VBUS_VALID_R

Session end rise: Enables interrupts and RXCMDs for logic 0 to

logic 1 transitions on SESS_END

Session valid rise: Enables interrupts and RXCMDs for logic 0

to logic 1 transitions on SESS_VLD

V_BUSvalid rise: Enables interrupts and RXCMDs for logic 0 to

logic 1 transitions on A_VBUS_VLD

0

HOST_DISCON_R Host disconnect rise: Enables interrupts and RXCMDs for

logic 0 to logic 1 transitions on HOST_DISCON

11.9 USB_INTR_EN_F register

The bits in this register enable interrupts and RXCMDs to be sent when the corresponding

bits in the USB_INTR_STAT register change from logic 1 to logic 0. By default, all

transitions are enabled. See Table 38.

Table 38. USB_INTR_EN_F - USB interrupt enable falling register (address R = 10h to 12h, W = 10h, S = 11h,

C = 12h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved

ID_GND_F

SESS_

END_F

SESS_

VALID_F

VBUS_

VALID_F

HOST_

DISCON_F

Reset

0

1

Access

R/W/S/C

ISP1705_1

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ISP1705

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ULPI Hi-Speed USB transceiver

Table 39. USB_INTR_EN_F - USB interrupt enable falling register (address R = 10h to 12h,

W = 10h, S = 11h, C = 12h) bit description

Bit

7 to 5

4

Symbol

Description

-

reserved

ID_GND_F

ID ground fall: Enables interrupts and RXCMDs for logic 1 to

logic 0 transitions on ID_GND.

3

2

1

SESS_END_F

SESS_VALID_F

VBUS_VALID_F

Session end fall: Enables interrupts and RXCMDs for logic 1 to

logic 0 transitions on SESS_END.

Session valid fall: Enables interrupts and RXCMDs for logic 1 to

logic 0 transitions on SESS_VLD.

V_BUSvalid fall: Enables interrupts and RXCMDs for logic 1 to

logic 0 transitions on A_VBUS_VLD.

0

HOST_DISCON_F

Host disconnect fall: Enables interrupts and RXCMDs for logic 1

to logic 0 transitions on HOST_DISCON.

11.10 USB_INTR_STAT register

This register (see Table 40) indicates the current value of the interrupt source signal.

Table 40. USB_INTR_STAT - USB interrupt status register (address R = 13h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved

ID_GND

SESS_

END

SESS_

VALID

VBUS_

VALID

HOST_

DISCON

Reset

X

R

X

R

X

R

0

Access

R

Table 41. USB_INTR_STAT - USB interrupt status register (address R = 13h) bit description

Bit

7 to 5

4

Symbol

-

Description

reserved

ID_GND

SESS_END

ID ground: Reﬂects the current state of the ID detector circuit.

3

Session end: Reﬂects the current value of the session end

voltage comparator.

2

1

SESS_VALID

VBUS_VALID

Session valid: Reﬂects the current value of the session valid

voltage comparator.

V_BUSvalid: Reﬂects the current value of the V_BUSvalid voltage

comparator.

0

HOST_DISCON

Host disconnect: Reﬂects the current value of the host

disconnect detector.

11.11 USB_INTR_L register

The bits of the USB_INTR_L register are automatically set by the ISP1705 when an

unmasked change occurs on the corresponding interrupt source signal. The ISP1705 will

automatically clear all bits when the link reads this register, or when the PHY enters

low-power mode.

Remark: It is optional for the link to read this register when the clock is running because

all signal information will automatically be sent to the link through the RXCMD byte.

The bit allocation of this register is given in Table 42.

ISP1705_1

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ISP1705

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ULPI Hi-Speed USB transceiver

Table 42. USB_INTR_L - USB interrupt latch register (address R = 14h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved

ID_GND_L

SESS_

END_L

SESS_

VALID_L

VBUS_

VALID_L

HOST_

DISCON_L

Reset

0

Access

R

Table 43. USB_INTR_L - USB interrupt latch register (address R = 14h) bit description

Bit

Symbol

Description

7 to 5 reserved

-

4

3

2

1

ID_GND_L

ID ground latch: Automatically set when an unmasked event occurs

on ID_GND. Cleared when this register is read.

SESS_END_L

SESS_VALID_L

VBUS_VALID_L

Session end latch: Automatically set when an unmasked event

occurs on SESS_END. Cleared when this register is read.

Session valid latch: Automatically set when an unmasked event

occurs on SESS_VLD. Cleared when this register is read.

V_BUSvalid latch: Automatically set when an unmasked event occurs

on A_VBUS_VLD. Cleared when this register is read.

0

HOST_DISCON_L Host disconnect latch: Automatically set when an unmasked event

occurs on HOST_DISCON. Cleared when this register is read.

11.12 DEBUG register

The bit allocation of the DEBUG register is given in Table 44. This register indicates the

current value of signals useful for debugging.

Table 44. DEBUG - Debug register (address R = 15h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved

LINE

STATE1

STATE0

Reset

0

Access

R

Table 45. DEBUG - Debug register (address R = 15h) bit description

Bit

7 to 2

1

Symbol

-

Description

reserved

LINESTATE1

LINESTATE0

Line state 1: Contains the current value of LINESTATE 1

Line state 0: Contains the current value of LINESTATE 0

0

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ISP1705

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ULPI Hi-Speed USB transceiver

11.13 SCRATCH register

This is a 1-byte empty register for testing purposes, see Table 46.

Table 46. SCRATCH - Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h)

bit description

Bit

Symbol

Access Value Description

7 to 0 SCRATCH[7:0] R/W/S/C 00h

Scratch: This is an empty register byte for testing

purposes. Software can read, write, set and clear

this register. The functionality of the PHY will not be

affected.

11.14 CARKIT_CTRL register

This register controls transparent UART mode. This register is only valid when the

CARKIT_MODE bit in the INTF_CTRL register (see Section 11.6) is set. When entering

UART mode, set the CARKIT_MODE bit, and then set the TXD_EN and RXD_EN bits.

After entering UART mode, the ULPI interface is not available. When exiting UART mode,

assert the STP pin or perform a hardware reset using chip select.

For bit allocation, see Table 47.

Table 47. CARKIT_CTRL - Carkit control register (address R = 19h to 1Bh, W = 19h, S = 1Ah, C = 1Bh) bit

allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

reserved

RXD_EN

0

TXD_EN

0

reserved

0

R/W/S/C

Table 48. CARKIT_CTRL - Carkit control register (address R = 19h to 1Bh, W = 19h,

S = 1Ah, C = 1Bh) bit description

Bit

7 to 4

3

Symbol

-

Description

reserved; the link must never write logic 1 to these bits

RXD_EN

RXD enable: Routes the UART RXD signal from the DP pin to the

DATA1 pin. This bit will automatically be cleared when UART mode is

exited.

2

TXD_EN

-

TXD enable: Routes the UART TXD signal from the DATA0 pin to the

DM pin. This bit will automatically be cleared when UART mode is

exited.

1 to 0

reserved; the link must never write logic 1 to these bits

ISP1705_1

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ISP1705

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ULPI Hi-Speed USB transceiver

11.15 PWR_CTRL register

This vendor-speciﬁc register controls the power feature of the ISP1705. The bit allocation

of the register is given in Table 49.

Table 49. PWR_CTRL - Power control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved

DP_WKPU_

EN

BVALID_

FALL

BVALID_

RISE

reserved

Reset

0

Access

R/W/S/C

Table 50. PWR_CTRL - Power control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,

C = 3Fh) bit description

Bit

7 to 5

4

Symbol

Description

-

reserved; the link must never write logic 1 to these bits

DP_WKPU_EN DP weak pull-up enable: Enable the weak pull-up resistor on the DP

pin (R_weakUP(DP)) in synchronous mode when V_BUSis above the

V_{A_SESS_VLD}threshold. Note that when the ISP1705 is in UART

mode, the DP weak pull-up will be enabled, regardless of the value of

this register bit.

0 — DP weak pull-up is disabled.

1 — DP weak pull-up is enabled when V_BUS> V_{A_SESS_VLD}

.

3

BVALID_FALL

BVALID fall: Enables RXCMDs for HIGH-to-LOW transitions on

BVALID. When BVALID changes from HIGH to LOW, the ISP1705

will send an RXCMD to the link with the ALT_INT bit set to logic 1.

This bit is optional and is not necessary for OTG devices. This bit is

provided for debugging purposes. Disabled by default.

2

BVALID_RISE

BVALID rise: Enables RXCMDs for LOW-to-HIGH transitions on

BVALID. When BVALID changes from LOW to HIGH, the ISP1705

will send an RXCMD to the link with the ALT_INT bit set to logic 1.

This bit is optional and is not necessary for OTG devices. This bit is

provided for debugging purposes. Disabled by default.

1 to 0

-

reserved; the link must never write logic 1 to these bits

ISP1705_1

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ISP1705

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12. Limiting values

Table 51. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

V_CCsupply voltage

V_CC(I/O)input/output supply voltage

Conditions

Min

Max

+5.5

+4.6

+5.5

Unit

V

−0.5

V

V_I

input voltage

on pins PSW_N and FAULT

V

on pins CLOCK, STP, DATA[7:0], CFG1,

CFG2, RESET_N, CHIP_SEL and

CHIP_SEL_N

V_CC(I/O)+ 0.5 V

on pins ID and CFG0

−0.5

−2

+4.6

+2.5

+4.6

+5.5

+2

V

on pin XTAL1

V

[1]

[2]

on pins DP and DM

V

on pin V_BUS

V

V_ESD

electrostatic discharge

voltage

human body model (JESD22-A114D)

machine model (JESD22-A115-A)

charged device model (JESD22-C101-C)

IEC 61000-4-2 contact on pins DP and DM

kV

V

−200

−500

−8

+200

+500

+8

V

[3]

kV

mA

°C

I_lu

latch-up current

-

100

T_stg

storage temperature

−60

+125

[1] The ISP1705 has been tested according to the additional requirements listed in Universal Serial Bus Speciﬁcation Rev. 2.0,

Section 7.1.1. The short circuit withstand test and the AC stress test were performed for 24 hours, and the ISP1705 was found to be fully

operational after the test completed.

[2] When an external series resistor is added to the V_BUSpin, it can withstand higher voltages for longer periods of time because the

resistor limits the current ﬂowing into the V_BUSpad. For example, with an external 1 kΩ resistor, V_BUScan tolerate 10 V for at least

5 seconds. Actual performance may vary depending on the resistor used and whether other components are connected to V_BUS

.

[3] The ISP1705 has been tested in-house according to the IEC 61000-4-2 standard on the DP and DM pins. It is recommended that

customers perform their own ESD tests, depending on application requirements.

13. Recommended operating conditions

Table 52. Recommended operating conditions

Symbol

V_CC

Parameter

Conditions

Min

3.0

0

Typ

3.6

3.3

-

Max

4.5

Unit

V

supply voltage

V_CC(I/O)

V_I

input/output supply voltage

input voltage

3.6

V

on pins PSW_N, FAULT and V_BUS

5.25

V_CC(I/O)

V

on pins CLOCK, STP, DATA[7:0],

CFG1, CFG2, RESET_N,

0

-

V

CHIP_SEL and CHIP_SEL_N

on pins DP, DM, ID and CFG0

on pin XTAL1

0

-

3.6

V

0

-

1.95

+125

+85

V

T_j

junction temperature

ambient temperature

−40

-

°C

T_amb

+25

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14. Static characteristics

Table 53. Static characteristics: supply pins

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values refer to V_CC= 3.6 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

V_POR(trip)

I_CC

Parameter

power-on reset trip voltage on REG1V8 pin

supply current Power-down mode (V_CC(I/O)is

Conditions

Min

0.95

-

Typ

-

Max

1.5

10

Unit

V

0.5

µA

lost or chip select is

non-active)

full-speed transceiver; bus idle;

no USB activity

-

13

-

mA

full-speed transceiver; 100 %

transmission; no inter-packet

delay

25.65

high-speed transceiver; 100 %

transmission; no inter-packet

delay

-

55.30

-

mA

low-power mode (bit

SUSPENDM is logic 0); V_BUS

valid detector disabled (bits

VBUS_VALID_R and

VBUS_VALID_F are cleared)

for host

-

70

100

330

-

µA

for peripheral

240

750

UART mode; low-speed

transceiver; idle

UART mode; full-speed

transceiver; idle

-

600

-

µA

mA

I_{CC(I/O)(stat)}static supply current on

pin V_CC(I/O)

Power-down mode (chip select

is non-active)

-

10

-

[1]

I_CC(I/O)

supply current on

pin V_CC(I/O)

ULPI bus idle; 15 pF load on

pin CLOCK

2

[1] The actual value of I_CC(I/O)varies depending on the capacitance loading, interface voltage and bus activity. Use the value provided here

only as a reference.

Table 54. Static characteristics: digital pins

Digital pins: CLOCK, DIR, STP, NXT, DATA[7:0], CHIP_SEL_N, CHIP_SEL, CFG1, CFG2 and RESET_N; unless otherwise

speciﬁed.

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values refer to V_CC= 3.6 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Input levels

Conditions

Min

Typ

Max

Unit

V_IH

V_IL

I_LI

HIGH-level input voltage

0.7V_CC(I/O)

-

V

LOW-level input voltage

input leakage current

-

0.3V_CC(I/O)

+1

V

−1

µA

Output levels

V_OH

HIGH-level output voltage

I_OL= +2 mA

V

_CC(I/O)− 0.4 -

-

V

ISP1705_1

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ISP1705

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ULPI Hi-Speed USB transceiver

Table 54. Static characteristics: digital pins …continued

Digital pins: CLOCK, DIR, STP, NXT, DATA[7:0], CHIP_SEL_N, CHIP_SEL, CFG1, CFG2 and RESET_N; unless otherwise

speciﬁed.

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values refer to V_CC= 3.6 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V

V_OL

I_OH

I_OL

LOW-level output voltage

I_OH= −2 mA

-

0.4

HIGH-level output current

LOW-level output current

V_OH= V_CC(I/O)− 0.4 V

V_OL= 0.4 V

8

-

mA

Impedance

Z_L

load impedance

45

-

65

Ω

Pull-up and pull-down

I_pu

pull-up current

interface protect enabled;

STP pin only; V_I= 0 V

−30

−50

−80

µA

UART mode; DATA0 pin only

−30

−50

−80

µA

I_pd

pull-down current

interface protect enabled;

DATA[7:0] pins only;

V_I= V_CC(I/O)

25

50

95

Capacitance

C_ininput capacitance

-

2.9

pF

Table 55. Static characteristics: digital input pin FAULT

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

V_IL

Parameter

Conditions

Min

-

Typ

Max

Unit

V

LOW-level input voltage

HIGH-level input voltage

LOW-level input current

HIGH-level input current

-

0.8

V_IH

2.0

−1

-

V

I_IL

V_I= 0 V

-

µA

I_IH

V_I= 5.25 V

1

Table 56. Static characteristics: digital output pin PSW_N

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

3.0^[1]

-

Typ

Max

5.25

0.4

1

Unit

V

V_OH

V_OL

I_OH

I_OL

HIGH-level output voltage external pull-up resistor connected

-

LOW-level output voltage

HIGH-level output current

LOW-level output current

I_OL= −4 mA

V

external pull-up resistor connected

V_O= 0.4 V

-

µA

mA

4.0

-

[1] When V_OHis less than V_O(REG3V3), I_CCmay increase because of the cross current.

Table 57. Static characteristics: analog pins (DP, DM)

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values refer to V_CC= 3.6 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Original USB transceiver (full speed and low speed)

Input levels (differential data receiver)

V_DI

differential input sensitivity voltage

|V_DP− V_DM

|

0.2

-

V

ISP1705_1

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ULPI Hi-Speed USB transceiver

Table 57. Static characteristics: analog pins (DP, DM) …continued

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values refer to V_CC= 3.6 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_CM

differential common mode voltage

range

includes V_DIrange

0.8

-

2.5

V

Input levels (single-ended receivers)

V_IL

LOW-level input voltage

HIGH-level input voltage

-

0.8

-

V

V_IH

2.0

Output levels

V_OL

LOW-level output voltage

HIGH-level output voltage

output signal crossover voltage

pull-up on DP; R_L= 1.5 kΩ

to 3.6 V

0.0

2.8

1.3

-

0.3

3.6

2.0

V

V_OH

pull-down on pins DP and

DM; R_L= 15 kΩ to GND

V_CRS

excluding the ﬁrst transition

from the idle state

Termination

V_TERM

termination voltage for upstream

facing port pull-up

for 1.5 kΩ pull-up resistor

3.0

-

3.6

V

Resistance

R_UP(DP)

pull-up resistance on pin DP

1425

100

1500

125

1575

150

Ω

R_weakUP(DP)weak pull-up resistance on pin DP

bit DP_WKPU_EN = 1 and

kΩ

V_BUS> V_{A_SESS_VLD}

Hi-Speed USB transceiver (HS)

Input levels

V_HSSQ

high-speed squelch detection

threshold voltage (differential signal

amplitude)

100

525

-

150

625

mV

V_HSDSC

high-speed disconnect detection

threshold voltage (differential signal

amplitude)

V_HSDI

high-speed differential input sensitivity |V_DP− V_DM

|

300

-

mV

V_HSCM

high-speed data signaling common

mode voltage range (guideline for

receiver)

includes V_DIrange

−50

+500

Output levels

V_HSOI

high-speed idle level voltage

−10

-

+10

mV

V_HSOL

high-speed data signaling LOW-level

voltage

V_HSOH

high-speed data signaling HIGH-level

voltage

360

-

440

mV

V_CHIRPJ

V_CHIRPK

Leakage current

Chirp J level (differential voltage)

700

-

1100

mV

Chirp K level (differential voltage)

−900

−500

I_LZ

off-state leakage current

−1.0

-

+1.0

5

µA

Capacitance

C_in

input capacitance

pin to GND

-

pF

ISP1705_1

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Table 57. Static characteristics: analog pins (DP, DM) …continued

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values refer to V_CC= 3.6 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Resistance

R_DN(DP)

pull-down resistance on pin DP

pull-down resistance on pin DM

14.25

15

15.75

kΩ

R_DN(DM)

Termination

Z_O(drv)(DP)

Z_O(drv)(DM)

Z_INP

driver output impedance on pin DP

driver output impedance on pin DM

steady-state drive

40.5

1

45

-

49.5

-

Ω

input impedance exclusive of

MΩ

pull-up/pull-down (for low-/full-speed)

UART mode

Input levels

V_IL

LOW-level input voltage

HIGH-level input voltage

pin DP

-

0.8

-

V

V_IH

2.35

Output levels

V_OL

LOW-level output voltage

HIGH-level output voltage

pin DM; I_OL= −4 mA

-

0.3

-

V

V_OH

pin DM; I_OH= +4 mA

2.4

Table 58. Static characteristics: analog pin V_BUS

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values refer to V_CC= 3.6 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Comparators

V_{A_VBUS_VLD}

V_{A_SESS_VLD}

A-device V_BUSvalid voltage

A-device session valid voltage

4.4

0.8

-

4.75

2.0

-

V

for A-device and B-device

1.6

100

V

V_{hys(A_SESS_VLD)}A-device session valid hysteresis for A-device and B-device

voltage

mV

V_{B_SESS_END}

Resistance

R_UP(VBUS)

B-device session end voltage

0.2

-

0.8

V

pull-up resistance on pin V_BUS

connect to REG3V3 when

CHRG_VBUS = 1

281

656

680

-

Ω

R_DN(VBUS)

pull-down resistance on pin V_BUSconnect to GND when

DISCHRG_VBUS = 1

1200

R_{I(idle)(VBUS)}

idle input resistance on pin V_BUSnot in Power-down mode

75

40

90

-

100

kΩ

chip deasserted

(Power-down mode)

V_CC(I/O)lost (Power-down

mode)

140

-

220

kΩ

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Table 59. Static characteristics: analog pin CFG0

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input levels

V_IL

V_IH

I_LI

LOW-level input voltage

HIGH-level input voltage

input leakage current

-

0.8

-

V

2.0

−1

V

+1

µA

Table 60. Static characteristics: ID detection circuit

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values refer to V_CC= 3.6 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

t_ID

Parameter

Conditions

Min

50

Typ

-

Max

-

Unit

ms

V

ID detection time

V_th(ID)

R_UP(ID)

ID detector threshold voltage

ID pull-up resistance

1.0

40

-

2.0

60

bit ID_PULLUP = 1

bit ID_PULLUP = 0

50

400

3.3

kΩ

V

R_weakPU(ID)weak pull-up resistance on pin ID

V_PU(ID)pull-up voltage on pin ID

320

3.0

480

3.6

Table 61. Static characteristics: resistor reference

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

SUSPENDM = HIGH.

Typical values refer to V_CC= 3.6 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_O(RREF)

output voltage on pin RREF

-

1.22

-

V

Table 62. Static characteristics: regulator

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

SUSPENDM = HIGH.

Typical values refer to V_CC= 3.6 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

1.65

3.0

Typ

1.8

Max

1.95

3.6

Unit

V

V_O(REG1V8)output voltage from internal 1.8 V regulator

V_O(REG3V3)output voltage from internal 3.3 V regulator not in UART mode

in UART mode

3.3

V

2.5

2.77

2.9

V

Table 63. Static characteristics: pin XTAL1

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

V_IL

Parameter

Conditions

Min

-

Typ

Max

0.37

-

Unit

V

LOW-level input voltage

HIGH-level input voltage

-

V_IH

1.32

V

ISP1705_1

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ULPI Hi-Speed USB transceiver

15. Dynamic characteristics

Table 64. Dynamic characteristics: reset and power

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_W(POR)

internal power-on reset

pulse width

0.2

-

µs

t_{w(REG1V8_H)}

t_{w(REG1V8_L)}

t_{W(RESET_N)}

REG1V8 HIGH pulse width

REG1V8 LOW pulse width

-

2

µs

ns

-

11

-

external RESET_N pulse

width

200

t_startup(PLL)

t_{d(det)clk(osc)}

PLL start-up time

measured after t_{d(det)clk(osc)}

-

640

µs

oscillator clock detector

delay

measured from regulator

start-up time

t_PWRUP

regulator start-up time

4.7 µF ± 20 % capacitor

each on the REG1V8 and

REG3V3 pins

-

1

ms

t_PWRDN

regulator power-down time

4.7 µF ± 20 % capacitor

each on the REG1V8 and

REG3V3 pins

100

Table 65. Dynamic characteristics: clock applied to XTAL1

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values refer to V_CC= 3.6 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MHz

ps

f_i(XTAL1)

input frequency on pin XTAL1 see Table 6

-

26.000

24.000

19.300

13.000

-

see Table 6

-

t_{jit(i)(XTAL1)RMS}RMS input jitter on pin XTAL1

200

∆f_i(XTAL1)

input frequency tolerance on

pin XTAL1

-

ppm

[1]

δ_i(XTAL1)

t_r(XTAL1)

t_f(XTAL1)

input duty cycle on pin XTAL1 for the ﬁrst transaction

-

50

-

%

rise time on pin XTAL1

fall time on pin XTAL1

only for square wave input

5

ns

-

[1] The internal PLL is triggered only on the positive edge from the crystal oscillator. Therefore, the duty cycle is not critical.

Table 66. Dynamic characteristics: CLOCK output

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values refer to V_CC= 3.6 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_o(AV)(CLOCK)

average output frequency on

pin CLOCK

59.970

60.000

60.030

MHz

t_{jit(o)(CLOCK)RMS}RMS output jitter on pin CLOCK

-

500

55

ps

%

δ_o(CLOCK)

output clock duty cycle on pin CLOCK

45

50

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ULPI Hi-Speed USB transceiver

Table 67. Dynamic characteristics: digital I/O pins (SDR)

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed. See Figure 30.

Typical values refer to V_CC= 3.6 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

t_su(STP)STP set-up time with respect to

the rising edge of pin CLOCK

input-only pin (STP)

6.0

-

ns

t_su(DATA)DATA set-up time with respect to bidirectional pins (DATA[7:0]) as inputs

the rising edge of pin CLOCK

6.0

-

ns

pF

t_h(STP)

STP hold time with respect to the input-only pin (STP)

rising edge of pin CLOCK

0.0

-

t_h(DATA)DATA hold time with respect to

the rising edge of pin CLOCK

bidirectional pins (DATA[7:0]) as inputs

0.0

-

t_d(DIR)

DIR output delay with respect to output-only pin DIR

-

9.0

20

the rising edge of pin CLOCK

t_d(NXT)

NXT output delay with respect to output-only pin NXT

the rising edge of pin CLOCK

t_d(DATA)DATA output delay with respect to bidirectional pins as output (DATA[7:0])

the rising edge of pin CLOCK

[1]

C_L

load capacitance

pins DATA[7:0], CLOCK, DIR, NXT, STP

[1] Load capacitance on each ULPI pin.

Table 68. Dynamic characteristics: digital I/O pins (DDR)

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed. See Figure 30.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

t_su(STP)

STP set-up time with respect to input-only pin (STP)

the rising edge of pin CLOCK

6.0

-

ns

[1][2]

t_su(DATA)DATA set-up time with respect to bidirectional pins (DATA[3:0]) as inputs

the rising edge of pin CLOCK

4.0

0.0

-

ns

t_h(STP)

t_h(DATA)

t_d(DIR)

t_d(NXT)

t_d(DATA)

C_L

STP hold time with respect to the input-only pin (STP)

rising edge of pin CLOCK

-

[2]

DATA hold time with respect to

the rising edge of pin CLOCK

bidirectional pins (DATA[7:0]) as inputs

-

DIR output delay with respect to output-only pin DIR

the rising edge of pin CLOCK

9.0

4.4

NXT output delay with respect to output-only pin NXT

the rising edge of pin CLOCK

-

[2]

[3]

DATA output delay with respect

to the rising edge of pin CLOCK

bidirectional pins (DATA[3:0]) as output

-

load capacitance

pins DATA[3:0], CLOCK, DIR, NXT, STP

t_d= 4 ns

-

10

15

pF

t_d= 4.4 ns

[1] Note that the value exceeds that speciﬁed in UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

[2] Also with respect to the falling edge of pin CLOCK.

[3] Load capacitance on each ULPI pin.

ISP1705_1

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ULPI Hi-Speed USB transceiver

Table 69. Dynamic characteristics: analog I/O pins (DP, DM) in USB mode

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values refer to V_CC= 3.6 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

High-speed driver characteristics; see Figure 26

t_HSR

t_HSF

rise time (10 % to 90 %)

fall time (10 % to 90 %)

drive 45 Ω to GND on DP and DM

500

-

ps

Full-speed driver characteristics; see Figure 26

t_FR

rise time

fall time

C_L= 50 pF; 10 % to 90 % of |V_OH− V_OL

|

4

-

20

ns

%

t_FF

C_L= 50 pF; 10 % to 90 % of |V_OH− V_OL

4

20

t_FRFM

differential rise and fall time t_FR/ t_FF; excluding the ﬁrst transition from

matching the idle state

90

111.1

Low-speed driver characteristics; see Figure 26

t_LR

transition time: rise time

transition time: fall time

rise and fall time matching

C_L= 200 pF to 600 pF; 1.5 kΩ pull-up on

75

80

-

300

125

ns

%

DM enabled; 10 % to 90 % of |V_OH− V_OL

|

t_LF

C_L= 200 pF to 600 pF; 1.5 kΩ pull-up on

DM enabled; 10 % to 90 % of |V_OH− V_OL

|

t_LRFM

t_LR/ t_LF; excluding the ﬁrst transition from

the idle state

Table 70. Dynamic characteristics: analog I/O pins (DP, DM) in transparent UART mode

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

Full-speed driver characteristics (DM only)

t_r(UART)

t_f(UART)

t_PLH(drv)

rise time for UART TXD

fall time for UART TXD

C_L= 185 pF; 0.37 V to 2.16 V

C_L= 185 pF; 2.16 V to 0.37 V

C_L= 185 pF; DATA0 to DM

25

-

75

39

ns

driver propagation delay

(LOW to HIGH)

t_PHL(drv)

driver propagation delay

(HIGH to LOW)

C_L= 185 pF; DATA0 to DM

-

34

ns

Low-speed driver characteristics (DM only)

t_r(UART)

t_f(UART)

t_PLH(drv)

rise time for UART TXD

fall time for UART TXD

C_L= 185 pF; 0.37 V to 2.16 V

C_L= 185 pF; 2.16 V to 0.37 V

C_L= 185 pF; DATA0 to DM

100

-

400

614

ns

driver propagation delay

(LOW to HIGH)

t_PHL(drv)

driver propagation delay

(HIGH to LOW)

C_L= 185 pF; DATA0 to DM

-

614

ns

Full-speed receiver characteristics (DP only)

t_PLH(rcv)

receiver propagation delay

(LOW to HIGH)

DP to DATA1

-

7

ns

t_PHL(rcv)

receiver propagation delay

(HIGH to LOW)

DP to DATA1

Low-speed receiver characteristics (DP only)

t_PLH(rcv)

receiver propagation delay

(LOW to HIGH)

DP to DATA1

-

7

ns

t_PHL(rcv)

receiver propagation delay

(HIGH to LOW)

DP to DATA1

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Table 71. Dynamic characteristics: analog I/O pins (DP, DM) in serial mode

V_CC= 3.0 V to 4.5 V; V_CC(I/O)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Driver timing (valid only for serial mode)

t_PLH(drv)driver propagation delay (LOW to

HIGH)

TX_DAT, TX_SE0 to DP, DM;

see Figure 27

-

11

ns

t_PHL(drv)driver propagation delay (HIGH to

LOW)

TX_DAT, TX_SE0 to DP, DM;

see Figure 27

t_PHZ

t_PLZ

t_PZH

t_PZL

driver disable delay from HIGH level TX_ENABLE to DP, DM; see Figure 28

driver disable delay from LOW level TX_ENABLE to DP, DM; see Figure 28

-

12

20

ns

driver enable delay to HIGH level

driver enable delay to LOW level

TX_ENABLE to DP, DM; see Figure 28

Receiver timing (valid only for serial mode)

Differential receiver

t_PLH(rcv)receiver propagation delay (LOW to DP, DM to RX_RCV, RX_DP and RX_DM;

HIGH) see Figure 29

-

17

ns

t_PHL(rcv)receiver propagation delay (HIGH to DP, DM to RX_RCV, RX_DP and RX_DM;

LOW)

see Figure 29

Single-ended receiver

t_PLH(se)single-ended propagation delay

(LOW to HIGH)

DP, DM to RX_RCV, RX_DP and RX_DM;

see Figure 29

-

17

ns

t_PHL(se)single-ended propagation delay

(HIGH to LOW)

DP, DM to RX_RCV, RX_DP and RX_DM;

see Figure 29

1.8 V

0.9 V

logic input 0.9 V

t

, t , t

HSF FF LF

t

, t , t

HSR FR LR

0 V

V

t

PHL(drv)

OH

PLH(drv)

90 %

V

OH

differential

data lines

V

CRS

10 %

V

OL

V

OL

004aaa861

004aaa573

Fig 26. Rise time and fall time

Fig 27. Timing of TX_DAT and TX_SE0 to DP and DM

2.0 V

1.8 V

differential

data lines

V

CRS

logic

input

0.9 V

0.8 V

0 V

t

PHL(rcv)

PLH(rcv)

PLH(se)

t

PHZ

PZH

t

PHL(se)

t

PLZ

PZL

V

OH

V

OH

V

− 0.3 V

OH

0.9 V

logic output

differential

data lines

V

CRS

V

+ 0.3 V

OL

V

OL

V

004aaa574

001aai187

OL

Fig 28. Timing of TX_ENABLE to DP and DM

Fig 29. Timing of DP and DM to RX_RCV, RX_DP and

RX_DM

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CLOCK

t

su(STP) h(STP)

CONTROL IN

(STP)

t

su(DATA)

h(DATA)

DATA IN

(8-BIT)

t

,

d(DIR)

t

d(NXT)

CONTROL OUT

(DIR, NXT)

t

,

d(DIR)

t

d(NXT)

d(DATA)

DATA OUT

(8-BIT)

004aaa722

Fig 30. ULPI timing interface

16. Application information

Table 72. Recommended bill of materials

Designator Application

Part type

Remark

C_bypass

highly recommended for all

applications

0.1 µF ± 20 %

-

C_ﬁlter

highly recommended for all

applications

4.7 µF ± 20 %

use a LOW ESR capacitor (0.2 Ω to 2 Ω) for best

performance

C_VBUS

mandatory for peripherals

mandatory for host

mandatory for OTG

in all applications

1 µF to 10 µF

120 µF (min)

1 µF to 6.5 µF

18 pF ± 20 %

-

use low ESR capacitor

-

C_XTAL

D_ESD

recommended to prevent

damages from ESD

IP4359CX4/LF; Wafer-Level Chip-Scale Package

(WLCSP); ESD IEC 61000-4-2 level 4; ±15 kV contact;

±15 kV air discharge compliant protection.

Note: ISP1705 and IP4359CX4/LF together have an IEC

61000-4-2 contact discharge tolerance of ±20 kV.

R_RREF

mandatory in all applications

12 kΩ ± 1 %

-

R_S(VBUS)

recommended for peripherals 1 kΩ ± 5 %

or external 5 V applications

R_pullup

recommended; for applications 10 kΩ

with an external V_BUSsupply

controlled by PSW_N

-

xtal

mandatory in all applications

19.2 MHz

24 MHz

C_L= 10 pF; R_S< 220 Ω; C_XTAL= 18 pF

C_L= 10 pF; R_S< 160 Ω; C_XTAL= 18 pF

ISP1705_1

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ULPI Hi-Speed USB transceiver

17. Package outline

HVQFN36: plastic thermal enhanced very thin quad flat package; no leads;

36 terminals; body 5 x 5 x 0.85 mm

SOT818-1

D

B

A

terminal 1

index area

A

E

A

1

c

detail X

C

y

e

1

y

v

M

C

A B

1 C

e

b

w

M

10

18

L

19

9

e

2

E

h

1

27

terminal 1

index area

36

28

X

D

h

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

D

E

e

1

e

2

L

v

w

y

1

h

max

0.05 0.30

0.00 0.18

5.1

4.9

3.75

3.45

5.1

4.9

3.75

3.45

0.5

0.3

mm

1

0.2

0.4

3.2

0.1

0.05 0.05

0.1

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

- - -

SOT818-1

- - -

03-06-13

MO-220

Fig 34. Package outline SOT818-1 (HVQFN36)

ISP1705_1

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TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm

SOT912-1

D

B

A

E

ball A1

index area

A

2

A

1

detail X

e

1

1/2 e

e

C

y

M

v

C A

C

B

b

y

w

C

1

F

E

D

C

B

A

e

2

1/2 e

ball A1

index area

1

2

3

4

5

6

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

2

v

w

y

1

max

0.25 0.90 0.35

0.15 0.75 0.25

3.6

3.4

3.6

3.4

mm

1.15

0.5

2.5

0.15 0.05 0.08

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

05-08-09

05-09-01

- - -

SOT912-1

Fig 35. Package outline SOT912-1 (TFBGA36)

ISP1705_1

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18. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

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18.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 36) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 73 and 74

Table 73. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 74. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 36.

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 36. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

19. Abbreviations

Table 75. Abbreviations

Acronym

ASIC

ATX

Description

Application Speciﬁc Integrated Circuit

Analog USB Transceiver

Charged Device Model

Compact Disc - Digital Video Disc

Compact Disc - Read-Only Memory

Compact Disc - ReWritable

Dual Data Rate

CDM

CD-DVD

CD-ROM

CD-RW

DDR

EMI

ElectroMagnetic Interference

End-Of-Packet

EOP

ESD

ElectroStatic Discharge

Effective Series Resistance

Field Programmable Gate-Array

Full Speed

ESR

FPGA

FS

HBM

HNP

HS

Human Body Model

Host Negotiation Protocol

High Speed

ID

Identiﬁcation

IEC

International Electrotechnical Commission

Low Speed

LS

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ULPI Hi-Speed USB transceiver

Table 75. Abbreviations …continued

Acronym

Description

MM

Machine Model

NRZI

OTG

Non-Return to Zero Inverted

On-The-Go

PDA

Personal Digital Assistant

Physical

PHY

PID

Packet Identiﬁer

PLL

Phase-Locked Loop

Power-On Reset

POR

RoHS

RXCMD

RXD

Restriction of Hazardous Substances

Receive Command

Receive Data

SDR

Single Data Rate

Single-Ended Zero

System-On-Chip

SE0

SOC

SOF

Start-Of-Frame

SRP

Session Request Protocol

Synchronous

SYNC

TTL

Transistor-Transistor Logic

Transmit Command

Transmit Data

TXCMD

TXD

UART

ULPI

USB

Universal Asynchronous Receiver-Transmitter

UTMI+ Low Pin Interface

Universal Serial Bus

USB-IF

UTMI

UTMI+

WLCSP

USB Implementers Forum

USB Transceiver Macrocell Interface

USB Transceiver Macrocell Interface Plus

Wafer-Level Chip-Scale Package

20. Glossary

A-device — An OTG device with an attached micro-A plug.

B-device — An OTG device with an attached micro-B plug.

Link — ASIC, SOC or FPGA that contains the USB host or peripheral core.

PHY — Physical layer containing the USB transceiver.

21. References

[1] Universal Serial Bus Speciﬁcation Rev. 2.0

[2] On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.3

[3] UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

ISP1705_1

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ULPI Hi-Speed USB transceiver

[4] UTMI+ Speciﬁcation Rev. 1.0

[5] USB 2.0 Transceiver Macrocell Interface (UTMI) Speciﬁcation Ver. 1.05

[6] Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)

(JESD22-A114D)

[7] Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)

(JESD22-A115-A)

[8] Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

(JESD22-C101-C)

[9] Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement

techniques - Electrostatic discharge immunity test (IEC 61000-4-2)

22. Revision history

Table 76. Revision history

Document ID

Release date

20080613

Data sheet status

Change notice

Supersedes

ISP1705_1

Product data sheet

-

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23. Legal information

23.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

23.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

23.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

23.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

24. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

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25. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 2. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3

Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 4. Recommended V_BUScapacitor value . . . . . . .18

Table 5. OTG_CTRL register power control bits . . . . . .19

Table 6. Allowed crystal or clock frequency on the

XTAL1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 7. External capacitor values for 13 MHz or

19.2 MHz clock frequency . . . . . . . . . . . . . . . .20

Table 8. External capacitor values for 24 MHz or

26 MHz clock frequency . . . . . . . . . . . . . . . . .20

Table 9. Pin states in Power-down mode . . . . . . . . . . .22

Table 10. ULPI signal description . . . . . . . . . . . . . . . . . .23

Table 11. Signal mapping during low-power mode . . . . .24

Table 12. Signal mapping for 6-pin serial mode . . . . . . .25

Table 13. Signal mapping for 3-pin serial mode . . . . . . .26

Table 14. UART signal mapping . . . . . . . . . . . . . . . . . . .26

Table 15. Operating states and their corresponding

resistor settings . . . . . . . . . . . . . . . . . . . . . . . .29

Table 16. TXCMD byte format . . . . . . . . . . . . . . . . . . . . .31

Table 17. RXCMD byte format . . . . . . . . . . . . . . . . . . . . .32

Table 18. LINESTATE[1:0] encoding for upstream

facing ports: peripheral . . . . . . . . . . . . . . . . . .33

Table 19. LINESTATE[1:0] encoding for downstream

facing ports: host . . . . . . . . . . . . . . . . . . . . . . .33

Table 20. Encoded V_BUSvoltage state . . . . . . . . . . . . . .33

Table 21. V_BUSindicators in RXCMD required for

typical applications . . . . . . . . . . . . . . . . . . . . . .34

Table 22. Encoded USB event signals . . . . . . . . . . . . . .35

Table 23. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .39

Table 24. Link decision times . . . . . . . . . . . . . . . . . . . . .40

Table 25. Register map . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 26. VENDOR_ID_LOW - Vendor ID low register

(address R = 00h) bit description . . . . . . . . . . .52

Table 27. VENDOR_ID_HIGH - Vendor ID high

C = 09h) bit allocation . . . . . . . . . . . . . . . . . . . 55

Table 33. INTF_CTRL - Interface control register

(address R = 07h to 09h, W = 07h, S = 08h,

C = 09h) bit description . . . . . . . . . . . . . . . . . . 55

Table 34. OTG_CTRL - OTG control register

(address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh,

C = 0Ch) bit allocation . . . . . . . . . . . . . . . . . . . 56

Table 35. OTG_CTRL - OTG control register

(address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh,

C = 0Ch) bit description . . . . . . . . . . . . . . . . . 57

Table 36. USB_INTR_EN_R - USB interrupt enable

rising register (address R = 0Dh to 0Fh,

W = 0Dh, S = 0Eh, C = 0Fh) bit allocation . . . 58

Table 37. USB_INTR_EN_R - USB interrupt enable

rising register (address R = 0Dh to 0Fh,

W = 0Dh, S = 0Eh, C = 0Fh) bit description . . 58

Table 38. USB_INTR_EN_F - USB interrupt enable

falling register (address R = 10h to 12h,

W = 10h, S = 11h, C = 12h) bit allocation . . . . 58

Table 39. USB_INTR_EN_F - USB interrupt enable

falling register (address R = 10h to 12h,

W = 10h, S = 11h, C = 12h) bit description . . . 59

Table 40. USB_INTR_STAT - USB interrupt status

register (address R = 13h) bit allocation . . . . . 59

Table 41. USB_INTR_STAT - USB interrupt status

register (address R = 13h) bit description . . . . 59

Table 42. USB_INTR_L - USB interrupt latch

register (address R = 14h) bit allocation . . . . . 60

Table 43. USB_INTR_L - USB interrupt latch

register (address R = 14h) bit description . . . . 60

Table 44. DEBUG - Debug register (address R = 15h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 45. DEBUG - Debug register (address R = 15h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 46. SCRATCH - Scratch register (address

R = 16h to 18h, W = 16h, S = 17h, C = 18h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 47. CARKIT_CTRL - Carkit control register

(address R = 19h to 1Bh, W = 19h, S = 1Ah,

C = 1Bh) bit allocation . . . . . . . . . . . . . . . . . . . 61

Table 48. CARKIT_CTRL - Carkit control register

(address R = 19h to 1Bh, W = 19h, S = 1Ah,

C = 1Bh) bit description . . . . . . . . . . . . . . . . . . 61

Table 49. PWR_CTRL - Power control register

(address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,

C = 3Fh) bit allocation . . . . . . . . . . . . . . . . . . . 62

Table 50. PWR_CTRL - Power control register

(address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,

register (address R = 01h) bit description . . . .52

Table 28. PRODUCT_ID_LOW - Product ID low

register (address R = 02h) bit description . . . .53

Table 29. PRODUCT_ID_HIGH - Product ID high

register (address R = 03h) bit description . . . .53

Table 30. FUNC_CTRL - Function control register

(address R = 04h to 06h, W = 04h, S = 05h,

C = 06h) bit allocation . . . . . . . . . . . . . . . . . . .53

Table 31. FUNC_CTRL - Function control register

(address R = 04h to 06h, W = 04h, S = 05h,

C = 06h) bit description . . . . . . . . . . . . . . . . . .53

Table 32. INTF_CTRL - Interface control register

(address R = 07h to 09h, W = 07h, S = 08h,

continued >>

ISP1705_1

Product data sheet

Rev. 01 — 13 June 2008

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ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

C = 3Fh) bit description . . . . . . . . . . . . . . . . . .62

Table 51. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .63

Table 52. Recommended operating conditions . . . . . . . .63

Table 53. Static characteristics: supply pins . . . . . . . . . .64

Table 54. Static characteristics: digital pins . . . . . . . . . . .64

Table 55. Static characteristics: digital input pin

FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 56. Static characteristics: digital output pin

PSW_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 57. Static characteristics: analog pins (DP, DM) . .65

Table 58. Static characteristics: analog pin V_BUS. . . . . .67

Table 59. Static characteristics: analog pin CFG0 . . . . . .68

Table 60. Static characteristics: ID detection circuit . . . .68

Table 61. Static characteristics: resistor reference . . . . .68

Table 62. Static characteristics: regulator . . . . . . . . . . . .68

Table 63. Static characteristics: pin XTAL1 . . . . . . . . . . .68

Table 64. Dynamic characteristics: reset and power . . . .69

Table 65. Dynamic characteristics: clock applied to

XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 66. Dynamic characteristics: CLOCK output . . . . .69

Table 67. Dynamic characteristics: digital I/O pins

(SDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 68. Dynamic characteristics: digital I/O pins

(DDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 69. Dynamic characteristics: analog I/O pins

(DP, DM) in USB mode . . . . . . . . . . . . . . . . . .71

Table 70. Dynamic characteristics: analog I/O pins

(DP, DM) in transparent UART mode . . . . . . . .71

Table 71. Dynamic characteristics: analog I/O pins

(DP, DM) in serial mode . . . . . . . . . . . . . . . . . .72

Table 72. Recommended bill of materials . . . . . . . . . . . .73

Table 73. SnPb eutectic process (from J-STD-020C) . . .80

Table 74. Lead-free process (from J-STD-020C) . . . . . .80

Table 75. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 76. Revision history . . . . . . . . . . . . . . . . . . . . . . . .83

ISP1705_1

Product data sheet

Rev. 01 — 13 June 2008

86 of 89

ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

26. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 2. Pin conﬁguration HVQFN36. . . . . . . . . . . . . . . . . .5

Fig 3. Pin conﬁguration TFBGA36 . . . . . . . . . . . . . . . . . .5

Fig 4. Digital overcurrent detection scheme. . . . . . . . . .12

Fig 5. Internal power-on reset timing . . . . . . . . . . . . . . .13

Fig 6. Power-up and reset sequence required before

the ULPI bus is ready for use. . . . . . . . . . . . . . . .14

Fig 7. Interface behavior with respect to RESET_N. . . .15

Fig 8. Interface behavior with respect to chip select . . .16

Fig 9.

V_BUSpin internal pull-up and pull-down scheme .19

Fig 10. Interface behavior when entering UART mode . .28

Fig 11. Interface behavior when exiting UART mode. . . .28

Fig 12. Single and back-to-back RXCMDs from the

ISP1705 to the link. . . . . . . . . . . . . . . . . . . . . . . .32

Fig 13. RXCMD A_VBUS_VLD indicator source . . . . . . .34

Fig 14. Example of register write, register read,

extended register write and extended

register read. . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Fig 15. USB reset and high-speed detection

handshake (chirp) sequence . . . . . . . . . . . . . . . .38

Fig 16. Example of using the ISP1705 to transmit and

receive USB data. . . . . . . . . . . . . . . . . . . . . . . . .39

Fig 17. High-speed transmit-to-transmit packet timing. . .40

Fig 18. High-speed receive-to-transmit packet timing . . .41

Fig 19. Preamble sequence. . . . . . . . . . . . . . . . . . . . . . .42

Fig 20. Full speed suspend and resume . . . . . . . . . . . . .43

Fig 21. High speed suspend and resume . . . . . . . . . . . .45

Fig 22. Remote wake-up from low-power mode . . . . . . .47

Fig 23. Transmitting USB packets without automatic

SYNC and EOP generation . . . . . . . . . . . . . . . . .48

Fig 24. Example of transmit followed by receive

in 6-pin serial mode . . . . . . . . . . . . . . . . . . . . . . .50

Fig 25. Example of transmit followed by receive

in 3-pin serial mode . . . . . . . . . . . . . . . . . . . . . . .50

Fig 26. Rise time and fall time . . . . . . . . . . . . . . . . . . . . .72

Fig 27. Timing of TX_DAT and TX_SE0 to DP and DM. .72

Fig 28. Timing of TX_ENABLE to DP and DM. . . . . . . . .72

Fig 29. Timing of DP and DM to RX_RCV, RX_DP

and RX_DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Fig 30. ULPI timing interface . . . . . . . . . . . . . . . . . . . . . .73

Fig 31. ISP1705 in peripheral-only application . . . . . . . .74

Fig 32. ISP1705 in OTG application . . . . . . . . . . . . . . . .75

Fig 33. ISP1705 in host application . . . . . . . . . . . . . . . . .76

Fig 34. Package outline SOT818-1 (HVQFN36) . . . . . . .77

Fig 35. Package outline SOT912-1 (TFBGA36). . . . . . . .78

Fig 36. Temperature proﬁles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

ISP1705_1

Product data sheet

Rev. 01 — 13 June 2008

87 of 89

ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

27. Contents

1

2

3

4

5

6

General description . . . . . . . . . . . . . . . . . . . . . . 1

8.12.15 STP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.12.16 NXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.12.17 CLOCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.12.18 CFG1, CFG2 . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.12.19 CHIP_SEL, CHIP_SEL_N . . . . . . . . . . . . . . . 21

8.12.20 GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

9

9.1

Modes of operation . . . . . . . . . . . . . . . . . . . . . 22

Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 22

Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 22

Power-down mode . . . . . . . . . . . . . . . . . . . . . 22

ULPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Synchronous mode . . . . . . . . . . . . . . . . . . . . 23

Low-power mode . . . . . . . . . . . . . . . . . . . . . . 24

6-pin full-speed or low-speed serial mode . . . 25

3-pin full-speed or low-speed serial mode . . . 25

Transparent UART mode . . . . . . . . . . . . . . . . 26

USB state transitions . . . . . . . . . . . . . . . . . . . 29

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

9.1.1

9.1.2

9.2

9.2.1

9.2.2

9.2.3

9.2.4

9.2.5

9.3

8

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.7.1

8.7.2

8.7.2.1

8.7.2.2

8.7.2.3

8.7.3

8.8

Functional description . . . . . . . . . . . . . . . . . . . 9

ULPI interface controller . . . . . . . . . . . . . . . . . . 9

USB serializer and deserializer. . . . . . . . . . . . . 9

Hi-Speed USB (USB 2.0) ATX . . . . . . . . . . . . . 9

Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . 10

Crystal oscillator and PLL. . . . . . . . . . . . . . . . 10

UART buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 10

OTG module . . . . . . . . . . . . . . . . . . . . . . . . . . 11

ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

V_BUScomparators. . . . . . . . . . . . . . . . . . . . . . 11

10

10.1

10.2

10.3

10.3.1

10.3.2

10.3.3

Protocol description . . . . . . . . . . . . . . . . . . . . 31

ULPI references . . . . . . . . . . . . . . . . . . . . . . . 31

TXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

RXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Linestate encoding. . . . . . . . . . . . . . . . . . . . . 32

V_BUSvalid comparator . . . . . . . . . . . . . . . . . . 11

Session valid comparator . . . . . . . . . . . . . . . . 11

Session end comparator. . . . . . . . . . . . . . . . . 11

SRP charge and discharge resistors . . . . . . . 12

Port power control. . . . . . . . . . . . . . . . . . . . . . 12

Band gap reference voltage . . . . . . . . . . . . . . 12

Power-On Reset (POR) . . . . . . . . . . . . . . . . . 12

Power-up, reset and bus idle sequence . . . . . 13

Interface protection. . . . . . . . . . . . . . . . . . . . . 15

Interface behavior with respect to

V_BUSstate encoding. . . . . . . . . . . . . . . . . . . . 33

Using and selecting the V_BUSstate encoding. 34

10.3.3.1 Standard USB host controllers. . . . . . . . . . . . 34

10.3.3.2 Standard USB peripheral controllers . . . . . . . 35

10.3.3.3 OTG devices . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.9

8.10

8.11

8.11.1

8.11.2

10.3.4

RxEvent encoding . . . . . . . . . . . . . . . . . . . . . 35

10.3.4.1 RxActive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

10.3.4.2 RxError. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.3.4.3 HostDisconnect . . . . . . . . . . . . . . . . . . . . . . . 36

RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Interface behavior with respect to

8.11.3

10.4

10.5

Register read and write operations . . . . . . . . 36

USB reset and high-speed detection

chip select. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Detailed description of pins . . . . . . . . . . . . . . 16

DATA[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

V_CC(I/O). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

RREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CFG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.12

handshake (chirp) . . . . . . . . . . . . . . . . . . . . . 36

USB packet transmit and receive . . . . . . . . . . 39

USB packet timing . . . . . . . . . . . . . . . . . . . . . 39

8.12.1

8.12.2

8.12.3

8.12.4

8.12.5

8.12.6

8.12.7

8.12.8

8.12.9

10.6

10.6.1

10.6.1.1 ISP1705 pipeline delays. . . . . . . . . . . . . . . . . 39

10.6.1.2 Allowed link decision time . . . . . . . . . . . . . . . 39

10.7

10.8

10.8.1

Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

USB suspend and resume . . . . . . . . . . . . . . . 42

Full-speed or low-speed host-initiated

V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

REG3V3 and REG1V8 . . . . . . . . . . . . . . . . . . 18

suspend and resume . . . . . . . . . . . . . . . . . . . 42

High speed suspend and resume . . . . . . . . . 43

Remote wake-up . . . . . . . . . . . . . . . . . . . . . . 46

No automatic SYNC and EOP generation

10.8.2

10.8.3

10.9

8.12.10 V_BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.12.11 PSW_N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.12.12 XTAL1 and XTAL2. . . . . . . . . . . . . . . . . . . . . . 19

8.12.13 DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.12.14 RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

(optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

On-The-Go operations . . . . . . . . . . . . . . . . . . 48

10.10

continued >>

ISP1705_1

Product data sheet

Rev. 01 — 13 June 2008

88 of 89

ISP1705

NXP Semiconductors

ULPI Hi-Speed USB transceiver

10.10.1 OTG comparators . . . . . . . . . . . . . . . . . . . . . . 49

10.10.2 Pull-up and pull-down resistors. . . . . . . . . . . . 49

10.10.3 ID detection. . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.10.4

10.11

10.12

10.13

V_BUScharge and discharge resistors . . . . . . . 49

Serial modes. . . . . . . . . . . . . . . . . . . . . . . . . . 49

Aborting transfers . . . . . . . . . . . . . . . . . . . . . . 51

Avoiding contention on the ULPI data bus . . . 51

11

Register map . . . . . . . . . . . . . . . . . . . . . . . . . . 52

VENDOR_ID_LOW register . . . . . . . . . . . . . . 52

VENDOR_ID_HIGH register. . . . . . . . . . . . . . 52

PRODUCT_ID_LOW register . . . . . . . . . . . . . 53

PRODUCT_ID_HIGH register . . . . . . . . . . . . 53

FUNC_CTRL register . . . . . . . . . . . . . . . . . . . 53

INTF_CTRL register . . . . . . . . . . . . . . . . . . . . 55

OTG_CTRL register . . . . . . . . . . . . . . . . . . . . 56

USB_INTR_EN_R register . . . . . . . . . . . . . . . 58

USB_INTR_EN_F register . . . . . . . . . . . . . . . 58

USB_INTR_STAT register. . . . . . . . . . . . . . . . 59

USB_INTR_L register. . . . . . . . . . . . . . . . . . . 59

DEBUG register . . . . . . . . . . . . . . . . . . . . . . . 60

SCRATCH register . . . . . . . . . . . . . . . . . . . . . 61

CARKIT_CTRL register . . . . . . . . . . . . . . . . . 61

PWR_CTRL register. . . . . . . . . . . . . . . . . . . . 62

11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

11.9

11.10

11.11

11.12

11.13

11.14

11.15

12

13

14

15

16

17

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 63

Recommended operating conditions. . . . . . . 63

Static characteristics. . . . . . . . . . . . . . . . . . . . 64

Dynamic characteristics . . . . . . . . . . . . . . . . . 69

Application information. . . . . . . . . . . . . . . . . . 73

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 77

18

Soldering of SMD packages . . . . . . . . . . . . . . 79

Introduction to soldering . . . . . . . . . . . . . . . . . 79

Wave and reﬂow soldering . . . . . . . . . . . . . . . 79

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 79

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 80

18.1

18.2

18.3

18.4

19

20

21

22

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 81

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 83

23

Legal information. . . . . . . . . . . . . . . . . . . . . . . 84

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 84

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 84

23.1

23.2

23.3

23.4

24

25

26

27

Contact information. . . . . . . . . . . . . . . . . . . . . 84

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 June 2008

Document identifier: ISP1705_1


型号：	ISP1705AET,118
厂家：	NXP
描述：	IC UNIVERSAL SERIAL BUS CONTROLLER, PBGA36, 3.5 X 3.5 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, PLASTIC, SOT912-1, TFBGA-36, Bus Controller 时钟外围集成电路
文件：	总89页 (文件大小：437K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISP1705AET,118 [NXP]

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