KMPC860TZQ50D4 [NXP]
32-BIT, 50MHz, RISC PROCESSOR, PBGA357, 25 X 25 MM, 1.27 MM PITCH, PLASTIC, BGA-357;型号: | KMPC860TZQ50D4 |
厂家: | NXP |
描述: | 32-BIT, 50MHz, RISC PROCESSOR, PBGA357, 25 X 25 MM, 1.27 MM PITCH, PLASTIC, BGA-357 时钟 外围集成电路 |
文件: | 总81页 (文件大小:1090K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MPC860EC
Rev. 8, 08/2007
Freescale Semiconductor
Technical Data
MPC860 PowerQUICC™ Family
Hardware Specifications
Contents
This hardware specification contains detailed information on
power considerations, DC/AC electrical characteristics, and
AC timing specifications for the MPC860 family.
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 7
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7. Thermal Calculation and Measurement . . . . . . . . . . 12
8. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 41
11. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 43
12. UTOPIA AC Electrical Specifications . . . . . . . . . . . 65
13. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 67
14. Mechanical Data and Ordering Information . . . . . . . 70
15. Document Revision History . . . . . . . . . . . . . . . . . . . 76
To locate published errata or updates for this document, refer
to the MPC860 product summary page on our website listed
on the back cover of this document or, contact your local
Freescale sales office.
© Freescale Semiconductor, Inc., 2001–2007. All rights reserved.
Overview
1 Overview
The MPC860 power quad integrated communications controller (PowerQUICC™) is a versatile one-chip
integrated microprocessor and peripheral combination designed for a variety of controller applications. It
particularly excels in communications and networking systems. The PowerQUICC unit is referred to as
the MPC860 in this hardware specification.
The MPC860 implements Power Architecture™ technology and contains a superset of Freescale’s
MC68360 quad integrated communications controller (QUICC), referred to here as the QUICC, RISC
communications proccessor module (CPM). The CPU on the MPC860 is a 32-bit core built on Power
Architecture technology that incorporates memory management units (MMUs) and instruction and data
caches.. The CPM from the MC68360 QUICC has been enhanced by the addition of the inter-integrated
2
controller (I C) channel. The memory controller has been enhanced, enabling the MPC860 to support any
type of memory, including high-performance memories and new types of DRAMs. A PCMCIA socket
controller supports up to two sockets. A real-time clock has also been integrated.
Table 1 shows the functionality supported by the MPC860 family.
Table 1. MPC860 Family Functionality
Cache (Kbytes)
Ethernet
1
Part
ATM
SCC
Reference
Instruction
Cache
Data Cache
10T
10/100
MPC860DE
MPC860DT
MPC860DP
MPC860EN
MPC860SR
MPC860T
4
4
4
4
8
4
4
4
8
4
Up to 2
Up to 2
Up to 2
Up to 4
Up to 4
Up to 4
Up to 4
1
—
1
—
2
2
2
4
4
4
4
1
1
1
1
1
1
1
1
2
Yes
Yes
—
16
4
1
—
—
1
4
Yes
Yes
Yes
Yes
4
MPC860P
MPC855T
16
4
1
1
1
Supporting documentation for these devices refers to the following:
1. MPC860 PowerQUICC Family User’s Manual (MPC860UM, Rev. 3)
2. MPC855T User’s Manual (MPC855TUM, Rev. 1)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
2
Freescale Semiconductor
Features
2 Features
The following list summarizes the key MPC860 features:
•
Embedded single-issue, 32-bit core (implementing the Power Architecture technology) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch without conditional execution.
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)
– 16-Kbyte instruction caches are four-way, set-associative with 256 sets; 4-Kbyte instruction
caches are two-way, set-associative with 128 sets.
– 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are
two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully-associative instruction, and data TLBs
— MMUs support multiple page sizes of 4-, 16-, and 512-Kbytes, and 8-Mbytes; 16 virtual
address spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
•
•
•
•
Operates at up to 80 MHz
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank.
— Up to 15 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and other memory
devices
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbytes to 256 Mbytes)
— Selectable write protection
— On-chip bus arbitration logic
•
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture.
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
3
Features
•
System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC)
— Reset controller
— IEEE 1149.1™ Std. test access port (JTAG)
Interrupts
•
— Seven external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
•
•
10/100 Mbps Ethernet support, fully compliant with the IEEE 802.3u® Standard (not available
when using ATM over UTOPIA interface)
ATM support compliant with ATM forum UNI 4.0 specification
— Cell processing up to 50–70 Mbps at 50-MHz system clock
— Cell multiplexing/demultiplexing
— Support of AAL5 and AAL0 protocols on a per-VC basis. AAL0 support enables OAM and
software implementation of other protocols.
— ATM pace control (APC) scheduler, providing direct support for constant bit rate (CBR) and
unspecified bit rate (UBR) and providing control mechanisms enabling software support of
available bit rate (ABR)
— Physical interface support for UTOPIA (10/100-Mbps is not supported with this interface) and
byte-aligned serial (for example, T1/E1/ADSL)
— UTOPIA-mode ATM supports level-1 master with cell-level handshake, multi-PHY (up to four
physical layer devices), connection to 25-, 51-, or 155-Mbps framers, and UTOPIA/system
clock ratios of 1/2 or 1/3.
— Serial-mode ATM connection supports transmission convergence (TC) function for
T1/E1/ADSL lines, cell delineation, cell payload scrambling/descrambling, automatic
idle/unassigned cell insertion/stripping, header error control (HEC) generation, checking, and
statistics.
•
Communications processor module (CPM)
— RISC communications processor (CP)
— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT
MODE, and RESTART TRANSMIT)
— Supports continuous mode transmission and reception on all serial channels
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
4
Freescale Semiconductor
Features
— Up to 8 Kbytes of dual-port RAM
— 16 serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
Four baud-rate generators (BRGs)
•
•
— Independent (can be tied to any SCC or SMC)
— Allows changes during operation
— Autobaud support option
Four serial communications controllers (SCCs)
— Ethernet/IEEE 802.3® standard optional on SCC1–4, supporting full 10-Mbps operation
(available only on specially programmed devices)
— HDLC/SDLC (all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support point-to-point protocol (PPP)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame-based with optional cyclic redundancy check (CRC))
Two SMCs (serial management channels)
— UART
•
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channels
One SPI (serial peripheral interface)
•
•
•
— Supports master and slave modes
— Supports multimaster operation on the same bus
2
One I C (inter-integrated circuit) port
— Supports master and slave modes
— Multiple-master environment support
Time-slot assigner (TSA)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, and clocking
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
5
Features
— Allows dynamic changes
— Can be internally connected to six serial channels (four SCCs and two SMCs)
Parallel interface port (PIP)
•
•
— Centronics interface support
— Supports fast connection between compatible ports on the MPC860 or the MC68360
PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports two independent PCMCIA sockets
— Supports eight memory or I/O windows
Low power support
•
— Full on—all units fully powered
— Doze—core functional units disabled except time base decrementer, PLL, memory controller,
RTC, and CPM in low-power standby
— Sleep—all units disabled except RTC and PIT, PLL active for fast wake up
— Deep sleep—all units disabled including PLL except RTC and PIT
— Power down mode—all units powered down except PLL, RTC, PIT, time base, and
decrementer
•
Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports conditions: = ≠ < >
— Each watchpoint can generate a break-point internally.
3.3-V operation with 5-V TTL compatibility except EXTAL and EXTCLK
357-pin ball grid array (BGA) package
•
•
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
6
Freescale Semiconductor
Maximum Tolerated Ratings
3 Maximum Tolerated Ratings
This section provides the maximum tolerated voltage and temperature ranges for the MPC860. Table 2
provides the maximum ratings.
This device contains circuitry protecting against damage due to high-static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for example, either GND or V ).
DD
Table 2. Maximum Tolerated Ratings
(GND = 0 V)
Rating
Symbol
Value
Unit
1
Supply voltage
V
–0.3 to 4.0
–0.3 to 4.0
–0.3 to 4.0
–0.3 to 4.0
GND – 0.3 to V
0
V
V
DDH
V
DDL
KAPWR
V
V
V
DDSYN
2
Input voltage
V
V
in
DDH
3
Temperature (standard)
T
°C
°C
°C
°C
°C
A(min)
T
95
j(max)
3
Temperature (extended)
T
–40
A(min)
T
95
j(max)
Storage temperature range
T
–55 to 150
stg
1
2
The power supply of the device must start its ramp from 0.0 V.
Functional operating conditions are provided with the DC electrical specifications in Table 6. Absolute maximum ratings are
stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device
reliability or cause permanent damage to the device.
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction applies to
power-up and normal operation (that is, if the MPC860 is unpowered, voltage greater than 2.5 V must not be applied to its
inputs).
3
Minimum temperatures are guaranteed as ambient temperature, T . Maximum temperatures are guaranteed as junction
A
temperature, T .
j
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
7
Thermal Characteristics
Figure 1 shows the undershoot and overshoot voltages at the interface of the MPC860.
V
/V
+ 20%
DDH DDL
V
/V
+ 5%
/V
DDH DDL
V
V
DDH DDL
IH
GND
GND – 0.3 V
V
IL
GND – 0.7 V
Not to Exceed 10%
1
of t
interface
Note:
1. t
refers to the clock period associated with the bus clock interface.
interface
Figure 1. Undershoot/Overshoot Voltage for V
and V
DDL
DDH
4 Thermal Characteristics
Table 3. Package Description
Package Designator
Package Code (Case No.)
Package Description
ZP
5050 (1103-01)
PBGA 357 25*25*0.9P1.27
PBGA 357 25*25*1.2P1.27
ZQ/VR
5058 (1103D-02)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
8
Freescale Semiconductor
Thermal Characteristics
Table 4 shows the thermal characteristics for the MPC860.
Table 4. MPC860 Thermal Resistance Data
ZP
ZQ / VR
Unit
Rating
Environment
Symbol
MPC860P MPC860P
Mold Compound Thickness
0.85
34
22
27
18
14
6
1.15
34
22
27
18
13
8
mm
1
2
Junction-to-ambient
Natural convection
Single-layer board (1s)
R
•C/W
θJA
3
3
3
Four-layer board (2s2p)
Single-layer board (1s)
Four-layer board (2s2p)
R
R
R
θJMA
θJMA
θJMA
Airflow (200 ft/min)
4
Junction-to-board
R
θJB
θJC
5
Junction-to-case
R
6
Junction-to-package top Natural convection
Ψ
2
2
JT
1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
2
3
4
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad
packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated value from
the junction to the exposed pad without contact resistance.
Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2.
5
6
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
9
Power Dissipation
5 Power Dissipation
Table 5 provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal,
and 2:1, where CPU frequency is twice the bus speed.
Table 5. Power Dissipation (P )
D
1
2
Die Revision
Frequency (MHz)
Typical
Maximum
Unit
D.4
(1:1 mode)
50
66
66
80
656
TBD
722
851
735
TBD
762
909
mW
mW
mW
mW
D.4
(2:1 mode)
1
2
Typical power dissipation is measured at 3.3 V.
Maximum power dissipation is measured at 3.5 V.
NOTE
Values in Table 5 represent V
-based power dissipation and do not
DDL
include I/O power dissipation over V
. I/O power dissipation varies
DDH
widely by application due to buffer current, depending on external circuitry.
6 DC Characteristics
Table 6 provides the DC electrical characteristics for the MPC860.
Table 6. DC Electrical Specifications
Characteristic
Symbol
, V , V
Min
Max
Unit
Operating voltage at 40 MHz or less
V
3.0
2.0
3.6
3.6
V
V
DDH
DDL DDSYN
KAPWR
(power-down mode)
KAPWR
(all other operating modes)
V
V
– 0.4
V
V
V
V
V
V
DDH
DDH
Operating voltage greater than 40 MHz
V
, V
, KAPWR,
DDL
3.135
2.0
3.465
DDH
V
DDSYN
KAPWR
(power-down mode)
3.6
KAPWR
(all other operating modes)
– 0.4
V
DDH
DDH
Input high voltage (all inputs except EXTAL and
EXTCLK)
V
2.0
5.5
0.8
IH
1
Input low voltage
V
GND
V
V
IL
EXTAL, EXTCLK input high voltage
V
0.7 × (V
)
V
+ 0.3
DDH
IHC
DDH
Input leakage current, V = 5.5 V (except TMS, TRST,
I
—
100
µA
in
in
DSCK, and DSDI pins)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
10
Freescale Semiconductor
DC Characteristics
Table 6. DC Electrical Specifications (continued)
Characteristic Symbol Min
Max
Unit
Input leakage current, V = 3.6 V (except TMS, TRST,
DSCK, and DSDI pins)
I
I
—
—
10
10
µA
in
In
In
Input leakage current, V = 0 V (except TMS, TRST,
µA
in
DSCK, and DSDI pins)
2
Input capacitance
C
—
20
—
pF
V
in
Output high voltage, I
= –2.0 mA, V
= 3.0 V
V
OH
2.4
OH
DDH
(except XTAL, XFC, and open-drain pins)
Output low voltage
V
—
0.5
V
OL
I
I
I
I
I
= 2.0 mA, CLKOUT
OL
OL
OL
OL
OL
3
= 3.2 mA
= 5.3 mA
4
= 7.0 mA, TXD1/PA14, TXD2/PA12
= 8.9 mA, TS, TA, TEA, BI, BB, HRESET, SRESET
1
2
2
V (max) for the I C interface is 0.8 V rather than the 1.5 V as specified in the I C standard.
IL
2
3
Input capacitance is periodically sampled.
A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/VFLS(0:1),
IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3,
RXD1/PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8, TIN1/L1RCLKA/BRGO1/CLK1/PA7,
BRGCLK1/TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5, TOUT2/CLK4/PA4, TIN3/BRGO3/CLK5/PA3, BRGCLK2/
L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1, L1TCLKB/TOUT4/CLK8/PA0, REJCT1/SPISEL/PB31, SPICLK/
PB30,SPIMOSI/PB29, BRGO4/SPIMISO/PB28, BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26, SMTXD1/PB25, SMRXD1/
PB24, SMSYN1/SDACK1/PB23, SMSYN2/SDACK2/PB22, SMTXD2/L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20, L1ST1/
RTS1/PB19, L1ST2/RTS2/PB18, L1ST3/L1RQB/PB17, L1ST4/L1RQA/PB16, BRGO3/PB15, RSTRT1/PB14, L1ST1/RTS1/
DREQ0/PC15, L1ST2/RTS2/DREQ1/PC14, L1ST3/L1RQB/PC13, L1ST4/L1RQA/PC12, CTS1/PC11, TGATE1/CD1/PC10,
CTS2/PC9, TGATE2/CD2/PC8, SDACK2/L1TSYNCB/PC7, L1RSYNCB/PC6, SDACK1/L1TSYNCA/PC5, L1RSYNCA/PC4,
PD15, PD14, PD13, PD12, PD11, PD10, PD9, PD8, PD5, PD6, PD7, PD4, PD3, MII_MDC, MII_TX_ER, MII_EN, MII_MDIO,
and MII_TXD[0:3]
4
BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD, WE1/BS_B1/IOWR,
WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A(2:3)/GPL_B(2:3)/
CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A, ALE_B/DSCK/AT1, OP(0:1),
OP2/MODCK1/STS, OP3/MODCK2/DSDO, and BADDR(28:30)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
11
Thermal Calculation and Measurement
7 Thermal Calculation and Measurement
For the following discussions, P = (V × I ) + PI/O, where PI/O is the power dissipation of the I/O
D
DD
DD
drivers.
7.1
Estimation with Junction-to-Ambient Thermal Resistance
An estimation of the chip junction temperature, TJ, in ºC can be obtained from the equation:
T = T + (R × P )
J
A
θJA
D
where:
T = ambient temperature (ºC)
A
R
= package junction-to-ambient thermal resistance (ºC/W)
θJA
P = power dissipation in package
D
The junction-to-ambient thermal resistance is an industry standard value which provides a quick and easy
estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated
that errors of a factor of two (in the quantity T – T ) are possible.
J
A
7.2
Estimation with Junction-to-Case Thermal Resistance
Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:
R
= R
+ R
θJC θCA
θJA
where:
R
R
R
= junction-to-ambient thermal resistance (ºC/W)
= junction-to-case thermal resistance (ºC/W)
= case-to-ambient thermal resistance (ºC/W)
θJA
θJC
θCA
R
is device related and cannot be influenced by the user. The user adjusts the thermal environment to
θJC
affect the case-to-ambient thermal resistance, R
. For instance, the user can change the airflow around
θCA
the device, add a heat sink, change the mounting arrangement on the printed-circuit board, or change the
thermal dissipation on the printed-circuit board surrounding the device. This thermal model is most useful
for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink
to the ambient environment. For most packages, a better model is required.
7.3
Estimation with Junction-to-Board Thermal Resistance
A simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a
two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. The
junction-to-case thermal resistance covers the situation where a heat sink is used or where a substantial
amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance
describes the thermal performance when most of the heat is conducted to the printed-circuit board. It has
been observed that the thermal performance of most plastic packages, especially PBGA packages, is
strongly dependent on the board temperature; see Figure 2.
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
12
Freescale Semiconductor
Thermal Calculation and Measurement
Board Temperature Rise Above Ambient Divided by Package Power
Figure 2. Effect of Board Temperature Rise on Thermal Behavior
If the board temperature is known, an estimate of the junction temperature in the environment can be made
using the following equation:
T = T + (R
× P )
D
J
B
θJB
where:
R
= junction-to-board thermal resistance (ºC/W)
θJB
T = board temperature (ºC)
B
P = power dissipation in package
D
If the board temperature is known and the heat loss from the package case to the air can be ignored,
acceptable predictions of junction temperature can be made. For this method to work, the board and board
mounting must be similar to the test board used to determine the junction-to-board thermal resistance,
namely a 2s2p (board with a power and a ground plane) and by attaching the thermal balls to the ground
plane.
7.4
Estimation Using Simulation
When the board temperature is not known, a thermal simulation of the application is needed. The simple
two-resistor model can be used with the thermal simulation of the application [2], or a more accurate and
complex model of the package can be used in the thermal simulation.
7.5
Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the
thermal characterization parameter (Ψ ) can be used to determine the junction temperature with a
JT
measurement of the temperature at the top center of the package case using the following equation:
T = T + (Ψ × P )
J
T
JT
D
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
13
Layout Practices
where:
Ψ = thermal characterization parameter
JT
T = thermocouple temperature on top of package
T
P = power dissipation in package
D
The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40 gauge
type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned
so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over 1 mm of wire extending from the junction. The thermocouple wire is
placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
7.6
References
Semiconductor Equipment and Materials International
805 East Middlefield Rd.
(415) 964-5111
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) Specifications
(Available from Global Engineering Documents)
800-854-7179 or
303-397-7956
JEDEC Specifications
http://www.jedec.org
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance
and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999,
pp. 212–220.
8 Layout Practices
Each VDD pin on the MPC860 should be provided with a low-impedance path to the board’s supply. Each
GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on the chip. The VDD power supply should be bypassed to ground using at least
four 0.1 µF-bypass capacitors located as close as possible to the four sides of the package. The capacitor
leads and associated printed circuit traces connecting to chip VDD and GND should be kept to less than half
an inch per capacitor lead. A four-layer board employing two inner layers as VCC and GND planes is
recommended.
All output pins on the MPC860 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize undershoot and reflections caused by these fast output
switching times. This recommendation particularly applies to the address and data buses. Maximum PC
trace lengths of 6 inches are recommended. Capacitance calculations should consider all device loads as
well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads because these loads create higher transient
currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins.
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
14
Freescale Semiconductor
Bus Signal Timing
9 Bus Signal Timing
Table 7 provides the bus operation timing for the MPC860 at 33, 40, 50, and 66 MHz.
The maximum bus speed supported by the MPC860 is 66 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC860 used at 80 MHz must be configured for a 40-MHz bus).
The timing for the MPC860 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for
minimum delays.
Table 7. Bus Operation Timings
33 MHz
Min Max
40 MHz
Min Max
50 MHz
Min Max
66 MHz
Min Max
Num
Characteristic
Unit
B1
CLKOUT period
30.30 30.30 25.00 30.30 20.00 30.30 15.15 30.30
–0.90 0.90 –0.90 0.90 –0.90 0.90 –0.90 0.90
ns
ns
B1a EXTCLK to CLKOUT phase skew
(EXTCLK > 15 MHz and MF <= 2)
B1b EXTCLK to CLKOUT phase skew
(EXTCLK > 10 MHz and MF < 10)
–2.30 2.30 –2.30 2.30 –2.30 2.30 –2.30 2.30
–0.60 0.60 –0.60 0.60 –0.60 0.60 –0.60 0.60
–2.00 2.00 –2.00 2.00 –2.00 2.00 –2.00 2.00
ns
ns
B1c CLKOUT phase jitter (EXTCLK > 15 MHz
1
and MF <= 2)
1
B1d CLKOUT phase jitter
ns
%
1
B1e CLKOUT frequency jitter (MF < 10)
—
—
0.50
2.00
3.00
0.50
—
—
—
0.50
2.00
3.00
0.50
—
—
—
0.50
2.00
3.00
0.50
—
—
—
0.50
2.00
3.00
0.50
—
1
B1f
CLKOUT frequency jitter (10 < MF < 500)
%
1
B1g CLKOUT frequency jitter (MF > 500)
—
—
—
—
%
2
B1h Frequency jitter on EXTCLK
—
—
—
—
%
B2
B3
B4
CLKOUT pulse width low
CLKOUT width high
12.12
12.12
—
10.00
10.00
—
8.00
8.00
—
6.06
6.06
—
ns
ns
ns
ns
ns
—
—
—
—
3
CLKOUT rise time
4.00
4.00
—
4.00
4.00
—
4.00
4.00
—
4.00
4.00
—
33
3
B5
CLKOUT fall time
—
—
—
—
B7
CLKOUT to A(0:31), BADDR(28:30),
7.58
6.25
5.00
3.80
RD/WR, BURST, D(0:31), DP(0:3) invalid
B7a CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3),
BDIP, PTR invalid
7.58
7.58
—
—
6.25
6.25
—
—
5.00
5.00
—
—
3.80
3.80
—
—
ns
ns
ns
ns
ns
B7b CLKOUT to BR, BG, FRZ, VFLS(0:1),
4
VF(0:2) IWP(0:2), LWP(0:1), STS invalid
B8
CLKOUT to A(0:31), BADDR(28:30)
RD/WR, BURST, D(0:31), DP(0:3) valid
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04
B8a CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3)
BDIP, PTR valid
B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2),
4
IWP(0:2), FRZ, LWP(0:1), STS valid
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
15
Bus Signal Timing
Table 7. Bus Operation Timings (continued)
33 MHz 40 MHz
Min Max Min Max
50 MHz
Min Max
66 MHz
Min Max
Num
Characteristic
Unit
B9
CLKOUT to A(0:31), BADDR(28:30),
RD/WR, BURST, D(0:31), DP(0:3),
TSIZ(0:1), REG, RSV, AT(0:3), PTR High-Z
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04
ns
B11 CLKOUT to TS, BB assertion
7.58 13.58 6.25 12.25 5.00 11.00 3.80 11.29
ns
ns
B11a CLKOUT to TA, BI assertion (when driven by 2.50
the memory controller or PCMCIA interface)
9.25
2.50
9.25
2.50
9.25
2.50
9.75
B12 CLKOUT to TS, BB negation
7.58 14.33 6.25 13.00 5.00 11.75 3.80
8.54
9.00
ns
ns
B12a CLKOUT to TA, BI negation (when driven by 2.50 11.00 2.50 11.00 2.50 11.00 2.50
the memory controller or PCMCIA interface)
B13 CLKOUT to TS, BB High-Z
7.58 21.58 6.25 20.25 5.00 19.00 3.80 14.04
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00
ns
ns
B13a CLKOUT to TA, BI High-Z (when driven by
the memory controller or PCMCIA interface)
B14 CLKOUT to TEA assertion
B15 CLKOUT to TEA High-Z
2.50 10.00 2.50 10.00 2.50 10.00 2.50
9.00
ns
ns
ns
ns
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00
B16 TA, BI valid to CLKOUT (setup time)
9.75
—
—
9.75
—
—
9.75
—
—
6.00
4.50
—
—
B16a TEA, KR, RETRY, CR valid to CLKOUT
(setup time)
10.00
10.00
10.00
5
B16b BB, BG, BR, valid to CLKOUT (setup time)
8.50
1.00
—
—
8.50
1.00
—
—
8.50
1.00
—
—
4.00
2.00
—
—
ns
ns
B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid
(hold time)
B17a CLKOUT to KR, RETRY, CR valid (hold
time)
2.00
6.00
1.00
4.00
2.00
—
—
—
—
—
2.00
6.00
1.00
4.00
2.00
—
—
—
—
—
2.00
6.00
1.00
4.00
2.00
—
—
—
—
—
2.00
6.00
2.00
4.00
2.00
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
B18 D(0:31), DP(0:3) valid to CLKOUT rising
6
edge (setup time)
B19 CLKOUT rising edge to D(0:31), DP(0:3)
6
valid (hold time)
B20 D(0:31), DP(0:3) valid to CLKOUT falling
7
edge (setup time)
B21 CLKOUT falling edge to D(0:31), DP(0:3)
7
valid (hold time)
B22 CLKOUT rising edge to CS asserted GPCM 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04
ACS = 00
B22a CLKOUT falling edge to CS asserted GPCM
ACS = 10, TRLX = 0
—
8.00
—
8.00
—
8.00
—
8.00
B22b CLKOUT falling edge to CS asserted GPCM 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54
ACS = 11, TRLX = 0, EBDF = 0
B22c CLKOUT falling edge to CS asserted GPCM 10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31
ACS = 11, TRLX = 0, EBDF = 1
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
16
Freescale Semiconductor
Bus Signal Timing
Table 7. Bus Operation Timings (continued)
33 MHz 40 MHz
50 MHz
66 MHz
Unit
Num
Characteristic
Min
Max
Min
Max
Min
Max
Min
Max
B23 CLKOUT rising edge to CS negated GPCM 2.00
read access, GPCM write access ACS = 00,
TRLX = 0, and CSNT = 0
8.00
2.00
8.00
2.00
8.00
2.00
8.00
ns
B24 A(0:31) and BADDR(28:30) to CS asserted 5.58
GPCM ACS = 10, TRLX = 0
—
—
4.25
10.50
—
—
—
3.00
8.00
—
—
—
1.79
5.58
—
—
—
ns
ns
ns
B24a A(0:31) and BADDR(28:30) to CS asserted 13.15
GPCM ACS = 11, TRLX = 0
B25 CLKOUT rising edge to OE, WE(0:3)
asserted
—
9.00
9.00
9.00
9.00
B26 CLKOUT rising edge to OE negated
2.00
9.00
—
2.00
9.00
—
2.00
9.00
—
2.00
9.00
—
ns
ns
B27 A(0:31) and BADDR(28:30) to CS asserted 35.88
GPCM ACS = 10, TRLX = 1
29.25
23.00
16.94
B27a A(0:31) and BADDR(28:30) to CS asserted 43.45
GPCM ACS = 11, TRLX = 1
—
35.50
—
—
28.00
—
—
20.73
—
—
ns
ns
ns
B28 CLKOUT rising edge to WE(0:3) negated
GPCM write access CSNT = 0
—
9.00
9.00
9.00
9.00
B28a CLKOUT falling edge to WE(0:3) negated
GPCM write access TRLX = 0, 1, CSNT = 1,
EBDF = 0
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54
B28b CLKOUT falling edge to CS negated GPCM
write access TRLX = 0, 1, CSNT = 1,
—
14.33
—
13.00
—
11.75
—
10.54
ns
ns
ACS = 10, or ACS = 11, EBDF = 0
B28c CLKOUT falling edge to WE(0:3) negated
GPCM write access TRLX = 0, 1, CSNT = 1
write access TRLX = 0, CSNT = 1,
EBDF = 1
10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31
B28d CLKOUT falling edge to CS negated GPCM
write access TRLX = 0, 1, CSNT = 1,
—
17.99
—
16.00
—
14.13
—
12.31
ns
ACS = 10, or ACS = 11, EBDF = 1
B29 WE(0:3) negated to D(0:31), DP(0:3) High-Z 5.58
GPCM write access CSNT = 0, EBDF = 0
—
—
4.25
10.5
—
—
3.00
8.00
—
—
1.79
5.58
—
—
ns
ns
B29a WE(0:3) negated to D(0:31), DP(0:3) High-Z 13.15
GPCM write access, TRLX = 0, CSNT = 1,
EBDF = 0
B29b CS negated to D(0:31), DP(0:3), High-Z
GPCM write access, ACS = 00, TRLX = 0, 1,
and CSNT = 0
5.58
—
—
4.25
10.5
—
—
3.00
8.00
—
—
1.79
5.58
—
—
ns
ns
B29c CS negated to D(0:31), DP(0:3) High-Z
GPCM write access, TRLX = 0, CSNT = 1,
ACS = 10, or ACS = 11, EBDF = 0
13.15
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
17
Bus Signal Timing
Table 7. Bus Operation Timings (continued)
33 MHz 40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B29d WE(0:3) negated to D(0:31), DP(0:3) High-Z 43.45
GPCM write access, TRLX = 1, CSNT = 1,
EBDF = 0
—
35.5
—
28.00
28.00
5.00
—
20.73
29.73
3.18
—
ns
B29e CS negated to D(0:31), DP(0:3) High-Z
GPCM write access, TRLX = 1, CSNT = 1,
ACS = 10, or ACS = 11, EBDF = 0
43.45
—
—
—
—
—
35.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
B29f WE(0:3) negated to D(0:31), DP(0:3) High-Z 8.86
GPCM write access, TRLX = 0, CSNT = 1,
EBDF = 1
6.88
B29g CS negated to D(0:31), DP(0:3) High-Z
GPCM write access, TRLX = 0, CSNT = 1,
ACS = 10, or ACS = 11, EBDF = 1
8.86
6.88
5.00
3.18
B29h WE(0:3) negated to D(0:31), DP(0:3) High-Z 38.67
GPCM write access, TRLX = 1, CSNT = 1,
EBDF = 1
31.38
31.38
24.50
24.50
17.83
17.83
B29i CS negated to D(0:31), DP(0:3) High-Z
GPCM write access, TRLX = 1, CSNT = 1,
ACS = 10, or ACS = 11, EBDF = 1
38.67
B30 CS, WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write access
5.58
—
—
4.25
—
—
3.00
8.00
—
—
1.79
5.58
—
—
ns
ns
8
B30a WE(0:3) negated to A(0:31), BADDR(28:30) 13.15
invalid GPCM, write access, TRLX = 0,
10.50
CSNT = 1, CS negated to A(0:31) invalid
GPCM write access, TRLX = 0, CSNT = 1
ACS = 10, or ACS = 11, EBDF = 0
B30b WE(0:3) negated to A(0:31), invalid GPCM 43.45
BADDR(28:30) invalid GPCM write access,
TRLX = 1, CSNT = 1. CS negated to
A(0:31), Invalid GPCM, write access,
TRLX = 1, CSNT = 1, ACS = 10, or
—
35.50
—
28.00
—
20.73
—
ns
ACS = 11, EBDF = 0
B30c WE(0:3) negated to A(0:31), BADDR(28:30) 8.36
invalid GPCM write access, TRLX = 0,
—
—
6.38
31.38
1.50
—
—
4.50
24.50
1.50
—
—
2.68
17.83
1.50
—
—
ns
ns
ns
CSNT = 1. CS negated to A(0:31) invalid
GPCM write access, TRLX = 0, CSNT = 1,
ACS = 10, ACS = 11, EBDF = 1
B30d WE(0:3) negated to A(0:31), BADDR(28:30) 38.67
invalid GPCM write access, TRLX = 1,
CSNT =1. CS negated to A(0:31) invalid
GPCM write access TRLX = 1, CSNT = 1,
ACS = 10, or ACS = 11, EBDF = 1
B31 CLKOUT falling edge to CS valid—as
requested by control bit CST4 in the
corresponding word in UPM
1.50
6.00
6.00
6.00
6.00
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
18
Freescale Semiconductor
Bus Signal Timing
Table 7. Bus Operation Timings (continued)
33 MHz 40 MHz
Min Max Min Max
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54
50 MHz
Min Max
66 MHz
Unit
Num
Characteristic
Min
Max
B31a CLKOUT falling edge to CS valid—as
requested by control bit CST1 in the
corresponding word in UPM
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
B31b CLKOUT rising edge to CS valid—as
requested by control bit CST2 in the
corresponding word in UPM
1.50
8.00
1.50
8.00
1.50
8.00
1.50
8.00
B31c CLKOUT rising edge to CS valid—as
requested by control bit CST3 in the
corresponding word in UPM
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04
13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31
B31d CLKOUT falling edge to CS valid—as
requested by control bit CST1 in the
corresponding word in UPM, EBDF = 1
B32 CLKOUT falling edge to BS valid—as
requested by control bit BST4 in the
corresponding word in UPM
1.50
6.00
1.50
6.00
1.50
6.00
1.50
6.00
B32a CLKOUT falling edge to BS valid—as
requested by control bit BST1 in the
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54
corresponding word in UPM, EBDF = 0
B32b CLKOUT rising edge to BS valid—as
requested by control bit BST2 in the
corresponding word in UPM
1.50
8.00
1.50
8.00
1.50
8.00
1.50
8.00
B32c CLKOUT rising edge to BS valid—as
requested by control bit BST3 in the
corresponding word in UPM
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54
13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31
B32d CLKOUT falling edge to BS valid—as
requested by control bit BST1 in the
corresponding word in UPM, EBDF = 1
B33 CLKOUT falling edge to GPL valid—as
requested by control bit GxT4 in the
corresponding word in UPM
1.50
6.00
1.50
6.00
1.50
6.00
1.50
6.00
B33a CLKOUT rising edge to GPL valid—as
requested by control bit GxT3 in the
corresponding word in UPM
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54
B34 A(0:31), BADDR(28:30), and D(0:31) to CS 5.58
valid—as requested by control bit CST4 in
the corresponding word in UPM
—
—
—
4.25
10.50
16.75
—
—
—
3.00
8.00
—
—
—
1.79
5.58
9.36
—
—
—
B34a A(0:31), BADDR(28:30), and D(0:31) to CS 13.15
valid—as requested by control bit CST1 in
the corresponding word in UPM
B34b A(0:31), BADDR(28:30), and D(0:31) to CS 20.73
valid—as requested by control bit CST2 in
the corresponding word in UPM
13.00
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
19
Bus Signal Timing
Table 7. Bus Operation Timings (continued)
33 MHz 40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
5.58
Max
Min
Max
Min
Max
Min
Max
B35 A(0:31), BADDR(28:30) to CS valid—as
requested by control bit BST4 in the
corresponding word in UPM
—
4.25
10.50
16.75
4.25
—
3.00
—
1.79
5.58
9.36
1.79
—
ns
B35a A(0:31), BADDR(28:30), and D(0:31) to BS 13.15
valid—as requested by control bit BST1 in
the corresponding word in UPM
—
—
—
—
—
—
8.00
—
—
—
—
—
—
ns
ns
ns
B35b A(0:31), BADDR(28:30), and D(0:31) to BS 20.73
valid—as requested by control bit BST2 in
the corresponding word in UPM
13.00
3.00
B36 A(0:31), BADDR(28:30), and D(0:31) to
GPL valid—as requested by control bit GxT4
in the corresponding word in UPM
5.58
9
B37 UPWAIT valid to CLKOUT falling edge
6.00
1.00
7.00
—
—
—
—
6.00
1.00
7.00
7.00
—
—
—
—
6.00
1.00
7.00
7.00
—
—
—
—
6.00
1.00
7.00
7.00
—
—
—
—
ns
ns
ns
ns
9
B38 CLKOUT falling edge to UPWAIT valid
10
B39 AS valid to CLKOUT rising edge
B40 A(0:31), TSIZ(0:1), RD/WR, BURST, valid to 7.00
CLKOUT rising edge
B41 TS valid to CLKOUT rising edge (setup time) 7.00
B42 CLKOUT rising edge to TS valid (hold time) 2.00
—
—
7.00
2.00
—
—
—
7.00
2.00
—
—
—
7.00
2.00
—
—
—
ns
ns
ns
B43 AS negation to memory controller signals
negation
—
TBD
TBD
TBD
TBD
1
2
Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value.
If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum values
in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time) then the maximum
allowed jitter on EXTAL can be up to 2%.
The timings specified in B4 and B5 are based on full strength clock.
The timing for BR output is relevant when the MPC860 is selected to work with external bus arbiter. The timing for BG output
is relevant when the MPC860 is selected to work with internal bus arbiter.
3
4
5
6
7
The timing required for BR input is relevant when the MPC860 is selected to work with internal bus arbiter. The timing for BG
input is relevant when the MPC860 is selected to work with external bus arbiter.
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is
asserted.
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read
accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where DLT3 = 1 in the
UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37 and
B38 are specified to enable the freeze of the UPM output signals as described in Figure 18.
The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified
in Figure 21.
8
9
10
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
20
Freescale Semiconductor
Bus Signal Timing
Figure 3 is the control timing diagram.
CLKOUT
A
B
Outputs
Outputs
Inputs
A
B
D
C
D
C
Inputs
A
B
C
D
Maximum output delay specification.
Minimum output hold time.
Minimum input setup time specification.
Minimum input hold time specification.
Figure 3. Control Timing
Figure 4 provides the timing for the external clock.
CLKOUT
B1
B1
B3
B2
B4
B5
Figure 4. External Clock Timing
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
21
Bus Signal Timing
Figure 5 provides the timing for the synchronous output signals.
CLKOUT
B8
B7
B9
Output
Signals
B8a
B8b
B7a
B7b
B9
Output
Signals
Output
Signals
Figure 5. Synchronous Output Signals Timing
Figure 6 provides the timing for the synchronous active pull-up and open-drain output signals.
CLKOUT
B13
B11
B12
B12a
B15
TS, BB
B13a
B11a
B14
TA, BI
TEA
Figure 6. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
22
Freescale Semiconductor
Bus Signal Timing
Figure 7 provides the timing for the synchronous input signals.
CLKOUT
B16
B17
TA, BI
B16a
B17a
B17
TEA, KR,
RETRY, CR
B16b
BB, BG, BR
Figure 7. Synchronous Input Signals Timing
Figure 8 provides normal case timing for input data. It also applies to normal read accesses under the
control of the UPM in the memory controller.
CLKOUT
B16
B17
TA
B18
B19
D[0:31],
DP[0:3]
Figure 8. Input Data Timing in Normal Case
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
23
Bus Signal Timing
Figure 9 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in
the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
CLKOUT
TA
B20
B21
D[0:31],
DP[0:3]
Figure 9. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1
Figure 10 through Figure 13 provide the timing for the external bus read controlled by various GPCM
factors.
CLKOUT
B11
B8
B12
TS
A[0:31]
CSx
B22
B23
B25
B26
B19
OE
B28
WE[0:3]
B18
D[0:31],
DP[0:3]
Figure 10. External Bus Read Timing (GPCM Controlled—ACS = 00)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
24
Freescale Semiconductor
Bus Signal Timing
CLKOUT
TS
B11
B8
B12
A[0:31]
CSx
B23
B22a
B24
B25
B26
B19
OE
B18
D[0:31],
DP[0:3]
Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)
CLKOUT
TS
B11
B8
B12
B22b
B22c
A[0:31]
B23
CSx
OE
B24a
B25
B26
B19
B18
D[0:31],
DP[0:3]
Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
25
Bus Signal Timing
CLKOUT
B11
B12
TS
B8
A[0:31]
B23
B22a
CSx
OE
B27
B26
B19
B27a
B22b B22c
B18
D[0:31],
DP[0:3]
Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 10, ACS = 11)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
26
Freescale Semiconductor
Bus Signal Timing
Figure 14 through Figure 16 provide the timing for the external bus write controlled by various GPCM
factors.
CLKOUT
B11
B8
B12
TS
B30
A[j0:31]
B22
B23
CSx
WE[0:3]
OE
B25
B28
B26
B29b
B29
B8
B9
D[0:31],
DP[0:3]
Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 0)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
27
Bus Signal Timing
CLKOUT
B11
B8
B12
TS
B30a B30c
A[0:31]
B22
B28b B28d
B23
CSx
WE[0:3]
OE
B25
B29c B29g
B29f
B29a
B26
B28a B28c
B8
B9
D[0:31],
DP[0:3]
Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 1)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
28
Freescale Semiconductor
Bus Signal Timing
CLKOUT
TS
B11
B12
B8
B30b B30d
A[0:31]
B22
B28b B28d
B23
CSx
WE[0:3]
OE
B25
B29e B29i
B29d B29h
B26
B29b
B8
B28a B28c
B9
D[0:31],
DP[0:3]
Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 1)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
29
Bus Signal Timing
Figure 17 provides the timing for the external bus controlled by the UPM.
CLKOUT
B8
A[0:31]
B31a
B31d
B31c
B31
B31b
CSx
B34
B34a
B34b
B32a B32d
B32c
B32
B32b
BS_A[0:3],
BS_B[0:3]
B35 B36
B35a
B33a
B35b
B33
GPL_A[0:5],
GPL_B[0:5]
Figure 17. External Bus Timing (UPM Controlled Signals)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
30
Freescale Semiconductor
Bus Signal Timing
Figure 18 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.
CLKOUT
UPWAIT
CSx
B37
B38
BS_A[0:3],
BS_B[0:3]
GPL_A[0:5],
GPL_B[0:5]
Figure 18. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing
Figure 19 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.
CLKOUT
B37
UPWAIT
B38
CSx
BS_A[0:3],
BS_B[0:3]
GPL_A[0:5],
GPL_B[0:5]
Figure 19. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
31
Bus Signal Timing
Figure 20 provides the timing for the synchronous external master access controlled by the GPCM.
CLKOUT
B41
B40
B42
TS
A[0:31],
TSIZ[0:1],
R/W, BURST
B22
CSx
Figure 20. Synchronous External Master Access Timing (GPCM Handled ACS = 00)
Figure 21 provides the timing for the asynchronous external master memory access controlled by the
GPCM.
CLKOUT
B39
AS
B40
A[0:31],
TSIZ[0:1],
R/W
B22
CSx
Figure 21. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)
Figure 22 provides the timing for the asynchronous external master control signals negation.
AS
B43
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
Figure 22. Asynchronous External Master—Control Signals Negation Timing
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
32
Freescale Semiconductor
Bus Signal Timing
Table 8 provides interrupt timing for the MPC860.
Table 8. Interrupt Timing
All Frequencies
Min Max
1
Num
Characteristic
Unit
I39
I40
I41
I42
I43
IRQx valid to CLKOUT rising edge (setup time)
IRQx hold time after CLKOUT
IRQx pulse width low
6.00
2.00
3.00
3.00
—
—
—
—
—
ns
ns
ns
ns
—
IRQx pulse width high
IRQx edge-to-edge time
4 × T
CLOCKOUT
1
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level-sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the
CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry and have no direct
relation with the total system interrupt latency that the MPC860 is able to support.
Figure 23 provides the interrupt detection timing for the external level-sensitive lines.
CLKOUT
I39
I40
IRQx
Figure 23. Interrupt Detection Timing for External Level Sensitive Lines
Figure 24 provides the interrupt detection timing for the external edge-sensitive lines.
CLKOUT
I41
I42
IRQx
I43
I43
Figure 24. Interrupt Detection Timing for External Edge Sensitive Lines
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
33
Bus Signal Timing
Table 9 shows the PCMCIA timing for the MPC860.
Table 9. PCMCIA Timing
33 MHz 40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
P44 A(0:31), REG valid to PCMCIA Strobe
20.73
—
16.75
—
13.00
—
9.36
—
ns
1
asserted
1
P45 A(0:31), REG valid to ALE negation
28.30
—
23.00
—
18.00
—
13.15
—
ns
ns
ns
ns
ns
ns
P46 CLKOUT to REG valid
7.58 15.58 6.25 14.25 5.00 13.00 3.79 11.84
8.58 7.25 6.00 4.84
P47 CLKOUT to REG invalid
—
—
—
—
P48 CLKOUT to CE1, CE2 asserted
P49 CLKOUT to CE1, CE2 negated
7.58 15.58 6.25 14.25 5.00 13.00 3.79 11.84
7.58 15.58 6.25 14.25 5.00 13.00 3.79 11.84
P50 CLKOUT to PCOE, IORD, PCWE, IOWR
assert time
—
11.00
11.00
—
11.00
—
11.00
P51 CLKOUT to PCOE, IORD, PCWE, IOWR
negate time
2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00
7.58 15.58 6.25 14.25 5.00 13.00 3.79 10.04
ns
P52 CLKOUT to ALE assert time
P53 CLKOUT to ALE negate time
ns
ns
ns
ns
—
15.58
—
14.25
—
—
13.00
—
—
11.84
—
1
P54 PCWE, IOWR negated to D(0:31) invalid
5.58
8.00
4.25
8.00
3.00
8.00
1.79
8.00
P55 WAITA and WAITB valid to CLKOUT rising
—
—
—
—
1
edge
P56 CLKOUT rising edge to WAITA and WAITB
2.00
—
2.00
—
2.00
—
2.00
—
ns
1
invalid
1
PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the
PCMCIA current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the
PSL timer expiration. See Chapter 16, “PCMCIA Interface,” in the MPC860 PowerQUICC™ Family
User’s Manual.
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
34
Freescale Semiconductor
Bus Signal Timing
Figure 25 provides the PCMCIA access cycle timing for the external bus read.
CLKOUT
TS
P44
A[0:31]
P46
P48
P45
P47
P49
P51
P52
REG
CE1/CE2
PCOE, IORD
ALE
P50
P53
P52
B18
B19
D[0:31]
Figure 25. PCMCIA Access Cycle Timing External Bus Read
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
35
Bus Signal Timing
Figure 26 provides the PCMCIA access cycle timing for the external bus write.
CLKOUT
TS
P44
A[0:31]
P46
P48
P45
P47
P49
P51
P52
B9
REG
CE1/CE2
PCWE, IOWR
ALE
P50
P53
B8
P54
P52
D[0:31]
Figure 26. PCMCIA Access Cycle Timing External Bus Write
Figure 27 provides the PCMCIA WAIT signal detection timing.
CLKOUT
P55
P56
WAITx
Figure 27. PCMCIA WAIT Signal Detection Timing
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
36
Freescale Semiconductor
Bus Signal Timing
Table 10 shows the PCMCIA port timing for the MPC860.
Table 10. PCMCIA Port Timing
33 MHz 40 MHz
50 MHz
66 MHz
Unit
Num
Characteristic
Min
Max
Min
Max
Min
Max
Min
Max
P57 CLKOUT to OPx valid
—
19.00
—
—
19.00
—
—
19.00
—
—
19.00
—
ns
ns
ns
ns
1
P58 HRESET negated to OPx drive
25.73
5.00
1.00
21.75
5.00
1.00
18.00
5.00
1.00
14.36
5.00
1.00
P59 IP_Xx valid to CLKOUT rising edge
P60 CLKOUT rising edge to IP_Xx invalid
OP2 and OP3 only.
—
—
—
—
—
—
—
—
1
Figure 28 provides the PCMCIA output port timing for the MPC860.
CLKOUT
P57
Output
Signals
HRESET
P58
OP2, OP3
Figure 28. PCMCIA Output Port Timing
Figure 29 provides the PCMCIA output port timing for the MPC860.
CLKOUT
P59
P60
Input
Signals
Figure 29. PCMCIA Input Port Timing
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
37
Bus Signal Timing
Table 11 shows the debug port timing for the MPC860.
Table 11. Debug Port Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
P61 DSCK cycle time
3 × T
—
—
—
—
ns
ns
ns
ns
ns
CLOCKOUT
P62 DSCK clock pulse width
P63 DSCK rise and fall times
1.25 × T
CLOCKOUT
0.00
3.00
—
P64 DSDI input data setup time
P65 DSDI data hold time
8.00
5.00
0.00
0.00
—
P66 DSCK low to DSDO data valid
P67 DSCK low to DSDO invalid
15.00
2.00
Figure 30 provides the input timing for the debug port clock.
DSCK
D61
D62
D61
D62
D63
Figure 30. Debug Port Clock Input Timing
D63
Figure 31 provides the timing for the debug port.
DSCK
D64
D65
DSDI
D66
D67
DSDO
Figure 31. Debug Port Timings
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
38
Freescale Semiconductor
Bus Signal Timing
Table 12 shows the reset timing for the MPC860.
Table 12. Reset Timing
33 MHz 40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
R69 CLKOUT to HRESET high impedance
R70 CLKOUT to SRESET high impedance
R71 RSTCONF pulse width
—
—
20.00
20.00
—
—
—
20.00
20.00
—
—
20.00
20.00
—
—
—
20.00
20.00
—
ns
ns
ns
515.15
—
425.00
—
340.00
—
257.58
—
R72
—
—
—
—
—
—
R73 Configuration data to HRESET rising edge 504.55
setup time
—
425.00
350.00
—
277.27
—
ns
ns
ns
ns
ns
ns
ns
R74 Configuration data to RSTCONF rising
edge setup time
350.00
0.00
0.00
—
—
—
350.00
0.00
—
—
350.00
0.00
0.00
—
—
—
350.00
0.00
0.00
—
—
—
R75 Configuration data hold time after
RSTCONF negation
R76 Configuration data hold time after
HRESET negation
—
0.00
—
—
—
R77 HRESET and RSTCONF asserted to data
out drive
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
R78 RSTCONF negated to data out high
impedance
—
—
—
—
—
R79 CLKOUT of last rising edge before chip
three-state HRESET to data out high
impedance
—
—
—
R80 DSDI, DSCK setup
90.91
0.00
—
—
—
75.00
0.00
—
—
—
60.00
0.00
—
—
—
45.45
0.00
—
—
—
ns
ns
ns
R81 DSDI, DSCK hold time
R82 SRESET negated to CLKOUT rising edge 242.42
for DSDI and DSCK sample
200.00
160.00
121.21
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
39
Bus Signal Timing
Figure 32 shows the reset timing for the data bus configuration.
HRESET
R71
R76
RSTCONF
D[0:31] (IN)
R73
R74
R75
Figure 32. Reset Timing—Configuration from Data Bus
Figure 33 provides the reset timing for the data bus weak drive during configuration.
CLKOUT
R69
HRESET
R79
RSTCONF
R77
R78
D[0:31] (OUT)
(Weak)
Figure 33. Reset Timing—Data Bus Weak Drive During Configuration
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
40
Freescale Semiconductor
IEEE 1149.1 Electrical Specifications
Figure 34 provides the reset timing for the debug port configuration.
CLKOUT
R70
R82
SRESET
R80
R80
R81
R81
DSCK, DSDI
Figure 34. Reset Timing—Debug Port Configuration
10 IEEE 1149.1 Electrical Specifications
Table 13 provides the JTAG timings for the MPC860 shown in Figure 35 through Figure 38.
Table 13. JTAG Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
J82
J83
J84
J85
J86
J87
J88
J89
J90
J91
J92
J93
J94
J95
J96
TCK cycle time
100.00
40.00
0.00
5.00
25.00
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock pulse width measured at 1.5 V
TCK rise and fall times
10.00
—
TMS, TDI data setup time
TMS, TDI data hold time
—
TCK low to TDO data valid
27.00
—
TCK low to TDO data invalid
0.00
—
TCK low to TDO high impedance
TRST assert time
20.00
—
100.00
40.00
—
TRST setup time to TCK low
—
TCK falling edge to output valid
TCK falling edge to output valid out of high impedance
TCK falling edge to output high impedance
Boundary scan input valid to TCK rising edge
TCK rising edge to boundary scan input invalid
50.00
50.00
50.00
—
—
—
50.00
50.00
—
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
41
IEEE 1149.1 Electrical Specifications
TCK
J82
J83
J82
J83
J84
J84
Figure 35. JTAG Test Clock Input Timing
TCK
J85
J86
TMS, TDI
J87
J88
J89
TDO
TCK
Figure 36. JTAG Test Access Port Timing Diagram
J91
J90
TRST
TCK
Figure 37. JTAG TRST Timing Diagram
J92
J93
J94
Output
Signals
Output
Signals
J95
J96
Output
Signals
Figure 38. Boundary Scan (JTAG) Timing Diagram
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
42
Freescale Semiconductor
CPM Electrical Characteristics
11 CPM Electrical Characteristics
This section provides the AC and DC electrical specifications for the communications processor module
(CPM) of the MPC860.
11.1 PIP/PIO AC Electrical Specifications
Table 14 provides the PIP/PIO AC timings as shown in Figure 39 through Figure 43.
Table 14. PIP/PIO Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
21
22
23
24
25
26
27
28
29
30
31
Data-in setup time to STBI low
Data-in hold time to STBI high
STBI pulse width
0
2.5 – t3
1.5
—
—
—
—
—
—
2
ns
CLK
CLK
ns
1
STBO pulse width
1 CLK – 5 ns
Data-out setup time to STBO low
2
5
CLK
CLK
CLK
CLK
ns
Data-out hold time from STBO high
STBI low to STBO low (Rx interlock)
STBI low to STBO high (Tx interlock)
Data-in setup time to clock high
—
2
—
—
—
25
15
7.5
—
Data-in hold time from clock high
ns
Clock low to data-out valid (CPU writes data, control, or direction)
ns
1
t3 = Specification 23.
DATA-IN
21
22
23
STBI
27
24
STBO
Figure 39. PIP Rx (Interlock Mode) Timing Diagram
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
43
CPM Electrical Characteristics
DATA-OUT
25
26
24
STBO
(Output)
28
23
STBI
(Input)
Figure 40. PIP Tx (Interlock Mode) Timing Diagram
DATA-IN
21
22
23
24
STBI
(Input)
STBO
(Output)
Figure 41. PIP Rx (Pulse Mode) Timing Diagram
DATA-OUT
25
26
24
STBO
(Output)
23
STBI
(Input)
Figure 42. PIP TX (Pulse Mode) Timing Diagram
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
44
Freescale Semiconductor
CPM Electrical Characteristics
CLKO
DATA-IN
29
30
31
DATA-OUT
Figure 43. Parallel I/O Data-In/Data-Out Timing Diagram
11.2 Port C Interrupt AC Electrical Specifications
Table 15 provides the timings for port C interrupts.
Table 15. Port C Interrupt Timing
1
≥ 33.34 MHz
Num
Characteristic
Unit
Min
Max
35
36
Port C interrupt pulse width low (edge-triggered mode)
Port C interrupt minimum time between active edges
55
55
—
—
ns
ns
1
External bus frequency of greater than or equal to 33.34 MHz.
Figure 44 shows the port C interrupt detection timing.
36
Port C
(Input)
35
Figure 44. Port C Interrupt Detection Timing
11.3 IDMA Controller AC Electrical Specifications
Table 16 provides the IDMA controller timings as shown in Figure 45 through Figure 48.
Table 16. IDMA Controller Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
40
41
DREQ setup time to clock high
DREQ hold time from clock high
7
3
—
—
ns
ns
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
45
CPM Electrical Characteristics
Table 16. IDMA Controller Timing (continued)
Characteristic
All Frequencies
Num
Unit
Min
Max
42
43
44
45
46
SDACK assertion delay from clock high
SDACK negation delay from clock low
—
—
—
—
7
12
12
20
15
—
ns
ns
ns
ns
ns
SDACK negation delay from TA low
SDACK negation delay from clock high
TA assertion to rising edge of the clock setup time (applies to external TA)
CLKO
(Output)
41
40
DREQ
(Input)
Figure 45. IDMA External Requests Timing Diagram
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
43
DATA
46
TA
(Input)
SDACK
Figure 46. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
46
Freescale Semiconductor
CPM Electrical Characteristics
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
44
DATA
TA
(Output)
SDACK
Figure 47. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
45
DATA
TA
(Output)
SDACK
Figure 48. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
47
CPM Electrical Characteristics
11.4 Baud Rate Generator AC Electrical Specifications
Table 17 provides the baud rate generator timings as shown in Figure 49.
Table 17. Baud Rate Generator Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
50
51
52
BRGO rise and fall time
BRGO duty cycle
BRGO cycle
—
40
40
10
60
—
ns
%
ns
50
50
BRGOX
51
51
52
Figure 49. Baud Rate Generator Timing Diagram
11.5 Timer AC Electrical Specifications
Table 18 provides the general-purpose timer timings as shown in Figure 50.
Table 18. Timer Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
61
62
63
64
65
TIN/TGATE rise and fall time
TIN/TGATE low time
10
1
—
—
—
—
25
ns
CLK
CLK
CLK
ns
TIN/TGATE high time
TIN/TGATE cycle time
CLKO low to TOUT valid
2
3
3
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
48
Freescale Semiconductor
CPM Electrical Characteristics
CLKO
60
61
63
62
TIN/TGATE
(Input)
61
64
65
TOUT
(Output)
Figure 50. CPM General-Purpose Timers Timing Diagram
11.6 Serial Interface AC Electrical Specifications
Table 19 provides the serial interface timings as shown in Figure 51 through Figure 55.
Table 19. SI Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
1, 2
70
71
71a
72
73
74
75
76
77
78
L1RCLK, L1TCLK frequency (DSC = 0)
—
SYNCCLK/2.5 MHz
2
L1RCLK, L1TCLK width low (DSC = 0)
P + 10
P + 10
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
3
L1RCLK, L1TCLK width high (DSC = 0)
L1TXD, L1ST(1–4), L1RQ, L1CLKO rise/fall time
L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC setup time)
L1CLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time)
L1RSYNC, L1TSYNC rise/fall time
15.00
—
20.00
35.00
—
—
15.00
—
L1RXD valid to L1CLK edge (L1RXD setup time)
L1CLK edge to L1RXD invalid (L1RXD hold time)
17.00
13.00
10.00
10.00
10.00
10.00
10.00
0.00
—
4
L1CLK edge to L1ST(1–4) valid
45.00
45.00
45.00
55.00
55.00
42.00
78A L1SYNC valid to L1ST(1–4) valid
79
80
L1CLK edge to L1ST(1–4) invalid
L1CLK edge to L1TXD valid
4
80A L1TSYNC valid to L1TXD valid
81
82
L1CLK edge to L1TXD high impedance
L1RCLK, L1TCLK frequency (DSC =1 )
—
16.00 or
SYNCCLK/2
83
L1RCLK, L1TCLK width low (DSC = 1)
L1RCLK, L1TCLK width high (DSC = 1)
P + 10
P + 10
—
—
ns
ns
3
83a
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
49
CPM Electrical Characteristics
Table 19. SI Timing (continued)
All Frequencies
Num
Characteristic
Unit
Min
Max
84
85
L1CLK edge to L1CLKO valid (DSC = 1)
—
30.00
—
ns
4
L1RQ valid before falling edge of L1TSYNC
1.00
L1TCL
K
2
86
87
88
L1GR setup time
42.00
42.00
—
—
—
ns
ns
ns
L1GR hold time
L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0, DSC = 0)
0.00
1
2
3
4
The ratio SYNCCLK/L1RCLK must be greater than 2.5/1.
These specs are valid for IDL mode only.
Where P = 1/CLKOUT. Thus, for a 25-MHz CLKO1 rate, P = 40 ns.
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever comes later.
L1RCLK
(FE = 0, CE = 0)
(Input)
71
70
71a
72
L1RCLK
(FE = 1, CE = 1)
(Input)
RFSD=1
75
74
L1RSYNC
(Input)
73
77
L1RXD
(Input)
BIT0
76
78
79
L1ST(4–1)
(Output)
Figure 51. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
50
Freescale Semiconductor
CPM Electrical Characteristics
L1RCLK
(FE = 1, CE = 1)
(Input)
72
83a
82
L1RCLK
(FE = 0, CE = 0)
(Input)
RFSD=1
75
L1RSYNC
(Input)
73
74
77
L1RXD
(Input)
BIT0
76
78
79
L1ST(4–1)
(Output)
84
L1CLKO
(Output)
Figure 52. SI Receive Timing with Double-Speed Clocking (DSC = 1)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
51
CPM Electrical Characteristics
L1TCLK
(FE = 0, CE = 0)
(Input)
71
70
72
L1TCLK
(FE = 1, CE = 1)
(Input)
73
TFSD=0
75
74
L1TSYNC
(Input)
80a
BIT0
80
81
L1TXD
(Output)
79
78
L1ST(4–1)
(Output)
Figure 53. SI Transmit Timing Diagram (DSC = 0)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
52
Freescale Semiconductor
CPM Electrical Characteristics
L1RCLK
(FE = 0, CE = 0)
(Input)
72
83a
82
L1RCLK
(FE = 1, CE = 1)
(Input)
TFSD=0
75
L1RSYNC
(Input)
73
74
81
L1TXD
(Output)
BIT0
80
78a
79
L1ST(4–1)
(Output)
78
84
L1CLKO
(Output)
Figure 54. SI Transmit Timing with Double Speed Clocking (DSC = 1)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
53
CPM Electrical Characteristics
Figure 55. IDL Timing
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
54
Freescale Semiconductor
CPM Electrical Characteristics
11.7 SCC in NMSI Mode Electrical Specifications
Table 20 provides the NMSI external clock timing.
Table 20. NMSI External Clock Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
1
100
101
102
103
104
105
106
107
108
RCLK1 and TCLK1 width high
1/SYNCCLK
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
RCLK1 and TCLK1 width low
1/SYNCCLK + 5
RCLK1 and TCLK1 rise/fall time
—
15.00
50.00
50.00
—
TXD1 active delay (from TCLK1 falling edge)
RTS1 active/inactive delay (from TCLK1 falling edge)
CTS1 setup time to TCLK1 rising edge
RXD1 setup time to RCLK1 rising edge
0.00
0.00
5.00
5.00
5.00
5.00
—
2
RXD1 hold time from RCLK1 rising edge
—
CD1 setup Time to RCLK1 rising edge
—
1
2
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 2.25/1.
Also applies to CD and CTS hold time when they are used as external sync signals.
Table 21 provides the NMSI internal clock timing.
Table 21. NMSI Internal Clock Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
1
100
102
103
104
105
106
107
108
RCLK1 and TCLK1 frequency
0.00
—
SYNCCLK/3
MHz
ns
RCLK1 and TCLK1 rise/fall time
—
30.00
30.00
—
TXD1 active delay (from TCLK1 falling edge)
RTS1 active/inactive delay (from TCLK1 falling edge)
CTS1 setup time to TCLK1 rising edge
RXD1 setup time to RCLK1 rising edge
0.00
0.00
40.00
40.00
0.00
40.00
ns
ns
ns
—
ns
2
RXD1 hold time from RCLK1 rising edge
—
ns
CD1 setup time to RCLK1 rising edge
—
ns
1
2
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 3/1.
Also applies to CD and CTS hold time when they are used as external sync signals.
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
55
CPM Electrical Characteristics
Figure 56 through Figure 58 show the NMSI timings.
RCLK1
102
102
101
106
100
RxD1
(Input)
107
108
CD1
(Input)
107
CD1
(SYNC Input)
Figure 56. SCC NMSI Receive Timing Diagram
TCLK1
102
102
101
100
TxD1
(Output)
103
105
RTS1
(Output)
104
104
CTS1
(Input)
107
CTS1
(SYNC Input)
Figure 57. SCC NMSI Transmit Timing Diagram
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
56
Freescale Semiconductor
CPM Electrical Characteristics
TCLK1
102
102
101
100
TxD1
(Output)
103
RTS1
(Output)
104
107
104
105
CTS1
(Echo Input)
Figure 58. HDLC Bus Timing Diagram
11.8 Ethernet Electrical Specifications
Table 22 provides the Ethernet timings as shown in Figure 59 through Figure 63.
Table 22. Ethernet Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
CLSN width high
RCLK1 rise/fall time
RCLK1 width low
RCLK1 clock period
RXD1 setup time
RXD1 hold time
40
—
—
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
80
20
5
1
120
—
—
RENA active delay (from RCLK1 rising edge of the last data bit)
10
100
—
—
RENA width low
TCLK1 rise/fall time
TCLK1 width low
—
15
—
40
99
10
10
10
10
1
TCLK1 clock period
101
50
50
50
50
TXD1 active delay (from TCLK1 rising edge)
TXD1 inactive delay (from TCLK1 rising edge)
TENA active delay (from TCLK1 rising edge)
TENA inactive delay (from TCLK1 rising edge)
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
57
CPM Electrical Characteristics
Table 22. Ethernet Timing (continued)
Characteristic
All Frequencies
Num
Unit
Min
Max
135
136
137
138
139
RSTRT active delay (from TCLK1 falling edge)
RSTRT inactive delay (from TCLK1 falling edge)
10
10
1
50
50
—
20
20
ns
ns
REJECT width low
CLK
ns
2
CLKO1 low to SDACK asserted
—
—
2
CLKO1 low to SDACK negated
ns
1
2
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 2/1.
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
CLSN(CTS1)
(Input)
120
Figure 59. Ethernet Collision Timing Diagram
RCLK1
121
121
124
123
RxD1
(Input)
Last Bit
125
126
127
RENA(CD1)
(Input)
Figure 60. Ethernet Receive Timing Diagram
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
58
Freescale Semiconductor
CPM Electrical Characteristics
TCLK1
128
128
129
131
121
TxD1
(Output)
132
133
134
TENA(RTS1)
(Input)
RENA(CD1)
(Input)
(Note 2)
Notes:
1. Transmit clock invert (TCI) bit in GSMR is set.
2. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the CSL bit is set in
the buffer descriptor at the end of the frame transmission.
Figure 61. Ethernet Transmit Timing Diagram
RCLK1
RxD1
(Input)
0
1
1
BIT1
125
BIT2
136
Start Frame Delimiter
RSTRT
(Output)
Figure 62. CAM Interface Receive Start Timing Diagram
REJECT
137
Figure 63. CAM Interface REJECT Timing Diagram
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
59
CPM Electrical Characteristics
11.9 SMC Transparent AC Electrical Specifications
Table 23 provides the SMC transparent timings as shown in Figure 64.
Table 23. SMC Transparent Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
1
150
151
SMCLK clock period
SMCLK width low
100
50
50
—
—
—
—
15
50
—
—
ns
ns
ns
ns
ns
ns
ns
151A SMCLK width high
152
153
154
155
SMCLK rise/fall time
SMTXD active delay (from SMCLK falling edge)
SMRXD/SMSYNC setup time
10
20
5
RXD1/SMSYNC hold time
1
SYNCCLK must be at least twice as fast as SMCLK.
SMCLK
151A
150
152
152
151
SMTXD
(Output)
Note 1
154
153
155
SMSYNC
154
155
SMRXD
(Input)
Note:
1. This delay is equal to an integer number of character-length clocks.
Figure 64. SMC Transparent Timing Diagram
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
60
Freescale Semiconductor
CPM Electrical Characteristics
11.10 SPI Master AC Electrical Specifications
Table 24 provides the SPI master timings as shown in Figure 65 and Figure 66.
Table 24. SPI Master Timing
All Frequencies
Unit
Num
Characteristic
Min
Max
160
161
162
163
164
165
166
167
MASTER cycle time
4
2
1024
512
—
t
t
cyc
cyc
MASTER clock (SCK) high or low time
MASTER data setup time (inputs)
Master data hold time (inputs)
Master data valid (after SCK edge)
Master data hold time (outputs)
Rise time output
50
0
ns
ns
ns
ns
ns
ns
—
—
0
20
—
—
—
15
Fall time output
15
SPICLK
(CI = 0)
(Output)
161
161
167
166
166
167
160
SPICLK
(CI = 1)
(Output)
163
162
SPIMISO
msb
167
Data
165
lsb
msb
(Input)
164
166
SPIMOSI
(Output)
msb
Data
lsb
msb
Figure 65. SPI Master (CP = 0) Timing Diagram
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
61
CPM Electrical Characteristics
SPICLK
(CI = 0)
(Output)
161
167
166
166
167
161
160
SPICLK
(CI = 1)
(Output)
163
162
SPIMISO
(Input)
msb
167
Data
165
lsb
msb
164
166
SPIMOSI
(Output)
msb
Data
lsb
msb
Figure 66. SPI Master (CP = 1) Timing Diagram
11.11 SPI Slave AC Electrical Specifications
Table 25 provides the SPI slave timings as shown in Figure 67 and Figure 68.
Table 25. SPI Slave Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
170
171
172
173
174
175
176
177
Slave cycle time
2
15
15
1
—
—
—
—
—
—
—
50
t
cyc
Slave enable lead time
Slave enable lag time
ns
ns
Slave clock (SPICLK) high or low time
Slave sequential transfer delay (does not require deselect)
Slave data setup time (inputs)
t
cyc
cyc
1
t
20
20
—
ns
ns
ns
Slave data hold time (inputs)
Slave access time
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
62
Freescale Semiconductor
CPM Electrical Characteristics
SPISEL
(Input)
172
171
174
SPICLK
(CI = 0)
(Input)
173
182
181
173
170
SPICLK
(CI = 1)
(Input)
177
181
182
180
178
Undef
SPIMISO
(Output)
msb
175
Data
lsb
msb
msb
179
176
181 182
lsb
SPIMOSI
(Input)
msb
Data
Figure 67. SPI Slave (CP = 0) Timing Diagram
SPISEL
(Input)
172
174
171
170
SPICLK
(CI = 0)
(Input)
173
182
181
182
173
181
SPICLK
(CI = 1)
(Input)
177
180
178
SPIMISO
(Output)
msb
msb
msb
Undef
175
Data
lsb
179
176
msb
181 182
Data
SPIMOSI
(Input)
lsb
Figure 68. SPI Slave (CP = 1) Timing Diagram
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
63
CPM Electrical Characteristics
2
11.12 I C AC Electrical Specifications
2
Table 26 provides the I C (SCL < 100 kHz) timings.
2
Table 26. I C Timing (SCL < 100 kHZ)
All Frequencies
Num
Characteristic
Unit
Min
Max
200
200
202
203
204
205
206
207
208
209
210
211
SCL clock frequency (slave)
SCL clock frequency (master)
0
100
100
—
kHz
kHz
μs
1
1.5
4.7
4.7
4.0
4.7
4.0
0
Bus free time between transmissions
Low period of SCL
—
μs
High period of SCL
—
μs
Start condition setup time
Start condition hold time
Data hold time
—
μs
—
μs
—
μs
Data setup time
250
—
—
ns
SDL/SCL rise time
1
μs
SDL/SCL fall time
—
300
—
ns
Stop condition setup time
4.7
μs
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3 × pre_scaler × 2).
The ratio SYNCCLK/(BRGCLK/pre_scaler) must be greater than or equal to 4/1.
2
Table 27 provides the I C (SCL > 100 kHz) timings.
2
Table 27. . I C Timing (SCL > 100 kHZ)
All Frequencies
Num
Characteristic
Expression
Unit
Min
Max
200
200
202
203
204
205
206
207
208
209
210
211
SCL clock frequency (slave)
fSCL
fSCL
0
BRGCLK/48
Hz
Hz
s
1
SCL clock frequency (master)
BRGCLK/16512
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
0
BRGCLK/48
Bus free time between transmissions
Low period of SCL
—
—
s
High period of SCL
—
s
Start condition setup time
Start condition hold time
Data hold time
—
s
—
s
—
—
s
Data setup time
1/(40 * fSCL)
—
s
SDL/SCL rise time
1/(10 * fSCL)
1/(33 * fSCL)
—
s
SDL/SCL fall time
—
s
Stop condition setup time
1/2(2.2 * fSCL)
s
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) × pre_scaler × 2).
The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater than or equal to 4/1.
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
64
Freescale Semiconductor
UTOPIA AC Electrical Specifications
2
Figure 69 shows the I C bus timing.
SDA
202
203
204
208
205
207
SCL
206
209
210
211
2
Figure 69. I C Bus Timing Diagram
12 UTOPIA AC Electrical Specifications
Table 28 shows the AC electrical specifications for the UTOPIA interface.
Table 28. UTOPIA AC Electrical Specifications
Num
Signal Characteristic
Direction
Min
Max
Unit
U1
UtpClk rise/fall time (Internal clock option)
Output
—
50
—
—
40
—
2
3.5
50
50
3.5
60
50
16
—
ns
%
Duty cycle
Frequency
MHz
ns
U1a UtpClk rise/fall time (external clock option)
Input
Duty cycle
Frequency
%
MHz
ns
U2
U3
U4
U5
RxEnb and TxEnb active delay
Output
Input
UTPB, SOC, Rxclav and Txclav setup time
UTPB, SOC, Rxclav and Txclav hold time
8
ns
Input
1
—
ns
UTPB, SOC active delay (and PHREQ and PHSEL active delay in
MPHY mode)
Output
2
16
ns
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
65
UTOPIA AC Electrical Specifications
Figure 70 shows signal timings during UTOPIA receive operations.
U1
U1
UtpClk
U5
PHREQn
U3
U4
RxClav
U2
RxEnb
U3
U4
UTPB
SOC
Figure 70. UTOPIA Receive Timing
Figure 71 shows signal timings during UTOPIA transmit operations.
U1
U1
UtpClk
U5
PHSELn
TxClav
U4
U3
U2
TxEnb
U5
UTPB
SOC
Figure 71. UTOPIA Transmit Timing
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
66
Freescale Semiconductor
FEC Electrical Characteristics
13 FEC Electrical Characteristics
This section provides the AC electrical specifications for the Fast Ethernet controller (FEC). Note that the
timing specifications for the MII signals are independent of system clock frequency (part speed
designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or
3.3 V.
13.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV, MII_RX_ER,
MII_RX_CLK)
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_RX_CLK frequency – 1%.
Table 29 provides information on the MII receive signal timing.
Table 29. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
M2
M3
MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup
MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold
MII_RX_CLK pulse width high
5
5
—
—
ns
ns
35%
65%
MII_RX_CLK
period
M4
MII_RX_CLK pulse width low
35%
65%
MII_RX_CLK
period
Figure 72 shows MII receive signal timing.
M3
MII_RX_CLK (Input)
M4
MII_RXD[3:0] (Inputs)
MII_RX_DV
MII_RX_ER
M1
M2
Figure 72. MII Receive Signal Timing Diagram
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
67
FEC Electrical Characteristics
13.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN,
MII_TX_ER, MII_TX_CLK)
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_TX_CLK frequency – 1%.
Table 30 provides information on the MII transmit signal timing.
Table 30. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
M6
M7
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid
MII_TX_CLK pulse width high
5
—
25
ns
—
35
65%
MII_TX_CLK
period
M8
MII_TX_CLK pulse width low
35%
65%
MII_TX_CLK
period
Figure 73 shows the MII transmit signal timing diagram.
M7
MII_TX_CLK (Input)
RMII_REFCLK
M5
M8
MII_TXD[3:0] (Outputs)
MII_TX_EN
MII_TX_ER
M6
Figure 73. MII Transmit Signal Timing Diagram
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
68
Freescale Semiconductor
FEC Electrical Characteristics
13.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 31 provides information on the MII async inputs signal timing.
Table 31. MII Async Inputs Signal Timing
Num
Characteristic
Min
Max
Unit
M9
MII_CRS, MII_COL minimum pulse width
1.5
—
MII_TX_CLK
period
Figure 74 shows the MII asynchronous inputs signal timing diagram.
MII_CRS, MII_COL
M9
Figure 74. MII Async Inputs Timing Diagram
13.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table 32 provides information on the MII serial management channel signal timing. The FEC functions
correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under
investigation.
Table 32. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10 MII_MDC falling edge to MII_MDIO output invalid (minimum propagation
delay)
0
—
ns
M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay)
M12 MII_MDIO (input) to MII_MDC rising edge setup
M13 MII_MDIO (input) to MII_MDC rising edge hold
M14 MII_MDC pulse width high
—
10
25
—
ns
ns
ns
0
—
40%
60%
MII_MDC
period
M15 MII_MDC pulse width low
40%
60%
MII_MDC
period
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
69
Mechanical Data and Ordering Information
Figure 75 shows the MII serial management channel timing diagram.
M14
MM15
MII_MDC (Output)
MII_MDIO (Output)
M10
M11
MII_MDIO (Input)
M12
M13
Figure 75. MII Serial Management Channel Timing Diagram
14 Mechanical Data and Ordering Information
Table 33 provides information on the MPC860 Revision D.4 derivative devices.
Table 33. MPC860 Family Revision D.4 Derivatives
2
Number of Ethernet Support
Multichannel
HDLC Support Support
ATM
Device
1
SCCs
(Mbps)
MPC855T
1
2
10/100
10
Yes
N/A
Yes
Yes
N/A
Yes
Yes
Yes
Yes
N/A
Yes
Yes
N/A
Yes
Yes
Yes
MPC860DE
MPC860DT
MPC860DP
MPC860EN
MPC860SR
MPC860T
10/100
10/100
10
4
10
10/100
10/100
MPC860P
1
Serial communications controller (SCC)
Up to 4 channels at 40 MHz or 2 channels at 25 MHz
2
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
70
Freescale Semiconductor
Mechanical Data and Ordering Information
Table 34 identifies the packages and operating frequencies available for the MPC860.
Table 34. MPC860 Family Package/Frequency Availability
Freq. (MHz) /
Temp. (Tj)
Package Type
Package
Order Number
1
Ball grid array
ZP suffix—leaded
ZQ suffix—leaded
VR suffix—lead-free are available as needed
50
ZP/ZQ
MPC855TZQ50D4
MPC860DEZQ50D4
MPC860DTZQ50D4
MPC860ENZQ50D4
MPC860SRZQ50D4
MPC860TZQ50D4
MPC860DPZQ50D4
MPC860PZQ50D4
0° to 95°C
Tape and Reel MPC855TZQ50D4R2
MPC860DEZQ50D4R2
MPC860ENZQ50D4R2
MPC860SRZQ50D4R2
MPC860TZQ50D4R2
MPC860DPZQ50D4R2
Sample
KMPC855TZQ50D4
KMPC860DEZQ50D4
KMPC860DTZQ50D4
KMPC860TZQ50D4
KMPC860SRZQ50D4
1
66
ZP/ZQ
MPC855TZQ66D4
MPC860DEZQ66D4
MPC860DTZQ66D4
MPC860ENZQ66D4
MPC860SRZQ66D4
MPC860TZQ66D4
MPC860DPZQ66D4
MPC860PZQ66D4
0° to 95°C
Tape and Reel MPC860SRZQ66D4R2
MPC860PZQ66D4R2
Sample
KMPC855TZQ66D4
KMPC860SRZQ66D4
KMPC860TZQ66D4
KMPC860ENZQ66D4
KMPC860PZQ66D4
1
80
ZP/ZQ
MPC855TZQ80D4
MPC860DEZQ80D4
MPC860DTZQ80D4
MPC860ENZQ80D4
MPC860SRZQ80D4
MPC860TZQ80D4
MPC860DPZQ80D4
MPC860PZQ80D4
0° to 95°C
Tape and Reel MPC860PZQ80D4R2
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
71
Mechanical Data and Ordering Information
Table 34. MPC860 Family Package/Frequency Availability (continued)
Freq. (MHz) /
Temp. (Tj)
Package Type
Package
Order Number
Sample
KMPC855TZQ80D4
KMPC860DEZQ80D4
KMPC860DTZQ80D4
KMPC860ENZQ80D4
KMPC860SRZQ80D4
KMPC860TZQ80D4
KMPC860DPZQ80D4
KMPC860PZQ80D4
1
Ball grid array (CZP suffix)
CZP suffix—leaded
CZQ suffix—leaded
CVR suffix—lead-free are available as needed
50
ZP/ZQ
MPC855TCZQ50D4
MPC860DECZQ50D4
MPC860DTCZQ50D4
MPC860ENCZQ50D4
MPC860SRCZQ50D4
MPC860TCZQ50D4
MPC860DPCZQ50D4
MPC860PCZQ50D4
–40° to 95°C
Tape and Reel MPC855TCZQ50D4R2
1
66
ZP/ZQ
MPC855TCZQ66D4
MPC860ENCZQ66D4
MPC860SRCZQ66D4
MPC860TCZQ66D4
MPC860DPCZQ66D4
MPC860PCZQ66D4
–40° to 95°C
1
The ZP package is no longer recommended for use. The ZQ package replaces the ZP package.
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
72
Freescale Semiconductor
Mechanical Data and Ordering Information
14.1 Pin Assignments
Figure 76 shows the top view pinout of the PBGA package. For additional information, see the MPC860
PowerQUICC User’s Manual, or the MPC855T User’s Manual.
NOTE: This is the top view of the device.
W
PD10 PD8
PD14 PD13 PD9
PA0 PB14 PD15
PD3
IRQ7 D0
D4
D1
D2
D10
D11
D9
D3
D5
VDDL
D20
D6
D7
D29
DP1
DP2 CLKOUT IPA3
V
U
T
VSSSYN1
N/C
PD6 M_Tx_EN IRQ0 D13
D27
D23
D17
D14
D16
D15
D18
D19
D22
D24
D26
D31
D28
DP3
DP0
PD4
PD5 IRQ1
D8
D21
D30 IPA5 IPA4 IPA2
IPA6 IPA0 IPA1 IPA7
N/C VSSSYN
XFC VDDSYN
PA1
PC6
PC5
PC4 PD11
PD7 VDDH D12
VDDH
D25
R
P
N
M
L
VDDH
WAIT_B WAIT_A
VDDL RSTCONF
PA2 PB15 PD12
KAPWR
PORESET
SRESET
PA4 PB17 PA3 VDDL
PB19 PA5 PB18 P B16
GND
GND
XTAL
TEXP
HRESET
EXTCLK EXTAL
PA7
PC8
PA6
PC7
BADDR28
MODCK2
OP0
BADDR29 VDDL
OP1 MODCK1
PB22 PC9
PA8 PB20
AS
K
J
PC10 PA9 PB23 PB21
PC11 PB24 PA10 PB25
GND
BADDR30 IPB6 ALEA IRQ4
IPB5 IPB1 IPB2 ALEB
M_COL IRQ2 IPB0 IPB7
H
G
F
VDDL M_MDIO TDI
TCK
TRST TMS TDO PA11
PB26 PC12 PA12 VDDL
PB27 PC13 PA13 PB29
PB28 PC14 PA14 PC15
BR
VDDL
CS3
IRQ6 IPB4 IPB3
GND
GND
TS
BI
IRQ3 BURST
VDDH
VDDH
CS6
E
D
C
B
A
BG
BB
A8
A9
N/C
A12
A13
N/C
A16
A17
A15
A20
A21
A19
A24
A23
A25
A18 BSA0 GPLA0 N/C
CS2 GPLA5 BDIP TEA
PB30 PA15 PB31
A3
A6
A26 TSIZ1 BSA1 WE0 GPLA1 GPLA3 CS7
CS0
TA GPLA4
A0
19
A1
A4
A10
A22 TSIZ0 BSA3 M_CRS WE2 GPLA2 CS5 CE1A WR GPLB4
A2
18
A5
17
A7
16
A11
15
A14
14
A27
13
A29
12
A30
11
A28
10
A31 VDDL BSA2 WE1 WE3 CS4 CE2A CS1
9
8
7
6
5
4
3
2
1
Figure 76. Pinout of the PBGA Package
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
73
Mechanical Data and Ordering Information
14.2 Mechanical Dimensions of the PBGA Package
Figure 77 shows the mechanical dimensions of the ZP PBGA package.
C
0.2
4X
0.2
C
D
A
0.25
C
0.35
C
E2
E
D2
B
TOP VIEW
A2
A3
A1
A
D1
SIDE VIEW
18X e
W
V
U
T
R
P
N
M
L
K
J
E1
H
G
F
MILLIMETERS
E
D
C
B
A
DIM MIN
MAX
2.05
0.70
1.35
0.90
0.90
A
A1
A2
A3
b
---
0.50
0.95
0.70
0.60
1
3
5
7
9
11 13 15 17 19
2
4 6 8 10 12 14 16 18
357X
b
BOTTOM VIEW
M
0.3
C A B
C
D
25.00 BSC
22.86 BSC
M
0.15
D1
D2
e
22.40
22.60
1.27 BSC
25.00 BSC
22.86 BSC
E
NOTE
E1
E2
1.
Dimensions and tolerance per ASME Y14.5M, 1994.
Dimensions in millimeters.
22.40
22.60
2.
3.
Dimension b is the maximum solder ball diameter measured parallel
to data C.
Figure 77. Mechanical Dimensions and Bottom Surface Nomenclature of the ZP PBGA Package
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
74
Freescale Semiconductor
Mechanical Data and Ordering Information
Figure 78 shows the mechanical dimensions of the ZQ PBGA package.
NOTE
1.
2.
3.
4.
All Dimensions in millimeters.
Dimensions and tolerance per ASME Y14.5M, 1994.
Maximum Solder Ball Diameter measured parallel to Datum A.
Datum A, the seating plane, is defined by the spherical crowns of the solder balls.
Figure 78. Mechanical Dimensions and Bottom Surface Nomenclature of the ZQ PBGA Package
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
75
Document Revision History
15 Document Revision History
Table 35 lists significant changes between revisions of this hardware specification.
Table 35. Document Revision History
Revision
Date
Changes
5.1
11/2001
• Revised template format, removed references to MAC functionality, changed Table 7
B23 max value @ 66 MHz from 2ns to 8ns, added this revision history table
6
10/2002
11/2002
• Added the MPC855T. Corrected Figure 26 on page -36.
6.1
• Corrected UTOPIA RXenb* and TXenb* timing values
• Changed incorrect usage of Vcc to Vdd
• Corrected dual port RAM to 8 Kbytes
6.2
8/2003
• Changed B28a through B28d and B29d to show that TRLX can be 0 or 1
• Changed reference documentation to reflect the Rev 2 MPC860 PowerQUICC Family
Users Manual
• Nontechnical reformatting
6.3
7.0
9/2003
9/2004
• •Added Section 11.2 on the Port C interrupt pins
• •Nontechnical reformatting
• Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL
Max of the I2C Standard
• Replaced the thermal characteristics in Table 4 by the ZQ package
• Add the new parts to the Ordering and Availablity Chart in Table 34
• Added the mechanical spec of the ZQ package in Figure 78
• Removed all of the old revisions from Table 5
8
08/2007
• Updated template.
• On page 1, added a second paragraph.
• After Table 2, inserted a new figure showing the undershoot/overshoot voltage
(Figure 1) and renumbered the rest of the figures.
• In Figure 3, changed all reference voltage measurement points from 0.2 and 0.8 V to
50% level.
• In Table 16, changed num 46 description to read, “TA assertion to rising edge ...”
• In Figure 46, changed TA to reflect the rising edge of the clock.
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
76
Freescale Semiconductor
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
77
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
78
Freescale Semiconductor
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Freescale Semiconductor
79
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
+1-800-521-6274 or
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
+1-480-768-2130
www.freescale.com/support
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064
Japan
0120 191014 or
+81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Semiconductor was negligent regarding the design or manufacture of the part.
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
The Power Architecture and Power.org word marks and the Power and Power.org logos
and related marks are trademarks and service marks licensed by Power.org. IEEE
802.3, 802.3u, and 1149.1 are trademarks or registered trademarks of the Institute of
Electrical and Electronics Engineers, Inc. (IEEE). This product is not endorsed or
approved by the IEEE. All other product or service names are the property of their
respective owners.
For Literature Requests Only:
Freescale Semiconductor
Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
+1-800 441-2447 or
© Freescale Semiconductor, Inc., 2001–2007. All rights reserved.
+1-303-675-2140
Fax: +1-303-675-2150
LDCForFreescaleSemiconductor
@hibbertgroup.com
Document Number: MPC860EC
Rev. 8
08/2007
Contact Us Worldwide: United States
Applications Technologies Support
Products
Buy
Freescale Search
Search
Results 2
Remove
Help
MPC855TVR50D4
Refine Your Results
- MPC855TVR50D4
Expand All
Show:
Orderable Parts
|
Results Refined By : Resources
>
Orderable Parts
Order
Part Number
Datasheet/
Part Data
Sub Topics
Expand All
Device Type
Industry
MPC855TVR50D4
MPC855TVR50D4R2
Related Links
Download Newly Introduced Parts
(200KB)
Download Phased Out Parts (250KB)
Samples FAQ
Request for a Sample Order Advice
Looking for Discussion Forums
www.freescale.com
Site Map
Terms of Use
Privacy Practices
Newsletter
View Agreement
RSS Feeds
©
相关型号:
KMPC860TZQ66D4
32-BIT, 66MHz, RISC PROCESSOR, PBGA357, 25 X 25 MM, 1.27 MM PITCH, PLASTIC, BGA-357
NXP
KMPC860TZQ80D4
32-BIT, 80MHz, RISC PROCESSOR, PBGA357, 25 X 25 MM, 1.27 MM PITCH, PLASTIC, BGA-357
NXP
KMPC866TZP133
RISC Microprocessor, 32-Bit, 133MHz, CMOS, PBGA256, 23 X 23 MM, PLASTIC, BGA-256
MOTOROLA
KMPC866TZP133A
32-BIT, 133MHz, RISC PROCESSOR, PBGA357, 25 X 25 MM, 1.27 MM PITCH, PLASTIC, BGA-357
NXP
©2020 ICPDF网 联系我们和版权申明