LH75411N0Q100C0,55_技术文档

IMPORTANT NOTICE

Dear customer,

As from June 1^st, 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from

Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data

sheets where the previous Sharp or Sharp Corporation references remain, please use the new

links as shown below.

For www.sharpsma.com use www.nxp.com/microcontrollers

for indicated sales addresses use salesaddresses@nxp.com (email)

The copyright notice at the bottom of each page (or elsewhere in the document, depending on the

version)

is replaced with:

If you have any questions related to the data sheet, please contact our nearest sales office via

e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and

understanding, In addition to that the Annex A (attached hereto) is added to the document.

NXP Semiconductors

LH75401/LH75411

System-on-Chip

Product data sheet

• JTAG Debug Interface and Boundary Scan

• Single 3.3 V Supply

DESCRIPTION

The NXP BlueStreak LH75401/LH75411 family con-

sists of two low-cost 16/32-bit System-on-Chip (SoC)

devices.

• 5 V Tolerant Digital I/O

– XTALIN and XTAL32IN inputs are 1.8 V ± 10 %

• LH75401 — contains the superset of features.

• 144-pin LQFP Package

• LH75411 — similar to LH75401, without CAN 2.0B.

• 40C to +85C Operating Temperature

COMMON FEATURES

• Highly Integrated System-on-Chip

• ARM7TDMI-S™ Core

Unique Features of the LH75401

• Color and Grayscale Liquid Crystal Display (LCD)

Controller

– 12-bit (4,096) Direct Mode Color, up to VGA

– 8-bit (256) Direct or Palettized Color, up to SVGA

– 4-bit (16) Direct Mode Color/Grayscale, up to XGA

– 12-bit Video Bus

– Supports STN, TFT, HR-TFT, and AD-TFT

Displays.

• High Performance (84 MHz CPU Speed)

– Internal PLL Driven or External Clock Driven

– Crystal Oscillator/Internal PLL Can Operate with

Input Frequency Range of 14 MHz to 20 MHz

• 32 kB On-chip SRAM

– 16 kB Tightly Coupled Memory (TCM) SRAM

– 16 kB Internal SRAM

• CAN Controller that supports CAN version 2.0B.

• Clock and Power Management

Unique Features of the LH75411

– Low Power Modes: Standby, Sleep, Stop

• Color and Grayscale LCD Controller (LCDC)

– 12-bit (4,096) Direct Mode Color, up to VGA

– 8-bit (256) Direct or Palettized Color, up to SVGA

– 4-bit (16) Direct Mode Color/Grayscale, up to XGA

– 12-bit Video Bus

• Eight Channel, 10-bit Analog-to-Digital Converter

• Integrated Touch Screen Controller

• Serial interfaces

– Two 16C550-type UARTs supporting baud rates

up to 921,600 baud (requires crystal frequency of

14.756 MHz).

– Supports STN, TFT, HR-TFT, and AD-TFT

Displays.

– One 82510-type UART supporting baud rates up

to 3,225,600 baud (requires a system clock of

70 MHz).

• Synchronous Serial Port

– Motorola SPI™

– National Semiconductor Microwire™

– Texas Instruments SSI

• Real-Time Clock (RTC)

• Three Counter/Timers

– Capture/Compare/PWM Compatibility

– Watchdog Timer (WDT)

• Low-Voltage Detector

Product data sheet

1

LH75401/LH75411

System-on-Chip

NXP Semiconductors

ORDERING INFORMATION

Table 1. Ordering information

Package

Type number

Version

Name

Description

plastic low profile quad flat package; 144 leads;

body 20 x 20 x 1.4 mm

LH75401N0Q100C0

LH75411N0Q100C0

LQFP144

SOT486-1

plastic low profile quad flat package; 144 leads;

body 20 x 20 x 1.4 mm

2

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

LH75401 BLOCK DIAGRAM

LH75401

14 to 20 MHz 32.768 kHz

OSCILLATOR,

PLL, POWER

MANAGEMENT, and

RESET CONTROL

REAL TIME

CLOCK

76-BIT GENERAL

PURPOSE I/O

INTERNAL

16KB SRAM

AHB

INTERFACE

ARM7TDMI-S

I/O

VECTORED

INTERRUPT

CONTROLLER

CONFIGURATION

TCM

16KB SRAM

SYNCHRONOUS

SERIAL PORT

4 CHANNEL

DMA

CONTROLLER

TIMER (3)

STATIC

MEMORY

CONTROLLER

ADVANCED

PERIPHERAL

BUS BRIDGE

WATCHDOG

TIMER

COLOR

LCD

CONTROLLER

CAN 2.0B

UART (3)

BROWNOUT

DETECTOR

ADVANCED

LCD

LINEAR

REGULATOR

INTERFACE

8 CHANNEL

10-BIT ADC

TOUCH PANEL

INTERFACE

ADVANCED HIGH

ADVANCED

PERFORMANCE

BUS (AHB)

PERPHERAL

BUS (APB)

LH75401-1

Figure 1. LH75401 Block Diagram

Product data sheet

Rev. 02 — 19 March 2009

3

LH75401/LH75411

System-on-Chip

NXP Semiconductors

LH75411 BLOCK DIAGRAM

LH75411

14 to 20 MHz 32.768 kHz

OSCILLATOR,

PLL, POWER

MANAGEMENT, and

RESET CONTROL

REAL TIME

CLOCK

76-BIT GENERAL

PURPOSE I/O

INTERNAL

16KB SRAM

AHB

INTERFACE

ARM 7TDMI-S

I/O

VECTORED

INTERRUPT

CONTROLLER

CONFIGURATION

TCM

16KB SRAM

SYNCHRONOUS

SERIAL PORT

4 CHANNEL

DMA

CONTROLLER

TIMER (3)

STATIC

MEMORY

CONTROLLER

ADVANCED

PERIPHERAL

BUS BRIDGE

WATCHDOG

TIMER

COLOR

LCD

UART (3)

CONTROLLER

BROWNOUT

DETECTOR

8 CHANNEL

10-BIT ADC

ADVANCED

LCD

INTERFACE

LINEAR

REGULATOR

TOUCH PANEL

INTERFACE

ADVANCED HIGH

ADVANCED

PERFORMANCE

BUS (AHB)

PERPHERAL

BUS (APB)

LH75411-1

Figure 2. LH75411 Block Diagram

4

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

PIN CONFIGURATION

1

108

LH75400/

LH75401/

LH75410/

LH75411

36

73

002aad207

Figure 3. LH75401/LH75411 pin configuration

Product data sheet

Rev. 02 — 19 March 2009

5

LH75401/LH75411

System-on-Chip

NXP Semiconductors

LH75401 Numerical Pin Listing

Table 2. LH75401 Numerical Pin List

PIN FUNCTION

NO. AT RESET

FUNCTION FUNCTION FUNCTION OUTPUT

BUFFER

BEHAVIOR DURING

NOTES

2

3

TYPE

DRIVE

8 mA

None

8 mA

None

8 mA

None

8 mA

None

8 mA

None

8 mA

TYPE

RESET

Pull-up

1

2

PA7

PA6

VDD

PA5

PA4

PA3

PA2

VSS

PA1

PA0

VDDC

D7

D15

D14

I/O

Bidirectional

1

I/O

3

Power

I/O

4

D13

D12

D11

D10

Bidirectional

1

Pull-up

5

I/O

6

I/O

7

I/O

8

Ground

I/O

9

D9

D8

Bidirectional

1

Pull-up

10

11

12

13

14

15

16

17

18

19

20

I/O

Power

I/O

Bidirectional

Pull-up

D6

I/O

VSSC

D5

Ground

I/O

Bidirectional

Pull-up

D4

I/O

VDD

D3

Power

I/O

Bidirectional

Pull-up

D2

I/O

D1

I/O

21

22

23

24

25

26

27

D0

I/O

8 mA

None

8 mA

Bidirectional

Output

Pull-up

HIGH

nWE

nOE

PB5

PB4

VSS

PB3

3

Output

HIGH

3

nWAIT

nBLE1

Bidirectional

Pull-up

1, 3

Pull-up

Ground

nBLE0

nCS3

nCS2

nCS1

Bidirectional

1, 3

Pull-up

28

29

30

PB2

PB1

PB0

8 mA

31

32

33

34

35

36

37

38

nCS0

PC7

PC6

VDD

PC5

PC4

PC3

PC2

8 mA

None

8 mA

Output

3

1

Pull-up

A23

A22

Bidirectional

Pull-down

Power

A21

A20

A19

A18

Bidirectional

Pull-down

1

6

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

Table 2. LH75401 Numerical Pin List (Cont’d)

PIN FUNCTION

NO. AT RESET

FUNCTION FUNCTION FUNCTION OUTPUT

BUFFER

TYPE

BEHAVIOR DURING

NOTES

2

3

TYPE

DRIVE

RESET

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

PC1

PC0

VSS

VDD

A15

A17

A16

8 mA

None

8 mA

None

8 mA

None

8 mA

None

8 mA

None

8 mA

None

4 mA

None

8 mA

6 mA

8 mA

None

8 mA

2 mA

6 mA

2 mA

None

Bidirectional

Pull-down

1

Ground

Power

Output

LOW

A14

A13

A12

A11

VSS

A10

Ground

Output

LOW

A9

A8

A7

A6

VDD

A5

Power

Output

LOW

A4

A3

A2

VSS

A1

Ground

Output

Input

LOW

A0

nRESETIN

TEST2

TEST1

TMS

RTCK

TCK

TDI

Pull-up

2, 3

2

Input

2

Input

2

Output

Input

Pull-up

2

TDO

LINREGEN

Output

Input

5

3

71 nRESETOUT

Output

Bidirectional

72

73

74

75

76

77

78

79

80

PD6

PD5

INT6

INT5

INT4

DREQ

DACK

Pull-down

Pull-up

1

1, 2

1

PD4

UARTRX1

VDDC

PD3

Power

INT3

INT2

INT1

INT0

UARTTX1

Bidirectional

Pull-up

1

PD2

PD1

1, 2

1

PD0

VSSC

Ground

Product data sheet

Rev. 02 — 19 March 2009

7

LH75401/LH75411

System-on-Chip

NXP Semiconductors

Table 2. LH75401 Numerical Pin List (Cont’d)

PIN FUNCTION

NO. AT RESET

FUNCTION FUNCTION FUNCTION OUTPUT

BUFFER

TYPE

BEHAVIOR DURING

NOTES

2

3

TYPE

DRIVE

RESET

81

82

nPOR

None

4 mA

8 mA

2 mA

4 mA

None

4 mA

None

4 mA

None

8 mA

Input

Pull-up

2, 3

4

XTAL32IN

Input

83 XTAL32OUT

Output

84

85

86

87

88

89

VSSA_PLL

VDDA_PLL

XTALIN

Ground

Power

Input

4

XTALOUT

VSSA_ADC

AN3 (LR/Y-)

Output

Ground

PJ7

PJ6

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

Input

90 AN4 (Wiper)

91 AN9

92 AN2 (LL/Y+)

93 AN8

94 AN1 (UR/X-)

95 AN6

96 AN0 (UL/X+)

97

VDDA_ADC

VDD

PE7

PE6

PE5

PE4

PE3

PE2

PE1

VSS

PE0

PF6

Power

98

99

SSPFRM

SSPCLK

SSPRX

Bidirectional

Pull-up

Pull-down

Pull-up

1

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

SSPTX

Pull-down

Pull-up

CANTX

UARTTX0

UARTRX0

CANRX

UARTTX2

Pull-up

Ground

UARTRX2

CTCAP2B

CTCAP2A

CTCAP1B

CTCAP1A

Bidirectional

Pull-up

1

2

CTCMP2B

CTCMP2A

CACMP1B

CTCMP1A

PF5

PF4

2

PF3

VDD

PF2

Power

CTCAP0E

CTCAP0D

CTCAP0C

CTCAP0B

CTCAP0A

CTCLK

Bidirectional

2

PF1

PF0

PG7

PG6

PG5

VSS

PG4

PG3

PG2

CTCMP0B

CTCMP0A

Ground

LCDVEEEN

LCDVDDEN

LCDMOD

Bidirectional

LCDDSPLEN LCDREV

8

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

Table 2. LH75401 Numerical Pin List (Cont’d)

PIN FUNCTION

NO. AT RESET

FUNCTION FUNCTION FUNCTION OUTPUT

BUFFER

TYPE

BEHAVIOR DURING

RESET

NOTES

2

3

TYPE

DRIVE

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

PG1

PG0

PH7

VDD

VSS

PH6

PH5

PH4

PH3

PH2

PH1

VDD

PH0

PI7

LCDCLS

LCDPS

8 mA

None

8 mA

None

8 mA

None

8 mA

Bidirectional

LCDDCLK

Power

Ground

LCDLP

LCDFP

LCDHRLP

LCDSPS

LCDSPL

Bidirectional

LCDEN

LCDVD11

LCDVD10

LCDVD9

Power

LCDVD8

LCDVD7

LCDVD6

LCDVD5

LCDVD4

Bidirectional

PI6

PI5

PI4

VSS

PI3

Ground

LCDVD3

LCDVD2

LCDVD1

LCDVD0

Bidirectional

PI2

PI1

PI0

NOTES:

1. Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral.

2. CMOS Schmitt trigger input.

3. Signals preceded with ‘n’ are active LOW.

4. Crystal Oscillator Inputs should be driven to 1.8 V ±10 % (MAX.)

5. LINREGEN activation requires a 0  pull-up to VDD.

Product data sheet

Rev. 02 — 19 March 2009

9

LH75401/LH75411

System-on-Chip

NXP Semiconductors

LH75401 Signal Descriptions

Table 3. LH75401 Signal Descriptions

PIN NO. SIGNAL NAME

TYPE

DESCRIPTION

NOTES

MEMORY INTERFACE (MI)

1

2

4

5

6

7

9

10

12

D[15:0]

Input/Output Data Input/Output Signals

1

13

15

16

18

19

20

21

22

23

24

25

27

28

29

30

31

nWE

Output

Input

Static Memory Controller Write Enable

2

nOE

Static Memory Controller Output Enable

Static Memory Controller External Wait Control

Static Memory Controller Byte Lane Strobe

Static Memory Controller Chip Select

2

nWAIT

nBLE1

nBLE0

nCS3

nCS2

nCS1

nCS0

1, 2

2

Output

32

33

35

36

37

38

39

40

43

44

45

46

47

49

50

51

52

53

55

56

57

58

60

61

A[23:0]

Output

Address Signals

1

DMA CONTROLLER (DMAC)

DMA Request

72

73

DREQ

DACK

Input

1

Output

DMA Acknowledge

10

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NOTES

NXP Semiconductors

Table 3. LH75401 Signal Descriptions (Cont’d)

PIN NO. SIGNAL NAME

TYPE

DESCRIPTION

COLOR LCD CONTROLLER (CLCDC)

120

121

122

123

124

125

128

129

130

LCDMOD

LCDVEEEN

LCDVDDEN

LCDDSPLEN

LCDREV

LCDCLS

LCDPS

Output

Signal Used by the Row Driver (AD-TFT, HR-TFT only)

Analog Supply Enable (AC Bias SIgnal)

Digital Supply Enable

1

LCD Panel Power Enable

Reverse Signal (AD-TFT, HR-TFT only)

Clock to the Row Drivers (AD-TFT, HR-TFT only)

Power Save (AD-TFT, HR-TFT only)

LCD Panel Clock

LCDDCLK

LCDLP

Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT)

Latch Pulse (AD-TFT, HR-TFT only)

1

LCDHRLP

LCDFP

Frame Pulse (STN), Vertical Synchronization Pulse (TFT)

Row Driver Counter Reset Signal (AD-TFT, HR-TFT only)

LCD Data Enable

LCDSPS

LCDEN

LCDSPL

Start Pulse Left (AD-TFT, HR-TFT only)

131

132

133

135

136

137

138

139

141

142

143

144

LCDVD[11:0]

Output

LCD Panel Data bus

1

SYNCHRONOUS SERIAL PORT (SSP)

SSP Serial Frame

99

SSPFRM

SSPCLK

SSPRX

SSPTX

Output

Input

1

100

101

102

SSP Clock

SSP RXD

Output

SSP TXD

UART0 (U0)

103

104

UARTTX0

UARTRX0

Output

Input

UART0 Transmitted Serial Data Output

UART0 Received Serial Data Input

UART1 (U1)

1

74

76

UARTRX1

UARTTX1

Input

UART1 Received Serial Data Input

UART1 Transmitted Serial Data Output

UART2 (U2)

1

Output

105

107

UARTTX2

UARTRX2

Output

Input

UART2 Transmitted Serial Data Output

UART2 Received Serial Data Input

CONTROLLER AREA NETWORK (CAN)

CAN Transmitted Serial Data Output

CAN Received Serial Data Input

1

103

104

CANTX

CANRX

Output

Input

1

Product data sheet

Rev. 02 — 19 March 2009

11

LH75401/LH75411

System-on-Chip

NOTES

NXP Semiconductors

Table 3. LH75401 Signal Descriptions (Cont’d)

PIN NO. SIGNAL NAME

TYPE

DESCRIPTION

ANALOG-TO-DIGITAL CONVERTER (ADC)

89

90

91

92

93

94

95

96

AN3 (LR/Y-)

AN4 (Wiper)

AN9

AN2 (LL/Y+)

AN8

AN1 (UR/X-)

AN6

AN0 (UL/X+)

Input

ADC Inputs

1

TIMER 0

117

116

115

114

113

CTCAP0[A:E]

Input

Timer 0 Capture Inputs

1

117

116

CTCMP0[A:B]

CTCLK

Output

Input

Timer 0 Compare Outputs

1

118

Common External Clock

TIMER 1

111

110

CTCAP1[A:B]

Input

Timer 1 Capture Inputs

1

111

110

CTCMP1[A:B]

CTCLK

Output

Input

Timer 1 Compare Outputs

1

118

Common External Clock

TIMER 2

109

108

CTCAP2[A:B]

Input

Timer 2 Capture Inputs

1

109

108

CTCMP2[A:B]

CTCLK

Input

Timer 2 Compare Outputs

1

118

Common External Clock

GENERAL PURPOSE INPUT/OUTPUT (GPIO)

1

2

4

5

6

7

9

10

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Input/Output General Purpose I/O Signals - Port A

Input/Output General Purpose I/O Signals - Port B

Input/Output General Purpose I/O Signals - Port C

1

24

25

27

28

29

30

PB5

PB4

PB3

PB2

PB1

PB0

32

33

35

36

37

38

39

40

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

12

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

Table 3. LH75401 Signal Descriptions (Cont’d)

PIN NO. SIGNAL NAME

TYPE

DESCRIPTION

NOTES

72

73

74

76

77

78

79

PD6

PD5

PD4

PD3

PD2

PD1

PD0

Input/Output General Purpose I/O Signals - Port D

1

89

90

91

92

93

94

95

96

PJ7

PJ6

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

Input

General Purpose I/O Signals - Port J

1

99

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

100

101

102

103

104

105

107

Input/Output General Purpose I/O Signals - Port E

Input/Output General Purpose I/O Signals - Port F

Input/Output General Purpose I/O Signals - Port G

1

108

109

110

111

113

114

115

PF6

PF5

PF4

PF3

PF2

PF1

PF0

116

117

118

120

121

122

123

124

PG7

PG6

PG5

PG4

PG3

PG2

PG1

PG0

125

128

129

130

131

132

133

135

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

Input/Output General Purpose I/O Signals - Port H

1

136

137

138

139

141

142

143

144

PI7

PI6

PI5

PI4

PI3

PI2

PI1

PI0

Input/Output General Purpose I/O Signals - Port I

RESET, CLOCK, AND POWER CONTROLLER (RCPC)

62

71

72

nRESETIN

nRESETOUT

INT6

Input

Output

Input

User Reset Input

2

1

System Reset Output

External Interrupt Input 6

Product data sheet

Rev. 02 — 19 March 2009

13

LH75401/LH75411

System-on-Chip

NOTES

NXP Semiconductors

Table 3. LH75401 Signal Descriptions (Cont’d)

PIN NO. SIGNAL NAME

TYPE

DESCRIPTION

73

74

76

77

78

79

81

82

83

86

87

INT5

Input

Output

Input

Output

External Interrupt Input 5

External Interrupt Input 4

External Interrupt Input 3

External Interrupt Input 2

External Interrupt Input 1

External Interrupt Input 0

Power-on Reset Input

1

2

INT4

INT3

INT2

INT1

INT0

nPOR

XTAL32IN

XTAL32OUT

XTALIN

XTALOUT

32.768 kHz Crystal Clock Input

32.768 kHz Crystal Clock Output

Crystal Clock Input

Crystal Clock Output

TEST INTERFACE

63

64

65

66

67

68

69

TEST2

TEST1

TMS

Input

Test Mode Pin 2

Test Mode Pin 1

Input

JTAG Test Mode Select Input

Returned JTAG Test Clock Output

JTAG Test Clock Input

RTCK

TCK

Output

Input

TDI

Input

JTAG Test Serial Data Input

JTAG Test Data Serial Output

POWER AND GROUND (GND)

TDO

Output

3

17

34

42

54

VDD

Power

I/O Ring VDD

98

112

126

134

8

26

41

48

59

VSS

Power

I/O Ring VSS

106

119

127

140

11

75

VDDC

VSSC

Power

Core VDD supply (Output if Linear Regulator Enabled, Otherwise Input)

Core VSS

14

80

70

84

85

88

97

LINREGEN

VSSA_PLL

VDDA_PLL

VSSA_ADC

VDDA_ADC

Input

Power

Linear Regulator Enable

PLL Analog VSS

PLL Analog VDD Supply

A-to-D converter Analog VSS

A-to-D converter Analog VDD Supply

NOTES:

1. These pin numbers have multiplexed functions.

2. Signals preceded with ‘n’ are active LOW.

14

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

LH75411 Numerical Pin Listing

Table 4. LH75411 Numerical Pin List

PIN FUNCTION

NO. AT RESET

FUNCTION FUNCTION FUNCTION OUTPUT

BUFFER

TYPE

BEHAVIOR DURING

NOTES

2

3

TYPE

DRIVE

RESET

1

PA7

PA6

VDD

PA5

PA4

PA3

PA2

VSS

PA1

PA0

VDDC

D7

D15

D14

I/O

8 mA

None

8 mA

None

8 mA

None

8 mA

None

8 mA

None

8 mA

None

8 mA

None

8 mA

None

Bidirectional

Pull-up

1

2

3

Power

I/O

4

D13

D12

D11

D10

Bidirectional

Pull-up

1

5

I/O

6

I/O

7

I/O

8

Ground

I/O

9

D9

D8

Bidirectional

Pull-up

1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

I/O

Power

I/O

Bidirectional

Pull-up

D6

I/O

VSSC

D5

Ground

I/O

Bidirectional

Pull-up

D4

I/O

VDD

D3

Power

I/O

Bidirectional

Output

Pull-up

HIGH

D2

I/O

D1

I/O

D0

I/O

nWE

nOE

PB5

PB4

VSS

PB3

PB2

PB1

PB0

nCS0

PC7

PC6

VDD

PC5

PC4

PC3

PC2

PC1

PC0

VSS

3

Output

HIGH

3

nWAIT

nBLE1

Bidirectional

Pull-up

1, 3

Ground

nBLE0

nCS3

nCS2

nCS1

Bidirectional

Output

Pull-up

1, 3

3

Pull-up

A23

A22

Bidirectional

Pull-down

1

Power

A21

A20

A19

A18

A17

A16

Bidirectional

Pull-down

1

Ground

Product data sheet

Rev. 02 — 19 March 2009

15

LH75401/LH75411

System-on-Chip

NXP Semiconductors

Table 4. LH75411 Numerical Pin List (Cont’d)

PIN FUNCTION

NO. AT RESET

FUNCTION FUNCTION FUNCTION OUTPUT

BUFFER

TYPE

BEHAVIOR DURING

NOTES

2

3

TYPE

DRIVE

None

8 mA

None

8 mA

None

8 mA

None

8 mA

None

8 mA

None

4 mA

None

8 mA

6 mA

8 mA

None

8 mA

2 mA

6 mA

2 mA

None

RESET

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

VDD

A15

Power

Output

LOW

A14

A13

A12

A11

VSS

A10

Ground

Output

LOW

A9

A8

A7

A6

VDD

A5

Power

Output

LOW

A4

A3

A2

VSS

A1

Ground

Output

Input

LOW

A0

nRESETIN

TEST2

TEST1

TMS

RTCK

TCK

TDI

Pull-up

2, 3

2

Input

2

Input

2

Output

Input

Pull-up

2

TDO

LINREGEN

Output

Input

5

3

71 nRESETOUT

Output

Bidirectional

72

73

74

75

76

77

78

79

80

81

82

PD6

PD5

INT6

INT5

INT4

DREQ

DACK

Pull-down

Pull-up

1

1, 2

1

PD4

UARTRX1

VDDC

PD3

Power

INT3

INT2

INT1

INT0

UARTTX1

Bidirectional

Pull-up

1

PD2

PD1

1, 2

1

PD0

VSSC

nPOR

XTAL32IN

Ground

Input

Pull-up

2, 3

4

Input

83 XTAL32OUT

Output

16

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

Table 4. LH75411 Numerical Pin List (Cont’d)

PIN FUNCTION

NO. AT RESET

FUNCTION FUNCTION FUNCTION OUTPUT

BUFFER

TYPE

BEHAVIOR DURING

NOTES

2

3

TYPE

DRIVE

RESET

84

85

86

87

88

89

VSSA_PLL

VDDA_PLL

XTALIN

Ground

Power

None

4 mA

8 mA

2 mA

4 mA

None

4 mA

None

4 mA

None

8 mA

Input

4

XTALOUT

VSSA_ADC

AN3 (LR/Y-)

Output

Ground

PJ7

PJ6

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

Input

90 AN4 (Wiper)

91 AN9

92 AN2 (LL/Y+)

93 AN8

94 AN1 (UR/X-)

95 AN6

96 AN0 (UL/X+)

97

VDDA_ADC

VDD

PE7

PE6

PE5

PE4

PE3

PE2

PE1

VSS

PE0

PF6

Power

98

99

SSPFRM

SSPCLK

SSPRX

Bidirectional

Pull-up

Pull-down

Pull-up

1

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

SSPTX

Pull-down

Pull-up

UARTTX0

UARTRX0

UARTTX2

Pull-up

Ground

UARTRX2

CTCAP2B

CTCAP2A

CTCAP1B

CTCAP1A

Bidirectional

Pull-up

1

2

CTCMP2B

CTCMP2A

CACMP1B

CTCMP1A

PF5

PF4

2

PF3

VDD

PF2

Power

CTCAP0E

CTCAP0D

CTCAP0C

CTCAP0B

CTCAP0A

CTCLK

Bidirectional

2

PF1

PF0

PG7

PG6

PG5

VSS

PG4

PG3

PG2

PG1

PG0

PH7

CTCMP0B

CTCMP0A

Ground

LCDVEEEN

LCDVDDEN

LCDMOD

Bidirectional

LCDDSPLEN LCDREV

LCDCLS

LCDPS

LCDDCLK

Product data sheet

Rev. 02 — 19 March 2009

17

LH75401/LH75411

System-on-Chip

NXP Semiconductors

Table 4. LH75411 Numerical Pin List (Cont’d)

PIN FUNCTION

NO. AT RESET

FUNCTION FUNCTION FUNCTION OUTPUT

BUFFER

TYPE

BEHAVIOR DURING

RESET

NOTES

2

3

TYPE

DRIVE

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

VDD

VSS

PH6

PH5

PH4

PH3

PH2

PH1

VDD

PH0

PI7

Power

None

8 mA

None

8 mA

None

8 mA

Ground

LCDLP

LCDFP

LCDHRLP

LCDSPS

LCDSPL

Bidirectional

LCDEN

LCDVD11

LCDVD10

LCDVD9

Power

LCDVD8

LCDVD7

LCDVD6

LCDVD5

LCDVD4

Bidirectional

PI6

PI5

PI4

VSS

PI3

Ground

LCDVD3

LCDVD2

LCDVD1

LCDVD0

Bidirectional

PI2

PI1

PI0

NOTES:

1. Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral.

2. CMOS Schmitt trigger input.

3. Signals preceded with ‘n’ are active LOW.

4. Crystal Oscillator Inputs should be driven to 1.8 V ±10 % (MAX.)

5. LINREGEN activation requires a 0  pull-up to VDD.

18

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

LH75411 Signal Descriptions

Table 5. LH75411 Signal Descriptions

PIN NO. SIGNAL NAME

TYPE

DESCRIPTION

NOTES

MEMORY INTERFACE (MI)

1

2

4

5

6

7

9

10

12

D[15:0]

Input/Output Data Input/Output Signals

1

13

15

16

18

19

20

21

22

23

24

25

27

28

29

30

31

nWE

Output

Input

Static Memory Controller Write Enable

2

nOE

Static Memory Controller Output Enable

Static Memory Controller External Wait Control

Static Memory Controller Byte Lane Strobe

Static Memory Controller Chip Select

2

nWAIT

nBLE1

nBLE0

nCS3

nCS2

nCS1

nCS0

1, 2

2

Output

32

33

35

36

37

38

39

40

43

44

45

46

47

49

50

51

52

53

55

56

57

58

60

61

A[23:0]

Output

Address Signals

1

DMA CONTROLLER (DMAC)

DMA Request

72

73

DREQ

DACK

Input

1

Output

DMA Acknowledge

Product data sheet

Rev. 02 — 19 March 2009

19

LH75401/LH75411

System-on-Chip

NOTES

NXP Semiconductors

Table 5. LH75411 Signal Descriptions (Cont’d)

PIN NO. SIGNAL NAME

TYPE

DESCRIPTION

COLOR LCD CONTROLLER (CLCDC)

120

121

122

123

124

125

128

129

130

LCDMOD

LCDVEEEN

LCDVDDEN

LCDDSPLEN

LCDREV

LCDCLS

LCDPS

Output

Signal Used by the Row Driver (AD-TFT, HR-TFT only)

Analog Supply Enable (AC Bias SIgnal)

Digital Supply Enable

1

LCD Panel Power Enable

Reverse Signal (AD-TFT, HR-TFT only)

Clock to the Row Drivers (AD-TFT, HR-TFT only)

Power Save (AD-TFT, HR-TFT only)

LCD Panel Clock

LCDDCLK

LCDLP

Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT)

Latch Pulse (AD-TFT, HR-TFT only)

1

LCDHRLP

LCDFP

Frame Pulse (STN), Vertical Synchronization Pulse (TFT)

Row Driver Counter Reset Signal (AD-TFT, HR-TFT only)

LCD Data Enable

LCDSPS

LCDEN

LCDSPL

Start Pulse Left (AD-TFT, HR-TFT only)

131

132

133

135

136

137

138

139

141

142

143

144

LCDVD[11:0]

Output

LCD Panel Data bus

1

SYNCHRONOUS SERIAL PORT (SSP)

SSP Serial Frame

99

SSPFRM

SSPCLK

SSPRX

SSPTX

Output

Input

1

100

101

102

SSP Clock

SSP RXD

Output

SSP TXD

UART0 (U0)

104

103

UARTRX0

UARTTX0

Input

UART0 Received Serial Data Input

UART0 Transmitted Serial Data Output

UART1 (U1)

1

Output

74

76

UARTRX1

UARTTX1

Input

UART1 Received Serial Data Input

UART1 Transmitted Serial Data Output

UART2 (U2)

1

Output

105

107

UARTTX2

UARTRX2

Output

Input

UART2 Transmitted Serial Data Output

UART2 Received Serial Data Input

ANALOG-TO-DIGITAL CONVERTER (ADC)

1

89

90

91

92

93

94

95

96

AN3 (LR/Y-)

AN4 (Wiper)

AN9

AN2 (LL/Y+)

AN8

AN1 (UR/X-)

AN6

AN0 (UL/X+)

Input

ADC Inputs

1

20

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

Table 5. LH75411 Signal Descriptions (Cont’d)

PIN NO. SIGNAL NAME

TYPE

DESCRIPTION

NOTES

TIMER 0

117

116

115

114

113

CTCAP0[A:E]

Input

Timer 0 Capture Inputs

1

117

116

CTCMP0[A:B]

CTCLK

Output

Input

Timer 0 Compare Outputs

1

118

Common External Clock

TIMER 1

111

110

CTCAP1[A:B]

Input

Timer 1 Capture Inputs

1

111

110

CTCMP1[A:B]

CTCLK

Output

Input

Timer 1 Compare Outputs

1

118

Common External Clock

TIMER 2

109

108

CTCAP2[A:B]

Input

Timer 2 Capture Inputs

1

109

108

CTCMP2[A:B]

CTCLK

Input

Timer 2 Compare Outputs

Common External Clock

1

118

GENERAL PURPOSE INPUT/OUTPUT (GPIO)

1

2

4

5

6

7

9

10

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Input/Output General Purpose I/O Signals - Port A

Input/Output General Purpose I/O Signals - Port B

Input/Output General Purpose I/O Signals - Port C

1

24

25

27

28

29

30

PB5

PB4

PB3

PB2

PB1

PB0

32

33

35

36

37

38

39

40

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

72

73

74

76

77

78

79

PD6

PD5

PD4

PD3

PD2

PD1

PD0

Input/Output General Purpose I/O Signals - Port D

1

Product data sheet

Rev. 02 — 19 March 2009

21

LH75401/LH75411

System-on-Chip

NXP Semiconductors

Table 5. LH75411 Signal Descriptions (Cont’d)

PIN NO. SIGNAL NAME

TYPE

DESCRIPTION

NOTES

89

90

91

92

93

94

95

96

PJ7

PJ6

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

Input

General Purpose I/O Signals - Port J

1

99

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

100

101

102

103

104

105

107

Input/Output General Purpose I/O Signals - Port E

Input/Output General Purpose I/O Signals - Port F

Input/Output General Purpose I/O Signals - Port G

1

108

109

110

111

113

114

115

PF6

PF5

PF4

PF3

PF2

PF1

PF0

116

117

118

120

121

122

123

124

PG7

PG6

PG5

PG4

PG3

PG2

PG1

PG0

125

128

129

130

131

132

133

135

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

Input/Output General Purpose I/O Signals - Port H

1

136

137

138

139

141

142

143

144

PI7

PI6

PI5

PI4

PI3

PI2

PI1

PI0

Input/Output General Purpose I/O Signals - Port I

RESET, CLOCK, AND POWER CONTROLLER (RCPC)

62

71

72

73

74

76

77

78

79

nRESETIN

nRESETOUT

INT6

Input

Output

Input

User Reset Input

2

1

System Reset Output

External Interrupt Input 6

External Interrupt Input 5

External Interrupt Input 4

External Interrupt Input 3

External Interrupt Input 2

External Interrupt Input 1

External Interrupt Input 0

INT5

INT4

INT3

INT2

INT1

INT0

22

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

Table 5. LH75411 Signal Descriptions (Cont’d)

PIN NO. SIGNAL NAME

TYPE

DESCRIPTION

NOTES

81

82

83

86

87

nPOR

Input

Power-on Reset Input

2

XTAL32IN

XTAL32OUT

XTALIN

32.768 kHz Crystal Clock Input

32.768 kHz Crystal Clock Output

Crystal Clock Input

Output

Input

XTALOUT

Output

Crystal Clock Output

TEST INTERFACE

63

64

65

66

67

68

69

TEST2

TEST1

TMS

Input

Test Mode Pin 2

Test Mode Pin 1

Input

JTAG Test Mode Select Input

Returned JTAG Test Clock Output

JTAG Test Clock Input

RTCK

TCK

Output

Input

TDI

Input

JTAG Test Serial Data Input

JTAG Test Data Serial Output

POWER AND GROUND (GND)

TDO

Output

3

17

34

42

54

VDD

Power

I/O Ring VDD

98

112

126

134

8

26

41

48

59

VSS

Power

I/O Ring VSS

106

119

127

140

11

75

VDDC

VSSC

Power

Core VDD supply (Output if Linear Regulator Enabled, Otherwise Input)

Core VSS

14

80

70

84

85

88

97

LINREGEN

VSSA_PLL

VDDA_PLL

VSSA_ADC

VDDA_ADC

Input

Power

Linear Regulator Enable

PLL Analog VSS

PLL Analog VDD Supply

A-to-D converter Analog VSS

A-to-D converter Analog VDD Supply

NOTES:

1. These pin numbers have multiplexed functions.

2. Signals preceded with ‘n’ are active LOW.

Product data sheet

Rev. 02 — 19 March 2009

23

LH75401/LH75411

System-on-Chip

NXP Semiconductors

LCD

TOUCH SCREEN

CAN

TRANSCEIVER

CAN

NETWORK

CAN

2.0B

STN/TFT,

AD-TFT/HR-TFT

A/D

FLASH

SRAM

LH75401

A/D

BOOT

ROM

UART

GPIO

SSP

SENSOR

ARRAY

1

4

7

2

5

8

0

3

6

9

#

SERIAL

EEPROM

*

KEY

MATRIX

LH754xx-2A

Figure 4. LH75401 System Application Example

FUNCTIONAL OVERVIEW

ARM7TDMI-S Processor

The LH75401/LH75411 microcontrollers feature the

ARM7TDMI-S core with an Advanced High-Performance

Bus (AHB) 2.0 interface. The ARM7TDMI-S is a 16/32-bit

embedded RISC processor and a member of the ARM7

Thumb family of processors. For more information, visit

the ARM Web site at www.arm.com.

Power Supplies

Five-Volt-tolerant 3.3 V I/Os are employed. The

LH75401/LH75411 microcontrollers require a single

3.3 V supply. The core logic requires 1.8 V, supplied by

an on-chip linear regulator. Core logic power may also

be supplied externally to achieve higher system

speeds. See the Electrical Specifications.

Clock Sources

The LH75401/LH75411 microcontrollers may use

two crystal oscillators, or an externally supplied clock.

There are two clock trees:

Bus Architecture

The LH75401/LH75411 microcontrollers use the

ARM Advanced Microcontroller Bus Architecture (AMBA)

2.0 internal bus protocol. Three AHB masters control

access to external memory and on-chip peripherals:

• One clock tree drives an internal Phase Lock Loop

(PLL) and the three UARTs. It supports a crystal

oscillator frequency range from 14 MHz to 20 MHz.

• The ARM processor fetches instructions and trans-

fers data

• The other is a 32.768 kHz oscillator that generates a

1 Hz clock for the RTC. (Use of the 32.768 kHz crys-

tal for the Real Time Clock is optional. If not using the

crystal, tie XTAL32IN to VSS and allow XTAL32OUT

to float.)

• The Direct Memory Access Controller (DMAC) trans-

fers from memory to memory, from peripheral to

memory, and from memory to peripheral

The 14-to-20 MHz crystal oscillator drives the UART

clocks, so an oscillator frequency of 14.7456 MHz is rec-

ommended to achieve modem baud rates.

• The LCDC refreshes an LCD panel with data from

the external memory or from internal memory if the

frame buffer is 16 kB or less.

The PLL may be bypassed and an external clock

supplied at XTALIN; the SoC will operate to DC with the

PLL disabled. When doing so, allow XTALOUT to float.

The input clock with the PLL bypassed will be twice the

desired system operating frequency, and care must be

taken not to exceed the maximum input clock voltage.

Maximum values for system speeds and input voltages

are given in the Electrical Specifications.

The ARM7TDMI-S processor is the default bus mas-

ter. An Advanced Peripheral Bus (APB) bridge is pro-

vided to access to the various APB peripherals.

Generally, APB peripherals are serviced by the ARM

core. However, if they are DMA-enabled, they are also

serviced by the DMAC to increase system performance

while the ARM core runs from local internal memory.

24

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

Reset Generation

Memory Interface Architecture

The LH75401/LH75411 microcontrollers provide the

following data-path management resources on chip:

EXTERNAL RESETS

Two external signals generate resets to the

ARM7TDMI-S core:

• AHB and APB data buses

• nPOR sets all internal registers to their default state

when asserted. It is used as a Power-On Reset.

• 16 kB of zero-wait-state TCM SRAM accessible via

processor

• nRESETIN sets all internal registers, except the

JTAG circuitry, to their default state when asserted.

• 16 kB of internal SRAM accessible via processor,

DMAC, and LCDC

When nPOR is asserted, nRESETIN defines the

microcontroller Test Mode. When nPOR is released,

nRESETIN behaves during Reset as described

previously.

• A Static Memory Controller (SMC) that controls

access to external memory

• A 4-stream general-purpose DMAC.

All external and internal system resources are

memory-mapped. This memory map partition has three

views, based on the setting of the REMAP bits in the

Reset, Clock, and Power Controller (RCPC).

INTERNAL RESETS

There are two types of Internal Resets generated:

• System Reset

The second partitioning of memory space is the

dividing of the segments into sections. The external

memory segment is divided into eight 64 MB sections,

of which the first four are used, each having a chip

select associated with it. Access to any of the last four

sections does not result in an external bus access and

does not cause a memory abort. The peripheral regis-

ter segment is divided into 4 kB peripheral sections, 21

of which are assigned to peripherals.

• RTC Reset.

System and RTC Resets are asserted by:

• An External Reset (a logic LOW signal on the exter-

nal nRESETIN or nPOR input pin)

• A signal from the internal Watchdog Timer

• A Soft Reset.

The reset latency depends on the PLL lock state.

Table 7. Memory Mapping

REMAP = 00

AHB Master Priority and Arbitration

The LH75401/LH75411 microcontrollers have three

AHB masters:

ADDRESS

REMAP = 01 REMAP = 10

(DEFAULT)

• ARM processor

• DMAC

External

Memory

Internal

0x00000000

0x20000000

0x40000000

TCM SRAM

SRAM

Reserved

• LCD Controller.

External

Memory

External

Memory

External

Memory

Each AHB master has a priority level that is perma-

nent and cannot change.

Internal

SRAM

Internal

SRAM

Internal

SRAM

0x60000000

Table 6. Bus Master Priority

0x80000000 TCM SRAM TCM SRAM TCM SRAM

0xA0000000

0xC0000000

Reserved

PRIORITY

BUS MASTER PRIORITY

1 (Highest) Color LCDC (LH75401 and LH75411)

0xE0000000 -

0xFFFBFFFF

2

DMAC

Reserved

3 (Lowest)

ARM7TDMI-S Core (Default)

Product data sheet

Rev. 02 — 19 March 2009

25

LH75401/LH75411

System-on-Chip

NXP Semiconductors

Table 8. APB Peripheral Register Mapping

ADDRESS RANGE DEVICE

• Supports memory-mapped devices, including

Random Access Memory (RAM), Read Only

Memory (ROM), Flash, and burst ROM

0xFFFC0000 - 0xFFFC0FFF UART0 (16550)

0xFFFC1000 - 0xFFFC1FFF UART1 (16550)

0xFFFC2000 - 0xFFFC2FFF UART2 (82510)

0xFFFC3000 - 0xFFFC3FFF Analog-to-Digital Converter

0xFFFC4000 - 0xFFFC4FFF Timer Module

• Supports external bus and external device widths of

8 and 16 bits

• Supports Asynchronous Burst Mode read access for

Burst Mode ROM devices, with up to 32 independent

wait states for read and write accesses

• Supports indefinite extended wait states via an

external hardware pin (nWAIT)

CAN (LH75401)

0xFFFC5000 - 0xFFFC5FFF

Reserved (LH75411)

0xFFFC6000 - 0xFFFC6FFF Synchronous Serial Port

0xFFFC7000 - 0xFFFDAFFF Reserved

0xFFFDB000 - 0xFFFDBFFF GPIO4

0xFFFDC000 - 0xFFFDCFFF GPIO3

0xFFFDD000 - 0xFFFDDFFF GPIO2

0xFFFDE000 - 0xFFFDEFFF GPIO1

0xFFFDF000 - 0xFFFDFFFF GPIO0

0xFFFE0000 - 0xFFFE0FFF Real Time Clock

0xFFFE1000 - 0xFFFE1FFF DMAC

• Supports varied bus turnaround cycles (1 to 16)

between a read and write operation

Direct Memory Access Controller (DMAC)

One central DMAC services all peripheral DMA

requirements for the DMA-capable peripherals listed in

Table 9.

The DMA is controlled by the system clock. It has an

APB slave port for programming of its registers and an

AHB port for data transfers.

Reset Clock and Power

0xFFFE2000 - 0xFFFE2FFF

Controller

Table 9. DMAC Stream Assignments

0xFFFE3000 - 0xFFFE3FFF Watchdog Timer

0xFFFE4000 - 0xFFFE4FFF Advanced LCD Interface

0xFFFE5000 - 0xFFFE5FFF I/O Configuration Peripheral

0xFFFE6000 - 0xFFFEFFFF Reserved

DMA REQUEST SOURCE

DMA STREAM

UART1RX (highest priority)

UART1TX

Stream0

Stream1

Stream2

Stream3

UART0RX/External Request (DREQ)

UART0TX (lowest priority)

Static Random Access Memory Controller

The LH75401/LH75411 microcontrollers have 32 kB

of Static Random Access Memory (SRAM) organized

into two 16 kB blocks:

DMAC FEATURES

• Four data streams that can be used to service:

– Four peripheral data streams (peripheral-to-

memory or memory-to-peripheral)

• 16 kB of TCM 0 Wait State SRAM is available to the

processor as an ARM7TDMI-S bus slave.

– Three peripheral data streams and one memory-

to-memory data stream.

• 16 kB of internal SRAM is available as an AHB slave

and accessible via processor, DMAC, and LCDC.

• Three transfer modes:

Each memory segment is 512 MB, though the TCM

and internal SRAMs are 16 kB each in size. Any

access beyond the first 16 kB is mapped to the lower

16 kB, but does not cause a data or prefetch abort.

– Memory to Memory (selectable on Stream3)

– Peripheral to Memory (all streams)

– Memory to Peripheral (all streams).

• Built-in data stream arbiter

Static Memory Controller (SMC)

• Seven programmable registers for each stream

The Static Memory Controller (SMC) is an AMBA

AHB slave peripheral that provides the interface

between the LH75401/LH75411 microcontrollers and

external memory devices.

• Ability for each stream to indicate a transfer error via

an interrupt

• 16-word First-In, First Out (FIFO) array, with pack

and unpack logic to handle all input/output combina-

tions of byte, half-word, and word transfers

SMC FEATURES

• Provides four banks of external memory, each with a

maximum size of 16 MB.

• APB slave port allows the ARM core to program

DMAC registers

• AHB port for data transfers.

26

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

ADVANCED LCD INTERFACE

Color LCD Controller (CLCDC)

The Advanced LCD Interface (ALI) allows for direct

connection to ultra-thin panels that do not include a tim-

ing ASIC. It converts TFT signals from the Color LCD

controller to provide the proper signals, timing and levels

for direct connection to a panel’s Row and Column driv-

ers for AD-TFT, HR-TFT, or any technology of panel that

allows for a connection of this type. The ALI also pro-

vides a bypass mode that allows interfacing to the built-

in timing ASIC in standard TFT and STN panels.

The CLCDC is an AMBA master-slave module that

connects to the AHB. It translates pixel-coded data into

the required formats and timings to drive single/dual

monochrome and color LCD panels. Packets of pixel-

coded data are fed, via the AHB interface, to two inde-

pendently programmable, 32-bit-wide DMA FIFOs.

Each FIFO is 16 words deep by 32 bits wide.

The CLCDC generates a single combined interrupt

to the Vectored Interrupt Controller (VIC) when an

interrupt condition becomes true for upper/lower panel

DMA FIFO underflow, base address update significa-

tion, vertical compare, or bus error.

NOTES:

1. The Advanced LCD Interface pertains to the LH75401 and

LH75411 microcontrollers.

2. VGA and XGA modes require 66 MHz core speed.

NOTE: LH75401 and LH75411 microcontrollers support full-color

operation.

Universal Asynchronous

Receiver Transmitters (UARTs)

The LH75401/LH75411 microcontrollers incorporate

three UARTs, designated UART0, UART1, and UART2.

CLCDC FEATURES

• STN, Color STN, TFT, HR-TFT, and AD-TFT

– Fully Programmable Timing Controls

– Advanced LCD Interface for displays with a low

level of integration, such as HR-TFT and AD-TFT

UART 0 AND 1 FEATURES

• Similar functionality to the industry-standard 16C550

• Programmable Resolution

– Up to VGA (640 × 480 DPI), 12-bit Direct Mode

Color

• Supported baud rates up to 921,600 baud (given an

external crystal frequency of 14.756 MHz)

• Supported character formats:

– Data bits per character: 5, 6, 7, or 8

– Parity generation and detection: Even, odd, stick,

or none

– Up to SVGA (800 × 600 DPI), 8-bit Direct/Pal-

ettized Color

– Up to XGA (1,024 × 768 DPI), 4-bit Direct Color/

Grayscale

– Stop bit generation: 1 or 2

– Direct or Palettized Colors

• Full-duplex operation

• Single and Dual Panels

• Separate transmit and receive FIFOs, with:

– Programmable depth (1 to 16)

– Programmable-service ‘trigger levels’ (1/8, 1/4,

1/2, 3/4, and 7/8)

• Supports Sharp and non-Sharp Panels

• CLCDC Outputs Available as General Purpose

Inputs/Outputs (GPIOs) if LCDC is Not Needed

• Additional Features

– Overrun protection.

– Fully programmable horizontal and vertical timing

for different display panels

– 256-entry, 16-bit palette RAM physically arranged

as a 128 × 32-bit RAM

– AC bias signal for STN panels and a data-enable

signal for TFT panels.

• Programmable baud-rate generator that:

– Enables the UART input clock to be divided by 16

to 65,535 × 16

– Generates an internal clock common to both

transmit and receive portions of the UART.

• DMA support

• Programmable Panel-related Parameters

– STN mono/color or TFT display

– Bits-per-pixel

• Support for generating and detecting breaks during

UART transactions

– STN 4- or 8-bit Interface Mode

– STN Dual or Single Panel Mode

– AC panel bias

• Loopback testing.

– Panel clock frequency

– Number of panel clocks per line

– Signal polarity, active HIGH or LOW

– Little Endian data format

– Interrupt-generation event.

Product data sheet

Rev. 02 — 19 March 2009

27

LH75401/LH75411

System-on-Chip

NXP Semiconductors

UART 2 FEATURES

The timers support a PWM Mode that uses the two

Timer Compare Registers associated with a timer to

create a PWM. Each timer can generate a separate

interrupt. The interrupt becomes active if any enabled

compare, capture, or overflow interrupt condition

occurs. The interrupt remains active until all compare,

capture, and overflow interrupts are cleared.

• Similar functionality to the industry-standard 82510

• Supported baud rates up to 3,225,600 baud (given a

system clock of 51.6096 MHz)

• 5, 6, 7, 8, or 9 data bits per character

• Even, odd, HIGH, LOW, software, or no parity-bit

generation and detection

Real Time Clock (RTC)

• 3/4, 1, 1-1/4, 1-1/2, 1-3/4, or 2 stop-bit generation

• LAN address flag

The RTC is an AMBA slave module that connects to

the APB. The RTC provides basic alarm functions or

acts as a long-time base counter by generating an inter-

rupt signal after counting for a programmed number of

cycles of an RTC input. Counting in 1-second intervals

is achieved using a 1 Hz clock input to the RTC.

• Full-duplex operation

• Separate transmit and receive FIFOs, with program-

mable depth (1 or 4). Each FIFO has overrun protec-

tion and:

– Programmable receive trigger levels: 1/4, 1/2,

3/4, or full

– Programmable transmit trigger levels: empty, 1/4,

1/2, 3/4.

RTC FEATURES

• 32-bit up-counter with programmable load

• Programmable 32-bit match Compare Register

• Two 16-bit baud-rate generators.

• Software-maskable interrupt that is set when the Coun-

ter and Compare Registers have identical values.

• One interrupt that can be triggered by transmit and

receive FIFO thresholds, receive errors, control

character or address marker reception, or timer

timeout

Controller Area Network (CAN)

The CAN 2.0B Controller is an AMBA-compliant

peripheral that connects as a slave to the APB. The

CAN Controller is located between the processor core

and a CAN Transceiver, and is accessed through the

AMBA port.

• Generation and detection of breaks during UART

transactions

• Support for local loopback, remote loopback, and

auto-echo modes

CAN communications are performed serially, at a

maximum frequency of 1 MB/s, using the TX (transmit)

and RX (receive) lines. The TX and RX signals for data

transmission and reception provide the communications

interface between the CAN Controller and the CAN bus.

All peripherals share the TX and RX lines, and always

see the common incoming and outgoing data.

• LAN Address Mode.

Timers

The LH75401/LH75411 microcontrollers have three

16-bit timers. The timers are clocked by the system

clock, but have an internal scaled-down system clock

that is used for the Pulse Width Modulator (PWM) and

compare functions.

Bus arbitration follows the CAN 2.0A and CAN 2.0B

specifications. The bus is always controlled by the

node with the highest priority (lowest ID). Only after the

bus has been released can the next highest priority

node control it. Transmit and receive errors are han-

dled according to the CAN protocol.

All counters are incremented by an internal pre-

scaled counter clock or external clock and can gener-

ate an overflow interrupt. All three timers have separate

internal prescaled counter clocks, with either a com-

mon external clock or a prescaled version of the sys-

tem clock.

Bus timing is critical to the CAN protocol. Therefore,

the CAN Controller has two programmable Bus Timing

Registers that define timing parameters.

• Timer 0 has five Capture Registers and two Com-

pare Registers.

NOTE: The CAN Controller pertains to the LH75401 microcon-

• Timer 1 and Timer 2 have two Capture and two Com-

pare Registers each.

trollers.

The Capture Registers have edge-selectable inputs

and can generate an interrupt. The Compare Registers

can force the compare output pin either HIGH or LOW

upon a match.

28

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

CAN 2.0B FEATURES

• Touch-pressure sensing circuits

• Full compliance with 2.0A and 2.0B Bosch

specifications

• Pen-down sensing circuit and interrupt generator

• Voltage-reference generator that is independently

controlled

• Supports 11-bit and 29-bit identifiers

• Supports bit rates up to 1Mbit/s

• 64-byte receive FIFO

• Conversion automation function to minimize control-

ler interrupt overhead

• Software-driven bit-rate detection for hot plug-in

support

• Brownout Detector.

• Single-shot transmission option

• Acceptance filtering

Synchronous Serial Port (SSP)

The SSP is a master-only interface for synchronous

serial communication with slave peripheral devices that

have a Motorola SPI, National Semiconductor

Microwire, or Texas Instruments DSP-compatible

Synchronous Serial Interface (SSI).

• Listen Only Mode

• Reception of ‘own’ messages

• Error interrupt generated for each CAN bus error

• Arbitration-lost interrupt with record of bit position

• Read/write error counters

The SSP performs serial-to-parallel conversion on

data received from a peripheral device. The transmit and

receive paths are buffered with internal FIFO memories.

These memories store eight 16-bit values independently

in both transmit and receive modes. During transmission:

• Last error register

• Programmable error-limit warning.

• Data writes to the transmit FIFO via the APB

interface.

Analog-to-Digital Converter (ADC)/

Brownout Detector

The ADC is an AMBA-compliant peripheral that con-

nects as a slave to the APB. The ADC block consists of

an 8-channel, 10-bit Analog-to-Digital Converter with

integrated Touch Screen Controller. The complete

Touch Screen interface is achieved by combining the

front-end biasing, control circuitry with analog-to-digital

conversion, reference generation, and digital control.

• The transmit data is queued for parallel-to-serial

conversion onto the transmit interface.

• The transmit logic formats the data into the appropri-

ate frame type:

– Motorola SPI

– National Semiconductor Microwire

– Texas Instruments DSP-compatible SSI.

The ADC also has a programmable measurement

clock derived from the system clock. The clock drives

the measurement sequencer and the successive-

approximation circuitry.

SSP FEATURES

• SSI in Master Only Mode. The SSP performs serial

communications as a master device in one of three

modes:

The ADC includes a Brownout Detector. The Brown-

out Detector is an asynchronous comparator that com-

pares a divided version of the 3.3 V supply and a

bandgap-derived reference voltage. If the supply dips

below a Trip point, the Brownout Detector sets a status

register bit. The status bit is wired to the VIC and can

interrupt the processor core. This allows the Host Con-

troller to warn users of an impending shutdown and may

provide the ADC with sufficient time to save its state.

– Motorola SPI

– Texas Instruments DSP-compatible synchronous

serial interface

– National Semiconductor Microwire.

• Two 16-bit-wide, 8-entry-deep FIFOs, one for data

transmission and one for data reception.

• Supports interrupt-driven data transfers that are

greater than the FIFO watermark.

ADC/BROWNOUT DETECTOR FEATURES

• Programmable clock bit rate.

• 10-bit fully differential Successive Approximation

Register (SAR) with integrated sample/hold

• Programmable data frame size, from 4 to 16 bits long,

depending on the size of data programmed. Each

frame transmits starting with the most-significant bit.

• 8-channel multiplexer for routing user-selected inputs

to the ADC in Single Ended and Differential Modes

• Four interrupts, each of which can be individually

enabled or disabled using the SSP Control Register

bits. A combined interrupt is also generated as an

OR function of the individual interrupt requests.

• 16-entry × 16-bit-wide FIFO that holds the 10-bit

ADC output and a 4-bit tag number

• Front bias-and-control network for Touch Screen

interface and support functions compatible with indus-

try-standard 4- and 5-wire touch-sensitive panels

• Loopback Test Mode.

Product data sheet

Rev. 02 — 19 March 2009

29

LH75401/LH75411

System-on-Chip

NXP Semiconductors

Table 10. SSP Modes

MODE

DESCRIPTION

DATA TRANSFERS

Full-duplex, 4-wire

For communications with Motorola SPI-compatible

devices. Clock polarity and phase are programmable. synchronous

Motorola SPI

For communications with Texas Instruments DSP-

compatible Serial Synchronous Interface devices.

Full-duplex, 4-wire

synchronous

SSI

NationalSemiconductor For communications with National Semiconductor

Microwire Microwire-compatible devices.

Half-duplexsynchronous,using

8-bit control messages

WDT FEATURES

Watchdog Timer (WDT)

• Counter generates an interrupt at a set interval and

the count reloads from the pre-set value after reach-

ing zero.

The WDT consists of a 32-bit down-counter that

allows a selectable time-out interval to detect malfunc-

tions. The timer must be reset by software periodically.

Otherwise, a time-out occurs, interrupting the system.

If the interrupt is not serviced within the timeout period,

the WDT triggers the RCPC to generate a System

Reset. If the WDT times out, it sets a bit in the RCPC

Reset Status Register.

• Default timeout period is set to the minimum timeout

of 216 system clock cycles.

• WDT is driven by the APB.

• Built-in protection mechanism guards against

interrupt-service failure.

The WDT supports 16 selectable time intervals, for

a time-out of 216 through 231 system clock cycles. All

Control and Status Registers for the Watchdog Timer

are accessed through the APB.

• WDT can be programmed to trigger a System Reset

on a timeout.

• WDT can be programmed to trigger an interrupt on

the first timeout; then, if the service routine fails to

clear the interrupt, the next WDT timeout triggers a

System Reset.

30

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

The VIC also accepts software-generated interrupts.

Software-generated interrupts use the same enabling

control as hardware-generated interrupts.

Vectored Interrupt Controller (VIC)

All internal and external interrupts are routed to the

VIC, where hardware determines the interrupt priority

(see Table 11). The VIC is also where the appropriate

signal to the processor (IRQ or FIQ) is generated. The

processor services the interrupt as either a vectored

interrupt or a default-vectored interrupt.

The VIC provides 32 interrupts:

• 16 vectored interrupts

• 16 or more default-vectored interrupts.

Any of the 32 interrupt source lines can be assigned

to any of the 16 interrupt vectors. Any line not explicitly

assigned to an interrupt vector is processed as a

default-vectored interrupt. At reset, all 32 lines become

default-vectored interrupts.

The VIC accepts inputs from 32 interrupt source lines:

• Seven external

• Twenty-three internal

• Two used as software interrupts.

Each interrupt line can be explicitly identified as an

IRQ (default) or FIQ interrupt. Vectored-interrupt

servicing is only available for IRQ interrupts.

All 32 interrupt source lines can be enabled, disabled,

and cleared individually, and individual status can be

determined. On reset, all interrupts are disabled.

Table 11. Interrupt Channels

DESCRIPTION SOURCE

WDT Watchdog Timer

POSITION

0

1

Not Used

Available as a software interrupt

Sourced by the ARM7TDMI-S Core

Timer0

2

ARM7 DBGCOMMRX

ARM7 DBGCOMMTX

Timer0 Combined

Timer1 Combined

Timer2 Combined

External Interrupt 0

External Interrupt 1

External Interrupt 2

External Interrupt 3

External Interrupt 4

External Interrupt 5

External Interrupt 6

Not Used

3

4

5

Timer1

6

Timer2

7

Sourced by the GPIO Block

Available as a software interrupt

Real Time Clock

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

RTC_ALARM

ADC TSCIRQ (combined) Analog-to-Digital Converter

ADC BrownOutINTR

ADC PenIRQ

Brown Out Detector

Analog-to-Digital Converter

LCD Controller

Synchronous Serial Port

UART1

LCD

SSPTXINTR

SSPRXINTR

SSPRORINTR

SSPRXTOINTR

SSPINTR

UART1 UARTRXINTR

UART1 UARTTXINTR

UART1 UARTINTR

UART0 UARTINTR

UART2 Interrupt

DMA

UART1

UART0

UART2

DMA

CAN (LH75401)

Reserved (LH75411)

31

CAN

Product data sheet

Rev. 02 — 19 March 2009

31

LH75401/LH75411

System-on-Chip

NXP Semiconductors

The state of the TEST1, TEST2, and nRESETIN sig-

nals determines the operating mode entered at Power-

on Reset (see Table 12).

Reset, Clock, and Power Controller (RCPC)

The RCPC lets users control System Reset, clocks,

power management, and external interrupt condition-

ing via the AMBA APB interface. This control includes:

Table 12. Device Operating Modes

• Enabling and disabling various clocks

• Managing power-down sequencing

• Selecting the sources for various clocks.

OPERATING MODE

TEST2 TEST1 nRESETIN

Reserved

PLL Bypass

Reserved

EmbeddedICE

Normal

0

1

0

1

0

1

0

1

x

0

1

x

The RCPC provides for an orderly start-up until the

crystal oscillator stabilizes and the PLL acquires lock. If

users want to change the system clock frequency dur-

ing normal operation, the RCPC ensures a seamless

transition between the old and new frequencies.

RCPC FEATURES

NOTE: TEST1, TEST2, and nRESETIN are latched on the rising

edge of nPOR. The microcontroller stays in that operating

mode until power is removed or nPOR transitions from LOW

to HIGH.

• Manages five Power Modes for minimizing power

consumption: Active, Standby, Sleep, Stop1, and

Stop2

• Generates the system clock (HCLK) from either the

PLL clock or the PLL-bypassed (oscillator) clock,

divided by 2, 4, 6, 8, … 30

General Purpose Input/Output (GPIO)

The LH75401/LH75411 microcontrollers have 10

GPIO ports:

• Generates three UART clocks from oscillator clock

• Generates the 1 Hz RTC clock

• Seven 8-bit ports

• Two 7-bit ports

• One 6-bit port.

• Generates the SSP and LCD clocks from HCLK,

divided by 1, 2, 4, 8, 16, 32, or 64

• Provides a selectable external clock output

The GPIO ports are designated A through J and pro-

vide 76 bits of programmable input/output (see Table

13). Pins of all ports, except Port J, can be configured

as inputs or outputs. Port J is input only. Upon System

Reset, all ports default to inputs.

• Generates system and RTC Resets based on an

external reset, Watchdog Timer reset, or soft reset

• Configures seven HIGH/LOW-level or rising/falling

edge-trigger external interrupts and converts them to

HIGH-level trigger interrupt outputs required by the VIC

Table 13. GPIO Ports

• Generates remap outputs used by the memory map

decoder

PORT

PROGRAMMABLE PINS

8 Input/Output Pins

6 Input/Output Pins

8 Input/Output Pins

7 Input/Output Pins

8 Input/Output Pins

7 Input/Output Pins

8 Input/Output Pins

8 Input Pins

• Provides an identification register

A

B

C

D

E

F

G

H

I

• Supports external or watchdog reset status.

Operating Modes

The LH75401/LH75411 microcontrollers support

three operating modes:

• Normal Mode

• PLL Bypass Mode, where the internal PLL is

bypassed and an external clock source is used; oth-

erwise the chip operates normally

J

• EmbeddedICE Mode, where the JTAG port

accesses the TAP Controller in the core and the core

is placed in Debug Mode.

32

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

Device Pin Multiplexing

Table 14. LCD Panel Signal Multiplexing

4-BIT STN (MONOCHROME)

8-BIT STN SINGLE PANEL

(MONOCHROME)

EXTERNAL PIN

SINGLE PANEL

DUAL PANEL

LVCVD11

LVCVD10

LVCVD9

LVCVD8

LVCVD7

LVCVD6

LVCVD5

LVCVD4

LVCVD3

LVCVD2

LVCVD1

LVCVD0

Reserved

MUSTN3

MUSTN2

MUSTN1

MUSTN0

MLSTN3

MLSTN2

MLSTN1

MLSTN0

Reserved

MUSTN3

MUSTN2

MUSTN1

MUSTN0

Reserved

MUSTN7

MUSTN6

MUSTN5

MUSTN4

MUSTN3

MUSTN2

MUSTN1

MUSTN0

NOTES:

1. MUSTN = Mono upper panel STN, dual and/or single panel.

2. MLSTN = Mono lower panel STN, dual panel only.

Table 15. LCD External Pin Multiplexing (LH75401 and LH75411)

DEFAULT

MODE

(NO LCD)

4-BIT MONO STN MODE

8-BIT

STN MODE

TFT

MODE

ALI

MODE

EXTERNAL PIN

SINGLE

DUAL

PG4/LCDVEEEN/LCDMOD

PG3/LCDVDDEN

PG2/LCDDSPLEN/LCDREV

PG1/LCDCLS

PG4

PG3

PG2

PG1

PG0

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

PI7

LCDVEEEN

LCDVDDEN

LCDVEEEN

LCDVDDEN

LCDVEEEN

LCDVDDEN

LCDVEEEN

LCDVDDEN

LCDMOD

LCDVDDEN

LCDREV

LCDCLS

LCDPS

LCDDSPLEN LCDDSPLEN LCDDSPLEN LCDDSPLEN

PG1

PG0

PG1

PG0

PG1

PG0

PG1

PG0/LCDPS

PG0

PH7/LCDDCLK

PH6/LCDLP/LCDHRLP

PH5/LCDFP/LCDSPS

PH4/LCDEN/LCDEN

PH3/LCDVD11

PH2/LCDVD10

PH1/LCDVD9

LCDDCLK

LCDLP

LCDFP

LCDEN

PH3

LCDDCLK

LCDLP

LCDFP

LCDEN

MLSTN3

MLSTN2

MLSTN1

MLSTN0

PI7

LCDDCLK

LCDLP

LCDFP

LCDEN

PH3

LCDDCLK

LCDLP

LCDDCLK

LCDLP

LCDFP

LCDEN

LCDVD11

LCDVD10

LCDVD9

LCDVD8

LCDVD7

LCDVD6

LCDVD5

LCDVD4

LCDVD3

LCDVD2

LCDVD1

LCDVD0

LCDVD11

LCDVD10

LCDVD9

LCDVD8

LCDVD7

LCDVD6

LCDVD5

LCDVD4

LCDVD3

LCDVD2

LCDVD1

LCDVD0

PH2

PH1

PH0/LCDVD8

PH0

PI7/LCDVD7

PI7

STN7

STN6

STN5

STN4

STN3

STN2

STN1

STN0

PI6/LCDVD6

PI6

PI5/LCDVD5

PI5

PI4/LCDVD4

PI4

PI3/LCDVD3

PI3

MUSTN3

MUSTN2

MUSTN1

MUSTN0

MUSTN3

MUSTN2

MUSTN1

MUSTN0

PI2/LCDVD2

PI2

PI1/LCDVD1

PI1

PI0/LCDVD0

PI0

Product data sheet

Rev. 02 — 19 March 2009

33

LH75401/LH75411

System-on-Chip

NXP Semiconductors

ELECTRICAL SPECIFICATIONS

Table 16. Absolute Maximum Ratings

PARAMETER

MINIMUM MAXIMUM

DC Core Supply Voltage (VDDC)

DC I/O Supply Voltage (VDD)

-0.3 V

-55°C

2.4 V

4.6 V

2.4 V

125°C

DC Analog Supply Voltage for ADC (VDDA0)

DC Analog Supply Voltage for PLL (VDDA1)

Storage Temperature (TSTG)

NOTE: These ratings are only for transient conditions. Operation at

or beyond absolute maximum rating conditions may affect

reliability and cause permanent damage to the device.

Table 17. Recommended Operating Conditions

PARAMETER

MINIMUM

TYP.

MAXIMUM

NOTES

DC Core Supply Voltage (VDDC) (Linear Regulator disabled)

DC Analog Supply Voltage for ADC (VDDA0)

DC I/O Supply Voltage (VDD)

1.7 V

3.0 V

1.8 V

3.3 V

1.98 V

3.6 V

1

DC Analog Supply Voltage for PLL (VDDA1)

Clock Frequency (ƒHCLK)

2

1.7 V

4.375 MHz

11.9047 ns

14 MHz

1.8 V

1.98 V

84 MHz

228.571 ns

20 MHz

85°C

3, 4, 5

4, 5

Clock Period (tHCLK)

Crystal Frequency

Industrial Operating Temperature

40°C

25°C

NOTES:

1. Core Voltage should never exceed I/O Voltage after initial power up. See the section titled ‘Power Supply Sequencing’.

2. Connect VDDA1 to VDDC when using the on-chip linear regulator.

3. On-chip Linear regulator enabled. When the on-chip linear regulator is enabled, Core power is drawn from VDD – allow VDDC pins to float.

4. Will operate to DC with PLL disabled. Core frequencies greater than 84 MHz require external clock and VDDC. Core frequencies faster than

70 MHz require an externally-supplied clock.

5. Processor is functional at minimum frequency, but not all peripherals may be enabled.

6. The maximum operating frequency is the crystal frequency × 3.5.

Table 18. Clock Frequency vs. Voltages (VDDC) vs. Temperature

PARAMETER

1.7 V

1.8 V

1.9 V

Clock Frequency (ƒHCLK)

Clock Period (tHCLK)

91.3 MHz

10.952 ns

86 MHz

97 MHz

10.309 ns

92 MHz

103.7 MHz

9.643 ns

25°C

70°C

Clock Frequency (ƒHCLK)

Clock Period (tHCLK)

97.4 MHz

10.266 ns

95.2 MHz

10.504 ns

11.627 ns

84 MHz

10.869 ns

90 MHz

Clock Frequency (ƒHCLK)

Clock Period (tHCLK)

85°C

11.9047 ns

11.111 ns

NOTES:

1. On-chip Linear regulator and PLL disabled; VDDC supplied externally.

2. Core speeds greater than 84 MHz require external VDDC and may not yield proper UART baud rates.

3. Core speeds greater than 70 MHz require an external clock.

4. Additional performance may be achieved in accordance with Figure 5.

34

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

110

105

100

95

2 V

1.95 V

1.9 V

1.85 V

1.8 V

90

1.75 V

1.7 V

85

1.65 V

1.6 V

80

75

70

25

35

45

55

65

75

85

Temp ( Celsius)

˚

LH754xx-106

Figure 5. Maximum Core Frequency versus Voltage and Temperature

Very Low Operating Temperatures and

Noise Immunity

The junction temperature, Tj, is the operating tem-

perature of the transistors in the integrated circuit. The

switching speed of the CMOS circuitry within the SoC

depends partly on Tj, and the lower the operating tem-

perature, the faster the CMOS circuits will switch.

Increased switching noise generated by faster switch-

ing circuits could affect the overall system stability. The

amount of switching noise is directly affected by the

application executed on the SoC.

NXP recommends that users implementing a system

to meet low industrial temperature standards should use

an external oscillator rather than a crystal to drive the

system clock input of the System-on-Chip. This change

from crystal to oscillator will increase the robustness

(i.e., noise immunity of the clock input to the SoC.

Product data sheet

Rev. 02 — 19 March 2009

35

LH75401/LH75411

System-on-Chip

NXP Semiconductors

DC Characteristics

All characteristics are specified over an operating

temperature of 40°C to +85°C, and at minimum and

maximum supply voltages.

Table 19. DC Characteristics

MIN. TYP. MAX. UNIT

SYMBOL

PARAMETER

CONDITIONS

NOTES

VIH

VIL

CMOS Input HIGH Voltage

CMOS Input LOW Voltage

Schmitt Trigger Positive Going Threshold

Schmitt Trigger Negative Going Threshold

Schmitt Trigger Hysteresis

Output Drive 1

2.0

V

0.8

1

VT+

VT-

Vhst

2.0

0.35

2.6

IOH = -2 mA

IOH = -4 mA

IOH = -6 mA

IOH = -8 mA

IOL = 2 mA

Output Drive 2

VOH

VOL

Output Drive 3

Output Drive 4

Output Drive 1

0.4

Output Drive 2

IOL = 4 mA

Output Drive 3

IOL = 6 mA

Output Drive 4

IOL = 8 mA

XTAL32IN External Clock Input

1.62 1.8 1.98

Externally supplied

XTALIN

IIN

External Clock Input

Input Leakage Current

Active Current

-10

10

70

A VIN = VDD or GND

IACTIVE

50

45

mA

A

2

ISTANDBY Standby Current

ISLEEP

ISTOP1

Sleep Current

Stop1 Current

4.0

3.0

35

3

4

3

4

ISTOP2

Stop2 Current (RTC ON)

Stop2 Current (RTC OFF)

120

23

A

ISTOP2

100

A

NOTES:

3. Using external 1.8 V supply, internal regulator disabled.

4. Using Internal linear regulator.

1. VIL MAX. = 0.5 V for pin TCK with 50 pF load.

2. Running a Typical Application at 51.6 MHz.

Table 20. Linear Regulator DC Characteristics

PARAMETER MIN. TYP. MAX. UNIT

Quiescent Current

SYMBOL

IQUIESCENT

ISLEEPLR

IOLR

75

8

A

mA

V

Current when Regulator is Disabled

Output Current Range

Output Voltage

0.0

100

0

VOLR

1.84

RPULL

Pull-up Resistor



36

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

Analog-To-Digital Converter Electrical

Characteristics

Table 21 shows the derated specifications for

extended temperature operation. See Figure 6 for the

ADC transfer characteristics.

Table 21. ADC Electrical Characteristics at Industrial Operating Range

PARAMETER

A/D Resolution

MIN.

TYP.

MAX.

UNITS

NOTES

10

17

10

Bits

Throughput Conversion

Acquisition Time

CLK Cycles

1

3

CLK Cycles

Clk Period

500

5,000

4.5

ns

LSB

mV

LSB

V

Differential Non-Linearity

Integral Non-Linearity

Offset Error

-0.99

-3.5

+3.5

-35

+35

Gain Error

-4.0

4.0

On-chip Voltage Reference (VREF)

Negative Reference Input (VREF-)

Positive Reference Input (VREF+)

Crosstalk between channels

Analog Input Voltage Range

Analog Input Current

Reference Input Current

Analog input capacitance

Operating Supply Voltage

Operating Current, VDDA

Standby Current

1.85

2.0

VSSA

VREF

-60

2.15

VSSA

(VREF-) +1.0

(VREF+) -1.0

VDDA

V

2

V

dB

V

0

VDDA

5

3

A

pF

V

5

15

3.0

3.6

590

180

< 1

A

V

4

Stop Current, VDDA

Brown Out Trip Point

Brown Out Hysterisis

Operating Temperature

2.63

120

mV

°C

40

85

NOTES:

1. The analog section of the ADC takes 16 × A2DCLK cycles per conversion,

plus 1 × A2DCLK cycles to be made available in the PCLK domain.

An additional 3 × PCLK cycles are required before being available on the APB.

2. The internal voltage reference is driven to nominal value VREF = 2.0 V. Using the Reference Multiplexer,

alternative low impedance (RS < 500) voltages can be selected as reference voltages. The range of voltages

allowed are specified above. However, the on-chip reference cannot drive the ADC unless the reference buffer is switched on.

3. The analog input pins can be driven anywhere between the power supply rails. If the voltage at the input to the

ADC exceeds VREF+ or is below VREF-, the A/D result will saturate appropriately at positive or negative full scale.

Trying to pull the analog input pins above or below the power supply rails will cause protection diodes to be

forward-biased, resulting in large current source/sink and possible damage to the ADC.

4. Bandgap and other low-bandwidth circuitry operating. All other ADC blocks shut down.

Product data sheet

Rev. 02 — 19 March 2009

37

LH75401/LH75411

System-on-Chip

NXP Semiconductors

OFFSET GAIN

ERROR ERROR

1024

1023

1022

1021

1020

1019

1018

IDEAL

TRANSFER CURVE

9

8

7

6

5

4

3

2

1

CENTER OF A

STEP OF THE ACTUAL

TRANSFER CURVE

ACTUAL

TRANSFER CURVE

INTEGRAL

NON-LINEARITY

1

2

3

4

5

6

7

8

9

1015 1016 1017 1018 1019 1020 1021 1022 1023 1024

LSB

OFFSET

ERROR

DNL

754xx-54

Figure 6. ADC Transfer Characteristics

38

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

POWER SUPPLY SEQUENCING

PERIPHERAL CURRENT CONSUMPTION

When using an external 1.8 V supply (instead of the

internal 1.8 V regulator), the external 1.8 V power sup-

ply must be energized before the 3.3 V supply. Other-

wise, the 1.8 V supply may not lag the 3.3 V supply by

more than 10 µs.

In addition to the modal current consumption, Table

23 shows the typical current consumption for each of

the on-board peripheral blocks. The values were deter-

mined with the peripheral clock running at maximum

frequency, typical conditions, and no I/O loads. This

current is supplied by the 1.8 V power supply.

If a longer delay time is needed, the voltage differ-

ence between the two power supplies must be within

1.5 V during power supply ramp up.

Table 22. Current Consumption by Mode

To avoid a potential latchup condition, voltage

should be applied to input pins only after the device is

powered-on as described above.

SYMBOL

PARAMETER

TYP. UNITS

ACTIVE MODE

ICHIP

Chip Current with Linear Regulator

50.2

mA

LINEAR REGULATOR

ICORE Core Current without Linear Regulator 42.1

Although this device contains an on-board regulator,

using its output to power external devices is not recom-

mended. External loads can affect the regulator’s sta-

bility and introduce noise into the supply. NXP cannot

guarantee device performance at rated speeds and

temperatures with external loads connected to this

supply.

IIO

I/O Current without Linear Regulator

5

IANALOG Analog Current

1.3

STANDBY MODE (TYPICAL CONDITIONS ONLY)

ICHIP Core Current with Linear Regulator 42.7

ICORE Core Current without Linear Regulator 34.6

mA

IIO

Current drawn by I/O

0.8

1.3

IANALOG Analog Current

CURRENT CONSUMPTION BY OPERATING MODE

SLEEP MODE (TYPICAL CONDITIONS ONLY)

Current consumption can depend on a number of

parameters. To make this data more usable, the values

presented in Table 22 were derived under the condi-

tions presented here.

ICHIP

ICORE Core Current without Linear Regulator

IIO Current drawn by I/O

IANALOG Analog Current

STOP1 MODE

Core Current with Linear Regulator

3.9

2.5

400

1.2

mA

µA

mA

Maximum Specified Value

The values specified in the MAXIMUM column were

determined using these operating characteristics:

Core Current with Linear Regulator, I/O,

and 14.7456 MHz osc.

ISTOP

2.96

mA

• All IP blocks either operating or enabled at maximum

frequency and size configuration

STOP2 MODE (RTC ON)

Leakage Current, Core and I/O

STOP2 MODE (RTC OFF)

ILEAK

34

18

µA

• Core operating at maximum power configuration

• All I/O loads at maximum (50 pF)

ILEAK

Leakage Current, Core and I/O

• All voltages at maximum specified values

• Maximum specified ambient temperature.

NOTES:

1. ICHIP = Chip Current with Linear Regulator (Core + I/O)

2. ICORE, IIO, IANALOG are the respective current consumption

specifications for VDDC, VDD, and VDDA.

Typical

The values in the TYPICAL column were determined

using a ‘typical’ application under ‘typical’ environmental

conditions and the following operating characteristics:

Table 23. Peripheral Current Consumption

PERIPHERAL

UARTs

TYPICAL

200

5

UNITS

µA

• SPI, Timer, and UART peripherals operating; all

other peripherals disabled

• LCD enabled with 320 × 240 × 16-bit color, 60 Hz

refresh rate

RTC

µA

DMA

4.1

mA

µA

• I/O loads at nominal

SSP

500

200

2.2

• FCLK = 51.6 MHz; HCLK = 51.6 MHz

• All voltages at typical values

• Nominal case temperature.

Counter/Timers

LCD

µA

mA

Product data sheet

Rev. 02 — 19 March 2009

39

LH75401/LH75411

System-on-Chip

NXP Semiconductors

AC Characteristics

All signal transitions are measured from the 50 %

point of the signal.

Table 24. Memory Interface Signals

SIGNAL

D[15:0]

I/O LOAD PARAMETER

MINIMUM

MAXIMUM

COMMENTS

Out 50 pF

tOVD

tOHD

tHCLK + 8 ns Data output valid following address valid

Data output invalid following address valid

D[15:0]

3 × tHCLK – 6 ns

2 tHCLK – 18 ns Data input valid following address valid

2 × tHCLK – 18 ns

D[15:0]

In

tIDD

Data Input Valid, following

Address Valid (nWAIT states)

+ (nWAIT –1)

× tHCLK

nCS3 - nCS0

nCS3 -nCS0

nOE

Out 30 pF

tOVCS

tOHCS

tOVOE

tOHOE

tOVBE

tHCLK + 6 ns nCS output valid following address valid

nCS output invalid following address valid

3 × tHCLK – 6 ns

tHCLK + 10 ns nOE output valid following address valid

nOE output invalid following address valid

nOE

nBLE1 - nBLE0 Out 30 pF

tHCLK + 10 ns nBLE output valid following address valid

nBLE output invalid following address

valid, read cycle

nBLE1 - nBLE0 Out 30 pF

tOHBER

tOHBEW

3 × tHCLK – 6 ns

2 × tHCLK – 6 ns

nBLE output invalid following address

valid, write cycle

nBLE1 - nBLE0 Out 30 pF

nWE

Out 30 pF

In

tOVWE

tOHWE

tIVWAIT

tHCLK + 10 ns nWE output valid following address valid

nWE

2 × tHCLK – 6 ns 2 tHCLK – 2.2 ns nWE output invalid following address valid

2 tHCLK – 18 ns nWAIT input valid following address valid

nWAIT

NOTE: The values in Table 24 represent the timing with no internal arbitration

delay and 1 wait state memory access. This is the worst case (fastest) timing.

Table 25. Synchronous Serial Port

SIGNAL

I/O LOAD PARAMETER MIN. MAX.

COMMENT

SSPFRM Out 50 pF

tOVSSPFRM

tOVSSPTX

tISSPRX

14 ns SSPFRM output valid, referenced to SSPCLK

12 ns SSPTX output valid, referenced to SSPCLK

SSPRX input valid, referenced to SSPCLK

SSPTX

SSPRX

Out 50 pF

In

22 ns

Table 26. Power-up Stabilization

DESCRIPTION

PARAMETER

TYP.

MAX.

UNIT

tLREG

tOSC32

tOSC14

tRSTOV

tPORH

Linear regulator stabilization time after power-up

200

550

2.5

s

ms

Oscillator stabilization time after Power Up (VDDC = VDDCMIN)

nPOR LOW to nPOR valid (once sampled LOW)

ms

3.5

HCLK

s

nPOR hold extend to allow PLL to lock once XTAL is stable

10

40

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

VDDmin

VDD

tOSC32

PLL

XTAL32

XTAL14

tPORH

tOSC14

LREG

nPOR

VDDCmin

tLREG

LH754xx-100

Figure 7. Power-up Stabilization

memory. If N wait states are programmed, the SMC

holds this state for N system clocks or until the SMC

detects that nWAIT is inactive, whichever occurs last.

As the number of wait states programmed increases,

the amount of delay before nWAIT must be asserted

also increases. If only 2 wait states are programmed,

nWAIT must be asserted in the clock cycle immediately

following the clock cycle during which the nCSx signal

is asserted. Once the SMC detects that the external

device has deactivated nWAIT, the SMC completes its

access in 3 system clock cycles.

MEMORY CONTROLLER WAVEFORMS

Static Memory Controller Waveforms

Figure 8 shows the waveform and timing for an

External Static Memory Write, with one Wait State. Fig-

ure 9 shows the waveform and timing for an External

Static Memory Write, with two Wait States. Figure 10

shows the waveform and timing for an External Static

Memory Read, with one Wait State.

The SMC supports an nWAIT input that can be used

by an external device to extend the wait time during a

memory access. The SMC samples nWAIT at the

beginning of at the beginning of each system clock

cycle. The system clock cycle in which the nCSx signal

is asserted counts as the first wait state. See Figure 11.

The SMC recognizes that nWAIT is active within 2

clock cycles after it has been asserted. To assure that

the current access (read or write) will be extended by

nWAIT, program at least two wait states for this bank of

The formula for the allowable delay between assert-

ing nCSx and asserting nWAIT is:

tASSERT = (system clock period) × (Wait States - 1)

(where Wait States is from 2 to 31.)

The signal tIDD is shown without a setup time, as

measurements are made from the Address Valid point

and HCLK is an internal signal, shown for reference only.

Product data sheet

Rev. 02 — 19 March 2009

41

LH75401/LH75411

System-on-Chip

NXP Semiconductors

Figure 8. External Static Memory Write, One Wait State

42

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

Figure 9. External Static Memory Write, Two Wait States

Product data sheet

Rev. 02 — 19 March 2009

43

LH75401/LH75411

System-on-Chip

NXP Semiconductors

Figure 10. External Static Memory Read, One Wait State

44

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

Figure 11. External Static Memory Read, nWAIT Active

Product data sheet

Rev. 02 — 19 March 2009

45

LH75401/LH75411

System-on-Chip

NXP Semiconductors

Synchronous Serial Port Waveform

Figure 12. Synchronous Serial Port Waveform

46

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

SoSize = DeSize and SoBurst = 4.

DMA Controller Timing Diagrams

Figure 13 and Figure 14 show examples of DMA

timing diagrams.

• Figure 14 shows the timing for a memory-to-periph-

eral data transfer, where

SoSize = DeSize and SoBurst = 4.

• Figure 13 shows the timing for a peripheral-to-mem-

ory data transfer, where

Figure 13. Peripheral-to-Memory Data-Transfer Timing

Product data sheet

Rev. 02 — 19 March 2009

47

LH75401/LH75411

System-on-Chip

NXP Semiconductors

Figure 14. Memory-to-Peripheral Data-Transfer Timing

48

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

TFT HORIZONTAL TIMING

Color LCD Controller Timing Waveforms

Figure 17 shows typical horizontal timing waveforms

for TFT panels.

This section describes typical output waveform dia-

grams for the CLCDC and the Advanced LCD Interface.

TFT VERTICAL TIMING

STN HORIZONTAL TIMING

Figure 18 shows typical vertical timing waveforms

for TFT panels.

Figure 15 shows typical horizontal timing waveforms

for STN panels. In this figure, the CLCDC Clock (an

input to the CLCDC) is scaled within the CLCDC and

used to produce the LCDDCLK output. Programmable

registers in the CLCDC set the timings (in terms of

LCDDCLK pulses) to produce the other signals that

control an STN display.

AD-TFT/HR-TFT HORIZONTAL TIMING WAVE-

FORMS

Figure 19 shows typical horizontal timing waveforms

for AD-TFT and HR-TFT panels. The ALI adjusts the

normal TFT timing to accommodate these panels.

For example, Figure 15 shows that the duration of

the LCDLP signal is controlled by Timing0:HSW

(the HSW bit field in the Timing0 Register). Figure

15 also shows that the polarity of the LCDLP sig-

nal is set by Timing2:IHS.

AD-TFT/HR-TFT VERTICAL TIMING WAVEFORMS

Figure 20 shows typical vertical timing waveforms

for AD-TFT and HR-TFT panels. The power sequenc-

ing and register information is the same as for TFT ver-

tical timing.

STN VERTICAL TIMING

Figure 16 shows typical vertical timing waveforms

for STN panels.

Product data sheet

Rev. 02 — 19 March 2009

49

LH75401/LH75411

System-on-Chip

NXP Semiconductors

Figure 15. STN Horizontal Timing Diagram

50

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

Figure 16. STN Vertical Timing Diagram

Product data sheet

Rev. 02 — 19 March 2009

51

LH75401/LH75411

System-on-Chip

NXP Semiconductors

Figure 17. TFT Horizontal Timing Diagram

52

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

Figure 18. TFT Vertical Timing Diagram

Product data sheet

Rev. 02 — 19 March 2009

53

LH75401/LH75411

System-on-Chip

NXP Semiconductors

1 AD-TFT or HR-TFT HORIZONTAL LINE

*

CLCDCLK

(INTERNAL)

AD-TFT and HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED

Timing0:HSW

APBPeriphClkCtrl1:LCD

ClkPrescale:LCDPS

(SHOWN FOR REFERENCE)

LCDLP

(HORIZONTAL

SYNCHRONIZATION

PULSE)

LCDDCLK

(PANEL CLOCK)

Timing2:PCD

Timing2:BCD

Timing2:IPC

Timing2:CPL

LCDVD[11:0]

001 002 003 004 005 006 007 008

320

PIXEL DATA

Timing0:HSW +

Timing0: HBP

LCDEN

(DATA ENABLE)

LCDDCLK

(DELAYED FOR

AD-TFT, HR-TFT)

LCDVD[11:0]

(DELAYED FOR

AD-TFT, HR-TFT)

001 002 003 004 005 006

317 318 319 320

1 LCDDCLK

LCDSPL

(AD-TFT, HR-TFT

START PULSE LEFT)

1 LCDDCLK

Timing1:LPDEL

LCDLP

(HORIZONTAL

SYNCHRONIZATION

PULSE)

Timing1:CLSDEL

Timing2:CLSDEL2

LCDCLS

LCDPS

Timing1:REVDEL

LCDREV

NOTE:

*

Source is RCPC.

LH754xx-80

Figure 19. AD-TFT, HR-TFT Horizontal Timing Diagram

Timing1:VSW

1.5 µs - 4 µs

LCDSPS

(VERTICAL

SYNCHRONIZATION)

LCDLP

(HORIZONTAL

SYNCHRONIZATION

PULSE)

LCDVD[11:0]

(LCD VIDEO DATA)

NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz.

LH754xx-81

Figure 20. AD-TFT, HR-TFT Vertical Timing Diagram

54

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

Figure 22 shows the suggested external compo-

nents for the 14.7456 MHz crystal circuit to be used

with the NXP LH75401/LH75411. The NAND gate rep-

resents the logic inside the SoC. See the chart for crys-

tal specifics.

SUGGESTED EXTERNAL COMPONENTS

Figure 21 shows the suggested external compo-

nents for the 32.768 kHz crystal circuit to be used with

the NXP LH75401/LH75411. The NAND gate repre-

sents the logic inside the SoC. See the chart for crys-

tal specifics.

ENABLE

INTERNAL TO THE

LH75400, LH75401,

LH75410, LH75411

EXTERNAL TO THE

LH75400, LH75401,

LH75410, LH75411

XTAL32IN

XTAL32OUT

Y1

32.768 kHz

R1

18 MΩ

C1

C2

15 pF

18 pF

GND

NOTES:

RECOMMENDED CRYSTAL SPECIFICATIONS

1. Y1 is a parallel-resonant type crystal. (See table)

2. The nominal values for C1 and C2 shown are for

a crystal specified at 12.5 pF load capacitance (CL).

3. The values for C1 and C2 are dependent upon

the cystal's specified load capacitance and PCB

stray capacitance.

PARAMETER

DESCRIPTION

32.768 kHz Crystal

Tolerance

Parallel Mode

±30 ppm

Aging

±3 ppm

4. R1 must be in the circuit.

Load Capacitance

ESR (MAX.)

12.5 pF

5. Ground connections should be short and return

to the ground plane which is connected to the

processor's core ground pins.

50 kΩ

1.0 µW (MAX.)

Drive Level

Recommended Part

MTRON SX1555 or equivalent

6. Tolerance for R1, C1, C2 is ≤ 5%.

LH754xx-101

Figure 21. Suggested External Components, 32.768 kHz Oscillator

Product data sheet

Rev. 02 — 19 March 2009

55

LH75401/LH75411

System-on-Chip

NXP Semiconductors

ENABLE

INTERNAL TO THE

LH75400, LH75401,

LH75410, LH75411

EXTERNAL TO THE

LH75400, LH75401,

LH75410, LH75411

XTALIN

XTALOUT

Y1

14.7456 MHz

R1

1 MΩ

C1

C2

18 pF

22 pF

GND

RECOMMENDED CRYSTAL SPECIFICATIONS

NOTES:

PARAMETER

DESCRIPTION

1. Y1 is a parallel-resonant type crystal. (See table)

2. The nominal values for C1 and C2 shown are for

a crystal specified at 18 pF load capacitance (CL).

3. The values for C1 and C2 are dependent upon

the cystal's specified load capacitance and PCB

stray capacitance.

14.7456 MHz Crystal (AT-Cut) Parallel Mode

Tolerance

±50 ppm

±100 ppm

±5 ppm

Stability

Aging

4. R1 must be in the circuit.

Load Capacitance

ESR (MAX.)

Drive Level

Recommended Part

18 pF

5. Ground connections should be short and return

to the ground plane which is connected to the

processor's core ground pins.

40 Ω

100 µW (MAX.)

MTRON SX2050 or equivalent

6. Tolerance for R1, C1, C2 is ≤ 5%.

LH754xx-102

Figure 22. Suggested External Components, 14.7456 MHz Oscillator

56

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

PACKAGE SPECIFICATIONS

LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm

SOT486-1

y

X

A

108

109

73

72

Z

E

e

H

A

E

2

A

E

(A )

3

A

1

θ

w M

p

L

p

b

L

pin 1 index

detail X

37

144

1

36

v

M

A

Z

w M

D

b

p

e

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

E

L

p

v

w

y

Z

E

θ

1

2

3

p

D

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 20.1 20.1

0.17 0.09 19.9 19.9

22.15 22.15

21.85 21.85

0.75

0.45

1.4

1.1

1.4

1.1

mm

1.6

0.25

1

0.2 0.08 0.08

0.5

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-03-14

03-02-20

SOT486-1

136E23

MS-026

Figure 23. Package outline SOT486-1 (LQFP144)

Product data sheet

Rev. 02 — 19 March 2009

57

LH75401/LH75411

144LQFP

System-on-Chip

NXP Semiconductors

21.2

0.5

1.6

17.5

NOTE: Dimensions in mm.

144LQFP

Figure 24. Recommended PCB Footprint

58

Rev. 02 — 19 March 2009

Product data sheet

System-on-Chip

LH75401/LH75411

NXP Semiconductors

REVISION HISTORY

Table 27. Revision history

Document ID

Release date Data sheet status

20090319 Product data sheet

Change notice Supersedes

LH75401_411_N_2

Modifications:

-

LH75401_411_N_1

• Changed document status to “Product data sheet”.

LH75401_411_N_1

20070716

Preliminary data sheet

-

LH754xx Data Sheet 5-10-07

Product data sheet

Rev. 02 — 19 March 2009

59

LH75401/LH75411

System-on-Chip

NXP Semiconductors

1. Annex A - Legal information

1.1

Data sheet status

[1][2]

[3]

Document status

Product status

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

1.2

Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the full

data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the Product

data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party customer(s).

NXP does not accept any liability in this respect.

1.3

Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance with

the Terms and conditions of commercial sale of NXP Semiconductors.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Export control — This document as well as the item(s) described herein may

be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

60

Rev. 02 — 19 March 2009

Product data sheet

LH75401/LH75411

System-on-Chip

NXP Semiconductors

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of non-automotive

qualified products in automotive equipment or applications.

damages or failed product claims resulting from customer design and use of

the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at customer’s own

risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,

1.4

Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

2. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com


型号：	LH75411N0Q100C0,55
厂家：	NXP
描述：	LH75411N0Q100C0SOT486-1 时钟外围集成电路
文件：	总62页 (文件大小：604K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LH75411N0Q100C0,55 [NXP]

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