LH79520N0M000B1,55 [NXP]
LH79520N0M000B1;
| 型号： | LH79520N0M000B1,55 |
| 厂家： | 
NXP |
| 描述： | LH79520N0M000B1 |
| 文件： | 总59页 (文件大小：666K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LH79520
System-on-Chip
Preliminary data sheet
• 64 Programmable General Purpose I/O Signals
– Multiplexed with Peripheral I/O Signals
FEATURES
• Highly Integrated System-on-Chip
• Programmable Color LCD Controller
– Up to 800 × 600 Resolution
• High Performance (77.4144 MHz CPU Speed)
• ARM720T™ RISC Core
– 32-bit ARM7TDMI™ RISC Core
– 8 kB Cache
– Supports STN, Color STN, AD-TFT, TFT
– Supports 15 Shades of Gray
– TFT: Supports 64 k Direct Colors or 256 Colors
selected from a Palette of 64,000 Colors
– Color STN: Supports 3,375 Direct Colors or 256
Colors Selected from a Palette of 3,375 Colors
– MMU (Windows CE™ Enabled)
– Write Buffer
• 32 kB On-Chip SRAM
• Flexible, Programmable Memory Interface
– SDRAM Interface
• Synchronous Serial Port
– Supports Data Rates Up to 1.8452 Mb/s
– Compatible with Common Interface Schemes
– Motorola SPI™
– 15-bit External Address Bus
– 32-bit External Data Bus
– National Semiconductor MICROWIRE™
– Texas Instruments SSI
– Two Segments (128 MB each)
– SRAM/Flash/ROM Interface
– 26-bit External Address Bus
– 32-bit External Data Bus
• JTAG Debug Interface and Boundary Scan
• 5 V Tolerant Digital I/O
– Seven Segments (64 MB Each)
– XTALIN and XTAL32IN inputs are 1.8 V 10 %
• Multi-stream DMA Controller
– Four 32-bit Burst-based Data Streams
DESCRIPTION
• Clock and Power Management
The LH79520, powered by an ARM720T, is a com-
plete System-on-Chip with a high level of integration to
satisfy a wide range of requirements and expectations.
The LH79520 combines a 32-bit ARM720T RISC,
Color LCD controller, Cache, Local SRAM, a number of
essential peripherals such as Direct Memory Access,
Serial and Parallel Interfaces, Infrared support, Timers,
Real Time Clock, Watchdog Timer, Pulse Width Modu-
lators, and an on-chip Phase Lock Loop. Debug is
made simple by JTAG support.
– 32.768 kHz Oscillator for Real Time Clock
– 14.7456 MHz Oscillator and On-chip PLL for
CPU and Bus Clocks
– Active, Standby, Sleep and Stop Power Modes
– Externally-supplied Clock Options
• Low Power Modes
– Active Mode: 55 mA (MAX.)
– Standby Mode: 35 mA (MAX.)
– Sleep Mode: 5.5 mA (MAX.)
– Stop Mode 2: 18 µA
This high level of integration lowers overall system
costs, reduces development cycle time and acceler-
ates product introduction. The LH79520’s fully static
design, power management unit, low voltage operation
(1.8 V Core, 3.3 V I/O), on-chip PLL, fast interrupt
response time, on-chip cache and SRAM, powerful
instruction set, and low power RISC core provide high
performance.
• Watchdog Timer
• Vectored Interrupt Controller
– 16 Standard and 16 Vectored IRQ Interrupts
– Hardware Interrupt Priority
– Software Interrupts
– FIQ Fast Interrupts
To build an advanced portable device, advanced pro-
cessing capability is required. This capability must come
with increased performance in the display system and
peripherals, and yet demand less power from batteries.
The LH79520 is an integrated solution to fit these needs.
• Three UARTs
– 16-byte FIFOs for Rx and Tx
– IrDA SIR Support
– Supports Data Rates Up to 460.8 kb/s
• Two 16-bit Pulse Width Modulators
• Two Dual Channel Timer Modules
• Real Time Clock
– 32-bit Up-counter with Programmable Load
– Programmable 32-bit Match Compare Register
Preliminary data sheet
1
LH79520
NXP Semiconductors
System-on-Chip
ORDERING INFORMATION
Table 1. Ordering information
Package
Type number
Version
Name
LQFP176
Description
plastic low profile quad flat package; 176 leads;
body 20 x 20 x 1.4 mm
LH79520N0Q000B1
SOT1017-1
2
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
DEBUG/TEST
INTERFACE
EXTERNAL
INTERRUPTS
14.7456 MHz 32.768 kHz
RESET
OSCILLATOR,
PLL POWER
MANAGEMENT, and
RESET CONTROL
REAL TIME
CLOCK
GENERAL
PURPOSE I/O
32KB
SRAM
TEST
LOGIC/PIN
MUXING
ARM 720T
CONDITIONED
EXTERNAL
INTERRUPTS
I/O
CONFIGURATION
SYNCHRONOUS
SERIAL PORT
VECTORED
INTERRUPT
CONTROLLER
STATIC
MEMORY
CONTROLLER
TIMER (4)
EXTERNAL
BUS
INTERFACE
INTERNAL
INTERRUPTS
WATCHDOG
TIMER
SDRAM
CONTROLLER
DMA
CONTROLLER
DUAL
CHANNEL PWM
ADVANCED
PERIPHERAL
BUS BRIDGE
UART (3)
IrDA
INTERFACE
COLOR
LCD
CONTROLLER
ADVANCED HIGH
ADVANCED
PERFORMANCE
BUS (AHB)
PERIPHERAL
BUS (APB)
ADVANCED
LCD
INTERFACE
79520-1B
Figure 1. LH79520 block diagram
Preliminary data sheet
Rev. 01 — 16 July 2007
3
LH79520
NXP Semiconductors
System-on-Chip
PIN CONFIGURATION
1
132
LH79520
44
89
002aad212
Figure 2. LH79520 pin configuration
4
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
NOTES
SIGNAL DESCRIPTIONS
Table 2. LH79520 Signal Descriptions
PIN NO. SIGNAL NAME
TYPE
DESCRIPTION
MEMORY INTERFACE (MI)
2-7
9-12
14-17
19-22
24-27
29-32
A[25:0]
D[31:0]
Output
Address Signals
50-54
56-63
65-66
67-69
71-74
76-79
81-84
86-87
Input/Output Data Input/Output Signals
1
101
109
110
111
112
102
104
105
107
108
106
41
SDCLK
DQM3
DQM2
DQM1
DQM0
SDCKE
nDCS1
nDCS0
nRAS
nCAS
nSDWE
nCS6
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
SDRAM Clock
1
1
1
1
1
1
1
1
Data Mask Output to SDRAMs
Data Mask Output to SDRAMs
Data Mask Output to SDRAMs
Data Mask Output to SDRAMs
SDRAM Clock Enable
SDRAM Chip Select
SDRAM Chip Select
Row Address Strobe
Column Address Strobe
SDRAM Write Enable
1
1
1
1
1
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Output Enable
Static Memory Controller Byte Lane Enable / Byte Write Enable
Static Memory Controller Byte Lane Enable / Byte Write Enable
Static Memory Controller Byte Lane Enable / Byte Write Enable
Static Memory Controller Byte Lane Enable / Byte Write Enable
Static Memory Controller Write Enable
Static Memory Controller External Wait Control
DMA CONTROLLER (DMAC)
DMA 0 End of Transfer
42
nCS5
43
nCS4
44
nCS3
46
nCS2
47
nCS1
48
nCS0
38
nOE
34
nBLE3
nBLE2
nBLE1
nBLE0
nWE
1
1
35
36
37
39
144
nWAIT
1, 3
148
147
146
157
145
144
DEOT0
nDACK0
DREQ0
DEOT1
DACK1
DREQ1
Output
Output
Input
1
1
DMA 0 Acknowledge
DMA 0 Request
1
Output
Output
Input
DMA 1 End of Transfer
1
DMA 1 Acknowledge
1
DMA 1 Request
1, 3
Preliminary data sheet
Rev. 01 — 16 July 2007
5
LH79520
NXP Semiconductors
System-on-Chip
NOTES
Table 2. LH79520 Signal Descriptions (Cont’d)
PIN NO. SIGNAL NAME
TYPE
DESCRIPTION
COLOR LCD CONTROLLER (CLCDC)
130
132
139
140
141
142
114
115
116
117
LCDVD[17:0]
Output
LCD Panel Data bus
1
118
119
121
122
123
124
126
127
137
129
LCDENAB
LCDFP
Output
Output
LCD Data Enable
1
1
Frame Pulse (STN), Vertical Synchronization Pulse (TFT)
Line Synchronization Pulse (STN),
Horizontal Synchronization Pulse (TFT)
131
LCDLP
Output
1
133
134
135
135
129
142
137
119
LCDDCLK
LCDDCLKIN
LCDVDDEN
LCDCLS
Output
Input
LCD Panel Data Clock
1
1
1
1
1
1
1
1
LCD External Clock Input
Output
Output
Output
Output
Output
Output
LCD Digital Supply Enable
LCD Clock Signal for Gate Driver (AD-TFT, HR-TFT only)
LCD Reset Signal for Row Display (AD-TFT, HR-TFT only)
LCD Reverse Signal (AD-TFT, HR-TFT only)
LCD Line Start Pulse (Left) (AD-TFT, HR-TFT only)
LCD Power Save (AD-TFT, HR-TFT only)
SYNCHRONOUS SERIAL PORT (SSP)
SSP Serial Frame Output
LCDSPS
LCDREV
LCDSPL
LCDPS
164
165
166
167
169
SSPFRM
SSPCLK
SSPEN
SSPTX
Output
Output
Output
Output
Input
1
1
1
1
1
SSP Clock
SSP Data Enable
SSP Data Out
SSPRX
SSP Data In
PULSE WIDTH MODULATOR (PWM)
PWM0 Output
150
151
157
PWM0
Output
Input
1
1
1
PWMSYNC0
PWM1
PWM0 Synchronizing Input
PWM1 Output
Output
UART0 (U0)
163
162
163
162
UARTRX0
UARTTX0
Input
Output
Input
UART0 Received Serial Data Input
UART0 Transmitted Serial Data Output
UART0 InfraRed Receive
1
1
1
1
UARTIRRX0
UARTIRTX0
Output
UART0 InfraRed Transmit
6
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
NOTES
Table 2. LH79520 Signal Descriptions (Cont’d)
PIN NO. SIGNAL NAME
TYPE
DESCRIPTION
UART1 (U1)
160
159
UARTRX1
UARTTX1
Input
UART1 Received Serial Data Input
UART1 Transmitted Serial Data Output
UART2 (U2)
1
1
Output
169
167
UARTRX2
UARTTX2
Input
UART2 Received Serial Data Input
UART2 Transmitted Serial Data Output
1
1
Output
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
153
155
156
159
160
164
165
166
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Input/Output General Purpose I/O Signals - Port A
1
1
1
1
1
1
139
140
141
142
146
147
148
152
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Input/Output General Purpose I/O Signals - Port B
Input/Output General Purpose I/O Signals - Port C
Input/Output General Purpose I/O Signals - Port D
Input/Output General Purpose I/O Signals - Port E
129
130
131
132
133
134
135
137
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
116
117
118
119
121
122
123
124
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
102
104
105
106
109
110
111
112
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
61
62
63
65
66
67
99
101
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
General Purpose I/O Signals - Port F.
Input/Output GPIO PF1 is only available when CLKINSEL is ‘0’
(i.e. the external clock source is not being used).
Preliminary data sheet
Rev. 01 — 16 July 2007
7
LH79520
NXP Semiconductors
System-on-Chip
Table 2. LH79520 Signal Descriptions (Cont’d)
PIN NO. SIGNAL NAME
TYPE
DESCRIPTION
NOTES
52
53
54
56
57
58
59
60
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
Input/Output General Purpose I/O Signals - Port G
1
34
35
41
42
43
44
50
51
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
Input/Output General Purpose I/O Signals - Port H
1
1
COUNTER/TIMER (C/T)
145
CTOUT1B
Output
Counter/Timer Output
RESET, CLOCK, AND POWER CONTROLLER (RCPC)
96
97
nRESETIN
nRESETOUT
INT7
Input
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Output
Input
Input
Reset Input
Reset Output
114
115
144
150
151
152
153
155
93
External Interrupt Input
External Interrupt Input
External Interrupt Input
External Interrupt Input
External Interrupt Input
External Interrupt Input
External Interrupt Input
External Interrupt Input
Crystal Input
1
1
INT6
INT5
1, 3
1
INT4
INT3
1
INT2
1
INT1
1
INT0
1
XTALIN
XTALOUT
XTAL32IN
XTAL32OUT
CLKINSEL
CLKIN
94
Crystal Output
89
32.768 kHz Crystal Oscillator Input
32.768 kHz Crystal Oscillator Output
External Clock Select
90
88
98
External Clock Input (if CLKINSEL = HIGH at reset)
1
1
External Clock Enable
(if CLKINSEL = LOW at reset, then this pin functions as PF1)
99
CLKEN
Output
156
98
CLKOUT
Output
Input
Clock Out (selectable from the internal bus clock or 32.768)
External UART Clock Input (with CLKSEL = LOW)
TEST INTERFACE
1
1
UARTCLK
174
170
173
172
171
175
nTRST
TMS
Input
Input
Input
Input
Output
Input
JTAG Test Reset Input
JTAG Test Mode Select Input
TCLK
TDI
JTAG Test Clock Input
JTAG Test Serial Data Input
TDO
JTAG Test Data Serial Output
TEST1
Tie LOW for Normal Operation (has internal pull-down).
JTAG Debug Enable: Tie LOW for Normal Operation; pull HIGH to
enable JTAG Debugging (has internal pull-down).
176
1
TEST2
nTSTA
Input
Input
Tie HIGH for Normal Operation (has internal pull-up).
8
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
NOTES
Table 2. LH79520 Signal Descriptions (Cont’d)
PIN NO. SIGNAL NAME
TYPE
DESCRIPTION
POWER AND GROUND (GND)
40
75
95
113
136
154
VDDC
Power
Core Power Supply
Core GND
45
120
138
VSSC
Ground
158
8
18
28
49
64
85
VDD
Power
Input/Output Power Supply
100
125
143
161
13
23
33
55
70
80
VSS
Ground
Input/Output GND
103
128
149
168
91
92
VDDA
VSSA
Power
Analog Power Supply for PLLs and XTAL Oscillators
Analog GND for PLLs and XTAL Oscillators
Ground
NOTES:
1. These pin numbers have multiplexed functions.
2. Signals preceded by ‘n’ are Active LOW.
3. Immediately after reset, pin 144 can be programmed to function as INT5, DREQ1 or both.
Software should avoid enabling both of these functions simultaneously. Pin 144 can also be
programmed to function as nWAIT, rendering the INT5/DREQ1 choice unavailable.
Preliminary data sheet
Rev. 01 — 16 July 2007
9
LH79520
NXP Semiconductors
System-on-Chip
NUMERICAL PIN LIST
Table 3. LH79520 Numerical Pin List
FUNCTION AT
RESET
OUTPUT
5
PIN NO.
FUNCTION 2 FUNCTION 3 TYPE
NOTES
7
DRIVE
1
nTSTA
A25
A24
A23
A22
A21
A20
VDD
A19
A18
A17
A16
VSS
A15
A14
A13
A12
VDD
A11
A10
A9
Input
Output
Output
Output
Output
Output
Output
Power
Output
Output
Output
Output
Ground
Output
Output
Output
Output
Power
Output
Output
Output
Output
Ground
Output
Output
Output
Output
Power
Output
Output
Output
Output
Ground
I/O
None
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
None
8 mA
8 mA
8 mA
8 mA
None
8 mA
8 mA
8 mA
8 mA
None
8 mA
8 mA
8 mA
8 mA
None
8 mA
8 mA
8 mA
8 mA
None
8 mA
8 mA
8 mA
8 mA
None
8 mA
8 mA
8 mA
8 mA
8 mA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A8
VSS
A7
A6
A5
A4
VDD
A3
A2
A1
A0
VSS
PH7
PH6
nBLE1
nBLE0
nOE
nBLE3
nBLE2
I/O
Output
Output
Output
10
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
PIN NO.
NXP Semiconductors
LH79520
Table 3. LH79520 Numerical Pin List (Cont’d)
FUNCTION AT
OUTPUT
5
FUNCTION 2 FUNCTION 3 TYPE
NOTES
7
RESET
DRIVE
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
nWE
VDDC
PH5
PH4
PH3
PH2
VSSC
nCS2
nCS1
nCS0
VDD
PH1
PH0
PG7
PG6
PG5
VSS
PG4
PG3
PG2
PG1
PG0
PF7
Output
Power
I/O
8 mA
None
8 mA
8 mA
8 mA
8 mA
None
8 mA
8 mA
8 mA
None
8 mA
8 mA
8 mA
8 mA
8 mA
None
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
None
8 mA
8 mA
8 mA
8 mA
8 mA
None
8 mA
8 mA
8 mA
8 mA
None
8 mA
8 mA
nCS6
nCS5
nCS4
nCS3
I/O
I/O
I/O
Ground
Output
Output
Output
Power
I/O
D31
D30
D29
D28
D27
I/O
I/O
I/O
I/O
Ground
I/O
D26
D25
D24
D23
D22
D21
D20
D19
I/O
I/O
I/O
I/O
I/O
PF6
I/O
PF5
I/O
VDD
PF4
Power
I/O
D18
D17
D16
PF3
I/O
PF2
I/O
D15
I/O
D14
I/O
VSS
D13
Ground
I/O
D12
I/O
D11
I/O
D10
I/O
VDDC
D9
Power
I/O
D8
I/O
Preliminary data sheet
Rev. 01 — 16 July 2007
11
LH79520
PIN NO.
NXP Semiconductors
System-on-Chip
Table 3. LH79520 Numerical Pin List (Cont’d)
FUNCTION AT
OUTPUT
5
FUNCTION 2 FUNCTION 3 TYPE
NOTES
7
RESET
DRIVE
78
79
D7
D6
I/O
I/O
8 mA
8 mA
None
8 mA
8 mA
8 mA
8 mA
None
8 mA
8 mA
None
None
80
VSS
Ground
I/O
81
D5
82
D4
I/O
83
D3
I/O
84
D2
I/O
85
VDD
Power
I/O
86
D1
87
D0
I/O
88
CLKINSEL
XTAL32IN
XTAL32OUT
VDDA
VSSA
XTALIN
XTALOUT
VDDC
nRESETIN
nRESETOUT
CLKIN
PF1
Input
Input
Output
Power
Ground
Input
Output
Power
Input
Output
Input
I/O
2
8
3
89
90
91
None
None
None
92
93
8
3
94
95
None
None
4 mA
None
2 mA
None
8 mA
8 mA
None
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
None
8 mA
8 mA
8 mA
96
1, 4
97
98
UARTCLK
CLKEN
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
VDD
Power
I/O
PF0
SDCLK
SDCKE
PE7
I/O
VSS
Ground
I/O
PE6
nDCS1
nDCS0
nSDWE
PE5
I/O
PE4
I/O
nRAS
nCAS
PE3
Output
Output
I/O
DQM3
DQM2
DQM1
DQM0
PE2
I/O
PE1
I/O
PE0
I/O
VDDC
INT7
Power
I/O
LCDVD11
LCDVD10
LCDVD9
4
4
INT6
I/O
PD7
I/O
12
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
PIN NO.
NXP Semiconductors
LH79520
Table 3. LH79520 Numerical Pin List (Cont’d)
FUNCTION AT
OUTPUT
5
FUNCTION 2 FUNCTION 3 TYPE
NOTES
7
RESET
DRIVE
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
PD6
PD5
LCDVD8
LCDVD7
LCDVD6
I/O
I/O
I/O
8 mA
8 mA
8 mA
None
8 mA
8 mA
8 mA
8 mA
None
8 mA
8 mA
None
8 mA
8 mA
8 mA
8 mA
8 mA
2 mA
8 mA
None
8 mA
None
8 mA
8 mA
8 mA
8 mA
None
None
4 mA
2 mA
4 mA
4 mA
None
4 mA
None
2 mA
2 mA
None
2 mA
PD4
LCDPS
VSSC
PD3
Ground
I/O
LCDVD5
LCDVD4
LCDVD3
LCDVD2
PD2
I/O
PD1
I/O
PD0
I/O
VDD
Power
Output
Output
Ground
I/O
LCDVD1
LCDVD0
VSS
PC7
LCDFP
LCDVD17
LCDLP
LCDSPS
PC6
I/O
PC5
I/O
PC4
LCDVD16
LCDDCLK
LCDDCLKIN
LCDVDDEN
I/O
PC3
I/O
PC2
I/O
PC1
LCDCLS
LCDSPL
I/O
VDDC
PC0
Power
I/O
LCDENAB
VSSC
PB7
Ground
I/O
LCDVD15
LCDVD14
LCDVD13
LCDVD12
PB6
I/O
PB5
I/O
PB4
LCDREV
I/O
VDD
Power
Input
Output
I/O
INT5/DREQ1
CTOUT1B
PB3
nWAIT
DACK1
DREQ0
nDACK0
DEOT0
4, 6
4
PB2
I/O
PB1
I/O
VSS
Ground
I/O
INT4
INT3
PB0
PWM0
PWMSYNC0
INT2
4
4
4
4
Input
I/O
PA7
INT1
I/O
VDDC
PA6
Power
I/O
INT0
4
Preliminary data sheet
Rev. 01 — 16 July 2007
13
LH79520
PIN NO.
NXP Semiconductors
System-on-Chip
Table 3. LH79520 Numerical Pin List (Cont’d)
FUNCTION AT
OUTPUT
5
FUNCTION 2 FUNCTION 3 TYPE
NOTES
7
RESET
DRIVE
8 mA
4 mA
None
4 mA
2 mA
None
4 mA
None
4 mA
4 mA
4 mA
4 mA
None
None
None
4 mA
None
None
None
None
None
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
PA5
PWM1
VSSC
PA4
CLKOUT
DEOT1
I/O
Output
Ground
I/O
UARTTX1
UARTRX1
PA3
I/O
4
4
VDD
Power
Output
Input
I/O
UARTIRTX0
UARTIRRX0
PA2
UARTTX0
UARTRX0
SSPFRM
SSPCLK
SSPEN
PA1
I/O
PA0
I/O
SSPTX
VSS
UARTTX2
Output
Ground
Input
Input
Output
Input
Input
Input
Input
Input
SSPRX
TMS
UARTRX2
4
1, 4
TDO
TDI
1, 4
TCLK
nTRST
TEST1
TEST2
1, 4
2
2
NOTES:
1. Input with internal pull-up.
2. Input with internal pull-down.
3. Output is for crystal oscillator only, no drive capability.
4. Input with Schmitt Trigger.
5. I/O = Input/Output.
6. Software should avoid enabling the INT5 and DREQ1 functions simultaneously.
7. Output Drive Values shown are MAX. See ‘DC Specifications’.
8. Crystal Oscillator Inputs should be driven to a maximum of 1.8 V 10 %.
14
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
PIN LCD DATA
NXP Semiconductors
LH79520
Table 4. LCD Data Multiplexing
STN
ALL TFT:
PALETTE
DATA OR
16-BIT
MONO 4-BIT
MONO 8-BIT
COLOR
ALL TFT: ALL TFT:
NO.
SIGNAL
5:5:5+I
5:6:5
SINGLE
PANEL
DUAL
PANEL
SINGLE
PANEL
DUAL
PANEL
SINGLE DUAL
PANEL PANEL
DIRECT
BLUE3
BLUE2
BLUE1
BLUE0
130 LCDVD17
132 LCDVD16
139 LCDVD15
140 LCDVD14
141 LCDVD13
142 LCDVD12
114 LCDVD11
115 LCDVD10
BLUE4
BLUE3
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
MLSTN7
MLSTN6
MLSTN5
MLSTN4
MLSTN3
MLSTN2
MLSTN1
MLSTN0
CLSTN7 BLUE2
CLSTN6 BLUE1
CLSTN5 BLUE0 GREEN5
CLSTN4
MLSTN3
MLSTN2
MLSTN1
MLSTN0
CLSTN3 GREEN4 GREEN4
CLSTN2 GREEN3 GREEN3
CLSTN1 GREEN2 GREEN2
CLSTN0 GREEN1 GREEN1
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
116
117
118
119
121
122
123
124
126
127
LCDVD9
LCDVD8
LCDVD7
LCDVD6
LCDVD5
LCDVD4
MUSTN7 MUSTN7 CUSTN7 CUSTN7 GREEN0 GREEN0
MUSTN6 MUSTN6 CUSTN6 CUSTN6
MUSTN5 MUSTN5 CUSTN5 CUSTN5
MUSTN4 MUSTN4 CUSTN4 CUSTN4
RED4
RED3
RED2
RED1
RED0
RED4
RED3
RED2
RED1
RED0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 15
LCDVD3 MUSTN3 MUSTN3 MUSTN3 MUSTN3 CUSTN3 CUSTN3
LCDVD2 MUSTN2 MUSTN2 MUSTN2 MUSTN2 CUSTN2 CUSTN2
LCDVD1 MUSTN1 MUSTN1 MUSTN1 MUSTN1 CUSTN1 CUSTN1
LCDVD0 MUSTN0 MUSTN0 MUSTN0 MUSTN0 CUSTN0 CUSTN0 Intensity6 BLUE4
NOTES:
1. The Intensity bit is identically generated for all three colors.
2. MUSTN = Monochrome Upper data bit for STN panel.
3. MLSTN = Monochrome Lower data bit for STN panel.
4. CUSTN = Color Upper data bit for STN panel.
5. CLSTN = Color Lower data bit for STN panel.
6. Connect to the LSB of the Red, Green, and Blue inputs of a 6:6:6 panel.
7. Recommended hookups for TFT 5:5:5 + Intensity and 5:6:5 are shown.
This wiring requires the BGR bit in the LCD Control Register to be 0.
Table 5. LCD Control and Timing Signals
STN AND
TFT
AD-TFT,
PIN
DESCRIPTION
Power Save (AD-TFT, HR-TFT only)
HR-TFT
LCDPS
119
129
131
133
LCDFP
LCDLP
LCDSPS
LCDLP
Frame Pulse (STN), Vertical Synchronization Pulse (TFT) /Row Display Reset
Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT)
Panel Data Clock
LCDDCLK
LCDDCLK
134 LCDDCLKIN
LCDDCLKIN External Clock Input
135
137
142
LCDVDDEN
LCDENAB
LCDCLS
LCDSPL
LCDREV
Digital Supply Enable/Gate Driver Clock
Data Enable/ Line Start Pulse (Left)
Reverse Signal (AD-TFT, HR-TFT only)
Preliminary data sheet
Rev. 01 — 16 July 2007
15
LH79520
NXP Semiconductors
System-on-Chip
TOUCH
SCREEN
CONTR.
CODEC
IMAGER
STN/
TFT/AD-TFT
SSP
PWM
UART
PIO
DMA
FLASH/
SRAM/
SDRAM
LH79520
UART
IR
MEMORY
CARD
INTERFACE
FLASH
CARD
79520-6A
Figure 3. LH79520 Application Diagram Example
strained by hardware to specific addresses, to be reor-
ganized at addresses identified by the user. These user
identified locations are called Virtual Addresses (VA).
When the MMU is enabled, Code and Data must be
built, loaded, and executed using Virtual Addresses
which the MMU translates to Physical Addresses. In
addition, the user may implement a memory protection
scheme by using the features of the MMU. Address
translation and memory protection services provided
by the MMU are controlled by the user. The MMU is
directly controlled through the System Control Copro-
cessor, Coprocessor 15 (CP15). The MMU is indirectly
controlled by a Translation Table (TT) and Page Tables
(PT) prepared by the user and established using a por-
tion of physical memory dedicated by the user to stor-
ing the TT and PT’s.
SYSTEM DESCRIPTIONS
ARM720T Processor
The LH79520 microcontroller features the ARM720T
cached core with an Advanced High-Performance Bus
(AHB) interface. The ARM720T features:
• 32-bit ARM7TDMI™ RISC Core
• 8 kB Cache
• MMU (Windows CE enabled)
The processor is a member of the ARM7T family of
processors. For more information, see the ARM docu-
ment, ‘ARM720T (Rev 3) Technical Reference Manual’,
available on NXP’s’s website at www.nxp.com.
The LH79520 MMU provides a means to map Phys-
ical Memory (PA) addresses to virtual memory
addresses. This allows physical memory, which is con-
16
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Memory Architecture
0xFFFFFFFF
0xFFFF0000
0xFFFC0000
An integrated SDRAM Controller and Static Memory
Controller provide a glueless interface to external
SDRAM, Flash, SRAM, ROM, and burst ROM. Three
remap options for the physical memory are selectable
by software, as shown in Figures 4, 5, and 6. Memory
is exclusively Little Endian.
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
ADVANCED PERIPHERAL BUS
PERIPHERALS
RESERVED
SDRAM CONTROLLER
0x80000000
0x60000000
0x40000000
INTERNAL STATIC MEMORY
EXTERNAL STATIC MEMORY
SDRAM
The SDRAM Controller provides the interface
between the internal bus and external (off-chip)
SDRAM memory devices (Figure 2).
The SDRAM Controller provides the following features:
• Two independently controlled chip selects.
0x20000000
0x00000000
EXTERNAL STATIC MEMORY
• Transfers data between the controller and SDRAM
in quad-word bursts.
79520-5
Figure 4. Memory Remap ‘00’ and ‘11’
• Supports both 32-bit and 16-bit SDRAM.
• Supports 2K, 4K, and 8K row address memory parts,
i.e. typical 256M, 128M, 64M, and 16M parts, with 8,
16, or 32 DQ bits per device.
0xFFFFFFFF
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
0xFFFF0000
• Two reset domains allow SDRAM contents to be
preserved over a soft reset.
ADVANCED PERIPHERAL BUS
PERIPHERALS
0xFFFC0000
STATIC MEMORY CONTROLLER (SMC)
RESERVED
The SMC provides the interface between the internal
bus and external (off-chip) memory devices.
0x80000000
INTERNAL STATIC MEMORY
0x60000000
The LH79520 boots from 16-bit memory. The SMC
address space is divided into eight memory banks of
64 MB each. The SMC supports:
EXTERNAL STATIC MEMORY
0x40000000
SDRAM
• Static Memory-mapped Devices including RAM,
ROM, Flash, and Burst ROM
0x20000000
INTERNAL STATIC MEMORY
0x00000000
• Asynchronous Operations:
79520-4
– Page Mode Reads for non-clocked memory
– Burst Mode Reads for burst mode ROM
Figure 5. Memory Remap ‘10’
• 8-, 16-, and 32-bit wide external memory data paths
0xFFFFFFFF
• Independent configuration for up to eight memory
banks, each up to 64 MB
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
0xFFFF0000
0xFFFC0000
ADVANCED PERIPHERAL BUS
PERIPHERALS
• Programmable Parameters:
– WAIT States (up to 32)
– Bus Turnaround Cycles (1 to 16)
– Initial and Subsequent Burst Read WAIT State for
Burst ROM Devices.
RESERVED
0x80000000
0x60000000
0x40000000
The Static Memory Controller (SMC) also supports
an nWAIT input that can be used by an external device
to vary the wait time.
INTERNAL STATIC MEMORY
EXTERNAL STATIC MEMORY
SDRAM
DMA Controller
0x20000000
0x00000000
The DMA Controller provides support for DMA-
capable peripherals. The LCD controller uses its own
DMA port, connecting directly to memory for retrieving
display data.
SDRAM
79520-3
Figure 6. Memory Remap ‘01’
Preliminary data sheet
Rev. 01 — 16 July 2007
17
LH79520
NXP Semiconductors
System-on-Chip
• Simultaneous servicing of up to 4 data streams
Advanced LCD Interface peripheral also provides a
bypass mode that allows the LH79520 to interface to the
built-in timing ASIC in standard TFT and STN panels.
• Three transfer modes are supported:
– Memory to Memory
– Peripheral to Memory
– Memory to Peripheral
Synchronous Serial Port (SSP)
The SSP is a master-only interface for synchronous
serial communication with slave peripheral devices that
support protocols for Motorola SPI, National Semicon-
ductor MICROWIRE, or Texas Instruments Synchro-
nous Serial Interface.
• Identical source and destination capabilities
• Transfer Size Programmable (Byte, Half-word, Word)
• Burst Size Programmable
• Address Increment or Address Freeze
• Master-only operation
• Transfer Error indication for each stream via an
interrupt
• Programmable clock rate
• 16-word FIFO array with pack and unpack logic
• Separate transmit FIFO and receive FIFO buffers,
16 bits wide, 8 locations deep
Handles all combinations of byte, half-word or word
transfers from input to output.
• DMA for transmit and receive
• Programmable interface protocols: Motorola SPI,
National Semiconductor MICROWIRE, or Texas
Instruments Synchronous Serial Port
Color LCD Controller (CLCDC)
The CLCDC provides all the necessary control and
drive signals to interface directly with a variety of color
and monochrome LCD panels.
• Programmable data frame size from 4 to 16 bits
• Independent masking of transmit FIFO, receive
FIFO and receive overrun interrupts
• Supports single and dual scan color and mono-
chrome Super Twisted Nematic (STN) displays with
4- or 8-bit interfaces
• Available internal loopback test mode.
• Supports Thin Film Transistor (TFT) color displays
• Programmable resolution up to 800 × 600
Universal Asynchronous
Receiver Transmitter (UART)
– 800 × 600 (16-bit color can only be supported at
The LH79520 incorporates three UARTs.
≤ 65 Hz refresh rates with 800 × 600 resolution).
• Programmable use of UART0 or IrDA SIR input/output
• 15 gray-level mono, 3,375 color STN, and 64 k color
TFT support
• Separate 16-byte transmit and receive FIFOs to
reduce CPU interrupts
• 1, 2, or 4 bits-per-pixel (BPP) for monochrome STN
• Programmable FIFO disabling for 1-byte depth
• Programmable baud rate generator
• 1-, 2-, 4-, or 8-BPP palettized color displays for color
STN and TFT
• Independent masking of transmit FIFO, receive
FIFO, receive timeout and modem status interrupts
• True-color non-palettized, for color STN and TFT
• Programmable timing for different display panels
• 256-entry, 16-bit palette fast-access RAM
• Frame, line and pixel clock signals
• False start bit detection
• Line Break generation and detection
• Fully-programmable serial interface characteristics:
– 5-, 6-, 7-, or 8-bit data word length
• AC bias signal for STN or data enable signal for
TFT panels
– Even-, odd- or no-parity bit generation and detection
– 1 or 2 stop bit generation
• Patented grayscale algorithm
• Interrupt Generation Events
• IrDA SIR Encode/Decode block, providing:
– Programmable use of IrDA SIR or UART0
input/output
• Dual 16-deep programmable 32-bit wide FIFOs for
buffering incoming data.
– Supports data rates up to 115.2 Kbps half-duplex
– Programmable internal clock generator, allowing
division of the Reference clock in increments of 1
to 512 for low-power mode bit durations.
ADVANCED LCD INTERFACE
The Advanced LCD Interface peripheral allows for
direct connection to ultra-thin panels that do not include
a timing ASIC. It converts TFT signals from the Color
LCD controller to provide the proper signals, timing and
levels for direct connection to a panel’s Row and Col-
umn drivers for AD-TFT, HR-TFT, or any technology of
panel that allows for a connection of this type. The
18
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
VARIATIONS FROM THE 16C550 UART
– FIQ interrupt request
– Non-vectored IRQ interrupt request (software to
poll IRQ source)
The UART varies from the industry-standard
16C550 UART device in six ways:
– Vectored IRQ interrupt request (up to 16 chan-
nels total)
• Receive FIFO trigger levels are fixed at 8 bytes
• Receive errors are stored in the FIFO, and do not
generate an interrupt.
• The Watchdog timer can only generate FIQ interrupt
requests
• The internal register map address space and each
register’s bit function differ.
• External interrupt inputs programmable
– Edge triggered or level triggered
– Rising edge/active HIGH or falling edge/active
LOW
The following 16C550 UART features are not sup-
ported:
• 1.5 stop bits (1 or 2 stop bits only are supported)
• The forcing stick parity function
The 28 interrupt channels are shown in Table 6.
• Independent receive clock.
Table 6. Interrupt Channels
CHANNEL
INTERRUPT SOURCE
External Interrupt 0
Pulse Width Modulator (PWM)
• Two independent output channels with separate
input clocks
0
1
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
Spare Internal Interrupt 0
COMRX (used for debug)
COMTX (used for debug)
SSP RX time-out interrupt SSPRXTO
CLCD Combined Interrupt
SSP SSPTXINTR
SSP SSPRXINTR
SSP SSPRORINTR
SSP SSPINTR
2
• Up to 16-bit resolution
3
• Programmable synchronous mode support
– Allows external input to start PWM
4
5
• Programmable pulse width (duty cycle), interval (fre-
quency), and polarity
6
7
– Static programming: PWM is stopped
– Dynamic programming: PWM is running
– Updates duty cycle, frequency, and polarity at the
end of a PWM cycle
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27-29
30
31
– Wide programming range.
Vectored Interrupt Controller
The Vectored Interrupt Controller combines the
interrupt request signals from 20 internal and eight
external interrupt sources and applies them, after
masking and prioritization, to the IRQ and FIQ interrupt
inputs of the ARM7TDMI processor core.
Counter/Timer0
Counter/Timer1
The Interrupt Controller incorporates a hardware
interrupt vector logic with programmable priority for up
to 16 interrupt sources. This logic reduces the interrupt
response time for IRQ type interrupts compared to
solutions using software polling to determine the high-
est priority interrupt source. This significantly improves
the real-time capabilities of the LH79520 in embedded
control applications.
Counter/Timer2
Counter/Timer3
UART ch0 Rx
UART ch0 Tx
UART ch0
UART ch1
UART ch2
• 20 internal and eight external interrupt sources
– Individually maskable
DMA Combined
Unused
– Status accessible for software polling
RTC_ALARM
• IRQ interrupt vector logic for up to 16 channels with
programmable priorities
WDT
• All of the interrupt channels, with the exception of the
Watchdog Timer interrupt, can be programmed to
generate:
Preliminary data sheet
Rev. 01 — 16 July 2007
19
LH79520
NXP Semiconductors
System-on-Chip
• Programmable clock prescalers for UARTs and
PWMs
Reset, Clock, and Power
Controller (RCPC)
The RCPC generates the various clock signals for the
operation of the LH79520 and provides for an orderly
start-up after power-on and during a wake-up from one
of the power saving operating modes. The RCPC allows
the software to individually select the frequency of the
various on-chip clock signals as required to operate the
chip in the most power-efficient mode. It features:
• Five global power control modes are available:
– Active
– Standby
– Sleep
– Stop1
– Stop2
• CPU and Bus clock frequency can be changed
on the fly
• 14.7456 MHz crystal oscillator and PLL for on-chip
Clock generation
• Selectable clock output
• External Clock input if on-chip oscillator and PLL are
not used
• Hardware reset (nRESETIN) and software reset.
The 32.768 kHz crystal oscillator is not required for
chip operation, so it may be left out of the design to
save power. If this crystal is not used, XTALIN should
be pulled to VDD or VSS so the input does not float.
• 32.768 kHz crystal oscillator generating 1 Hz clock
for Real Time Clock
• Individually controlled clocks for peripherals and CPU
• Clock source for UARTs is selectable between
14.7456 MHz crystal oscillator and external clock
source
Table 7. Clock and Enable States for Different Power Modes
(Using On-chip Oscillator and PLL)
FUNCTION
ACTIVE STANDBY SLEEP STOP1 STOP2
14.7456 MHz Oscillator
PLL
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Peripheral Clock
CPU Clock
ON
OFF
OFF
OFF
20
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Real Time Clock
Timer
The RTC can provide a basic alarm function or long
time base counter. This is achieved by generating an
interrupt signal after counting for a programmed num-
ber of cycles of RTC input. Counting in one-second
intervals is achieved by the use of a 1 Hz clock input to
the RTC.
The LH79520 incorporates two Timer modules,
each comprising two 16-bit independently programma-
ble timers. This gives a total of four independent timers.
• Each timer has two operating modes:
– Free-running mode: After reaching 0x0000 the
timer wraps around to 0xFFFF and generates an
interrupt request. It continues to count down from
0xFFFF.
The features of the RTC are:
• 32-bit up counter with programmable load
• Programmable 32-bit match compare register
– Periodic timer mode: After reaching 0x0000 the
timer is automatically reloaded with its pro-
grammed value and generates an interrupt re-
quest. It continues to count down from the
loaded value.
• Software maskable interrupt when counter and com-
pare registers are identical.
RTC input clock sources:
• PLL clock
• Each timer contains a programmable pre-scaler:
– Bus clock divided by 1, 16, or 256
• 32.768 kHz clock
• 1 Hz clock (default).
• Timers can be cascaded to achieve longer timing
periods
• Carry-out of higher-order timer provides clock signal
for next lower order timer
Watchdog Timer
The Watchdog Timer provides hardware protection
against malfunctions. It is a programmable timer to be
reset by software at regular intervals. Failure to reset
the timer will cause a FIQ interrupt. Failure to service
the FIQ interrupt will then generate a System Reset.
The features of the Watchdog Timer are:
• Possible timing ranges:
15
– 2 (single timer)
31
– 2 (two timers cascaded)
47
– 2 (three timers cascaded)
63
– 2 (four timers cascaded)
• Driven by the bus clock
• Output signal of lowest order timer is externally avail-
able as CTOUT1B signal.
16
31
• 16 programmable time-out periods: 2 through 2
clock cycles
Input/Output Configuration System
• Generates a system reset (resets LH79520) or a FIQ
Interrupt whenever a time-out period is reached
The registers provided by the IOCON System allow
the user to directly control the pin multiplexing of the
device; by setting or clearing bits in a set of registers, the
user can configure the LH79520 for peripheral devices.
• Software enable, lockout, and counter-reset mecha-
nisms add security against inadvertent writes
• Protection mechanism guards against interrupt-ser-
vice failure:
General Purpose Input/Output (GPIO)
The LH79520 provides up to 64 bits of programma-
ble input/output. These eight 8-bit ports are Ports A
through H, and are multiplexed with other signals.
– The first WDT time-out triggers FIQ and asserts
nWDFIQ status flag
– If FIQ service routine fails to clear nWDFIQ, then
the next WDT time-out triggers a soft reset.
• Individually programmable input/output pins
• All I/O ports default to Input on power-up.
Preliminary data sheet
Rev. 01 — 16 July 2007
21
LH79520
NXP Semiconductors
System-on-Chip
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
DC Core Supply Voltage
DC I/O Supply Voltage
DC Analog Supply Voltage
Storage Temperature
VDDC
VDD
-0.3 to 2.4
-0.3 to 4.6
-0.3 to 2.4
-55 to +125
V
V
V
VDDA
TSTG
°C
NOTE: These stress ratings are only for transient conditions. Oper-
ation at or beyond absolute maximum rating conditions may
affect reliability and cause permanent damage to the device.
Recommended Operating Conditions
PARAMETER
MINIMUM TYPICAL
MAXIMUM
1
1.62 V
3.0 V
1.8 V
3.3 V
1.8 V
1.98 V
3.6 V
DC Core Supply Voltage (VDDC)
1
DC I/O Supply Voltage (VDD)
DC Analog Supply Voltage (VDDA)
1.62 V
10 MHz
0°C
1.98 V
2
Clock Frequency
77.4144 MHz
+70°C
Commercial Operating Temperature
Industrial Operating Temperature
25°C
25°C
-40°C
+85°C
NOTES:
1. Core Voltage should never exceed I/O Voltage after initial power
up. See the section titled ‘Power Supply Sequencing’.
2. Using 14.7456 MHz Input Crystal and On-Chip PLL. Functional to
DC when using external clock.
22
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
DC/AC SPECIFICATIONS (COMMERCIAL)
Unless otherwise noted, all data provided under
commercial DC specifications are based on 0°C to
+70°C, VDDC = 1.62 V to 1.98 V, VDD = 3.0 V to 3.6 V,
VDDA = 1.62 V to 1.98 V.
DC Specifications (Commercial)
SYMBOL
PARAMETER
CMOS input HIGH voltage
MIN. TYP. MAX. UNIT
CONDITIONS
NOTES
VIH
2.0
5.5
0.8
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VIL
CMOS input LOW voltage
VIT+
VIT-
Positive Input threshold voltage (Schmitt trigger pins)
Negative Input threshold voltage (Schmitt trigger pins)
Schmitt trigger hysteresis
1.60
1.20
0.40
1
1
VHYST
VIT+ – VIT-
CMOS output HIGH voltage
Output drive (2 mA type)
2.6
2.6
2.6
2.6
IOH = -50 µA
IOH = -2 mA
IOH = -4 mA
IOH = -8 mA
IOL = 50 µA
IOL = 2 mA
IOL = 4 mA
IOL = 8 mA
VOH
VOL
Output drive (4 mA type)
Output drive (8 mA type)
CMOS output LOW voltage
Output drive (2 mA type)
0.4
0.4
0.4
0.4
1
Output drive (4 mA type)
Output drive (8 mA type)
XTAL32IN External Clock Input
1.62 1.8 1.98
1.62 1.8 1.98
2
2
XTALIN
IIN
External Clock Input
Input leakage current
Output tri-state leakage current
Active current
-10
-10
10
10
55
35
5.5
µA VIN = VDD or GND
IOZ
µA VOUT = VDD or GND
IACTIVE
43.5
27.5
3.9
500
34
mA
mA
mA
µA
3
ISTANDBY Standby current
3, 4
ISLEEP
ISTOP1
ISTOP2
ISTOP2
CIN
Sleep current
Stop1 current
Stop2 current (RTC ON)
Stop2 current (RTC OFF)
Input Capacitance
µA
18
µA
4
4
pF
COUT
Output Capacitance
Pull-up or Pull-down Resistance
pF
RPULL
33
K Ω
NOTES:
1. Table 2 details each pin’s buffer type.
2. P-P Sinusoidal; 0.0 V DC offset.
3. Running Typical Application over operating range.
4. Current measured with CPU stopped and all peripherals enabled.
AC Test Conditions
PARAMETER
Supply Voltage (VDD)
RATING
3.0 to 3.6
1.62 to 1.98
VSS to VDD
2
UNIT
V
Core Voltage (VDDC)
V
Input Pulse Levels
V
Input Rise and Fall Times
Input and Output Timing Ref. Levels
ns
V
VDD/2
Preliminary data sheet
Rev. 01 — 16 July 2007
23
LH79520
NXP Semiconductors
System-on-Chip
For outputs from the LH79520, tOVXXX (e.g. tOVA)
represents the amount of time for the output to become
valid from the rising edge of the reference clock signal.
Maximum requirements for tOVXXX are shown in
Table 8.
AC Specifications
All signals described in Table 8 relate to transitions
after a reference clock signal. The illustration in Figure
7 represents all cases of these sets of measurement
parameters; except for the Asynchronous Memory
Interface — which are referenced to Address Valid.
The signal tOHXXX (e.g. tOHA) represents the
amount of time the output will be held valid from the ris-
ing edge of the reference clock signal. Minimum
requirements for tOHXXX are listed in Table 8.
The reference clock signals in this design are:
• HCLK, the System Bus clock
• PCLK, the Peripheral Bus clock (locked to HCLK in
the LH79520)
For Inputs, tISXXX (e.g. tISD) represents the
amount of time the input signal must be valid before the
rising edge of the clock signal. Minimum requirements
for tISXXX are shown in Table 8.
• SSPCLK, the Synchronous Serial Interface clock
• UARTCLK, the UART Interface clock
The signal tIHXXX (e.g. tIHD) represents the
amount of time the memory output must be held valid
from the rising edge of the reference clock signal. Min-
imum requirements are shown in Table 8.
• LCDDCLK, the LCD Data clock from the
LCD Controller
• and SDCLK, the SDRAM clock.
All signal transitions are measured from the 50 %
point of the clock to the 50 % point of the signal. See
Figure 7.
REFERENCE
CLOCK
tOHXXX
tOVXXX
OUTPUT
SIGNAL (O)
tISXXX tIHXXX
INPUT
SIGNAL (I)
79520-34
Figure 7. LH79520 Signal Timing
24
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Table 8. AC Signal Characteristics (Commercial)
SIGNAL
TYPE LOAD DRIVE SYMBOL
MIN.
MAX.
DESCRIPTION
ASYNCHRONOUS MEMORY INTERFACE SIGNALS
Data Output Valid, following
Address Valid
tOVD
tOHD
tHCLK + 6 ns
Output 50 pF 8 mA
Data Output Invalid, following
Address Valid
3 × tHCLK - 6 ns
D[31:0]
Data Input Valid, following
Address Valid
2 × tHCLK – 18 ns
Input
tIDD
2 × tHCLK – 18 ns
+ (nWAIT –1)
× tHCLK
Data Input Valid, following
Address Valid (nWAIT states)
Chip Select Output Valid,
following Address Valid
tOVCS
tOHCS
tOVBE
tHCLK + 6 ns
nCS6 - nCS0 Output 30 pF 8 mA
Chip Select Output Invalid,
following Address Valid
3 × tHCLK - 6 ns
Byte Lane Enable Valid,
following Address Valid
tHCLK + 10 ns
Byte Lane Enable Invalid, follow-
ing Address Valid; Write Cycle
nBLE[3:0]
Output 30 pF 8 mA
Output 30 pF 8 mA
tOHBEW
tOHBER
tOVWE
tOHWE
tOVOE
tOHOE
tISWAIT
2 × tHCLK - 6 ns
3 × tHCLK - 6 ns
Byte Lane Enable Invalid, follow-
ing Address Valid; Read Cycle
Write Enable Valid, following
Address Valid
tHCLK + 10 ns
nWE
nOE
Write Enable Invalid, following
Address Valid
2 × tHCLK - 6 ns 2 × tHCLK - 6 ns
tHCLK + 10 ns
Ouput Enable Valid, following
Address Valid
Output 30 pF 8 mA
Input
Ouput Enable Invalid, following
Address Valid
3 × tHCLK - 6 ns
WAIT Input Valid, following
Address Valid
nWAIT
A[25:0]
2 × tHCLK – 18 ns
SYNCHRONOUS MEMORY INTERFACE SIGNALS
Ouput 50 pF 8 mA
tOVA
tOVD
10.5 ns
11 ns
Address Valid
Output Data Valid
Output Data Hold
Input Data Setup
Output 50 pF 8 mA
tOHD
1.2 ns
5 ns
D[31:0]
tISD
Input
tIDD
1.5 ns
Input Data Hold
tOVCA
tOHCA
tOVRA
tOHRA
tOVSDW
tOHSDW
tOVC0
tOHC0
tOVDQ
tOHDQ
tOVSC
tOHSC
tSDCLK
10.5 ns
10.5 ns
10.5 ns
10.5 ns
10.5 ns
10.5 ns
CAS Valid
nCAS
Output 50 pF 8 mA
Output 50 pF 8 mA
Output 30 pF 8 mA
Output 30 pF 8 mA
Output 30 pF 8 mA
2 ns
2 ns
2 ns
2 ns
2 ns
CAS Hold
RAS Valid
nRAS
RAS Hold
SDWE Write Enable Valid
SDWE Write Enable Hold
SDCKE Clock Enable Valid
SDCKE Clock Enable Hold
DQM Data Mask Valid
DQM Data Mask Hold
SDCS Data Mask Valid
SDCS Data Mask Hold
SDRAM Clock Period
nSDWE
SDCKE
DQM[3:0]
nSDCS[1:0] Output 30 pF 8 mA
SDCLK Output 30 pF 8 mA
2 ns
19.37 ns
Preliminary data sheet
Rev. 01 — 16 July 2007
25
LH79520
SIGNAL
NXP Semiconductors
System-on-Chip
Table 8. AC Signal Characteristics (Commercial) (Cont’d)
TYPE LOAD DRIVE SYMBOL
MIN.
MAX.
DESCRIPTION
SYNCHRONOUS SERIAL PORT (SSP)
tOVSSPFRM Output Valid,
Referenced to SSPCLK
SSPFRM
SSPEN
Output 50 pF 2 mA tOVSSPFRM
14 ns
tOVSSPEN Output Valid,
Referenced to SSPCLK
Output 50 pF 2 mA tOVSSPENB
Output 50 pF 2 mA tOVSSPOUT
14ns
14ns
SSPTX
SSPRX
SSP Transmit Valid
SSP Receive Setup
Input
tISSSPIN
17 ns
INTERRUPTS
INTR[5:0]
Input
Note 1
NOTES:
1. INTR[5:0] are asynchronous signals. Interrupts must be held Active until serviced in Level Sensitive Mode,
and held Active for a minimum of 20 ns in Edge Sensitive Mode.
2. nDACK0, DACK1 and DREQ[1:0] are asynchronous signals. They must be held Active until serviced,
for a minimum of 20 ns.
26
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
DC/AC SPECIFICATIONS (INDUSTRIAL)
Unless otherwise noted, all data provided under
industrial DC specifications are based on -40°C to
+85°C, VDDC = 1.62 V to 1.98 V, VDD = 3.0 V to 3.6 V,
VDDA = 1.62 V to 1.98 V.
DC Specifications (Industrial)
SYMBOL
VIH
PARAMETER
CMOS input HIGH voltage
MIN. TYP. MAX. UNIT
CONDITIONS
NOTES
2.0
5.5
0.8
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VIL
CMOS input LOW voltage
VIT+
Positive Input thrueshold voltage (Schmitt trigger pins)
Negative Input threshold voltage (Schmitt trigger pins)
Schmitt trigger hysteresis
1.60
1.20
0.40
VIT-
1
1
VHST
VIT+ – VIT-
CMOS output HIGH voltage
Output drive (2 mA type)
2.6
2.6
2.6
2.6
IOH = -50 µA
IOH = -2 mA
IOH = -4 mA
IOH = -8 mA
IOL = 50 µA
IOL = 2 mA
IOL = 4 mA
IOL = 8 mA
VOH
VOL
Output drive (4 mA type)
Output drive (8 mA type)
CMOS output LOW voltage
Output drive (2 mA type)
0.4
0.4
0.4
0.4
1
Output drive (4 mA type)
Output drive (8 mA type)
XTAL32IN External Clock Input
1.62 1.8 1.98
1.62 1.8 1.98
2
2
XTALIN
IIN
External Clock Input
Input leakage current
Output tri-state leakage current
Active current
-10
-10
10
10
µA VIN = VDD or GND
IOZ
µA VOUT = VDD or GND
IACTIVE
43.5
27.5
3.9
mA
mA
mA
µA
3
ISTANDBY Standby current
3, 4
ISLEEP
ISTOP1
ISTOP2
ISTOP2
CIN
Sleep current
Stop1 current
500
34
Stop2 current (RTC ON)
Stop2 current (RTC OFF)
Input Capacitance
µA
18
µA
4
4
pF
COUT
Output Capacitance
Pull-up or Pull-down Resistance
pF
RPULL
33
K Ω
NOTES:
1. Table 2 details each pin’s buffer type.
2. P-P Sinusoidal; 0.0 V DC offset.
3. Running Typical Application over operating range.
4. Current measured with CPU stopped and all peripherals enabled.
AC Test Conditions
PARAMETER
Supply Voltage (VDD)
RATING
3.0 to 3.6
1.62 to 1.98
VSS to VDD
2
UNIT
V
Core Voltage (VDDC)
V
Input Pulse Levels
V
Input Rise and Fall Times
Input and Output Timing Ref. Levels
ns
V
VDD/2
Preliminary data sheet
Rev. 01 — 16 July 2007
27
LH79520
NXP Semiconductors
System-on-Chip
CURRENT CONSUMPTION BY OPERATING MODE
Table 9. Current Consumption by Mode
Current consumption can depend on a number of
parameters. To make this data more usable, the values
presented in Table 9 were derived under the conditions
presented here.
SYMBOL
PARAMETER
TYP. UNITS
ACTIVE MODE*
ICORE Core Current
IIO I/O Current
STANDBY MODE
ICORE Core Current
IIO Current drawn by I/O
SLEEP MODE
ICORE Core Current
33.6
9.6
mA
mA
Maximum Specified Value
The values specified in the MAXIMUM column were
determined using these operating characteristics:
29.6
0.8
mA
mA
• All IP blocks either operating or enabled at maximum
frequency and size configuration
3.8
2
mA
µA
• Core operating at maximum power configuration
• All I/O loads at maximum (50 pF)
IIO
Current drawn by I/O
STOP1 MODE
• All voltages at maximum specified values
• Maximum specified ambient temperature.
ILEAK
ILEAK
ILEAK
Leakage Current, Core and I/O 2.96
STOP2 MODE (RTC ON)
mA
µA
µA
Leakage Current, Core and I/O 35
STOP2 MODE (RTC OFF)
Typical
The values in the TYPICAL column were determined
using a ‘typical’ application under ‘typical’ environmental
conditions and the following operating characteristics:
Leakage Current, Core and I/O 18
NOTE: *ICORE = 58 mA MAX., IIO = 19 mA MAX., all active
• SPI, UART, PWMs, and Timer peripherals operat-
ing; all other peripherals disabled
Table 10. Peripheral Current Consumption
• LCD enabled with 320 × 240 × 16-bit color, 60 Hz
refresh rate
PERIPHERAL
TYPICAL
UNITS
• I/O loads at nominal
UARTs
RTC
200
5
µA
µA
mA
µA
µA
mA
• Cache enabled
• FCLK = 77.4 MHz; HCLK = 51.6 MHz
• All voltages at typical values
• Nominal case temperature.
DMA
4.1
500
207
2.2
SSP
Counter/Timers
LCD
PERIPHERAL CURRENT CONSUMPTION
In addition to the modal current consumption, Table
10 shows the typical current consumption for each of
the on-board peripheral blocks. The values were deter-
mined with the peripheral clock running at maximum
frequency, typical conditions, and no I/O loads.
28
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
AC Specifications (Industrial)
Table 11. AC Signal Characteristics (Industrial)
TYPE LOAD DRIVE SYMBOL MIN. MAX.
ASYNCHRONOUS MEMORY INTERFACE SIGNALS
SIGNAL
DESCRIPTION
Data Output Valid, following
Address Valid
tOVD
tOHD
tHCLK + 6.5 ns
Output 50 pF 8 mA
Data Output Invalid, following
Address Valid
3 × tHCLK – 6 ns
D[31:0]
Data Input Valid, following
Address Valid (1 WAIT state)
2 × tHCLK – 18 ns
Input
tIDD
2 × tHCLK – 18 ns
+ (nWAIT –1)
× tHCLK
Data Input Valid, following
Address Valid (nWAIT states)
Chip Select Output Valid,
following Address Valid
tOVCS
tOHCS
tOVBE
tHCLK + 6 ns
nCS6 - nCS0 Output 30 pF 8 mA
Chip Select Output Invalid,
following Address Valid
3 × tHCLK – 6 ns
Byte Lane Enable Valid,
following Address Valid
tHCLK + 10 ns
Byte Lane Enable Invalid, follow-
ing Address Valid; Write Cycle
nBLE[3:0]
Output 30 pF 8 mA
Output 30 pF 8 mA
tOHBEW
tOHBER
tOVWE
tOHWE
tOVOE
tOHOE
tISWAIT
2 × tHCLK – 6 ns
3 × tHCLK – 6 ns
Byte Lane Enable Invalid, follow-
ing Address Valid; Read Cycle
Write Enable Valid, following
Address Valid
tHCLK + 10 ns
nWE
nOE
Write Enable Invalid, following
Address Valid
2 × tHCLK – 6 ns 2 × tHCLK - 6 ns
tHCLK + 10 ns
Ouput Enable Valid, following
Address Valid
Output 30 pF 8 mA
Input
Ouput Enable Invalid, following
Address Valid
3 × tHCLK – 6 ns
WAIT Input Valid, following
Address Valid
nWAIT
A[25:0]
2 × tHCLK – 18 ns
SYNCHRONOUS MEMORY INTERFACE SIGNALS
Ouput 50 pF 8 mA
tOVA
tOVD
10.5 ns
11.5 ns
Address Valid
Output Data Valid
Output Data Hold
Input Data Setup
Input Data Hold
Output 50 pF 8 mA
tOHD
1.2 ns
5 ns
D[31:0]
tISD
Input
tIDD
1.5 ns
tOVCA
tOHCA
tOVRA
tOHRA
tOVSDW
tOHSDW
tOVC0
tOHC0
tOVDQ
tOHDQ
11 ns
11 ns
11 ns
11 ns
11 ns
CAS Valid
nCAS
Output 50 pF 8 mA
Output 50 pF 8 mA
Output 30 pF 8 mA
Output 30 pF 8 mA
Output 30 pF 8 mA
2 ns
2 ns
2 ns
2 ns
2 ns
CAS Hold
RAS Valid
nRAS
RAS Hold
SDWE Write Enable Valid
SDWE Write Enable Hold
SDCKE Clock Enable Valid
SDCKE Clock Enable Hold
DQM Data Mask Valid
DQM Data Mask Hold
nSDWE
SDCKE
DQM[3:0]
Preliminary data sheet
Rev. 01 — 16 July 2007
29
LH79520
SIGNAL
NXP Semiconductors
System-on-Chip
Table 11. AC Signal Characteristics (Cont’d)(Industrial)
TYPE LOAD DRIVE
SYMBOL
tOVSC
MIN.
MAX.
DESCRIPTION
11 ns
SDCS Data Mask Valid
SDCS Data Mask Hold
SDRAM Clock Period
nSDCS[1:0] Output 30 pF 8 mA
tOHSC
2 ns
SDCLK
Output 30 pF 8 mA
tSDCLK
19.37 ns
SYNCHRONOUS SERIAL PORT (SSP)
SSPFRM Output Valid,
Referenced to SSPCLK
SSPFRM
SSPEN
Output 50 pF 2 mA tOVSSPFRM
14 ns
SSPEN Output Valid,
Referenced to SSPCLK
Output 50 pF 2 mA tOVSSPENB
Output 50 pF 2 mA tOVSSPOUT
14ns
14ns
SSPTX
SSPRX
SSP Transmit Valid
SSP Receive Setup
Input
tISSSPIN
17 ns
INTERRUPTS
INTR[5:0]
Input
Note 1
NOTES:
1. INTR[5:0] are asynchronous signals. Interrupts must be held Active until serviced in Level Sensitive Mode,
and held Active for a minimum of 20 ns in Edge Sensitive Mode.
2. nDACK0, DACK1 and DREQ[1:0] are asynchronous signals. They must be held Active until serviced,
for a minimum of 20 ns.
EXTERNAL CLOCKS
Table 12. External Clocks AC Specifications
SYMBOL
DESCRIPTION
CLKIN Period
MIN.
UNIT
tCLKIN
6.66
2.8
2.8
1
ns
tSSPCLK
tCLKINH
tCLKINL
tSSPCLK
CLKIN HIGH Time
CLKIN LOW TIme
SSPCLK Period
ns
tSSPCLKH
tSSPCLKL
ns
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
tSSPCLKH SSPCLK HIGH Time
tSSPCLKL SSPCLK LOW Time
0.4
0.4
1
tUCLK
UCLK
79520-58
tUCLKH
tUCLKL
UCLK HIGH Time
UCLK LOW Time
0.4
0.4
Figure 9. Synchronous Serial I/F Clocks AC Timing
NOTES:
1. PCLK is the period chosen for the internal peripheral
clock domain.
2. MAX. period is DC. See ‘Recommended Operating Conditions’.
tUCLK
tUCLKH
tUCLKL
tCLKIN
tCLKINL
tCLKINH
79520-59
Figure 10. External UARTs/SIR Clock AC Timing
79520-57
Figure 8. External Clock AC Timing
30
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
then nWAIT must be asserted in the clock cycle imme-
diately following the clock cycle during which the nCSx
signal is asserted. Once the SMC detects that the
external device has deactivated nWAIT, the SMC will
complete its access in 3 system clock cycles.
Static Memory Controller Waveforms
nWAIT INPUT
The Static Memory Controller (SMC) supports an
nWAIT input that can be used by an external device to
extend the wait time during a memory access. The
SMC samples nWAIT at the beginning of at the begin-
ning of each system clock cycle. The system clock
cycle in which the nCSx signal is asserted counts as
the first wait state. See Figure 11.
The formula for the allowable delay between assert-
ing nCSx and asserting nWAIT is:
tASSERT = (system clock period) × (Wait States - 1)
(where Wait States is from 2 to 31.)
The SMC recognizes that nWAIT is active within 2
clock cycles after it has been asserted. To assure that
the current access (read or write) will be extended by
nWAIT, at least two wait states must be programmed
for this bank of memory. If N wait states are pro-
grammed, then the Static Memory Controller (SMC)
holds this state for N system clocks, or until the SMC
detects that nWAIT is inactive, whichever occurs last.
As the number of wait states programmed increases,
the amount of delay before nWAIT must be asserted
also increases. If only 2 wait states are programmed,
READ AND WRITE WAVEFORMS
Figure 12 shows the waveform and timing for an
External Static Memory Write. Figure 13 shows the
waveform and timing for an External Static Memory
Read, with one Wait State. Figure 14 shows the wave-
form and timing for an External Static Memory Read,
with two Wait States.
The signal tIDD is shown without a setup time, as
measurements are made from the Address Valid point
and HCLK is an internal signal, shown for reference only.
Preliminary data sheet
Rev. 01 — 16 July 2007
31
LH79520
NXP Semiconductors
System-on-Chip
Figure 11. nWait Assertion
32
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Figure 12. External Static Memory Write, One Wait State
Preliminary data sheet
Rev. 01 — 16 July 2007
33
LH79520
NXP Semiconductors
System-on-Chip
Figure 13. External Static Memory Read, One Wait State
34
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Figure 14. External Static Memory Write, Two Wait States
Preliminary data sheet
Rev. 01 — 16 July 2007
35
LH79520
NXP Semiconductors
System-on-Chip
Figure 15. Synchronous Serial Port Waveform
36
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
SDRAM Memory Controller Waveforms
Figure 16 shows the waveform and timing for an
SDRAM Burst Read (page already open). Figure 17
shows the waveform and timing for SDRAM to Activate
a Bank and Write.
tSDCLK
SCLK
tOHXXX
READ
SDRAMcmd
tOV
tOVXXX
A[15:0]
BANK,
COLUMN
tISD tIHD
DATA n
tOVA
D[31:0]
NOTES:
DATA n + 2
DATA n + 1
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X).
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. nDQM is LOW.
DATA n + 3
5. SDCKE is HIGH.
LH79520-35
Figure 16. SDRAM Burst Read
tSDCLK
SCLK
tOVC0
SDCKE
tOVXXX tOHXXX
ACTIVE
tOVA
WRITE
SDRAMcmd
A[15:0]
BANK,
ROW
BANK,
COLUMN
tOVA
DATA
D[31:0]
tOVD
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X).
tOHD
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. Refer to the AC timing table.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. nDQM is LOW.
79520-36
Figure 17. SDRAM Bank Activate and Write
Preliminary data sheet
Rev. 01 — 16 July 2007
37
LH79520
NXP Semiconductors
System-on-Chip
Figure 19 shows the timing with relation to a single
read or the last word of a burst read from the requesting
peripheral. Figure 20 shows the timing with relation to
a single write or the last word of a burst write to the
requesting peripheral.
External DMA Handshake Signal Timing
DREQ TIMING
As Figure 18 shows, once asserted, DREQ0 or
DREQ1 must not transition from LOW to HIGH again
until after nDACK0 or DACK1 has been asserted.
The timing of DACK/DEOT may become unpredict-
able when a Write to SDRAM occurs just prior to a sin-
gle word Write to the requesting peripheral. If the write
buffer is enabled for the SDRAM Controller, this can
cause the DACK/DEOT to occur an indeterminate
number of cycles prior to the actual Write to the
requesting peripheral.
DACK/DEOT TIMING
These timing diagrams indicate when nDACK0,
DACK1, DEOT0 and DEOT1 occur in relation to an
external bus access to/from the external peripheral that
requested the DMA transfer.
DREQ MAY
TRANSITON
DREQ
tDREQ0L,
tDREQ1L
MUST NOT
CHANGE STATE
DREQ0,
DREQ1
DACK1
nDACK0
NOTE: tDREQ0L = DREQ0 LOW Pulse Width = 2 HCLK MIN.
tDREQ1L = DREQ1 LOW Pulse Width = 2 HCLK MIN.
79520-158
Figure 18. DREQ Timing Restrictions
38
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
HCLK
(See Note)
A[23:0]
D[31:0]
ADDRESS
DATA
nCSx
nWEN
nBLE[1:0]
nOE
nDACK0/
DEOT0/DEOT1
DACK1
NOTE: * HCLK is an internal signal provided for reference only.
79520-156
Figure 19. Read, from Peripheral to Memory, Burst Size = 1
HCLK
(See Note)
A[23:0]
D[15:0]
ADDRESS
DATA
nCSx
nWEN
nBLE[1:0]
nOE
nDACK0/
DEOT0/DEOT1
DACK1
NOTE: * HCLK is an internal signal provided for reference only.
79520-157
Figure 20. Write, from Memory to Peripheral, Burst Size = 1
Preliminary data sheet
Rev. 01 — 16 July 2007
39
LH79520
NXP Semiconductors
System-on-Chip
HCLK*
A[23:0]
ADDRESS
DATA #1
DATA #2
DATA #3
DATA #4
D[31:0]
nCSx
nWEN
nBLE[1:0]
nOE
nDACK0/DEOT0/DEOT1
DACK1
NOTE: * HCLK is an internal signal, provided for reference only.
79520-169
Figure 21. Read, Peripheral to Memory: Peripheral Burst Size = 4
40
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Figure 22. Write, Memory to Peripheral: Burst Size = 4; Destination Width > External Access Width
Preliminary data sheet
Rev. 01 — 16 July 2007
41
LH79520
NXP Semiconductors
System-on-Chip
TFT VERTICAL TIMING
Figure 26 presents typical vertical timing waveforms
for TFT panels.
Color LCD Controller System Timing
Waveforms
This section contains typical output waveform dia-
grams.
AD-TFT AND HR-TFT HORIZONTAL TIMING
WAVEFORMS
STN HORIZONTAL TIMING
Figure 27 presents typical horizontal timing wave-
forms for AD-TFT and HR-TFT panels. The ALI adjusts
and delays the normal TFT timing for the Row and Col-
umn driver chips integrated into AD-TFT and HR-TFT
panels. Other panels requiring the use of the ALI will
have similar timing waveforms.
Figure 23 presents typical horizontal timing wave-
forms for STN panels. Figure 23 shows that the CLCDC
Clock (an input to the CLCDC) is scaled within the
CLCDC and utilized to produce the LCDDCLK output.
Figure 24 presents typical vertical timing waveforms
for STN panels.
AD-TFT AND HR-TFT VERTICAL TIMING
Figure 28 presents typical vertical timing wave-
forms for AD-TFT and HR-TFT panels. The power
sequencing and register information is the same
as for TFT vertical timing.
TFT HORIZONTAL TIMING
Figure 25 presents typical horizontal timing wave-
forms for TFT panels.
42
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Figure 23. STN Horizontal Timing Diagram
Preliminary data sheet
Rev. 01 — 16 July 2007
43
LH79520
NXP Semiconductors
System-on-Chip
Figure 24. STN Vertical Timing Diagram
44
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Figure 25. TFT Horizontal Timing Diagram
Preliminary data sheet
Rev. 01 — 16 July 2007
45
LH79520
NXP Semiconductors
System-on-Chip
Figure 26. TFT Vertical Timing Diagram
46
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
1 AD-TFT or HR-TFT HORIZONTAL LINE
CLCDC CLOCK
(INTERNAL)
PERIPHCLKSEL2:LCSRC
PERIPHCLKCTRL2:LCDCLK
LCDCLKPRESCALE:LCDPSVAL
(SHOWN FOR REFERENCE)
TIMING0:HSW
LCDLP
(HORIZONTAL SYNC PULSE)
LCDDCLK
(PANEL DATA CLOCK)
TIMING2:PCD
TIMING2:BCD
TIMING2:IPC
TIMING2:CPL
LCDMux:PIN133
LCDVD[17:0]
16 × (TIMING0:PPL+1)
001 002 003 004 005 006 007 008
PIXEL DATA
320
TIMING0:HSW +
TIMING0:HBP
LCDENAB
(INTERNAL DATA ENABLE)
133 LCDDCLK
(DELAYED FOR HR-TFT)
LCDVD[17:0]
(DELAYED FOR HR-TFT)
001 002 003 004 005 006
317 318 319 320
1 LCDDCLK
ALITIMING2:SPLDEL
LCDSPL
(LINE START PULSE LEFT)
137
131
1 LCDDCLK
ALITIMING1:LPDEL
LCDLP
(HORIZONTAL SYNC PULSE)
ALITIMING1:PSCLS
ALITIMING2:PS2CLS2
135 LCDCLS
LCDPS
119
ALITIMING1:REVDEL
142 LCDREV
NOTE:
Circled numbers are LH79520 pin numbers.
79520-120
Figure 27. AD-TFT and HR-TFT Horizontal Timing Diagram
TIMING1:VSW
LCDSPS
(Vertical Sync)
1.5 µs - 4 µs
LCDCLS
(Gate Driver Clock)
LCDVD[17:0]
(LCD DATA)
NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz.
79520-20
Figure 28. AD-TFT and HR-TFT Vertical Timing Diagram
Preliminary data sheet
Rev. 01 — 16 July 2007
47
LH79520
NXP Semiconductors
System-on-Chip
Reset, Clock, and Power Controller
(RCPC) Waveforms
Figure 29 shows the method the LH79520 uses
when coming out of Reset or Power On.
Figure 30 shows external reset timing, and Table 13
gives the timing parameters.
Table 13. Reset AC Timing
DESCRIPTION
PARAMETER
MIN. TYP. MAX.
UNIT
tOSC32
tOSC14
tRSTIW
Oscillator stabilization time after Power Up (VDDC = VDDCMIN)
Oscillator stabilization time after Power Up (VDDC = VDDCMIN)
nRESETIN Pulse Width (once sampled LOW)
550
2.5
ms
ms
2
HCLK
nRESETIN LOW to nRESETOUT valid
(once nRESETIN sampled LOW)
tRSTOV
3.5
1
HCLK
tRSTIH
nRESETIN hold extend to allow PLL to lock once XTAL is stable
nRESETOUT hold relative to nRESETIN HIGH
10
µs
tRSTOH
HCLK
VDDCmin
VDDC
tOSC32
XTAL32
XTAL14
tRSTIH
tOSC14
nRESETI
tRSTOH
nRESETO
79520-37
Figure 29. PLL Start-up
tRSTIW
nRESETIN
tRSTOH
tRSTOV
nRESETO
79520-60
Figure 30. External Reset
48
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
NXP recommends that users implementing a system
to meet industrial temperature standards should use an
external oscillator rather than a crystal to drive the sys-
tem clock input of the System-on-Chip. This change
from crystal to oscillator will increase the robustness
(i.e., noise immunity of the clock input to the SoC).
Power Supply Sequencing
The 1.8 V power supply must be energized before
the 3.3 V supply. Otherwise, the 1.8 V supply may not
lag the 3.3 V supply by more than 10 µs.
If a longer delay time is needed, the voltage differ-
ence between the two power supplies must be within
1.5 V during power supply ramp up.
Assuring Proper Reset Behavior
To prevent a potential latch-up condition, voltage
should only be applied to input pins after the device is
powered-up as described above.
A separate reset for the TAP controller and power-
on was designed into the LH79520 to give the Designer
control over how the chip boots up and to be useful for
bringing up software and hardware using E-ICE.
Low Operating Temperatures and
Noise Immunity
However, for the LH79520 to enter Normal mode, an
initial reset pulse is required for the TAP controller
when Power-on Reset is asserted.
The junction temperature, Tj, is the operating tem-
perature of the transistors in the integrated circuit. The
switching speed of the CMOS circuitry within the SoC
depends partly on Tj, and the lower the operating tem-
perature, the faster the CMOS circuits will switch.
Increased switching noise generated by faster switch-
ing circuits could affect the overall system stability. The
amount of switching noise is directly affected by the
application executed on the SoC.
Figure 31 illustrates one method for assuring proper
TAP controller reset. This is a recommendation;
Designers should assess their requirements and imple-
ment a solution that satisfies them.
This recommended circuit uses an external AND
gate to AND the nRESETIN and nTRST signals, insur-
ing that the TAP Controller gets reset with either signal,
and the LH79520 always powers up in Normal Mode.
LH79520
nTRST
nTRST
nRESETIN
nRESETIN
79520-174
Figure 31. TAP Controller Reset Circuit Example
Preliminary data sheet
Rev. 01 — 16 July 2007
49
LH79520
NXP Semiconductors
System-on-Chip
Similarly, the VSSA path is from the IC pin to the
high frequency capacitor, then to the low frequency
capacitor, keeping the distance from the IC pin to the
high frequency cap as short as possible.
Printed Circuit Board Layout Practices
LH79520 POWER SUPPLY DECOUPLING
The LH79520 has separate power and ground pins
for different internal circuitry sections. The VDD and
VSS pins supply power to I/O buffers, while VDDC and
VSSC supply power to the core logic.
CAUTION
Note that the VSSA pin specifically does not have a connection to the
circuit board ground. The LH79520 PLL circuit has an internal DC
ground connection to VSS (GND), so the external VSSA pin must
NOT be connected to the circuit board ground, but only to the filter
components.
Each of the VDD and VDDC pins must be provided
with a low impedance path to the corresponding board
power supply. Likewise, the VSS and VSSC pins must be
provided with a low impedance path to the board ground.
Each power supply must be decoupled to ground
using at least one 0.1 µF high frequency capacitor
located as close as possible to a VDDx, VSSx pin pair
on each of the four sides of the chip. If room on the cir-
cuit board allows, add one 0.01 µF high frequency
capacitor near each VDDx, VSSx pair on the chip.
UNUSED INPUT SIGNAL CONDITIONING
Floating input signals can cause excessive power
consumption. Unused inputs which do not include inter-
nal pull-up or pull-down resistors should be pulled up or
down externally, to tie the signal to its inactive state.
To be effective, the capacitor leads and associated
circuit board traces connecting to the chip VDDx, VSSx
pins must be kept to less than half an inch (12.7 mm)
per capacitor lead. There must be one bulk 10 µF
capacitor for each power supply placed near one side
of the chip.
Some GPIO signals may default to inputs. If the pins
which carry these signals are unused, software can
program these signals as outputs, to eliminate the need
for pull-ups or pull-downs. Power consumption may be
higher than expected until such software executes.
Some LH79520 inputs have internal pull-ups or pull-
downs. If unused, these inputs do not require external
conditioning.
REQUIRED LH79520 PLL, VDDA, VSSA FILTER
The VDDA pin supplies power to the chip PLL cir-
cuitry. VSSA is the ground return path for the PLL circuit.
If the internal PLL circuit will be used, these pins must
have a low-pass filter attached as shown in Figure 32.
OTHER CIRCUIT BOARD LAYOUT PRACTICES
All output pins on the LH79520 have fast rise and fall
times. Printed circuit trace interconnection length must
therefore be reduced to minimize overshoot, under-
shoot and reflections caused by transmission line
effects of these fast output switching times. This rec-
ommendation particularly applies to the address and
data buses.
VDDC
(SOURCE)
VDDC
LH79520
When considering capacitance, calculations must
consider all device loads and capacitances due to the
circuit board traces. Capacitance due to the traces will
depend upon a number of factors, including the trace
width, dielectric material the circuit board is made from
and proximity to ground and power planes.
100 Ω
PIN 91
VDDA
+
22 µF
0.1 µF
PIN 92
VSSA
Attention to power supply decoupling and printed cir-
cuit board layout becomes more critical in systems with
higher capacitive loads. As these capacitive loads
increase, transient currents in the power supply and
ground return paths also increase.
79520-64
Figure 32. VDDA, VSSA Filter Circuit
The Schottky diode shown in the schematic must
have a low forward drop specification, to allow VDDA to
quickly transition through the entire input voltage range.
Add pull-up resistors to all unused inputs unless
an internal pull-down resistor has been specified;
see Table 3. (All pull-up/pull-down resistors must be
33 KΩ MAX.) Consider all signals that are Inputs at
Reset time.
The power pin VDDA path must be a single wire
from the IC package pin to the high frequency capaci-
tor, then to the low frequency capacitor, and finally
through the series resistor to the board power supply.
The distance from the IC pin to the high frequency
capacitor must be kept as short as possible.
50
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
Figure 34 shows the suggested external components
for the 14.7456 MHz crystal circuit to be used with the
NXP LH79520. The NAND gate represents the logic
inside the SoC. See the chart for crystal specifics.
SUGGESTED EXTERNAL COMPONENTS
Figure 33 shows the suggested external compo-
nents for the 32.768 kHz crystal circuit to be used with
the NXP LH79520. The NAND gate represents the
logic inside the SoC. See the chart for crystal specifics.
ENABLE
INTERNAL TO
THE LH79520
EXTERNAL TO
THE LH79520
XTAL32IN
XTAL32OUT
Y1
32.768 kHz
R1
10 MΩ
C1
15 pF
C2
18 pF
GND
GND
RECOMMENDED CRYSTAL SPECIFICATIONS
NOTES:
1. Y1 is a parallel-resonant type crystal. (See table)
2. The nominal values for C1 and C2 shown are for
a crystal specified at 12.5 pF load capacitance (CL).
3. The values for C1 and C2 are dependent upon
the cystal's specified load capacitance and PCB
stray capacitance.
PARAMETER
DESCRIPTION
32.768 kHz Crystal
Tolerance
Aging
Load Capacitance
ESR (MAX.)
Drive Level
Parallel Mode
30 ppm
3 ppm
12.5 pF
50 kΩ
1.0 µW (MAX.)
MTRON SX1555 or equivalent
4. R1 must be in the circuit.
5. Ground connections should be short and return
to the ground plane which is connected to the
processor's core ground pins.
Recommended Part
6. Tolerance for R1, C1, C2 is ≤ 5%.
79520-172
Figure 33. Suggested External Components, 32.768 kHz Oscillator (XTAL32IN and XTAL32OUT)
Preliminary data sheet
Rev. 01 — 16 July 2007
51
LH79520
NXP Semiconductors
System-on-Chip
ENABLE
INTERNAL TO
THE LH79520
EXTERNAL TO
THE LH79520
XTALIN
XTALOUT
Y1
14.7456 MHz
R1
1 MΩ
C1
18 pF
C2
22 pF
GND
GND
RECOMMENDED CRYSTAL SPECIFICATIONS
PARAMETER DESCRIPTION
14.7456 MHz Crystal (AT-Cut) Parallel Mode
NOTES:
1. Y1 is a parallel-resonant type crystal. (See table)
2. The nominal values for C1 and C2 shown are for
a crystal specified at 18 pF load capacitance (CL).
3. The values for C1 and C2 are dependent upon
the cystal's specified load capacitance and PCB
stray capacitance.
Tolerance
50 ppm
100 ppm
5 ppm
Stability
Aging
4. R1 must be in the circuit.
Load Capacitance
ESR (MAX.)
Drive Level
Recommended Part
18 pF
40 Ω
5. Ground connections should be short and return
to the ground plane which is connected to the
processor's core ground pins.
100 µW (MAX.)
MTRON SX2050 or equivalent
6. Tolerance for R1, C1, C2 is ≤ 5%.
79520-173
Figure 34. Suggested External Components, 14.7456 MHz Oscillator
52
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
PACKAGE SPECIFICATIONS
LQFP176: plastic low profile quad flat package; 176 leads; body 20 x 20 x 1.4 mm
SOT1017-1
c
y
X
A
89
132
Z
E
133
88
e
(A )
3
A
2
A
1
H
E
A
E
M
w
θ
b
L
p
p
L
pin 1 index
176
45
detail X
44
1
M
M
v
A
B
M
w
e
b
Z
D
p
D
B
H
v
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
1
A
2
A
3
b
p
c
D
E
e
H
D
H
E
L
L
p
v
w
y
Z
D
Z
E
θ
max
°
°
0.15 1.45
0.05 1.35
0.23 0.20 20.2 20.2
0.13 0.09 19.8 19.8
22.2 22.2
21.8 21.8
0.75
0.45
1.5
1.3
1.5
1.3
7
0
mm
1.6
0.25
0.4
1
0.2
0.07 0.08
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
07-07-07
07-07-07
SOT1017-1
Figure 35. Package outline SOT1017-1 (LQFP176)
Preliminary data sheet
Rev. 01 — 16 July 2007
53
LH79520
NXP Semiconductors
System-on-Chip
21.25
0.4
1.70
17.2
NOTE: Dimensions in mm.
79520-155
Figure 36. Recommended PCB Footprint
54
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH79520
REVISION HISTORY
Table 14. Revision history
Document ID
Release date Data sheet status
Change notice Supersedes
LH79520 Data Sheet v1_3
LH79520_N_1
20070716
Preliminary data
sheet
-
Modifications:
• First NXP version based on the LH79520 data sheet of 20060330
Preliminary data sheet
Rev. 01 — 16 July 2007
55
LH79520
NXP Semiconductors
System-on-Chip
1. Legal information
1.1
Data sheet status
[1][2]
[3]
Document status
Product status
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
1.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the full
data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
1.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
1.4
Trademarks
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
2. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
© NXP B.V. 2007. All rights reserved.
IMPORTANT NOTICE
Dear customer,
As from June 1st, 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from
Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data
sheets where the previous Sharp or Sharp Corporation references remain, please use the new
links as shown below.
For www.sharpsma.com use www.nxp.com/microcontrollers
for indicated sales addresses use salesaddresses@nxp.com (email)
The copyright notice at the bottom of each page (or elsewhere in the document, depending on the
version)
- Copyright © (year) by SHARP Corporation.
is replaced with:
- © NXP B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via
e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and
understanding, In addition to that the Annex A (attached hereto) is added to the document.
NXP Semiconductors
ANNEX A: Disclaimers (11)
1. t001dis100.fm: General (DS, AN, UM)
General — Information in this document is believed to be accurate and reliable. However, NXP
Semiconductors does not give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability for the consequences of
use of such information.
2. t001dis101.fm: Right to make changes (DS, AN, UM)
Right to make changes — NXP Semiconductors reserves the right to make changes to
information published in this document, including without limitation specifications and product
descriptions, at any time and without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
3. t001dis102.fm: Suitability for use (DS, AN, UM)
Suitability for use — NXP Semiconductors products are not designed, authorized or warranted
to be suitable for use in medical, military, aircraft, space or life support equipment, nor in
applications where failure or malfunction of a NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe property or environmental damage. NXP
Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in
such equipment or applications and therefore such inclusion and/or use is at the customer’s own
risk.
4. t001dis103.fm: Applications (DS, AN, UM)
Applications — Applications that are described herein for any of these products are for
illustrative purposes only. NXP Semiconductors makes no representation or warranty that such
applications will be suitable for the specified use without further testing or modification.
5. t001dis104.fm: Limiting values (DS)
Limiting values — Stress above one or more limiting values (as defined in the Absolute
Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting
values are stress ratings only and operation of the device at these or any other conditions above
those given in the Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
6. t001dis105.fm: Terms and conditions of sale (DS)
Terms and conditions of sale — NXP Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms,
including those pertaining to warranty, intellectual property rights infringement and limitation of
liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any
inconsistency or conflict between information in this document and such terms and conditions, the
latter will prevail.
7. t001dis106.fm: No offer to sell or license (DS)
No offer to sell or license — Nothing in this document may be interpreted or construed as an
offer to sell products that is open for acceptance or the grant, conveyance or implication of any
license under any copyrights, patents or other industrial or intellectual property rights.
8. t001dis107.fm: Hazardous voltage (DS, AN, UM; if applicable)
Hazardous voltage — Although basic supply voltages of the product may be much lower, circuit
voltages up to 60 V may appear when operating this product, depending on settings and
application. Customers incorporating or otherwise using these products in applications where
such high voltages may appear during operation, assembly, test etc. of such application, do so at
their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages
resulting from or in connection with such high voltages. Furthermore, customers are drawn to
safety standards (IEC 950, EN 60 950, CENELEC, ISO, etc.) and other (legal) requirements
applying to such high voltages.
9. t001dis108.2.fm: Bare die (DS; if applicable)
Bare die (if applicable) — Products indicated as Bare Die are subject to separate specifications
and are not tested in accordance with standard testing procedures. Product warranties and
guarantees as stated in this document are not applicable to Bare Die Products unless such
warranties and guarantees are explicitly stated in a valid separate agreement entered into by
NXP Semiconductors and customer.
10. t001dis109.fm: AEC unqualified products (DS, AN, UM; if applicable)
AEC unqualified products — This product has not been qualified to the appropriate Automotive
Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive critical
applications, including but not limited to applications where failure or malfunction of an NXP
Semiconductors product can reasonably be expected to result in personal injury, death or severe
property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or
use of NXP Semiconductors products in such equipment or applications and therefore such
inclusion and/or use is for the customer’s own risk.
11. t001dis110.fm: Suitability for use in automotive applications only (DS, AN, UM; if
applicable)
Suitability for use in automotive applications only — This NXP Semiconductors product has
been developed for use in automotive applications only. The product is not designed, authorized
or warranted to be suitable for any other use, including medical, military, aircraft, space or life
support equipment, nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore such inclusion and/or
use is at the customer’s own risk.
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