LPC11U12FHN33.201 [NXP]
32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; 6 kB SRAM; USB device; USART; 32位ARM Cortex -M0微控制器;高达32 KB的闪存; 6 KB的SRAM ; USB设备; USART型号: | LPC11U12FHN33.201 |
厂家: | NXP |
描述: | 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; 6 kB SRAM; USB device; USART |
文件: | 总69页 (文件大小:1581K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LPC11U1x
32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; 6 kB
SRAM; USB device; USART
Rev. 2 — 11 January 2012
Product data sheet
1. General description
The LPC11U1x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction
set and memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11U1x operate at CPU frequencies of up to 50 MHz.
Equipped with a highly flexible and configurable Full Speed USB 2.0 device controller, the
LPC11U1x brings unparalleled design flexibility and seamless integration to today’s
demanding connectivity solutions.
The peripheral complement of the LPC11U1x includes up to 32 kB of flash memory, 6 kB
of SRAM data memory, one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485
USART with support for synchronous mode and smart card interface, two SSP interfaces,
four general purpose counter/timers, a 10-bit ADC, and up to 40 general purpose I/O pins.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Non Maskable Interrupt (NMI) input selectable from several input sources.
System tick timer.
Memory:
Up to 32 kB on-chip flash program memory.
Total of 6 kB SRAM data memory (4 kB main SRAM and 2 kB USB SRAM).
16 kB boot ROM includes
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
ROM-based 32-bit integer division routines.
Debug options:
Standard JTAG test interface for BSDL.
Serial Wire Debug.
Digital peripherals:
Up to 40 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, input inverter, and open-drain mode. Eight pins support a
programmable glitch filter.
Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Two GPIO grouped interrupt modules enable an interrupt based on a
programmable pattern of input states of a group of GPIO pins.
High-current source output driver (20 mA) on one pin (P0_7).
High-current sink driver (20 mA) on true open-drain pins (P0_4 and P0_5).
Four general purpose counter/timers with a total of up to 5 capture inputs and 13
match outputs.
Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal
low-power WatchDog Oscillator (WDO).
Analog peripherals:
10-bit ADC with input multiplexing among eight pins.
Serial interfaces:
USB 2.0 full-speed device controller.
USART with fractional baud rate generation, internal FIFO, a full modem control
handshake interface, and support for RS-485/9-bit mode and synchronous mode.
USART supports an asynchronous smart card interface (ISO 7816-3).
Two SSP controllers with FIFO and multi-protocol capabilities.
I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with
a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
Clock generation:
Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).
12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as
a system clock.
Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable
frequency output.
PLL allows CPU operation up to the maximum CPU rate with the system oscillator
or the IRC as clock sources.
A second, dedicated PLL is provided for USB.
Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
Power control:
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Power profiles residing in boot ROM allow optimized performance and minimized
power consumption for any given application through one simple function call.
Processor wake-up from Deep-sleep and Power-down modes via reset, selectable
GPIO pins, watchdog interrupt, or USB port activity.
Processor wake-up from Deep power-down mode using one special function pin.
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, Power-down, and Deep power-down modes.
Power-On Reset (POR).
Brownout detect with four separate thresholds for interrupt and forced reset.
Unique device serial number for identification.
Single 3.3 V power supply (1.8 V to 3.6 V).
Temperature range 40 C to +85 C.
Available as LQFP48, TFBGA48, and HVQFN33 packages.
Pin compatible to the LPC134x series.
LPC11U1X
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 11 January 2012
2 of 69
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
3. Applications
Consumer peripherals
Handheld scanners
USB audio devices
Medical
Industrial control
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC11U12FHN33/201 HVQFN33
plastic thermal enhanced very thin quad flat package; no leads; 33
n/a
terminals; body 7 7 0.85 mm
LPC11U12FBD48/201 LQFP48
LPC11U13FBD48/201 LQFP48
LPC11U14FHN33/201 HVQFN33
plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
plastic thermal enhanced very thin quad flat package; no leads; 33
n/a
terminals; body 7 7 0.85 mm
LPC11U14FHI33/201
HVQFN33
plastic thermal enhanced very thin quad flat package; no leads; 33
n/a
terminals; body 5 5 0.85 mm
LPC11U14FBD48/201 LQFP48
LPC11U14FET48/201 TFBGA48
plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
plastic thin fine-pitch ball grid array package; 48 balls; body
SOT1155-2
4.5 4.5 0.7 mm
4.1 Ordering options
Table 2.
Ordering options
Type number
Flash SRAM
USART
I2C-bus
FM+
SSP USB
ADC
GPIO
device channels pins
CPU
16 kB 4 kB
16 kB 4 kB
24 kB 4 kB
32 kB 4 kB
32 kB 4 kB
32 kB 4 kB
32 kB 4 kB
USB
2 kB
2 kB
2 kB
2 kB
2 kB
2 kB
2 kB
Total
6 kB
6 kB
6 kB
6 kB
6 kB
6 kB
6 kB
LPC11U12FHN33/201
LPC11U12FBD48/201
LPC11U13FBD48/201
LPC11U14FHN33/201
LPC11U14FHI33/201
LPC11U14FBD48/201
LPC11U14FET48/201
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
1
1
1
1
1
1
1
8
8
8
8
8
8
8
26
40
40
26
26
40
40
LPC11U1X
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 11 January 2012
3 of 69
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
5. Block diagram
SWD, JTAG
XTALIN XTALOUT
RESET
LPC11U12/13/14
SYSTEM OSCILLATOR
CLOCK
GENERATION,
IRC, WDO
BOD
TEST/DEBUG
INTERFACE
POWER CONTROL,
SYSTEM
CLKOUT
FUNCTIONS
POR
ARM
CORTEX-M0
PLL0
USB PLL
FLASH
16/24/32 kB
SRAM
6 kB
ROM
16 kB
system bus
master
slave
slave
slave
slave
USB_DP
USB_DM
USB_VBUS
slave
USB DEVICE
CONTROLLER
HIGH-SPEED
GPIO
AHB-LITE BUS
GPIO ports 0/1
USB_FTOGGLE,
USB_CONNECT
slave
AHB TO APB
BRIDGE
RXD
TXD
DCD, DSR , RI
CTS, RTS, DTR
SCLK
USART/
SMARTCARD INTERFACE
(1)
(1)
AD[7:0]
10-bit ADC
SCL, SDA
2
I C-BUS
CT16B0_MAT[1:0]
16-bit COUNTER/TIMER 0
CT16B0_CAP0
SCK0, SSEL0,
MISO0, MOSI0
SSP0
CT16B1_MAT[1:0]
CT16B1_CAP0
CT32B0_MAT[3:0]
16-bit COUNTER/TIMER 1
32-bit COUNTER/TIMER 0
SCK1, SSEL1,
MISO1, MOSI1
SSP1
(1)
CT32B0_CAP[1:0]
IOCON
CT32B1_MAT[3:0]
32-bit COUNTER/TIMER 1
(2)
CT32B1_CAP[1:0]
SYSTEM CONTROL
PMU
WINDOWED WATCHDOG
TIMER
GPIO pins
GPIO PIN INTERRUPTS
GPIO pins
GPIO pins
GPIO GROUP0 INTERRUPT
GPIO GROUP1 INTERRUPT
002aaf885
(1) DSR, RI, CT32B0_CAP1 are not available on HVQFN33 packages.
(2) CT32B1_CAP1 is available only on the TFBGA48package.
Fig 1. Block diagram
LPC11U1X
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 11 January 2012
4 of 69
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
6. Pinning information
6.1 Pinning
terminal 1
index area
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PIO1_19/DTR/SSEL1
TRST/PIO0_14/AD3/CT32B1_MAT1
TDO/PIO0_13/AD2/CT32B1_MAT0
TMS/PIO0_12/AD1/CT32B1_CAP0
TDI/PIO0_11/AD0/CT32B0_MAT3
PIO0_22/AD6/CT16B1_MAT1/MISO1
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO0_9/MOSI0/CT16B0_MAT1
RESET/PIO0_0
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE
XTALIN
LPC11U1x
XTALOUT
V
DD
PIO0_20/CT16B1_CAP0
33 V
SS
PIO0_2/SSEL0/CT16B0_CAP0
PIO0_8/MISO0/CT16B0_MAT0
002aaf888
Transparent top view
Fig 2. Pin configuration (HVQFN33)
LPC11U1X
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 11 January 2012
5 of 69
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
1
2
36
35
34
33
32
31
30
29
28
27
26
25
PIO1_25/CT32B0_MAT1
PIO1_13/DTR/CT16B0_MAT0/TXD
TRST/PIO0_14/AD3/CT32B1_MAT1
TDO/PIO0_13/AD2/CT32B1_MAT0
TMS/PIO0_12/AD1/CT32B1_CAP0
TDI/PIO0_11/AD0/CT32B0_MAT3
PIO1_29/SCK0/CT32B0_CAP1
PIO0_22/AD6/CT16B1_MAT1/MISO1
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO0_9/MOSI0/CT16B0_MAT1
PIO0_8/MISO0/CT16B0_MAT0
PIO1_21/DCD/MISO1
PIO1_19/DTR/SSEL1
RESET/PIO0_0
3
4
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE
5
V
SS
6
XTALIN
LPC11U1x
7
XTALOUT
8
V
DD
9
PIO0_20/CT16B1_CAP0
PIO0_2/SSEL0/CT16B0_CAP0
PIO1_26/CT32B0_MAT2/RXD
PIO1_27/CT32B0_MAT3/TXD
10
11
12
PIO1_31
002aaf884
Fig 3. Pin configuration (LQFP48)
LPC11U1X
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 11 January 2012
6 of 69
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
ball A1
index area
LPC11U1x
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
002aag101
Transparent top view
Fig 4. Pin configuration (TFBGA48)
LPC11U1X
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 11 January 2012
7 of 69
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
6.2 Pin description
Table 3 shows all pins and their assigned digital or analog functions ordered by GPIO port
number. The default function after reset is listed first. All port pins have internal pull-up
resistors enabled after reset with the exception of the true open-drain pins PIO0_4 and
PIO0_5.
Every port pin has a corresponding IOCON register for programming the digital or analog
function, the pull-up/pull-down configuration, the repeater, and the open-drain modes.
The USART, counter/timer, and SSP functions are available on more than one port pin.
Table 4 shows how peripheral functions are assigned to port pins.
Table 3.
Symbol
Pin description
Reset Type
Description
state
[1]
[2]
RESET/PIO0_0
2
3
C1
I; PU
I
RESET — External reset input with 20 ns glitch
filter. A LOW-going pulse as short as 50 ns on
this pin resets the device, causing I/O ports and
peripherals to take on their default states, and
processor execution to begin at address 0. This
pin also serves as the debug select input. LOW
level selects the JTAG boundary scan. HIGH
level selects the ARM SWD debug mode.
-
I/O
I/O
PIO0_0 — General purpose digital input/output
pin.
[3]
PIO0_1/CLKOUT/
CT32B0_MAT2/
USB_FTOGGLE
3
4
C2
I; PU
PIO0_1 — General purpose digital input/output
pin. A LOW level on this pin during reset starts
the ISP command handler.
-
-
O
O
CLKOUT — Clockout pin.
CT32B0_MAT2 — Match output 2 for 32-bit
timer 0.
-
O
USB_FTOGGLE — USB 1 ms Start-of-Frame
signal.
[3]
PIO0_2/SSEL0/
CT16B0_CAP0
8
9
10 F1
I; PU
I/O
PIO0_2 — General purpose digital input/output
pin.
-
-
I/O
I
SSEL0 — Slave select for SSP0.
CT16B0_CAP0 — Capture input 0 for 16-bit
timer 0.
[3]
[4]
PIO0_3/USB_VBUS
PIO0_4/SCL
14 H2
I; PU
I/O
I
PIO0_3 — General purpose digital input/output
pin.
-
USB_VBUS — Monitors the presence of USB
bus power.
10 15 G3
I; IA
-
I/O
I/O
PIO0_4 — General purpose digital input/output
pin (open-drain).
SCL — I2C-bus clock input/output (open-drain).
High-current sink only if I2C Fast-mode Plus is
selected in the I/O configuration register.
LPC11U1X
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 11 January 2012
8 of 69
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
Pin description
Reset Type
Description
state
[1]
[4]
[3]
PIO0_5/SDA
11 16 H3
I; IA
-
I/O
I/O
PIO0_5 — General purpose digital input/output
pin (open-drain).
SDA — I2C-bus data input/output (open-drain).
High-current sink only if I2C Fast-mode Plus is
selected in the I/O configuration register.
PIO0_6/USB_CONNECT/
SCK0
15 22 H6
I; PU
-
I/O
O
PIO0_6 — General purpose digital input/output
pin.
USB_CONNECT — Signal used to switch an
external 1.5 k resistor under software control.
Used with the SoftConnect USB feature.
-
I/O
I/O
SCK0 — Serial clock for SSP0.
[5]
[3]
PIO0_7/CTS
16 23 G7
17 27 F8
I; PU
PIO0_7 — General purpose digital input/output
pin (high-current output driver).
-
I
CTS — Clear To Send input for USART.
PIO0_8/MISO0/
CT16B0_MAT0
I; PU
I/O
PIO0_8 — General purpose digital input/output
pin.
-
-
I/O
O
MISO0 — Master In Slave Out for SSP0.
CT16B0_MAT0 — Match output 0 for 16-bit
timer 0.
[3]
[3]
PIO0_9/MOSI0/
CT16B0_MAT1
18 28 F7
I; PU
I/O
PIO0_9 — General purpose digital input/output
pin.
-
-
I/O
O
MOSI0 — Master Out Slave In for SSP0.
CT16B0_MAT1 — Match output 1 for 16-bit
timer 0.
SWCLK/PIO0_10/SCK0/
CT16B0_MAT2
19 29 E7
I; PU
-
I
SWCLK — Serial wire clock and test clock TCK
for JTAG interface.
I/O
PIO0_10 — General purpose digital
input/output pin.
-
-
O
O
SCK0 — Serial clock for SSP0.
CT16B0_MAT2 — Match output 2 for 16-bit
timer 0.
[6]
TDI/PIO0_11/AD0/
CT32B0_MAT3
21 32 D8
I; PU
-
I
TDI — Test Data In for JTAG interface.
I/O
PIO0_11 — General purpose digital input/output
pin.
-
-
I
AD0 — A/D converter, input 0.
O
CT32B0_MAT3 — Match output 3 for 32-bit
timer 0.
LPC11U1X
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 11 January 2012
9 of 69
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
Pin description
Reset Type
Description
state
[1]
[6]
[6]
[6]
[6]
[6]
TMS/PIO0_12/AD1/
CT32B1_CAP0
22 33 C7
23 34 C8
24 35 B7
25 39 B6
26 40 A6
I; PU
-
I
TMS — Test Mode Select for JTAG interface.
I/O
PIO_12 — General purpose digital input/output
pin.
-
-
I
I
AD1 — A/D converter, input 1.
CT32B1_CAP0 — Capture input 0 for 32-bit
timer 1.
TDO/PIO0_13/AD2/
CT32B1_MAT0
I; PU
-
O
TDO — Test Data Out for JTAG interface.
I/O
PIO0_13 — General purpose digital
input/output pin.
-
-
I
AD2 — A/D converter, input 2.
O
CT32B1_MAT0 — Match output 0 for 32-bit
timer 1.
TRST/PIO0_14/AD3/
CT32B1_MAT1
I; PU
-
I
TRST — Test Reset for JTAG interface.
I/O
PIO0_14 — General purpose digital
input/output pin.
-
-
I
AD3 — A/D converter, input 3.
O
CT32B1_MAT1 — Match output 1 for 32-bit
timer 1.
SWDIO/PIO0_15/AD4/
CT32B1_MAT2
I; PU
-
I/O
I/O
SWDIO — Serial wire debug input/output.
PIO0_15 — General purpose digital
input/output pin.
-
-
I
AD4 — A/D converter, input 4.
O
CT32B1_MAT2 — Match output 2 for 32-bit
timer 1.
PIO0_16/AD5/
I; PU
I/O
PIO0_16 — General purpose digital
CT32B1_MAT3/WAKEUP
input/output pin.
-
-
I
AD5 — A/D converter, input 5.
O
CT32B1_MAT3 — Match output 3 for 32-bit
timer 1.
-
I
WAKEUP — Deep power-down mode wake-up
pin with 20 ns glitch filter. This pin must be
pulled HIGH externally to enter Deep
power-down mode and pulled LOW to exit Deep
power-down mode. A LOW-going pulse as short
as 50 ns wakes up the part.
[3]
PIO0_17/RTS/
30 45 A3
I; PU
I/O
PIO0_17 — General purpose digital
CT32B0_CAP0/SCLK
input/output pin.
-
-
O
I
RTS — Request To Send output for USART.
CT32B0_CAP0 — Capture input 0 for 32-bit
timer 0.
-
I/O
SCLK — Serial clock input/output for USART in
synchronous mode.
LPC11U1X
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 11 January 2012
10 of 69
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
Pin description
Reset Type
Description
state
[1]
[3]
PIO0_18/RXD/
CT32B0_MAT0
31 46 B3
I; PU
I/O
I
PIO0_18 — General purpose digital
input/output pin.
-
RXD — Receiver input for USART.Used in
UART ISP mode.
-
O
CT32B0_MAT0 — Match output 0 for 32-bit
timer 0.
[3]
PIO0_19/TXD/
CT32B0_MAT1
32 47 B2
I; PU
I/O
O
PIO0_19 — General purpose digital
input/output pin.
-
TXD — Transmitter output for USART. Used in
UART ISP mode.
-
O
CT32B0_MAT1 — Match output 1 for 32-bit
timer 0.
[3]
[3]
PIO0_20/CT16B1_CAP0
7
9
F2
I; PU
I/O
I
PIO0_20 — General purpose digital
input/output pin.
-
CT16B1_CAP0 — Capture input 0 for 16-bit
timer 1.
PIO0_21/CT16B1_MAT0/
MOSI1
12 17 G4
I; PU
-
I/O
O
PIO0_21 — General purpose digital
input/output pin.
CT16B1_MAT0 — Match output 0 for 16-bit
timer 1.
-
I/O
I/O
MOSI1 — Master Out Slave In for SSP1.
[6]
PIO0_22/AD6/
20 30 E8
I; PU
PIO0_22 — General purpose digital
CT16B1_MAT1/MISO1
input/output pin.
-
-
I
AD6 — A/D converter, input 6.
O
CT16B1_MAT1 — Match output 1 for 16-bit
timer 1.
-
I/O
I/O
MISO1 — Master In Slave Out for SSP1.
[6]
[3]
PIO0_23/AD7
27 42 A5
I; PU
PIO0_23 — General purpose digital
input/output pin.
-
I
AD7 — A/D converter, input 7.
PIO1_5/CT32B1_CAP1
-
-
-
H8
I; PU
I/O
PIO1_5 — General purpose digital input/output
pin.
-
I
CT32B1_CAP1 — Capture input 1 for 32-bit
timer 1.
[3]
PIO1_13/DTR/
36 B8
I; PU
I/O
PIO1_13 — General purpose digital
CT16B0_MAT0/TXD
input/output pin.
-
-
O
O
DTR — Data Terminal Ready output for USART.
CT16B0_MAT0 — Match output 0 for 16-bit
timer 0.
-
O
TXD — Transmitter output for USART.
LPC11U1X
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 11 January 2012
11 of 69
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
Pin description
Reset Type
Description
state
[1]
[3]
[3]
[3]
PIO1_14/DSR/
CT16B0_MAT1/RXD
-
37 A8
I; PU
I/O
PIO1_14 — General purpose digital
input/output pin.
-
-
I
DSR — Data Set Ready input for USART.
O
CT16B0_MAT1 — Match output 1 for 16-bit
timer 0.
-
I
RXD — Receiver input for USART.
PIO1_15/DCD/
CT16B0_MAT2/SCK1
28 43 A4
I; PU
I/O
PIO1_15 — General purpose digital
input/output pin.
I
DCD — Data Carrier Detect input for USART.
-
O
CT16B0_MAT2 — Match output 2 for 16-bit
timer 0.
-
I/O
I/O
SCK1 — Serial clock for SSP1.
PIO1_16/RI/
-
48 A2
I; PU
PIO1_16 — General purpose digital
CT16B0_CAP0
input/output pin.
-
-
I
I
RI — Ring Indicator input for USART.
CT16B0_CAP0 — Capture input 0 for 16-bit
timer 0.
[3]
[3]
[3]
[3]
[3]
PIO1_19/DTR/SSEL1
PIO1_20/DSR/SCK1
PIO1_21/DCD/MISO1
PIO1_22/RI/MOSI1
1
-
2
B1
I; PU
I/O
PIO1_19 — General purpose digital
input/output pin.
-
O
DTR — Data Terminal Ready output for USART.
SSEL1 — Slave select for SSP1.
-
I/O
I/O
13 H1
26 G8
38 A7
18 H4
I; PU
PIO1_20 — General purpose digital
input/output pin.
-
I
DSR — Data Set Ready input for USART.
SCK1 — Serial clock for SSP1.
-
I/O
I/O
-
I; PU
PIO1_21 — General purpose digital
input/output pin.
-
I
DCD — Data Carrier Detect input for USART.
MISO1 — Master In Slave Out for SSP1.
-
I/O
I/O
-
I; PU
PIO1_22 — General purpose digital
input/output pin.
-
I
RI — Ring Indicator input for USART.
MOSI1 — Master Out Slave In for SSP1.
-
I/O
I/O
PIO1_23/CT16B1_MAT1/
SSEL1
-
I; PU
PIO1_23 — General purpose digital
input/output pin.
-
-
O
CT16B1_MAT1 — Match output 1 for 16-bit
timer 1.
I/O
SSEL1 — Slave select for SSP1.
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Table 3.
Symbol
Pin description
Reset Type
Description
state
[1]
[3]
[3]
[3]
PIO1_24/CT32B0_MAT0
PIO1_25/CT32B0_MAT1
-
-
-
21 G6
I; PU
I/O
O
PIO1_24 — General purpose digital
input/output pin.
-
CT32B0_MAT0 — Match output 0 for 32-bit
timer 0.
1
A1
I; PU
I/O
O
PIO1_25 — General purpose digital
input/output pin.
-
CT32B0_MAT1 — Match output 1 for 32-bit
timer 0.
PIO1_26/CT32B0_MAT2/
RXD
11 G2
12 G1
24 H7
I; PU
-
I/O
O
PIO1_26 — General purpose digital
input/output pin.
CT32B0_MAT2 — Match output 2 for 32-bit
timer 0.
-
I
RXD — Receiver input for USART.
[3]
[3]
PIO1_27/CT32B0_MAT3/
TXD
-
-
I; PU
I/O
PIO1_27 — General purpose digital
input/output pin.
-
O
CT32B0_MAT3 — Match output 3 for 32-bit
timer 0.
-
O
TXD — Transmitter output for USART.
PIO1_28/CT32B0_CAP0/
SCLK
I; PU
I/O
PIO1_28 — General purpose digital
input/output pin.
-
I
CT32B0_CAP0 — Capture input 0 for 32-bit
timer 0.
-
I/O
I/O
SCLK — Serial clock input/output for USART in
synchronous mode.
[3]
[3]
PIO1_29/SCK0/
CT32B0_CAP1
-
-
31 D7
I; PU
PIO1_29 — General purpose digital
input/output pin.
-
-
I/O
I
SCK0 — Serial clock for SSP0.
CT32B0_CAP1 — Capture input 1 for 32-bit
timer 0.
PIO1_31
25
-
I; PU
I/O
PIO1_31 — General purpose digital
input/output pin.
[7]
[7]
[8]
USB_DM
USB_DP
XTALIN
13 19 G5
14 20 H5
F
F
-
-
-
-
USB_DM — USB bidirectional D line.
USB_DP — USB bidirectional D+ line.
4
6
D1
Input to the oscillator circuit and internal clock
generator circuits. Input voltage must not
exceed 1.8 V.
[8]
XTALOUT
VDD
5
7
E1
-
-
-
-
Output from the oscillator amplifier.
6; 8;
29 44 E2
B4,
Supply voltage to the internal regulator, the
external rail, and the ADC. Also used as the
ADC reference voltage.
VSS
33 5;
B5,
-
-
Ground.
41 D2
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[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;
F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.
[2] See Figure 30 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to
reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down
mode.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 29).
[4] I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 29);
includes high-current output driver.
[6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 29); includes digital
input glitch filter.
[7] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode
only). This pad is not 5 V tolerant.
[8] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
To assign a peripheral function to a port, program the FUNC bits in the port pin’s IOCON
register with this function. The user must ensure that the assignment of a function to a port
pin is unambiguous. Only the debug functions for JTAG and SWD are selected by default
in their corresponding IOCON registers. All other functions must be programmed in the
IOCON block before they can be used. For details see the LPC11Uxx user manual.
Table 4.
Multiplexing of peripheral functions
Type Default Available on ports
HVQFN33/LQFP48/TFBGA48 LQFP48/TFBGA48
Peripheral Function
TFBGA48
USART
RXD
I
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
PIO0_18
PIO0_19
PIO0_7
PIO0_17
PIO1_13
-
-
PIO1_14
PIO1_13
-
PIO1_26
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TXD
O
-
PIO1_27
CTS
I
-
-
RTS
O
-
-
-
DTR
O
PIO1_19
-
-
-
DSR
I
PIO1_14
PIO1_21
PIO1_16
PIO1_28
PIO1_29
-
PIO1_20
DCD
I
PIO1_15
-
-
RI
I
PIO1_22
-
SCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PIO0_17
PIO0_6
PIO0_2
PIO0_8
PIO0_9
PIO1_15
PIO1_19
PIO0_22
PIO0_21
PIO0_2
PIO0_8
PIO0_9
PIO0_10
SSP0
SCK0
PIO0_10
SSEL0
MISO0
MOSI0
SCK1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SSP1
-
PIO1_20
PIO1_23
PIO1_21
PIO1_22
PIO1_16
PIO1_13
PIO1_14
-
SSEL1
MISO1
MOSI1
CT16B0_CAP0
CT16B0_MAT0
CT16B0_MAT1
CT16B0_MAT2
-
-
-
CT16B0
-
O
-
O
-
O
PIO1_15
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Table 4.
Multiplexing of peripheral functions
Peripheral Function
Type Default Available on ports
HVQFN33/LQFP48/TFBGA48 LQFP48/TFBGA48
TFBGA48
CT16B1
CT32B0
CT16B1_CAP0
I
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
yes
yes
yes
yes
yes
yes
yes
PIO0_20
PIO0_21
PIO0_22
PIO0_17
PIO1_29
PIO0_18
PIO0_19
PIO0_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CT16B1_MAT0
CT16B1_MAT1
CT32B0_CAP0
CT32B0_CAP1
CT32B0_MAT0
CT32B0_MAT1
CT32B0_MAT2
CT32B0_MAT3
CT32B1_CAP0
CT32B1_CAP1
CT32B1_MAT0
CT32B1_MAT1
CT32B1_MAT2
CT32B1_MAT3
AD0
O
O
I
-
-
PIO1_23
-
PIO1_28
-
I
-
-
O
O
O
O
I
PIO1_24
-
PIO1_25
-
PIO1_26
-
PIO0_11
PIO0_12
-
PIO1_27
-
CT32B1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PIO1_5
O
O
O
O
I
PIO0_13
PIO0_14
PIO0_15
PIO0_16
PIO0_11
PIO0_12
PIO0_13
PIO0_14
PIO0_15
PIO0_16
PIO0_22
PIO0_23
PIO0_3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADC
AD1
I
AD2
I
AD3
I
AD4
I
AD5
I
AD6
I
AD7
I
USB
USB_VBUS
USB_FTOGGLE
USB_CONNECT
CLKOUT
I
O
O
O
I
PIO0_1
PIO0_6
CLKOUT
JTAG
PIO0_1
TDI
PIO0_11
PIO0_12
PIO0_13
PIO0_14
PIO0_10
PIO0_10
PIO0_15
TMS
I
TDO
O
I
TRST
TCK
I
SWD
SWCLK
I
SWDIO
I/O
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7. Functional description
7.1 On-chip flash programming memory
The LPC11U1x contain up to 32 kB on-chip flash program memory. The flash can be
programmed using In-System Programming (ISP) or In-Application Programming (IAP)
via the on-chip boot loader software.
7.2 SRAM
The LPC11U1x contain a total of 6 kB on-chip static RAM memory.
7.3 On-chip ROM
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (APIs):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
programming
• Power profiles for configuring power consumption and PLL settings
• 32-bit integer division routines
7.4 Memory map
The LPC11U1x incorporates several distinct memory regions, shown in the following
figures. Figure 5 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
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LPC11U12/13/14
4 GB
0xFFFF FFFF
reserved
0xE010 0000
0xE000 0000
private peripheral bus
reserved
APB peripherals
0x4008 0000
0x5000 4000
0x5000 0000
GPIO
25 - 31 reserved
0x4006 4000
GPIO GROUP1 interrupt
GPIO GROUP0 interrupt
24
23
22
0x4006 0000
0x4005 C000
reserved
0x4008 4000
SSP1
USB
0x4005 8000
0x4004 C000
0x4008 0000
0x4000 0000
20 - 21 reserved
APB peripherals
1 GB
GPIO pin interrupt
19
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
reserved
system control
IOCON
18
17
0x2000 4800
SSP0
2 kB USB RAM
reserved
16
15
0x2000 4000
0x2000 0000
flash controller
0x4003 C000
0x4003 8000
0.5 GB
14
PMU
reserved
10 - 13 reserved
0x1FFF 4000
0x1FFF 0000
0x4002 8000
0x4002 4000
0x4002 0000
16 kB boot ROM
reserved
reserved
9
8
7
6
5
4
3
2
reserved
ADC
0x4001 C000
0x4001 8000
32-bit counter/timer 1
32-bit counter/timer 0
16-bit counter/timer 1
16-bit counter/timer 0
USART/SMART CARD
WWDT
0x1000 1000
0x1000 0000
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
4 kB SRAM
reserved
0x0000 8000
0x0000 6000
1
0
0x4000 4000
0x4000 0000
32 kB on-chip flash (LPC11U14)
24 kB on-chip flash (LPC11U13)
2
I C-bus
0x0000 00C0
0x0000 4000
0x0000 0000
active interrupt vectors
16 kB on-chip flash (LPC11U12)
0x0000 0000
0 GB
002aaf891
Fig 5. LPC11U1x memory map
7.5 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.5.1 Features
• Controls system exceptions and peripheral interrupts.
• In the LPC11U1x, the NVIC supports 24 vectored interrupts.
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• Four programmable interrupt priority levels, with hardware priority level masking.
• Software interrupt generation.
7.5.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
7.6 IOCON block
The IOCON block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupts being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
7.6.1 Features
• Programmable pull-up, pull-down, or repeater mode.
• All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (VDD = 3.3 V) if their
pull-up resistor is enabled.
• Programmable pseudo open-drain mode.
• Programmable 10-ns glitch filter on pins PIO0_22, PIO0_23, and PIO0_11 to
PIO0_16. The glitch filter is turned off by default.
• Programmable hysteresis.
• Programmable input inverter.
7.7 General Purpose Input/Output GPIO
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs
can be set or cleared in one write operation.
LPC11U1x use accelerated GPIO functions:
• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
• Entire port value can be written in one instruction.
Any GPIO pin providing a digital function can be programmed to generate an interrupt on
a level, a rising or falling edge, or both.
The GPIO block consists of three parts:
1. The GPIO ports.
2. The GPIO pin interrupt block to control eight GPIO pins selected as pin interrupts.
3. Two GPIO group interrupt blocks to control two combined interrupts from all GPIO
pins.
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7.7.1 Features
• GPIO pins can be configured as input or output by software.
• All GPIO pins default to inputs with interrupt disabled at reset.
• Pin registers allow pins to be sensed and set individually.
• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request.
• Port interrupts can be triggered by any pin or pins in each port.
7.8 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports
hot-plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC11U1x USB interface consists of a full-speed device controller with on-chip PHY
for device functions.
Remark: Configure the LPC11U1x in default power mode with the power profiles before
using the USB (see Section 7.16.5.1). Do not use the USB with the part in performance,
efficiency, or low-power mode.
7.8.1 Full-speed USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, and endpoint buffer memory. The
serial interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
7.8.1.1 Features
• Dedicated USB PLL available.
• Fully compliant with USB 2.0 specification (full speed).
• Supports 10 physical (5 logical) endpoints including one control endpoint.
• Single and double buffering supported.
• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.
• Supports wake-up from Deep-sleep mode and Power-down mode on USB activity
and remote wake-up.
• Supports SoftConnect.
7.9 USART
The LPC11U1x contains one USART.
The USART includes full modem control, support for synchronous mode, and a smart
card interface. The RS-485/9-bit mode allows both software address detection and
automatic address detection using 9-bit mode.
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The USART uses a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.9.1 Features
• Maximum USART data bit rate of 3.125 Mbit/s.
• 16-byte receive and transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
• Support for RS-485/9-bit mode.
• Support for modem control.
• Support for synchronous mode.
• Includes smart card interface.
7.10 SSP serial I/O controller
The SSP controllers are capable of operation on a SSP, 4-wire SSI, or Microwire bus. It
can interact with multiple masters and slaves on the bus. Only a single master and a
single slave can communicate on the bus during a given data transfer. The SSP supports
full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
7.10.1 Features
• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
7.11 I2C-bus serial I/O controller
The LPC11U1x contain one I2C-bus controller.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
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7.11.1 Features
• The I2C-interface is an I2C-bus compliant interface with open-drain pins. The I2C-bus
interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• The I2C-bus controller supports multiple address recognition and a bus monitor mode.
7.12 10-bit ADC
The LPC11U1x contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
7.12.1 Features
• 10-bit successive approximation ADC.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range 0 V to VDD
.
• 10-bit conversion time 2.44 s (up to 400 kSamples/s).
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or timer match signal.
• Individual result registers for each ADC channel to reduce interrupt overhead.
7.13 General purpose external event counter/timers
The LPC11U1x includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
7.13.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt.
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• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
7.14 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.15 Windowed WatchDog Timer (WWDT)
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.15.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect feed sequence causes reset or interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
• The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated
watchdog oscillator (WDO). This gives a wide range of potential timing choices of
watchdog operation under different power conditions.
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7.16 Clocking and power control
7.16.1 Integrated oscillators
The LPC11U1x include three independent oscillators. These are the system oscillator, the
Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for
more than one purpose as required in a particular application.
Following reset, the LPC11U1x will operate from the internal RC oscillator until switched
by software. This allows systems to operate without any external crystal and the
bootloader code to operate at a known frequency.
See Figure 6 for an overview of the LPC11U1x clock generation.
LPC11U1X
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CPU, system control,
PMU
system clock
n
SYSTEM CLOCK
DIVIDER
memories,
peripheral clocks
SYSAHBCLKCTRLn
(AHB clock enable)
IRC oscillator
main clock
SSP0 PERIPHERAL
CLOCK DIVIDER
SSP0
UART
SSP1
watchdog oscillator
USART PERIPHERAL
CLOCK DIVIDER
MAINCLKSEL
(main clock select)
SSP1 PERIPHERAL
CLOCK DIVIDER
IRC oscillator
SYSTEM PLL
system oscillator
SYSPLLCLKSEL
(system PLL clock select)
USB PLL
system oscillator
USB 48 MHz CLOCK
DIVIDER
USB
USBPLLCLKSEL
(USB clock select)
USBUEN
(USB clock update enable)
IRC oscillator
system oscillator
watchdog oscillator
CLKOUT PIN CLOCK
DIVIDER
CLKOUT pin
CLKOUTUEN
(CLKOUT update enable)
IRC oscillator
WDT
watchdog oscillator
WDCLKSEL
(WDT clock select)
002aaf892
Fig 6. LPC11U1x clocking generation block diagram
7.16.1.1 Internal RC oscillator
The IRC may be used as the clock source for the WDT, and/or as the clock that drives the
system PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz.
Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC11U1x
use the IRC as the clock source. Software may later switch to one of the other available
clock sources.
LPC11U1X
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7.16.1.2 System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using
the PLL. On the LPC11U1x, the system oscillator must be used to provide the clock
source to USB.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
7.16.1.3 Watchdog oscillator
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and
temperature is 40 % (see also Table 13).
7.16.2 System PLL and USB PLL
The LPC11U1x contain a system PLL and a dedicated PLL for generating the 48 MHz
USB clock. The system and USB PLLs are identical.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The output
divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output
frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.
The PLL settling time is 100 s.
7.16.3 Clock output
The LPC11U1x features a clock output function that routes the IRC oscillator, the system
oscillator, the watchdog oscillator, or the main clock to an output pin.
7.16.4 Wake-up process
The LPC11U1x begin operation at power-up and when awakened from Deep power-down
mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation
to resume quickly. If the main oscillator or the PLL is needed by the application, software
will need to enable these features and wait for them to stabilize before they are used as a
clock source.
7.16.5 Power control
The LPC11U1x support a variety of power control features. There are four special modes
of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode. The CPU clock rate may also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
value. This allows a trade-off of power versus processing speed based on application
requirements. In addition, a register is provided for shutting down the clocks to individual
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on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic
power use in any peripherals that are not required for the application. Selected
peripherals have their own clock divider which provides even better power control.
7.16.5.1 Power profiles
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC11U1x for one of the following power modes:
• Default mode corresponding to power configuration after reset.
• CPU performance mode corresponding to optimized processing capability.
• Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
• Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
Remark: When using the USB, configure the LPC11U1x in Default mode.
7.16.5.2 Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.16.5.3 Deep-sleep mode
In Deep-sleep mode, the LPC11U1x is in Sleep-mode and all peripheral clocks and all
clock sources are off with the exception of the IRC. The IRC output is disabled unless the
IRC is selected as input to the watchdog timer. In addition all analog blocks are shut down
and the flash is in stand-by mode. In Deep-sleep mode, the user has the option to keep
the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD
protection.
The LPC11U1x can wake up from Deep-sleep mode via reset, selected GPIO pins, a
watchdog timer interrupt, or an interrupt generating USB port activity.
Deep-sleep mode saves power and allows for short wake-up times.
7.16.5.4 Power-down mode
In Power-down mode, the LPC11U1x is in Sleep-mode and all peripheral clocks and all
clock sources are off with the exception of watchdog oscillator if selected. In addition all
analog blocks and the flash are shut down. In Power-down mode, the user has the option
to keep the BOD circuit running for BOD protection.
The LPC11U1x can wake up from Power-down mode via reset, selected GPIO pins, a
watchdog timer interrupt, or an interrupt generating USB port activity.
LPC11U1X
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Power-down mode reduces power consumption compared to Deep-sleep mode at the
expense of longer wake-up times.
7.16.5.5 Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip with the exception of the
WAKEUP pin. The LPC11U1x can wake up from Deep power-down mode via the
WAKEUP pin.
The LPC11U1x can be prevented from entering Deep power-down mode by setting a lock
bit in the PMU block. Locking out Deep power-down mode enables the user to always
keep the watchdog timer or the BOD running.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from
floating while in Deep power-down mode.
7.16.6 System control
7.16.6.1 Reset
Reset has four sources on the LPC11U1x: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip reset by any source, once the operating voltage attains
a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
An external pull-up resistor is required on the RESET pin if Deep power-down mode is
used.
7.16.6.2 Brownout detection
The LPC11U1x includes four levels for monitoring the voltage on the VDD pin. If this
voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to
the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading
a dedicated status register. Four additional threshold levels can be selected to cause a
forced reset of the chip.
7.16.6.3 Code security (Code Read Protection - CRP)
This feature of the LPC11U1x allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)
and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by
programming a specific pattern into a dedicated flash location. IAP commands are not
affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details see the LPC11U1x user manual.
There are three levels of Code Read Protection:
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1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the USART.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC11U1x user manual.
7.16.6.4 APB interface
The APB peripherals are located on one APB bus.
7.16.6.5 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the ROM.
7.16.6.6 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
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7.17 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is
configured to support up to four breakpoints and two watch points.
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the
LPC11U1x is in reset.
To perform boundary scan testing, follow these steps:
1. Erase any user code residing in flash.
2. Power up the part with the RESET pin pulled HIGH externally.
3. Wait for at least 250 s.
4. Pull the RESET pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan operations are completed, assert the TRST pin to enable the
SWD debug mode and release the RESET pin (pull HIGH).
Remark: The JTAG interface cannot be used for debug purposes.
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8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
supply voltage (core and
external rail)
1.8
3.6
V
[2]
VI
input voltage
5 V tolerant I/O pins; only valid
when the VDD supply voltage is
present
0.5
+5.5
V
[3]
[3]
IDD
supply current
per supply pin
-
-
-
100
100
100
mA
mA
mA
ISS
ground current
I/O latch-up current
per ground pin
(0.5VDD) < VI < (1.5VDD);
Tj < 125 C
Ilatch
[4]
[5]
Tstg
storage temperature
non-operating
65
+150
150
1.5
C
C
W
Tj(max)
Ptot(pack)
maximum junction temperature
-
-
total power dissipation (per
package)
based on package heat transfer, not
device power consumption
VESD
electrostatic discharge voltage human body model; all pins
6500
+6500
V
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2] Including voltage on outputs in 3-state mode.
[3] The peak current is limited to 25 times the corresponding maximum current.
[4] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined
based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.
[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
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9. Static characteristics
Table 6.
Static characteristics
T
amb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
[2]
VDD
supply voltage (core
and external rail)
1.8
3.3
3.6
V
IDD
supply current
Active mode; VDD = 3.3 V;
Tamb = 25 C; code
while(1){}
executed from flash;
system clock = 12 MHz
[3][4][5]
[6][7][8]
-
-
-
2
7
1
-
-
-
mA
mA
mA
[4][5][6]
[7][8][9]
system clock = 50 MHz
[3][4][5]
[6][7][8]
Sleep mode;
VDD = 3.3 V; Tamb = 25 C;
system clock = 12 MHz
[4][7]
Deep-sleep mode; VDD = 3.3 V;
Tamb = 25 C
-
-
-
360
2
-
-
-
A
A
nA
Power-down mode; VDD = 3.3 V;
Tamb = 25 C
[10]
Deep power-down mode;
220
VDD = 3.3 V; Tamb = 25 C
Standard port pins, RESET
IIL
LOW-level input current VI = 0 V; on-chip pull-up resistor
disabled
-
0.5
0.5
0.5
-
10
10
10
5.0
nA
nA
nA
V
IIH
IOZ
VI
HIGH-level input
current
VI = VDD; on-chip pull-down resistor
disabled
-
OFF-state output
current
VO = 0 V; VO = VDD; on-chip
pull-up/down resistors disabled
-
[11][12]
[13]
input voltage
pin configured to provide a digital
function
0
VO
output voltage
output active
0
-
-
VDD
-
V
V
VIH
HIGH-level input
voltage
0.7VDD
VIL
LOW-level input voltage
hysteresis voltage
-
-
0.3VDD
V
Vhys
VOH
-
0.4
-
V
HIGH-level output
voltage
2.0 V VDD 3.6 V; IOH = 4 mA
1.8 V VDD < 2.0 V; IOH = 3 mA
2.0 V VDD 3.6 V; IOL = 4 mA
1.8 V VDD < 2.0 V; IOL = 3 mA
VOH = VDD 0.4 V;
VDD 0.4
-
-
-
-
-
-
V
VDD 0.4
-
V
VOL
LOW-level output
voltage
-
0.4
0.4
-
V
-
V
IOH
HIGH-level output
current
4
mA
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
3
-
-
mA
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Table 6.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
IOL
LOW-level output
current
VOL = 0.4 V
4
-
-
mA
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
3
-
-
-
-
mA
mA
[14]
[14]
IOHS
IOLS
HIGH-level short-circuit VOH = 0 V
output current
45
LOW-level short-circuit VOL = VDD
output current
-
-
50
mA
Ipd
Ipu
pull-down current
pull-up current
VI = 5 V
VI = 0 V;
10
50
150
A
A
15
50
85
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
10
50
85
A
A
VDD < VI < 5 V
0
0
0
High-drive output pin (PIO0_7)
IIL
LOW-level input current VI = 0 V; on-chip pull-up resistor
disabled
-
0.5
0.5
0.5
-
10
10
10
5.0
nA
nA
nA
V
IIH
IOZ
VI
HIGH-level input
current
VI = VDD; on-chip pull-down resistor
disabled
-
OFF-state output
current
VO = 0 V; VO = VDD; on-chip
pull-up/down resistors disabled
-
[11][12]
[13]
input voltage
pin configured to provide a digital
function
0
VO
output voltage
output active
0
-
-
VDD
-
V
V
VIH
HIGH-level input
voltage
0.7VDD
VIL
LOW-level input voltage
hysteresis voltage
-
-
-
-
-
-
-
-
0.3VDD
V
Vhys
VOH
0.4
-
V
HIGH-level output
voltage
2.5 V VDD 3.6 V; IOH = 20 mA
1.8 V VDD < 2.5 V; IOH = 12 mA
2.0 V VDD 3.6 V; IOL = 4 mA
1.8 V VDD < 2.0 V; IOL = 3 mA
VDD 0.4
-
V
VDD 0.4
-
V
VOL
LOW-level output
voltage
-
0.4
0.4
-
V
-
V
IOH
HIGH-level output
current
VOH = VDD 0.4 V;
2.5 V VDD 3.6 V
20
mA
1.8 V VDD < 2.5 V
VOL = 0.4 V
12
4
-
-
-
-
mA
mA
IOL
LOW-level output
current
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
3
-
-
-
-
mA
mA
[14]
IOLS
LOW-level short-circuit VOL = VDD
output current
50
Ipd
Ipu
pull-down current
pull-up current
VI = 5 V
VI = 0 V
10
50
150
A
A
15
50
85
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
10
50
85
A
A
VDD < VI < 5 V
0
0
0
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Table 6.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
I2C-bus pins (PIO0_4 and PIO0_5)
VIH
HIGH-level input
voltage
0.7VDD
-
-
V
VIL
LOW-level input voltage
hysteresis voltage
-
-
0.3VDD
V
Vhys
IOL
-
0.05VDD
-
-
-
V
LOW-level output
current
VOL = 0.4 V; I2C-bus pins configured
as standard mode pins
3.5
mA
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
VOL = 0.4 V; I2C-bus pins configured
as Fast-mode Plus pins
3
-
-
-
-
IOL
LOW-level output
current
20
mA
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
VI = VDD
16
-
-
-
[15]
ILI
input leakage current
2
4
A
A
VI = 5 V
-
10
22
Oscillator pins
Vi(xtal)
crystal input voltage
0.5
0.5
1.8
1.8
1.95
1.95
V
V
Vo(xtal)
USB pins
IOZ
crystal output voltage
[2]
OFF-state output
current
0 V < VI < 3.3 V
-
-
10
A
[2]
[2]
VBUS
VDI
bus supply voltage
-
-
-
5.25
-
V
V
differential input
(D+) (D)
0.2
sensitivity voltage
[2]
[2]
VCM
differential common
mode voltage range
includes VDI range
0.8
0.8
-
-
2.5
2.0
V
V
Vth(rs)se single-ended receiver
switching threshold
voltage
[2]
[2]
VOL
LOW-level output
voltage
for low-/full-speed;
RL of 1.5 k to 3.6 V
-
-
-
0.18
3.5
V
V
VOH
HIGH-level output
voltage
driven; for low-/full-speed;
RL of 15 k to GND
2.8
[2]
Ctrans
ZDRV
transceiver capacitance pin to GND
-
-
-
20
pF
[16][2]
driver output
with 33 series resistor; steady state
drive
36
44.1
impedance for driver
which is not high-speed
capable
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] For USB operation 3.0 V VDD((3V3) 3.6 V. Guaranteed by design.
[3] IRC enabled; system oscillator disabled; system PLL disabled.
[4]
[5] BOD disabled.
[6] All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to USART, SSP0/1 disabled in the syscon block.
IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
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[7] USB_DP and USB_DM pulled LOW externally.
[8] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
[9] IRC disabled; system oscillator enabled; system PLL enabled.
[10] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode.
[11] Including voltage on outputs in 3-state mode.
[12] VDD supply voltage must be present.
[13] 3-state outputs go into 3-state mode in Deep power-down mode.
[14] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[15] To VSS
.
[16] Includes external resistors of 33 1 % on USB_DP and USB_DM.
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Table 7.
ADC static characteristics
Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V.
Symbol
VIA
Parameter
Conditions
Min
Typ
Max
VDD
1
Unit
V
analog input voltage
analog input capacitance
differential linearity error
integral non-linearity
offset error
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Cia
pF
[1][2]
[3]
ED
1
LSB
LSB
LSB
%
EL(adj)
EO
1.5
3.5
0.6
4
[4]
[5]
EG
gain error
[6]
ET
absolute error
LSB
k
Rvsi
voltage source interface
resistance
40
[7][8]
Ri
input resistance
-
-
2.5
M
[1] The ADC is monotonic, there are no missing codes.
[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 7.
[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 7.
[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 7.
[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 7.
[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 7.
[7] Tamb = 25 C; maximum sampling frequency fs = 400kSamples/s and analog input capacitance Cia = 1 pF.
[8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs Cia).
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offset
error
gain
error
E
E
O
G
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
4
3
2
1
0
(5)
(4)
(3)
1 LSB
(ideal)
1018 1019 1020 1021 1022 1023 1024
1
2
3
4
5
6
7
V
(LSB
)
ideal
IA
offset error
E
O
V
− V
SS
DD
1 LSB =
1024
002aaf426
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 7. ADC characteristics
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9.1 BOD static characteristics
Table 8.
BOD static characteristics[1]
Tamb = 25 C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Vth
threshold voltage interrupt level 0
assertion
-
-
1.65
1.80
-
-
V
V
de-assertion
interrupt level 1
assertion
-
-
2.22
2.35
-
-
V
V
de-assertion
interrupt level 2
assertion
-
-
2.52
2.66
-
-
V
V
de-assertion
interrupt level 3
assertion
-
-
2.80
2.90
-
-
V
V
de-assertion
reset level 0
assertion
-
-
1.46
1.63
-
-
V
V
de-assertion
reset level 1
assertion
-
-
2.06
2.15
-
-
V
V
de-assertion
reset level 2
assertion
-
-
2.35
2.43
-
-
V
V
de-assertion
reset level 3
assertion
-
-
2.63
2.71
-
-
V
V
de-assertion
[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see
LPC11U1x user manual.
9.2 Power consumption
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see LPC11U1x user manual):
• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
• Configure GPIO pins as outputs using the GPIOnDIR registers.
• Write 0 to all GPIOnDATA registers to drive the outputs LOW.
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002aag749
9
6
3
0
(2)
48 MHz
I
DD
(mA)
(2)
36 MHz
(2)
24 MHz
(1)
12 MHz
1.8
2.4
3.0
3.6
V
(V)
DD
Conditions: Tamb = 25 C; Active mode entered executing code while(1){} from flash;
internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the
SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode; USB_DP and
USB_DM pulled LOW externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 8. Typical supply current versus regulator supply voltage VDD in active mode
002aag750
9
(2)
48 MHz
36 MHz
I
DD
(mA)
6
3
0
(2)
(2)
(1)
24 MHz
12 MHz
-40
-15
10
35
60
85
temperature (°C)
Conditions: VDD = 3.3 V; Active mode entered executing code while(1){} from flash; internal
pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL
register; all peripheral clocks disabled; low-current mode; USB_DP and USB_DM pulled LOW
externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 9. Typical supply current versus temperature in Active mode
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002aag751
4
3
2
1
0
I
DD
(mA)
(2)
48 MHz
(2)
36 MHz
(2)
24 MHz
(1)
12 MHz
-40
-15
10
35
60
85
temperature (°C)
Conditions: VDD = 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; BOD
disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled;
low-current mode; USB_DP and USB_DM pulled LOW externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 10. Typical supply current versus temperature in Sleep mode
002aag745
385
I
DD
(μA)
375
V
V
= 3.6 V
= 3.3 V
DD
DD
365
355
345
V
V
= 2.0 V
= 1.8 V
DD
DD
-40
-15
10
35
60
85
temperature (°C)
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG
register; USB_DP and USB_DM pulled LOW externally.
Fig 11. Typical supply current versus temperature in Deep-sleep mode
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002aag746
20
I
DD
V
= 3.6 V, 3.3 V
DD
(μA)
V
= 2.0 V
= 1.8 V
DD
V
DD
15
10
5
0
-40
-15
10
35
60
85
temperature (°C)
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG
register; USB_DP and USB_DM pulled LOW externally.
Fig 12. Typical supply current versus temperature in Power-down mode
002aag747
0.8
I
DD
V
DD
V
DD
V
DD
V
DD
= 3.6 V
= 3.3 V
= 2.0 V
= 1.8 V
(μA)
0.6
0.4
0.2
0
-40
-15
10
35
60
85
temperature (°C)
Fig 13. Typical supply current versus temperature in Deep power-down mode
9.3 Peripheral power consumption
The supply current per peripheral is measured as the difference in supply current between
the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG
and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both
registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless
noted otherwise, the system oscillator and PLL are running in both measurements.
The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.
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Table 9.
Power consumption for individual analog and digital blocks
Peripheral
Typical supply current in
mA
Notes
n/a
12 MHz 48 MHz
IRC
0.27
-
-
-
-
-
-
System oscillator running; PLL off; independent
of main clock frequency.
System oscillator 0.22
at 12 MHz
IRC running; PLL off; independent of main clock
frequency.
Watchdog
oscillator at
500 kHz/2
0.004
System oscillator running; PLL off; independent
of main clock frequency.
BOD
0.051
-
-
Independent of main clock frequency.
Main PLL
ADC
-
-
-
0.21
0.08
0.12
-
-
-
0.29
0.47
CLKOUT
Main clock divided by 4 in the CLKOUTDIV
register.
CT16B0
CT16B1
CT32B0
CT32B1
GPIO
-
-
-
-
-
0.02
0.02
0.02
0.02
0.23
0.06
0.06
0.07
0.06
0.88
-
-
-
-
GPIO pins configured as outputs and set to
LOW. Direction and pin state are maintained if
the GPIO is disabled in the SYSAHBCLKCFG
register.
IOCONFIG
I2C
-
-
-
-
-
-
-
0.03
0.04
0.04
0.12
0.12
0.22
0.02
0.10
0.13
0.15
0.45
0.45
0.82
0.06
-
-
-
-
-
-
ROM
SPI0
SPI1
UART
WWDT
Main clock selected as clock source for the
WDT.
USB
-
-
1.2
-
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9.4 Electrical pin characteristics
002aae990
3.6
V
(V)
OH
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2
0
10
20
30
40
50
60
I
(mA)
OH
Conditions: VDD = 3.3 V; on pin PIO0_7.
Fig 14. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level
output current IOH
.
002aaf019
60
I
T = 85 °C
25 °C
−40 °C
OL
(mA)
40
20
0
0
0.2
0.4
0.6
V
(V)
OL
Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.
Fig 15. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus
LOW-level output voltage VOL
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002aae991
15
I
OL
T = 85 °C
25 °C
−40 °C
(mA)
10
5
0
0
0.2
0.4
0.6
V
(V)
OL
Conditions: VDD = 3.3 V; standard port pins and PIO0_7.
Fig 16. Typical LOW-level output current IOL versus LOW-level output voltage VOL
002aae992
3.6
V
OH
(V)
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2
0
8
16
24
I
(mA)
OH
Conditions: VDD = 3.3 V; standard port pins.
Fig 17. Typical HIGH-level output voltage VOH versus HIGH-level output source current
IOH
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002aae988
10
I
pu
(μA)
−10
−30
−50
−70
T = 85 °C
25 °C
−40 °C
0
1
2
3
4
5
V (V)
I
Conditions: VDD = 3.3 V; standard port pins.
Fig 18. Typical pull-up current Ipu versus input voltage VI
002aae989
80
T = 85 °C
I
pd
25 °C
(μA)
−40 °C
60
40
20
0
0
1
2
3
4
5
V (V)
I
Conditions: VDD = 3.3 V; standard port pins.
Fig 19. Typical pull-down current Ipd versus input voltage VI
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10. Dynamic characteristics
10.1 Flash memory
Table 10. Flash characteristics
amb = 40 C to +85 C, unless otherwise specified.
T
Symbol
Nendu
tret
Parameter
endurance
Conditions
Min
Typ
Max
Unit
[1]
10000 100000
-
cycles
years
years
ms
retention time
powered
10
20
95
-
-
unpowered
-
-
ter
erase time
sector or multiple
100
105
consecutive sectors
[2]
tprog
programming time
0.95
1
1.05
ms
[1] Number of program/erase cycles.
[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash
in blocks of 256 bytes.
10.2 External clock
Table 11. Dynamic characteristic: external clock
Tamb = 40 C to +85 C; VDD over specified ranges.[1]
Symbol Parameter
Conditions
Min
Typ[2] Max
Unit
MHz
ns
fosc
oscillator frequency
1
-
-
-
-
-
-
25
Tcy(clk)
tCHCX
tCLCX
tCLCH
tCHCL
clock cycle time
clock HIGH time
clock LOW time
clock rise time
clock fall time
40
1000
Tcy(clk) 0.4
-
ns
Tcy(clk) 0.4
-
ns
-
-
5
5
ns
ns
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
t
CHCX
t
t
t
CHCL
CLCX
CLCH
T
cy(clk)
002aaa907
Fig 20. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
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10.3 Internal oscillators
Table 12. Dynamic characteristics: IRC
Tamb = 40 C to +85 C; 2.7 V VDD 3.6 V[1].
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
fosc(RC)
internal RC oscillator
frequency
-
11.88
12
12.12
MHz
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
002aaf403
12.15
f
(MHz)
VDD = 3.6 V
3.3 V
3.0 V
2.7 V
12.05
2.4 V
2.0 V
11.95
11.85
−40
−15
10
35
60
85
temperature (°C)
Conditions: Frequency values are typical values. 12 MHz 1 % accuracy is guaranteed for
2.7 V VDD 3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the IRC to
fall outside the 12 MHz 1 % accuracy specification for voltages below 2.7 V.
Fig 21. Internal RC oscillator frequency versus temperature
Table 13. Dynamic characteristics: Watchdog oscillator
Symbol
Parameter
Conditions
Min Typ[1] Max Unit
[2][3]
[2][3]
fosc(int)
internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1
-
7.8
-
kHz
frequency
in the WDTOSCCTRL register;
DIVSEL = 0x00, FREQSEL = 0xF
in the WDTOSCCTRL register
-
1700
-
kHz
[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
[2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %.
[3] See the LPC11U1x user manual.
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10.4 I/O pins
Table 14. Dynamic characteristics: I/O pins[1]
Tamb = 40 C to +85 C; 3.0 V VDD 3.6 V.
Symbol Parameter Conditions
Min
3.0
2.5
Typ
Max
5.0
Unit
ns
tr
tf
rise time
fall time
pin configured as output
pin configured as output
-
-
5.0
ns
[1] Applies to standard port pins and RESET pin.
10.5 I2C-bus
Table 15. Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +85 C.[2]
Symbol
Parameter
Conditions
Min
Max
100
400
1
Unit
fSCL
SCL clock
frequency
Standard-mode
Fast-mode
0
0
0
-
kHz
kHz
MHz
ns
Fast-mode Plus
[4][5][6][7]
tf
fall time
of both SDA and SCL
signals
300
Standard-mode
Fast-mode
20 + 0.1 Cb
300
ns
ns
s
s
s
s
s
s
s
s
s
ns
ns
ns
Fast-mode Plus
Standard-mode
Fast-mode
-
120
tLOW
LOW period of the
SCL clock
4.7
1.3
0.5
4.0
0.6
0.26
0
-
-
-
-
-
-
-
-
-
-
-
-
Fast-mode Plus
Standard-mode
Fast-mode
tHIGH
HIGH period of the
SCL clock
Fast-mode Plus
Standard-mode
Fast-mode
[3][4][8]
[9][10]
tHD;DAT
data hold time
0
Fast-mode Plus
Standard-mode
Fast-mode
0
tSU;DAT
data set-up time
250
100
50
Fast-mode Plus
[1] See the I2C-bus specification UM10204 for details.
[2] Parameters are valid over operating temperature range unless otherwise specified.
[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[5] Cb = total capacitance of one bus line in pF.
[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
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[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
t
t
SU;DAT
f
70 %
30 %
70 %
30 %
SDA
SCL
t
t
HD;DAT
VD;DAT
t
f
t
HIGH
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
t
LOW
1 / f
S
SCL
002aaf425
Fig 22. I2C-bus pins clock timing
LPC11U1X
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10.6 SSP interface
Table 16. Dynamic characteristics of SPI pins in SPI mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPI master (in SPI mode)
[1]
[1]
[2]
Tcy(clk)
clock cycle time
data set-up time
full-duplex mode
when only transmitting
in SPI mode
50
40
15
-
-
-
-
ns
ns
ns
tDS
2.4 V VDD 3.6 V
2.0 V VDD < 2.4 V
1.8 V VDD < 2.0 V
in SPI mode
[2]
[2]
[2]
[2]
[2]
20
24
0
ns
ns
ns
ns
ns
-
-
-
-
-
tDH
data hold time
-
tv(Q)
th(Q)
data output valid time in SPI mode
data output hold time in SPI mode
-
10
-
0
SPI slave (in SPI mode)
Tcy(PCLK) PCLK cycle time
20
-
-
-
-
-
-
ns
ns
ns
ns
ns
[3][4]
[3][4]
[3][4]
[3][4]
tDS
data set-up time
data hold time
in SPI mode
in SPI mode
0
-
tDH
3 Tcy(PCLK) + 4
-
tv(Q)
th(Q)
data output valid time in SPI mode
data output hold time in SPI mode
-
-
3 Tcy(PCLK) + 11
2 Tcy(PCLK) + 5
[1] Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2]
[3] Tcy(clk) = 12 Tcy(PCLK)
[4] Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V.
Tamb = 40 C to 85 C.
.
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T
t
t
clk(L)
cy(clk)
clk(H)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
CPHA = 1
t
t
DH
DS
DATA VALID
DATA VALID
MISO
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
t
MOSI
MISO
t
CPHA = 0
DS
DH
DATA VALID
DATA VALID
002aae829
Fig 23. SSP master timing in SPI mode
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T
t
t
clk(L)
cy(clk)
clk(H)
SCK (CPOL = 0)
SCK (CPOL = 1)
t
t
DH
DS
MOSI
MISO
DATA VALID
DATA VALID
t
t
h(Q)
v(Q)
CPHA = 1
DATA VALID
DATA VALID
t
t
DH
DS
MOSI
MISO
DATA VALID
DATA VALID
DATA VALID
t
t
h(Q)
CPHA = 0
v(Q)
DATA VALID
002aae830
Fig 24. SSP slave timing in SPI mode
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11. Application information
11.1 Suggested USB interface solutions
V
DD
USB_CONNECT
USB_VBUS
LPC11Uxx
soft-connect switch
R1
1.5 kΩ
R
= 33 Ω
S
S
USB-B
connector
USB_DP
USB_DM
R
= 33 Ω
V
SS
002aaf893
Fig 25. USB interface on a self-powered device
V
DD
LPC11Uxx
R1
1.5 kΩ
USB_VBUS
USB-B
connector
R
= 33 Ω
= 33 Ω
S
S
USB_DP
R
USB_DM
V
SS
002aaf894
Fig 26. USB interface on a bus-powered device
11.2 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV(RMS) is needed.
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LPC1xxx
XTALIN
C
i
C
g
100 pF
002aae788
Fig 27. Slave mode operation of the on-chip oscillator
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(Figure 27), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 28 and in
Table 17 and Table 18. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (the fundamental frequency is represented by L, CL and
RS). Capacitance CP in Figure 28 represents the parallel package capacitance and should
not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer.
LPC1xxx
L
XTALIN
XTALOUT
C
L
C
P
=
XTAL
R
S
C
X2
C
X1
002aaf424
Fig 28. Oscillator modes and models: oscillation mode of operation and external crystal
model used for CX1/CX2 evaluation
Table 17. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation Crystal load
Maximum crystal
External load
frequency FOSC
capacitance CL
series resistance RS
capacitors CX1, CX2
1 MHz - 5 MHz
10 pF
< 300
< 300
< 300
18 pF, 18 pF
39 pF, 39 pF
57 pF, 57 pF
20 pF
30 pF
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Table 17. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation Crystal load
Maximum crystal
External load
frequency FOSC
capacitance CL
series resistance RS
capacitors CX1, CX2
5 MHz - 10 MHz
10 pF
< 300
< 200
< 100
< 160
< 60
18 pF, 18 pF
39 pF, 39 pF
57 pF, 57 pF
18 pF, 18 pF
39 pF, 39 pF
18 pF, 18 pF
20 pF
30 pF
10 MHz - 15 MHz
15 MHz - 20 MHz
10 pF
20 pF
10 pF
< 80
Table 18. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) high frequency mode
Fundamental oscillation Crystal load
Maximum crystal
External load
frequency FOSC
capacitance CL
series resistance RS
capacitors CX1, CX2
15 MHz - 20 MHz
10 pF
< 180
< 100
< 160
< 80
18 pF, 18 pF
39 pF, 39 pF
18 pF, 18 pF
39 pF, 39 pF
20 pF
20 MHz - 25 MHz
10 pF
20 pF
11.3 XTAL Printed-Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of
third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plain. Loops must be made as small as possible in
order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller
accordingly to the increase in parasitics of the PCB layout.
LPC11U1X
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11.4 Standard I/O pad configuration
Figure 29 shows the possible pin modes for standard I/O pins with analog input function:
• Digital output driver
• Digital input: Pull-up enabled/disabled
• Digital input: Pull-down enabled/disabled
• Digital input: Repeater mode enabled/disabled
• Analog input
V
DD
ESD
output enable
pin configured
as digital output
driver
output
PIN
ESD
V
DD
V
SS
weak
pull-up
pull-up enable
weak
pull-down
repeater mode
enable
pin configured
as digital input
pull-down enable
data input
select analog input
pin configured
as analog input
analog input
002aaf304
Fig 29. Standard I/O pad configuration
LPC11U1X
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11.5 Reset pad configuration
V
DD
V
DD
V
DD
R
pu
ESD
20 ns RC
GLITCH FILTER
reset
PIN
ESD
V
SS
002aaf274
Fig 30. Reset pad configuration
11.6 ADC usage notes
The following guidelines show how to increase the performance of the ADC in a noisy
environment beyond the ADC specifications listed in Table 7:
• The ADC input trace must be short and as close as possible to the LPC11U1x chip.
• The ADC input traces must be shielded from fast switching digital signals and noisy
power supply lines.
• Because the ADC and the digital core share the same power supply, the power supply
line must be adequately filtered.
• To improve the ADC performance in a very noisy environment, put the device in Sleep
mode during the ADC conversion.
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12. Package outline
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
C
v
C
C
A
B
e
b
y
1
y
w
C
9
16
L
8
17
e
E
e
2
h
33
1
24
X
terminal 1
index area
32
25
0
D
h
2.5
scale
5 mm
v
Dimensions
Unit
(1)
(1)
(1)
A
A
b
c
D
D
E
E
e
e
1
e
2
L
w
y
y
1
1
h
h
max 1.00 0.05 0.35
mm nom 0.85 0.02 0.28 0.2 7.0 4.70 7.0 4.70 0.65 4.55 4.55 0.60 0.1 0.05 0.08 0.1
min 0.80 0.00 0.23 6.9 4.55 6.9 4.55 0.45
7.1 4.85 7.1 4.85
0.75
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
hvqfn33_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
- - -
09-03-17
09-03-23
Fig 31. Package outline HVQFN33 (7 x 7 x 0.85 mm)
LPC11U1X
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Product data sheet
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NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
D
B
A
terminal 1
index area
A
A
1
E
c
detail X
C
e
1
y
y
v
w
C
C
A
B
C
1
e
1/2 e
b
9
16
L
17
8
e
e
E
h
2
1/2 e
24
1
terminal 1
index area
32
25
X
D
h
0
2.5
scale
5 mm
Dimensions (mm are the original dimensions)
(1)
(1)
(1)
(1)
Unit
A
A
1
b
c
D
D
E
E
e
e
e
L
v
w
y
y
1
h
h
1
2
max
0.05 0.30
5.1 3.75 5.1 3.75
0.5
mm nom 0.85
min
0.2
0.5 3.5 3.5
0.1 0.05 0.05 0.1
0.00 0.18
4.9 3.45 4.9 3.45
0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
hvqfn33f_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
11-10-11
11-10-17
MO-220
Fig 32. Package outline HVQFN33 (5 x 5 x 0.85 mm)
LPC11U1X
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NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.6
mm
0.25
0.5
1
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
03-02-25
SOT313-2
136E05
MS-026
Fig 33. Package outline LQFP48 (SOT313-2)
LPC11U1X
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TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 x 4.5 x 0.7 mm
SOT1155-2
D
B
A
ball A1
index area
A
2
E
A
A
1
detail X
e
1
C
Ø v
Ø w
C
C
A
B
e
1/2 e
b
y
1
y
C
H
e
G
F
E
D
C
B
A
e
2
1/2 e
ball A1
index area
1
2
3
4
5
6
7
8
X
0
5 mm
scale
v
Dimensions
Unit
A
A
1
A
2
b
D
E
e
e
1
e
2
w
y
y
1
max 1.10 0.30 0.80 0.35 4.6 4.6
mm nom 0.95 0.25 0.70 0.30 4.5 4.5 0.5 3.5 3.5 0.15 0.05 0.08 0.1
min 0.85 0.20 0.65 0.25 4.4 4.4
sot1155-2_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
- - -
JEITA
11-01-18
11-03-01
SOT1155-2
Fig 34. Package outline TFBGA48 (SOT1155-2)
LPC11U1X
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13. Soldering
Footprint information for reflow soldering of HVQFN33 package
Hx
Gx
see detail X
P
nSPx
Ay
By
SLy
Hy Gy
nSPy
C
D
SLx
Bx
Ax
0.60
0.30
solder land
solder paste
occupied area
detail X
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
Gx
Gy
Hx
Hy
6.2
SLx
SLy
nSPx nSPy
0.5
5.95
5.95
4.25
4.25
0.85
0.27
5.25
5.25
6.2
3.75
3.75
3
3
11-11-15
11-11-20
Issue date
002aag766
Fig 35. Reflow soldering for the HVQFN33 (5x5) package
LPC11U1X
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Footprint information for reflow soldering of HVQFN33 package
OID = 8.20 OA
PID = 7.25 PA+OA
OwDtot = 5.10 OA
evia = 4.25
0.20 SR
chamfer (4×)
W = 0.30 CU
e = 0.65
SPD = 1.00 SP
0.45 DM
GapD = 0.70 SP
evia = 2.40
B-side
SDhtot = 2.70 SP
Solder resist
covered via
4.55 SR
DHS = 4.85 CU
LbD = 5.80 CU
LaD = 7.95 CU
0.30 PH
0.60 SR cover
0.60 CU
(A-side fully covered)
number of vias: 20
solder land
solder land plus solder paste
solder paste deposit
occupied area
solder resist
Remark:
Stencil thickness: 0.125 mm
Dimensions in mm
001aao134
Fig 36. Reflow soldering for the HVQFN33 (7x7) package
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Footprint information for reflow soldering of LQFP48 package
SOT313-2
Hx
Gx
(0.125)
P2
P1
Hy Gy
By
Ay
C
D2 (8×)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ax
Ay
Bx
By
C
D1
D2
Gx
Gy
Hx
Hy
0.500 0.560 10.350 10.350 7.350 7.350 1.500 0.280 0.500 7.500 7.500 10.650 10.650
sot313-2_fr
Fig 37. Reflow soldering for the LQFP48 package
LPC11U1X
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32-bit ARM Cortex-M0 microcontroller
Footprint information for reflow soldering of TFBGA48 package
SOT1155-2
Hx
P
P
Hy
see detail X
solder land
solder paste deposit
solder land plus solder paste
SL
occupied area
solder resist
SP
SR
detail X
DIMENSIONS in mm
P
SL
SP
SR
Hx
Hy
0.50
0.225 0.275 0.325
4.75
4.75
sot1155-2_fr
Fig 38. Reflow soldering for the TFBGA48 package
LPC11U1X
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14. Abbreviations
Table 19. Abbreviations
Acronym
A/D
Description
Analog-to-Digital
ADC
AHB
APB
Analog-to-Digital Converter
Advanced High-performance Bus
Advanced Peripheral Bus
BrownOut Detection
BOD
GPIO
JTAG
PLL
General Purpose Input/Output
Joint Test Action Group
Phase-Locked Loop
RC
Resistor-Capacitor
SPI
Serial Peripheral Interface
Serial Synchronous Interface
Synchronous Serial Port
Test Access Port
SSI
SSP
TAP
USART
Universal Synchronous Asynchronous Receiver/Transmitter
LPC11U1X
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15. Revision history
Table 20. Revision history
Document ID
LPC11U1X v.2
Modifications:
Release date
20120111
Data sheet status
Change notice
Supersedes
Product data sheet
-
LPC11U1X v.1
• Number of physical and logical endpoints corrected in Section 7.8.1.
• Use of JTAG updated in Section 2 (for BSDL only).
• Sampling frequency corrected in Table note 7 of Table 7.
• Conditions for parameter Tstg updated in Table 5.
• Part LPC11U14FHI33/201 added.
• Editorial updates.
• ROM-based integer division routines added (Section 2).
• Use of USB with power profiles specified (Section 7.8).
• Power consumption data added in Section 9.2.
• SSP dynamic characteristics added (Table 16).
• IRC dynamic characteristics added (Table 12).
• Data sheet status changed to Product data sheet.
• Section 13 added.
• Description of pin PIO0_3 updated in Table 3: this pin is not used by the boot loader.
LPC11U1X v.1
20110411
Objective data sheet
-
-
LPC11U1X
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16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
16.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
LPC11U1X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 11 January 2012
67 of 69
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
16.4 Trademarks
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
LPC11U1X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 11 January 2012
68 of 69
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
18. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
7.16.5.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 26
7.16.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.16.5.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 26
7.16.5.4 Power-down mode. . . . . . . . . . . . . . . . . . . . . 26
7.16.5.5 Deep power-down mode . . . . . . . . . . . . . . . . 27
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
4
4.1
5
7.16.6
System control . . . . . . . . . . . . . . . . . . . . . . . . 27
7.16.6.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.16.6.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 27
7.16.6.3 Code security (Code Read Protection - CRP) 27
7.16.6.4 APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 28
7.16.6.5 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.16.6.6 External interrupt inputs. . . . . . . . . . . . . . . . . 28
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
7
7.1
7.2
7.3
7.4
7.5
Functional description . . . . . . . . . . . . . . . . . . 16
On-chip flash programming memory . . . . . . . 16
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 16
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Nested Vectored Interrupt Controller (NVIC) . 17
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 18
IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 18
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
General Purpose Input/Output GPIO . . . . . . . 18
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
USB interface . . . . . . . . . . . . . . . . . . . . . . . . 19
Full-speed USB device controller . . . . . . . . . . 19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SSP serial I/O controller . . . . . . . . . . . . . . . . . 20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
I2C-bus serial I/O controller . . . . . . . . . . . . . . 20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General purpose external event
7.17
Emulation and debugging . . . . . . . . . . . . . . . 29
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 30
9
Static characteristics . . . . . . . . . . . . . . . . . . . 31
BOD static characteristics . . . . . . . . . . . . . . . 37
Power consumption . . . . . . . . . . . . . . . . . . . 37
Peripheral power consumption . . . . . . . . . . . 40
Electrical pin characteristics. . . . . . . . . . . . . . 42
9.1
9.2
9.3
9.4
7.5.1
7.5.2
7.6
7.6.1
7.7
7.7.1
7.8
7.8.1
7.8.1.1
7.9
7.9.1
7.10
7.10.1
7.11
7.11.1
7.12
7.12.1
7.13
10
Dynamic characteristics. . . . . . . . . . . . . . . . . 45
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 45
External clock. . . . . . . . . . . . . . . . . . . . . . . . . 45
Internal oscillators . . . . . . . . . . . . . . . . . . . . . 46
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SSP interface. . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1
10.2
10.3
10.4
10.5
10.6
11
Application information . . . . . . . . . . . . . . . . . 52
Suggested USB interface solutions . . . . . . . . 52
XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
XTAL Printed-Circuit Board (PCB) layout
11.1
11.2
11.3
guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Standard I/O pad configuration . . . . . . . . . . . 55
Reset pad configuration. . . . . . . . . . . . . . . . . 56
ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 56
11.4
11.5
11.6
counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 21
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
System tick timer . . . . . . . . . . . . . . . . . . . . . . 22
Windowed WatchDog Timer (WWDT) . . . . . . 22
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clocking and power control . . . . . . . . . . . . . . 23
Integrated oscillators . . . . . . . . . . . . . . . . . . . 23
12
13
14
15
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 57
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 65
Revision history . . . . . . . . . . . . . . . . . . . . . . . 66
7.13.1
7.14
7.15
7.15.1
7.16
7.16.1
16
Legal information . . . . . . . . . . . . . . . . . . . . . . 67
Data sheet status. . . . . . . . . . . . . . . . . . . . . . 67
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 68
16.1
16.2
16.3
16.4
7.16.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 24
7.16.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 25
7.16.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 25
7.16.2
7.16.3
7.16.4
7.16.5
System PLL and USB PLL . . . . . . . . . . . . . . . 25
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Wake-up process . . . . . . . . . . . . . . . . . . . . . . 25
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 25
17
18
Contact information . . . . . . . . . . . . . . . . . . . . 68
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 January 2012
Document identifier: LPC11U1X
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