LPC2290FBD144/01,5_技术文档

LPC2290

16/32-bit ARM microcontroller with CAN, 10-bit ADC and

external memory interface

Rev. 03 — 16 November 2006

Product data sheet

1. General description

The LPC2290 microcontroller is based on a 16/32-bit ARM7TDMI-S CPU with real-time

emulation and embedded trace support. For critical code size applications, the alternative

16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.

With its 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit

ADC, two advanced CAN channels, PWM channels and up to nine external interrupt pins

this microcontroller is particularly suitable for automotive and industrial control

applications as well as medical systems and fault-tolerant maintenance buses. The

LPC2290 provides up to 76 GPIOs depending on bus conﬁguration. With a wide range of

additional serial communications interfaces, it is also suited for communication gateways

and protocol converters as well as many other general-purpose applications.

Remark: Throughout the data sheet, the term ‘LPC2290’ will apply to devices with and

without the /01 sufﬁx. New devices will use the /01 sufﬁx to differentiate from the original

devices only when necessary.

2. Features

2.1 Enhancements introduced with LPC2290/01 device

I CPU clock up to 72 MHz and 64 kB of on-chip static RAM.

I Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original

LPC2290. A port pin can be read at any time regardless of its function.

I Dedicated result registers for ADC reduce interrupt overhead.

I UART0/1 include fractional baud rate generator, auto-bauding capabilities and

handshake ﬂow-control fully implemented in hardware.

I SSP serial controller supporting SPI, 4-wire SSI, and Microwire buses.

2.2 Key features common for LPC2290 and LPC2290/01

I 16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package.

I 16/64 kB on-chip static RAM.

I Serial bootloader using UART0 provides in-system download and programming

capabilities.

I EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with the

on-chip RealMonitor software as well as high-speed real-time tracing of instruction

execution.

I Two interconnected CAN interfaces with advanced acceptance ﬁlters. Additional serial

interfaces include two UARTs (16C550), Fast I²C-bus (400 kbit/s) and two SPIs.

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

I Eight channel 10-bit ADC with conversion time as low as 2.44 µs.

I Two 32-bit timers (with four capture and four compare channels), PWM unit (six

outputs), Real-Time Clock (RTC) and watchdog.

I Vectored Interrupt Controller (VIC) with conﬁgurable priorities and vector addresses.

I Conﬁgurable external memory interface with up to four banks, each up to 16 MB and

8/16/32-bit data width.

I Up to 76 general purpose I/O pins (5 V tolerant). Up to nine edge/level sensitive

external interrupt pins available.

I 60/72 MHz maximum CPU clock available from programmable on-chip PLL with

settling time of 100 µs.

I On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.

I Power saving modes include Idle and Power-down.

I Processor wake-up from Power-down mode via external interrupt.

I Individual enable/disable of peripheral functions for power optimization.

I Dual power supply:

N CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ± 0.15 V).

N I/O power supply range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC2290FBD144

LQFP144

plastic low proﬁle quad ﬂat package;

SOT486-1

144 leads; body 20 × 20 × 1.4 mm

LPC2290FBD144/01

LQFP144

plastic low proﬁle quad ﬂat package;

SOT486-1

144 leads; body 20 × 20 × 1.4 mm

3.1 Ordering options

Table 2.

Ordering options

Type number

LPC2290FBD144

RAM CAN

Enhancements

Temperature range

−40 °C to +85 °C

16 kB 2 channels None

LPC2290FBD144/01 64 kB 2 channels Higher CPU clock, more

on-chip SRAM, Fast I/Os,

improved UARTs, added SSP,

upgraded ADC

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

2 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

4. Block diagram

(1)

TMS

(1)

TDI

(1)

XTAL2

XTAL1 RST

(1)

TRST

TCK

TDO

TEST/DEBUG

INTERFACE

LPC2290

LPC2290/01

SYSTEM

FUNCTIONS

PLL

ARM7TDMI-S

system

clock

P0[31:0]

FAST GENERAL

PURPOSE I/O

VECTORED

INTERRUPT

CONTROLLER

(3)

AHB BRIDGE

P1[31:16], P1[1:0]

ARM7 local

bus

AMBA Advanced High-performance

Bus(AHB)

INTERNAL

SRAM

CONTROLLER

AHB

DECODER

(2)

16/64 kB

SRAM

CS3 to CS0

(2)

AHB TO APB

BRIDGE

APB

DIVIDER

A23 to A0

EXTERNAL MEMORY

CONTROLLER

(2)

BLS3 to BLS0

(2)

OE, WE

Advanced

Peripheral Bus

(APB)

(2)

D31 to D0

SCL

2

EXTERNAL

INTERRUPTS

I C-BUS SERIAL

INTERFACE

EINT3 to EINT0

SDA

SCK0, SCK1

4 × CAP0

4 × CAP1

4 × MAT0

4 × MAT1

(3)

CAPTURE/

COMPARE

TIMER 0/TIMER 1

SPI AND SSP

MOSI0, MOSI1

MISO0, MISO1

SSEL0, SSEL1

SERIAL INTERFACES

0 AND 1

TXD0, TXD1

RXD0, RXD1

AIN3 to AIN0

AIN7 to AIN4

A/D CONVERTER

UART0/UART1

DSR1, CTS1,

DCD1, RI1

P0[30:0]

P1[31:16], P1[1:0]

P2[31:0]

TD2, TD1

RD2, RD1

GENERAL

PURPOSE I/O

CAN

P3[31:0]

WATCHDOG

TIMER

PWM6 to PWM1

PWM0

SYSTEM

CONTROL

REAL-TIME CLOCK

002aaa796

(1) When test/debug interface is used, GPIO/other functions sharing these pins are not available.

(2) Pins shared with GPIO.

(3) Available in LPC2290/01 only.

Fig 1. Block diagram

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

3 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

5. Pinning information

5.1 Pinning

1

108

LPC2290

36

73

002aaa797

Fig 2. LQFP144 pinning

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

4 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

5.2 Pin description

Table 3.

Symbol

Pin description

Type

Description

P0.0 to P0.31

I/O

Port 0: Port 0 is a 32-bit bidirectional I/O port with individual direction controls

for each bit. The operation of port 0 pins depends upon the pin function

selected via the Pin Connect Block.

Pins 26 and 31 of port 0 are not available.

P0.0 — General purpose digital input/output pin.

TXD0 — Transmitter output for UART0.

PWM1 — Pulse Width Modulator output 1.

P0.1 — General purpose digital input/output pin.

RXD0 — Receiver input for UART0.

P0.0/TXD0/

PWM1

42^[1]

I/O

O

P0.1/RXD0/

PWM3/EINT0

49^[2]

I/O

I

O

PWM3 — Pulse Width Modulator output 3.

EINT0 — External interrupt 0 input

I

P0.2/SCL/

CAP0.0

50^[3]

I/O

P0.2 — General purpose digital input/output pin.

SCL — I²C-bus clock input/output. Open-drain output (for I²C-bus

compliance).

I

CAP0.0 — Capture input for Timer 0, channel 0.

P0.3 — General purpose digital input/output pin.

SDA — I²C-bus data input/output. Open-drain output (for I²C-bus

P0.3/SDA/

58^[3]

I/O

MAT0.0/EINT1

compliance).

O

MAT0.0 — Match output for Timer 0, channel 0.

EINT1 — External interrupt 1 input.

I

P0.4/SCK0/

CAP0.1

59^[1]

I/O

I

P0.4 — General purpose digital input/output pin.

SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.

CAP0.1 — Capture input for Timer 0, channel 1.

P0.5 — General purpose digital input/output pin.

P0.5/MISO0/

MAT0.1

61^[1]

I/O

MISO0 — Master In Slave OUT for SPI0. Data input to SPI master or data

output from SPI slave.

O

MAT0.1 — Match output for Timer 0, channel 1.

P0.6 — General purpose digital input/output pin.

P0.6/MOSI0/

CAP0.2

68^[1]

I/O

MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data

input to SPI slave.

I

CAP0.2 — Capture input for Timer 0, channel 2.

P0.7 — General purpose digital input/output pin.

SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.

PWM2 — Pulse Width Modulator output 2.

EINT2 — External interrupt 2 input.

P0.7/SSEL0/

PWM2/EINT2

69^[2]

I/O

I

O

I

P0.8/TXD1/

PWM4

75^[1]

I/O

O

P0.8 — General purpose digital input/output pin.

TXD1 — Transmitter output for UART1.

PWM4 — Pulse Width Modulator output 4.

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

5 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

Table 3.

Symbol

Pin description …continued

Type

Description

P0.9/RXD1/

PWM6/EINT3

76^[2]

I/O

I

P0.9 — General purpose digital input/output pin.

RXD1 — Receiver input for UART1.

O

I

PWM6 — Pulse Width Modulator output 6.

EINT3 — External interrupt 3 input.

P0.10/RTS1/

CAP1.0

78^[1]

83^[1]

84^[1]

85^[1]

92^[2]

I/O

O

I

P0.10 — General purpose digital input/output pin.

RTS1 — Request to Send output for UART1.

CAP1.0 — Capture input for Timer 1, channel 0.

P0.11 — General purpose digital input/output pin.

CTS1 — Clear to Send input for UART1.

P0.11/CTS1/

CAP1.1

I/O

I

CAP1.1 — Capture input for Timer 1, channel 1.

P0.12 — General purpose digital input/output pin.

DSR1 — Data Set Ready input for UART1.

MAT1.0 — Match output for Timer 1, channel 0.

P0.13 — General purpose digital input/output pin.

DTR1 — Data Terminal Ready output for UART1.

MAT1.1 — Match output for Timer 1, channel 1.

P0.14 — General purpose digital input/output pin.

DCD1 — Data Carrier Detect input for UART1.

EINT1 — External interrupt 1 input.

P0.12/DSR1/

MAT1.0

I/O

I

O

I/O

O

I/O

I

P0.13/DTR1/

MAT1.1

P0.14/DCD1/

EINT1

I

Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take

over control of the part after reset.

P0.15/RI1/

EINT2

99^[2]

I/O

P0.15 — General purpose digital input/output pin.

RI1 — Ring Indicator input for UART1.

I

EINT2 — External interrupt 2 input.

P0.16/EINT0/

MAT0.2/CAP0.2

100^[2]

I/O

I

P0.16 — General purpose digital input/output pin.

EINT0 — External interrupt 0 input.

O

I

MAT0.2 — Match output for Timer 0, channel 2.

CAP0.2 — Capture input for Timer 0, channel 2.

P0.17 — General purpose digital input/output pin.

CAP1.2 — Capture input for Timer 1, channel 2.

P0.17/CAP1.2/ 101^[1]

SCK1/MAT1.2

I/O

I

I/O

SCK1 — Serial Clock for SPI1/SSP. SPI clock output from master or input to

slave (SSP is available in LPC2290/01 only).

O

MAT1.2 — Match output for Timer 1, channel 2.

P0.18 — General purpose digital input/output pin.

CAP1.3 — Capture input for Timer 1, channel 3.

P0.18/CAP1.3/ 121^[1]

MISO1/MAT1.3

I/O

I

I/O

MISO1 — Master In Slave Out for SPI1/SSP. Data input to SPI master or data

output from SPI slave (SSP is available in LPC2290/01 only).

O

MAT1.3 — Match output for Timer 1, channel 3.

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

6 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

Table 3.

Symbol

P0.19/MAT1.2/ 122^[1]

MOSI1/CAP1.2

Pin description …continued

Type

I/O

O

Description

P0.19 — General purpose digital input/output pin.

MAT1.2 — Match output for Timer 1, channel 2.

I/O

MOSI1 — Master Out Slave In for SPI1/SSP. Data output from SPI master or

data input to SPI slave (SSP is available in LPC2290/01 only).

I

CAP1.2 — Capture input for Timer 1, channel 2.

P0.20 — General purpose digital input/output pin.

MAT1.3 — Match output for Timer 1, channel 3.

P0.20/MAT1.3/ 123^[2]

SSEL1/EINT3

I/O

O

I

SSEL1 — Slave Select for SPI1/SSP. Selects the SPI interface as a slave

(SSP is available in LPC2290/01 only).

I

EINT3 — External interrupt 3 input.

P0.21/PWM5/

CAP1.3

4^[1]

I/O

O

I

P0.21 — General purpose digital input/output pin.

PWM5 — Pulse Width Modulator output 5.

CAP1.3 — Capture input for Timer 1, channel 3.

P0.22 — General purpose digital input/output pin.

CAP0.0 — Capture input for Timer 0, channel 0.

MAT0.0 — Match output for Timer 0, channel 0.

P0.23 — General purpose digital input/output pin.

RD2 — CAN2 receiver input.

P0.22/CAP0.0/ 5^[1]

MAT0.0

I/O

I

O

I/O

I

P0.23/RD2

P0.24/TD2

P0.25

6^[1]

8^[1]

I/O

O

I/O

I

P0.24 — General purpose digital input/output pin.

TD2 — CAN2 transmitter output.

21^[1]

23^[4]

P0.25 — General purpose digital input/output pin.

RD1 — CAN1 receiver input.

P0.27/AIN0/

CAP0.1/MAT0.1

I/O

I

P0.27 — General purpose digital input/output pin.

AIN0 — ADC, input 0. This analog input is always connected to its pin.

CAP0.1 — Capture input for Timer 0, channel 1.

MAT0.1 — Match output for Timer 0, channel 1.

P0.28 — General purpose digital input/output pin.

AIN1 — ADC, input 1. This analog input is always connected to its pin.

CAP0.2 — Capture input for Timer 0, channel 2.

MAT0.2 — Match output for Timer 0, channel 2.

P0.29 — General purpose digital input/output pin.

AIN2 — ADC, input 2. This analog input is always connected to its pin.

CAP0.3 — Capture input for Timer 0, Channel 3.

MAT0.3 — Match output for Timer 0, channel 3.

P0.30 — General purpose digital input/output pin.

AIN3 — ADC, input 3. This analog input is always connected to its pin.

EINT3 — External interrupt 3 input.

I

O

I/O

I

P0.28/AIN1/

CAP0.2/MAT0.2

25^[4]

32^[4]

33^[4]

I

O

I/O

I

P0.29/AIN2/

CAP0.3/MAT0.3

I

O

I/O

I

P0.30/AIN3/

EINT3/CAP0.0

I

CAP0.0 — Capture input for Timer 0, channel 0.

P1.0 to P1.31

I/O

Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls

for each bit. The operation of port 1 pins depends upon the pin function

selected via the Pin Connect Block.

Pins 2 through 15 of port 1 are not available.

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

7 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

Table 3.

Symbol

P1.0/CS0

Pin description …continued

Type

I/O

O

Description

91^[5]

P1.0 — General purpose digital input/output pin.

CS0 — LOW-active Chip Select 0 signal.

(Bank 0 addresses range 0x8000 0000 to 0x80FF FFFF)

P1.1 — General purpose digital input/output pin.

P1.1/OE

90^[5]

34^[5]

24^[5]

15^[5]

7^[5]

I/O

O

OE — LOW-active Output Enable signal.

P1.16/

TRACEPKT0

I/O

O

P1.16 — General purpose digital input/output pin.

TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up.

P1.17 — General purpose digital input/output pin.

P1.17/

TRACEPKT1

I/O

O

TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up.

P1.18 — General purpose digital input/output pin.

P1.18/

TRACEPKT2

I/O

O

TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up.

P1.19 — General purpose digital input/output pin.

P1.19/

TRACEPKT3

I/O

O

TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up.

P1.20 — General purpose digital input/output pin.

P1.20/

TRACESYNC

102^[5]

I/O

O

TRACESYNC — Trace Synchronization. Standard I/O port with internal

pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1[25:16] to

operate as Trace port after reset.

P1.21/

PIPESTAT0

95^[5]

86^[5]

82^[5]

70^[5]

I/O

O

P1.21 — General purpose digital input/output pin.

PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up.

P1.22 — General purpose digital input/output pin.

P1.22/

PIPESTAT1

I/O

O

PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up.

P1.23 — General purpose digital input/output pin.

P1.23/

PIPESTAT2

I/O

O

PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pull-up.

P1.24 — General purpose digital input/output pin.

P1.24/

TRACECLK

I/O

O

TRACECLK — Trace Clock. Standard I/O port with internal pull-up.

P1.25 — General purpose digital input/output pin.

P1.25/EXTIN0 60^[5]

I/O

I

EXTIN0 — External Trigger Input. Standard I/O with internal pull-up.

P1.26 — General purpose digital input/output pin.

P1.26/RTCK

52^[5]

I/O

RTCK — Returned Test Clock output. Extra signal added to the JTAG port.

Assists debugger synchronization when processor frequency varies.

Bidirectional pin with internal pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1[31:26] to

operate as Debug port after reset.

P1.27/TDO

P1.28/TDI

P1.29/TCK

P1.30/TMS

144^[5]

140^[5]

126^[5]

113^[5]

I/O

O

P1.27 — General purpose digital input/output pin.

TDO — Test Data out for JTAG interface.

I/O

I

P1.28 — General purpose digital input/output pin.

TDI — Test Data in for JTAG interface.

I/O

I

P1.29 — General purpose digital input/output pin.

TCK — Test Clock for JTAG interface.

I/O

I

P1.30 — General purpose digital input/output pin.

TMS — Test Mode Select for JTAG interface.

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

8 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

Table 3.

Pin description …continued

Symbol

43^[5]

Type

I/O

I

Description

P1.31/TRST

P1.31 — General purpose digital input/output pin.

TRST — Test Reset for JTAG interface.

P2.0 to P2.31

I/O

Port 2 — Port 2 is a 32-bit bidirectional I/O port with individual direction

controls for each bit. The operation of port 2 pins depends upon the pin

function selected via the Pin Connect Block.

P2.0/D0

98^[5]

I/O

P2.0 — General purpose digital input/output pin.

D0 — External memory data line 0.

P2.1/D1

105^[5]

106^[5]

108^[5]

109^[5]

114^[5]

115^[5]

116^[5]

117^[5]

118^[5]

120^[5]

124^[5]

125^[5]

127^[5]

129^[5]

130^[5]

131^[5]

132^[5]

P2.1 — General purpose digital input/output pin.

D1 — External memory data line 1.

P2.2/D2

P2.2 — General purpose digital input/output pin.

D2 — External memory data line 2.

P2.3/D3

P2.3 — General purpose digital input/output pin.

D3 — External memory data line 3.

P2.4/D4

P2.4 — General purpose digital input/output pin.

D4 — External memory data line 4.

P2.5/D5

P2.5 — General purpose digital input/output pin.

D5 — External memory data line 5.

P2.6/D6

P2.6 — General purpose digital input/output pin.

D6 — External memory data line 6.

P2.7/D7

P2.7 — General purpose digital input/output pin.

D7 — External memory data line 7.

P2.8/D8

P2.8 — General purpose digital input/output pin.

D8 — External memory data line 8.

P2.9/D9

P2.9 — General purpose digital input/output pin.

D9 — External memory data line 9.

P2.10/D10

P2.11/D11

P2.12/D12

P2.13/D13

P2.14/D14

P2.15/D15

P2.16/D16

P2.17/D17

P2.10 — General purpose digital input/output pin.

D10 — External memory data line 10.

P2.11 — General purpose digital input/output pin.

D11 — External memory data line 11.

P2.12 — General purpose digital input/output pin.

D12 — External memory data line 12.

P2.13 — General purpose digital input/output pin.

D13 — External memory data line 13.

P2.14 — General purpose digital input/output pin.

D14 — External memory data line 14.

P2.15 — General purpose digital input/output pin.

D15 — External memory data line 15.

P2.16 — General purpose digital input/output pin.

D16 — External memory data line 16.

P2.17 — General purpose digital input/output pin.

D17 — External memory data line 17.

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

9 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

Table 3.

Symbol

Pin description …continued

Type

I/O

I

Description

P2.18/D18

133^[5]

P2.18 — General purpose digital input/output pin.

D18 — External memory data line 18.

P2.19/D19

P2.20/D20

P2.21/D21

P2.22/D22

P2.23/D23

P2.24/D24

P2.25/D25

134^[5]

136^[5]

137^[5]

1^[5]

P2.19 — General purpose digital input/output pin.

D19 — External memory data line 19.

P2.20 — General purpose digital input/output pin.

D20 — External memory data line 20.

P2.21 — General purpose digital input/output pin.

D21 — External memory data line 21.

P2.22 — General purpose digital input/output pin.

D22 — External memory data line 22.

10^[5]

11^[5]

12^[5]

13^[5]

P2.23 — General purpose digital input/output pin.

D23 — External memory data line 23.

P2.24 — General purpose digital input/output pin.

D24 — External memory data line 24.

P2.25 — General purpose digital input/output pin.

D25 — External memory data line 25.

P2.26/D26/

BOOT0

P2.26 — General purpose digital input/output pin.

D26 — External memory data line 26.

BOOT0 — While RESET is low, together with BOOT1 controls booting and

internal operation. Internal pull-up ensures high state if pin is left

unconnected.

P2.27/D27/

BOOT1

16^[5]

I/O

I

P2.27 — General purpose digital input/output pin.

D27 — External memory data line 27.

BOOT1 — While RESET is low, together with BOOT0 controls booting and

internal operation. Internal pull-up ensures high state if pin is left

unconnected.

BOOT1:0 = 00 selects 8-bit memory on CS0 for boot.

BOOT1:0 = 01 selects 16-bit memory on CS0 for boot.

BOOT1:0 = 10 selects 32-bit memory on CS0 for boot.

BOOT1:0 = 11 selects internal ﬂash memory.

P2.28/D28

P2.29/D29

17^[5]

18^[5]

19^[2]

I/O

I

P2.28 — General purpose digital input/output pin.

D28 — External memory data line 28.

P2.29 — General purpose digital input/output pin.

D29 — External memory data line 29.

P2.30/D30/

AIN4

P2.30 — General purpose digital input/output pin.

D30 — External memory data line 30.

AIN4 — ADC, input 4. This analog input is always connected to its pin.

P2.31 — General purpose digital input/output pin.

D31 — External memory data line 31.

P2.31/D31/

AIN5

20^[2]

I/O

I

AIN5 — ADC, input 5. This analog input is always connected to its pin.

P3.0 to P3.31

I/O

Port 3 — Port 3 is a 32-bit bidirectional I/O port with individual direction

controls for each bit. The operation of port 3 pins depends upon the pin

function selected via the Pin Connect Block.

LPC2290_3

Product data sheet

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

Table 3.

Symbol

P3.0/A0

Pin description …continued

Type

I/O

O

Description

89^[5]

P3.0 — General purpose digital input/output pin.

A0 — External memory address line 0.

P3.1/A1

88^[5]

87^[5]

81^[5]

80^[5]

74^[5]

73^[5]

72^[5]

71^[5]

66^[5]

65^[5]

64^[5]

63^[5]

62^[5]

56^[5]

55^[5]

53^[5]

48^[5]

47^[5]

46^[5]

I/O

O

P3.1 — General purpose digital input/output pin.

A1 — External memory address line 1.

P3.2/A2

I/O

O

P3.2 — General purpose digital input/output pin.

A2 — External memory address line 2.

P3.3/A3

I/O

O

P3.3 — General purpose digital input/output pin.

A3 — External memory address line 3.

P3.4/A4

I/O

O

P3.4 — General purpose digital input/output pin.

A4 — External memory address line 4.

P3.5/A5

I/O

O

P3.5 — General purpose digital input/output pin.

A5 — External memory address line 5.

P3.6/A6

I/O

O

P3.6 — General purpose digital input/output pin.

A6 — External memory address line 6.

P3.7/A7

I/O

O

P3.7 — General purpose digital input/output pin.

A7 — External memory address line 7.

P3.8/A8

I/O

O

P3.8 — General purpose digital input/output pin.

A8 — External memory address line 8.

P3.9/A9

I/O

O

P3.9 — General purpose digital input/output pin.

A9 — External memory address line 9.

P3.10/A10

P3.11/A11

P3.12/A12

P3.13/A13

P3.14/A14

P3.15/A15

P3.16/A16

P3.17/A17

P3.18/A18

P3.19/A19

I/O

O

P3.10 — General purpose digital input/output pin.

A10 — External memory address line 10.

P3.11 — General purpose digital input/output pin.

A11 — External memory address line 11.

P3.12 — General purpose digital input/output pin.

A12 — External memory address line 12.

P3.13 — General purpose digital input/output pin.

A13 — External memory address line 13.

P3.14 — General purpose digital input/output pin.

A14 — External memory address line 14.

P3.15 — General purpose digital input/output pin.

A15 — External memory address line 15.

P3.16 — General purpose digital input/output pin.

A16 — External memory address line 16.

P3.17 — General purpose digital input/output pin.

A17 — External memory address line 17.

P3.18 — General purpose digital input/output pin.

A18 — External memory address line 18.

P3.19 — General purpose digital input/output pin.

A19 — External memory address line 19.

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

LPC2290_3

Product data sheet

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

Table 3.

Symbol

P3.20/A20

Pin description …continued

Type

I/O

O

Description

45^[5]

P3.20 — General purpose digital input/output pin.

A20 — External memory address line 20.

P3.21/A21

P3.22/A22

44^[5]

41^[5]

40^[5]

I/O

O

P3.21 — General purpose digital input/output pin.

A21 — External memory address line 21.

I/O

O

P3.22 — General purpose digital input/output pin.

A22 — External memory address line 22.

P3.23/A23/

XCLK

I/O

O

P3.23 — General purpose digital input/output pin.

A23 — External memory address line 23.

XCLK — Clock output.

P3.24/CS3

P3.25/CS2

P3.26/CS1

P3.27/WE

36^[5]

35^[5]

30^[5]

I/O

O

P3.24 — General purpose digital input/output pin.

CS3 — LOW-active Chip Select 3 signal.

(Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF)

P3.25 — General purpose digital input/output pin.

CS2 — LOW-active Chip Select 2 signal.

I/O

O

(Bank 2 addresses range 0x8200 0000 to 0x82FF FFFF)

P3.26 — General purpose digital input/output pin.

CS1 — LOW-active Chip Select 1 signal.

I/O

O

(Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF)

P3.27 — General purpose digital input/output pin.

WE — LOW-active Write enable signal.

29^[5]

28^[2]

I/O

O

P3.28/BLS3/

AIN7

I/O

O

P3.28 — General purpose digital input/output pin.

BLS3 — LOW-active Byte Lane Select signal (Bank 3).

AIN7 — ADC, input 7. This analog input is always connected to its pin.

P3.29 — General purpose digital input/output pin.

BLS2 — LOW-active Byte Lane Select signal (Bank 2).

AIN6 — ADC, input 6. This analog input is always connected to its pin.

P3.30 — General purpose digital input/output pin.

BLS1 — LOW-active Byte Lane Select signal (Bank 1).

P3.31 — General purpose digital input/output pin.

BLS0 — LOW-active Byte Lane Select signal (Bank 0).

TD1: CAN1 transmitter output.

I

P3.29/BLS2/

AIN6

27^[4]

I/O

O

I

P3.30/BLS1

P3.31/BLS0

97^[4]

96^[4]

I/O

O

I/O

O

TD1

22^[5]

O

RESET

135^[6]

I

External Reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

XTAL2

V_SS

142^[7]

141^[7]

I

Input to the oscillator circuit and internal clock generator circuits.

Output from the oscillator ampliﬁer.

O

I

3, 9, 26, 38,

54, 67, 79,

93, 103, 107,

111, 128

Ground: 0 V reference.

V_SSA

139

I

Analog ground: 0 V reference. This should nominally be the same voltage

as V_SS, but should be isolated to minimize noise and error.

LPC2290_3

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

Table 3.

Symbol

V_SSA(PLL)

Pin description …continued

Type

Description

138

I

PLL analog ground: 0 V reference. This should nominally be the same

voltage as V_SS, but should be isolated to minimize noise and error.

V_DD(1V8)

37, 110

143

I

1.8 V core power supply: This is the power supply voltage for internal

circuitry.

V_DDA(1V8)

Analog 1.8 V core power supply: This is the power supply voltage for

internal circuitry. This should be nominally the same voltage as V_DD(1V8)but

should be isolated to minimize noise and error.

V_DD(3V3)

2, 31, 39, 51,

57, 77, 94,

104, 112, 119

I

3.3 V pad power supply: This is the power supply voltage for the I/O ports.

V_DDA(3V3)

14

Analog 3.3 V pad power supply: This should be nominally the same voltage

as V_DD(3V3)but should be isolated to minimize noise and error.

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

[2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If conﬁgured for an input

function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns.

[3] Open-drain 5 V tolerant digital I/O I²C-bus 400 kHz speciﬁcation compatible pad. It requires external pull-up to provide an output

functionality.

[4] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If conﬁgured

for a digital input function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns. When conﬁgured as an ADC input,

digital section of the pad is disabled.

[5] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

The pull-up resistor’s value ranges from 60 kΩ to 300 kΩ.

[6] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.

[7] Pad provides special analog functionality.

LPC2290_3

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

6. Functional description

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on RISC

principles, and the instruction set and related decode mechanism are much simpler than

those of microprogrammed CISC. This simplicity results in a high instruction throughput

and impressive real-time interrupt response from a small and cost-effective processor

core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set.

• A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

6.2 On-chip SRAM

On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed

as 8-bit, 16-bit, and 32-bit. The LPC2290 provides 16 kB of SRAM and the LPC2290/01

provides 64 kB of SRAM.

6.3 Memory map

The LPC2290 memory maps incorporate several distinct regions, as shown in Figure 3.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either

on-chip bootloader, external memory BANK0 or on-chip static RAM. This is described in

Section 6.18 “System control”.

LPC2290_3

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LPC2290

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16/32-bit ARM microcontroller with external memory interface

4.0 GB

3.75 GB

3.5 GB

0xFFFF FFFF

AHB PERIPHERALS

0xF000 0000

0xEFFF FFFF

VPB PERIPHERALS

0xE000 0000

0xDFFF FFFF

RESERVED ADDRESS SPACE

3.0 GB

0x8400 0000

0x83FF FFFF

EXTERNAL MEMORY BANK3

0x8300 0000

0x82FF FFFF

EXTERNAL MEMORY BANK2

0x8200 0000

0x81FF FFFF

EXTERNAL MEMORY BANK1

0x8100 0000

0x80FF FFFF

EXTERNAL MEMORY BANK0

0x8000 0000

0x7FFF FFFF

2.0 GB

BOOT BLOCK (RE-MAPPED FROM

ON-CHIP ROM MEMORY

0x7FFF E000

0x7FFF DFFF

RESERVED ADDRESS SPACE

0x4001 0000

0x4000 FFFF

64 KBYTE ON-CHIP STATIC RAM (/01 ONLY)

16 KBYTE ON-CHIP STATIC RAM

0x4000 4000

0x4000 3FFF

0x4000 0000

0x3FFF FFFF

1.0 GB

RESERVED ADDRESS SPACE

0x0000 0000

002aaa798

0.0 GB

Fig 3. LPC2290 and LPC2290/01 memory map

6.4 Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and

categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and

non-vectored IRQ as deﬁned by programmable settings. The programmable assignment

scheme means that priorities of interrupts from the various peripherals can be dynamically

assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC

combines the requests to produce the FIQ signal to the ARM processor. The fastest

possible FIQ latency is achieved when only one request is classiﬁed as FIQ, because then

the FIQ service routine can simply start dealing with that device. But if more than one

request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC

that identiﬁes which FIQ source(s) is (are) requesting an interrupt.

LPC2290_3

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LPC2290

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16/32-bit ARM microcontroller with external memory interface

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned

to this category. Any of the interrupt requests can be assigned to any of the 16 vectored

IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a

register from the VIC and jumping there. If any of the vectored IRQs are requesting, the

VIC provides the address of the highest-priority requesting IRQs service routine,

otherwise it provides the address of a default routine that is shared by all the non-vectored

IRQs. The default routine can read another VIC register to see what IRQs are active.

6.4.1 Interrupt sources

Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has

one interrupt line connected to the VIC, but may have several internal interrupt ﬂags.

Individual interrupt ﬂags may also represent more than one interrupt source.

Table 4.

Block

Interrupt sources

Flag(s)

VIC channel #

WDT

Watchdog Interrupt (WDINT)

0

1

2

3

4

-

Reserved for software interrupts only

EmbeddedICE, DbgCommRx

ARM Core

Timer 0

EmbeddedICE, DbgCommTx

Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

RX Line Status (RLS)

Timer 1

UART0

5

6

Transmit Holding Register Empty (THRE)

RX Data Available (RDA)

Character Time-out Indicator (CTI)

Auto-Baud Time-Out (ABTO) (available in LPC2290/01 only)

End of Auto-Baud (ABEO)

UART1

RX Line Status (RLS)

7

Transmit Holding Register empty (THRE)

RX Data Available (RDA)

Character Time-out Indicator (CTI)

Modem Status Interrupt (MSI)

Auto-Baud Time-Out (ABTO) (available in LPC2290/01 only)

End of Auto-Baud (ABEO)

PWM0

I²C-bus

SPI0

Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)

SI (state change)

8

9

SPIF, MODF

10

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16/32-bit ARM microcontroller with external memory interface

Table 4.

Interrupt sources …continued

Flag(s)

Block

VIC channel #

SPI1/SSP

Source: SPI1 SPI Interrupt Flag (SPIF), Mode Fault (MODF) 11

Source: SSP (available in LPC2290/01 only)

TX FIFO at least half empty (TXRIS)

RX FIFO at least half full (RXRIS)

Receive Timeout condition (RTRIS)

Receive Overrun (RORRIS)

PLL

PLL Lock (PLOCK)

12

RTC

RTCCIF (Counter Increment), RTCALF (Alarm)

13

System Control External Interrupt 0 (EINT0)

External Interrupt 1 (EINT1)

14

15

External Interrupt 2 (EINT2)

16

External Interrupt 3 (EINT3)

17

A/D

ADC

18

CAN

1 ORed CAN Acceptance Filter

CAN1 (TX int, RX int)

CAN2 (TX int, RX int)

19

20, 21

22, 23

6.5 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Conﬁguration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any

enabled peripheral function that is not mapped to a related pin should be considered

undeﬁned.

6.6 External memory controller

The external Static Memory Controller is a module which provides an interface between

the system bus and external (off-chip) memory devices. It provides support for up to four

independently conﬁgurable memory banks (16 MB each with byte lane enable control)

simultaneously. Each memory bank is capable of supporting SRAM, ROM, ﬂash EPROM,

burst ROM memory, or some external I/O devices.

Each memory bank may be 8-bit, 16-bit, or 32-bit wide.

6.7 General purpose parallel I/O and Fast I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

GPIO registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

6.7.1 Features

• Direction control of individual bits.

• Separate control of output set and clear.

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16/32-bit ARM microcontroller with external memory interface

• All I/O default to inputs after reset.

6.7.2 Fast I/O features available in LPC2290/01 only

• Fast I/O registers are located on the ARM local bus for the fastest possible I/O timing.

• All GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

• Mask registers allow single instruction to set or clear any number of bits in one port.

6.8 10-bit ADC

The LPC2290 each contain a single 10-bit successive approximation ADC with eight

multiplexed channels.

6.8.1 Features

• Measurement range of 0 V to 3.3 V.

• Capable of performing more than 400000 10-bit samples per second.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or Timer Match signal.

6.8.2 ADC features available in LPC2290/01 only

• Every analog input has a dedicated result register to reduce interrupt overhead.

• Every analog input can generate an interrupt once the conversion is completed.

6.9 CAN controllers and acceptance ﬁlter

The LPC2290 contains two CAN controllers. The CAN is a serial communications protocol

which efﬁciently supports distributed real-time control with a very high level of security. Its

domain of application ranges from high-speed networks to low cost multiplex wiring.

6.9.1 Features

• Data rates up to 1 Mbit/s on each bus.

• 32-bit register and RAM access.

• Compatible with CAN speciﬁcation 2.0B, ISO 11898-1.

• Global Acceptance Filter recognizes 11-bit and 29-bit RX identiﬁers for all CAN buses.

• Acceptance Filter can provide FullCAN-style automatic reception for selected

Standard identiﬁers.

• Full CAN messages can generate interrupts.

6.10 UARTs

The LPC2290 contains two UARTs. In addition to standard transmit and receive data

lines, UART1 also provides a full modem control handshake interface.

6.10.1 Features

• 16 B Receive and Transmit FIFOs.

LPC2290_3

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16/32-bit ARM microcontroller with external memory interface

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in baud rate generator.

• Standard modem interface signals included on UART1.

6.10.2 UART features available in LPC2290/01 only

• The transmission FIFO control enables implementation of software (XON/XOFF) ﬂow

control on both UARTs and hardware (CTS/RTS) ﬂow control on UART1 only.

• Fractional baud rate generator enables standard baud rates such as 115200 to be

achieved with any crystal frequency above 2 MHz.

• Auto-bauding.

• Auto-CTS/RTS ﬂow-control fully implemented in hardware.

6.11 I²C-bus serial I/O controller

The I²C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C-bus is a multi-master bus, it can be

controlled by more than one bus master connected to it.

The I²C-bus implemented in LPC2290 supports bit rate up to 400 kbit/s (Fast I²C-bus).

6.11.1 Features

• Compliant with standard I²C-bus interface.

• Easy to conﬁgure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus may be used for test and diagnostic purposes.

6.12 SPI serial I/O controller

The LPC2290 contains two SPIs. The SPI is a full duplex serial interface, designed to be

able to handle multiple masters and slaves connected to a given bus. Only a single master

and a single slave can communicate on the interface during a given data transfer. During a

data transfer the master always sends a byte of data to the slave, and the slave always

sends a byte of data to the master.

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6.12.1 Features

• Compliant with SPI speciﬁcation.

• Synchronous, serial, full duplex, communication.

• Combined SPI master and slave.

• Maximum data bit rate of one eighth of the input clock rate.

6.13 SSP serial I/O controller (available in LPC2290/01 only)

The LPC2290/01 contains one Serial Synchronous Port controller (SSP). The SSP

controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact

with multiple masters and slaves on the bus. However, only a single master and a single

slave can communicate on the bus during a given data transfer. The SSP supports full

duplex transfers, with frames of 4 bits to 16 bits of data ﬂowing from the master to the

slave and from the slave to the master. Often only one of these data ﬂows carries

meaningful data.

The SSP and SPI1 share the same pins on LPC2290/01. After a reset, SPI1 is enabled

and SSP is disabled.

6.13.1 Features

• Synchronous Serial Communication.

• 8-frame FIFOs for both transmit and receive.

• Compatible with Motorola SPI, 4-wire TI SSI and National Semiconductor Microwire

buses.

• Master or slave operation.

• Four bits to 16 bits per SPI frame.

6.14 General purpose timers

The TIMER0 and TIMER1 are designed to count cycles of the peripheral clock (PCLK)

and optionally generate interrupts or perform other actions at speciﬁed timer values,

based on four match registers. It also includes four capture inputs to trap the timer value

when an input signal transitions, optionally generating an interrupt. Multiple pins can be

selected to perform a single capture or match function, providing an application with ‘or’

and ‘and’, as well as ‘broadcast’ functions among them.

6.14.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit prescaler.

• Four 32-bit capture channels per timer that can take a snapshot of the timer value

when an input signal transitions. A capture event may also optionally generate an

interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

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• Four external outputs per timer corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

6.14.2 Timer features available in LPC2290/01 only

• Timers can count cycles of the externally supplied clock providing external event

counting functionality

6.15 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

6.15.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect/incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal pre-scaler.

• Selectable time period from (T_cy(PCLK)× 256 × 4) to (T_cy(PCLK)× 2³²× 4) in multiples of

T

_cy(PCLK)× 4.

6.16 Real-time clock

The Real-Time Clock (RTC) is designed to provide a set of counters to measure time

when normal or idle operating mode is selected. The RTC has been designed to use little

power, making it suitable for battery powered systems where the CPU is not running

continuously (Idle mode).

6.16.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra-low power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

• Programmable Reference Clock Divider allows adjustment of the RTC to match

various crystal frequencies.

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

6.17 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2290. The Timer is designed to count

cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other

actions when speciﬁed timer values occur, based on seven match registers. The PWM

function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires three

non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (MR0) controls the PWM cycle rate, by resetting the count upon match.

The other match register controls the PWM edge position. Additional single edge

controlled PWM outputs require only one match register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a

rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.

Again, the MR0 match register controls the PWM cycle rate. The other match registers

control the two PWM edge positions. Additional double edge controlled PWM outputs

require only two match registers each, since the repetition rate is the same for all PWM

outputs.

With double edge controlled PWM outputs, speciﬁc match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

6.17.1 Features

• Seven match registers allow up to six single edge controlled or three double edge

controlled PWM outputs, or a mix of both types.

• The match registers also allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the

output is a constant LOW. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

• Pulse period and width can be any number of timer counts. This allows complete

ﬂexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

LPC2290_3

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

• Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must ‘release’ new match values before they can become

effective.

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit prescaler.

6.18 System control

6.18.1 Crystal oscillator

The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output

frequency is called f_oscand the ARM processor clock frequency is referred to as CCLK for

purposes of rate equations, etc. f_oscand CCLK are the same value unless the PLL is

running and connected. Refer to Section 6.18.2 “PLL” for additional information.

6.18.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled

Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the

multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper

frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so

there is an additional divider in the loop to keep the CCO within its frequency range while

the PLL is providing the desired output frequency. The output divider may be set to divide

by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,

it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed

following a chip reset and may be enabled by software. The program must conﬁgure and

activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The

PLL settling time is 100 µs.

6.18.3 Reset and wake-up timer

Reset has two sources on the LPC2290: the RESET pin and watchdog reset. The RESET

pin is a Schmitt trigger input pin with an additional glitch ﬁlter. Assertion of chip reset by

any source starts the Wake-up Timer (see Wake-up Timer description below), causing the

internal chip reset to remain asserted until the external reset is de-asserted, the oscillator

is running, a ﬁxed number of clocks have passed, and the on-chip ﬂash controller has

completed its initialization.

When the internal reset is removed, the processor begins executing at address 0, which is

the reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

The Wake-up Timer ensures that the oscillator and other analog functions required for

chip operation are fully functional before the processor is allowed to execute instructions.

This is important at power-on, all types of reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the Wake-up Timer.

LPC2290_3

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufﬁcient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of V_DDramp (in the case of power-on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.18.4 External interrupt inputs

The LPC2290 include up to nine edge or level sensitive External Interrupt Inputs as

selectable pin functions. When the pins are combined, external events can be processed

as four independent interrupt signals. The External Interrupt Inputs can optionally be used

to wake up the processor from Power-down mode.

6.18.5 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

ﬂash memory, or to the on-chip static RAM. This allows code running in different memory

spaces to have control of the interrupts.

6.18.6 Power control

The LPC2290 support two reduced power modes: Idle mode and Power-down mode. In

Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may generate interrupts to

cause the processor to resume execution. Idle mode eliminates power used by the

processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a reset or certain speciﬁc interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings.

6.18.7 APB bus

The APB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The APB divider serves two purposes. The ﬁrst

is to provide peripherals with the desired PCLK via APB bus so that they can operate at

the speed chosen for the ARM processor. In order to achieve this, the APB bus may be

slowed down to ¹⁄₂to ¹⁄₄of the processor clock rate. Because the APB bus must work

properly at power-up (and its timing cannot be altered if it does not work since the APB

divider control registers reside on the APB bus), the default condition at reset is for the

APB bus to run at ¹⁄₄of the processor clock rate. The second purpose of the APB divider

is to allow power savings when an application does not require any peripherals to run at

the full processor rate. Because the APB divider is connected to the PLL output, the PLL

remains active (if it was running) during Idle mode.

LPC2290_3

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

6.19 Emulation and debugging

The LPC2290 support emulation and debugging via a JTAG serial port. A trace port

allows tracing program execution. Debugging and trace functions are multiplexed only with

GPIOs on Port 1. This means that all communication, timer and interface peripherals

residing on Port 0 are available during the development and debugging phase as they are

when the application is run in the embedded system itself.

6.19.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the remote

debug protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a Debug Communication Channel function built-in. The debug

communication channel allows a program running on the target to communicate with the

host debugger or another separate host without stopping the program ﬂow or even

entering the debug state. The debug communication channel is accessed as a

coprocessor 14 by the program running on the ARM7TDMI-S core. The debug

communication channel allows the JTAG port to be used for sending and receiving data

without affecting the normal program ﬂow. The debug communication channel data and

control registers are mapped in to addresses in the EmbeddedICE logic.

6.19.2 Embedded trace

Since the LPC2290 has signiﬁcant amounts of on-chip memory, it is not possible to

determine how the processor core is operating simply by observing the external pins. The

Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply

embedded processor cores. It outputs information about processor execution to the trace

port.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It

compresses the trace information and exports it through a narrow trace port. An external

trace port analyzer must capture the trace information under software debugger control.

Instruction trace (or PC trace) shows the ﬂow of execution of the processor and provides a

list of all the instructions that were executed. Instruction trace is signiﬁcantly compressed

by only broadcasting branch addresses as well as a set of status signals that indicate the

pipeline status on a cycle by cycle basis. Trace information generation can be controlled

by selecting the trigger resource. Trigger resources include address comparators,

counters and sequencers. Since trace information is compressed the software debugger

requires a static image of the code being executed. Self-modifying code can not be traced

because of this restriction.

6.19.3 RealMonitor

RealMonitor is a conﬁgurable software module, developed by ARM Inc., which enables

real-time debug. It is a lightweight debug monitor that runs in the background while users

debug their foreground application. It communicates with the host using the DCC (Debug

Communications Channel), which is present in the EmbeddedICE logic. The LPC2290

contain a speciﬁc conﬁguration of RealMonitor software programmed into the on-chip

ﬂash memory.

LPC2290_3

Product data sheet

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

7. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

V_DD(1V8)

V_DD(3V3)

V_DDA(3V3)

V_IA

Parameter

Conditions

internal rail

external rail

Min

−0.5

-

Max

Unit

V

supply voltage (1.8 V)

supply voltage (3.3 V)

analog supply voltage (3.3 V)

analog input voltage

input voltage

+2.5

+3.6

V

+4.6

V

+5.1

V

[2][3]

[2][4]

[5]

V_I

5 V tolerant I/O pins

other I/O pins

+6.0

V

V_DD(3V3)+ 0.5

100

V

I_DD

supply current

per supply pin

mA

°C

W

[5]

I_SS

ground current

per ground pin

-

100

[6]

T_stg

storage temperature

−65

-

+150

1.5

P_tot(pack)

total power dissipation (per

package)

based on package heat

transfer, not device power

consumption

[7]

V_esd

electrostatic discharge voltage human body model; all

pins

−2000

+2000

V

[1] The following applies to Table 5:

a) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] Only valid when the V_DD(3V3)supply voltage is present.

[4] Not to exceed 4.6 V.

[5] The peak current is limited to 25 times the corresponding maximum current.

[6] Dependent on package type.

[7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

8. Static characteristics

Table 6.

Static characteristics

T_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol Parameter

Conditions

internal rail

external rail

Min

1.65

3.0

Typ^[1]

1.8

Max

1.95

3.6

Unit

V

V_DD(1V8)supply voltage (1.8 V)

V_DD(3V3)supply voltage (3.3 V)

3.3

V

V_DDA(3V3)analog supply voltage

(3.3 V)

2.5

3.3

3.6

V

Standard port pins, RESET, RTCK

I_IL

LOW-level input current

V_I= 0 V; no pull-up

-

3

µA

I_IH

I_OZ

HIGH-level input current V_I= V_DD(3V3); no pull-down

OFF-state output current V_O= 0 V, V_O= V_DD(3V3)

;

no pull-up/down

I_latch

I/O latch-up current

−(0.5V_DD(3V3)) < V_I<

100

-

mA

(1.5V_DD(3V3)); T_j< 125 °C

[2][3][4]

V_I

input voltage

0

-

5.5

V

V_O

output voltage

output active

0

-

V_DD(3V3)

V

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

2.0

-

V

-

0.8

V

V_hys

V_OH

V_OL

I_OH

I_OL

-

0.4

-

V

[5]

[6]

HIGH-level output voltage I_OH= −4 mA

LOW-level output voltage I_OL= −4 mA

HIGH-level output current V_OH= V_DD(3V3)− 0.4 V

LOW-level output current V_OL= 0.4 V

V_DD(3V3)− 0.4 -

-

V

-

0.4

-

V

−4

4

-

mA

-

I_OHS

HIGH-level short-circuit

output current

V_OH= 0 V

−45

[6]

I_OLS

LOW-level short-circuit

output current

V_OL= V_DD(3V3)

-

50

mA

[7]

[8]

[7]

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

10

−15

0

50

−50

0

150

−85

0

µA

mA

V_I= 0 V

V_DD(3V3)< V_I< 5 V

I_DD(act)

active mode supply

current

V_DD(1V8)= 1.8 V,

CCLK = 60 MHz,

-

50

-

T

_amb= 25 °C, code

while(1){}

executed from ﬂash, no

active peripherals

I_DD(pd)

Power-down mode supply V_DD(1V8)= 1.8 V,

current _amb= 25 °C,

-

10

-

µA

T

V_DD(1V8)= 1.8 V,

_amb= 85 °C

110

300

500

1000

T

V_DD(1V8)= 1.8 V,

_amb= 125 °C

T

LPC2290_3

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

Table 6.

Static characteristics …continued

T_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol Parameter

I²C-bus pins

Conditions

Min

Typ^[1]

Max

Unit

V_IH

V_IL

V_hys

V_OL

I_LI

HIGH-level input voltage

0.7V_DD(3V3)

-

V

LOW-level input voltage

hysteresis voltage

-

0.3V_DD(3V3)

V

0.5V_DD(3V3)

-

V

[5]

LOW-level output voltage I_OLS= 3 mA

input leakage current V_I= V_DD(3V3); to V_SS

V_I= 5 V

-

0.4

4

V

2

µA

10

22

Oscillator pins

V_i(XTAL1)input voltage on pin

XTAL1

0

-

1.8

V

V_o(XTAL2)output voltage on pin

XTAL2

[1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 °C), nominal supply voltages.

[2] Including voltage on outputs in 3-state mode.

[3] V_DD(3V3)supply voltages must be present.

[4] 3-state outputs go into 3-state mode when V_DD(3V3)is grounded.

[5] Accounts for 100 mV voltage drop in all supply lines.

[6] Only allowed for a short time period.

[7] Minimum condition for V_I= 4.5 V, maximum condition for V_I= 5.5 V.

[8] Applies to P1[25:16].

LPC2290_3

Product data sheet

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

Table 7.

ADC static characteristics

V_DDA= 2.5 V to 3.6 V; T_amb= −40 °C to +125 °C unless otherwise speciﬁed. ADC frequency 4.5 MHz.

Symbol

V_IA

Parameter

Conditions

Min

Typ

Max

V_DDA

1

Unit

V

analog input voltage

0

-

C_ia

analog input

capacitance

pF

E_D

differential linearity

error

-

±1

LSB

[1][2][3]

[1][4]

[1][5]

[1][6]

[1][7]

E_L(adj)

E_O

integral non-linearity

offset error

-

±2

LSB

%

±3

E_G

gain error

±0.5

±4

E_T

absolute error

LSB

[1] Conditions: V_SSA= 0 V, V_DDA= 3.3 V.

[2] The ADC is monotonic, there are no missing codes.

[3] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width. See Figure 4.

[4] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 4.

[5] The offset error (E_O) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 4.

[6] The gain error (E_G) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 4.

[7] The absolute voltage error (E_T) is the maximum difference between the center of the steps of the actual transfer curve of the

non-calibrated ADC and the ideal transfer curve. See Figure 4.

LPC2290_3

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

gain

error

offset

error

E

O

G

1023

1022

1021

1020

1019

1018

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

1018 1019 1020 1021 1022 1023 1024

1

2

3

4

5

6

7

V

IA

(LSB

)

ideal

V

− V

SSA

DDA

1 LSB =

offset

error

1024

002aaa668

E

O

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 4. ADC characteristics

LPC2290_3

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

9. Dynamic characteristics

Table 8.

Dynamic characteristics

T_amb= −40 °C to +125 °C; V_DD(1V8), V_DD(3V3)over speciﬁed ranges.^[1]

Symbol

External clock

f_osc

Parameter

Conditions

Min

Typ

Max

Unit

oscillator frequency

supplied by an external

oscillator (signal generator)

1

-

50

30

MHz

external clock frequency

supplied by an external

crystal oscillator

external clock frequency if

on-chip PLL is used

10

-

25

MHz

external clock frequency if

on-chip bootloader is used

for initial code download

T_cy(clk)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

clock cycle time

clock HIGH time

clock LOW time

clock rise time

clock fall time

20

-

1000

ns

T

-

_cy(clk)× 0.4

-

_cy(clk)× 0.4

-

5

-

Port pins (except P0.2 and P0.3)

t_r

t_f

rise time

-

10

-

ns

fall time

I²C-bus pins (P0.2 and P0.3)

[2]

t_ffall time

V_IHto V_IL

20 + 0.1 × C_b

-

ns

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Bus capacitance C_bin pF, from 10 pF to 400 pF.

LPC2290_3

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

Table 9.

External memory interface dynamic characteristics

C_L= 25 pF, T_amb= 40 °C

Symbol

Parameter

Conditions

Min

Typ Max

Unit

Common to read and write cycles

t_CHAV

XCLK HIGH to address valid

time

-

10

ns

t_CHCSL

t_CHCSH

XCLK HIGH to CS LOW time

-

10

ns

XCLK HIGH to CS HIGH

time

t_CHANV

XCLK HIGH to address

invalid time

-

10

ns

Read cycle parameters

t_CSLAVCS LOW to address valid

[1]

−5

-

+10

ns

time

t_OELAV

OE LOW to address valid

time

t_CSLOEL

t_am

CS LOW to OE LOW time

memory access time

-

+5

-

ns

[2][3]

[2][4]

[5]

(T_cy(CCLK)× (2 + WST1)) +

(−20)

t_am(ibr)

t_am(sbr)

memory access time (initial

burst-ROM)

(T_cy(CCLK)× (2 + WST1)) +

(−20)

-

ns

memory access time

T_cy(CCLK)+ (−20)

(subsequent burst-ROM)

t_h(D)

data hold time

0

-

ns

t_CSHOEH

t_OEHANV

CS HIGH to OE HIGH time

−5

+5

OE HIGH to address invalid

time

t_CHOEL

t_CHOEH

XCLK HIGH to OE LOW time

−5

-

+5

ns

XCLK HIGH to OE HIGH

time

Write cycle parameters

[1]

t_AVCSL

address valid to CS LOW

T

_cy(CCLK)− 10

-

ns

time

t_CSLDV

CS LOW to data valid time

CS LOW to WE LOW time

CS LOW to BLS LOW time

WE LOW to data valid time

CS LOW to data valid time

WE LOW to WE HIGH time

−5

-

+5

ns

t_CSLWEL

t_CSLBLSL

t_WELDV

t_CSLDV

[2]

t_WELWEH

T

_cy(CCLK)× (1 + WST2) − 5

_cy(CCLK)− 5

T

_cy(CCLK)× (1 +

WST2) + 5

t_BLSLBLSHBLS LOW to BLS HIGH time

-

T_cy(CCLK)

(1 + WST2) + 5

×

ns

t_WEHANV

t_WEHDNV

WE HIGH to address invalid

time

T_cy(CCLK)+ 5

[2]

WE HIGH to data invalid time

(2 × T_cy(CCLK)) − 5

T_cy(CCLK)− 5

-

(2 × T_cy(CCLK)) + 5 ns

T_cy(CCLK)+ 5 ns

t_BLSHANVBLS HIGH to address invalid

time

LPC2290_3

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LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

Table 9.

External memory interface dynamic characteristics …continued

C_L= 25 pF, T_amb= 40 °C

Symbol

Parameter

Conditions

Min

Typ Max

Unit

[2]

t_BLSHDNVBLS HIGH to data invalid

time

(2 × T_cy(CCLK)) − 5

-

(2 × T_cy(CCLK)) + 5 ns

t_CHDV

XCLK HIGH to data valid

time

-

10

ns

t_CHWEL

t_CHBLSL

t_CHWEH

t_CHBLSH

t_CHDNV

XCLK HIGH to WE LOW

time

XCLK HIGH to BLS LOW

time

XCLK HIGH to WE HIGH

time

XCLK HIGH to BLS HIGH

time

XCLK HIGH to data invalid

time

[1] Except on initial access, in which case the address is set up T_cy(CCLK)earlier.

[2] T_cy(CCLK)= ¹⁄_CCLK.

[3] Latest of address valid, CS LOW, OE LOW to data valid.

[4] Address valid to data valid.

[5] Earliest of CS HIGH, OE HIGH, address change to data invalid.

Table 10. Standard read access speciﬁcations

Access cycle

Max frequency

WST setting

Memory access time requirement

WST ≥ 0; round up to

integer

standard read

2 + WST1

_RAM+ 20 ns

t

_RAM+ 20 ns

t_RAM≤ t_cy(CCLK)× (2 + WST1) – 20 ns

f _MAX

≤

--------------------------------

WST1 ≥

WST2 ≥

– 2

--------------------------------

t_cy(CCLK)

t

standard write

1 + WST2

t

_WRITE– t_CYC+ 5

t_WRITE≤ t_cy(CCLK)× (1 + WST2) – 5 ns

t_INIT≤ t_cy(CCLK)× (2 + WST1) – 20 ns

---------------------------------

-------------------------------------------

t

_WRITE+ 5 ns

t_cy(CCLK)

burst read - initial

burst read - subsequent 3×

2 + WST1

t_INIT+ 20 ns

-------------------------------

WST1 ≥

– 2

-------------------------------

t_INIT+ 20 ns

t_cy(CCLK)

N/A

1

t

_ROM≤ t_cy(CCLK)– 20 ns

--------------------------------

t_ROM+ 20 ns

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

33 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

9.1 Timing

XCLK

t

CSHOEH

CSLAV

CS

addr

data

t

h(D)

am

t

CSLOEL

t

OEHANV

OELAV

OE

t

CHOEH

CHOEL

002aaa749

Fig 5. External memory read access

XCLK

CS

t

CSLDV

t

AVCSL

t

WELWEH

t

CSLWEL

t

BLSLBLSH

BLS/WE

t

WEHANV

t

WELDV

CSLBLSL

t

BLSHANV

addr

data

t

WEHDNV

BLSHDNV

t

CSLDV

OE

002aaa750

Fig 6. External memory write access

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

34 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

V

DD

− 0.5 V

0.2V

+ 0.9 V

DD

0.2V

− 0.1 V

DD

0.45 V

t

CHCX

t

CHCL

CLCX

CLCH

T

cy(clk)

002aaa907

Fig 7. External clock timing

9.2 LPC2290 power consumption measurements

002aab452

60

I

current

DD

(mA)

(1)

(2)

40

20

0

10

20

30

40

50

60

frequency (MHz)

Test conditions: code executed from on-chip RAM; all peripherals are enabled in PCONP register; PCLK = ^CCLK⁄₄.

(1) 1.8 V core at 25 °C (typical)

(2) 1.65 V core at 25 °C (typical)

Fig 8. LPC2290 I_DD(act)measured at different frequencies (CCLK) and temperatures

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

35 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

002aab453

15

I

current

DD

(mA)

10

(1)

(2)

5

0

10

20

30

40

50

60

frequency (MHz)

Test conditions: Idle mode entered executing code from on-chip RAM; all peripherals are enabled in PCONP register;

PCLK = ^CCLK⁄₄.

(1) 1.8 V core at 25 °C (typical)

(2) 1.65 V core at 25 °C (typical)

Fig 9. LPC2290 I_DDidle measured at different frequencies (CCLK) and temperatures

002aab454

500

I

current

(µA)

DD

(1)

(2)

(3)

400

300

200

100

0

−100

−50

0

50

100

150

temp (°C)

Test conditions: Power-down mode entered executing code from on-chip RAM; all peripherals are enabled in PCONP

register.

(1) 1.95 V core

(2) 1.8 V core

(3) 1.65 V core

Fig 10. LPC2290 I_DD(pd)measured at different temperatures

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

36 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

10. Package outline

LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm

SOT486-1

y

X

A

108

109

73

72

Z

E

e

H

A

E

2

A

E

(A )

3

A

1

θ

w M

p

L

p

b

L

pin 1 index

detail X

37

144

1

36

v

M

A

Z

w M

D

b

p

e

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 20.1 20.1

0.17 0.09 19.9 19.9

22.15 22.15

21.85 21.85

0.75

0.45

1.4

1.1

1.4

1.1

mm

1.6

0.25

1

0.2 0.08 0.08

0.5

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-03-14

03-02-20

SOT486-1

136E23

MS-026

Fig 11. Package outline SOT486-1 (LQFP144)

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

37 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

11. Abbreviations

Table 11. Abbreviations

Acronym

ADC

Description

Analog-to-Digital Converter

Advanced Microcontroller Bus Architecture

AMBA Peripheral Bus

AMBA

APB

CAN

Controller Area Network

CISC

CPU

Complex Instruction Set Computer

Central Processing Unit

FIFO

GPIO

PLL

First In, First Out

General Purpose Input/Output

Phase-Locked Loop

PWM

RAM

RISC

SPI

Pulse Width Modulator

Random Access Memory

Reduced Instruction Set Computer

Serial Peripheral Interface

Static Random Access Memory

Synchronous Serial Port

SRAM

SSP

TTL

Transistor-Transistor Logic

Universal Asynchronous Receiver/Transmitter

UART

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

38 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

12. Revision history

Table 12. Revision history

Document ID

LPC2290_3

Release date

20061116

Data sheet status

Change notice

Supersedes

Product data sheet

-

LPC2290-02

Modiﬁcations:

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• New features speciﬁc to the LPC2290/01 have been added throughout.

LPC2290-02

LPC2290-01

20041223

Product data

-

LPC2290-01

20040209

Preliminary data

-

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

39 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

13. Legal information

13.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

result in personal injury, death or severe property or environmental damage.

13.2 Deﬁnitions

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

13.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

I²C-bus — logo is a trademark of NXP B.V.

14. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

LPC2290_3

Product data sheet

Rev. 03 — 16 November 2006

40 of 41

LPC2290

NXP Semiconductors

16/32-bit ARM microcontroller with external memory interface

15. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

6.17.1

6.18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

System control . . . . . . . . . . . . . . . . . . . . . . . . 23

Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 23

PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Reset and wake-up timer . . . . . . . . . . . . . . . . 23

External interrupt inputs. . . . . . . . . . . . . . . . . 24

Memory mapping control . . . . . . . . . . . . . . . . 24

Power control . . . . . . . . . . . . . . . . . . . . . . . . . 24

APB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Emulation and debugging. . . . . . . . . . . . . . . . 25

EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 25

Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 25

RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2

2.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Enhancements introduced with LPC2290/01

device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key features common for LPC2290 and

6.18.1

6.18.2

6.18.3

6.18.4

6.18.5

6.18.6

6.18.7

6.19

2.2

LPC2290/01 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3

3.1

4

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.19.1

6.19.2

6.19.3

6

6.1

6.2

6.3

6.4

6.4.1

6.5

6.6

6.7

Functional description . . . . . . . . . . . . . . . . . . 14

Architectural overview. . . . . . . . . . . . . . . . . . . 14

On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 14

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14

Interrupt controller . . . . . . . . . . . . . . . . . . . . . 15

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 16

Pin connect block . . . . . . . . . . . . . . . . . . . . . . 17

External memory controller. . . . . . . . . . . . . . . 17

General purpose parallel I/O and Fast I/O . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Fast I/O features available in LPC2290/01

only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ADC features available in LPC2290/01 only. . 18

CAN controllers and acceptance ﬁlter . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

UART features available in LPC2290/01 only. 19

I²C-bus serial I/O controller . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SPI serial I/O controller. . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SSP serial I/O controller (available in

7

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 26

Static characteristics . . . . . . . . . . . . . . . . . . . 27

9

9.1

9.2

Dynamic characteristics. . . . . . . . . . . . . . . . . 31

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

LPC2290 power consumption measurements 35

10

11

12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 37

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38

Revision history . . . . . . . . . . . . . . . . . . . . . . . 39

6.7.1

6.7.2

13

Legal information . . . . . . . . . . . . . . . . . . . . . . 40

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 40

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40

13.1

13.2

13.3

13.4

6.8

6.8.1

6.8.2

6.9

6.9.1

6.10

6.10.1

6.10.2

6.11

6.11.1

6.12

14

15

Contact information . . . . . . . . . . . . . . . . . . . . 40

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.12.1

6.13

LPC2290/01 only). . . . . . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

General purpose timers . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Timer features available in LPC2290/01 only . 21

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Pulse width modulator . . . . . . . . . . . . . . . . . . 22

6.13.1

6.14

6.14.1

6.14.2

6.15

6.15.1

6.16

6.16.1

6.17

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 16 November 2006

Document identifier: LPC2290_3


型号：	LPC2290FBD144/01,5
厂家：	NXP
描述：	LPC2290 - 16/32-bit ARM microcontroller with CAN, 10-bit ADC and external memory interface QFP 144-Pin 时钟 PC 外围集成电路
文件：	总41页 (文件大小：198K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC2290FBD144/01,5 [NXP]

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