MC100ES7011PDR2 [NXP]
100E SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, PLASTIC, SOIC-8;
| 型号： | MC100ES7011PDR2 |
| 厂家： | 
NXP |
| 描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, PLASTIC, SOIC-8 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总4页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
TECHNICAL DATA
Order number: MC100ES7011P
Rev 0, 05/2004
Product Preview
MC100ES7011P
Low Voltage 1:2 Differential PECL
Clock Fanout Buffer
The MC100ES7011P is a low voltage 1:2 Differential PECL to LVDS clock
fanout buffer. Designed for the most demanding clock distribution systems, the
MC100ES7011P supports various applications that require the distribution of
precisely aligned differential clock signals. Using SiGe technology and a fully
differential architecture, the device offers very low skew outputs and superior
digital signal characteristics. Target applications for this clock driver are in high
performance clock distribution in computing, networking and
1:2 DIFFERENTIAL PECL TO LVDS
CLOCK FANOUT DRIVER
telecommunication systems.
Features
•
•
•
•
•
•
•
•
•
1:2 differential clock fanout buffer
50 ps maximum device skew
D SUFFIX
8-LEAD SOIC PACKAGE
CASE 751-06
SiGe Technology
Supports DC to 1000 MHz operation
LVDS compatible differential clock outputs
PECL compatible differential clock inputs
3.3V power supply
ORDERING INFORMATION
Supports industrial temperature range
Standard 8 lead SOIC package
Device
Package
SO-8
MC100ES7011PD
MC100ES7011PDR2
SO-8
PIN DESCRIPTION
1
8
7
VCC
Q0
Q0
Q1
Pin
D, D
Function
ECL Data Inputs
LVDS Data Outputs
Positive Supply
Qn, Qn
VCC
2
D
D
VEE
Negative Supply
6
5
3
4
VEE
Q1
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
746
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MC100ES7011P
Table 1. General Specifications
Characteristics
Value
TBD
TBD
TBD
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
0 LFPM, 8 SOIC
TBD
θ
JA Thermal Resistance (Junction to Ambient)
500 LFPM, 8 SOIC
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Table 2. Absolute Maximum Ratings1
Symbol
Parameter
Power Supply Voltage
Conditions
Rating
Unit
VSUPPLY
Difference between VCC & VEE
3.9
V
VIN
Input Voltage
VCC – VEE ≤ 3.6V
VCC + 0.3
V
V
V
EE – 0.3
IOUT
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
Storage Temperature Range
–40 to +85
°C
°C
TSTG
–65 to +150
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Table 3. DC Characteristics (VCC = 3.3V±5%; TJ = 0°C to 110°C)1
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
PECL differential input signals (D, D)
VPP
Differential Input Voltage2
0.15
1.0
1.0
V
V
Differential Operation
Differential Operation
VCMR
Differential Cross Point Voltage3
V
CC – 0.6
VIH
VIL
IIN
Input High Voltage
Input Low Voltage
Input Current
VCC – 1.165
VCC – 1.810
VCC – 0.880
VCC – 1.475
±150
V
V
mA
VIN = VIH or VIN
LVDS clock outputs (Q[0:1], Q[0:1])
VPP
VOS
Output Differential Voltage (peak-to-peak)
Output Offset Voltage
250
mV
mV
LVDS
LVDS
1125
1275
TBD
Supply Current
ICC
VCC pin (core)
Maximum Quiescent Supply Current without
output termination current
TBD
mA
1. DC characteristics are design targets and pending characterization.
2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range
and the input swing lies within the VPP (DC) specification.
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
747
MC100ES7011P
Table 4. AC Characteristics (VCC = 3.3V±5%; TJ = 0°C to 110°C)1 2
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
PECL differential input signals (D, D)
VPP
Differential Input Voltage (peak-to-peak)3
0.2
1
1.0
V
V
VCMR
Differential Cross Point Voltage4
Input Frequency
VCC - 0.6
fCLK
tPD
1000
MHz
ps
Differential
Propagation Delay D to Q[0:1]
TBD
Differential
LVDS clock outputs (Q[0:1], Q[0:1])
tSK(O)
tSK(PP)
tJIT(CC)
DCO
Output-to-Output Skew
50
ps
ps
Differential
Differential
Output-to-Output Skew (part-to-part)
Output Cycle-to-Cycle Jitter
Output Duty Cycle
TBD
TBD
TBD
TBD
0.05
50
%
DCfref = 50%
20% to 80%
tr / tf
Output Rise/Fall Times
TBD
ns
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50Ω to VTT.
3. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew.
4. VCMR (AC) is the crosspoint of the differential PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)
range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP(AC) impacts the device propagation delay, device
and part-to-part skew.
748
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MC100ES7011P
ZO = 50Ω
ZO = 50Ω
Differential Pulse
Generator
Z = 50Ω
DUT
MC100ES7011P
RT = 50Ω
TT=GND
RT = 50Ω
V
VTT=GND
Figure 2. MC100ES7011P AC Test Reference
D
V
DIF=0.8V
VCMR=VCC–1.3V
D
Q[0–1]
Q[0–1]
tPD (D to Q[0–1])
Figure 3. MC100ES7011P AC Reference
Measurement Waveform (PECL Input)
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
749
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