MC33909Q3AD [NXP]
POWER SUPPLY MANAGEMENT CKT;
| 型号： | MC33909Q3AD |
| 厂家： | 
NXP |
| 描述： | POWER SUPPLY MANAGEMENT CKT |
| 文件： | 总94页 (文件大小：2482K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33909
Rev. 4.0, 8/2016
NXP Semiconductors
Advance Information
System basis chip with DC/DC and
multiple switch-to-ground interface
33909
This SMARTMOS IC integrates the common functionality of system basis chips
with switch detection inputs. The device works as an advanced power
management unit for the MCU and additional integrated circuits such as
sensors, CAN transceivers, and eXtreme switches. It has one built-in enhanced
high-speed CAN interface (ISO 11898-2 and -5), with local and bus failure
diagnostics, protection and fail-safe operation mode, and includes four LINs,
compatible with specification 2.1 and SAEJ2602-2.
SYSTEM BASIS CHIP
The IC starts operating when the VBATP (reverse battery protected) pin
reaches 5.3 V maximum. The device requires a reverse blocking ultrafast or
Schottky diode for operation. The VPRE supply operating in Buck/Boost mode
allows functional operation of the IC from 2.5 V to 35 V on VBATP. The VPRE
pin supplies the source voltage for the VDD, VAUX, CAN5V, and SG power
rails.
AD SUFFIX (PB-FREE)
48 PIN LQFP-EP
98ASA00737D
Switch-to-ground inputs are available for switch detection and supply
configurable pulsed wetting current, with low sustain current levels for
improved thermal and power management. The IC can be programmed to
wake-up when a change of state is detected on any input. The device also
implements an innovative and advanced fail-safe state machine and concept
solution.
Applications
• Front/rear body controllers
• Gateway modules
• Electric power steering
• Power train
Features
• VDD rail (3.3 V or 5.0 V) operates down to 2.5 V on VBATP (provided by
VPRE Buck/Boost)
• VAUX rail (3.3 V or 5.0 V) capable of surviving short-to-battery (40 V)
conditions
• Low Q current operation for low-power sleep mode, typ. 125 μA
• Secured SPI and advanced watchdog
• SAFE_B pin for limp home mode
• Six switch to GND inputs with selectable wake-up in change of state
• Analog multiplexer
VPRE VAUXE VAUXB
VSW VPREGATE
VAUX
VDDE
VBAT
BOOT
PI Filter
VBAT_SMPS
VDDB
VDD
VDD
VBATP
VBAT
VBATSNS
WDI
SAFE_B
AMUX
SG0
SG1
SG2
SG3
SG4
SG5
RST_B
INT_B
MCU
MOSI
MISO
SCLK
CS_B
SPI
CANH
CANL
CAN Bus
RXD_L0:RXD_L3
TXD_L0:TXD_L3
VBATP
RXD_C
TXD_C
LIN_0
LIN_1
LIN_2
LIN_3
LIN Bus
LIN Bus
LIN Bus
LIN Bus
CAN5V
GND LIN
GND
CANGND
Figure 1. 33909AD simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© 2016 NXP B.V.
ORDERABLE PARTS
1
Orderable parts
This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided
on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search
for the following device numbers.
Table 1. Orderable part variations
Temperature
VDD output
voltage
CAN
interface(s)
Switch to GND
inputs
LIN interface(s)
Part number
MC33909N5AD
Package
Notes
(T )
A
0
1
2
4
0
1
2
4
MC33909L5AD
MC33909D5AD
MC33909Q5AD
MC33909N3AD
MC33909L3AD
MC33909D3AD
MC33909Q3AD
Notes
5.0 V
3.3 V
7.0 x 7.0,
48 LQFP
exposed pad
(1)
-40 °C to 125 °C
1
6
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
33909
NXP Semiconductors
2
INTERNAL BLOCK DIAGRAM
2
Internal block diagram
BOOT VSW VPRE VPREGATE
VDDE
VDDB
VDD
Power Supply
VBATP_SMPS
VPRE Regulator
VDD Regulator
POR
Sleep State
Internal rails
Bandgap
VBATP
VAUXE
VAUXB
VAUX
VBATSNS
VAUX
Regulator
250 mV accuracy
Digital Control
Logic
SAFE_B
RESET_B
WDI
Fail-safe
Power Management
State Machine
Inputs
SG0
VPRE
VPRE
VPRE
CANH
CANL
6-20
mA
2.0
mA
1.0
mA
(Low-power
mode)
Enhanced High
Speed CAN
Physical
TXD_C
RXD_C
SG0
Interface
3.5 V REF
comparator
To SPI
SG1
SG2
CANGND
CAN5V
VPRE
5V CAN
Regulator
VPRE
VPRE
SG5
SG3
SG4
6-20
mA
2.0
mA
1.0
mA
(Low-power
mode)
TXD_Lx
RXD_Lx
SG5
Internal
2.5 V
3.5 V REF
comparator
LIN
Interface
To SPI
Temperature
Monitor and
Control
LINx
Internal
2.5 V
Internal
2.5 V
VPRE
VBATP
Oscillator and
Clock Control
VDD
40 µA
CS_B
SCLK
MOSI
MISO
SPI Interface
and Control
25
VDD
MUX
control
VDD
Internal
2.5 V
VDD
+
-
AMUX
INT_B
GND LIN
GND1/2
125 kΩ
Interrupt
Control
Figure 2. 33909AD simplified internal block diagram
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3
NXP Semiconductors
INTERNAL BLOCK DIAGRAM
2.1
Pin connections
Transparent Top View
VAUXE
VPRE
SG2
SG3
36
35
34
33
32
31
30
29
28
27
26
25
1
2
VAUXB
VAUX
SG4
3
LIN0
4
RXD_C
TXD_C
CANH
LIN1
5
GNDLIN
LIN3
6
EP
7
LIN2
CANL
8
SG5
GNDCAN
CAN5V
SAFE_B
MISO
9
AMUX
10
11
12
RST_B
TXD_L0
Figure 3. 33909AD pin connections
A functional description of each pin can be found in the Functional device operation section.
Table 2. 33909 pin definitions
Pin number
Pin name
Pin function
Definition
Exposed pad – connect to the ground plane
Switch to Ground inputs
–
EP
SG0 - SG5
LIN0
Ground
Input
1-3, 9, 47, 48
LIN0 bus input/output connected to the LIN bus
LIN1 bus input/output connected to the LIN bus
Ground for LIN 0 - 3 bus
4
5
6
7
8
Input/Output
Input/Output
Ground
LIN1
GND LIN
LIN3
LIN3 bus input/output connected to the LIN bus
LIN2 bus input/output connected to the LIN bus
Input/Output
Input/Output
LIN2
This is the device reset output whose main function is to reset the MCU. This pin has an internal pull-up
to VDD. RESET_B input voltage is also monitored in order to detect external reset and safe conditions.
11
RST_B
Input/Output
Analog multiplex output
10
12
AMUX
Output
Input
LIN0 bus transmit data input. Includes an internal pull-up resistor to VDD
TXD_L0
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NXP Semiconductors
4
INTERNAL BLOCK DIAGRAM
Table 2. 33909 pin definitions (continued)
Pin number
Pin name
Pin function
Definition
LIN0 bus receive data output
Watchdog inhibit
13
14
15
16
17
18
19
20
21
22
23
24
25
RXD_L0
WDI
Output
Input
Open drain output to the MCU is used to indicate an input switch change of state.
LIN1 bus transmit data input. Includes an internal pull-up resistor to VDD
LIN1 bus receive data output
INT_B
Output
TXD_L1
RXD_L1
RXD_L2
TXD_L2
TXD_L3
RXD_L3
MOSI
Input
Output
LIN2 bus receive data output
Output
LIN2 bus transmit data input. Includes an internal pull-up resistor to VDD
LIN3 bus transmit data input. Includes an internal pull-up resistor to VDD
LIN3 bus receive data output
Input
Input
Output
SPI control data input pin from the MCU
Input / SPI
Input / SPI
Input / SPI
Output / SPI
SPI control clock input pin
SCLK
SPI control chip select bar input pin. Logic [0] allows data to be transferred in.
Provides digital data from 33909 to the MCU
CS_B
MISO
Output of the safe circuitry. The pin is asserted LOW in case a safe condition is detected (e.g.: software
watchdog is not triggered, VDD low, issue on reset pin, etc.). Open drain structure.
26
SAFE_B
Output
Output voltage for the embedded CAN interface. A capacitor must be connected to this pin.
Power ground for the embedded CAN interface
CAN low output
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
CAN5V
GNDCAN
CANL
Output
Ground
Output
Output
Input
CAN high output
CANH
CAN bus transmit data input. Internal pull-up to VDD
CAN bus receive data output
TXD_C
RXD_C
VAUX
Output
Input
Output pin for the auxiliary voltage
Base connection for the external PNP transistor
Supply for VDD, VAUX, CAN5V, and SG Inputs
Collector connection for the external PNP transistor
Emitter connection for the external LDO
Base connection for the external LDO
VDD supply voltage
VAUXB
VPRE
Output
Input
VAUXE
VDDE
Input
Input
VDDB
Output
Input
VDD
Gate control for low-side FET
VPREGATE
GND
Output
Ground
Output
Input
Ground for logic and analog (GND1 and GND2)
Switching output
VSW
Boot capacitor to VSW
BOOT
Supply for SMPS power rail. This pin requires external reverse battery protection.
VBATP_SMPS
Power
Battery supply input pin. This pin requires external reverse battery protection. Supplies internal voltage
except SMPS.
45
46
VBATP
Power
Input
Battery sense input. A 1.0 kΩ external resistor required to pass battery transients.
VBATSNS
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NXP Semiconductors
ELECTRICAL CHARACTERISTICS
3
Electrical characteristics
3.1
Maximum ratings
Table 3. Maximum ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Electrical ratings
VBATP/VBATP_SMPS
VBATSNS
Ratings
Value
Unit
Notes
DC Voltage at Power Supply Pins
DC Voltage at Battery Sense Pin
-0.3 to 40
-14.0 to 41
-0.3 to 7.0
-0.3 to 40
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
DC Voltage at INT_B, RST_B, MISO, MOSI, CS_B, SCLK, AMUX
DC Voltage at SAFE_B Pin
VDIG
VSAFE_B
DC Voltage at WDI Pin
VWDI
-0.3 to 18
DC Voltage at SG0, 1, 2, 3, 4, 5
DC Voltage on CAN_5V pin
VSG
VCAN_5V
VBUS_CAN
VBUS_DIG
VBUS_LIN
VPRE
-14 to 40
-0.3 to 7.0
-32 to 40
DC Voltage on CANL, CANH
DC Voltage on TXD_C, RXD_C, TXD_Lx, RXD_Lx
DC Voltage on LINx
-0.3 to VDD +0.3
-27 to 40
-0.3 to8.0
-0.3 to 8.0
-0.3 to 40
-0.3 to 45
-0.3 to 7.0
-0.3 to 8.0
-2.0 to 40
-0.3 to 40
200
DC Voltage at VPRE Pin
DC Voltage at VPRE_GATE Pin
DC Voltage at VSW Pin
VPRE_GATE
VSW
DC Voltage at BOOT Pin
VBOOT
DC Voltage at VDD Pin
VDD
DC Voltage at VDDE, VDDB Pin
DC Voltage at VAUX Pin
VDD_E,B
VAUX
VAUX_E,B
IBUS_CAN
DC Voltage at VAUXE, VAUXB Pin
Continuous Current Capability of CANL, CANH
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NXP Semiconductors
6
ELECTRICAL CHARACTERISTICS
Table 3. Maximum ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Ratings
Value
Unit
Notes
ESD ratings
AEC Q100
• LINx pins versus GND
VESD1-1
VESD1-2
VESD1-3
VESD1-4
VESD2-1
VESD2-2
±8000
±4000
3000
• VBAT_SMPS, VBATSNS pins versus GND
• VBATP pin versus GND
• all other pins
(2)
V
2000
Charge Device Model
• Corner pins (pins 1, 12, 24, 25, 36, 37, and 48)
• All other pins (pins 2-11, 14-23, 26-35, 38-47)
750
500
Contact Discharge, Unpowered
VESD4-1
VESD4-2
VESD4-3
VESD4-4
VESD4-5
• LIN0, LIN1, LIN2, and LIN3 pin with 220 pF
• LIN0, LIN1, LIN2, and LIN3 pin without capacitor
• CANH and CANL
• SGx - pins with 47-100 nF capacitor
• VBATP, VBAT_SMPS, VBATSNS
6000
6000
6000
6000
6000
(3)
V
V
Unpowered
VESD5-1
VESD5-2
VESD5-3
VESD5-4
• LIN0, LIN1, LIN2, and LIN3 pin with 220 pF and without capacitor
• CANH, CANL pin without capacitor
• VBATP (100 nF to GND)
15000
15000
8000
(3)
• VBATSNS (1.0 kΩ series resistance)
8000
SGx pins with 47 nF to 100 nF capacitor
• Air discharge - unpowered and powered
• Contact discharge - unpowered and powered
VESD6-1
VESD6-2
(3)
(3)
15000
8000
V
V
Contact Discharge, Unpowered, GND connected to ESD gun GND
• CANH, CANL without capacitor
VESD7-1
Thermal ratings
TA
7000
Ambient Temperature
Junction Temperature
Storage Temperature
-40 to 125
-40 to 150
-55 to 150
°C
°C
°C
TJ
TSTORE
Notes
2. ESD testing is performed in accordance with the Human Body Model (HBM) JESD22/A114 (CZAP = 100 pF, RZAP = 1500 Ω) and the Charge
Device Model (CDM), Robotic (CZAP = 4.0 pF).
3. According to Hardware requirements for LIN, CAN, and Flexray Interfaces in Automotive Applications, Revision 1.0, 2008-12-10 (IEC 61000-4-2:
CZAP = 150 pF, RZAP = 330 Ω.
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NXP Semiconductors
ELECTRICAL CHARACTERISTICS
Table 4. Table of thermal resistance data
Symbol
Ratings
Value
72
Unit
°C/W
°C/W
°C/W
°C/W
Notes
(4),(5)
RΘJA
Junction to Ambient, Natural Convection, Single Layer board (1s)
Junction to Ambient, Natural Convection, Four layer board (2s2p)
Junction to Case Top
(4),(5)
(6)
RΘJA
31
RΘJCTOP
RΘJCBOTTOM
Notes
23
(7)
Junction to Case Bottom
1.2
4. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
5. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board,
respectively.
6. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
7. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance.
33909
NXP Semiconductors
8
ELECTRICAL CHARACTERISTICS
3.2
Static electrical characteristics
Table 5. Static electrical characteristics
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Power input
Full DC voltage Range
Typical DC Operating Range
2.5
7.0
–
–
35
27
VBATP
V
V
VBATP Undervoltage
V
2.3
35
–
–
–
2.5
40
14
BATUV
• VBAT Power Down Range, POR occurs
VBATP Overvoltage Detector Thresholds, at VBATP Pin
• Not active in Low-power modes
VS_HIGH
V
Total Supply Current, in Normal Mode, CAN in Recessive Mode, SGx
is open switch, 5.0 V CAN and VAUX ON, LINx in Recessive Mode
IVBATP
7.0
mA
Low-power Mode VDD Off. Wake-up from CAN, SGx inputs at
T
= 64 ms, LIN
• VBATP = 18 V and 8.0 V
ILPM_OFF
–
100
190
μA
SCAN
Low-power Mode VDDON (5.0 V) with VDD Undervoltage and VDD
Overcurrent Monitoring, Wake-up from CAN, SGx Inputs at
ILPM_ON
–
–
125
90
200
170
μA
μA
T
= 64 m and LIN
SCAN
• VBATP = 18 V and 8.0 V
Low-power Mode VDD OFF (no wake-up)
• VBATP = 18 V and 8.0 V
IOSC
VPRE buck boost converter
Minimum Start Up Voltage
• VBAT Power Up Range, V is not Operating (VBATP <
VBAT_MIN_SU
4.5
5.0
5.3
V
DD
VBAT_MIN_SU
)
Buck to Boost Mode Threshold Voltage
Boost to Buck Mode Threshold Voltage
Peak Input Current Limit
VBATPTHD
VBATPTHU
IPRE_LIM
ILOAD
6.2
6.8
3.5
–
6.6
7.25
4.0
–
7.0
7.8
–
V
V
(8)
(8)
A
Transient Load Current Change
VPRE Load regulation Variation
Switching Frequency
500
25
mA
A/ms
kHz
(8)
IPRE/DT
fSW
–
–
(8),(9)
418
440
462
Continuous Output Load Current
• Buck mode
(8)
ILOAD_BUCK
3.0
–
–
–
–
0.5
A
• Boost mode (VBATP = 2.5 V)
ILOAD_BOOST
Current Limit Blanking Time
tILIM_BT
200
25
–
600
–
ns
Continuous Output Load Current During Low-power Mode
ILPM_LOAD
40
mA
Notes
8. Guaranteed by design.
9. Fixed frequency.
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NXP Semiconductors
ELECTRICAL CHARACTERISTICS
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
VPRE buck boost converter
VPRE Overvoltage
VPRE Overvoltage Hysteresis
VPREOV
VPREOVHYST
VPREUV
7.2
0.05
5.5
0.05
19
–
–
8.0
0.2
6.0
0.2
24
–
V
V
VPRE Undervoltage
–
V
VPRE Undervoltage Hysteresis
IPFF: Input Voltage Detection
IPFF: Input Voltage Hysteresis
IPFF: Input Voltage Filter Time
IPFF: HS Peak Current Detection
IPFF: HS Peak Current Filter Time
VPRE Thermal Warning Threshold
VPRE Thermal Shutdown Threshold
VPRE Thermal Shutdown Hysteresis
VPRE External Capacitor
VPREUVHYST
VSUP_IPFF
–
V
–
V
VSUP_IPFF_HYST
t_VSUP_IPFF
IPRE_IPFF_PK
t_IPRE_IPFF
TPRE_TWARN
TPRE_TSD
0.2
1.0
2.2
100
–
–
V
–
4.0
–
μs
A
–
–
300
–
ns
°C
°C
°C
μF
mΩ
(10)
(10)
(10)
(10)
(10)
125
–
160
10
–
TPRE_TSD_HYS
CVPRE
–
–
–
47
–
–
VPRE External Capacitor ESR
RVPRE
–
100
Buck converter
Output Voltage VPRE
VPREBUCK
6.3
–
6.5
–
6.7
V
• VBATP = VBATP(THD or THU) to 36 V
VSW Drain-source On-resistance
• ID = 500 mA, VBATP = 9.0 V
RDS(on)
Boost converter
VPREBST
300
mΩ
Output Voltage VPRE in Boost Mode
6.0
6.3
7.0
V
• VBATP = 2.5 V to VBATP (THD or THU), IVPRE = -550 mA
VPREGATE Output Voltage, Power MOSFET ON
VPREGATE Source Continuous Current
VPREGATE Sink Continuous Current
VG
ISOURCE
ISINK
VPRE
–
3.5
–
4.0
350
350
V
(10)
(10)
mA
mA
200
500
Notes
10. Guaranteed by design.
33909
NXP Semiconductors
10
ELECTRICAL CHARACTERISTICS
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
VDD voltage regulator, VDD pin
Output voltage (5.0 V device)
VOUT5
4.9
3.23
-90
5.0
3.3
–
5.1
3.367
-60
V
V
• VBATP = 2.5 V to 35 V, IOUT = 0 mA to 500 mA, Normal mode
Output voltage (3.3 V device)
VOUT3
• VBATP = 2.5 V to 35 V, IOUT = 0 mA to 500 mA, Normal mode
VDD Short-circuit Current
ISCVDD
mA
mA
• VDD = 1.65 V, VSCFDIFF = VPRE-VDDE
VDD Foldback Current Limit
IVDD_FBILIM
-60
–
-30
• VDD = 0.5 V, VSCFDIFF = VPRE-VDDE
VDD Foldback Current Limit Threshold (VDD voltage when foldback
current kicks in)
VDD_FB
IVDDBC
0.5
25
40
1.075
1.65
–
V
VDD Base Current Capability
–
–
mA
dB
PSRR (Power supply rejection ratio)
• f = 350 kHz to 500 kHz
(11)
PSRRVDD
–
(11)
(11)
Range of Decoupling Capacitor
External capacitor ESR
CEXT
4.7
10
–
–
100
100
μF
R3CAPESR
mΩ
Low-power Mode VDDON, output voltage (5.0 V device)
• IOUT ≤ 40 mA (time limited), VBATP ≥ 8.5 V
VDDLP5
4.7
5.0
5.25
V
• IOUT ≤ 20 mA (time limited), VBATP ≥ 5.5 V
Low-power Mode VDDON, output voltage (3.3 V device)
• IOUT ≤ 40 mA (time limited), VBATP ≥ 8.5 V
• IOUT ≤ 20 mA (time limited), VBATP ≥ 5.5 V
VDDLP3
3.135
2.0
3.3
5.0
3.465
9.0
V
Low-power Wake-up Current Threshold, VBATP ≥ 6.0 V
ILP-ITH
mA
Voltage regulator for CAN interface supply, CAN5V pin
Output Voltage
5VCANOUT
4.75
5.0
5.25
V
• IOUT = 0 mA to 200 mA, VBATP = 5.5 V to 40 V
Output Current Limitation
Undervoltage Threshold Falling
Undervoltage Threshold Rising
Undervoltage Hysteresis
Thermal Shutdown
5VCANILIM
5VCANUV
5VCANUV
5VCANUV
5VCANTS
CEXT-CAN
200
4.0
–
–
–
mA
V
4.7
4.75
0.3
–
4.0
–
V
0.05
160
1.0
0.1
–
V
(11)
(11)
°C
μF
External Capacitance
–
100
Notes
11. Guaranteed by design.
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ELECTRICAL CHARACTERISTICS
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
V Auxiliary output, 5.0 V and 3.3 V selectable VB-AUX, VAUX pin
VAUX Output Voltage 5.0 V
VAUX5
4.85
3.2
5.0
3.3
5.15
3.4
V
V
• IOUT = 0 mA to 200 mA
VAUX Output Voltage 3.3 V
VAUX3
• IOUT = 0 mA to 200 mA
VAUX Undervoltage Detector 5.0 V
VAUX Undervoltage Detector 3.3 V
VAUX-UVTH5
VAUX-UVTH3
4.2
4.5
3.0
4.75
3.1
V
V
2.75
VAUX-OVTH
VAUX-SBDL
VAUX Overvoltage
5.6
VDD-15 mV
200
6.0
VDD
–
7.0
VDD+15 mv
360
V
V
• VAUX Short to Battery Detection Level
VAUX Tracking Supply
VAUX_TRACK
• VDD = 5.0 V only, IAUX = 100 mA
VAUX Current Limit
• VAUX = 1.65 V
IAUX-ILIM
mA
VAUX Fold-back Current Limit
• VAUX < VAUX-FB
IAUX-FBILIM
120
0.5
–
230
mA
V
VAUXE Fold-back Current Limit Threshold - VAUX level at which Fold-
back Current Kicks In
VAUX-FB
1.075
1.65
VAUX Short to Battery Leakage
VAUX Base Current Capability
IAUX-SBLK
IVAUXBC
C3CAP
0.0
10
–
–
–
–
15
–
µA
mA
μF
(12)
(12)
External Capacitance
2.2
10
100
100
External Capacitor ESR - Includes PCB Impedance
R3CAPESR
mΩ
Undervoltage reset and reset function, RST_B pin
VDD Undervoltage Threshold 5H, 5.0 V device (falling)
VST-TH5H
VST-TH5L
VST-TH3L
VST-TH3H
VST-HYST
VST-TH3L
VSVDD-OV
VOL
4.25
2.75
1.85
2.75
50
4.5
3.3
–
4.75
3.4
2.05
3.15
500
500
6.0
500
25
V
V
VDD Undervoltage Reset Threshold 5L,5.0 V device (falling)
VDD Undervoltage Threshold 3L, 3.3 V device (falling)
VDD Undervoltage 3H 3.3 V device (falling)
VDD Undervoltage Hysteresis, 5.0 V device
VDD Undervoltage Hysteresis, 3.3 V device
VDD Overvoltage
V
–
V
100
100
–
mV
mV
V
40
5.5
–
RST_B VOL at 1.5 mA, V
= 2.5 V to 35 V
–
mV
mA
kΩ
V
BATP
I
RST_B Sink Current - VRESET Driven Low (25 °C Only)
Pull-up Resistor (to VDD pin)
5.0
10
7.0
20
0.4
–
SINKRESET
RPULL-UP
–
RST_B input Threshold
VST-VTH
–
–
RST_B Input Hysteresis
VRST-HYST
450
950
mV
Notes
12. Guaranteed by design.
33909
NXP Semiconductors
12
ELECTRICAL CHARACTERISTICS
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
VBATSNS input
VBATSNS Resistor Divider (VBATP = 27 V)
• 5.0 V device, Divider 1/5.94
VACC5
VACC3
–
–
–
–
5.0
5.0
%
• 3.3 V device, Divider 1/8.9
Input Resistor to GND. In all modes except in Low-power modes
RVBATSNS
Analog MUX output
CMUX
50
–
–
kΩ
(13)
(13)
External Capacitor at AMUX Output
–
–
–
4.0
–
1.0
–
nF
mV/°C
mV
Chip Temperature Sensor Coefficient
Input Offset Voltage when Selected as Analog
TEMP-COEFF
VOFFSET
-10
10
Analog Operational Amplifier Output Voltage
• Sink 250 µA
VOL
–
–
–
50
mV
V
Analog Operational Amplifier Output Voltage
• Source 250 µA
VOH
VDD -0.1
VDD +0.1
Temperature limit
(13)
(13)
Temperature monitor
TLIM
155
5.0
–
–
185
15
°C
°C
Temperature Monitor Hysteresis
TLIM(HYS)
WDI input
SAFE_B Mode A
RWDIA
RWDIB1
RWDIB2
RWDIB3
–
–
–
–
–
–
2.5
14
40
–
kΩ
kΩ
kΩ
kΩ
V
• External Resistor to GND on WDI pin
SAFE_B Mode B1
7.0
29
80
8.0
• External Resistor to GND on WDI pin
SAFE_B Mode B2
• External Resistor to GND on WDI pin
SAFE_B Mode B3
• External Resistor to GND on WDI pin
Watchdog Inhibit for Debug
• For Watchdog inhibit mode
VWDIT
–
SAFE output
SAFE_B Sink Current
I
mA
V
SINKSAFE_B
• SAFE_B driven low (25 °C only)
2.5
0.0
–
–
–
SAFE_B Low Level
• I = 500 μA
VOLSAFE
1.0
1.0
SAFE_B Leakage Current (VDDLOW, or device unpowered)
• VSAFE_B = 35 V
I
μA
SAFE_B-IN
-1.0
0.0
Notes
13. Guaranteed by design.
33909
13
NXP Semiconductors
ELECTRICAL CHARACTERISTICS
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Interrupt
Characteristic
Min.
Typ.
Max.
Unit
Notes
Output Low Voltage - IOUT = 1.5 mA
VOLINT
VOHINT
RPU
–
0.2
–
1.0
V
V
INT_B Voltage High - INT_B = Open circuit
Pull-up Resistor
VDD -0.5
VDD +0.1
10
20
7.5
25
25
kΩ
mA
Sink Current - VINT > 5.0 V, INT Driven Low (25 °C only)
ISINKINT
2.5
CAN logic input pins (TXD)
High Level Input Voltage
VIH
VIL
0.7 x VDD
–
–
V
V
Low Level Input Voltage
Pull-up resistor - VIN = 0 V
0.3 x VDD
66
RPUCAN
22
33
kΩ
CAN data output pins (RXD)
Low Level Output Voltage - IRXD = 5.0 mA
VOUTLOW
VOUTHIGH
IOUTHIGH
IOUTLOW
0.3 x VDD
VDD
0.0
–
–
V
V
High Level Output Voltage - IRXD = -3.0 mA
High Level Output Current - VRXD = VIO - 0.4 V
Low Level Output Current - VRXD = 0.4 V
0.7 x VDD
-6.0
2.0
-3.0
5.0
-1.0
mA
mA
12
CAN output pins (CANH, CANL) - RBUS = 60 Ω for product test
Bus Pins Common Mode Voltage for Full Functionality
(voltage range for CAN test)
VCOM
-15
–
20
V
Differential Input Voltage Threshold
Differential Input Hysteresis
Input Resistance
VCANH-VCANL
VDIFF-HYST
RIN
500
100
5.0
10
–
–
900
-
mV
mV
kΩ
kΩ
%
–
50
Differential Input Resistance
Input Resistance Matching
RIN-DIFF
–
100
3.0
RIN-MATCH
-3.0
0.0
CANH Output Voltage (45 Ω < RBUS < 65 Ω)
• TX dominant state
VCANH
2.75
2.0
3.5
2.5
4.5
3.0
V
V
V
• TX recessive state
CANL Output Voltage (45 Ω < RBUS < 65 Ω)
• TX dominant state
VCANL
0.5
2.0
1.5
2.5
2.25
3.0
• TX recessive state
Differential Output Voltage (45 Ω < RBUS < 65 Ω)
• TX dominant state
VOH-VOL
1.5
-0.5
2.0
0.0
3.0
0.05
• TX recessive state
CANH Output Current Capability - Dominant state
CANL Output Current Capability - Dominant state
CANL Overcurrent Detection - Error reported in register
CANH Overcurrent Detection - Error reported in register
ICANH
ICANL
ICANL-OC
ICANH-OC
–
35
–
–
-35
–
mA
mA
mA
mA
-100
70
-85
85
-70
100
CANH, CANL Input Resistance Device Supplied and in CAN Sleep
Mode, V_CANH, V_CANL from 0 V to 5.0 V
RINSLEEP
5.0
–
50
kΩ
33909
NXP Semiconductors
14
ELECTRICAL CHARACTERISTICS
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
CAN output pins (CANH, CANL) - RBUS = 60 Ω for product test (continued)
CANL, CANH Output Voltage in Sleep and Standby Modes
(45 Ω < RBUS < 65 Ω)
VCANLP
-0.1
0.0
0.1
V
CANH, CANL Input Current, Device Unsupplied, VBATP connected to
GND
ICAN
μA
µA
• VCANH, VCANL = 5.0 V
–
–
5.0
–
250
–
• VCANH, VCANL = -2.0 V to + 7.0 V
Loss of Ground Leakage Current (GB CZ)
(14)
I
–
250
–
LEAKGND
• VBATP = 12 V
CANH and CANL diagnostic information
GND Detection Threshold
• CANL
• CANH
VLG
VHG
-200
4.7
250
5.1
900
5.7
mV
V
VBATP Detection Threshold
• CANL
VLVB
VHVB
• CANH
LIN 0-3 pin (parameters guaranteed for 7.0 V < VBATP < 17 V)
Operating Voltage Range (voltage range for LIN testing)
Supply Voltage Range (voltage range for LIN testing)
VBATTERY
VBATP
VBATP_NON_OP
IBUS_LIM
IBUS_PAS_DOM
8.0
7.0
-0.3
40
–
–
18
18
V
V
Voltage Range within which the Device is Not Destroyed
Current Limitation for Driver Dominant State Driver ON, VBUS = 18 V
–
40
V
90
200
mA
Input Leakage Current at the Receiver Driver OFF; VBUS = 0 V;
VBATP = 12 V
-1.0
–
–
–
–
mA
Leakage Output Current to GND Driver OFF; 7.0 V < VBATP < 17 V;
8.0 V < VBUS < 18 V
IBUS_PAS_REC
20
μA
Control Unit Disconnected from GND (Loss of local ground must not
affect communication in the residual network)
GNDDEVICE = VBATP, VBATP = 12 V, 0 < VBUS < 18 V
(14)
IBUS_NO_GND
-1.0
–
–
–
1.0
mA
VBATP Disconnected, VBATP_DEVICE = GND, 0 < VBUS < 18 V (Node
has to sustain the current which can flow under this condition. Bus
must remain operational under this condition)
IBUSNO_BAT
100
μA
Receiver Dominant State
VBUSDOM
VBUSREC
VBUS_CNT
VHYS
VBATP
VBATP
VBATP
VBATP
–
0.6
0.475
–
–
–
0.4
–
Receiver Recessive State
Receiver Threshold Center (VTH_DOM + VTH_REC)/2
0.5
–
0.525
0.175
Receiver Threshold Hysteresis (VTH_REC - VTH_DOM
)
Notes
14. Guaranteed by CZ. Parameter not tested in production.
33909
15
NXP Semiconductors
ELECTRICAL CHARACTERISTICS
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
LIN 0-3 pin (parameters guaranteed for 7.0 V < VBATP < 17 V) (continued)
Voltage Drop at the Serial Diode in Pull-up Path - High Z State at LINx
VBATP_SHIFT (GBD)
VSERDIODE
VSHIFT_BAT
VSHIFT_GND
VBUSWU
0.4
0.0
0.0
3.2
20
5.9
–
–
–
1.0
11.5%
11.5%
3.8
V
(15)
(15)
VBATP
VBATP
GND_SHIFT (GBD)
–
LIN Wake-up Threshold from Stop or Sleep Mode
LIN Pull-up Resistor to VBATP
3.5
30
6.2
100
160
10
V
kΩ
V
RSLAVE
60
LIN Undervoltage Threshold (rising and falling) (J2602)
LIN Undervoltage Hysteresis (VUVR – VUVF) (J2602)
Overtemperature Shutdown
VUVR, VUVF
VUVHSY
6.85
–
mV
°C
°C
(15)
(15)
TLINSD
150
–
180
–
Overtemperature Shutdown Hysteresis
TLINSD_HYS
LIN RXD output pins
VOL_RXDL
Low Level Output Voltage - IIN ≤ 1.5 mA
–
–
–
–
0.9
5.25
3.5
V
V
V
High Level Output Voltage (VDD = 5.0 V) - IOUT ≤ 250 μA
High Level Output Voltage (VDD = 3.3 V) - IOUT ≤ 250 μA
4.25
3.0
VOH_RXDL5
VOH_RXDL3
LIN TXD input pins
Low Level Input Voltage
0.3 x VDD
–
–
V
VIL_TXDL
High Level Input Voltage
0.7 x VDD
–
–
–
V
VIH_TXDL
VINHYSTL
Input Threshold Voltage Hysteresis
Pull-up Resistor - VIN = 0.0 V
450
22
950
66
mV
kΩ
R
33
PULLIN
Switch input
Leakage (SGx pins) to GND
ILEAKSG_GND
• Inputs tristated, analog mux selected for each input, voltage at
SGx = GND
µA
µA
–
–
–
–
2.0
2.0
Leakage (SGx pins) to Battery
ILEAKSG_BAT
• Inputs tristated, analog mux selected for each input, voltage at
SGx = VBATP
Leakage (SGx pins) Voltage at SGx = 36 V, VBATP and VPRE = 0 V
Pulse Wetting Current 1 - Mode 1 IPULSE1 = 6.0 mA
Pulse Wetting Current 2 - Mode 2 IPULSE2 = 8.0 mA
Pulse Wetting Current 3 - Mode 3 IPULSE1 = 10 mA
ILEAKSG_WE
IWET1
–
–
–
–
–
2.0
6.6
8.8
11
µA
mA
mA
mA
5.4
7.2
9.0
IWET2
IWET3
Notes
15. Guaranteed by design.
33909
NXP Semiconductors
16
ELECTRICAL CHARACTERISTICS
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Switch input (continued)
Pulse Wetting Current 4 - Mode 4 IPULSE2 = 12 mA
Pulse Wetting Current 5 - Mode 5 IPULSE3 = 14 mA
Pulse Wetting Current 6 - Mode 6 IPULSE4 = 16 mA
Pulse Wetting Current 7 - Mode 7 IPULSE5 = 20 mA
Sustain Current
IWET4
IWET5
10.8
12.6
14.4
18
–
–
–
–
–
13.2
15.4
17.6
22
mA
mA
mA
mA
mA
IWET6
IWET7
ISUSTAIN
1.60
2.40
Matching Between SG Channels (2.0 mA)
ISUS(MAX) – ISUS(MIN) X 100
ISUS(AVG)
IMATCH(SUS)
-10
–
–
10
%
%
Matching Between SG Channels (6, 8, 10, 12, 14, 16, and 20 mA)
IWET(MAX) – IWET(MIN) X 100
IWET(AVG)
IMATCH(WET)
-5.0
5.0
Switch Detection Threshold - Normal mode
Low-power Polling Current
VICTHR
3.20
0.850
100
–
3.8
1.35
350
V
ISUSTAINLP
1.1
210
mA
mV
Low-power Switch Detection Threshold
VLPICTHR
Digital interface
VIH
Input Logic High Voltage Thresholds (MISO, MOSI, SCLK, CS_B)
Input Logic Low Voltage Thresholds (MISO, MOSI, SCLK, CS_B)
0.7 X VDD
–
–
–
–
–
–
–
–
–
–
–
V
V
VIL
IHZ
0.2 X VDD
–
-2.0
Tri-state Leakage Current (MISO) - V
= 0.0 V to V
DD
2.0
3.0
µA
µA
µA
µA
µA
V
DD
SCLK/MOSI Input Current - SCLK/MOSI = 0.0 V
SCLK/MOSI Pull-down Current - SCLK/MOSI = V
CS_B Input Current - CS = VDD
ISCLK, IMOSI
ISCLK, IMOSI
ICS_B
-3.0
-5.0
-15
DD
-10
10
CS_B Pull-up Current- CS = 0.0 V
ICS_B
30
100
MISO High-side Output Voltage - ISO(HIGH) = -200 µA
MISO Low-side Output Voltage - ISO(LOW) = 1.6 mA
Input Capacitance on SCLK, MOSI, Tri-state MISO
VSO(HIGH)
VSO(LOW)
CIN
VDD – 0.8
VDD + 0.3
–
–
0.40
20
V
(16)
pF
Notes
16. Guaranteed by characterization in the development phase, parameter not tested.
33909
17
NXP Semiconductors
ELECTRICAL CHARACTERISTICS
3.3
Dynamic electrical characteristics
Table 6. Dynamic electrical characteristics
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Switch input
tPULSE(ON)
Characteristic
Min.
Typ.
Max.
Unit
Notes
(17)
(17)
(17)
(17)
(17)
(18)
Pulse Wetting Current Timer - Normal Mode
Interrupt Delay Time - Normal Mode
18
–
–
–
22
16
20
20
66
9.1
ms
µs
%
tINT-DLY
tSCAN TIMER
tINT TIMER
Scan Timer Accuracy - Low-power Mode
Interrupt Timer Accuracy - Low-power Mode
Tscan Timer (time actual polling takes place) - Low-power Mode
Glitch Filter Timer - Normal Mode
–
–
–
–
%
tTSCAN TIME
44
–
55
–
µs
µs
tGLITCH TIMER
Digital interface timing
(18)
(17)
(17)
(17)
(17)
(17)
(17)
(17)
(17)
(17)
(17)
(17)
(17)
(17)
(17)
Transfer Frequency
fOP
tSCK
tLEAD
tLAG
tSCKHS
tSCKLS
tSUS
tHS
–
160
140
50
56
56
16
20
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6.25
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Period - 1
Enable Lead Time - 2
–
Enable Lag Time - 3
–
SCLK High Time - 4
–
SCLK Low Time - 5
–
MOSI Input Setup Time - 6
MOSI Input Hold Time - 7
MISO Access Time - 8
–
–
tA
116
100
116
–
MISO Disable Time - 9
tDIS
–
MISO Output Valid Time - 10
MISO Output Hold Time (No cap on MISO) - 11
Rise Time (Design Information) - 12
Fall Time (Design Information) - 13
CS_B Negated Time - 14
tVS
–
tHO
20
–
tRO
30
30
–
tFO
–
tCSN
500
Supply, voltage regulator, reset
(17)
(18)
VBATP Undervoltage Detector Threshold Deglitcher
tS_LOW1/2 DGLT
30
–
50
10
100
20
µs
µs
Deglitcher Time to Set Reset Pin Low
tRST-DGLT
VPREGATE
tVPREMST
(17)
VPREGATE (mode select) Time
–
150
–
µs
Notes
17. Guaranteed by CZ. Parameter not tested in production. All SPI timing is performed with a 100 pF load on MISO, unless otherwise noted.
18. Guaranteed by design.
33909
NXP Semiconductors
18
ELECTRICAL CHARACTERISTICS
Table 6. Dynamic electrical characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
VPRE
Characteristic
Min.
Typ.
Max.
Unit
V/ms
V/ms
Notes
VPRE Soft start Ramp cap. = 57 µF
VPRESS
5.0
12
25
VDD regulator
VDD Soft Start Ramp - CVDD = 10 µF; I = 10 mA
V
5.0
12
25
DD_SS
VAUX regulator
VAUX Soft Start Ramp (non-tracking mode) - CVAUX = 10 µF; I =
10 mA
V
5.0
5.0
12
–
25
25
V/ms
V/ms
AUX_SS
V
VAUX Soft Start Ramp (tracking mode) - CVAUX = 10 µF; I = 10 mA
AUX_SSTR
Reset pulse duration
VDD Undervoltage (SPI selectable)
• Short, default at power ON when BATFAIL bit set
–
–
–
–
–
–
–
–
1.0
5.0
10
(19)
(19)
(20)
• Medium
• Medium long
• Long
tRST-PULSE
ms
ms
20
Watchdog Reset
tRST-WD
–
1.0
–
AMUX output
AMUX Access Time (Selected output to selected output)
• CMUX = 1.0 nF Rising edge of CS_B to selected
tAMUX-VALID
–
–
20
–
–
µs
µs
AMUX Access Time (Tri-state to ON)
tAMUX-VALID
20
• CMUX = 1.0 nF Rising edge of CS_B to selected
Oscillator
tOSC-TOL
Interrupt
Oscillator Tolerance
-5.0
–
5.0
µs
µs
INT pulse duration (refer to SPI)
(19)
• Short
• Medium
t
–
–
25
100
–
–
INT-PULSE
Notes
19. Guaranteed by design.
20. AMUX settling time to be within 10 mV accuracy. AMUXVALID is dependent of the voltage step applied on the source SGx pin, or the difference
between the first and second channel selected as the multiplexed analog output. See Figure 10 for a typical AMUX access time versus voltage
step waveform.
33909
19
NXP Semiconductors
ELECTRICAL CHARACTERISTICS
Table 6. Dynamic electrical characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
CAN dynamic characteristics
TXD Dominant State Timeout
Bus Dominant Clamping Detection
tDOUT
tDOM
0.8
0.8
1.8
1.6
2.8
2.8
ms
ms
Propagation Loop Delay TXD to RXD, recessive to dominant (Slew
rate 0)
tLRD
60
120
210
ns
Propagation Delay TXD to CAN, recessive to dominant
Propagation Delay CAN to RXD, recessive to dominant
Propagation Loop Delay TXD to RXD, dominant to recessive
Propagation Delay TXD to CAN, dominant to recessive
Propagation Delay CAN to RXD, dominant to recessive
tTRD
tRRD
tLDR
tTDR
tRDR
–
–
70
45
110
140
255
150
140
ns
ns
ns
ns
ns
100
–
120
75
–
50
LIN 1-4 physical layer: driver characteristics for normal slew rate - 20.0 kBit/sec according to lin physical layer specification bus load RBUS and
C
BUS 1.0 nF/1.0 k, 6. nF/660, 10 nF/500. Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. (21)
Duty Cycle 1:
• THREC (max) = 0.744 * VBATP
D1
D2
0.396
–
–
–
• THDOM (max) = 0.581 * VBATP
• D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V ≤ VBATP ≤ 18 V
Duty Cycle 2:
• THREC (min.) = 0.422 * VBATP
–
0.581
• THDOM (min.) = 0.284 * VBATP
• D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V ≤ VBATP ≤ 18 V
LIN physical layer: driver characteristics for slow slew rate - 10.4 kBit/sec according to lin physical layer specification (48), (50) bus load RBUS
and CBUS 1.0 nF/1.0 k, 6.8 nF/660, 10 nF/500. Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. (22)
Duty Cycle 3:
• THREC (max) = 0.778 * VBATP
D3
D4
0.417
–
–
• THDOM (max) = 0.616 * VBATP
• D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V ≤ VBATP ≤ 18 V
Duty Cycle 4:
• THREC (min.) = 0.389 * VBATP
–
–
–
0.59
100
• THDOM (min.) = 0.251 * VBATP
• D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V ≤ VBATP ≤ 18 V
LIN physical layer: driver characteristics for fast slew rate
LIN Fast Slew Rate (Programming mode)
BRFAST
20
kBits/s
Notes
21. See Figure 4.
22. See Figure 5.
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ELECTRICAL CHARACTERISTICS
Table 6. Dynamic electrical characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
LIN physical layer: characteristics and wake-up timings, VBATP from 7.0 V to 18 V, bus load RBUS and CBUS 1.0 nF/1.0 k, 6.8 nF/660, 10 nF/500.
Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. (23)
Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF
Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR
)
tREC_PD
–
4.2
–
6.0
2.0
µs
µs
tREC_SYM
-2.0
Bus Wake-up Deglitcher (Sleep and Stop modes) (See Figure 9 for
Sleep and Figure 11 for Low-power mode.)
(24)
tPROPWL
42
70
95
µs
Bus Wake-up Event Reported
• From Sleep Mode
• From Stop Mode
(24)
(24)
tWAKE_SLEEP
tWAKE_STOP
–
9.0
250
27
–
35
µs
s
TXD Permanent Dominant State Delay
tTXDDOM
0.65
1.0
1.35
Notes
23. See Figure 6 and Figure 7.
24. Guaranteed by characterization.
3.4
Timing diagrams
Figure 4. LIN timing measurements for normal slew rate
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ELECTRICAL CHARACTERISTICS
Figure 5. LIN timing measurements for slow slew rate
Figure 6. LIN receiver timing
Figure 7. LIN wake-up timing from low-power VDD off mode
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ELECTRICAL CHARACTERISTICS
Figure 8. LIN wake-up timing from low-power VDD on mode
3
14
CS_B
1
4
2
SCLK
5
10
9
8
11
DON'T
CARE
MISO
DATA
MSB OUT
MSB IN
LSB OUT
12 13
7
6
MOSI
DATA
LSB IN
Figure 9. SPI timing diagram
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ELECTRICAL CHARACTERISTICS
Figure 10. AMUX access time
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FUNCTIONAL DEVICE OPERATION
4
Functional device operation
4.1
Battery voltage ranges
The 33909 device operates from 3.5 V ≤ Battery ≤ 36 V (2.5 V ≤ VBATP ≤ 35 V) and can survive to 41 V Battery. Overvoltage kicks in at
VBATP > 35 V and shuts down main functions of the IC. Battery voltages in excess of 41 V must be clamped externally in order to protect
the IC from destruction. The VBATP pin must be isolated from the main battery node by a diode.
Battery Voltage
41 V
VBATP
40 V
Survivable
36 V
28 V
35 V
27V
Full
Parametrics
Normal Mode
Full Parametrics
8.0 V
7.0 V
Full Parametrics
3.5 V
3.3 V
2.5 V
2.3 V
POR activated
No operation
0 V
0 V
Figure 11. 33909 (buck - boost mode) battery diagram
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NXP Semiconductors
FUNCTIONAL DEVICE OPERATION
Battery Voltage
41 V
VBATP
40 V
Survivable
36 V
28 V
35 V
27 V
Full
Parametrics
Normal Mode
Full Parametrics
8.0 V
7.0 V
Degraded Parametrics
3.5 V
3.3 V
2.5 V
2.3 V
POR activated
No operation
0 V
0 V
Figure 12. 33909 (buck only mode) battery diagram
4.1.1
POR
A Power On Reset occurs between 2.3 V < VBATP < 2.5 V. The 33909 is held in reset when VBATP < PORFALLING. The 33909 re-
initializes after the POR is de-asserted (VBATP_MIN_SU).
4.1.2
No operation
No operation in this range. The device does not send or receive SPI commands, and must reset properly upon leaving this range (when
battery is supplied). No unintended leakage currents flows causing undesired effects.
4.1.3
Start-up requirements
Upon application of voltage to the VBATP node, the IC does not supply the VDD and VAUX voltage rails until all parameters can be
guaranteed. Internal circuitry can power up and begin to function, but the supply rails remain OFF until a stable output voltage (VDD and
VAUX) can be supplied. A typical voltage of 7.2 V on VBATP is expected to be the value where VDD and VAUX would be able to regulate
within specified range (another voltage may be determined to be the correct value, 7.0 V is a guide). This allows the micro to power up in
a known state with no glitches due to the power supply.
Upon startup of the VDD and VAUX rails, a soft start circuit limits the turn ON time of the rails (15 V/ms typical - dVDD/dt), to reduce the
overshoot of the regulated voltages. Figure 13 shows the desired waveform for the startup of the VDD and VAUX supplies.
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FUNCTIONAL DEVICE OPERATION
VBATP_st
VBATP
Vint_2.5
Vpre_EN
Vpre_UV
Tdelay_VPREINT
Vpre
Vpre_INT_Buffer
(Low Power)
VDD_UV
Tdelay_VDDINT
VDD
VDD_INT_Buffer
(Low power)
INT_B
RESET_B
Startup and
IC states
Figure 13. Power up sequencing
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FUNCTIONAL DEVICE OPERATION
VBATP_MIN_SU
5.0v
PORFALLING
2.5v
VBATP
Buck / Boost On
VPRE_EN
Figure 14. VBATP start-up and POR
4.1.4
Power supply functional block
This block has the VBATP supply and VPRE supply as an input. The internal 2.5 V rail is generated in this block. Power On Reset (POR),
Sleep mode power, and the Bandgap reference are controlled here as well.
4.2
Input functional block
There are six Switch-to-Ground inputs used to detect switch closures and provide wetting current. The main functions of this block is to
detect a change of state at the input via a 3.5 V (typical) comparator, provide a signal to the main logic to issue an interrupt signal, and
also provide wetting/sustain current for the switch. A SPI read allows the micro to know the status of all the inputs.
4.2.1
SG inputs
The SG inputs are switch to ground detect inputs with a comparator threshold (VICTHR - 3.5 V typical). A closed switch is a switch shorted
to ground (or otherwise below the VICTHR value) and is reported via the SPI as a logic 1. An open switch is any condition causing the
input voltage to rise above the VICTHR value, and is reported via the SPI as a logic 0. In the case where the user needs a Switch to
Battery, the user must take note that the IC reports a logic 1 when the input voltage is less then VICTHR. The inputs also provide a wetting
current output with selectable values ranging from 6.0 to 20 mA (IWETX) in steps of 2.0 mA. A sustain (ISUSTAIN) current level is used to
decrease power consumption in the IC. The current sources are pull-up sources with a reference of VPRE. A blocking diode is in series
with the current source to block voltages at the input greater than the VPRE from back feeding into the IC. Due to this diode, the maximum
voltage the SGx pins can pull up to is ~ 6.5 V (VPRE) - 1 diode drop (~0.7 V) for a final value of ~5.7 V. This use greatly benefits the power
consumption of the input current sources, but does limit headroom when using the current sources to drive external loads. VPRE voltage
is supplied during Normal (via the SMPS) and Low-power modes (via internal linear). Battery voltages below 7.0 V are not supported in
Low-power mode.
All register settings programmed in Normal mode are remembered in Sleep mode. The current used to detect open switches in Low-power
mode is ~1.0 mA. Upon leaving Low-power mode the programmed settings are used.
In Low-power mode, the inputs do not use the typical 3.5 V switch threshold. Rather a comparison threshold is used to measure the
beginning of the tSCAN time (before the LPM current source is turned on) and after the tSCAN timer (typical 55 μs) has completed. If this
voltage has passed the low-power switch detection threshold (typ 210 mV), the IC detects an open switch and compares to the internal
logic to determine if a change of state has occurred.
Figure 16 describes the state diagram for the SGx inputs and how they move from state to state. Of note is the three times retry of the
wetting current (IPRGM in this notation) in case of a tLIM. This allows for one time thermal events to be dealt with and still operate normally
when able. After three times tLIM, the input goes to tri-state and wait for the user to clear the tLIM fault via the SPI word.
In the case where a SAFE mode operation would like to sense the key OFF condition of the module, SG0 is used in conjunction with the
WDI pin to facilitate the SAFE operation and turn OFF the VDD supply.
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FUNCTIONAL DEVICE OPERATION
Go To LPM
CS_B
64ms (config)
Normal
Mode
Normal
LPM
Polling time
Tscan time
55us
X * 1mA SG
Load Current
0uA
Figure 15. Low-power mode typical timing diagram
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FUNCTIONAL DEVICE OPERATION
Tri-state
I = 0 mA
1
4
3
5
10
11
7
6
IWETTING
LPM (1.0 mA)
ISUSTAIN
2
8
9
1) Change from 0 mA to Wetting current value: Wetting current programmed to all time or Pulsed
Mode and untristate the input.
2) Maintain Wetting current: When switch is closed to ground and 20 ms timer not expired (wetting
current timer enabled).
3) Change from Wetting Current to 0 mA: Go to Low Power mode (LPM) or Tri-state command sent.
4) Change from 0 mA to Sustain current (2.0 mA): Wetting current off command sent and untri-state.
5) Change from Sustain current to 0 mA: Go to LPM or Tri-state command
6) Change from LPM to Wetting current: Wake-up and not in Wetting current off mode.
7) Change from LPM to Sustain current: Wake-up and in Wetting current off mode.
8) Change from Sustain to Wetting current: Switch opens and wetting current timer on or a SPI
message to turn Wetting current on.
9) Change from Wetting current to Sustain: Closed switch and timer expired or a SPI message
turning Wetting current off.
10) Change from 0 mA to LPM current: During active scan timer (100 us long) in LPM (Periodic
sense).
11) Change from LPM current to 0 mA: During inactive scan timer in LPM.
Note 1. Three Tlim instances on the SG sensor puts the device into Sustain only mode for the SGs.
A SPI read clears the function and allows wetting current to be active again.
Note 2. Overvoltage on the VBATP pin causes the SG inputs to switch to Sustain only until the
overvoltage condition is gone.
Note 3. A POR results in the IC resetting and the SG inputs back in the Tri-state condition.
Figure 16. 33909 SG state diagram
4.2.1.1
Alternative functions of the SG0 pin
There are some additional functions for SG0. These functions are described in the block most closely associated with their additional
functions.
1. SG0 can be used in conjunction with the SAFE mode to determine how the IC should operate when a SAFE condition is detected.
See Table 7 for information on SAFE mode operation.
4.2.2
SG input pin functions: SGx
Each input pin is the connection used by the user to determine the state of the switch, and source the wetting and sustain currents. A
capacitor is required on the input with a minimum value of 47 nF (CAPSG) and a maximum capacitance of 100 nF. Characterization of
the input defines the available capacitor range.
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FUNCTIONAL DEVICE OPERATION
4.2.3
Oscillator and timer control functional block
The oscillator is generated in this block. All timers are generated from the reference oscillator. The oscillator is trimmed to 5.0%. There
is no external pin for the oscillator and timer control block. The 5.0% oscillator is turned OFF in Low-power mode to reduce quiescent
current.
A second oscillator is used in Low-power mode. The oscillator operates at 200 kHz and is accurate to 20%. All of the Low-power mode
timers are based on this Low-power oscillator.
4.2.4
TLIM functional block
The device has multiple tlim cells to detect thermal excursions. An independent tLIM cell exists for multiple circuit blocks including:
1. CAN regulator
2. VPRE circuitry
3. SG inputs
4. LIN cells
The corresponding block contains the description of what occurs when tLIM is seen by the related circuitry. Hysteresis for each cell is used
to keep the device from cycling. There is no external pin connection for the tLIM functional block.
4.2.4.1
INT_B functional block
This block is used to alert the micro to a change of state on an input. The INT_B pin is an interrupt output from the 33909 device. The
INT_B pin is an open-drain output with an internal pull-up to VDD. In Normal mode, a switch state change triggers the INT_B pin (when
enabled). The INT_B pin and INT_B bit in the SPI register are latched on the falling edge of CS_B. This permits the MCU to determine
the origin of the interrupt. The INT_B pin is cleared on the rising edge of CS_B. The INT_B pin does not clear with rising edge of CS_B if
a switch contact change has occurred while CS_B was LOW.
4.2.5
INT_B pin functions: INT_B
The INT_B output is asserted low or drives a pulse when an interrupt condition occurs. The INT condition is enabled in the INT register.
The INT_B operation (assertion of a low level or a pulse) is defined by the SPI.
4.2.6
SAFE_B functional block
This mode is entered when specific fail conditions occur. The “Safe state” condition defaults to condition A in Table 7. A SPI word can
then be used to modify the operation as found in Table 7. Safe mode is entered after additional event or conditions are met: timeout for
CAN communication. Exit of the Safe state is always possible by a wake-up event: in the safe state the device is automatically wakeable
CAN. Upon wake-up, the device operation is resumed: enter in Reset mode.
4.2.6.1
Debug detect
The operation of the SAFE_B block is determined by the state of the WDI pin and the associated resistance to ground is supplied external
to the IC. The IC is put into watchdog inhibit mode when the voltage at the WDI pin is > 10 V. This results in a SAFE mode A, but no
watchdog refresh is needed.
The debug detect circuit measures an external pull-down resistor on the WDI. Three thresholds exist (excluding the Test mode) and
outputs to the logic block, in which mode the SAFE_B block should operate (Mode<B3:A>). The mode is read in by determining the resistor
value on the WDI pin at power ON only (during the INIT RESET node), and remains in this state until a new power ON sequence is
detected.
4.2.6.2
Fail-safe operation
Fail-safe functionality
4.2.6.2.1
Upon a dedicated event or issue, detected at a device pin (i.e RESET), the Safe mode can be entered. In this mode, the SAFE_B pin is
active low.
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FUNCTIONAL DEVICE OPERATION
4.2.6.2.2
Description
Upon activation of the SAFE_B pin, and if the failure condition which caused the activation of SAFE_B has not recovered, the device can
help to reduce ECU consumption, assuming the MCU is not able to set the whole ECU in Low-power mode.
Two main cases are available:
• Upon SAFE_B activation, the MCU remains powered (VDD stays ON), until the failure condition recovers (i.e S/W is able to properly
control the device and properly refresh the W/D).
• Upon SAFE_B activation, the system continues to monitor external events, and disable the MCU supply (turn VDD off). The external
events monitored are: SG0 switch to ground and CAN and LIN traffic. For this condition, three sub cases exist: B1,B2, B3.
Note: CAN and LIN traffic bus idle indicates the ECU of the vehicle is no longer active, thus the car is being parked and stopped.
SAFE_B mode code
VDD status
Remains ON
A
Turn OFF 8 sec. after CAN and LIN traffic bus idle detection.
B1
B2
B3
Turn OFF when the SG0 switch is closed to ground.
Turn OFF 8 sec. after CAN and LIN traffic bus idle detection when SG0 low level is detected.
Exit of the safe state with VDD OFF is always possible by a wake-up event: in this Safe state the device is automatically wakeable with
CAN and the SG0 input. Upon wake-up, the device operation is resumed: enter in Reset mode. The SAFE_B pin remains active, until a
proper read and clear of the SPI flags reporting the SAFE_B conditions.
Figure 17 illustrates the SAFE_B mode activation and the power consumption reduction after CAN traffic idle time.
bit 11,12 of INIT command xx(1)
nth W/D
failure
No
Return to
Normal mode
SAFE High
SAFE Low
Reset 1.0 ms pulse
Reset 1.0 ms pulse
Yes
bit 11,12 of INIT command 00
SAFE Low
7 consecutive
W/D Failure
Note (4)
No (SAFE_B remains low)
State A: RWDI < 2.5 kΩ
W/D Failure
- SAFE Low
- VDD On
Yes
- Reset 1.0 ms
periodic pulse
State A: RWDI < 2.5 kΩ
VDD Low or RESETB
s/c to ground Failure
A) Evaluation of
Resistor detected
at WDI pin during
power up or SPI
register content
- SAFE Low
- VDD On
- Reset Low
VDD Low Failure:
VDD < VDD_UVTH
t > 100ms
W/D
Failure
State B1: 7.0 kΩ < RWDI
14 kΩ
<
BUS idle time out expired(2)
(CAN and LIN)
State:
INIT, Normal, Normal
Request, Flash
B) ECU external
signal monitoring
- bus idle time out
- SG0 monitoring
- Reset Low
- SAFE Low
- VDD on
- SAFE Low
- VDD Off
- Reset Low
State B2: 29 kΩ < RWDI < 40 kΩ
& SG0 Low
RESET_B short-circuit to
GND Failure:
RESET_B < RST-TVH; t > 100 ms
SAFE_B pin
release
State B3: 80 kΩ < RWDI
BUS idle time out expired(2)
(CAN and LIN) & SG0 Low
(SAFE_B High)(3)
State:
1.0 ms Reset
pulse
Wake-up event, VDD ON, SAFE_B pin remains Low
Failure recovery, SAFE_B pin remains Low
Notes:
1) Bits 11 and 12 of the INIT command control the number of times a reset / Watchdog failure should occur nth
time: 00 = 1st time, 01
= 2nd time, 10 = 3rd time, 11 = 5th time.
2) 8 second timer for bus idle time out.
3) SPI command to release SAFE_B pin after recovery from failure (5F000000).
4) Dynamic behavior: 1.0 ms reset pulse every 256 ms due to no watchdog refresh SPI command and the
device state transitions between RESET and Normal Request or INIT RESET and INIT modes.
Figure 17. SAFE operation flow chart
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FUNCTIONAL DEVICE OPERATION
Table 7. SAFE mode operation
State
VDD
CAN5V
OFF
VAUX
LINx
SGx
CAN0
High-impedance
OFF: CAN termination 25k to
Power down
OFF
OFF
OFF
High-impedance
High-impedance
OFF: internal 30 kΩ pull-up
active. Transmitter: receiver/
wake-up OFF.
Init Reset
ON
OFF
OFF
High-impedance GND Transmitter/receiver /wake-
up OFF
INIT
ON
ON
OFF
OFF
OFF
OFF
High-impedance
OFF
Keep SPI
configuration
Reset
SPI configuration OFF
Normal
Request
Keep SPI
configuration
ON
ON
OFF
ON
OFF
SPI
OFF
SPI configuration OFF
SPI
configuration
Normal
SPI configuration
SPI configuration SPI configuration
configuration
Low-power
VDDOFF
OFF
OFF
OFF
OFF + wake-up enable/disable SPI configuration OFF + wake-up enable/disable
OFF + wake-up enable/disable SPI configuration OFF + wake-up enable/disable
Low-power
VDDON
OFF
safe
case A:
ON
SAFE_B
output low:
A: Keep SPI
configuration,B: OFF
OFF
OFF + wake-up enable
SPI configuration OFF + wake-up en
SPI configuration SPI configuration
SAFE_Bcase safe
case B:
A
OFF
SPI
configuration
SPI
configuration
FLASH
ON
OFF
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FUNCTIONAL DEVICE OPERATION
WDI resistor ꢀ mode A
VDD (High)
RESET_B
VDD (High)
RESET_B
SAFE_B
SAFE_B
OFF State
ON State
Delay time to enter in SAFE mode
with consumption reduction and
evaluate resistor at WDI pin
WDI resistor ꢀ mode B(1,2,3)
VDD
RESET_B
SAFE_B (Low)
CANx Bus
(mode 1 and 3
CAN bus idle time(8s)
LIN bus idle time (8s)
LINx Bus
(mode 1 and 3)
SG0
(mode 2 and 3)
Figure 18. SAFE mode A and B (1, 2, 3)
4.2.6.3
SAFE_B pin functions: SAFE_B
This pin is an output which is asserted low in case a fault event occurs. The objective is to drive electrical safe circuitry outside the MCU
and the SBC. This safe circuitry activates the default function of the ECU, independent of the MCU and SBC.
Flexibility is provided to the user to select SAFE output operation via a resistor at the WDI pin. The SAFE output is an open drain structure.
4.2.6.4
SAFE_B pin functions: WDI
This pin is an input used to set the device in Debug mode. When the device is powered up with a voltage at the WDI pin > 10 V, the device
enters into Debug mode. In this mode, only a single WD refresh command (SPI 0x47000000) is necessary to put the device in Normal
Mode. This allows for easy debugging of the software routine controlling the device.
In addition, a resistor can be connected from the WDI pin to GND to select Fail-safe mode operation.
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FUNCTIONAL DEVICE OPERATION
4.2.7
Watchdog functional block
4.2.7.1
In normal request mode
In Normal Request mode, the device expects to receive a watchdog configuration before the end of the normal request timeout period.
This period is reset to a long (256 ms) after power-on and when BATFAIL is set. In Normal Request mode the watchdog operation is
“timeout” only and can be triggered/served any time within the period.
4.2.7.2
Watchdog type selection
Two different watchdog modes are implemented: Window or Advance. The selection of “Window” or “Advance” is done in INIT mode, after
device power up when the Batfail flag is set. Configuration is done via the SPI. Then the watchdog mode selection content is locked and
can be changed only via a secured SPI procedure.
4.2.7.3
Window watchdog operation
The window watchdog is available in Normal mode only. The watchdog period selection can be kept (SPI is selectable in INIT Mode),
while the device enters into Low-power Stop mode. The watchdog period is reset to the default long period after BATFAIL.
The period and the refresh of watchdog are done by the SPI. A refresh must be done in the open window of the period, which starts at
50% of the selected period and ends at the end of the period. If the watchdog is triggered before 50%, or not triggered before end of period,
a reset has occurred. The device enters into Reset mode.
4.2.7.4
Watchdog in debug mode
When the device is in Debug mode (entered after a POR when the WDI is > 10.0 V), the watchdog continues to operate, but does not
affect the device operation by asserting a reset. A single WD refresh command (SPI 0x47000000) is necessary to put the device in Normal
Mode. For the user, operation appears without the watchdog once Normal Mode is entered. When Debug is left by software (SPI mode
reg.), the watchdog period starts at the end of the SPI command. When Debug mode is left by hardware, when the voltage on the WDI
drops below 8.9 V, the device enters into an INIT Reset mode. The WDI pin is discussed in the SAFE_B functional block section.
4.2.7.5
Watchdog in flash mode
During Flash mode operation, the watchdog can be selected to a long timeout period. Watchdog is timeout only and an INT pulse can be
generated at 50% of the time window.
4.2.7.6
Advance watchdog operation
When the Advance watchdog is selected (at INIT mode), the refresh of the watchdog must be done using a random number and with 1,
2, or 4 SPI commands. The software must read a random byte from the SBC, then it must return the random byte inverted to clear the
watchdog. The random byte write can be done in 1, 2, or 4 different SPI commands.
If 1 command is selected, all 8 bits are written at once.
If 2 commands are selected, first write command must include 4 of the 8 bits of the inverted random byte. The second command must
include the next 4 bits. This completes the watchdog refresh.
If 4 commands are selected, the first write command must include 2 of the 8 bits of the inverted random byte. The second command must
include the next 2 bits, the 3rd command the next 2, and the last command, the last 2. This completes the watchdog refresh.
When multiple writes are used, the most significant bits are sent first. The latest SPI command needs to be done inside the open window
time frame.
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FUNCTIONAL DEVICE OPERATION
4.2.7.7
Detail SPI operation and SPI commands for all watchdog types
In INIT mode, the W/D type is selected using register Init W/D, bits 1, 2, and 3. The W/D period is selected via TIM_A register. The W/D
period selection can also be done in Normal mode or in Normal Request mode.
Transition from INIT mode to Normal mode, or from Normal Request mode to Normal mode is done via a single W/D refresh command
(SPI 0x47000000).
While in Normal mode, the W/D refresh command depends upon the W/D type selected in INIT mode. These are detailed in the following
paragraph:
Simple W/D: refresh commands is 0x47000000. It can be sent any time within the W/D period if the timeout W/D operation is selected
(INIT-W/D register, bit 1 WD N/Win = 0). It must be sent in the open window (second half of the period) if the Window Watchdog operation
was selected (INIT-W/D register, bit 1 WD N/Win = 1).
4.2.7.8
Advance watchdog
The first time device enters into Normal mode (entry on Normal mode using the 0x47000000 command), the RND code must be read
using SPI command 0x0B000000. Device returns on the MISO fourth byte of the RND code. The full 32 bit MISO response is
0xXX0000RD.
Advance Watchdog, refresh by 1 SPI command:
The refresh command is 0x4B0000RD. During each refresh command device returns a new Random Code on MISO. This new random
code must be inverted and sent along with the next refresh command, and so on.
It must be done in the open window if the Window operation was selected.
Advance Watchdog, refresh by 2 SPI commands:
The refresh command is split in 2 SPI commands.
The first partial refresh command is 0x4B0000w1, and the second is 0x4B0000w2. Byte w1 contains the first 4 inverted bits of the RD byte
plus the last 4 bits equal to zero. Byte w2 contains 4 bits equal to zero plus the last 4 inverted bits of the RD byte.
During this second refresh command, the device returns a new Random Code on MISO. This new random code must be inverted and
send along with the next 2 refresh commands and so on.
The second command must be done in the open window if the Window operation was selected.
Advance Watchdog, refresh by 4 SPI commands:
The refresh command is split in 4 SPI commands.
The first partial refresh command is 0x4B0000w1, the second is 0x4B0000w2, the third is 0x4B0000w3 and the last is 0x5Aw4.
Byte w1 contains the first 2 inverted bits of the RD byte plus the last 6 bits equal to zero.
Byte w2 contains 2 bits equal to zero plus the next 2 inverted bits of the RD byte plus 4 bits equal to zero.
Byte w3 contains 4 bits equal to zero plus the next 2 inverted bits of the RD byte plus 2 bits equal to zero.
Byte w4 contains 6 bits equal to zero plus the next 2 inverted bits of the RD byte.
During this fourth refresh command, the device returns on MISO a new Random Code. This new random code must be inverted and sent
along with the next 4 refresh commands. The fourth command must be done in the open window, if the Window operation was selected.
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FUNCTIONAL DEVICE OPERATION
4.3
Operational modes
4.3.1
Introduction
The device has several operation modes. The transitions and conditions to enter or leave each mode are described in Figure 19.
Debug
mode
detection
VBATP rise &
DD > VDD_UVTH
INIT Reset
V
VBATP fail
Power Down
start tIR
(tIR = 1.0 ms)
VBATP fail
tINIT expired
Or VDD < VDD_UVTH
W/D refresh
by SPI
tIR expired &
VDD > VDD_UVTH
FLASH
start tWDF
(max 32768 ms)
INIT
Start tINIT
(tINIT = 256 ms)
External
RESETb
SPI secured (1)
or tWDF expired
or VDD < VDD_UVTH
SPI secured (1)
SPI write
(0x47000000 )
(W/D refresh)
SPI secured (1)
VDD < VDD_UVTH
or tWD expired
RESET
start tR
or W/D failure (3)
or SPI secured (1)
Normal
Start tWDN
W/D refresh
by SPI
(1.0 ms or config)
(tWDN = config)
Wake-up
t
R expired
SPI write
(0x47000000 )
(W/D refresh)
& VDD > VDD_UVTH
t
NR expired
SPI
NORMAL
REQUEST
start tNR
LOW POWER
VDD ON
Wake-up
(256 ms)
SG scan
Start tWDL (2)
tOC expired
or Wake-up
IDD < IOC
(2.0 mA)
OC ended
if enable
W/D refresh
by SPI
t
Wake-up
IDD > IOC
(2.0 mA)
LP VDDON
VDD < VDD_UVTHLP
IDD > 2.0 mA
SG scan
start tOC time
tWDL expired or VDD < VDD_UVTHLP
SPI
SPI
LOW POWER
VDD OFF
SG scan
FAIL SAFE
DETECTED
(1) Refer to “SPI secured” description.
(2) If enabled by SPI prior to entering LP VDD ON mode.
(3) W/D refresh in closed window or enhanced W/D refresh failure.
Figure 19. State diagram
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FUNCTIONAL DEVICE OPERATION
4.3.1.1
INIT reset
This mode is automatically entered after device “power ON”. In this mode, the RST_B pin is asserted low, for a duration of typically 1.0 ms.
Control bits and flags are “set” to their default reset condition. The BATFAIL is set to indicate the device is coming from an unpowered
condition, and all previous device configurations are lost and “reset” is the default value. The duration of the INIT reset is typically 1.0 ms.
INIT reset mode is also entered from INIT mode, if the expected SPI command does not occur in due time (ref. INIT mode)
4.3.1.1.1
INIT
This mode is automatically entered from “INIT reset” mode. In this mode, the device must be configured via the SPI within a time of 256 ms
max. One SPI word to configure the INIT registers (three registers called Watchdog, REG, and MISC) must be configured during INIT
mode.
Once the INIT registers configuration is done, a SPI Watchdog Refresh command must be sent in order to set the device into Normal
mode. If the SPI W/D refresh does not occur within the 256 ms period, the device returns into INIT reset mode for a typical 1.0 ms, and
then reenter into INIT mode.
Register read operation is allowed in INIT mode, to collect device status or to read back the INIT register configuration. When INIT mode
is left by a SPI Watchdog refresh command, it is possible to reenter the INIT mode only by a secured SPI command.
4.3.1.1.2
Reset
In this mode, the RST_B pin is asserted low. Some bits and flags are reset. Reset mode is entered from Normal mode, from Normal
Request mode, from LP VDD ON mode and from Flash mode, when the watchdog is not triggered, or a VDD low condition is detected.
The duration of reset is typically 1.0 ms by default. The user can define a longer Reset pulse activation, only when the Reset mode is
entered, following a VDD low condition. Reset pulse is always 1.0 ms, in case the Reset mode is entered due to a wrong watchdog refresh
command.
4.3.1.2
Normal request
This mode is automatically entered from Reset mode, or after a wake-up from Low-power VDD ON mode. A watchdog refresh SPI
command is necessary to allow a transition to Normal mode. The duration of the Normal request mode is 256 ms maximum duration when
Normal Request mode is entered after Reset or when entered from the LP VDD ON mode. If the watchdog refresh SPI command does
not occur within the 256 ms, the device enters into Reset mode for a duration of typically 1.0 ms.
4.3.1.2.1
Normal
In this mode, all device functions are available. This mode is entered by a SPI watchdog refresh command from Normal Request mode,
or from INIT mode. During Normal mode, the device watchdog function is operating, and a periodic watchdog refresh must occur. In case
of an incorrect or missing watchdog refresh command, the device enters into Reset mode.
From Normal mode, the device can be set by a SPI command into Low-power modes (Low-power VDD ON or Low-power VDD OFF).
Dedicated secured SPI commands can be used to enter from Normal mode in Reset mode, INIT mode, or Flash mode.
4.3.1.2.2
Debug
Debug is a special operation condition of the device which allows the system easy software and hardware debugging. The debug
operation is detected after power up if the WDI pin is set above 10 V.
When debug is detected, all the software watchdog operations are disabled: 256 ms of INIT mode, watchdog refresh of Normal mode and
Flash mode of 256 ms, or a user defined timeout of Normal request mode, are not operating and does not lead to a transition into INIT
reset or Reset mode.
4.3.1.3
Flash
In this mode, the software watchdog period is extended up to typically 32 seconds. This allows the MCU flash memory to be reloaded,
while the software overhead refreshes the watchdog is limited. The Flash mode is left by the SPI command and the device enters into
Reset mode. In case of an incorrect or missing watchdog refresh, the command device enters into Reset mode.
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FUNCTIONAL DEVICE OPERATION
4.3.1.3.1
Low-power modes
The device has two main Low-power modes: Low-power mode with VDD OFF, and Low-power mode with VDD ON.
4.3.1.3.2
Low-power - V off
DD
In this mode, VDD is turned OFF and the MCU connected to VDD is unsupplied. This mode is entered by the SPI. In order to prevent
accidental VDD turn off, a VDDoff en control bit is used. This bit must be set to "1" for Low-power - VDD OFF mode to be activated.It can
also be entered by automatic transition due to fail-safe management. The 5 V-CAN and VAUX regulators are also turned off.
When the device is in Low-power VDD OFF mode, it monitors external events to wake-up and leave the LP mode. The wake-up events
can occur from:
• CAN bus
• LIN bus
• Expiration of an internal timer
• SG input
When a wake-up event is detected, the device enters into Reset mode and then into Normal Request mode. The wake-up source is
reported into the device SPI registers. In summary, a wake-up event from LP VDD OFF, leads to a VDD regulator turn ON, and an MCU
operation restart.
4.3.1.3.3
Low-power - V on
DD
In this mode, the voltage at the VDD pin remains at 5.0 V (or 3.3 V, depending upon device part number). The objective is to maintain the
MCU in a reduced power consumption mode. In this mode, the DC output current is expected to be limited to a few 100 μA or some mA,
as the ECU is in reduced power operation mode. The 5 V-CAN and VAUX regulators are turned OFF.
However, in Low-power VDD ON mode, the device is able to deliver several micro amps of current on VDD (up to typ. 2.0 mA). The current
delivery can be time limited, by a selectable internal timer. Timer duration is up to 32 ms, and is triggered when the output current exceeds
the output current threshold, typically 2.0 mA. This allows, for instance, a periodic activation of the MCU while the device remains in LP
VDD ON mode. If the duration exceeds the selected time (ex 32 ms), the device detects a wake-up.
The same wake-up event as in LP VDD OFF mode (CAN, SGx, timer, cyclic sense) are available in LP VDD ON mode. In addition, two
additional wake-up conditions are available.
• By a dedicated SPI command (hex 0x49000010).
• Output current from VDD exceeding typically a 2.0 mA threshold, the device wakes up, provided additional conditions are met (timing
detection...).
• If VDD maximum load is exceeded (>80 ma), VDD starts to fall. When VDD falls below approximately 1.0 V, the device then wakes up
and issue a reset.
Wake-up events are reported to the MCU via a low level pulse at the INT pin. The MCU detects the INT pulse and resume operation.
4.3.1.3.4
Watchdog function in LP V on mode
DD
It is possible to enable the watchdog function in low-power VDD ON mode, for timeout functionality.
Refresh of the watchdog is done either by:
• a dedicated SPI command (different from any other SPI command, or simple CS activation, which would wake-up)
• or by a temporary (less than 32 ms max) VDD overcurrent wake-up (IDD > 2.0 mA typ).
As long as the watchdog refresh occurs, the device remains in LP VDD ON mode.
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FUNCTIONAL DEVICE OPERATION
4.3.1.3.5
Cyclic sense operation
This function can be used in both Low-power modes (LP VDD OFF and LP VDD ON). Cyclic sense is a specific detection of an event on
an SGx, during the cyclic activation of the SGx input. Cyclic sense principle (synchronous cyclic sense):
A dedicated timer allows to select a cyclic sense period from 3.0 to 512 ms (selection in timer B). At the end of the period, the SGx is
activated for a duration of tSCAN. During the TSCAN duration, the SGx is monitored. If it is it the expected level, the device detects a wake-
up. Cyclic sense can operate for both Low-power modes: Low-power VDD ON and Low-power VDD OFF.
Cyclic sense period is selected by the SPI configuration prior to entering Low-power mode. The expected level on SGx is selected at the
time the device is set into Low-power mode. This means prior to entering Low-power mode, SGx must be activated, so the level of SGx
can be sampled. During device Low-power mode, if the opposite level on SGx is reached during the SGx activation mode, the device
wakes up.
During Cyclic Sense active time (tSCAN), the level of SGx is the same as the one before entering Low-power mode. So full flexibility is
offered, as the SGx high-side or low-side switch can be activated by the SPI in Normal mode. The level of SGx is sensed during the SGx
active time, and is deglitched for a duration of typically 30 μs. This means SGx should be in the expected state for a duration longer than
the deglitcher time.
4.3.1.3.6
CAN functional block
The 33909 has an enhanced High Speed CAN physical interface. A single CAN5V pin is used for a capacitor for the internal 5.0 V regulator
to power the CAN interface. There is also a single dedicated Ground for the CAN bus (CANGND).
The CAN5V regulator supplies a maximum of 200 mA, while the CAN physical layer is designed to current limit to less than 100 mA in
case of a short on the bus. If the user does not use the physical layer, the user may use the CAN5V supply as another supply rail. The
CAN5V regulator turns OFF in LP modes.
VBATP
Pattern
Detection
Wake-up
Receiver
SPI & State machine
CAN5V
Driver
QH
RIN
2.5V
CANH
CANL
Differential
Receiver
RXD
TXD
RIN
5VCAN
Driver
QL
SPI & State machine
SPI & State machine
Thermal
Failure Detection
& Management
Figure 20. CAN interface block diagram
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FUNCTIONAL DEVICE OPERATION
4.3.1.3.7
TX/RX mode
In TX/RX mode, both the CAN driver and the receiver are ON. In this mode, the CAN lines are controlled by the TXD pin level, and the
CAN bus state is reported on the RXD pin.
The CAN5V regulator must be ON. It supplies the CAN driver and receiver.
TLRD
TXD
0.3 CAN5V
0. 7 CAN5V
TLDR
0.7 CAN5V
RXD
0.3 CAN5V
Figure 21. CAN propagation delays TXD to CAN and CAN to RXD
TTRD
TXD
VDIFF
RXD
0.7 CAN5V
TTDR
0.3 CAN5V
0.9V
TRRD
0.5V
TRDR
0.7 CAN5V
0.3 CAN5V
Figure 22. CAN propagation delays TXD to CAN and CAN to RXD
VBAT
VBATP
VDD
100nF
2.2µF
CANH
CANL
Signal
generator
RBUS
60O
CBUS
100pF
TXD
RXD
All pins are not
shown
15pF
GND
Figure 23. CAN test setup
4.3.1.3.8
Sleep mode
Sleep mode is a reduced current consumption mode. CANH and CANL lines are terminated to GND via the RIN resistor (typ 25 kΩ). In
order to monitor bus activities, the CAN wake-up receiver is ON.
Wake-up events occurring on the CAN bus pin are reporting by dedicated flags in SPI, and results in a device mode transition out of Low-
power mode.
4.3.1.3.9
Listen only mode
This mode is used to disable the CAN driver, but leave the CAN receiver active. In this mode, the device is only able to report the CAN
state on the RXD pin. The TXD pin has no effect on CAN bus lines. The CAN5V regulator must be ON.
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FUNCTIONAL DEVICE OPERATION
4.3.1.3.10 CAN interface supply
The supply voltage for the CAN driver is the CAN5V pin. The CAN interface also has a supply path from the battery line, through the
VBATP pin. This path is used in CAN sleep mode to allow wake-up detection. During CAN communication (transmission and reception),
the CAN interface current is sourced from the CAN5V pin. During CAN Low-power mode, the current is sourced from the VBATP pin.
4.3.1.3.11 CAN driver operation in TX/RX mode
The CAN drive can be enabled via SPI as soon as the device is in normal mode. When the CAN interface is in Normal mode, the driver
has two states: recessive or dominant. The driver state is controlled by the TXD pin. The bus state is reported through the RXD pin.
When TXD is high, the driver is set in the recessive state, and CANH and CANL lines are biased to the voltage set with CAN5V divided
by 2, or approximately 2.5 V. When TXD is low, the bus is set into the dominant state, and CANL and CANH drivers are active. CANL is
pulled low and CANH is pulled high.
The RXD pin reports the bus state: CANH minus the CANL voltage is compared versus an internal threshold (a few hundred mV).
If “CANH minus CANL” is below the threshold, the bus is recessive and RXD is set high.
If “CANH minus CANL” is above the threshold, the bus is dominant and RXD is set low.
Recessive State
TXD
Dominant State
CANH-DOM
CANL/CANH-
CANH
REC
2.5 V
CANL
High ohmic termination
CANL-DOM
(50 kΩ) to GND
RXD
Receiver
BUS Driver
(bus dominant set by other IC)
Go to sleep, Sleep
or Stand-by Mode
Normal or Listen Only Mode
Normal or Listen Only Mode
Figure 24. BUS signal in Tx/Rx and low-power mode_48LD
4.3.1.3.12 Minimum baud rate
The minimum baud is determined by the shortest TXD permanent dominant timing detection. The maximum number of consecutive
dominant bits in a frame is twelve (six bits of active error flag and its echo error flag). The shortest TXD dominant detection time of 300 μs
lead to a single bit time of: 300 μs/12 = 25 μs, so the minimum Baud rate is 1/25 μs = 40 kBaud.
4.3.1.3.13 Termination
The device supports differential termination resistors between CANH and CANL lines. Refer to device typical application.
4.3.1.3.14 Low-power mode
In Low-power mode, the CAN is internally supplied from the VBATP pin. In Low-power mode, the CANH and CANL drivers are disabled,
and the receiver is also disabled. CANH and CANL have a typical 25 kΩ impedance to GND. The wake-up receiver can be activated if
wake-up is enabled by the SPI command. When the device is set back into Normal mode, CANH and CANL are set back into the recessive
level. This is illustrated in Figure 24.
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FUNCTIONAL DEVICE OPERATION
4.3.1.3.15 Wake-up
When the CAN interface is in Sleep mode with wake-up enabled, the CAN bus traffic is detected. The CAN bus wake-up is a pattern wake-
up. The wake-up by the CAN is enabled or disabled via the SPI. There are two methods for wake-up, Three dominant pulses or a single
dominant pulse described in the figures below. The default condition is for the three dominant pulses to cause a wake-up.
CANH
Dominant
Pulse #1
Dominant
Pulse #4
Dominant
Pulse #2
Dominant
Pulse #3
CAN Bus
CANL
Incoming CAN message
Internal differential
wake-up receiver signal
min 650 ns
Internal wake-up signal
min 650 ns
min 1.2 us
max 1500 ns
max 120 µs
Figure 25. Three dominant pulses pattern wake-up
CANH
Dominant
Pulse #1
CAN Bus
CANL
Incoming CAN message
Internal differential
wake-up receiver signal
Internal wake-up signal
min 1.2 µs
max 2.5 µs
Figure 26. Single pulse pattern wake-up
4.3.1.3.16 CAN wake-up report
The CAN wake reporting is done via the device state machine.
4.3.1.3.17 Pattern wake-up
In order to wake-up the CAN interface, the wake-up receiver must receive a series of three consecutive valid dominant pulses, by default
when the CANWU bit is low. CANWU bit can be set high by SPI and the wake-up occurs after a single pulse duration of 1.0 μs (typ).
A valid dominant pulse is longer than 500 ns. The three pulses occur in a time frame of 120 μs, to be considered valid. When three pulses
meet these conditions, the wake signal is detected. This is illustrated by Figure 25.
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FUNCTIONAL DEVICE OPERATION
Standard Termination
CANH
C4
60
CAN Bus
CANL
C5
No Termination
CANH
CANL
C4
CAN Bus
C5
Figure 27. Typical application and bus termination options
4.3.1.3.18 State transition
CAN5V regulator OFF only in low-power, or disable by a SPI command. CAN5V can be enabled by SPI after power up and in the INIT
state. This gains the reset, time to charge the external capacitor and have the CAN5V active in Debug and Flash modes. Refer to the
Figure 19.
4.3.1.3.19 CAN bus diagnostic
The aim is to implement a diagnostic of bus short-circuit to GND, VBATP, and internal ECU 5.0 V. Several comparators are implemented
on CANH and CANL lines. These comparators monitor the bus level in the recessive and dominant states. The information is then
managed by a logic circuitry to properly determine the failure and report it. Table 8 indicates the state of the comparators in case of a bus
failure, and depending upon the driver state.
Table 8. CAN failure detection truth table
Driver recessive state
Driver dominant state
Failure description
Lg (threshold 1.75 V)
Hg (threshold 1.75 V)
Lg (threshold 1.75 V)
Hg (threshold 1.75 V)
No failure
1
1
0
1
CANL to GND
CANH to GND
0
0
0
1
0
0
0
0
Lb (threshold VBATP-2.0 V)
Hb (threshold VBATP-2.0 V)
Lb (threshold VBATP-2.0 V)
Hb (threshold VBATP-2.0 V)
No failure
0
1
1
0
1
1
0
1
0
0
1
1
CANL to VBATP
CANH to VBATP
4.3.1.3.20 Detection principle
In the recessive state, if one of the two bus lines are shorted to GND or VBATP, the voltage at the other line follows the shorted line, due
to the bus termination resistance. For example: if CANL is shorted to GND, the CANL voltage is zero, the CANH voltage measured by the
Hg comparator is also close to zero.
In the recessive state, the failure detection to GND or VBATP is possible. However, it is not possible with the above implementation to
distinguish which of the CANL or CANH lines are shorted to GND or VBATP. A complete diagnostic is possible once the driver is turned
on, and in the dominant state.
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FUNCTIONAL DEVICE OPERATION
Vr5
H5
Hb
VBAT (12-14V)
VDD
VRVB (VBAT-2.0V)
Vrvb
VDD (5.0V)
Vrg
H5
H5
TX
CANH
CANL
VR5 (VDD-0.43V)
Logic
Diag
CANH dominant level (3.6V)
Recessive level (2.5V)
Vrg
H5
H5
VRG (1.75V)
Vrvb
CANL dominant level (1.4V)
GND (0.0V)
Vr5
Figure 28. CAN bus simplified structure truth table for failure detection
4.3.1.3.21 Number of samples for proper failure detection
The failure detector requires at least one cycle of the recessive and dominant states to properly recognize the bus failure. The error is fully
detected after five cycles of the recessive-dominant states. As long as the failure detection circuitry has not detected the same error for
five recessive-dominant cycles, the error is not reported.
4.3.1.3.22 Bus clamping detection
If the bus is detected to be in dominant for a time longer than (TDOM), the bus failure flag is set and the error is reported in the SPI.
Such condition could occur in case the CANH line is shorted to a high voltage. In this case, current flows from the high voltage short-circuit
through the bus termination resistors (60 Ω), and the device CANH and CANL input resistors, which are terminated to internal 2.5 V
biasing or to GND (sleep mode).
Depending upon the high voltage short-circuit, the number of nodes, RIN actual resistor, and node state (sleep or active), the voltage
across the bus termination can be sufficient to create a positive dominant voltage between CANH and CANL, and RXD pin is low. This
would prevent start of any CAN communication, and thus a proper failure identification (requires five pulses on TXD). The bus dominant
clamp circuit helps to determine such failure situation.
4.3.1.3.23 RX permanent recessive failure
The aim of this detection is to diagnose an external hardware failure at the RX output pin and ensure a permanent failure at RX does not
disturb the network communication. If RX is shorted to a logic high signal, the CAN protocol module within the MCU does not recognize
any incoming message. In addition, it is not be able to easily distinguish the bus idle state and can start communication at any time. In
order to prevent this, an RX failure detection is necessary.
Figure 29. RX path simplified schematic, RX short to VDD detection
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FUNCTIONAL DEVICE OPERATION
4.3.1.4
Implementation for detection
The proposed implementation is to sense the RXD output voltage at each low to high transition of the differential receiver. Excluding the
internal propagation delay, the RXD output is low when the differential receiver is low. In case of an external short to VDD at the RXD
output, RXD is tied to a high level and can be detected at the next low to high transition of the differential receiver.
As soon as the RXD permanent recessive is detected, the RXD driver is deactivated. Once the error is detected, the flag is latched and
the driver is disabled.
4.3.1.4.1
Recovery condition
The internal recovery is done by sampling a correct low level at TXD, as shown in Figure 30.
CANL & H
Diff output
Sampling
Sampling
RXD output
RX flag
Rx short to VDD
RX flag latched
RX no longer shorted to VDD
The RX flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register.
Figure 30. RX path simplified schematic, RX short to VDD detection
4.3.1.4.2
Important information for bus driver reactivation
The driver stays disabled until the failure is cleared (RX is no longer permanent recessive). One transition on the CAN bus (internal
differential receiver transition) and the bus driver is activated by entering into Normal mode.
4.3.1.4.3
TXD permanent dominant
Principle
If the TXD is set to a permanent low level, the CAN bus is set into dominant level and no communication is possible. The device has a
TXD permanent timeout detector. After the timeout, the bus driver is disabled and the bus is released into a recessive state. The TXD
permanent flag is set.
Recovery
The TXD permanent dominant is also used and activated, in case of a TXD short to RXD. The recovery condition for a TXD permanent
dominant (recovery means the re-activation of the CAN drivers) is done by entering into a Normal mode controlled by the MCU, or when
TXD is recessive while RXD changes from recessive to dominant.
4.3.1.5
TXD to RXD short-circuit
Principle
4.3.1.5.1
In case TXD is shorted to RXD, during incoming dominant information, RXD is set low. Consequently, the TXD pin is low and drives CANH
and CANL into a dominant state. Thus the bus is stuck in dominant. No further communication is possible.
4.3.1.5.2
Detection and recovery
The TXD permanent dominant timeout activates and releases the CANL and CANH drivers. However, at the next incoming dominant bit,
the bus is stuck in dominant again. The recovery condition is same as the TXD dominant failure.
4.3.1.5.3
CAN functional pin: TXD
CAN bus transmit data input. Internal pull-up to VDD
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FUNCTIONAL DEVICE OPERATION
4.3.1.5.4
CAN functional pin: RXD
CAN bus receive data output.
4.3.1.5.5
CAN functional pin: CANH
CAN high output.
4.3.1.5.6
CAN functional pin: CANL
CAN low output.
4.3.1.6
LIN interface functional block
The 33909 has 4 LIN interfaces which fulfill LIN protocol specification 2.1 and SAEJ2602-2. The LIN pin represents the single-wire bus
transmitter and receiver, and is suited for automotive bus systems. The LIN interface is only active during Normal mode. The CAN5V
regulator serves as the internal supply for the LIN and must be enabled for LIN functionality.
The LIN driver is a low-side MOSFET with internal overcurrent thermal shutdown. An internal pull-up resistor with a serial diode structure
is integrated, so no external pull-up components are required for the application in a slave node. An additional pull-up resistor of 1.0 kΩ
must be added when the device is used in the master node. The LIN pin exhibits no reverse current from the LIN bus line to VBATP, even
in the event of GND shift or VBATP disconnection. The transmitter has a 20 kbps baud rate (normal mode) or 10 kbps baud rate (slow
mode) which is configurable via the SPI.
The receiver thresholds are ratiometric with the device supply pin. If the LIN voltage goes below the LIN undervoltage threshold (VUVL
,
VUVH), the bus enters in recessive state, even if communication is sent on TXD. In case of LIN Thermal Shutdown, the transceiver and
receiver are disabled. When the temperature is below the TLINSD, the TSD flag must be cleared and the LIN is able to continue
communication. The LIN driver remains OFF until the TSD flag is cleared.
4.3.1.6.1
Data input pin (TXD)
The TXD input pin is the MCU interface to control the state of the LIN output. When TXD is LOW (dominant), LIN output is LOW; when
TXD is HIGH (recessive), the LIN output transistor is turned OFF. The threshold is 3.3 V and 5.0 V compatible. This pin has an internal
pull-up current source to force the recessive state, in case the input pin is left floating.
4.3.1.6.2
Data output pin (RXD)
The RXD output pin is the MCU interface, which reports the state of the LIN bus voltage. In Normal or Slow mode, LIN HIGH (recessive)
is reported by a high voltage on RXD; LIN LOW (dominant) is reported by a low voltage on RXD. In Fast mode, the RXD output signal is
inverted compare to the LIN: a high level on the LIN reports a low level on RXD, and a low level on the LIN reports a high level on RXD.
The RXD output structure is a buffer tristate output.
It is the receiver output of the LIN interface. The low level is fixed. The high level is dependant on the VDD voltage. If VDD is set at 3.3 V,
RXD VOH is 3.3 V. If VDD is set at 5.0 V, RXD VOH is 5.0 V. In the sleep mode, RXD is high-impedance. Due to internal biasing, the RXD
pin cannot be pulled up to another supply besides VDD. When a wake-up event is recognized from the LIN bus pin, RXD is pulled LOW
to report the wake-up event. For this, an external pull-up resistor connected on RXD pin is needed.
4.3.1.6.3
Normal mode
In the Normal mode, the LIN bus can transmit and receive information. The default condition is the 20 kbps mode and has slew rate and
timing compatible with Normal Baud Rate and LIN protocol specification 2.1. The 10 kbps selection is SPI configurable and has slew rate
and timing compatible with Low Baud Rate. From Normal mode the device can enter in Fast Baud Rate (Toggle function).
4.3.1.6.4
Fast mode
In the Fast mode, the slew rate is around 10 times faster than the Normal mode. This allows very fast data transmission (>100 kbps), for
instance, for electronic control unit (ECU) tests and microcontroller program downloads. The bus pull-up resistor might be reduced to
ensure a correct RC time constant in line with the high baud rate used. Fast mode is entered via the SPI.
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4.3.1.6.5
Sleep mode
In the Sleep mode, the transmission path is disabled and the device is in low-power mode. Supply current from VBATP is very low. Wake-
up can occur from LIN bus activity. After a wake-up event, the device enters in Awake Mode. In the Sleep mode, the internal 725 kΩ pull-
up resistor is connected and the 30 kΩ disconnected.
4.3.1.6.6
Remote wake from LIN bus (awake transitional mode)
The LIN bus wake-up is recognized by a recessive-to-dominant transition, followed by a dominant level with a duration greater than 70 μs,
followed by a dominant-to-recessive transition. This is illustrated in Figure 7 and Figure 8. Once the wake-up is detected, the device enters
to the Awake transitional mode with RXD pulled LOW.
4.3.2
Fail-safe features
Table 9 describes the protections.
Table 9. Fail-safe protections
Block
Fault
Function mode
Condition
Fallout
Recovery
undervoltage
LIN voltage < 5.8 V (Typical)
LIN transmitter in recessive state
Condition gone
Normal
TXD pin
permanent
Dominant
TXD pin low for more then 1.0 s (Typ)
Temperature > 160 °C (Typ)
LIN transmitter in recessive state
Condition gone
Condition gone
LIN
LIN transmitter in recessive state
High-side turned off.
LIN thermal
shutdown
Normal and
Awake modes
4.3.2.0.1
LIN functional pin: LINx
LIN bus.
4.3.2.0.2
LIN functional pin: TXD-Lx
LIN bus transmit data input. Includes an internal pull-up resistor to VDD
.
4.3.2.0.3
LIN functional pin: RXD-Lx
LIN bus receive data output
4.3.2.1
VPRE regulator functional block
The 33909 has a VPRE pre-regulator designed to run as a non-inverting Buck - Boost supply for the VDD and VAUX power supplies. This
regulator provides efficient DC-DC conversion as well as boost operation at low input voltage (low battery). The output voltage level is
6.5 V.
The converter has both a high and low-side FET and requires a single inductor for operation. The high-side FET is integrated into the
33909. The low-side Boost FET is external. The converter uses external diodes instead of synchronous switches to reduce the number
of pins.
The 33909 has a Low-power mode to reduce quiescent current when full power is not needed by the micro. In Low-power mode, the buck
boost converter is placed in a zero quiescent current mode and a small internal regulator is employed to power the VPRE node.
The VPRE supply contains a thermal limit circuit, which is used to supply a thermal warning as well as provide a thermal limit which turns
OFF the IC. A flag exists for both of these functions. When thermal limit is reached the VPRE supply turns off. The thermal shutdown limit
was designed to be above the other IC thermal thresholds. The user should take care when the IC thermal limits are reached in order to
maintain Voltage regulator operation of VPRE and VDD
.
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FUNCTIONAL DEVICE OPERATION
BOOTSTRAP
VBATP
VSW
Control
VPREGATE
VBATP
VPRE
COMP1 COMP2
Figure 31. VPRE block diagram
4.3.2.1.1
VPRE pin functions:
There are four pins associated with the VPRE regulator
• VPREGATE - Gate drive for low-side (Boost) FET.
• VSW - Switching node of high-side (Buck) FET.
• BOOT - Supply for high-side (internal) pre-driver.
• VPRE - Pre-regulator output (6.5 V).
4.3.2.1.2
VPRE pin functions: BOOT
An external bootstrap 0.1 μF capacitor connected between VSW and the BOOT pin is used to generate a high voltage supply for the high-
side driver circuit of the buck controller. The capacitor is pre-charged to approximately 10 V, while the internal FET is off. On switching,
the VSW pin is pulled up to VBATP, causing the BOOT pin to rise to approximately VBATP + 10 V.
4.3.2.1.3
VPRE pin functions: VPREGATE
This is an output for driving an external FET for boost mode operation. Due to the fact the gate drive supply voltage is VPRE, the external
power MOSFET should be a logic level device. It also has to have a low RDS(ON) for acceptable efficiency. During Buck mode, this gate
output is held low.
To use the 33909 in Buck Only mode, the VPREGATE pin is held at Ground and an internal comparator alerts the IC it is in Buck Only
mode.
4.3.2.1.4
VPRE pin functions: VPRE
The output of the switching regulator is brought into the chip at the VPRE pin. This voltage is required for both the switching regulator
control and as the supply voltage for all the linear regulators. The VPRE pin functions as a supply rail for some IC functions, including the
rail for the SG input current sources. The VPRE supply also supplies the CAN5V internal rail.
4.3.2.1.5
VPRE pin functions: VSW
The internal switching transistor is an N-channel power MOSFET. The RDS(ON) of this internal power FET is approximately 0.25 Ω at
+125 ºC. The nominal instantaneous current limits well below the saturation current of the MOSFET and external surface mounted
inductor, to supply the current for the linear regulators connected to the VPRE pin. The input to the drain of the internal n-channel MOSFET
must be protected by an external series blocking diode, for reverse battery protection.
4.3.2.1.6
VPRE external components
The VPRE power supply requires external components for the Buck and Boost mode architecture. The VPRE supply uses an external
inductor, MOSFET and two diodes. Buck-Boost usage case
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FUNCTIONAL DEVICE OPERATION
Usage of the Buck-Boost feature is the most widely used case. In this case, all of the external components are populated and VPRE
produces approximately 6.5 V through the full battery operation range. This use case allows the 33909 to remain fully functional during
the battery crank profile down to 2.5 V.
The Boost circuitry remains OFF when the VBATP pin is above the VBATPTHD threshold and the Buck circuitry operates as required in
Boost mode when the VBATP pin is below VBATPTHU as seen in Figure 32. In the range between VBATPTHD and VBATPTHU, the IC
operates as needed to supply VPRE at 6.5 V.
7.5v
VBATP
VBATPTHD
6.5v
VBATPTHU
VBATPBOOSTNOT
VBATPBUCKNOT
Figure 32. VPRE buck-boost voltage levels
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FUNCTIONAL DEVICE OPERATION
4.3.2.2
Buck usage case
A second option for the user is to use only the Buck circuitry and not the Boost circuitry (saving the added cost if Boost is not required).
When using the Buck only mode, the user does not populate the low-side FET (VPREGATE) and the associated diode. In this case, the
user grounds the VPREGATE and the 33909 detects this during startup. The VBATP pin voltage range in this mode is ~7.0 V to 35 V.
As the battery voltage decreases, the high-side switch turns ON to 100% duty cycle and operate in a “pass thru” mode. The following
figures illustrate some of the device mode transitions.
Power up to
Normal Mode to Sleep
Mode (VDD Off)
Normal Mode to STOP
Normal Mode
A
B
B
C
B
D
Mode (VDD On)
Vpre_UV
VBATP
Vpre
VDD_UV
VDD
CAN5V
VAUX
INT_B
RESET_B
SPI
1
2
3
4
5
3
4
6
Modes
Notes: SPI communications.
1) INIT command
2) Watchdog refresh (INIT to Normal)
3) Normal SPI commands as needed
4) Low power configuration setup
5) Sleep mode command
6) Stop mode command
Figure 33. Power up to normal and to low-power modes
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FUNCTIONAL DEVICE OPERATION
Wake up from Low Power
VDD off mode
Wake up from Low Power
B
C
B
D
VDD on mode
VBATP
Vpre
VBATP
Vpre
VDD
VDD
CAN5V
CAN5V
VAUX
INT_B
VAUX
INT_B
RESET_B
SPI
RESET_B
SPI
7
8
7
8
Modes
CAN BUS
LIN BUS
CAN BUS
LIN BUS
CAN wake
up pattern
CAN wake
up pattern
LIN Wake
up filter
LIN Wake
up filter
SGx
SGx
FWU
Timer
FWU
Timer
Start
Stop
Start
Stop
FWU Timer (SPI selectable)
FWU Timer (SPI selectable)
Wake up detected
IDD
SPI
IDD 3mA typ
IDD deglitcher or timer
9
Notes:
7) SPI communications as needed
8) Watchdog refresh
Wake up detected
9) SPI communication (except watchdog if configured)
Figure 34. Wake-up from low-power modes
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FUNCTIONAL DEVICE OPERATION
4.3.2.3
V
supply
DD
The VDD output is an external LDO regulator supplying +5.0 V (3.0 V selectable via a different part number) with 2.0% accuracy. The
supply is capable of sourcing a maximum of 500 mA steady state current from VPRE (6.5 V typical) for VBATP pin voltages from
V
DD
2.5 V to 35 V (45 V transient) [Buck only to V
= 7.0 V]. This regulator incorporates external current limit short-circuit protection and
BATP
internal thermal protection. The regulator remains on in current limitation. The voltage output is stable under all load/line conditions. The
rail does not turn on until the specified voltage can be obtained from the VPRE node.
V
DD
4.3.2.3.1
VDD pins
There are three pins associated with the VDD regulator
• VDDE - Emitter connection for external LDO device.
• VDDB - Base connection for external LDO device.
• VDD - Feedback voltage and main supply voltage node
4.3.2.3.2
VDD pin functions: VDDE
Input pin used to sense the voltage (V
) across the external sense resistor from VPRE to VDDE. Current limit is derived from this
DDSNS
sense voltage measurement. Kelvin lines is used by the user to ensure proper voltage sensing, therefore careful layout planning is
required.
4.3.2.3.3
VDD pin functions: VDDB
Output pin used to for the base drive of the external LDO device.
4.3.2.3.4
VDD pin functions: VDD
Input pin used for feedback control loop of the V supply. A Kelvin trace is provided to the VDD pin for proper feedback control.
DD
4.3.2.3.5
VDD external components
The V power supply requires an external PNP be connected to the VPRE pin. The V supply uses an external resistor to monitor and
DD
DD
limit the V
voltage and provide load current limit; this is placed between the VPRE and VDDE pins.
DDSNS
4.3.2.4
V
regulator functional block
AUX
The V
regulator uses an external PNP pass device referenced to the pre regulator voltage, VPRE, via an internal short to battery
AUX
protection switch. V
is capable of driving up to 200mA of load current and can be configured for an output voltage of 5.0 V or 3.3 V
AUX
with 3.0% accuracy. Additionally, V
can be configured as a tracking regulator. In tracking mode, V
tracks the V regulator voltage
AUX
AUX DD
to within 15 mV, but note that tracking mode is only possible when the V regulator is configured as a 5.0 V supply, as shown in the
DD
Table 10.
The V
regulator is short to battery protected and current limited (200 mA min.). No external components are required for these two
AUX
features. In low-power mode, V
is disabled and draws zero quiescent current. Upon power up, V
is disabled. V
is enabled by
AUX
AUX
AUX
writing to bits 7 and 6 of the REG register as shown by the following:
Table 10. REG register
Bits
Description
VAUX[1], VAUX[0]- Vauxilary regulator control
Regulator OFF
b7 b6
00
Regulator ON. Undervoltage (UV) and overcurrent (OC) and overvoltage (OV) monitoring flags not reported. VAUXdisable in case OC or UV
detected after 1.0 ms blanking time (monitoring of flags not reported).
01
10
11
Regulator ON. Undervoltage (UV) and overcurrent (OC) and overvoltage (OV) monitoring flags active. VAUX disable in case OC or UV
detected after 1.0 ms blanking time. (monitoring of flags not reported).
Regulator ON. Undervoltage (UV) and overcurrent (OC) and overvoltage (OV) monitoring flags active. VAUX disable in case OC or UV
detected after 25 μs blanking time.
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FUNCTIONAL DEVICE OPERATION
At power up, when the device is in its INIT state, the REG INIT register can be written to set V
shown by the following:
to 3.3 V or 5.0 V or 5.0 V tracking, as
AUX
Table 11. Setting VAUX to 3.3 V or 5.0 V
Bits
Description
[VAUX5/3]- Select Vauxilary output voltage
VAUX = 3.3 V
b2
0
VAUX = 5.0 V
1
Tracking Enable
b1
0
VAUX is independent of VDD
VAUX tracks VDD (VAUX does not turn ON if set in 3.3 V part)
1
Writing to this initialization register is locked out when the device leaves the INIT state. Also, note that the logic does not allow tracking
mode if V is set to 3.3 V, as Table 12 illustrates.
DD
Table 12. VAUX tracking vs. supply
VDD value
VAUX value
VAUX tracking
SPI Configurable
Not capable
VAUX supply
SPI configurable
5.0 V
5.0 V
3.3 V
3.3 V
5.0 V
3.3 V
5.0 V
3.3 V
Default
Not capable
SPI configurable
Default
Not capable
The V
regulator also contains a digitally controlled soft start to minimize overshoots upon power up. Also included in V
, is a fold-
AUX
AUX
back current limit.
4.3.2.4.1
VAUX pins
There are three pins exclusively associated with the V
regulator
AUX
• VAUXB - This pin is connected to the base of the external PNP and provides the necessary base current.
• VAUXE - This pin is connected to the emitter of the external PNP transistor. 33909 includes short to battery blocking FET between
VPRE and VAUXE.
• VAUX - This pin is the feedback pin as well as the main supply node for supply the voltage (3.3/5.0 V).
Additionally:
• VPRE - supply to VAUX and also note all V
load current flows into 33909 via the VPRE pin before reaching the external PNP.
AUX
4.3.2.4.2
VAUX external components
VAUX requires an external PNP with sufficient beta to provide up to 200 mA load current within the constraints of the max base drive
available from the VAUXB pin. Also, a capacitor is required for loop stability and transient load response.
4.3.2.4.3
VAUX fault mode behavior
Current Limit: V
limits the load current to 200 mA minimum, 360 mA maximum. A current limit event can be reported via the SPI and
AUX
INT pin if configured as such in the REG register.
Undervoltage: After V has come up, an undervoltage event can be reported via the SPI and INT pin if configured as such in the REG
AUX
register. The undervoltage event disables the V
regulator if configured as such in the REG register. If configured to disable, the V
AUX
AUX
can only be turned back ON by re-writing to the REG register.
Overvoltage: Overvoltage, or short to V causes an internal switch between the VPRE and VAUX_E to be turned off. This is done to
BAT
protect the VAUX PNP device and other things on the Vpre line. This event is not latched. When the overvoltage event has ended, the
internal switch is re-activated and VAUX returns to normal operation.
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FUNCTIONAL DEVICE OPERATION
4.3.2.5
VBATSNS
The 33909 contains a VBATSNS function to allow the user to see the battery voltage via the AMUX pin. This pin connects directly to the
battery (before the series diode connected to VBATP). The VBATSNS is used for additional functions internal to the die and should have
pcb traces capable of running up to some current. The ratio of the resister divider is 1/5.94 (5.0 V part) or 1/8.9 (3.3 V part).
4.3.2.5.1
VBATSNS pin functions: VBATSNS
Direct battery voltage input sense. A series resistor is required to limit the input current during high voltage transients.
4.3.2.5.2
MUX output (AMUX)
Various signals may be brought out via the analog multiplexer (AMUX) pin. The AMUX pin is referenced to V and can be selected via
DD
the SPI. The signals which can be viewed on the AMUX are located in Table 13. The AMUX output pin is clamped to a maximum of V
volts regardless of the higher voltages present on the input pin.
DD
For SG inputs, when an input has been selected to output on the AMUX, the corresponding bit in the MISO data stream is logic [0]. When
selecting a channel to be read out the AMUX, the user may also set the desired current (16 mA, 2.0 mA, or high-impedance) in the SPI
word. The MCU may change or update the analog select register via software at any time in Normal Mode when set for SPI selection.
Table 13. AMUX SPI selection
Bits
Description
MUX_4, MUX_3, MUX_2, MUX_1, MUX_0 - Selection of the device external input signal or internal signal to be measured
at AMUX pin
b8 b7 b6 b5 b4 b3
All functions disable. AMUX pin high-impedance
Voltage at SG0
0 00000
0 00001
0 00101
0 00110
0 00111
0 01000
0 01011
0 10001
Voltage at SG1
Voltage at SG2
Voltage at SG3
Voltage at SG4
Voltage at SG5
Ground
Voltage at VBATSNS pin. Refer to electrical table for attenuation ratio (approximately 6 for VDD = 5.0 V, approximately 9
for VDD = 3.3 V) [Default]
0 10010
0 10011
Device internal temperature sensor voltage
A diode/circuit is brought out the AMUX pin to allow for knowledge of the temperature on the IC. The diode is characterized and a voltage/
temperature curve generated to allow for temperature monitoring of the IC.
4.3.2.5.3
MUX pin functions: AMUX
The MUX output delivers an internal analog voltage to the MCU A/D input. Value is selected via the SPI. Output is clamped at VDD.
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4.3.2.5.4
Undervoltage reset and reset function (RST_B)
The RST_B pin is an open drain structure with an internal pull-up current source. The low-side driver has limited current capability when
asserted low, in order to tolerate a short to high level (i.e short to 5.0 V).The RST_B pin voltage is monitored in order to detect a failure
(e.g. RST_B pin shorted to 5.0 V or GND).
During sleep mode the under voltage detect circuit polls during normal scan timer periods to determine if V
condition. If the IC is in under voltage the IC wakes up and issues a reset to the system.
is in an undervoltage
BATP
The RESET pin reports the MCU undervoltage condition at the VDD pin, as well as a failure in the watchdog refresh operation. VDD
undervoltage reset operates also in Low-power V ON Mode.
DD
The undervoltage threshold at VDD can lead to a Reset or an Interrupt. This is selected by the SPI. When “RST-TH1-5”is selected in
Normal mode, an INT is asserted when VDD falls below “RST-TH1-5”. This allows the MCU to operate in a degraded mode (e.g. with V
= 4.0 V).
DD
4.3.2.5.5
RESET pin functions: RST_B
The RESET pin is an open drain structure with an internal pull-up current source.
4.3.2.5.6
Serial peripheral interface (SPI)
The 33909 contains a serial peripheral interface consisting of Serial Clock (SCLK), Serial Data Out (MISO), Serial Data In (MOSI), and
Chip Select Bar (CS_B). The SPI interface is used (as applicable) to provide configuration, control, and status functions. This device is
configured as an SPI slave. The 33909 contains a data valid method via SCLK input to keep non-modulo 32-bit transmissions from being
written into the IC.
4.3.2.5.7
Chip select low (CS_B)
The CS_B input selects this device for serial transfers. On the falling edge of CS_B, the MISO pin is released from tri-state mode, and all
status information are latched in the SPI shift register. While CS_B is asserted, register data is shifted in the MOSI pin and shifted out the
MISO pin on each subsequent SCLK. On the rising edge of CS_B, the MISO pin is tri-stated and the fault register reloaded (latched) with
the current filtered status data. To allow sufficient time to reload the fault registers, the CS_B pin must remain low for a minimum of t
CSN
prior to going high again. The CS_B is immune to spurious pulses of shorter duration than t
neither status bits nor control bits are altered).
(MISO may come out of tri-state, but
CSGRT
The CS_B input contains a passive pull-up to VDD to command the de-asserted state should an open circuit condition occur. This pin has
threshold compatible voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply.
4.3.2.5.8
Serial clock (SCLK)
The SCLK input is the clock signal input for synchronization of serial data transfer. This pin has threshold compatible voltages allowing
proper operation with microprocessors using a 3.3 to 5.0 volt supply.
When CS_B is asserted, both the Master Microprocessor and this device latch input data on the rising edge of SCLK. The SPI master
typically shifts data out on the falling edge of SCLK, while this device shifts data out on the rising edge of SCLK, to allow more time to
drive the MISO pin to the proper level.
This input is used as the input for the modulo-32 bit counter validation. Any SPI transmissions which are NOT exact multiples of 32-bits
(i.e. clock edges) is treated as an illegal transmission. The entire frame aborts and no information is changed in the configuration or control
registers. The entire frame aborts and no information is changed in the configuration or control registers.
4.3.2.5.9
Serial data output (MISO)
The MISO output pin is in a tri-state condition when CS_B is negated. When CS_B is asserted, MISO is driven to the state of the MSB of
the internal register and is the first bit transmitted on MISO. This pin supplies a “rail to rail” output, depending on the voltage at the VDD pin.
4.3.2.5.10 Serial data input (MOSI)
The MOSI input takes data from the master microprocessor while CS_B is asserted. The MSB is the first bit of each word received on
MOSI and the LSB is the last bit of each word received on MOSI. This pin has a threshold level compatible input voltages allowing proper
operation with microprocessors using a 3.3 to 5.0 V (V ) supply.
DD
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FUNCTIONAL DEVICE OPERATION
4.3.2.5.11 Secured SPI description
A request is done by sending a specific SPI command the 33909 device provides an unpredictable “random code” on MISO. Software
must perform a logical change on the code and return it to the device with the new SPI command to perform the desired action. The
“random code” is different at every exercise of the secured procedure and can be read back at any time. The SPI secure uses the Special
MODE register for the following transitions:
- from Normal mode to Init mode
- from INIT mode to activate SAFE_B mode
- from Normal mode to Flash mode
- from Normal mode to Reset mode (reset request).
- from Normal mode to Reset SG registers (reset request).
“Random code” is also used when the “advance watchdog” is selected.
Changing of device critical parameter
Some critical parameters are configured one time at device power ON only, while the batfail flag is set in the INIT mode. If a change is
required while device is no longer in INIT mode, device must be set back in INIT mode using the secured SPI procedure.
4.3.2.5.12 SPI control register definition for SBC operations
The device uses a 32 -bit SPI word and does not have the ability to daisy chain to another IC. The IC decodes the first byte of the MOSI
word and supply the requested data on the following 3 bytes. In read register mode, the IC decodes the first byte and provides the full
contents of the registers called out in the address in the next three bytes. This causes the device status (12-bits) to be cut off at 8-bits.
In write register mode, the IC decodes the first byte then writes the contents of the MOSI word to the correct address. The MISO word
sends the full device status and the contents of all the SG registers. In the read flags mode, the IC decodes the first byte and provides the
full contents of the device flag depending on the address. In some cases the first bit of the second byte (bit 23 is used to determine which
registers are provided). The MISO output is the full device status along with the contents of the selected device flags address.
The SPI word structure is as follows:
MOSI, Master Out Slave In bits:
• bits 31 and 30 (called C1 and C0) are control bits to select the SPI operation mode (write control bit to device register, read back of
the control bits, read of device flag).
• bit 29 to 24 (A5 to A0) to select the register address (read and write).
• bits 23 to 0 (D23 to D0): control bits
MISO, Master IN Slave Out bits:
• bits 31 to 20 is the Device status registers (Do31 to Do20)
• bits 19 to 17 (Do19 to Do17) are unused in normal (write) MISO words.
• bits 16 to 0 (Do16 to Do0) the SGn Status register bits.
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SPI Bit 31 30 29 28 27 26 25 24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C1
C0
A5
A4
A3
A2
A1
A0
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MOSI
Control bits
Register Address
Data
Do
16
Do
15
Do
14
Do
13
Do
12
Do
11
Do
10
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
Do9
Do8
Do7
Do6
Do5
Do4
Do3
Do2
Do1
Do0
MISO
LIN23-G
RST
SG Status registers
TRAN-G VREG-G
CAN-G
INTb
VPRE-G SAFE-G
Device Status
LIN01-G
SG-G
S20
WU
Tlim
Do
19
Do
18
Do
17
Do
16
Do
15
Do
14
Do
13
Do
12
Do
11
Do
10
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
Do9
Do8
Do7
Do6
Do5
Do4
Do3
Do2
Do1
Do0
Reg
Device Status
Extended Device Status, Register Control bits or Device Flags
Figure 35. SPI word
Table 14. SPI control bits
Control bits MOSI [31-30] C1-C0
Type of command
Note
Allows user to read back any register.
Read back of register content
00
Write to register address, to control device operation and Write to any register for operational control.
read back of device status register and SG status register This SPI word results in the “normal” MISO SPI
01
set.
pattern.
Read back device flags. There are multiple flag
registers containing various device information
of interest.
Read of device flags form a register address
Reserved
10
11
Not used
The device contains several registers. Their address is coded on 6-bits (bits 29 to 24). Each register controls or reports part of the device
function. Data can be written to the register to control the device operation or set the default value or behavior. Every register can also be
read back to ensure its content (default setting or value previously written) is correct.
In addition, some of the registers are used to report device flags. The device returns one of three messages, a read of an existing register,
normal MISO, or a register set of Flags depending on the previous command. After a POR the default word is for the normal MISO
registers to be read out with the next word determined by the previous SPI command control bits.
MISO: When a write operation is performed to store data or control bit into the device, MISO pin report a 32-bits fixed device status
composed of 4 bytes: In a read operation, MISO reports the fixed device status (bits 31 to 24) and the next 24-bits are the content of the
selected register is the list of device registers and their associated address, coded with bits 29 to 24.
Table 15. SPI command overview
Address MOSI
[31-30]A29...A24
Quick reference
name
Description
Functionality
Unused
00_0000
00_0001
00_0010
Memory Word A
RAM_A
1) Write “data word” to register address. 2) Read back “data word”
from register address
Memory Word B
RAM_B
Init REG
Init W/D
Init MISC
Initialization Regulators
Initialization Watchdog
Initialization Miscellaneous functions
1) Write “device initialization control bits” to register address. 2)
Read back “initialization control bits” from register address
00_0011
00_0100
1) Write to register to select device Specific Mode, using “Inverted
Random Code”. 2) Read “Random Code”.
Specific Modes
SPE_MODE
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Table 15. SPI command overview (continued)
Address MOSI
Description
Quick reference
name
Functionality
[31-30]A29...A24
Timer_A: W/D & Low-power MCU
consumption
TIM_A
TIM_B
TIM_C
1) Write “timing values” to register address. 2) Read back register
“timing values”
Timer_B: Periodic scan & Cyclic Interrupt
00_0101
Timer_C: W/D Low-power & Forced Wake-
up
1) Write “device control bits” to register address. 2) Read back
register “control bits”
Analog Multiplexer
Watchdog Refresh
Interrupt Control
MUX
00_0110
00_0111
00_1000
W/D
Watchdog Refresh Commands
1) Write “device control bits” to register address, to select device
operation. 2) Read back register “control bits”
Interrupt
1) Write to register to select Low-power mode, with optional
“Inverted Random code” and select wake-up functionality. 2)
Read operations: Read back device “Current Mode” Read
“Random Code”, Leave “Debug Mode”
Mode register
MODE
00_1001
Regulator Control
REG
CAN
00_1010
00_1011
CAN interface control
1) Write “device control bits” to register address, to select device
operation. 2) Read back register “control bits”. 3) Read device
flags from each of the register addresses.
LIN 0-1
LIN01
LIN23
SGWU
00_1100
00_1101
00_1110
LIN 2-3
Enable for wake-up from sleep after a change of state for SG
inputs: Wake-up enable = 1, Non-wake-up = 0 (Default = 1)
SG wake-up enable
Enable polling at 1.0 ms for fast wake-up independent of nominal
sleep polling timer: Override polling settings for SG5-0 to
1.0 ms = 1, use polling setting as defined in sleep state command
= 0 (Default = 0)
Fast scan for SG5-0
SGFS
00_1111
01_0000
Enable for wake-up from sleep after a change of state for SG
inputs after three consecutive polling results confirming change of
state: Wake-up enable = 1, Non-wake-up = 0 (Default = 0)
SG wake-up delay enable
SGWUD
Configure Wetting current sources to desired current level for
SG4-0 (Default = 101 = 16 mA)
Wetting Command Register 0
Wetting Command Register 1
SGM0
SGM1
01_0001
Configure Wetting current sources to desired current level for
SG5 (Default = 101 = 16 mA)
01_0010
Enable Wetting current source timer: Enable Wetting current
source timer = 1, disable – Wetting current ON full time = 0
(Default = 1)
Wetting current timer
Tri-state command
SGMT
SGT
01_0011
Enable tristate at input: Enable tristate = 1, Input active = 0
(Default = 1)
01_0100
Additionally, there are three specific SPI words to carry out certain functions on the IC.
Table 16. SPI specific instructions
SPI MOSI Word
Function
Command Part of Watchdog Inhibit mode
Acknowledge Safe condition
Wake-up via the SPI
Resulting Behavior
Even with WDI pin > 10 V, IC leaves WD Inhibit mode (requires WD refreshed)
Clears SAFE registers and unasserts SAFE_B pin (after SAFE condition is gone)
Wakes the IC from low-power mode (VDD ON) with specific SPI word
0x5E000000
0x5F000000
0x49000010
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Table 17. Overview individual bits
Type of command
MOSI/
MISO
Control
bits [31-30]
Address [29-24]
address
Bits [23-0]
All 0’s (except when noted)
Register control bits content
Control Bits
MOSI
MISO
MOSI
MISO
00
Read back of “device control bits”
Device Fixed Status (8 bits)
address
Device Fixed Status (12 bits)
01
Write device control bit to address selected by bits
(29-24). MISO return 32-bits status
Normal MISO status registers
Read device flags and wake-up flags, from register
address (bit29-24). MISO return fixed device status
(bit 31-20) + flags from the selected address
(requires a double write)
Read of device flags from a register
address, and sub address LOW (bit 23)
address
MOSI
MISO
10
Device Fixed Status (12 bits)
Flag Registers
Table 18. MISO device status bits description
Flag
Description
Indicates an INT has occurred and INT flags are pending to be read.
INT
WU
Indicates a Wake-up has occurred and Wake-up flags are pending to be read.
Indicates an Reset has occurred and the flags reporting the Reset source are pending to be read.
Indicates a TLIM has occurred and TLIM flags are pending to be read.
The INT, or WU or RST source is a transceiver interface (CAN or LIN).
The INT, or WU or RST source is the VPRE switch mode power supply.
The INT, or WU or RST source is a regulator supply (VDD or VAUX).
The INT, or WU or RST source is from a SAFE condition.
RST
TLIM
TRAN-G
VPRE-G
VREG-G
SAFE_B-G
LIN23-G
LIN01-G
CAN-G
The INT, or WU or RST source is a LIN bus (LIN2 or LIN3).
The INT, or WU or RST source is a LIN bus (LIN0 or LIN1).
The INT, or WU or RST source is CAN interface. CAN local or CAN bus source.
The INT, or WU or RST source is SG interface, flag from SG inputs.
SG-G
Table 19. Internal memory registers A and B, RAM_A and RAM_B
MOSI, bits 23-0
MOSI First Byte [31-24] [b_31
b_30] 00_0xxx
a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
Default state
0
Condition for default
POR
RAM_A
00_0001
Rb2 Rb2 Rb2 Rb2 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1
Rb9 Rb8 Rb7 Rb6 Rb5 Rb4 Rb3 Rb2 Rb1 Rb0
3
2
1
0
9
8
7
6
5
4
3
2
1
0
Default state
0
Condition for default
POR
RAM_B
00_0010
Rb2 Rb2 Rb2 Rb2 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1
Rb9 Rb8 Rb7 Rb6 Rb5 Rb4 Rb3 Rb2 Rb1 Rb0
3
2
1
0
9
8
7
6
5
4
3
2
1
0
Default state
0
Condition for default
POR
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Table 20. Initialization registers - regulator, INIT REG
MOSI bits
[31-24]
[b_31 b_30] 00_0011
MOSI bits 7-0
bit 4
bit 7
bit 6
bit 5
bit 3
bit 2
bit 1
bit 0
00_0011
Default state
VPRE_Disable
0
VDDLrst[1]
0
VDDLrst[0]
0
VDDrstD[1]
1
VDDrstD[0]
0
VAUX5/3 VAUXtracker
Unused
0
0
0
Condition for default
POR/Reset
Table 21. Individual bits (watchdog)
Bit
Description
VPRE_Disable
VPRE is enabled and used by the IC
Disable VPRE internal circuitry (use external source to power VPRE node)
VDDLRST[1] VDDL RST[0] - Select the VDD undervoltage threshold, to activate Reset pin and/or INT
Reset at approximately 0.9 VDD
b7
0
1
b6, b5
00
01
10
11
b4, b3
00
01
10
11
b2
0
.
INT at approximately 0.9 VDD, Reset at approximately 0.7 VDD
Reset at approximately 0.7 VDD
Reset at approximately 0.9 VDD
VDDRSTD[1] VDDRSTD[0] - Select the Reset pin low lev duration, after VDD rises above the VDD undervoltage threshold
1.0 ms
5.0 ms
10 ms [Default]
20 ms
[VAUX5/3]- Select Vauxilary output voltage
VAUX = 3.3 V
VAUX = 5.0 V
1
Tracking Enable
b1
0
VAUX is independent of VDD
VAUX tracks VDD (ignored if VDD and VAUX not set to 5.0 V)
Unused
1
b0
Table 22. Initialization registers - watchdog
MOSI bits 15-8
MOSI bits [31-24] [b_31
b_30] 00_0011
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
WD
SAFE_B[0]
00_0011
WD2INT
0
MCU_OC
0
OC-TIM
0
WD SAFE_B[1]
0
WD_spi[1]
0
WD_spi[0]
0
WD N/Win
0
Default state
0
Condition for default
POR
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Table 23. Individual bits (watchdog)
Bit
Description
WD2INT - Select the maximum time delay between INT occurrence and INT source read SPI command
Function disabled. No constraint between INT occurrence and INT source read.
b15
0
INT source read must occur before the remaining of the current W/D period plus 2 complete W/D periods.
1
MCU_OC, OC-TIM - In Low-power VDDON, select watchdog refresh and VDD current monitoring functionality.VDD_OC_LP threshold
is defined in device electrical parameters (approximately 2.0 mA)
b14, b13
In low-power mode, W/D is not selected
In Low-power VDD ON mode, VDD overcurrent has no effect.
no W/D + 00
no W/D + 01
In Low-power VDD ON mode, VDD overcurrent has no effect.
In Low-power VDD ON mode, VDD current > VDD_OC_LP threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is
selected in Timer register (selection range from 0.1 to 32 ms – 8 total options).
no W/D + 10
no W/D + 11
Unused
In low-power mode W/D is selected
In Low-power VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. W/D refresh must occur by SPI command.
W/D + 00
W/D + 01
In Low-power VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. W/D refresh must occur by SPI command.
In Low-power VDD ON mode, VDD current > VDD_OC_LP threshold for a time < I_mcu_OC is a W/D refresh condition. VDD current >
V
DD_OC_LP threshold for a time > I_mcu_OC is wake-up event. I_mcu_OC time is selected in Timer register (selection range from 0.1
W/D + 10
to 32 ms – 8 total options)
Unused
W/D + 11
WD SAFE_B - Select the activation of the SAFE_B pin low, at first or second consecutive RESET pulse.
SAFE_B pin is set low at the time of the RESET pin low activation
SAFE_B pin is set low at the second consecutive time RESET pulse
SAFE_B pin is set low at the third consecutive time RESET pulse
SAFE_B pin is set low at the fifth consecutive time RESET pulse
WD_spi[1] WD_spi[0] - Select the Watchdog (W/D) Operation
b12, b11
00
01
10
11
b10, b9
00
Simple Watchdog selection: W/D refresh done by a 8 bits or 32 bits SPI
Enhanced 1: Refresh is done using the Random Code, and by a single 32 bits.
Enhanced 2: Refresh is done using the Random Code, and by two 32 bit commands.
Enhanced 4: Refresh is done using the Random Code, and by four 32 bit commands.
WD N/Win - Select the Watchdog (W/D) Window or Timeout operation
Watchdog operation is TIMEOUT, W/D refresh can occur anytime in the period
Watchdog operation is WINDOW, W/D refresh must occur in the open window (second half of period)
01
10
11
b8
0
1
Table 24. Initialization registers - miscellaneous, INIT MISC
MOSI, bits 23-16
bit 20 bit 19
LPM w RND AMUX config INT_B pulse INT_B width INT_B flash
MOSI bits [31-24]
[b_31 b_30] 00_0011
bit 23
bit 22
bit 21
bit 18
bit 17
bit 16
00_0011
Default state
SAFE_B[2]
0
SAFE_B[1]
0
SAFE_B[0]
0
0
0
0
0
0
Condition for default
POR
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Table 25. Individual bits (INIT MISC)
Bit
Description
LPM w RND - Select the functionality to change mode (enter in Low-power) using the device Random Code
b23
Function disable: the Low-power mode can be entered without usage of Random Code
0
Function enabled: the Low-power mode is entered using the Random Code
1
AMUX SPI configured
b22
AMUX is determined by the SPI
0
N/A
1
INT_B pulse - Select INT pin operation: low level pulse or low level
b21
INT_B pin asserts a low level pulse, duration selected by bit [b4]
0
INT_B pin assert a permanent low level (no pulse)
1
INT_B width - Select the INT pulse duration
b20
INT_B pulse duration is typ. 100 μs. Refer to dynamic parameter table for exact value.
0
INT_B pulse duration is typ. 25 μs. Refer to dynamic parameter table for exact value.
1
INT_B flash - Select INT pulse generation at 50% of the Watchdog Period in Flash mode
b19
Function disable
0
Function enable: an INT pulse occurs at 50% of the Watchdog Period when device in Flash mode.
1
b18, b17, b16
0xx
SAFE_B[2], SAFE_B[1], SAFE_B[0] - Set state of Safe operation
Function disable (W/D inhibit mode)
RB3
RB2
RB1
RA
100
101
110
111
Table 26. Specific mode register SPE-MODE
MOSI, bits 7-0
MOSI bits [31-24]
[b_31 b_30] 00_0100
MOSI bits
23-11
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00_0100
Default state
Unused
0
Rnd_C7b
0
Rnd_C6b
0
Rnd_C5b
0
Rnd_C4b
Rnd_C3b
0
Rnd_C2b
0
Rnd_C1b
0
Rnd_C0b
0
Condition for default
POR
Table 27. Specific mode register SPE-MODE
MOSI, bits 10-8
MOSI bits [31-24]
[b_31 b_30] 00_0100
MOSI bits 23-
11
bit 10
bit 9
bit 8
00_0100
Default state
Unused
0
Sel_Mod[2]
0
Sel_Mod[1]
Sel_Mod[0]
0
0
Condition for default
POR
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Table 28. Individual bit description (SPE-MODE)
Bit
Description
Sel_Mod[2] Sel_Mod[1], Sel_Mod[0]- Mode selection: these 3 bits are used to select which mode the device enters upon a SPI
command.
b10, b9, b8
RESET mode
INIT mode
000
001
FLASH mode
RESET SG inputs
N/A
010
011
100 - 111
[Rnd_C7b... Rnd_C0b]- Random Code inverted, these 8 bits are the inverted bits obtained from the SPE-MODE Register read
command.
b7....b0
The SPE MODE register is used for the following operation:
- Set the device in Reset mode, to exercise or test the Reset functions.
- Go to Init mode, using the Secure SPI command.
- Go to Flash mode (in this mode the watchdog timer can be extended up to 32 sec).
- Reset the registers for SG (switch to ground) inputs only.
- Activate the SAFE_B pin by S/W.
These mode (called Special Mode) are accessible via secured SPI command, which consist in two commands:
1. Reading a random code and
2. Write the inverted random code plus mode selection or SAFE_B pin activation:
Return to INIT mode is done as follow (this is done from Normal mode only):
1. Read random code:
MOSI: 0000 0100 0000 0000 0000 0000 0000 0000 [Hex:0x 04 00 00 00]
MISO report 32 bits, random code are bits (7-0)
MISO = xxxx xxxx xxxx xxxx xxxx xxxx R7 R6 R5 R4 R3 R2 R1 R0 (Rx = 8 bits random code)
2. Write INIT mode + random code inverted
MOSI: 0100 0100 0000 0000 0000 0001 Ri7 Ri6 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex:0x 44 00 01 HH] (Rix = random code inverted)
MISO: xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx (don't care)
SAFE_B pin activation: SAFE_B pin can be set low, in INIT and Normal mode, with following commands:
1. Read random code:
MOSI: 0000 0100 0000 0000 0000 0000 0000 0000 [Hex:0x 04 00 00 00]
MISO report 32 bits, random code are bits (7-0)
MISO = xxxx xxxx xxxx xxxx xxxx xxxx R7 R6 R5 R4 R3 R2 R1 R0 (Rx = 8 bits random code)
2. Write INIT mode + random code bits 7:6 not inverted and random code bits 5:0 inverted
MOSI: 0100 0100 0000 0000 0000 0001 R7 R6 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 44 00 01 HH] (Ri7-6 = random code, Ri5-0 = random
code inverted)
MISO: xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx (don't care)
Go to Reset mode is done as follow (this is done from Normal mode only):
1. Read random code:
MOSI: 0000 0100 0000 0000 0000 0000 0000 0000 [Hex:0x 04 00 00 00]
MISO report 32 bits, random code are bits (7-0)
MISO = xxxx xxxx xxxx xxxx xxxx xxxx R7 R6 R5 R4 R3 R2 R1 R0 (Rx = 8 bits random code)
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2. Write Reset mode + random code bits inverted
MOSI: 0100 0100 0000 0000 0000 0000 Ri7 Ri6 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 44 00 00 HH] (RiX = random code inverted)
MISO: xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx (don't care)
Go to Flash mode is done as follow (this is done from Normal mode only):
1. Read random code:
MOSI: 0000 0100 0000 0000 0000 0000 0000 0000 [Hex:0x 04 00 00 00]
MISO report 32 bits, random code are bits (7-0)
MISO = xxxx xxxx xxxx xxxx xxxx xxxx R7 R6 R5 R4 R3 R2 R1 R0 (Rx = 8 bits random code)
2. Write INIT mode + random code bits 7:6 not inverted and random code bits 5:0 inverted
MOSI: 0100 0100 0000 0000 0000 0010 Ri7 Ri6 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 44 00 02 HH] (RiX = random code inverted)
MISO: xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx (don't care)
Reset SG registers is done as follow (this is done from Normal mode only):
1. Read random code:
MOSI: 0000 0100 0000 0000 0000 0000 0000 0000 [Hex:0x 04 00 03 00]
MISO report 32 bits, random code are bits (7-0)
MISO = xxxx xxxx xxxx xxxx xxxx xxxx R7 R6 R5 R4 R3 R2 R1 R0 (Rx = 8 bits random code)
2. Write SG reset mode + random code bits inverted
MOSI: 0100 0100 0000 0000 0000 0011 Ri7 Ri6 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 44 00 03 HH] (RiX = random code inverted)
MISO: xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx (don't care).
Table 29. Watchdog and low-power MCU consumption, TIM_A
MOSI, bits 7-0
MOSI bits [31-24]
[b_31 b_30] 00_0101
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00_0101
Default state
I_mcu[2]
0
I_mcu[1]
0
I_mcu[0]
0
W/D Nor[4]
1
W/D_N[3]
1
W/D_Nor[2] W/D_N[1] W/D_Nor[0]
1
1
0
Condition for default
POR
Table 30. Individual bit description for I_mcu timer
Typical Timing Value (in ms)
b6, b5
b7
00
3 (def)
4
01
6
10
12
16
11
24
32
0
1
8
Table 31. Individual bit description for watchdog period in device normal mode
Typical Timing Value (in ms)
b2, b1, b0
b4, b3
000
2.5
3
001
5
010
10
12
14
16
011
20
24
28
32
100
40
48
56
64
101
80
110
160
192
224
111
320
384
448
512
00
01
10
11
6
96
3.5
4
7
112
128
8
256 (def)
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Table 32. Timer register B, periodic scan and cyclic INT, in device low-power mode, TIM_B
MOSI, bits 15-8
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Cyc-sen[3]
1
Cyc-sen[2]
1
Cyc-sen[1]
0
Cyc-sen[0]
0
Cyc-int[3]
0
Cyc-int[2]
0
Cyc-int[1]
0
Cyc-int[0]
0
Default state
Condition for default
POR
Table 33. Individual bit description for periodic scan
Typical timing value (in ms)
b14, b13, b12
b15
000
3
001
6
010
12
011
24
100
48
64 (def)
101
96
110
111
384
512
0
192
256
1
4
8
16
32
128
Table 34. Individual bit description for periodic interrupt
Typical timing value (in ms)
b10, b9, b8
b11
000
6 (def)
8
001
12
010
011
48
100
96
101
192
258
110
111
768
0
24
32
384
512
1
16
64
128
1024
Table 35. Timer register C, watchdog LP mode and forced wake-up timer, TIM_C
MOSI bits 23-16
bit 23
WD-LP-F[3]
0
bit 22
WD-LP-F[2]
0
bit 21
WD-LP-F[1]
0
bit 20
WD-LP-F[0]
0
bit 19
bit 18
FWU[2]
0
bit 17
FWU[1]
0
bit 16
FWU[0]
0
FWU[3]
Default state
0
Condition for default
POR
Table 36. Individual bit description for watchdog in low-power VDD on mode
Typical timing value (in ms)
b22, b21, b20
b23
000
12 (def)
16
001
24
010
48
011
96
100
192
256
101
384
512
110
111
1536
2048
0
768
1
32
64
128
1024
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FUNCTIONAL DEVICE OPERATION
Table 37. Individual bit description for watchdog in flash mode
Typical timing value (in ms)
b22, b21, b20
b23
000
48 (def)
256
001
96
010
192
011
384
100
768
101
1536
8192
110
3072
16384
111
6144
32768
0
1
512
1024
2048
4096
Table 38. Individual bit description for forced wake-up
Typical timing value (in ms)
b18, b17, b16
b19
000
48 (def)
64
001
96
010
192
258
011
384
512
100
101
1536
2048
110
3072
4096
111
6144
8192
0
1
768
128
1024
Table 39. AMUX
MOSI, bits 7-0
bit 4
MOSI First Byte [31-24] MOSI, bits
[b_31 b_30] 00_0110
23-8
bit 7
bit 6
bit 5
bit 3
MUX_0
bit 2
bit 1
bit 0
00_0110
Default state
Unused
0
MUX_4
0
MUX_3
0
MUX_2
0
MUX_1
0
Unused
0
Unused
0
Unused
0
0
Condition for default
POR
Table 40. Individual bits AMUX
Bits
Description
MUX_4, MUX_3, MUX_2, MUX_1, MUX_0 - Selection of the device external input signal or internal signal to be measured at AMUX
pin
b8 b7 b6 b5 b4 b3
All functions disable. AMUX pin high-impedance.
Voltage at SG0
0 00000
0 00001
0 00101
0 00110
0 00111
0 01000
0 01011
Voltage at SG1
Voltage at SG2
Voltage at SG3
Voltage at SG4
Voltage at SG5
Voltage at VBATSNS pin. Refer to electrical table for attenuation ratio (approximately 6 for VDD = 5.0 V, approximately 9 for
VDD = 3.3 V) [Default].
0 10010
0 10011
Device internal temperature sensor voltage
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FUNCTIONAL DEVICE OPERATION
Table 41. Watchdog refresh register, W/D
MOSI bits 7-0
bit 3
MOSI bits [31-24]
[b_31 b_30] 00_0111
MOSI bits
23-8
bit 7
bit 6
bit 5
bit 4
bit 2
bit 1
bit 0
00_0111
Default state
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Condition for default
POR
Table 42. INT_B register(25)
MOSI bits 7-0
bit 4
MOSI bits [31-24]
[b_31 b_30] 00_1000
MOSI bits
23-9
bit8
bit 7
bit 6
bit 5
LIN1 fail
0
bit 3
bit 2
bit 1
bit 0
CAN
failure
00_1000
Unused
MCU req LIN3 fail LIN2fail
SAFE_B
0
LIN0 fail
Vmon
0
Default state
0
0
0
0
0
0
Condition for default
POR
Notes
25. The first time the device is set in Normal mode, the CAN is in Sleep wake-up enable (10). The next time device is set in Normal mode, the CAN
state is controlled by the bit7 and bit6 states.
Table 43. Individual bit description (INT_B register)
Bits
Description
MCU req- Control bit to request an INT. INT occurs once when the bit is enabled.
b8
0
INT disable
INT enable
LIN3 Fail
1
b7
0
INT disable
INT enable
LIN2 Fail
1
b6
0
INT disable
INT enable
LIN1 Fail
1
b5
0
INT disable
INT enable
LIN0 Fail
1
b4
0
NT disable
INT enable
SAFE_B- description to be done
INT disable
INT enable
1
b3
0
1
b2
0
INT disable
INT enable
1
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FUNCTIONAL DEVICE OPERATION
Table 43. Individual bit description (INT_B register) (continued)
Bits
Description
CAN failure- control bit for CAN failure INT (CANH/L to GND, VDD or VBATP, CAN overcurrent, Driver Over Temp, TX-PD, RX-PR,
RX2HIGH, and CANBUS Dominate clamp)
b1
INT disable
INT enable
0
1
Vmon- enable interruption by voltage monitoring of one of the voltage regulator: VAUX, CAN5V, VDD(IDD overcurrent, overvoltage,
undervoltage), VSUV, VSOV, VBATP_BATFAIL, CAN5V low or thermal shutdown, VAUXlow or VAUXovercurrent
b0
INT disable
INT enable
0
1
Table 44. MODE register, moDE
MOSI bits 7-0
bit 3
MOSI bits [31-24]
[b_31 b_30] 00_1001
MOSIbits
23-8
bit 7
bit 6
bit 5
bit 4
bit 2
bit 1
bit 0
00_1001
Unused
N/A
Mode[4]
N/A
Mode[3]
N/A
Mode[2]
N/A
Mode[1]
N/A
Mode[0]
N/A
Rnd_b[2]
N/A
Rnd_b[1]
N/A
Rnd_b[0]
N/A
Default state
Table 45. Individual bit description for low-power VDD off selection and operation mode
Low-power VDD OFF Selection and Function
b7, b6, b5, b4, b3
0 1100
FWU
OFF
OFF
ON
Periodic Sense
OFF
ON
0 1101
0 1110
OFF
ON
0 1111
ON
Table 46. Individual bit description for low-power VDD on selection and operation mode
Low-power VDD on selection and function
b7, b6, b5, b4, b3
FWU
Periodic Sense
Periodic INT
Watchdog
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1001
1 1010
1 1011
1 1100
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
ON
ON
OFF
OFF
ON
OFF
ON
ON
ON
OFF
ON
ON
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
ON
ON
OFF
ON
ON
ON
ON
OFF
OFF
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FUNCTIONAL DEVICE OPERATION
Table 46. Individual bit description for low-power VDD on selection and operation mode (continued)
Low-power VDD on selection and function
b7, b6, b5, b4, b3
FWU
Periodic Sense
Periodic INT
Watchdog
1 1101
1 1110
1 1111
ON
ON
ON
ON
ON
ON
OFF
ON
ON
OFF
ON
ON
Table 47. REGULATOR register, REG
MOSI bits 7-0
MOSI bits [31-24]
[b_31 b_30] 00_1010
MOSI bits
23-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00_1010
Default state
Unused
0
VAUX[1]
0
VAUX[0]
0
Unused
N/A
CAN5V[1]
0
CAN5V[0]
0
Unused
N/A
Unused
N/A
VDDoff en
N/A
Condition for default
POR
POR
Table 48. Individual bit description (REG)
Bits
Description
VAUX[1], VAUX[0]- Vauxilary regulator control
Regulator OFF
b7 b6
00
Regulator ON. Undervoltage (UV) and overcurrent (OC) and overvoltage (OV) monitoring flags not reported. VAUX disable in case
OC or UV detected after 1.0 ms blanking time (monitoring of flags not reported).
01
10
11
Regulator ON. Undervoltage (UV) and overcurrent (OC) and overvoltage (OV) monitoring flags active. VAUX disable in case OC or
UV detected after 1.0 ms blanking time. (monitoring of flags not reported).
Regulator ON. Undervoltage (UV) and overcurrent (OC) and overvoltage (OV) monitoring flags active. VAUX disable in case OC or
UV detected after 25 μs blanking time.
CAN5V[1], CAN5V[0]- CAN5V regulator control
b4 b3
00
Regulator OFF
Regulator ON. Thermal protection active. Undervoltage (UV) and overcurrent (OC) monitoring flags not reported.
Regulator ON. Thermal protection active. Undervoltage (UV) and overcurrent (OC) monitoring flags active.
01
10
Regulator ON. Thermal protection active. Undervoltage (UV) and overcurrent (OC) monitoring flags active. CAN5V disable in case
OC or UV detected after 25 μs blanking time.
11
VDDoff en - Control bit to allow transition into Low-power VDDOFF mode (to prevent VDD turn OFF)
Disable Usage of Low-power VDD OFF mode
b0
0
Enable Usage of Low-power VDD OFF mode
1
Table 49. CAN registers, CAN(26)
MOSI bits [31-24]
MOSI bits 7-0
bit 4
[b_31 b_30] 00_1011
bit 7
bit 6
bit 5
bit 3
bit 2
bit 1
bit 0
CAN
mod[1]
CAN
mod[0]
00_1011
Unused
0
Unused
0
Unused
CMFB Enable
0
Wake-up 1/3
0
CAN int
Default state
0
1
0
0
Condition for default
POR
note
POR
Note:
26. The first time the device is set in Normal mode, the CAN is in Sleep wake-up enable (10). The next time the device is set in Normal mode, the
CAN state is controlled by the bit 2 and bit 1 states.
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FUNCTIONAL DEVICE OPERATION
Table 50. Individual bit description (CAN)
Bits
Description
CMFB enable for CAN
b4
0
Common Mode Feed Back circuit is turned off
Common Mode Feed Back circuit is turned on
Wake-up 1/3- Selection of CAN wake-up mechanism
Three dominant pulses wake-up mechanism
Single dominant pulse wake-up mechanism
1
b3
0
1
CAN mod[1], CAN mod[0]- CAN interface mode control, wake-up enable/disable
CAN interface in sleep mode, CAN wake-up disable.
b2 b1
00
01
CAN interface in receive only mode, CAN driver disable.
CAN interface is in sleep mode, CAN wake-up enabled. In device low-power mode, CAN wake-up is reported by device wake-up. In
device normal mode, CAN wake-up reported by INT and Flags generated.
10
CAN interface in transmit and receive mode
11
b0
0
CAN INT - Select the CAN failure detection reporting
Select INT generation when a bus failure is fully identified and decoded (i.e. after five dominant pulses on TxCAN)
Select INT generation as soon as a bus failure is detected, event if not fully identified.
1
Table 51. LIN 0-1 register
MOSI bits 9-0
MOSI bits [31-24]
MOSIbits
[b_31 b_30] 00_1100
23-10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LIN1
J260
2
LIN1
mode[1]
LIN1 Slew LIN1 Slew
LIN0
mode[1] mode[0]
LIN0
LIN0 Slew LIN0 Slew
LIN0
J2602
00_1100
Unused
0
LIN1mode
[0]
rate[1]
0
rate[0]
0
rate[1]
0
rate[0]
0
Default state
1
0
0
1
0
0
Condition for default
POR
Table 52. Individual bit description (LIN0-1)
Bits
Description
LIN1 mode [1], LIN1 mode [0]- LIN 1 interface mode control, wake-up enable/disable
LIN1 disable, wake-up capability disable
not used
b9 b8
00
01
LIN1 disable, wake-up capability enable
LIN1 Transmit Receive mode
10
11
Slew rate[1], Slew rate[0] LIN 1 slew rate selection
Slew rate for 20 kbit/s baud rate
Slew rate for 10 kbit/s baud rate
Slew rate for fast baud rate
b7 b6
00
01
10
Slew rate for fast baud rate
11
LIN1 J2602
b5
LIN1 remain recessive
0
LIN1 operates below 6 V
1
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FUNCTIONAL DEVICE OPERATION
Table 52. Individual bit description (LIN0-1) (continued)
Bits
Description
LIN0 mode [1], LIN0 mode [0]- LIN 0 interface mode control, wake-up enable/disable
LIN0 disable, wake-up capability disable
not used
b4 b3
00
01
LIN0 disable, wake-up capability enable
LIN0 Transmit Receive mode
10
11
Slew rate[1], Slew rate[0] LIN0 slew rate selection
Slew rate for 20 kbit/s baud rate
Slew rate for 10 kbit/s baud rate
Slew rate for fast baud rate
b2 b1
00
01
10
Slew rate for fast baud rate
11
LIN0 J2602
b0
LIN0 remain recessive
0
LIN0 operate below 6.0 V
1
Table 53. LIN 2-3 register
MOSI bits [31-24]
MOSI
bits 23-
MOSI bits 9-0
[b_31 b_30] 00_1101
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
10
LIN3
Slew
rate[1]
LIN2
Slew
rate[0]
LIN3
mode[1] mode[0]
LIN3
LIN3 Slew
rate[0]
LIN2
mode[1]
LIN2
mode[0]
LIN2Slew
rate[1]
LIN2
J2602
00_1101
Unused
0
LIN3 J2602
Default state
1
0
0
0
0
1
0
0
0
0
Condition for default
POR
Table 54. Individual bit description (LIN2-3)
Bits
Description
LIN3 mode [1], LIN3 mode [0]- LIN 3 interface mode control, wake-up enable/disable
LIN3 disable, wake-up capability disable
Not used
b9 b8
00
01
LIN3 disable, wake-up capability enable
LIN3 Transmit Receive mode
10
11
Slew rate[1], Slew rate[0] LIN 3 slew rate selection
Slew rate for 20 kbit/s baud rate
b7 b6
00
Slew rate for 10 kbit/s baud rate
01
Slew rate for fast baud rate
10
Slew rate for fast baud rate
11
LIN3 J2602
b5
LIN3 remain recessive
0
LIN3 operate below 6.0 V
1
LIN2 mode [1], LIN2 mode [0]- LIN2 interface mode control, wake-up enable/disable
LIN2 disable, wake-up capability disable
b4 b3
00
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FUNCTIONAL DEVICE OPERATION
Table 54. Individual bit description (LIN2-3) (continued)
Bits
Description
Not used
01
10
11
b2 b1
00
01
10
11
b5
0
LIN2 disable, wake-up capability enable
LIN2 Transmit Receive mode
Slew rate[1], Slew rate[0] LIN 2 slew rate selection
Slew rate for 20 kbit/s baud rate
Slew rate for 10 kbit/s baud rate
Slew rate for fast baud rate
Slew rate for fast baud rate
LIN2 J2602
LIN2 remain recessive
LIN2 operate below 6.0 V
1
Table 55. SG wake-up enable
MOSI bits [31-24]
MOSI bits 23-0
[b_31 b_30] 00_1110
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 23-17
bit 15-11
SG5
SG4
SG3
SG2
1
SG1
SG0
00_ 1110
Default state
Unused
0
Unused
1
Unused Unused
Unused Unused Unused
Condition for default
POR/Reset command
Table 56. SG5-0 fast scan enable
MOSI bits [31-24]
MOSI bits 23-0
[b_31 b_30] 00_1111
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 23-17
bit 15-0
SG5
SG4
SG3
SG2
0
SG1
SG0
00_ 1111
Default state
Unused
0
Unused
0
Unused Unused
Unused Unused Unused
Condition for default
POR/Reset command
Table 57. Individual bit description (SG5-0 fast scan enable)
Bits
Description
SG5-0 (Default = 0)
Use normal wake-up timing as defined in sleep state command.
Enables fast wake-up at 1.0 ms polling independent of normal wake-up selected in sleep state command.
b10,b7-4,b0
0
1
Table 58. SG wake-up delay enable
MOSI bits 23-0
MOSI bits [31-24]
[b_31 b_30] 01_0000
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 23-17
bit 15-11
SG5
SG4
SG3
SG2
0
SG1
SG0
01_ 0000
Default state
Unused
0
Unused
0
Unused Unused
Unused Unused Unused
Condition for default
POR/Reset command
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FUNCTIONAL DEVICE OPERATION
Table 59. Individual bit description (wake-up delay enable)
Bits
Description
Controls SG5 – SG0 to Enable/Disable Wake-up delay during sleep mode. (Default = 0)
b10,b7-4,b0
Disables wake-up delay for SGn from sleep mode (Device does not wake up with change of state on SGn).
Enable wake-up delay for SGn from sleep mode (Device wakes up with change of state on SGn)
0
1
Table 60. Wetting current register 0
MOSI bits [31-24]
MOSI bits 23-0
bits 14-12
[b_31 b_30] 01_0001
bits 23-21
bit 20-18
bits 17-15
bits 11-9
bits 8-6
bit 5-3
bit 2-0
01_ 0001
Default state
SG4
110
SG3
110
SG2
110
SG1
110
Unused
Unused
Unused
Unused
Unused
Unused
SG0
110
Condition for default
POR/Reset command
Table 61. Individual bit description (wetting current register 0)
Bits
Description
Bit pattern for Wetting current level for input pins (Default = 110)
Sets the Wetting current Off
b[cba]
000
Sets the Wetting current level to 6.0 mA
001
Sets the Wetting current level to 8.0 mA
010
Sets the Wetting current level to 10 mA
011
Sets the Wetting current level to 12 mA
100
Sets the Wetting current level to 14 mA
101
Sets the Wetting current level to 16 mA
110
Sets the Wetting current level to 20 mA
111
Controls SG4 Wetting current setting. (Default = 110)
Controls SG3 Wetting current setting. (Default = 110)
Controls SG2 Wetting current setting. (Default = 110)
Controls SG1 Wetting current setting. (Default = 110)
Controls SG0 Wetting current setting. (Default = 110)
b23-21
b20-18
b17-15
b14-12
b2-0
Table 62. Wetting current register 1
MOSI bits [31-24]
MOSI bits 23-0
bits 14-12
[b_31 b_30] 01_0010
bits 23-21
bit 20-18
bits 17-15
bits 11-9
bits 8-6
bit 5-3
bit 2-0
01_ 0010
Default state
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
SG5
110
Unused
Unused
Unused
Unused
Condition for default
POR/Reset command
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FUNCTIONAL DEVICE OPERATION
Table 63. Individual bit description (wetting current register 1)
Bits
Description
Bit pattern for Wetting current level for input pins (Default = 110)
Sets the Wetting current to Off
b[cba]
000
001
010
011
100
101
110
111
b8-6
Sets the Wetting current level to 6.0 mA
Sets the Wetting current level to 8.0 mA
Sets the Wetting current level to 10 mA
Sets the Wetting current level to 12 mA
Sets the Wetting current level to 14 mA
Sets the Wetting current level to 16 mA
Sets the Wetting current level to 20 mA
Controls SG5 Wetting current setting. (Default = 110)
Table 64. SG wetting current timer enable
MOSI bits 23-0
MOSI bits [31-24]
[b_31 b_30] 01_0011
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 23-17
bit 15-11
SG5
SG4
SG3
SG2
1
SG1
SG0
01_ 0011
Default state
Unused
0
Unused
0
Unused Unused
Unused Unused Unused
Condition for default
POR/Reset command
Table 65. Individual bit description (wetting current timer enable)
Bits
Description
Controls SG5-0 Wetting current timer enable. (Default = 1). This enables a 20 ms (nominal) timer turns off the Wetting
current
b10,b7-b4,b0
Disables timer and results in the Wetting current to run continuously
Enables timer to turn off Wetting current after 20 ms (nominal)
0
1
Table 66. SG tristate
MOSI bits 23-0
MOSI bits [31-24]
[b_31 b_30] 01_0100
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 23-17
bit 15-11
SG5
SG4
SG3
SG2
1
SG1
SG0
01_ 0100
Default state
Unused
0
Unused
0
Unused Unused
Unused Unused Unused
Condition for default
POR/Reset command
Table 67. Individual bit description (Tristate)
Bits
Description
Set SG5-0 to tri-state (Default = 1)
Sets input to active mode.
Sets input to tristate (Hi Z) mode.
b10,b7-b4,b0
0
1
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FUNCTIONAL DEVICE OPERATION
4.3.3
Device flags registers
Table 68. Device flags - MISC
MOSI
MISO bits 8-0
MOSI bits [31-24]
bits 23-
10 00_1001
10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
WD INT at
Unused 50% Flash
mode
FSM
State
(bit4)
FSM
State
(bit3)
FSM
State
(bit1)
FSM
State
(bit0)
SAFE_B
Activated
FSM State
(bit2)
WDI
WDI pin
WDI pin
10 00_1001
mode status (bit 1) status (bit 0)
Default state
0
0
0
0
0
0
1
0
0
0
0
Condition for default
POR
Table 69. Individual bit description - MISC
Bits
Description
Unused
b23-10
WD INT at 50% Flash mode
Description
b9
Watchdog interrupt pulse generation at 50% of the watchdog period in Flash mode
Set: Time elapsed to 50% of watchdog timer in Flash mode. Reset: Flag read (SPI)
Note: Flag resets only after exiting Flash mode and then SPI flag read.
Set/Reset condition
SAFE_B activated
Description
SAFE_B pin activated for any reason
b8
Set/Reset condition
FSM State (Bit 4,3,2,1,0)
Description
Set: Safe mode activated. Reset: POR or SPI read
b7, b6, b5,
b4, b3
Determine what state the device is in (see Table 70 for description)
Set/Reset condition
WDI Mode
Set: Determined by state of IC. Reset: POR
Description
In watchdog inhibit mode
b2
Set/Reset condition
WDI pin status (BIT1,0)
Description
Set: Voltage at WDI greater then threshold. Reset: Voltage lowered below threshold or POR
WDI pin in Safe mode A [00], B1 [01], B2 [10], B3 [11]
Set: WDI set during INIT Reset. Reset: POR.
b1, b0
Set/Reset condition
Table 70. FSM state
Bits
Description
State
b7, b6, b5, b4, b3
00000
INIT
Normal Request
Normal
Flash
00010
00011
00001
Low-power VDD ON – xxx = SPI Mode command bits 6:3 (forced wake-up, periodic interrupt, watchdog)
10000
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FUNCTIONAL DEVICE OPERATION
Table 71. Device flags - regulators
MOSI
MISO bits 7-0
bit 4 bit 3
CAN5V CAN5Voverc VBATP
MOSI bits [31-24]
bits 23-
10 00_1010
20
bit 7
bit 6
bit 5
bit 2
bit 1
bit 0
CAN5V
Thermal
shutdown
VAUX
Undervoltage
VAUX
overcurrent
VBATP
VBATP
10 00_1010
Unused
0
UV
urrent
batfail
Undervoltage Overvoltage
Default state
0
0
0
0
0
0
0
0
Condition for default
POR
Table 72. Device flags - regulators
MOSI
MOSI bits [31-24]
bits 23-
MISO bits 15-8
10 00_1010
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
20
IDD
Overcurrent
Boosted Low-power
IDD
VDD
VDD
VPRE
Thermal
Shutdown
VDD
Overvoltage
VAUX
Overvoltage
VPRE
Overcurrent
NORMAL
mode
10 00_1010
Unused
0
Undervolta Undervoltage>
ge
0
100 ms
0
V
DD On mode
Default state
0
0
0
0
0
0
Condition for default
POR
Table 73. Device flags - regulators
MISO bits 19-16
bit 17
MOSI bits [31-24]
10 00_1010
MOSI bits
23-20
bit 19
bit 18
bit 16
10 00_1010
Default state
Unused
0
VPRE IPFF
0
VPRE Overcurrent
0
VPRE Overvoltage
VPRE Undervoltage
0
0
Condition for default
POR
Table 74. Individual bit description - regulators
Bits
Description
Unused
b23-8
VPRE IPFF
Description
Report VPRE IPFF
b19
Set/Reset condition
VPRE Overcurrent
Description
Set: VPRE IPFF. Reset: VPRE out of IPFF and flag read (SPI)
Reports current out of VPRE is higher than the IPRE-OC threshold.
b18
b17
b16
Set/Reset condition
VPRE Overvoltage
Description
Set: current above threshold for t > 100 μs typ. Reset; current below threshold and flag read (SPI)
Reports when VPRE was above overvoltage threshold
Set/Reset condition
VPRE Undervoltage
Description
Set: VPRE was above OV threshold. Reset: VPRE below OV and flag read (SPI)
Reports when VPRE is below undervoltage threshold
Set/Reset condition
Set: VPRE below threshold for t > 100 μs typ. Reset: VPRE above threshold and flag read (SPI)
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Table 74. Individual bit description - regulators (continued)
Bits
Description
VPRE Thermal Shutdown
Description
Reports the VPRE has reached overtemperature threshold, and was turned off.
Set: VPRE OFF due to thermal condition. Reset: VPRE recover and flag read (SPI)
b15
b14
Set/Reset condition
VPRE_Boosted
Description
Reports VPRE boost circuit activated
Set/Reset condition
Set: VPRE boost activated. Reset: VPRE out of boost mode and flag read (SPI)
IDD Overcurrent Low-power VDD
On mode
Reports current out of VDD pin is higher than the IDD-OC threshold LP, while device is in Low-power VDD
ON mode.
b13
Description
Set/Reset condition
IDD Overcurrent NORMAL mode
Description
Set: current above threshold for t > 100 μs typ. Reset; current below threshold and flag read (SPI)
Reports current out of VDD pin is higher than IDD-OC threshold, while device is in Normal mode.
b12
b11
Set/Reset condition
VDD Overvoltage
Description
Set: current above threshold for t > 100 μs typ. Reset; current below threshold and flag read (SPI)
Reports VDD pin is higher than the typ VDD + 0.6 V threshold (27)
Set/Reset condition
VDD low interrupt
Set: VDD above threshold for t >100 μs typ. Reset: VDD below threshold and flag read (SPI)
Reports VDD output voltage is lower than the VDD_UV threshold and causing an Interrupt, based on the
VDDLRST[1:0] bits set in the INIT register. This flag only sets if the setup in INIT is set to cause an Interrupt
on an undervoltage.
Description
b10
Set/Reset condition
VDD low >100 ms
Description
Set: VDD below threshold for t > 100 μs typ. Reset: VDD above threshold and flag read (SPI)
Reports VDD pin is lower than the VDDUV threshold for a time longer than 100 ms (27)
Set: VDD below threshold for t > 100 ms typ. Reset: VDD above threshold and flag read (SPI)
b9
b8
Set/Reset condition
VAUX Overvoltage
Description
Reports VAUX pin is higher than the typ VAUX + 0.6 V threshold.
Set/Reset condition
VAUX Under voltage
Set: VAUX above threshold for t > 100 μs typ. Reset: VAUX below threshold and flag read (SPI)
Reports VAUX regulator output voltage is lower than the VAUX_UV threshold. The VAUX undervoltage flag
typically occurs in conjunction with the VAUX overcurrent flag, due to the functional cause.
Description
b7
Set/Reset condition
VAUX_OVERCURRENT
Description
Set: VAUX below threshold for t > 100 μs typ. Reset: VAUX above threshold and flag read (SPI)
Report current out of VAUX regulator is above VAUX_OC threshold.
b6
b5
b4
Set/Reset condition
CAN5V Thermal shutdown
Description
Set: Current above threshold for t > 100 μs. Reset: Current below threshold and flag read by SPI.
Report the CAN5V regulator has reached overtemperature threshold.
Set/Reset condition
CAN5V UV
Set: CAN5V thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
Description
Reports CAN5V regulator output voltage is lower than the CAN5V UV threshold.
Set/Reset condition
Set: CAN5V below CAN5V UV for t > 100 μs typ. Reset: CAN5V > threshold and flag read (SPI)
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Table 74. Individual bit description - regulators (continued)
Bits
Description
CAN5V overcurrent
Description
Report the CAN driver output current is above threshold.
b3
Set: CAN5V current above threshold for t > 100 μs. Reset: CAN5V current below threshold and flag read
(SPI)
Set/Reset condition
VBATP batfail
Description
Report the device voltage at VBATP pin was below BATFAIL threshold.
b2
b1
Set/Reset condition
VBATP_underVOLTAGE
Description
Set: VBATP below BATFAIL. Reset: VBATP above threshold, and flag read (SPI)
Reports VBATP pin is lower than the VBATP low resoled.
Set/Reset condition
VBATP Overvoltage
Description
Set: VBATP below threshold for t > 100 μs typ. Reset: VBATP above threshold and flag read (SPI)
Report VBATP was above overvoltage threshold
b0
Set/Reset condition
Set: VBATP was above OV threshold. Reset: VBATP below OV and flag read (SPI)
Notes
27. When a VDD overvoltage condition occurs, the flag register for VDD undervoltage > 100 ms is also set. This was done to logically enable a SAFE
condition when the over voltage occurs.
Table 75. Device flags – CAN
MOSI
bits 22-
17
MISO bits 7-0
MOSI bits [31-24] MOSI bit 23
10 00_1011
Select bit
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CAN
wake-up
CAN
Overtemp
Bus Dom
clamp
CAN
Overcurrent
10 00_1011
0
Unused
0
-
RxD low
RxD high
0
TxD dom
0
Default state
0
0
0
0
0
0
Condition for default
POR
Table 76. Device flags – CAN
MISO bits 7-0
MOSI bits [31-24] MOSI bit 23 MOSI bits
10 00_1011
Select bit
22-16
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
CANL to
VBAT
CANL to
GND
CANH to
VBAT
CANH to
GND
10 00_1011
0
Unused
0
CAN_UF
0
CAN_F
0
Unused
Unused
0
Default state
0
0
0
0
0
Condition for default
POR
Table 77. Individual bit description – CAN
Bits
Description
CAN_UF
Description
Report the CAN failure detection has not yet identified the bus failure
b15
b14
Set/Reset condition
CAN_F
Set: bus failure pre detection. Reset: CAN bus failure recovered and flag read
Description
Report the CAN failure detection has identified the bus failure
Set/Reset condition
Set: bus failure complete detetction.Reset: CAN bus failure recovered and flag read
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Table 77. Individual bit description – CAN (continued)
Bits
Description
CANL to VBAT
Description
Report CAN L short to VBAT failure
b13
b11
b10
b8
Set/Reset condition
CANL to GND
Description
Set: failure detected. Reset failure recovered and flag read (SPI)
Report CAN L short to GND failure
Set/Reset condition
CANH to VBAT
Description
Set: failure detected. Reset failure recovered and flag read (SPI)
Report CAN H short to VBAT failure
Set/Reset condition
CANH to GND
Description
Set: failure detected. Reset failure recovered and flag read (SPI)
Reports CAN H short to VBATP failure
Set/Reset condition
CAN wake-up
Description
Set: failure detected. Reset failure recovered and flag read (SPI)
Reports the wake-up source is CAN
b7
Set/Reset condition
CAN Overtemp
Description
Set: after CAN wake detected. Reset: Flag read (SPI)
Reports the CAN interface has reach overtemperature threshold.
b5
Set/Reset condition
RxD low
Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
Description
Reports the Rx pin is shorted to GND.
b4
Set/Reset condition
RxD high
Set: Rx low failure detected. Reset: failure recovered and flag read (SPI)
Description
Reports the Rx pin is shorted to recessive voltage.
b3
Set/Reset condition
TxD dom
Set: Rx high failure detected. Reset: failure recovered and flag read (SPI)
Description
Reports the Tx pin is shorted to GND
b2
Set/Reset condition
Bus Dom clamp
Description
Set: Tx low failure detected. Reset: failure recovered and flag read (SPI)
Reports the CAN bus is dominant for a time longer than tDOM
b1
Set/Reset condition
CAN Overcurrent
Description
Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
Reports the CAN current is above CAN overcurrent threshold.
b0
Set/Reset condition
Set: CAN current above threshold. Reset: current below threshold and flag read (SPI)
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Table 78. Device flags – interrupt
MOSI bits [31-24] MOSIbits
MISO bits 7-0
bit 3
10 00_1000
23-16
bit 7
bit 6
bit 5
bit 4
bit 2
bit 1
bit 0
SAFE SPI
resistor
mismatch
Reset
request
RESET Low <
100 ms
VPRE thermal
warning
10 00_1000
Unused INT request RST high
Unused Unused
Default state
0
0
0
0
0
0
0
0
0
Condition for default
POR
Table 79. Device flags – interrupt
MOSI bits [31-24] MOSIbits
MISO bits 15-8
10 00_1000
23-16
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
INT service
Timeout
VDD low
RST
RST low >
100 ms
multiple
Resets
W/D refresh
failure
10 00_1000
Unused
0
FWU
0
SPI Wake-up Unused
Default state
0
0
0
0
0
0
0
Condition for default
POR
Table 80. Individual bit description – interrupt
Bits
Description
INT service Timeout
Reports the INT timeout error detected. An interrupt occurrence stays asserted for more than three watchdog
periods without ever being cleared.
Description
b15
Set/Reset condition
FWU
Set: INT service timeout expired and WD2INT set. Reset: flag read and original INT cleared.
Description
Reports the wake-up source is Forced Wake-up
b14
b13
Set/Reset condition
SPI Wake-up
Description
Set: after Forced Wake-up detected. Reset: Flag read (SPI)
Reports the wake-up source is SPI command, in Low-power VDD on.
Set: after SPI Wake-up detected. Reset: Flag read (SPI)
Set/Reset condition
VDD low RST
Reports VDD is below the VDD undervoltage threshold and causes a RESET, based on the VDDLRST [1:0] bits
set in the INIT register.
Description
b11
Set/Reset condition
RST low > 100ms
Description
Set: VDD below threshold. Reset: flag read (SPI)
Reports the Reset pin has detected a low level, longer than 100 ms (Reset permanent low)
Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI)
b10
b9
Set/Reset condition
Multiple Resets
Description
Reports the more than 8 consecutive reset pulses occurred, due to missing or wrong W/D refresh.
Set: after detection of multiple reset pulses. Reset: flag read (SPI)
Set/Reset condition
W/D refresh failure
Description
Reports a wrong or missing W/D failure occurred
Set: Failure detected. Reset: flag read (SPI)
b8
Set/Reset condition
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Table 80. Individual bit description – interrupt (continued)
Bits
Description
INT request
Description
Reports the INT source is an INT request from a SPI command.
Set: INT occurred. Reset: flag read (SPI)
b7
b6
b5
b2
Set/Reset condition
RST high
Description
Reports the RST_B pin is shorted to high voltage.
Set: RST failure detection. Reset: flag read.
Set/Reset condition
Reset Request
Description
Reports the RST source is an request from a SPI command (go to RST mode).
Set: After reset occurred due to SPI request. Reset: flag read (SPI)
Set/Reset condition
RESET Low < 100 ms
Description
Reports the Reset pin has detected a low level, shorter than 100 ms
Set/Reset condition
Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI)
SAFE SPI resistor
mismatch
b1
b0
Description
Reports the SPI word setting the state of SAFE (A, B1, B2, B3) does not match the resistor value set at startup
Set: after SPI command to set SAFE mode and if it does not match. Reset: POR or matching SPI word sent.
Set/Reset condition
VPRE thermal warning
Description
Reports the VPRE thermal warning temperature has been reached
Set/Reset condition
Set: after VPRE thermal warning: Reset Temperature falls below thermal warning limit and SPI read.
Table 81. Device flags – LIN01
MOSI bits [31-24] MOSI bits
MISO bits 7-0
10 00_1100
23-16
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LIN0 wake-
up
LIN 0
Overtemp
LIN0 bus dom
clamp
10 00_1100
Unused
0
Unused
0
Unused
0
RxD0 low
0
RxD0 high
0
TxD0 dom
0
Default state
0
0
0
Condition for default
POR
Table 82. Device flags – LIN01
MISO bits 7-0
MOSI bits [31-24]
10 00_1100
MOSI bits
23-16
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
LIN
1Overtemp
LIN1 bus dom
clamp
10 00_1100
Unused
0
Unused LIN1wake-up
Unused
0
RxD1 low
0
RxD1 high TxD1 dom
Default state
0
0
0
0
0
0
Condition for default
POR
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Table 83. Individual bit description – LIN01
Bits
Description
LIN1 wake-up
Description
Reports the wake-up source is LIN1
b14
b12
b11
b10
b9
Set/Reset condition
LIN 1 Overtemp
Description
Set: after CAN wake detected. Reset: Flag read (SPI)
Reports the LIN1 interface has reach overtemperature threshold.
Set/Reset condition
RxD1 low
Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
Description
Reports the RxDL pin is shorted to GND.
Set/Reset condition
RxD1 high
Set: Rx low failure detected. Reset: failure recovered and flag read (SPI)
Description
Reports the RxDL pin is shorted to recessive voltage.
Set/Reset condition
TxD1 dom
Set: Rx high failure detected. Reset: failure recovered and flag read (SPI)
Description
Reports the TxDL pin is shorted to GND.
Set/Reset condition
LIN1 busdom clamp
Description
Set: Tx low failure detected. Reset: failure recovered and flag read (SPI)
Reports the LIN1 bus is dominant for a time longer than t
DOM
b8
Set/Reset condition
LIN0 wake-up
Description
Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
Reports the wake-up source is LIN0
b6
Set/Reset condition
LIN 0 Overtemp
Description
Set: after CAN wake detected. Reset: Flag read (SPI)
Reports the LIN0 interface has reach overtemperature threshold.
b4
Set/Reset condition
RxD0 low
Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
Description
Reports the RxDL pin is shorted to GND.
b3
Set/Reset condition
RxD0 high
Set: Rx low failure detected. Reset: failure recovered and flag read (SPI)
Description
Reports the RxDL pin is shorted to recessive voltage.
b2
Set/Reset condition
TxD0 dom
Set: Rx high failure detected. Reset: failure recovered and flag read (SPI)
Description
Reports the TxDL pin is shorted to GND.
b1
Set/Reset condition
LIN0 busdom clamp
Description
Set: Tx low failure detected. Reset: failure recovered and flag read (SPI)
Reports the LIN0 bus is dominant for a time longer than tDOM
b0
Set/Reset condition
Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
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Table 84. Device flags – LIN23
MISO bits 7-0
MOSI bits [31-24]
10 00_1101
MOSI bits
23-16
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LIN2 wake-
up
LIN 2
Overtemp
LIN2 busdom
clamp
10 00_1101
Unused
0
Unused
0
Unused
0
RxD2 low
0
RxD2 high TxD2 dom
Default state
0
0
0
0
0
Condition for default
POR
Table 85. Device flags – LIN23
MISO bits 7-0
MOSI bits [31-24]
10 00_1101
MOSI bits
23-16
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
LIN3 wake-
up
LIN 3
Overtemp
LIN3 busdom
clamp
10 00_1101
Unused
0
Unused
0
Unused
0
RxD3 low
0
RxD3 high TxD3 dom
Default state
0
0
0
0
0
Condition for default
POR
Table 86. Individual bit description – LIN23
Bits
Description
LIN3 wake-up
Description
Reports the wake-up source is LIN3
b14
b12
b11
b10
b9
Set/Reset condition
LIN 3 Overtemp
Description
Set: after CAN wake detected. Reset: Flag read (SPI)
Reports the LIN3 interface has reach overtemperature threshold.
Set/Reset condition
RxD3 low
Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
Description
Reports the RxDL pin is shorted to GND.
Set/Reset condition
RxD3 high
Set: Rx low failure detected. Reset: failure recovered and flag read (SPI)
Description
Reports the RxDL pin is shorted to recessive voltage.
Set/Reset condition
TxD3 dom
Set: Rx high failure detected. Reset: failure recovered and flag read (SPI)
Description
Reports the TxDL pin is shorted to GND.
Set/Reset condition
LIN3 busdom clamp
Description
Set: Tx low failure detected. Reset: failure recovered and flag read (SPI)
Reports the LINx bus is dominant for a time longer than tDOM
b8
Set/Reset condition
LIN2 wake-up
Description
Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
Reports the wake-up source is LIN2
b6
Set/Reset condition
LIN 2 Overtemp
Description
Set: after CAN wake detected. Reset: Flag read (SPI)
Reports the LIN2 interface has reach overtemperature threshold.
b4
Set/Reset condition
Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
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Table 86. Individual bit description – LIN23 (continued)
Bits
Description
RxD2 low
Description
Reports the RxDL pin is shorted to GND.
b3
b2
b1
Set/Reset condition
RxD2 high
Set: Rx low failure detected. Reset: failure recovered and flag read (SPI)
Description
Reports the RxDL pin is shorted to recessive voltage.
Set/Reset condition
TxD2 dom
Set: Rx high failure detected. Reset: failure recovered and flag read (SPI)
Description
Reports the TxDL pin is shorted to GND.
Set/Reset condition
LIN2 busdom clamp
Description
Set: Tx low failure detected. Reset: failure recovered and flag read (SPI)
Reports the LINx bus is dominant for a time longer than tDOM
b0
Set/Reset condition
Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
4.3.3.1
Abnormal operation (as applicable to each specific ASIC)
The 33909 is subject to various conditions considered abnormal as defined within this section.
4.3.3.1.1
Jump start
Complete functionality is guaranteed for a battery voltage of 26.5 V (or other application specific value) up to T ≤ 50 °C for at least two
A
minutes. A complete characterization is completed at this voltage and temperature. Performance at two minutes is guaranteed by bench
characterization. No internal faults is set or abnormal operation noted as a result of operating in this range.
4.3.3.1.2
Load dump
The device must be capable of withstanding a typical load dump transient voltage of 40 V (or other application specific value) over the
entire specified operating temperature range. Full parametric conformance is not required, Functionality up to overvoltage shutdown is
guaranteed as well as up to the thermal capability of the package and external components with the exception of internal diagnostics,
which are not required. No internal faults are set as a result of operating in this range.
4.3.3.1.3
Low-voltage operation
The low-voltage operating range is the application specific voltage range where full parametric conformance is not required of the device.
However, all functions remain in stable operation and return to their proper behavior upon return to the normal operation voltage range.
4.3.3.1.4
Undervoltage lockout
This undervoltage lockout voltage range is dependent upon the silicon technology and the design, but is defined as the voltage range
where all applicable output drivers are maintained in their OFF state. This range is intended to define the voltages at which the device is
not capable of meeting internal threshold requirements to guarantee functionality. While in undervoltage lockout, the driver outputs are
not be allowed to 'float' and inadvertently turn an output ON.
4.3.3.1.5
Reverse battery
This device with applicable external components is not damaged by exposure to reverse battery conditions of -14 V (or other application
specific values). This test is performed for a period of one minute at 25 °C. In addition, this negative voltage condition does not force any
of the logic level I/O pins to a negative voltage less than -0.6 V at 10 mA, or to a positive voltage greater the 5.0 V DC. This insures
protection of the digital device interfacing with this device.
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4.3.3.1.6
Ground offset
The applicable driver outputs and/or current sense inputs are capable of operation with a ground offset of 2.0 V DC. The device is not
damaged by exposure to this condition and maintains specified functionality.
4.3.3.1.7
Shorts to ground
All I/O's of the device are available at the module connector and are protected against shorts to ground with maximum ground offset
considered (i.e. -2.0 V referenced to device ground or other application specific value). The device is not be damaged by this condition.
4.3.3.1.8
Shorts to battery
All I/O's of the device are available at the module connector and are protected against a short to battery (voltage value is application
dependent, there may be cases where short to jump start or load dump voltage values are required). The device is not damaged by this
condition.
4.3.3.1.9
Unpowered shorts to battery
All I/O's of the device are available at the module connector and are protected against unpowered (battery to the module is open) shorts
to battery per application specifics. The device is not damaged by this condition, does not enable any outputs, and does not back feed
onto the power rails (i.e, VBATP, VDD) or the digital I/O pins.
4.3.3.1.10 Loss of module ground
The definition of a loss of ground condition at the device level is, all pins of the IC see very low-impedance to battery. The nomenclature
is suited to a test environment. In the application, a loss of ground condition results in all I/O pins floating to battery voltage, while all
externally referenced I/O pins are at worst case pulled to ground. All applicable driver outputs and current sense inputs are protected
against excessive leakage current due to loads are referenced to an external ground (i.e, high-side drivers).
4.3.3.1.11 Loss of module battery
The loss of battery condition at the parts level is, the power input pins of the IC see infinite impedance to the battery supply voltage
(depending upon the application), but there is some undefined impedance looking from these pins to ground. All applicable driver outputs
and current sense inputs are protected against excessive leakage current due to loads are referenced to an external battery connection
(i.e., low-side drivers).
4.3.3.1.12 Stress tests (as applicable to each specific ASIC)
Each of the outputs must have a series of stress tests performed on 100% of the parts shipped. Experience has shown failure to
incorporate these tests results in field and plant failures. The following is a list of the tests required and a brief description of each test. In
general, for all of the following tests a significant number of parts must be tested to failure for the parameter in question so a statistically
valid destruction level can be found. After this level is determined for each of the following parameters, a level for a production test is
determined. This level must not be so high as to damage a normal part, but it must fail parts which do not fit in the normal process window.
Note: In all cases, the stress test must be performed to the level found during the previous part characterization and is not be tested to
the specification level. Even if the part meets this specification, but the parameter in question does not fall within the proper statistical
window, the part must be rejected. The only way a part can be considered good if it does not fall within the normal statistical window is if
an exact root cause analysis is performed and a detailed explanation is given, along with an assessment of risk. Any stress test limits
arrived at must at least meet the minimum requirements listed in this specification or the test has no validity.
4.3.3.1.13 Gate stress tests (as applicable to large power MOSFET drivers)
The gate stress test helps to test out random manufacturing defects within the gate oxide of the MOSFET. An initial gate-to-source leakage
test is performed with as high a voltage as possible without causing significant leakage of the Gate-to-source zener clamp. The leakage
is measured and recorded. Now a higher voltage (18 Volts, process and design related.) is applied to the gate of the MOSFET for a short
period of time. The leakage is again tested at the lower voltage and recorded. If the leakage is above an absolute value, or if possible
above a delta increase, the part is bad and must be rejected.
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4.3.3.1.14 BV
test (as applicable to power output drivers)
DSS
The purpose of this test is to ensure there is adequate headroom between the breakdown of the MOSFET output and the maximum clamp
voltage. Provisions need to be made to be able to defeat the drain-to-gate clamp diode so that the BV value can be measured. It is
DSS
also acceptable if the exact value is not found, but that a minimum guard band is tested to. A guard band of 5.0 to 10 V would be typical.
4.3.3.1.15 Elevated supply voltage stress
The purpose of this test is to find weak devices might fail if an unusual transient was seen. An elevated voltage of 40 Volts (Process
dependent) is applied to the VBATP pin.
4.3.3.1.16 IDDQ stress test
The purpose of this test is to identify defects (shorted or leaky devices) which cannot be detected by conventional functional testing. IDDQ
testing is required to be done separately for digital and analog circuit blocks. Test definition is per AEC Q100-007.
4.3.3.1.17 SCAN testing
The purpose of this test is to identify defects (shorted or leaky devices) which cannot be detected by conventional functional testing. IDDQ
testing is required to be done separately for digital and analog circuit blocks. Test definition is per AEC Q100-007.
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TYPICAL APPLICATIONS
5
Typical applications
The 33909 System basis chip is a highly integrated system basis chip with switch to ground input detection inputs. The 33909 was
designed to supply microprocessors and module power along with many of the most commonly needed functions in body modules.
L2
C26
R25
D3
VAUX
U2
D2
C19
U1
C20
CBOOT
VAUXB VAUX
VAUXE
VPRE
VSW VPREGATE
R16
VBAT
BOOT
C27 VBAT_SMPS
VDDE
L1
U3
VDDB
VDD
CPI1 CPI2
PI Filter
C17
D1
VDD
C21
C25
SAFE_B
AMUX
VBATP
VBATSNS
WDI
C18
RVBATSNS
RST_B
INT_B
RWDI
33909
MOSI
MISO
SCLK
CS_B
SG0
SG1
SG2
SG3
SG4
SG5
C0
C1
C2
C3
C4
C5
R0
R1
R2
R3
R4
R5
SPI
RXD_L0
TXD_L0
MCU
RXD_L1
TXD_L1
RXD_L2
TXD_L2
CANH
CANL
R22
CAN Bus
RXD_L3
TXD_L3
R21
RXD_C
TXD_C
VBATP
D7
D6
R19
R20
LIN_0
LIN_1
D5
R18
LIN Bus
D4
R17
LIN Bus
CAN5V
C22
LIN_2
LIN_3
LIN Bus
LIN Bus
GND
GND
CANGND
Figure 36. 33909AD typical application diagram
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PACKAGING
6
Packaging
6.1
Package dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and
perform a keyword search for the drawing’s document number.
Table 87.
Package
Suffix
Package outline drawing number
98ASA00737D
48-Pin LQFP
AD
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NXP Semiconductors
PACKAGING
33909
NXP Semiconductors
90
PACKAGING
.
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91
NXP Semiconductors
PACKAGING
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92
REVISION HISTORY
7
Revision history
Revision
Date
Description of changes
•
Initial Release
1.0
10/2013
1/2015
•
•
Removed 64-pin version
Major update
2.0
3.0
•
•
•
•
Added DC/DC to device description.
Updated Electrical Characteristics tables for ILOAD_BUCK, VDD Undervoltage, SPI VIH/VIL specs.
Updated text to match current device.
3/2015
Updated SPI tables to remove unused bits.
•
Changed device status in Orderable parts from PC to MC.
4/2015
7/2015
•
•
Added SG Low-power Mode Timing Diagram
Corrected TXD pin timing in Table 9
4.0
•
•
Added missing Interrupt table to Dynamic electrical characteristics
Updated to NXP document form and style
8/2016
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Information in this document is provided solely to enable system and software implementers to use NXP products.
There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits
based on the information in this document. NXP reserves the right to make changes without further notice to any
products herein.
How to Reach Us:
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NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular
purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"
parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,
and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each
customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor
the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the
following address:
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© 2016 NXP B.V.
Document Number: MC33909
Rev. 4.0
8/2016
相关型号：
MC33909Q5AD
System Basis Chip, 1 CAN, 4 LIN, 6 MSDI, 2A DC/DC, LV124, 5V/500mA LDO, LQFP-EP 48, Tray
NXP
MC33910G5AC
0.11A BUF OR INV BASED PRPHL DRVR, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BBA, LQFP-32
ROCHESTER
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