MC9328MXLVH20R2 [NXP]
IC,MICROPROCESSOR,32-BIT,CMOS,BGA,256PIN,PLASTIC;
| 型号： | MC9328MXLVH20R2 |
| 厂家： | 
NXP |
| 描述： | IC,MICROPROCESSOR,32-BIT,CMOS,BGA,256PIN,PLASTIC 时钟 外围集成电路 |
| 文件： | 总84页 (文件大小：1453K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC9328MXL/D
Rev. 5.1, 11/2004
Freescale Semiconductor
Advance Information
MC9328MXL
Package Information
Plastic Package
(MAPBGA–225 or 256)
MC9328MXL
Ordering Information
See Table 2 on page 5
Contents
1 Introduction
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
2 Signals and Connections . . . . . . . . . . . . . . . . . . . .6
3 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4 Pin-Out and Package Information. . . . . . . . . . . . .79
Contact Information . . . . . . . . . . . . . . . . . Last Page
The Freescale Semiconductor i.MX family builds on the
DragonBall family of application processors which have
demonstrated leadership in the portable handheld market.
Continuing this legacy, the i.MX (Media Extensions) series
provides a leap in performance with an ARM9™
microprocessor core and highly integrated system functions.
The i.MX products specifically address the requirements of
the personal, portable product market by providing intelligent
integrated peripherals, an advanced processor core, and
power management capabilities.
The new MC9328MXL features the advanced and power-
efficient ARM920T™ core that operates at speeds up to
200 MHz. Integrated modules, which include an LCD
controller, USB support, and an MMC/SD host controller,
support a suite of peripherals to enhance any product seeking
to provide a rich multimedia experience. It is packaged in
either a 256-pin Mold Array Process-Ball Grid Array
(MAPBGA) or 225-pin PBGA package. Figure 1 shows the
functional block diagram of the MC9328MXL.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
This document contains information on a new product. Specifications and information herein are
subject to change without notice.
Introduction
Standard
System I/O
System Control
Power
Control
CGM
(PLLx2)
JTAG/ICE
Bootstrap
GPIO
PWM
Connectivity
MC9328MXL
CPU Complex
ARM9TDMI™
MMC/SD
Timer 1 & 2
RTC
Memory Stick®
Host Controller
Watchdog
SPI 1 and
SPI 2
I Cache
D Cache
Multimedia
UART 1
UART 2
Multimedia
Accelerator
Interrupt
Controller
AIPI 1
AIPI 2
VMMU
Video Port
2
SSI/I S
DMAC
Bus
Human Interface
2
I C
(11 Chnl)
Control
LCD Controller
EIM &
SDRAMC
USB Device
Figure 1. MC9328MXL Functional Block Diagram
1.1 Conventions
This document uses the following conventions:
•
•
•
•
•
•
•
•
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
Logic level one is a voltage that corresponds to Boolean true (1) state.
Logic level zero is a voltage that corresponds to Boolean false (0) state.
To set a bit or bits means to establish logic level one.
To clear a bit or bits means to establish logic level zero.
A signal is an electronic construct whose state conveys or changes in state convey information.
A pin is an external physical connection. The same pin can be used to connect a number of signals.
Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
•
•
•
LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and
high bytes or words are spelled out.
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are
hexadecimal.
MC9328MXL Advance Information, Rev. 5.1
2
Freescale Semiconductor
Introduction
1.2 Features
To support a wide variety of applications, the MC9328MXL offers a robust array of features, including the
following:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ARM920T™ Microprocessor Core
AHB to IP Bus Interfaces (AIPIs)
External Interface Module (EIM)
SDRAM Controller (SDRAMC)
DPLL Clock and Power Control Module
Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2)
Two Serial Peripheral Interfaces (SPI1 and SPI2)
Two General-Purpose 32-bit Counters/Timers
Watchdog Timer
Real-Time Clock/Sampling Timer (RTC)
LCD Controller (LCDC)
Pulse-Width Modulation (PWM) Module
Universal Serial Bus (USB) Device
Multimedia Card and Secure Digital (MMC/SD) Host Controller Module
Memory Stick® Host Controller (MSHC)
Direct Memory Access Controller (DMAC)
•
Synchronous Serial Interface and Inter-IC Sound (SSI/I2S) Module
•
•
•
•
•
•
•
•
•
Inter-IC (I2C) Bus Module
Video Port
General-Purpose I/O (GPIO) Ports
Bootstrap Mode
Multimedia Accelerator (MMA)
Power Management Features
Operating Voltage Range: 1.7 V to 1.98 V core, 1.7 V to 3.3V I/O
256-pin MAPBGA Package
225-pin MAPBGA Package
1.3 Target Applications
The MC9328MXL is targeted for advanced information appliances, smart phones, Web browsers, digital MP3
audio players, handheld computers, and messaging applications.
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
3
Introduction
1.4 Revision History
Table 1 provides revision history for this release. This history includes technical content revisions only and not
stylistic or grammatical changes.
Product Documentation
Table 1. MC9328MXL Data Sheet Revision History
Revision
Changes references from Motorola to Freescale Semiconductor as applicable, throughout document.
The following documents are required for a complete description of the MC9328MXL and are necessary to design
properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall
products, the following documents are helpful when used in conjunction with this document.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)
EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)
MC9328MXL Product Brief (order number MC9328MXLP/D)
MC9328MXL Reference Manual (order number MC9328MXLRM/D)
The Freescale manuals are available on the Freescale Semiconductors Web site at
http://www.freescale.com/semiconductors. These documents may be downloaded directly from the Freescale Web
site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.
MC9328MXL Advance Information, Rev. 5.1
4
Freescale Semiconductor
Introduction
1.5 Ordering Information
Table 2 provides ordering information for both the 256-lead mold array process ball grid array (MAPBGA)
package and the 225-lead BGA package.
Table 2. MC9328MXL Ordering Information
Package Type
Frequency
Temperature
Solderball Type
Order Number
-40OC to 85OC
256-lead MAPBGA
150 MHz
Standard
Pb-free
MC9328MXLCVH15(R2)
MC9328MXLCVM15(R2)
MC9328MXLVH20(R2)
MC9328MXLVM20(R2)
MC9328MXLDVH20(R2)
MC9328MXLDVM20(R2)
MC9328MXLCVF15(R2)
MC9328MXLCVP15(R2)
MC9328MXLVF20(R2)
MC9328MXLVP20(R2)
MC9328MXLDVF20(R2)
MC9328MXLDVP20(R2)
0OC to 70OC
-30OC to 70OC
-40OC to 85OC
0OC to 70OC
200 MHz
Standard
Pb-free
Standard
Pb-free
225-lead MAPBGA
150 MHz
200 MHz
Standard
Pb-free
Standard
Pb-free
-30OC to 70OC
Standard
Pb-free
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
5
Signals and Connections
2 Signals and Connections
Table 3 identifies and describes the MC9328MXL signals that are assigned to package pins. The signals are
grouped by the internal module that they are connected to.
Table 3. MC9328MXL Signal Descriptions
Signal Name
Function/Notes
External Bus/Chip-Select (EIM)
A[24:0]
Address bus signals
Data bus signals
D[31:0]
EB0
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].
Byte Strobe—Active low external enable byte signal that controls D [23:16].
Byte Strobe—Active low external enable byte signal that controls D [15:8].
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].
Memory Output Enable—Active low output enables external data bus.
EB1
EB2
EB3
OE
CS [5:0]
Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.
ECB
LBA
Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
Active low signal sent by a flash device causing the external burst device to latch the starting burst
address.
BCLK (burst clock)
RW
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE
input signal by external DRAM.
DTACK
DTACK signal—The external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is
not terminated by the external DTACK signal after 1022 clock counts have elapsed.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the MC9328MXL upon system
reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0]
SDIBA [3:0]
SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A [15:11].
These signals are logically equivalent to core address p_addr [25:21] in SDRAM/SyncFlash cycles.
SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address signals A
[19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM/SyncFlash
cycles.
MA [11:10]
MA [9:0]
SDRAM address signals
SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected
on SDRAM/SyncFlash cycles.
DQM [3:0]
CSD0
SDRAM data enable
SDRAM/SyncFlash Chip-select signal which is multiplexed with the CS2 signal. These two signals
are selectable by programming the system control register.
MC9328MXL Advance Information, Rev. 5.1
6
Freescale Semiconductor
Signals and Connections
Table 3. MC9328MXL Signal Descriptions (Continued)
Function/Notes
Signal Name
CSD1
SDRAM/SyncFlash Chip-select signal which is multiplexed with CS3 signal. These two signals are
selectable by programming the system control register. By default, CSD1 is selected, so it can be
used as SyncFlash boot chip-select by properly configuring BOOT [3:0] input pins.
RAS
SDRAM/SyncFlash Row Address Select signal
SDRAM/SyncFlash Column Address Select signal
SDRAM/SyncFlash Write Enable signal
SDRAM/SyncFlash Clock Enable 0
SDRAM/SyncFlash Clock Enable 1
SDRAM/SyncFlash Clock
CAS
SDWE
SDCKE0
SDCKE1
SDCLK
RESET_SF
SyncFlash Reset
Clocks and Resets
EXTAL16M
Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is
shut down.
XTAL16M
EXTAL32K
XTAL32K
CLKO
Crystal output
32 kHz crystal input
32 kHz crystal output
Clock Out signal selected from internal clock signals.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all
modules (except the reset module and the clock control module) are reset.
RESET_OUT
POR
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from
the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally
generated by an external RC circuit designed to detect a power-up event.
JTAG
TRST
TDO
TDI
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
Serial Output for test instructions and data. Changes on the falling edge of TCK.
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
Test Clock to synchronize test logic and control register access through the JTAG port.
TCK
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge
of TCK.
DMA
BIG_ENDIAN
DMA_REQ
Big Endian—Input signal that determines the configuration of the external chip-select space. If it is
driven logic-high at reset, the external chip-select space will be configured to little endian. If it is
driven logic-low at reset, the external chip-select space will be configured to big endian.
External DMA request pin.
ETM
ETMTRACESYNC
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
7
Signals and Connections
Signal Name
Table 3. MC9328MXL Signal Descriptions (Continued)
Function/Notes
ETMTRACECLK
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.
ETMPIPESTAT [2:0]
ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM
mode.
ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK(burst clock), PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
CMOS Sensor Interface
CSI_D [7:0]
CSI_MCLK
CSI_VSYNC
CSI_HSYNC
CSI_PIXCLK
Sensor port data
Sensor port master clock
Sensor port vertical sync
Sensor port horizontal sync
Sensor port data latch clock
LCD Controller
LD [15:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
FLM/VSYNC
Frame Sync or Vsync—This signal also serves as the clock signal output for the gate
driver (dedicated signal SPS for Sharp panel HR-TFT).
LP/HSYNC
LSCLK
Line pulse or H sync
Shift clock
ACD/OE
CONTRAST
SPL_SPR
PS
Alternate crystal direction/output enable.
This signal is used to control the LCD bias voltage as contrast control.
Program horizontal scan direction (Sharp panel dedicated signal).
Control signal output for source driver (Sharp panel dedicated signal).
CLS
Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated
signal).
REV
Signal for common electrode driving signal preparation (Sharp panel dedicated signal).
SPI 1 and 2
Master Out/Slave In
SPI1_MOSI
SPI1_MISO
SPI1_SS
Slave In/Master Out
Slave Select (Selectable polarity)
Serial Clock
SPI1_SCLK
SPI1_SPI_RDY
SPI2_TXD
Serial Data Ready
SPI2 Master TxData Output—This signal is multiplexed with a GPI/O pin yet shows up as a primary
or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters
in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned
pin.
SPI2_RXD
SPI2 Master RxData Input—This signal is multiplexed with a GPI/O pin yet shows up as a primary or
alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in
the MC9328MXL Reference Manual for information about how to bring this signal to the assigned
pin.
MC9328MXL Advance Information, Rev. 5.1
8
Freescale Semiconductor
Signals and Connections
Table 3. MC9328MXL Signal Descriptions (Continued)
Function/Notes
Signal Name
SPI2_SS
SPI2 Slave Select—This signal is multiplexed with a GPI/O pin yet shows up as a primary or
alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in
the MC9328MXL Reference Manual for information about how to bring this signal to the assigned
pin.
SPI2_SCLK
SPI2 Serial Clock—This signal is multiplexed with a GPI/O pin yet shows up as a primary or
alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in
the MC9328MXL Reference Manual for information about how to bring this signal to the assigned
pin.
General Purpose Timers
TIN
Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers
simultaneously.
TMR2OUT
Timer 2 Output
USB Device
USBD_VMO
USBD_VPO
USBD_VM
USB Minus Output
USB Plus Output
USB Minus Input
USB Plus Input
USBD_VP
USBD_SUSPND
USBD_RCV
USBD_OE
USB Suspend Output
USB Receive Data
USB OE
USBD_AFE
USB Analog Front End Enable
Secure Digital Interface
SD_CMD
SD Command—If the system designer does not wish to make use of the internal pull-up, via the Pull-
up enable register, a 4.7K–69K external pull up resistor must be added.
SD_CLK
MMC Output Clock
SD_DAT [3:0]
Data—If the system designer does not wish to make use of the internal pull-up, via the Pull-up enable
register, a 50K–69K external pull up resistor must be added.
Memory Stick Interface
MS_BS
Memory Stick Bus State (Output)—Serial bus control signal
Memory Stick Serial Data (Input/Output)
MS_SDIO
MS_SCLKO
MS_SCLKI
Memory Stick Serial Clock (Input)—Serial protocol clock source for SCLK Divider
Memory Stick External Clock (Output)—Test clock input pin for SCLK divider. This pin is only for test
purposes, not for use in application mode.
MS_PI0
MS_PI1
General purpose Input0—Can be used for Memory Stick Insertion/Extraction detect
General purpose Input1—Can be used for Memory Stick Insertion/Extraction detect
UARTs – IrDA/Auto-Bauding
UART1_RXD
UART1_TXD
Receive Data
Transmit Data
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
9
Signals and Connections
Signal Name
Table 3. MC9328MXL Signal Descriptions (Continued)
Function/Notes
UART1_RTS
UART1_CTS
UART2_RXD
UART2_TXD
UART2_RTS
UART2_CTS
UART2_DSR
UART2_RI
Request to Send
Clear to Send
Receive Data
Transmit Data
Request to Send
Clear to Send
Data Set Ready
Ring Indicator
UART2_DCD
UART2_DTR
Data Carrier Detect
Data Terminal Ready
Serial Audio Port – SSI (configurable to I2S protocol)
SSI_TXDAT
SSI_RXDAT
SSI_TXCLK
SSI_RXCLK
SSI_TXFS
Transmit Data
Receive Data
Transmit Serial Clock
Receive Serial Clock
Transmit Frame Sync
Receive Frame Sync
SSI_RXFS
I2C
I2C_SCL
I2C_SDA
I2C Clock
I2C Data
PWM
PWMO
PWM Output
Digital Supply Pins
NVDD
NVSS
Digital Supply for the I/O pins
Digital Ground for the I/O pins
Supply Pins – Analog Modules
AVDD
AVSS
Supply for analog blocks
Quiet ground for analog blocks
Internal Power Supply
QVDD
QVSS
Power supply pins for silicon internal circuitry
Ground pins for silicon internal circuitry
MC9328MXL Advance Information, Rev. 5.1
10
Freescale Semiconductor
Specifications
Table 3. MC9328MXL Signal Descriptions (Continued)
Function/Notes
Signal Name
Substrate Supply Pins
SVDD
SGND
Supply routed through substrate of package; not to be bonded
Ground routed through substrate of package; not to be bonded
3 Specifications
This section contains the electrical specifications and timing diagrams for the MC9328MXL processor.
3.1 Maximum Ratings
Table 4 provides information on maximum ratings.
Table 4. Maximum Ratings
Rating
Symbol
Vdd
Minimum
Maximum
Unit
V
Supply voltage
-0.3
0
3.3
70
Maximum operating temperature range
MC9328MXLVH20/MC9328MXLVM20/
MC9328MXLVF20/MC9328MXLVP20
TA
°C
Maximum operating temperature range
MC9328MXLDVH20/MC9328MXLDVM20/
MC9328MXLDVF20/MC9328MXLDVP20
TA
TA
-30
-40
70
85
°C
°C
Maximum operating temperature range
MC9328MXLCVH15/MC9328MXLCVM15/
MC9328MXLCVF15/MC9328MXLCVP15
ESD at human body model (HBM)
ESD at machine model (MM)
Latch-up current
VESD_HBM
VESD_MM
ILatchup
Test
–
–
2000
100
200
150
V
V
–
mA
°C
Storage temperature
-55
8001
13002
Power Consumption
Pmax
mW
1. A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from
the ARM® core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.
2. A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches
from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core
running its heaviest OS application at 200MHz, and where the whole image is running out of SDRAM. QVDD at
2.0V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst measurement recorded in the factory environment,
max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA.
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
11
Specifications
3.2 Recommended Operating Range
Table 5 provides the recommended operating ranges for the supply voltages. The MC9328MXL has multiple pairs
of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. All other VDD
and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power to the enclosed I/
O pads. This design allows different peripheral supply voltage levels in a system.
Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the
AVDD pins from other VDD pins.
For more information about I/O pads grouping per VDD, please refer to Table 3 on page 6.
Table 5. Recommended Operating Range
Rating
Symbol
Minimum Maximum Unit
I/O supply voltage (if using MSHC, SPI, BTA, USBd, LCD and CSI
which are only 3 V interfaces)
NVDD
2.70
3.30
V
I/O supply voltage (if not using the peripherals listed above)
Internal supply voltage (Core = 150 MHz)
Internal supply voltage (Core = 200 MHz)
Analog supply voltage
NVDD
QVDD
QVDD
AVDD
1.70
1.70
1.80
1.70
3.30
1.90
2.00
3.30
V
V
V
V
3.3 Power Sequence Requirements
For required power-up and power-down sequencing, please refer to the "Power-Up Sequence" section of
application note AN2537 on the i.MX website page.
3.4 DC Electrical Characteristics
Table 6 contains both maximum and minimum DC characteristics of the MC9328MXL.
Table 6. Maximum and Minimum DC Characteristics
Number or
Symbol
Parameter
Min
Typical
Max
Unit
Iop
Full running operating current at 1.8V for QVDD, 3.3V for
NVDD/AVDD (Core = 96 MHz, System = 96 MHz, MPEG4
decoding playback from external memory card to both
external SSI audio decoder and TFT display panel, and OS
with MMU enabled memory system is running on external
SDRAM).
–
QVDD at
–
mA
1.8v = 120mA;
NVDD+AVDD at
3.0v = 30mA
Sidd1
Sidd2
Sidd3
Standby current
(Core = 150 MHz, QVDD = 1.8V, temp = 25°C)
–
–
–
25
45
35
–
–
–
µA
µA
µA
Standby current
(Core = 150 MHz, QVDD = 1.8V, temp = 55°C)
Standby current
(Core = 150 MHz, QVDD = 2.0V, temp = 25°C)
MC9328MXL Advance Information, Rev. 5.1
12
Freescale Semiconductor
Specifications
Table 6. Maximum and Minimum DC Characteristics (Continued)
Number or
Symbol
Parameter
Min
Typical
Max
Unit
Sidd4
Standby current
–
60
–
µA
(Core = 150 MHz, QVDD = 2.0V, temp = 55°C)
V
Input high voltage
0.7V
–
–
–
–
–
Vdd+0.2
0.4
V
V
IH
DD
V
Input low voltage
–
0.7V
–
IL
V
Output high voltage (I
= 2.0 mA)
Vdd
0.4
V
OH
OH
DD
V
Output low voltage (I = -2.5 mA)
OL
V
OL
IL
I
Input low leakage current
–
1
µA
(V = GND, no pull-up or pull-down)
IN
I
Input high leakage current
–
–
–
–
–
–
1
4.0
–
µA
mA
mA
µA
IH
(V = V , no pull-up or pull-down)
IN
DD
I
Output high current
(V = 0.8VDD, VDD = 1.8V)
OH
OH
I
Output low current
-4.0
OL
(V = 0.4V, VDD = 1.8V)
OL
I
Output leakage current
–
5
OZ
(V = V , output is tri-stated)
out
DD
C
Input capacitance
–
–
–
–
5
5
pF
pF
i
C
Output capacitance‘
o
3.5 AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are
specified relative to an appropriate edge of other signals. All timing specifications are specified at a system
operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an operating supply voltage
from VDD min to VDD max under an operating temperature from TL to TH. All timing is measured at 30 pF loading.
Table 7. Tristate Signal Timing
Pin
Parameter
Minimum
Maximum
Unit
TRISTATE Time from TRISTATE activate until I/O becomes Hi-Z
–
20.8
ns
Table 8. 32k/16M Oscillator Signal Timing
Parameter
Minimum
RMS
Maximum
Unit
EXTAL32k input jitter (peak to peak)
–
5
20
ns
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
13
Specifications
Table 8. 32k/16M Oscillator Signal Timing (Continued)
Parameter
EXTAL32k startup time
Minimum
RMS
Maximum
Unit
800
–
–
TBD
–
–
TBD
–
ms
–
EXTAL16M input jitter (peak to peak)
EXTAL16M startup time
TBD
–
3.6 Embedded Trace Macrocell
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit
shift register comprised of the following:
•
•
•
32-bit data field
7-bit address field
A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address
field, and a 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit
data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.
The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used
in Figure 2.
2a
1
2b
3a
TRACECLK
3b
TRACECLK
(Half-Rate Clocking Mode)
Output Trace Port
Valid Data
Valid Data
4a
Figure 2. Trace Port Timing Diagram
Table 9. Trace Port Timing Diagram Parameter Table
1.8V ꢀ.1ꢀV 3.ꢀV ꢀ.3ꢀV
4b
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
CLK frequency
Clock high time
Clock low time
0
1.3
3
85
–
0
2
2
100
–
MHz
ns
2a
2b
–
–
ns
MC9328MXL Advance Information, Rev. 5.1
14
Freescale Semiconductor
Specifications
Unit
Table 9. Trace Port Timing Diagram Parameter Table (Continued)
1.8V ꢀ.1ꢀV 3.ꢀV ꢀ.3ꢀV
Ref
No.
Parameter
Minimum
Maximum
Minimum
Maximum
3a
3b
4a
4b
Clock rise time
–
4
3
–
–
–
–
2
3
3
3
–
–
ns
ns
ns
ns
Clock fall time
–
Output hold time
Output setup time
2.28
3.42
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
15
Specifications
3.7 DPLL Timing Specifications
Parameters of the DPLL are given in Table 10. In this table, Tref is a reference clock period after the
pre-divider and Tdck is the output double clock period.
Table 1ꢀ. DPLL Specifications
Parameter
Test Conditions
Vcc = 1.8V
Minimum Typical Maximum
Unit
Reference clock freq range
5
5
–
–
100
30
MHz
MHz
Pre-divider output clock
freq range
Vcc = 1.8V
Double clock freq range
Pre-divider factor (PD)
Vcc = 1.8V
–
80
1
–
–
–
220
16
MHz
–
–
Total multiplication factor (MF) Includes both integer
and fractional parts
5
15
MF integer part
MF numerator
–
5
0
–
–
15
–
–
Should be less than the
denominator
1022
MF denominator
–
–
1
–
–
–
1023
312.5
300
–
Pre-multiplier lock-in time
µsec
Tref
Freq lock-in time after
full reset
FOL mode for non-integer MF
(does not include pre-multi lock-in
time)
250
280
(56 µs)
Freq lock-in time after
partial reset
FOL mode for non-integer MF
(does not include pre-multi lock-in
time)
220
250
(50 µs)
270
Tref
Phase lock-in time after
full reset
FPL mode and integer MF (does
not include pre-multi lock-in time)
300
270
–
350
(70 µs)
400
370
0.01
1.5
Tref
Phase lock-in time after
partial reset
FPL mode and integer MF (does
not include pre-multi lock-in time)
320
(64 µs)
Tref
Freq jitter (p-p)
–
0.005
(0.01%)
2•Tdck
ns
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.8V
–
1.0
(10%)
Power supply voltage
Power dissipation
–
1.7
–
–
–
2.5
4
V
FOL mode, integer MF,
mW
f
dck = 200 MHz, Vcc = 1.8V
MC9328MXL Advance Information, Rev. 5.1
16
Freescale Semiconductor
Specifications
3.8 Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and
Figure 4.
NOTE:
Be aware that NVDD must ramp up to at least 1.8V before QVDD is
powered up to prevent forward biasing.
90% AVDD
1
10% AVDD
POR
2
RESET_POR
Exact 300ms
3
7 cycles @ CLK32
RESET_DRAM
4
14 cycles @ CLK32
HRESET
RESET_OUT
CLK32
HCLK
Figure 3. Timing Relationship with POR
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
17
Specifications
5
RESET_IN
14 cycles @ CLK32
HRESET
4
RESET_OUT
6
CLK32
HCLK
Figure 4. Timing Relationship with RESET_IN
Table 11. Reset Module Timing Parameter Table
1.8V ꢀ.1ꢀV
3.ꢀV ꢀ.3ꢀV
Ref
No.
Parameter
Unit
Min
Max
–
Min
Max
–
note1
300
note1
300
1
2
Width of input POWER_ON_RESET
–
Width of internal POWER_ON_RESET
(CLK32 at 32 kHz)
300
300
ms
3
4
5
6
7K to 32K-cycle stretcher for SDRAM reset
7
14
4
7
14
–
7
14
4
7
14
–
Cycles of
CLK32
14K to 32K-cycle stretcher for internal system reset
HRESERT and output reset at pin RESET_OUT
Cycles of
CLK32
Width of external hard-reset RESET_IN
Cycles of
CLK32
4K to 32K-cycle qualifier
4
4
4
4
Cycles of
CLK32
1. POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should
allow for crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence.
Through the process of supplying crystals for use with CMOS oscillators, crystal manufacturers have
developed a working knowledge of start-up time of their crystals. Typically, start-up times range from
400 ms to 1.2 seconds for this type of crystal.
If an external stable clock source (already running) is used instead of a crystal, the width of POR should
be ignored in calculating timing for the start-up process.
MC9328MXL Advance Information, Rev. 5.1
18
Freescale Semiconductor
Specifications
3.9 External Interface Module
The External Interface Module (EIM) handles the interface to devices external to the MC9328MXL,
including the generation of chip-selects for external peripherals and memory. The timing diagram for the
EIM is shown in Figure 5, and Table 12 on page 20 defines the parameters of signals.
(HCLK) Bus Clock
1a
2a
3a
1b
2b
3b
Address
Chip-select
Read (Write)
4a
5a
4b
5b
OE (rising edge)
4c
5c
4d
OE (falling edge)
EB (rising edge)
EB (falling edge)
5d
6b
6a
6a
LBA (negated falling edge)
LBA (negated rising edge)
6c
7a
7b
Burst Clock (rising edge)
7c
7d
Burst Clock (falling edge)
Read Data
8b
9a
9a
8a
9b
Write Data (negated falling)
9c
Write Data (negated rising)
10a
10a
DTACK
Figure 5. EIM Bus Timing Diagram
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
19
Specifications
Table 12. EIM Bus Timing Parameter Table
1.8V 0.10V
3.ꢀV ꢀ.3ꢀV
Ref No.
Parameter
Unit
Min
Typical Max
Min
Typical Max
1a
1b
2a
2b
3a
3b
4a
4b
4c
4d
5a
5b
5c
5d
6a
6b
6c
7a
7b
7c
7d
8a
8b
9a
9b
9c
10a
Clock fall to address valid
2.48
1.55
2.69
1.55
1.35
1.86
2.32
2.11
2.38
2.17
1.91
1.81
1.97
1.76
2.07
1.97
1.91
1.61
1.61
1.55
1.55
5.54
0
3.31
2.48
3.31
2.48
2.79
2.59
2.62
2.52
2.69
2.59
2.52
2.42
2.59
2.48
2.79
2.79
2.62
2.62
2.62
2.48
2.59
–
9.11
5.69
7.87
6.31
6.52
6.11
6.85
6.55
7.04
6.73
5.54
5.24
5.69
5.38
6.73
6.83
6.45
5.64
5.84
5.59
5.80
–
2.4
1.5
2.6
1.5
1.3
1.8
2.3
2.1
2.3
2.1
1.9
1.8
1.9
1.7
2.0
1.9
1.9
1.6
1.6
1.5
1.5
5.5
0
3.2
2.4
3.2
2.4
2.7
2.5
2.6
2.5
2.6
2.5
2.5
2.4
2.5
2.4
2.7
2.7
2.6
2.6
2.6
2.4
2.5
–
8.8
5.5
7.6
6.1
6.3
5.9
6.8
6.5
6.8
6.5
5.5
5.2
5.5
5.2
6.5
6.6
6.4
5.6
5.8
5.4
5.6
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock fall to address invalid
Clock fall to chip-select valid
Clock fall to chip-select invalid
Clock fall to Read (Write) Valid
Clock fall to Read (Write) Invalid
Clock1 rise to Output Enable Valid
Clock1 rise to Output Enable Invalid
Clock1 fall to Output Enable Valid
Clock1 fall to Output Enable Invalid
Clock1 rise to Enable Bytes Valid
Clock1 rise to Enable Bytes Invalid
Clock1 fall to Enable Bytes Valid
Clock1 fall to Enable Bytes Invalid
Clock1 fall to Load Burst Address Valid
Clock1 fall to Load Burst Address Invalid
Clock1 rise to Load Burst Address Invalid
Clock1 rise to Burst Clock rise
Clock1rise to Burst Clock fall
Clock1 fall to Burst Clock rise
Clock1 fall to Burst Clock fall
Read Data setup time
Read Data hold time
–
–
–
–
Clock1 rise to Write Data Valid
Clock1 fall to Write Data Invalid
Clock1 rise to Write Data Invalid
DTACK setup time
1.81
1.45
1.63
2.52
2.72
2.48
–
6.85
5.69
–
1.8
1.4
1.62
2.5
2.7
2.4
–
6.8
5.5
–
–
–
–
–
1. Clock refers to the system clock signal, HCLK, generated from the System PLL
MC9328MXL Advance Information, Rev. 5.1
20
Freescale Semiconductor
Specifications
3.9.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only CS5 group is
designed to support DTACK signal function when using the external DTACK signal for data
acknowledgement.
3.9.2 DTACK Signal Timing
Figure 6 shows the access cycle timing used by chip-select 5. The signal values and units of measure for
this figure are found in Table 13.
HCLK
CS5
3
RW
1
5
OE
4
EXT_DTACK
2
INT_DTACK
Figure 6. DTACK Timing, WSC=111111, DTACK_sel=ꢀ
Table 13. Access Cycle Timing Parameters
1.8V ꢀ.1ꢀV
3.ꢀV ꢀ.3ꢀV
Ref
No.
Characteristic
Unit
Min
Max
Min
Max
1
2
CS5 asserted to OE asserted
–
0
T
–
–
0
T
–
ns
ns
External DTACK input setup from CS5
asserted
3
4
CS5 pulse width
3T
0
–
3T
0
–
ns
ns
External DTACK input hold after CS5 is
negated
1.5T
1.5T
5
OE negated after CS5 is negated
0
4.5
0
4
ns
Note:
1. n is the number of wait states in the current memory access cycle. The max n is 1022.
2. T is the system clock period (system clock is 96 MHz).
3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
21
Specifications
HCLK
CS5
RW
OE
1
EXT_DTACK (WAIT)
INT_DTACK
Figure 7. DTACK Timing, WSC=111111, DTACK_sel=1
Table 14. Access Cycle Timing Parameters
1.8V ꢀ.1ꢀV
Min Max
3.ꢀV ꢀ.3ꢀV
Ref
No.
Characteristic
Unit
Min
Max
1
External DTACK input setup from CS5
asserted
0
–
0
–
ns
Note:
1. n is the number of wait states in the current memory access cycle. The max n is 1022.
2. T is the system clock period (system clock is 96 MHz).
3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MXL Advance Information, Rev. 5.1
22
Freescale Semiconductor
Specifications
3.9.3 EIM External Bus Timing
The timing diagrams in this section show the timing of accesses to memory or a peripheral.
hclk
hsel_weim_cs[0]
htrans
hwrite
Seq/Nonseq
Read
haddr
hready
V1
weim_hrdata
weim_hready
Last Valid Data
V1
weim_bclk
weim_addr
Last Valid Address
V1
weim_cs
weim_r/w
Read
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
V1
Figure 8. WSC = 1, A.HALF/E.HALF
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
23
Specifications
hclk
hsel_weim_cs[0]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid Data
Write Data (V1)
Unknown
weim_hrdata
Last Valid Data
weim_hready
weim_bclk
weim_addr
Last Valid Address
V1
weim_cs[0]
weim_r/w
weim_lba
weim_oe
weim_eb
Write
weim_data_out
Last Valid Data
Write Data (V1)
Figure 9. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
MC9328MXL Advance Information, Rev. 5.1
24
Freescale Semiconductor
Specifications
hclk
hsel_weim_cs[0]
htrans
Nonseq
Read
V1
hwrite
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V1 + 2
weim_cs[0]
weim_r/w
weim_lba
weim_oe
Read
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Figure 1ꢀ. WSC = 1, OEA = 1, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
25
Specifications
hclk
hsel_weim_cs[0]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid Data
Write Data (V1 Word)
Last Valid Data
weim_hrdata
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V1 + 2
weim_cs[0]
weim_r/w
weim_lba
weim_oe
weim_eb
Write
weim_data_out
1/2 Half Word
2/2 Half Word
Figure 11. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5.1
26
Freescale Semiconductor
Specifications
hclk
hsel_weim_cs[3]
htrans
Nonseq
hwrite
Read
V1
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V1 + 2
weim_cs[3]
weim_r/w
weim_lba
weim_oe
Read
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Figure 12. WSC = 3, OEA = 2, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
27
Specifications
hclk
hsel_weim_cs[3]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata Last Valid
Write Data (V1 Word)
Last Valid Data
Data
weim_hrdata
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V1 + 2
weim_cs[3]
weim_r/w
weim_lba
weim_oe
Write
weim_eb
weim_data_out]
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 13. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5.1
28
Freescale Semiconductor
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
hwrite
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V1 + 2
weim_cs[2]
weim_r/w
Read
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Figure 14. WSC = 3, OEA = 4, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
29
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid
Data
Write Data (V1 Word)
Last Valid Data
weim_hrdata
weim_hready
weim_bclk
weim_addr Last Valid Addr
weim_cs[2]
Address V1
Address V1 + 2
weim_r/w
Write
weim_lba
weim_oe
weim_eb
weim_data_out
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 15. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5.1
30
Freescale Semiconductor
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
hwrite
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V1 + 2
weim_cs[2]
weim_r/w
Read
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Figure 16. WSC = 3, OEN = 2, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
31
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
hwrite
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V1 + 2
weim_cs[2]
weim_r/w
weim_lba
Read
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Figure 17. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5.1
32
Freescale Semiconductor
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid
Data
Write Data (V1 Word)
Last Valid Data
Unknown
weim_hrdata
weim_hready
weim_bclk
weim_addr Last Valid Addr
weim_cs[2]
Address V1
Address V1 + 2
weim_r/w
Write
weim_lba
weim_oe
weim_eb
weim_data_out
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 18. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
33
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid
Data
Write Data (V1 Word)
Last Valid Data
Unknown
weim_hrdata
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V1 + 2
weim_cs[2]
weim_r/w
weim_lba
weim_oe
weim_eb
Write
weim_data_out
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 19. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5.1
34
Freescale Semiconductor
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
Nonseq
Write
V8
hwrite
haddr
hready
hwdata
Last Valid Data
Write Data
Read Data
weim_hrdata
weim_hready
Last Valid Data
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V8
weim_cs[2]
weim_r/w
weim_lba
Read
Write
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
weim_data_out
Read Data
Last Valid Data
Write Data
Figure 2ꢀ. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
35
Specifications
Read
Idle
Write
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
Nonseq
Write
V8
hwrite
haddr
hready
hwdata
Last Valid Data
Write Data
weim_hrdata
weim_hready
Last Valid Data
Read Data
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V8
Write
weim_cs[2]
weim_r/w
Read
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
weim_data_out
Read Data
Last Valid Data
Write Data
Figure 21. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF
MC9328MXL Advance Information, Rev. 5.1
36
Freescale Semiconductor
Specifications
hclk
hsel_weim_cs[4]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid
Data
Write Data (Word)
Last Valid Data
weim_hrdata
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V1 + 2
weim_cs
weim_r/w
Write
weim_lba
weim_oe
weim_eb
weim_data_out
Last Valid Data
Write Data (1/2 Half Word)
Write Data (2/2 Half Word)
Figure 22. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
37
Specifications
hclk
hsel_weim_cs[4]
htrans
Nonseq
Read
V1
Nonseq
Write
V8
hwrite
haddr
hready
hwdata
weim_hrdata
weim_hready
Last Valid Data
Write Data
Read Data
Last Valid Data
weim_bclk
weim_addr Last Valid Addr
weim_cs[4]
Address V1
Address V8
weim_r/w
Read
Write
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
Read Data
weim_data_in
weim_data_out
Last Valid Data
Write Data
Figure 23. WSC = 3, CSA = 1, A.HALF/E.HALF
MC9328MXL Advance Information, Rev. 5.1
38
Freescale Semiconductor
Specifications
hclk
hsel_weim_cs[4]
htrans
Nonseq
Read
V1
Idle
Seq
Read
V2
hwrite
haddr
hready
weim_hrdata
weim_hready
Last Valid Data
Read Data (V1)
Read Data (V2)
weim_bclk
weim_addr
Last Valid
Address V1
Address V2
CNC
weim_cs[4]
weim_r/w
weim_lba
Read
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
Read Data
(V1)
Read Data
(V2)
weim_data_in
Figure 24. WSC = 2, OEA = 2, CNC = 3, BCM = ꢀ, A.HALF/E.HALF
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
39
Specifications
hclk
hsel_weim_cs[4]
htrans
Nonseq
Read
V1
Idle Nonseq
hwrite
haddr
Write
V8
hready
hwdata
Last Valid Data
Write Data
weim_hrdata
Last Valid Data
Read Data
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V8
CNC
weim_cs[4]
weim_r/w
Read
Write
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
weim_data_out
Read Data
Last Valid Data
Write Data
Figure 25. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF
MC9328MXL Advance Information, Rev. 5.1
40
Freescale Semiconductor
Specifications
hclk
hsel_weim_cs[2]
htrans
Idle
Nonseq
Read
V1
Nonse
Read
V5
hwrite
haddr
hready
weim_hrdata
weim_hready
weim_bclk
weim_addr]
Last Valid Addr
Address V1
Address V5
weim_cs[2]
Read
weim_r/w
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_ecb
weim_data_in
V1 Word V2 Word
V5 Word V6 Word
Figure 26. WSC = 3, SYNC = 1, A.HALF/E.HALF
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
41
Specifications
hclk
hsel_weim_cs[2]
htrans
Idle
Nonseq
Read
V1
Seq
Read
V2
Seq
Read
V3
Seq
Read
V4
hwrite
haddr
hready
weim_hrdata
weim_hready
weim_bclk
Last Valid Data
V1 Word
V2 Word
V3 Word
V4 Word
weim_addr
Last Valid Addr
Address V1
weim_cs[2]
weim_r/w
Read
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_ecb
weim_data_in
V1 Word
V2 Word
V3 Word
V4 Word
Figure 27. WSC = 2, SYNC = 1, DOL = [1/ꢀ], A.WORD/E.WORD
MC9328MXL Advance Information, Rev. 5.1
42
Freescale Semiconductor
Specifications
hclk
hsel_weim_cs[2]
htrans
Idle
Seq
Nonseq
hwrite
Read
V1
Read
V2
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
weim_bclk
weim_addr
weim_cs[2]
weim_r/w
Last Valid
Address V1
Address V2
Read
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_ecb
weim_data_in
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Figure 28. WSC = 2, SYNC = 1, DOL = [1/ꢀ], A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
43
Specifications
hclk
hsel_weim_cs[2]
Non
seq
Idle
htrans
hwrite
Seq
Read
V2
Read
V1
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
weim_bclk
Last
weim_addr
weim_cs[2]
Address V1
Read
weim_r/w
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_ecb
weim_data_in
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Figure 29. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5.1
44
Freescale Semiconductor
Specifications
hclk
hsel_weim_cs[2]
htrans
Non
seq
Idle
Seq
Read
V2
hwrite
Read
V1
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
weim_bclk
weim_addr
weim_cs[2]
Last
Address V1
weim_r/w
weim_lba
Read
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_ecb
weim_data_in
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Figure 3ꢀ. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
45
Specifications
3.1ꢀ SPI Timing Diagrams
To utilize the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as
a master, two control signals are used for data transfer rate control: the SS signal (output) and the
SPI_RDY signal (input). The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2
Sample Period Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for
either SPI 1 or SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI 1
Control Register (CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS
becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as
well as to increment the data FIFO. Figure 31 through Figure 35 show the timing relationship of the master
SPI using different triggering mechanisms.
2
5
3
SS
1
4
SPIRDY
SCLK, MOSI, MISO
Figure 31. Master SPI Timing Diagram Using SPI_RDY Edge Trigger
SS
SPIRDY
SCLK, MOSI, MISO
Figure 32. Master SPI Timing Diagram Using SPI_RDY Level Trigger
SS (output)
SCLK, MOSI, MISO
Figure 33. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger
SS (input)
SCLK, MOSI, MISO
Figure 34. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT
MC9328MXL Advance Information, Rev. 5.1
46
Freescale Semiconductor
Specifications
SS (input)
6
7
SCLK, MOSI, MISO
Figure 35. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge
Table 15. Timing Parameter Table for Figure 31 through Figure 35
1.8V ꢀ.1ꢀV
3.ꢀV ꢀ.3ꢀV
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
2T 1
2T1
1
2
SPI_RDY to SS output low
–
–
–
–
ns
ns
3 • Tsclk 2
3 • Tsclk2
SS output low to first SCLK
edge
3
4
5
Last SCLK edge to SS output
high
2 • Tsclk
0
–
–
–
2 • Tsclk
0
–
–
–
ns
ns
ns
SS output high to SPI_RDY
low
SS output pulse width
Tsclk +
WAIT 3
Tsclk +
WAIT3
6
7
SS input low to first SCLK
edge
T
–
–
T
–
–
ns
ns
SS input pulse width
T
T
1. T = CSPI system clock period (PERCLK2).
2. Tsclk = Period of SCLK.
3. WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register.
3.11 LCD Controller
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD
controller with various display configurations, refer to the LCD controller chapter of the MC9328MXL
Reference Manual.
LSCLK
LD[15:0]
1
Figure 36. SCLK to LD Timing Diagram
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
47
Specifications
Table 16. LCDC SCLK Timing Parameter Table
1.8V ꢀ.1ꢀV 3.ꢀV ꢀ.3ꢀV
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
SCLK to LD valid
–
2
–
2
ns
Non-display region
T3
Display region
T1
T4
VSYN
T2
HSYN
OE
Line Y
Line 1
Line Y
LD[15:0]
T6
T7
T5
XMAX
HSYN
SCLK
OE
T8
(1,1)
(1,2)
LD[15:0]
VSYN
(1,X)
T9
T10
Figure 37. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing
Table 17. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing
Symbol
Description
Minimum
Corresponding Register Value
Unit
T1
End of OE to beginning of VSYN
T5+T6
(VWAIT1·T2)+T5+T6+T7+T9
Ts
+T7+T9
T2
T3
T4
T5
T6
HSYN period
XMAX+5
XMAX+T5+T6+T7+T9+T10
VWIDTH·(T2)
Ts
Ts
Ts
Ts
Ts
VSYN pulse width
T2
2
End of VSYN to beginning of OE
HSYN pulse width
VWAIT2·(T2)
1
HWIDTH+1
End of HSYN to beginning to T9
1
HWAIT2+1
MC9328MXL Advance Information, Rev. 5.1
48
Freescale Semiconductor
Specifications
Unit
Table 17. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
Symbol
Description
Minimum
Corresponding Register Value
T7
T8
T9
End of OE to beginning of HSYN
SCLK to valid LD data
1
-3
2
HWAIT1+1
Ts
ns
Ts
3
2
End of HSYN idle2 to VSYN edge
(for non-display region)
T9
T10
End of HSYN idle2 to VSYN edge
(for Display region)
1
1
2
1
1
2
Ts
Ts
Ts
VSYN to OE active (Sharp = 0)
when VWAIT2 = 0
T10
VSYN to OE active (Sharp = 1)
when VWAIT2 = 0
Note:
•
•
•
•
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
VSYN, HSYN and OE can be programmed as active high or active low. In Figure 37, all 3 signals are active low.
The polarity of SCLK and LD[15:0] can also be programmed.
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 37, SCLK
is always active.
•
•
For T9 non-display region, VSYN is non-active. It is used as an reference.
XMAX is defined in pixels.
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
49
Specifications
3.12 Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the
MMC/SD module (inner system) and the application (user programming).
3a
1
2
4b
3b
Bus Clock
4a
5b
5a
Valid Data
CMD_DAT Input
Valid Data
7
CMD_DAT Output
Valid Data
Valid Data
6a
6b
Figure 38. Chip-Select Read Cycle Timing Diagram
Table 18. SDHC Bus Timing Parameter Table
1.8V ꢀ.1ꢀV
3.ꢀ ꢀ.3ꢀV
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
CLK frequency at Data transfer Mode
(PP)1—10/30 cards
0
25/5
0
25/5
MHz
2
CLK frequency at Identification Mode2
Clock high time1—10/30 cards
Clock low time1—10/30 cards
Clock fall time1—10/30 cards
0
6/33
15/75
–
400
–
0
400
–
kHz
ns
3a
3b
4a
10/50
10/50
–
–
–
ns
10/50
10/50
ns
(5.00)3
4b
Clock rise time1—10/30 cards
–
14/67
(6.67)3
–
10/50
ns
5a
5b
6a
6b
7
Input hold time3—10/30 cards
Input setup time3—10/30 cards
Output hold time3—10/30 cards
Output setup time3—10/30 cards
Output delay time3
5.7/5.7
5.7/5.7
5.7/5.7
5.7/5.7
0
–
–
5/5
5/5
5/5
5/5
0
–
–
ns
ns
ns
ns
ns
–
–
–
–
16
14
1. CL ≤ 100 pF / 250 pF (10/30 cards)
2. CL ≤ 250 pF (21 cards)
3. CL ≤ 25 pF (1 card)
MC9328MXL Advance Information, Rev. 5.1
50
Freescale Semiconductor
Specifications
3.12.1 Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card
response to the host command starts after exactly NID clock cycles. For the card address assignment,
SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and
card response is NCR clock cycles as illustrated in Figure 39. The symbols for Figure 39 through Figure 43
are defined in Table 19.
Table 19. State Signal Parameters for Figure 39 through Figure 43
Card Active
Definition
Host Active
Definition
Symbol
Symbol
Z
High impedance state
Data bits
S
T
Start bit (0)
D
Transmitter bit
(Host = 1, Card = 0)
*
Repetition
P
E
One-cycle pull-up (1)
End bit (1)
CRC
Cyclic redundancy check bits (7 bits)
N
ID cycles
Host Command
CID/OCR
Content
CMD
CMD
Content
CRC
******
ST
E Z
Z S T
Z Z Z
Identification Timing
N
CR cycles
Host Command
CID/OCR
Content
******
Content
Z Z Z
CRC
ST
E Z
Z S T
SET_RCA Timing
Figure 39. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in
Figure 40, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a
period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the
responding card. The other two diagrams show the separating periods NRC and NCC
.
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
51
Specifications
NCR cycles
Host Command
Response
Content
CRC
E Z Z Z
CMD
Content
CRC
******
ST
E Z Z P
P S T
Command response timing (data transfer mode)
NRC cycles
Response
Content
Host Command
Content
CMD
******
CRC
CRC
E Z Z Z
ST
E Z
Z S T
Timing response end to next CMD start (data transfer mode)
NCC cycles
Host Command
Host Command
Content
CRC
E Z Z Z
CMD
Content
CRC
E Z
******
ST
Z S T
Timing of command sequences (all modes)
Figure 4ꢀ. Timing Diagrams at Data Transfer Mode
Figure 41 on page 53 shows basic read operation timing. In a read operation, the sequence starts with a
single block read command (which specifies the start address in the argument field). The response is sent
on the SD_CMD lines as usual. Data transmission from the card starts after the access time delay NAC
,
beginning from the last bit of the read command. If the system is in multiple block read mode, the card
sends a continuous flow of data blocks with distance NAC until the card sees a stop transmission command.
The data stops two clock cycles after the end bit of the stop command.
MC9328MXL Advance Information, Rev. 5.1
52
Freescale Semiconductor
Specifications
NCR cycles
Host Command
Response
Content
CRC
E Z
CMD
DAT
Content
CRC
******
******
ST
E Z Z P
P S T
Z****Z
*****
Z Z P
P S DDDD
Read Data
Timing of single block read
NAC cycles
NCR cycles
Host Command
Response
Content
CRC
E Z
CMD
DAT
Content
CRC
******
ST
E Z Z P
Z Z P
P S T
Z****Z
******
*****
Read Data
*****
*****
Read Data
P S DDDD
P
P S DDDD
NAC cycles
NAC cycles
Timing of multiple block read
NCR cycles
Host Command
Response
CMD
Content
CRC
******
Content
CRC
E Z
ST
E Z Z P
P S T
NST
DAT
*****
*****
DDDD
DDDD E Z Z Z
Timing of stop command
(CMD12, data transfer mode)
Valid Read Data
Figure 41. Timing Diagrams at Data Read
Figure 42 shows the basic write operation timing. As with the read operation, after the card response, the
data transfer starts after NWR cycles. The data is suffixed with CRC check bits to allow the card to check
for transmission errors. The card sends back the CRC check result as a CC status token on the data line. If
there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC
status (010) is returned. The card expects a continuous flow of data blocks if it is configured to multiple
block mode, with the flow terminated by a stop transmission command.
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
53
Specifications
Figure 42. Timing Diagrams at Data Write
MC9328MXL Advance Information, Rev. 5.1
54
Freescale Semiconductor
Specifications
The stop transmission command may occur when the card is in different states. Figure 43 shows the
different scenarios on the bus.
Figure 43. Stop Transmission During Different Scenarios
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
55
Specifications
Table 2ꢀ. Timing Values for Figure 39 through Figure 43
Symbol Minimum Maximum Unit
Parameter
Parameter
MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum
(VIL)
MMC/SD bus clock, CLK
(All values are referred to
minimum (VIH) and
maximum (VIL)
Command response cycle
Identification response cycle
Access time delay cycle
Command read cycle
NCR
NID
2
5
2
8
8
2
2
64
Clock
cycles
Command response cycle
5
Clock
cycles
Identification response
cycle
NAC
NRC
NCC
NWR
NST
TAAC + NSAC
Clock
cycles
Access time delay cycle
–
–
–
2
Clock
cycles
Command read cycle
Command-command cycle
Command write cycle
Clock
cycles
Command-command cycle
Command write cycle
Stop transmission cycle
Clock
cycles
Stop transmission cycle
Clock
cycles
TAAC: Data read access time -1 defined in CSD register bit[119:112]
NSAC: Data read access time -2 in CLK cycles (NSAC·100) defined in CSD register
bit[111:104]
TAAC: Data read access
time -1 defined in CSD
register bit[119:112]
NSAC: Data read access
time -2 in CLK cycles
(NSAC·100) defined in
CSD register bit[111:104]
3.12.2 SDIO-IRQ and ReadWait Service Handling
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the
interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data
in this mode. The memory controller generates an interrupt according to this low and the system interrupt
continues until the source is removed (SD_DAT[1] returns to its high level).
In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the "Interrupt
Period" during the data access, and the controller must sample SD_DAT[1] during this short period to
determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each
block (512 bytes).
MC9328MXL Advance Information, Rev. 5.1
56
Freescale Semiconductor
Specifications
CMD
Content
CRC
Response
******
S
ST
E Z Z P S
E Z Z Z
Z Z Z
DAT[1]
Interrupt Period
IRQ
IRQ
Block Data
Block Data
S
E
E
For 4-bit
L H
DAT[1]
Interrupt Period
For 1-bit
Figure 44. SDIO IRQ Timing Diagram
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In
this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the
clock running, and allows the user to submit commands as normal. After all commands are submitted, the
user can switch back to the data transfer operation and all counter and status values are resumed as access
continues.
CMD
******
CMD52 CRC
******
P S T
E Z Z Z
DAT[1]
Block Data
Block Data
S
S
E Z Z L H
S
E
E
For 4-bit
DAT[2]
Block Data
Block Data
E Z Z L L L L L L L L L L L L L L L L L L L L L H Z S
For 4-bit
Figure 45. SDIO ReadWait Timing Diagram
3.13 Memory Stick Host Controller
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS,
MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in
either four-state or two-state access mode.
The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according
to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet
transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1,
BS2, and BS3 states are regarded as one packet length and one communication transfer is always
completed within one packet length (in four-state access mode).
The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When
an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0
and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
57
Specifications
2
3
5
1
4
MS_SCLKI
6
8
7
MS_SCLKO
MS_BS
9
10
11
12
11
12
MS_SDIO(output)
14
13
MS_SDIO (input)
(RED bit = 0)
15
16
MS_SDIO (input)
(RED bit = 1)
Figure 46. MSHC Signal Timing Diagram
Table 21. MSHC Signal Timing Parameter Table
3.ꢀ ꢀ.3V
Ref
No.
Parameter
Unit
Minimum Maximum
1
2
MS_SCLKI frequency
–
20
20
–
25
–
MHz
ns
MS_SCLKI high pulse width
MS_SCLKI low pulse width
MS_SCLKI rise time
3
–
ns
4
3
ns
5
MS_SCLKI fall time
–
3
ns
6
MS_SCLKO frequency1
MS_SCLKO high pulse width1
MS_SCLKO low pulse width1
MS_SCLKO rise time1
MS_SCLKO fall time1
–
25
–
MHz
ns
7
20
15
–
8
–
ns
9
5
ns
10
–
5
ns
MC9328MXL Advance Information, Rev. 5.1
58
Freescale Semiconductor
Specifications
Unit
Table 21. MSHC Signal Timing Parameter Table (Continued)
3.ꢀ ꢀ.3V
Minimum Maximum
Ref
No.
Parameter
11
12
13
14
15
16
MS_BS delay time1
–
–
3
3
–
–
–
–
ns
ns
ns
ns
ns
ns
MS_SDIO output delay time1,2
MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)3
MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)3
MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1)4
MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)4
18
0
23
0
1. Loading capacitor condition is less than or equal to 30pF.
2. An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the
MS_SDIO pin, because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick
SDIO pin when the pin direction changes.
3. If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge.
4. If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
59
Specifications
3.14 Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected
clock signal is passed through a divider and a prescaler before being input to the counter. The output is
available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in
Figure 47 and the parameters are listed in Table 22.
1
2a
3b
System Clock
2b
4b
3a
4a
PWM Output
Figure 47. PWM Output Timing Diagram
Table 22. PWM Output Timing Parameter Table
1.8V 0.10V
3.ꢀV ꢀ.3ꢀV
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
System CLK frequency1
Clock high time1
Clock low time1
0
87
–
0
5/10
5/10
–
100
–
MHz
ns
2a
2b
3a
3b
4a
4b
3.3
7.5
–
–
–
ns
Clock fall time1
5
5/10
5/10
–
ns
Clock rise time1
–
6.67
–
–
ns
Output delay time1
Output setup time1
5.7
5.7
5
ns
–
5
–
ns
1. CL of PWMO = 30 pF
3.15 SDRAM Controller
A write to an address within the memory region initiates the program sequence. The first command issued
to the SyncFlash is Load Command Register. The value in A [7:0] determines which operation the
command performs. For this write setup operation, an address of 0x40 is hardware generated. The bank
and other address lines are driven with the address to be programmed. The next command is Active which
registers the row address and confirms the bank address. The third command supplies the column address,
re-confirms the bank address, and supplies the data to be written. SyncFlash does not support burst writes,
therefore a Burst Terminate command is not required.
A read to the memory region initiates the status read sequence. The first command issued to the SyncFlash
is the Load Command Register with A [7:0] set to 0x70 which corresponds to the Read Status Register
operation. The bank and other address lines are driven to the selected address. The second command is
MC9328MXL Advance Information, Rev. 5.1
60
Freescale Semiconductor
Specifications
Active which sets up the status register read. The bank and row addresses are driven during this command.
The third command of the triplet is Read. Bank and column addresses are driven on the address bus during
this command. Data is returned from memory on the low order 8 data bits following the CAS latency.
1
SDCLK
2
3S
3
CS
RAS
CAS
3H
3S
3S
3H
3S
3H
3H
4H
WE
ADDR
DQ
4S
ROW/BA
COL/BA
8
5
6
Data
7
3S
DQM
3H
Note: CKE is high during the read/write cycle.
Figure 48. SDRAM/SyncFlash Read Cycle Timing Diagram
Table 23. SDRAM Timing Parameter Table
1.8V ꢀ.1ꢀV
3.ꢀV ꢀ.3ꢀV
Ref
No.
Parameter
Unit
Minimum Maximum Minimum Maximum
1
2
SDRAM clock high-level width
SDRAM clock low-level width
SDRAM clock cycle time
2.67
6
–
–
–
–
4
4
–
–
–
–
ns
ns
ns
ns
3
11.4
3.42
10
3
3S
CS, RAS, CAS, WE, DQM setup time
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
61
Specifications
Table 23. SDRAM Timing Parameter Table (Continued)
1.8V ꢀ.1ꢀV
3.ꢀV ꢀ.3ꢀV
Ref
No.
Parameter
Unit
Minimum Maximum Minimum Maximum
3H
4S
4H
5
CS, RAS, CAS, WE, DQM hold time
Address setup time
2.28
3.42
2.28
–
–
–
2
3
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
–
2
–
SDRAM access time (CL = 3)
SDRAM access time (CL = 2)
SDRAM access time (CL = 1)
Data out hold time
6.84
6.84
22
–
6
5
–
–
6
5
–
–
22
–
6
2.85
–
–
2.5
–
7
Data out high-impedance time (CL = 3)
Data out high-impedance time (CL = 2)
Data out high-impedance time (CL = 1)
Active to read/write command period (RC = 1)
6.84
6.84
22
6
7
–
–
6
7
–
–
22
–
1
1
8
–
tRCD
tRCD
1. tRCD = SDRAM clock cycle time. This settings can be found in the MC9328MXL reference manual.
MC9328MXL Advance Information, Rev. 5.1
62
Freescale Semiconductor
Specifications
SDCLK
CS
1
3
2
RAS
CAS
6
WE
ADDR
DQ
4
5
7
/ BA
ROW/BA
COL/BA
DATA
8
9
DQM
Figure 49. SDRAM/SyncFlash Write Cycle Timing Diagram
Table 24. SDRAM Write Timing Parameter Table
1.8V ꢀ.1ꢀV
3.ꢀV ꢀ.3ꢀV
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
2
3
4
5
6
SDRAM clock high-level width
SDRAM clock low-level width
SDRAM clock cycle time
Address setup time
2.67
6
–
–
–
–
–
–
4
4
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
11.4
3.42
2.28
10
3
Address hold time
2
Precharge cycle period1
2
2
tRP
tRP
2
2
7
Active to read/write command delay
–
–
ns
tRCD
tRCD
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
63
Specifications
Table 24. SDRAM Write Timing Parameter Table (Continued)
1.8V ꢀ.1ꢀV 3.ꢀV ꢀ.3ꢀV
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
8
9
Data setup time
Data hold time
4.0
–
–
2
2
–
–
ns
ns
2.28
1. Precharge cycle timing is included in the write timing diagram.
2. tRP and tRCD = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference
manual.
SDCLK
1
3
2
CS
RAS
CAS
6
7
7
WE
ADDR
DQ
4
5
BA
ROW/BA
DQM
Figure 5ꢀ. SDRAM Refresh Timing Diagram
Table 25. SDRAM Refresh Timing Parameter Table
1.8V ꢀ.1ꢀV 3.ꢀV ꢀ.3ꢀV
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
SDRAM clock high-level width
SDRAM clock low-level width
2.67
6
–
–
4
4
–
–
ns
ns
2
MC9328MXL Advance Information, Rev. 5.1
64
Freescale Semiconductor
Specifications
Table 25. SDRAM Refresh Timing Parameter Table (Continued)
1.8V ꢀ.1ꢀV 3.ꢀV ꢀ.3ꢀV
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
3
4
5
6
SDRAM clock cycle time
Address setup time
11.4
3.42
2.28
–
–
–
–
10
3
–
–
–
–
ns
ns
ns
ns
Address hold time
2
1
1
Precharge cycle period
tRP
tRP
1
1
7
Auto precharge command period
–
–
ns
tRC
tRC
1. tRP and tRC = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference
manual.
SDCLK
CS
RAS
CAS
WE
ADDR
DQ
BA
DQM
CKE
Figure 51. SDRAM Self-Refresh Cycle Timing Diagram
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
65
Specifications
3.16 USB Device Port
Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous
transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is
identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section
covers the transfer modes and how they work from the ground up.
Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same
packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved
in the form of packets, however, because isochronous pipes are given a fixed portion of the USB
bandwidth at all times, there is no end-of-transfer.
USBD_AFE
(Output)
t VMO_ROE
4
t ROE_VPO
1
USBD_ROE
(Output)
6
3
tPERIOD
tVPO_ROE
USBD_VPO
(Output)
USBD_VMO
(Output)
tROE_VMO
tFEOPT
USBD_SUSPND
(Output)
2
5
USBD_RCV
(Input)
USBD_VP
(Input)
USBD_VM
(Input)
Figure 52. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX)
Table 26. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX)
1.8V ꢀ.1ꢀV
3.ꢀV ꢀ.3ꢀV
Ref No.
Parameter
Unit
Minimum Maximum Minimum Maximum
1
2
3
tROE_VPO; USBD_ROE active to
USBD_VPO low
83.14
81.55
83.54
83.47
81.98
83.80
83.14
81.55
83.54
83.47
81.98
83.80
ns
ns
ns
t
ROE_VMO; USBD_ROE active to
USBD_VMO high
tVPO_ROE; USBD_VPO high to
USBD_ROE deactivated
MC9328MXL Advance Information, Rev. 5.1
66
Freescale Semiconductor
Specifications
Table 26. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX)
1.8V ꢀ.1ꢀV 3.ꢀV ꢀ.3ꢀV
Minimum Maximum Minimum Maximum
Ref No.
Parameter
Unit
4
tVMO_ROE; USBD_VMO low to
248.90
249.13
248.90
249.13
ns
USBD_ROE deactivated (includes SE0)
5
6
t
t
FEOPT; SE0 interval of EOP
PERIOD; Data transfer rate
160.00
11.97
175.00
12.03
160.00
11.97
175.00
12.03
ns
Mb/s
USBD_AFE
(Output)
USBD_ROE
(Output)
USBD_VPO
(Output)
USBD_VMO
(Output)
USBD_SUSPND
(Output)
USBD_RCV
(Input)
1
tFEOPR
USBD_VP
(Input)
USBD_VM
(Input)
Figure 53. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX)
Table 27. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX)
1.8V ꢀ.1ꢀV 3.ꢀV ꢀ.3ꢀV
Ref No.
Parameter
Unit
Minimum
82
Maximum
Minimum
82
Maximum
1
tFEOPR; Receiver SE0 interval of EOP
–
–
ns
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
67
Specifications
3.17 I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
SDA
5
3
4
SCL
2
6
1
2
Figure 54. Definition of Bus Timing for I C
2
Table 28. I C Bus Timing Parameter Table
1.8V 0.10V
3.ꢀV ꢀ.3ꢀV
Ref No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
2
3
4
5
6
Hold time (repeated) START condition
Data hold time
182
0
–
171
–
160
0
–
150
–
ns
ns
ns
ns
ns
ns
Data setup time
11.4
80
10
HIGH period of the SCL clock
LOW period of the SCL clock
Setup time for STOP condition
–
120
320
160
–
480
182.4
–
–
–
–
3.18 Synchronous Serial Interface
The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode,
the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous
mode, the transmitter and receiver each have their own clock and frame synchronization signals.
Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In
gated clock mode, the clock functions only during transmission. The internal and external clock timing
diagrams are shown in Figure 56 through Figure 58 on page 70.
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is
typically used in star or ring-time division multiplex networks with other processors or codecs, allowing
interface to time division multiplexed networks without additional logic. Use of the gated clock is not
allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to
communicate with a wide variety of devices.
MC9328MXL Advance Information, Rev. 5.1
68
Freescale Semiconductor
Specifications
1
STCK Output
4
2
STFS (bl) Output
STFS (wl) Output
6
8
12
10
11
32
STXD Output
SRXD Input
31
Note: SRXD input in synchronous mode only.
Figure 55. SSI Transmitter Internal Clock Timing Diagram
1
SRCK Output
3
5
SRFS (bl) Output
SRFS (wl) Output
7
9
13
14
SRXD Input
Figure 56. SSI Receiver Internal Clock Timing Diagram
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
69
Specifications
15
16
17
STCK Input
18
20
STFS (bl) Input
STFS (wl) Input
24
22
28
27
34
26
STXD Output
SRXD Input
33
Note: SRXD Input in Synchronous mode only
Figure 57. SSI Transmitter External Clock Timing Diagram
15
16
17
SRCK Input
19
21
SRFS (bl) Input
SRFS (wl) Input
25
23
30
29
SRXD Input
Figure 58. SSI Receiver External Clock Timing Diagram
Table 29. SSI (Port C Primary Function) Timing Parameter Table
1.8V 0.10V
Minimum Maximum
Internal Clock Operation1 (Port C Primary Function2)
3.ꢀV ꢀ.3ꢀV
Ref No.
Parameter
Unit
Minimum
Maximum
1
2
3
STCK/SRCK clock period1
STCK high to STFS (bl) high3
SRCK high to SRFS (bl) high3
95
1.5
-1.2
–
83.3
1.3
–
ns
ns
ns
4.5
-1.7
3.9
-1.5
-1.1
MC9328MXL Advance Information, Rev. 5.1
70
Freescale Semiconductor
Specifications
Table 29. SSI (Port C Primary Function) Timing Parameter Table (Continued)
1.8V 0.10V 3.ꢀV ꢀ.3ꢀV
Minimum Maximum
Ref No.
Parameter
Unit
Minimum
Maximum
4
5
STCK high to STFS (bl) low3
SRCK high to SRFS (bl) low3
STCK high to STFS (wl) high3
SRCK high to SRFS (wl) high3
STCK high to STFS (wl) low3
SRCK high to SRFS (wl) low3
2.5
0.1
4.3
-0.8
2.2
0.1
3.8
-0.8
3.9
ns
ns
ns
ns
ns
ns
ns
6
1.48
-1.1
2.51
0.1
4.45
-1.5
1.3
7
-1.1
2.2
-1.5
3.8
8
4.33
-0.8
9
0.1
-0.8
13.8
10
STCK high to STXD valid from high
impedance
14.25
15.73
12.5
11a
11b
12
STCK high to STXD high
0.91
0.57
12.88
21.1
0
3.08
3.19
13.57
–
0.8
0.5
11.3
18.5
0
2.7
2.8
11.9
–
ns
ns
ns
ns
ns
STCK high to STXD low
STCK high to STXD high impedance
SRXD setup time before SRCK low
SRXD hold time after SRCK low
13
14
–
–
External Clock Operation (Port C Primary Function2)
15
16
17
18
19
20
21
22
23
24
25
26
STCK/SRCK clock period1
92.8
–
81.4
40.7
40.7
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STCK/SRCK clock high period
STCK/SRCK clock low period
STCK high to STFS (bl) high3
SRCK high to SRFS (bl) high3
STCK high to STFS (bl) low3
SRCK high to SRFS (bl) low3
STCK high to STFS (wl) high3
SRCK high to SRFS (wl) high3
STCK high to STFS (wl) low3
SRCK high to SRFS (wl) low3
27.1
–
–
61.1
–
–
–
92.8
92.8
92.8
92.8
92.8
92.8
92.8
92.8
28.16
81.4
81.4
81.4
81.4
81.4
81.4
81.4
81.4
24.7
–
0
–
0
–
0
–
0
–
–
0
0
–
0
STCK high to STXD valid from high
impedance
18.01
15.8
27a
27b
STCK high to STXD high
STCK high to STXD low
8.98
9.12
18.13
18.24
7.0
8.0
15.9
16.0
ns
ns
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
71
Specifications
Table 29. SSI (Port C Primary Function) Timing Parameter Table (Continued)
1.8V 0.10V 3.ꢀV ꢀ.3ꢀV
Ref No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
28
29
30
STCK high to STXD high impedance
SRXD setup time before SRCK low
SRXD hole time after SRCK low
18.47
1.14
0
28.5
–
16.2
1.0
0
25.0
–
ns
ns
ns
–
–
Synchronous Internal Clock Operation (Port C Primary Function2)
31
32
SRXD setup before STCK falling
SRXD hold after STCK falling
15.4
0
–
–
13.5
0
–
–
ns
ns
Synchronous External Clock Operation (Port C Primary Function2)
33
34
SRXD setup before STCK falling
SRXD hold after STCK falling
1.14
0
–
–
1.0
0
–
–
ns
ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a
non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.
2. There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad
261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they
can be viewed both at Port C primary function and Port B alternate function. When SSI signals are
configured as input, the SSI module selects the input based on status of the FMCR register bits in the
Clock controller module (CRM). By default, the input are selected from Port C primary function.
3. bl = bit length; wl = word length.
Table 3ꢀ. SSI (Port B Alternate Function) Timing Parameter Table
1.8V 0.10V
Minimum Maximum
Internal Clock Operation1 (Port B Alternate Function2)
3.ꢀV ꢀ.3ꢀV
Ref
No.
Parameter
Unit
Minimum Maximum
1
2
3
4
5
6
7
8
STCK/SRCK clock period1
STCK high to STFS (bl) high3
SRCK high to SRFS (bl) high3
STCK high to STFS (bl) low3
SRCK high to SRFS (bl) low3
STCK high to STFS (wl) high3
SRCK high to SRFS (wl) high3
STCK high to STFS (wl) low3
95
–
83.3
1.5
–
ns
ns
ns
ns
ns
ns
ns
ns
1.7
4.8
4.2
1.0
4.6
2.0
4.2
1.0
4.6
-0.1
3.08
1.25
1.71
-0.1
3.08
1.0
-0.1
2.7
5.24
2.28
4.79
1.0
1.1
1.5
-0.1
2.7
5.24
MC9328MXL Advance Information, Rev. 5.1
72
Freescale Semiconductor
Specifications
Table 3ꢀ. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
1.8V 0.10V 3.ꢀV ꢀ.3ꢀV
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
9
SRCK high to SRFS (wl) low3
1.25
2.28
1.1
2.0
ns
ns
10
STCK high to STXD valid from high
impedance
14.93
16.19
13.1
14.2
11a STCK high to STXD high
11b STCK high to STXD low
1.25
2.51
12.43
20
3.42
3.99
14.59
–
1.1
2.2
10.9
17.5
0
3.0
3.5
12.8
–
ns
ns
ns
ns
ns
12
13
14
STCK high to STXD high impedance
SRXD setup time before SRCK low
SRXD hold time after SRCK low
0
–
–
External Clock Operation (Port B Alternate Function2)
15
16
17
18
19
20
21
22
23
24
25
26
STCK/SRCK clock period1
92.8
27.1
61.1
–
–
81.4
40.7
40.7
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STCK/SRCK clock high period
STCK/SRCK clock low period
STCK high to STFS (bl) high3
SRCK high to SRFS (bl) high3
STCK high to STFS (bl) low3
SRCK high to SRFS (bl) low3
STCK high to STFS (wl) high3
SRCK high to SRFS (wl) high3
STCK high to STFS (wl) low3
SRCK high to SRFS (wl) low3
–
–
–
–
92.8
92.8
92.8
92.8
92.8
92.8
92.8
92.8
29.07
81.4
81.4
81.4
81.4
81.4
81.4
81.4
81.4
25.5
–
0
–
0
–
0
–
0
–
0
–
0
–
0
STCK high to STXD valid from high
impedance
18.9
16.6
27a STCK high to STXD high
27b STCK high to STXD low
9.23
10.60
17.90
1.14
0
20.75
21.32
29.75
–
8.1
9.3
15.7
1.0
0
18.2
18.7
26.1
–
ns
ns
ns
ns
ns
28
29
30
STCK high to STXD high impedance
SRXD setup time before SRCK low
SRXD hold time after SRCK low
–
–
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
73
Specifications
Table 3ꢀ. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
1.8V 0.10V 3.ꢀV ꢀ.3ꢀV
Minimum Maximum
Synchronous Internal Clock Operation (Port B Alternate Function2)
Ref
No.
Parameter
Unit
Minimum
Maximum
31
32
SRXD setup before STCK falling
SRXD hold after STCK falling
18.81
0
–
–
16.5
0
–
–
ns
ns
Synchronous External Clock Operation (Port B Alternate Function2)
33
34
SRXD setup before STCK falling
SRXD hold after STCK falling
1.14
0
–
–
1.0
0
–
–
ns
ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a
non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.
2. There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad
261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they
can be viewed both at Port C primary function and Port B alternate function. When SSI signals are
configured as inputs, the SSI module selects the input based on FMCR register bits in the Clock controller
module (CRM). By default, the input are selected from Port C primary function.
3. bl = bit length; wl = word length.
MC9328MXL Advance Information, Rev. 5.1
74
Freescale Semiconductor
Specifications
3.19 CMOS Sensor Interface
The CMOS Sensor Interface (CSI) module consists of a control register to configure the interface timing, a control
register for statistic data generation, a status register, interface logic, a 32 × 32 image data receive FIFO, and a
16 × 32 statistic data FIFO.
3.19.1 Gated Clock Mode
Figure 59 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the
CSI is programmed to received data on the positive edge. Figure 60 on page 76 shows the timing diagram when the
CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative
edge. The parameters for the timing diagrams are listed in Table 31 on page 76.
1
VSYNC
7
HSYNC
5
6
2
PIXCLK
Valid Data
Valid Data
Valid Data
DATA[7:0]
3
4
Figure 59. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
75
Specifications
1
VSYNC
7
HSYNC
PIXCLK
6
5
2
Valid Data
Valid Data
Valid Data
DATA[7:0]
3
4
Figure 6ꢀ. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Table 31. Gated Clock Mode Timing Parameters
Ref No.
Parameter
Min
Max
Unit
1
2
3
4
5
6
7
csi_vsync to csi_hsync
csi_hsync to csi_pixclk
csi_d setup time
180
–
–
ns
ns
1
1
–
ns
csi_d hold time
1
–
ns
csi_pixclk high time
csi_pixclk low time
csi_pixclk frequency
10.42
10.42
0
–
ns
–
ns
48
MHz
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and
setup time, according to:
Rising-edge latch data
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
MC9328MXL Advance Information, Rev. 5.1
76
Freescale Semiconductor
Specifications
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
3.19.2 Non-Gated Clock Mode
Figure 61 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the
CSI is programmed to received data on the positive edge. Figure 62 on page 78 shows the timing diagram when the
CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative
edge. The parameters for the timing diagrams are listed in Table 32 on page 78.
1
VSYNC
6
4
5
PIXCLK
Valid Data
Valid Data
Valid Data
DATA[7:0]
2
3
Figure 61. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
77
Specifications
1
VSYNC
6
4
5
PIXCLK
Valid Data
Valid Data
Valid Data
DATA[7:0]
2
3
Figure 62. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Table 32. Non-Gated Clock Mode Parameters
Ref No.
Parameter
Min
Max
Unit
1
2
3
4
5
6
csi_vsync to csi_pixclk
csi_d setup time
180
1
–
–
ns
ns
csi_d hold time
1
–
ns
csi_pixclk high time
csi_pixclk low time
csi_pixclk frequency
10.42
10.42
0
–
ns
–
ns
48
MHz
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and
setup time, according to:
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore:
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
MC9328MXL Advance Information, Rev. 5.1
78
Freescale Semiconductor
4 Pin-Out and Package Information
Table 33 illustrates the package pin assignments for the 256-pin MAPBGA package.
Table 33. MC9328MXL 256 MAPBGA Pin Assignments
1
2
3
4
5
6
7
8
9
1ꢀ
11
12
13
14
15
16
A
B
C
NVSS1
DAT3
CLK
NVSS4
USBD_
AFE
NVDD4
NVSS3
UART1_
RTS
UART1_
RXD
NVDD3
N.C.
N.C.
QVDD4
N.C.
N.C.
N.C.
A24
A23
DAT1
D31
CMD
SSI1_RXDAT
SSI1_RXCLK
USBD_
ROE
USBD_VP
SSI0_
RXCLK
SSI0_
TXCLK
SPI1_
SCLK
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
QVSS4
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DAT0
USBD_
RCV
UART2_
CTS
UART2_
RXD
SSI0_
RXFS
UART1_
TXD
D
E
F
A22
A20
A18
A15
D30
A21
D27
A17
D29
D28
D25
D24
SSI1_RXFS
D26
USBD_
SUSPND
USBD_
VPO
USBD_
VMO
SSI0_
RXDAT
SPI1_
SPI_RDY
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
CLS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DAT2
A16
USBD_VM
UART2_
RTS
SSI0_
TXDAT
SPI1_SS
A19
SSI1_
TXFS
UART2_
TXD
SSI0_
TXFS
SPI1_
MISO
REV
N.C.
N.C.
LSCLK
VSYNC
SPL_SPR
LD1
G
D23
D21
SSI1_
TXDAT
SSI1_
TXCLK
UART1_
CTS
SPI1_
MOSI
CONTRAST
OE_ACD
HSYNC
H
J
A13
A12
A10
A8
D22
A11
D16
A7
A14
D18
A9
D20
D19
D17
D15
A6
NVDD1
NVDD1
NVDD1
D14
NVDD1
NVDD1
NVSS1
NVDD1
NVSS1
NVSS1
NVSS1
NVSS1
NVSS1
RW
QVSS1
NVDD1
NVDD1
CAS
QVDD1
NVSS2
NVDD2
TCK
PS
NVSS2
NVDD2
TIN
LD0
LD6
LD2
LD7
LD4
LD8
LD5
LD11
LD9
LD3
QVDD3
TOUT2
CSI_D2
CSI_D6
QVSS3
LD15
K
L
LD10
PWMO
LD12
LD13
CSI_D0
LD14
D13
D11
CSI_MCLK
CSI_D4
CSI_D1
CSI_VSYNC
CSI_D3
CSI_D5
M
A5
D12
SDCLK
MA10
RAS
RESET_IN
BIG_ENDI
AN
CSI_
HSYNC
N
A4
EB1
D10
D7
A0
D4
PA17
D1
D3
DQM1
RESET_SF
RESET_
OUT
BOOT2
CSI_
PIXCLK
CSI_D7
TMS
TDI
P
R
A3
D9
EB0
A1
CS3
CS4
D6
D8
ECB
D5
D2
DQM3
D0
SDCKE1
DQM0
BOOT3
BOOT0
POR
TRST
I2C_CLK
TDO
I2C_DATA
QVDD2
XTAL32K
1
EB2
EB3
LBA
SDCKE0
BOOT1
EXTAL32K
BCLK
T
NVSS1
A2
OE
CS5
CS2
CS1
CS0
MA11
DQM2
SDWE
CLKO
AVDD1
TRISTATE
EXTAL16M
XTAL16M
QVSS2
1.
burst clock
Table 34 illustrates the package pin assignments for the 225-pin PBGA package.
Table 34. MC9328MXL 225 PBGA Pin Assignments
1
2
3
4
5
6
7
8
9
1ꢀ
11
12
13
14
15
A
B
C
D
E
F
CMD
SSI1_
RXCLK
SSI1_
TXCLK
USBD_
ROE
USBD_
SUSPND
USBD_VM
SSI0_
RXFS
SSI0_
TXCLK
SPI1_RDY
SPI1_
SCLK
REV
PS
LD2
LD4
LD5
DAT3
D31
A23
A21
A20
CLK
DAT0
A24
SSI1_
RXDAT
USBD_
AFE
USBD_RCV
DAT2
USBD_
VMO
SSI0_
RXDAT
UART1_
TXD
SPI1_SS
LSCLK
SPL_
SPR
LD0
LD8
LD3
LD9
LD6
LD7
NVDD2
LD13
SSI1_
RXFS
SSI1_
TXFS
USBD_
VPO
UART2_
RXD
SSI0_
TXFS
UART1_
RTS
CONTRAST VSYNC
LD12
DAT1
D30
SSI1_
TXDAT
NVDD1
NVDD1
NVDD1
USBD_VP
QVSS
QVDD4
UART2_
TXD
NVDD3
SPI1_
MOSI
HSYNC
LD1
LD11
TIN
TOUT2
CSI_D0
CSI_D2
A22
D29
D27
UART2_
RTS
UART1_
RXD
UART1_
CTS
SPI1_
MISO
OE_
ACD
LD10
LD14
CSI_
MCLK
A19
D28
NVDD1
UART2_
CTS
SSI0_
RXCLK
SSI0_
TXDAT
CLS
QVDD3
LD15
CSI_D7
CSI_D4
G
H
A17
A15
A18
A16
D26
D23
D25
D24
NVDD1
D22
NVSS
NVSS
NVDD4
NVSS
NVSS
NVSS
NVSS
NVSS
QVSS
PWMO CSI_D3
CSI_HSYNC
I2C_DATA
CSI_D5
TMS
NVDD2
CSI_D1
CSI_
CSI_
VSYNC
PIXCLK
J
A14
A13
A12
A11
D21
CS2
D20
D19
NVDD1
NVDD1
NVSS
NVSS
NVSS
QVSS
QVDD1
NVDD1
NVSS
NVSS
ECB
CSI_D6
D1
I2C_
CLK
TCK
TDI
TDO
BOOT1
BOOT0
K
BOOT2
BIG_
ENDIAN
RESET_
OUT
XTAL32K
L
A10
D16
A9
D17
D13
D18
D10
NVDD1
EB3
NVDD1
NVDD1
CS5
CS4
D2
NVSS
RW
NVSS
NVSS
POR
QVSS
XTAL16M
RESET_IN
EXTAL32K
EXTAL16M
1
M
D15
CS1
BOOT3
QVDD2
BCLK
N
P
R
A8
D14
A6
A7
A5
D12
A4
EB0
A3
D9
A2
D8
A1
D7
CS3
D6
CS0
D5
PA17
MA10
D4
D0
MA11
LBA
DQM2
DQM1
D3
DQM0
RAS
SDCKE0
SDCKE1
CAS
TRISTATE
CLKO
TRST
RESETSF
AVDD1
D11
EB1
EB2
OE
A0
SDCLK
DQM3
SDWE
1.
burst clock
Pin-Out and Package Information
4.1 MAPBGA 256 Package Dimensions
Figure 63 illustrates the 256 MAPBGA 14 mm × 14 mm × 1.30 mm package, which has 0.8 mm spacing between
the pads. The device designator for the MAPBGA package is VH.
Case Outline 1367
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS.
Figure 63. MC9328MXL 256 MAPBGA Mechanical Drawing
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
81
Pin-Out and Package Information
4.2 PBGA 225 Package Dimensions
Figure 64 illustrates the 225 PBGA 13 mm × 13 mm × 0.8 mm package.
Case Outline 13ꢀ4B
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
Figure 64. MC9328MXL 225 PBGA Mechanical Drawing
MC9328MXL Advance Information, Rev. 5.1
82
Freescale Semiconductor
NOTES
MC9328MXL Advance Information, Rev. 5.1
Freescale Semiconductor
83
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MC9328MXL/D
Rev. 5.1
11/2004
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