MCF53281CVM240J [NXP]
IC,MICROPROCESSOR,32-BIT,BGA,256PIN,PLASTIC;
| 型号： | MCF53281CVM240J |
| 厂家： | 
NXP |
| 描述： | IC,MICROPROCESSOR,32-BIT,BGA,256PIN,PLASTIC |
| 文件： | 总50页 (文件大小：600K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF5329DS
Rev. 5, 11/2008
MCF5329
MAPBGA–256
17mm x 17mm
MAPBGA–196
15mm x 15mm
MCF532x ColdFire®
Microprocessor Data Sheet
Features
• Version 3 ColdFire variable-length RISC processor core
• System debug support
• JTAG support for system level board testing
• On-chip memories
– 16-Kbyte unified write-back cache
– 32-Kbyte dual-ported SRAM on CPU internal bus,
accessible by core and non-core bus masters (e.g., DMA,
FEC, LCD controller, and USB host and OTG)
• Power management
• Liquid Crystal Display Controller (LCDC)
• Embedded Voice-over-IP (VoIP) system solution
• SDR/DDR SDRAM Controller
• Universal Serial Bus (USB) Host Controller
• Universal Serial Bus (USB) On-the-Go (OTG) controller
• Synchronous Serial Interface (SSI)
• Fast Ethernet Controller (FEC)
• Cryptography Hardware Accelerators
• FlexCAN Module
• Three Universal Asynchronous Receiver Transmitters
(UARTs)
• I2C Module
• Queued Serial Peripheral Interface (QSPI)
• Pulse Width Modulation (PWM) module
• Real Time Clock
• Four 32-bit DMA Timers
• Software Watchdog Timer
• Four Periodic Interrupt Timers (PITs)
• Phase Locked Loop (PLL)
• Interrupt Controllers (x2)
• DMA Controller
• FlexBus (External Interface)
• Chip Configuration Module (CCM)
• Reset Controller
• General Purpose I/O interface
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1
2
3
MCF532x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . .3
5.7.2 DDR SDRAM AC Timing Characteristics. . . . . 25
5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . 28
5.9 Reset and Configuration Override Timing . . . . . . . . . . 29
5.10 LCD Controller Timing Specifications . . . . . . . . . . . . . 30
5.11 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.12 ULPI Timing Specification . . . . . . . . . . . . . . . . . . . . . . 33
5.13 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 33
5.14 I2C Input/Output Timing Specifications . . . . . . . . . . . . 35
5.15 Fast Ethernet AC Timing Specifications . . . . . . . . . . . 37
5.15.1 MII Receive Signal Timing . . . . . . . . . . . . . . . . 37
5.15.2 MII Transmit Signal Timing. . . . . . . . . . . . . . . . 37
5.15.3 MII Async Inputs Signal Timing . . . . . . . . . . . . 38
5.15.4 MII Serial Management Channel Timing . . . . . 38
5.16 32-Bit Timer Module Timing Specifications . . . . . . . . . 39
5.17 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . 39
5.18 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 40
5.19 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 42
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.1 Package Dimensions—256 MAPBGA. . . . . . . . . . . . . 45
7.2 Package Dimensions—196 MAPBGA. . . . . . . . . . . . . 46
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . . .5
3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.3 Supply Voltage Sequencing and Separation Cautions . .5
3.3.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .5
3.3.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .6
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .6
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4.2 Pinout—256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .14
4.3 Pinout—196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .15
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .17
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .18
5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .19
5.6 External Interface Timing Characteristics . . . . . . . . . . .20
5.6.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.7 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.7.1 SDR SDRAM AC Timing Characteristics. . . . . .23
4
5
6
7
8
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
2
Freescale Semiconductor
MCF532x Family Comparison
USB OTG
(To/From SRAM backdoor)
FlexBus
Chip
Selects
SDRAMC
S4
S1
USB Host
LCDC
M6
M5
USB OTG
USB Host
LCDC
External
Interface
XBS
M4
M2
(To/From PADI)
SDRAMC
M1 S7 M0
S6
QSPI
Cryptography
Modules
2
I C
INTC0
INTC1
UART
RNGA
SDRAMC
SKHA
MDHA
(To/From PADI)
PWM
DMA Timer
FEC
FEC
CANRX
CANTX
SSI
2
FlexCAN
DMA Timers
QSPI
I C
UARTs
(To/From PADI)
DREQn
DMA
DACKn
D[31:0]
A[23:0]
DIV
EMAC
R/W
ULPI Interface
V3 ColdFire CPU
CS[5:0]
TA
TS
USB OTG
USB Host
(To/From PADI)
PORTS
SDRAMC
SSI
BE/BWE[3:0]
TRST
16 KByte
Cache
TCLK
TMS
TDI
JTAG
TAP
PWMs, EPORT,
Watchdog, PITs
TDO
(1024x32)x4
RESET
Reset
PLL
32 KByte
SRAM
LCDC
RTC
RCON
JTAG_EN
RSTOUT
(4096x32)x2
(To/From XBS backdoor)
Figure 1. MCF5329 Block Diagram
1
MCF532x Family Comparison
The following table compares the various device derivatives available within the MCF532x family.
Table 1. MCF532x Family Configurations
Module
MCF5327
MCF5328 MCF53281 MCF5329
ColdFire Version 3 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
•
•
•
•
Core (System) Clock
up to 240 MHz
up to 80 MHz
Peripheral and External Bus Clock
(Core clock ÷ 3)
Performance (Dhrystone/2.1 MIPS)
Unified Cache
up to 211
16 Kbytes
32 Kbytes
Static RAM (SRAM)
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
3
Ordering Information
Table 1. MCF532x Family Configurations (continued)
Module
MCF5327
MCF5328 MCF53281 MCF5329
LCD Controller
•
•
•
•
•
•
•
•
SDR/DDR SDRAM Controller
USB 2.0 Host
•
•
•
•
USB 2.0 On-the-Go
•
•
•
•
UTMI+ Low Pin Interface (ULPI)
Synchronous Serial Interface (SSI)
Fast Ethernet Controller (FEC)
Cryptography Hardware Accelerators
Embedded Voice-over-IP System Solution
FlexCAN 2.0B communication module
UARTs
—
•
•
•
•
•
•
•
—
—
—
—
3
•
•
•
•
—
—
—
3
•
—
•
•
—
•
•
3
•
3
•
I2C
QSPI
•
•
•
•
PWM Module
•
•
•
•
Real Time Clock
•
•
•
•
32-bit DMA Timers
4
•
4
•
4
•
4
•
Watchdog Timer (WDT)
Periodic Interrupt Timers (PIT)
Edge Port Module (EPORT)
Interrupt Controllers (INTC)
16-channel Direct Memory Access (DMA)
FlexBus External Interface
General Purpose I/O Module (GPIO)
JTAG - IEEE® 1149.1 Test Access Port
Package
4
•
4
•
4
•
4
•
2
•
2
•
2
•
2
•
•
•
•
•
•
•
•
•
•
•
•
•
196
256
256
256
MAPBGA
MAPBGA
MAPBGA
MAPBGA
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part
Number
Description
Package
Speed
Temperature
MCF5327CVM240
MCF5328CVM240
MCF53281CVM240
MCF5329CVM240
MCF5327 RISC Microprocessor
MCF5328 RISC Microprocessor
MCF53281 RISC Microprocessor
MCF5329 RISC Microprocessor
196 MAPBGA
256 MAPBGA
256 MAPBGA
256 MAPBGA
240 MHz
240 MHz
240 MHz
240 MHz
–40° to +85° C
–40° to +85° C
–40° to +85° C
–40° to +85° C
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
4
Freescale Semiconductor
Hardware Design Considerations
3
Hardware Design Considerations
3.1
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog V pins. The filter shown in
DD
Figure 2 should be connected between the board V and the PLLV pins. The resistor and capacitors should be placed as
DD
DD
close to the dedicated PLLV pin as possible.
DD
10 Ω
Board IVDD
PLL VDD Pin
10 µF
0.1 µF
GND
Figure 2. System PLL V Power Filter
DD
3.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 3 should be
connected between the board EV or IV and each of the USBV pins. The resistor and capacitors should be placed as
DD
DD
DD
close to the dedicated USBV pin as possible.
DD
0 Ω
Board EVDD
USB VDD Pin
10 µF
0.1 µF
GND
Figure 3. USB V Power Filter
DD
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
3.3
Supply Voltage Sequencing and Separation Cautions
The relationship between SDV and EV is non-critical during power-up and power-down sequences. SDV (2.5V or
DD
DD
DD
3.3V) and EV are specified relative to IV
.
DD
DD
3.3.1
Power Up Sequence
If EV /SDV are powered up with IV at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to
DD
DD
DD
the EV /SDV to be in a high impedance state. There is no limit on how long after EV /SDV powers up before IV
DD
DD
DD
DD
DD
must powered up. IV should not lead the EV , SDV , or PLLV by more than 0.4 V during power ramp-up or there is
DD
DD
DD
DD
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
5
Pin Assignments and Reset States
high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 500 us to avoid
turning on the internal ESD protection clamp diodes.
3.3.2
Power Down Sequence
If IV /PLLV are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
DD
DD
There is no limit on how long after IV and PLLV power down before EV or SDV must power down. IV should
DD
DD
DD
DD
DD
not lag EV , SDV , or PLLV going low by more than 0.4 V during power down or there is undesired high current in the
DD
DD
DD
ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop IV /PLLV to 0 V.
DD
DD
2. Drop EV /SDV supplies.
DD
DD
4
Pin Assignments and Reset States
4.1
Signal Multiplexing
The following table lists all the MCF532x pins grouped by function. The Dir column is the direction for the primary function
of the pin only. Refer to Section 7, “Package Information,” for package diagrams. For a more detailed discussion of the
MCF532x signals, consult the MCF5329 Reference Manual (MCF5329RM).
NOTE
In this table and throughout this document, a single signal within a group is designated
without square brackets (i.e., A23), while designations for multiple signals within a group
use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed
numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Pins that are
muxed with GPIO default to their GPIO functionality.
Table 3. MCF5327/8/9 Signal Information and Muxing
MCF53281
MCF5329
256
MCF5327
196
MAPBGA
MCF5328
256
MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
Reset
MAPBGA
RESET2
RSTOUT
—
—
—
—
—
—
I
J11
N15
P14
N15
P14
EVDD
EVDD
O
P14
Clock
EVDD
EVDD
EVDD
EVDD
SDVDD
EXTAL
XTAL2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
L14
K14
M11
N11
L1
P16
N16
P13
R13
T2
P16
N16
P13
R13
T2
O
I
EXTAL32K
XTAL32K
FB_CLK
O
O
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
6
Freescale Semiconductor
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
MCF53281
MCF5329
256
MCF5327
196
MAPBGA
MCF5328
256
MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
MAPBGA
Mode Selection
RCON2
—
—
—
—
—
—
I
I
M7
M8
M8
EVDD
EVDD
DRAMSEL
G11
H12
H12
FlexBus
SDVDD
SDVDD
A[23:22]
A[21:16]
—
—
FB_CS[5:4]
—
—
—
O
O
B11,C11
C13, D13
C13, D13
B12, A12,
D11, C12,
B13, A13
E13, A14,
B14, C14,
A15, B15
E13, A14,
B14, C14,
A15, B15
SD_BA[1:0]3
SD_A[13:11]3
—
—
O
O
A14, B14
D14, B16
D14, B16
SDVDD
SDVDD
A[15:14]
A[13:11]
—
—
C13, C14,
D12
C15, C16,
D15
C15, C16,
D15
SDVDD
SDVDD
A10
—
—
—
—
—
O
O
D13
D16
D16
A[9:0]
SD_A[9:0]3
D14,
E11–14,
F11–F14,
G14
E14–E16,
F13–F16,
G16– G14
E14–E16,
F13–F16,
G16– G14
SD_D[31:16]4
FB_D[31:17]4
—
—
I/O
I/O
H3–H1,
M1–M4,
M1–M4,
SDVDD
SDVDD
D[31:16]
D[15:1]
—
—
J4–J1, K1, N1–N4, T3, N1–N4, T3,
L4, M2, M3, P4, R4, T4, P4, R4, T4,
N1, N2, P1, N5, P5, R5, N5, P5, R5,
P2, N3
T5
T5
F4–F1,
J3–J1,
J3–J1,
G5–G2, L5, K4–K1, L2, K4–K1, L2,
N4, P4, M5, R6, N7, P7, R6, N7, P7,
N5, P5, L6 R7, T7, P8, R7, T7, P8,
R8
R8
D02
—
FB_D[16]4
—
—
I/O
O
M6
T8
T8
SDVDD
SDVDD
BE/BWE[3:0]
PBE[3:0]
SD_DQM[3:0]3
H4, P3, G1, L4, P6, L3, L4, P6, L3,
M4
N6
N6
SDVDD
SDVDD
SDVDD
SDVDD
OE
TA2
R/W
TS
PBUSCTL3
PBUSCTL2
PBUSCTL1
PBUSCTL0
—
—
—
—
—
—
O
I
P6
R9
R9
G13
N6
G13
N8
G13
N8
—
O
O
DACK0
D2
H4
H4
Chip Selects
SDVDD
SDVDD
FB_CS[5:4]
FB_CS[3:1]
PCS[5:4]
PCS[3:1]
—
—
—
O
O
—
B13, A13
B13, A13
A11, D10,
C10
A12, B12,
C12
A12, B12,
C12
SDVDD
FB_CS0
—
—
O
B10
D12
D12
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
7
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
MCF53281
MCF5329
256
MCF5327
196
MAPBGA
MCF5328
256
MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
MAPBGA
SDRAM Controller
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SD_A10
SD_CKE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
O
O
O
O
O
O
O
L2
E1
K3
K2
—
P2
H2
R1
R2
J4
P2
H2
R1
R2
J4
SD_CLK
SD_CLK
SD_CS1
SD_CS0
E2
H5
K6
L3
M1
K4
D1
H1
L1
T6
P3
R3
P1
H3
H1
L1
SD_DQS3
SD_DQS2
SD_SCAS
SD_SRAS
SD_SDR_DQS
SD_WE
T6
P3
R3
P1
H3
External Interrupts Port5
IRQ72
IRQ62
PIRQ72
PIRQ62
—
—
—
I
I
J13
—
J13
J14
J13
J14
EVDD
EVDD
USBHOST_
VBUS_EN
IRQ52
PIRQ52
USBHOST_
VBUS_OC
—
I
—
J15
J15
EVDD
IRQ42
IRQ32
IRQ22
IRQ12
PIRQ42
PIRQ32
PIRQ22
PIRQ12
SSI_MCLK
—
—
I
I
I
I
L13
M14
M13
N13
J16
K14
K15
K16
J16
K14
K15
K16
EVDD
EVDD
EVDD
EVDD
—
—
USB_CLKIN
DREQ12
SSI_CLKIN
FEC
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
FEC_MDC
FEC_MDIO
FEC_TXCLK
FEC_TXEN
FEC_TXD0
FEC_COL
PFECI2C3
PFECI2C2
PFECH7
PFECH6
PFECH5
PFECH4
PFECH3
PFECH2
PFECH1
I2C_SCL2
I2C_SDA2
—
—
—
—
—
—
—
—
—
—
O
I/O
I
—
—
—
—
—
—
—
—
—
C1
C2
A2
B2
E4
A8
C8
D8
C6
C1
C2
A2
B2
E4
A8
C8
D8
C6
—
O
O
I
ULPI_DATA0
ULPI_CLK
ULPI_NXT
ULPI_STP
ULPI_DATA4
FEC_RXCLK
FEC_RXDV
FEC_RXD0
I
I
I
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
8
Freescale Semiconductor
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
MCF53281
MCF5329
256
MCF5327
196
MAPBGA
MCF5328
256
MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
MAPBGA
EVDD
EVDD
EVDD
EVDD
EVDD
FEC_CRS
FEC_TXD[3:1]
FEC_TXER
PFECH0
ULPI_DIR
—
—
—
—
—
I
O
O
I
—
—
—
—
—
B8
D3–D1
B1
B8
D3–D1
B1
PFECL[7:5] ULPI_DATA[3:1]
PFECL4
PFECL[3:1] ULPI_DATA[7:5]
—
FEC_RXD[3:1]
FEC_RXER
E7, A6, B6 E7, A6, B6
PFECL0
—
I
D4
D4
LCD Controller
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
LCD_D17
LCD_D16
LCD_D17
LCD_D16
LCD_D15
LCD_D14
LCD_D13
LCD_D12
LCD_D[11:8]
PLCDDH1
PLCDDH0
PLCDDH1
PLCDDH0
PLCDDM7
PLCDDM6
PLCDDM5
PLCDDM4
PLCDDM[3:0]
CANTX
—
—
—
—
—
—
—
—
—
O
—
—
—
—
C9
D9
—
CANRX
—
O
O
O
O
O
O
O
O
A6
B6
C6
D6
A5
B5
C9
D9
A7
B7
C7
D7
—
—
—
A7
B7
C7
D7
—
—
—
—
C5, D5, A4, D6, E6, A5, D6, E6, A5,
B4
C4
B3
A3
A2
B5
C5
D5
A4
A3
B5
C5
D5
A4
A3
EVDD
EVDD
EVDD
EVDD
EVDD
LCD_D7
LCD_D6
PLCDDL7
PLCDDL6
PLCDDL5
PLCDDL4
PLCDDL[3:0]
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
LCD_D5
LCD_D4
LCD_D[3:0]
D4, C3, D3, B4, C4, B3, B4, C4, B3,
B2
C3
C3
EVDD
LCD_ACD/
LCD_OE
PLCDCTLH0
—
—
O
D7
B9
B9
EVDD
EVDD
EVDD
LCD_CLS
PLCDCTLL7
—
—
—
—
—
—
O
O
O
C7
B7
A7
A9
A9
LCD_CONTRAST PLCDCTLL6
D10
C10
D10
C10
LCD_FLM/
PLCDCTLL5
LCD_VSYNC
EVDD
LCD_LP/
PLCDCTLL4
—
—
O
A8
B10
B10
LCD_HSYNC
EVDD
EVDD
EVDD
EVDD
LCD_LSCLK
LCD_PS
PLCDCTLL3
PLCDCTLL2
PLCDCTLL1
—
—
—
—
—
—
—
—
O
O
O
O
B8
C8
D8
B9
A10
A11
B11
C11
A10
A11
B11
C11
LCD_REV
LCD_SPL_SPR PLCDCTLL0
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
9
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
MCF53281
MCF5329
256
MCF5327
196
MAPBGA
MCF5328
256
MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
MAPBGA
USB Host & USB On-the-Go
USB
VDD
USBOTG_M
USBOTG_P
USBHOST_M
USBHOST_P
—
—
—
—
—
—
—
—
—
—
—
—
I/O
I/O
I/O
I/O
G12
H13
K13
J12
L15
L16
L15
L16
USB
VDD
USB
VDD
M15
M16
M15
M16
USB
VDD
FlexCAN (MCF53281 & MCF5329 only)
CANRX and CANTX do not have dedicated bond pads. Please refer to the following pins for muxing:
I2C_SDA, SSI_RXD, or LCD_D16 for CANRX and I2C_SCL, SSI_TXD, or LCD_D17 for CANTX.
PWM
EVDD
EVDD
EVDD
EVDD
PWM7
PWM5
PWM3
PWM1
PPWM7
PPWM5
PPWM3
PPWM1
—
—
I/O
I/O
I/O
I/O
—
—
H13
H14
H15
H16
H13
H14
H15
H16
—
—
DT3OUT
DT2OUT
DT3IN
DT2IN
H14
J14
SSI
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
SSI_MCLK
SSI_BCLK
SSI_FS
PSSI4
PSSI3
PSSI2
PSSI1
PSSI0
PSSI1
PSSI0
—
—
PWM7
PWM5
CANRX
CANTX
—
I/O
I/O
I/O
I
—
—
—
—
—
—
—
G4
F4
G3
—
G4
F4
G3
G2
G1
—
U2CTS
U2RTS
U2RXD
U2TXD
U2RXD
U2TXD
SSI_RXD2
SSI_TXD2
SSI_RXD2
SSI_TXD2
O
—
I
G2
G1
—
O
—
I2C
I2C_SCL2
I2C_SDA2
I2C_SCL2
I2C_SDA2
PFECI2C1
PFECI2C0
PFECI2C1
PFECI2C0
CANTX
CANRX
—
U2TXD
U2RXD
U2TXD
U2RXD
I/O
I/O
I/O
I/O
—
—
—
—
F3
F2
—
—
EVDD
EVDD
EVDD
EVDD
E3
E4
F3
F2
—
DMA
DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing:
TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
10
Freescale Semiconductor
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
MCF53281
MCF5329
256
MCF5327
196
MAPBGA
MCF5328
256
MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
MAPBGA
QSPI
EVDD
EVDD
QSPI_CS2
QSPI_CS1
PQSPI5
PQSPI4
U2RTS
PWM7
—
O
O
P10
L11
T12
T13
T12
T13
USBOTG_
PU_EN
EVDD
EVDD
EVDD
EVDD
QSPI_CS0
QSPI_CLK
QSPI_DIN
PQSPI3
PQSPI2
PQSPI1
PQSPI0
PWM5
I2C_SCL2
U2CTS
—
—
—
—
O
O
I
—
P11
R12
N12
P12
P11
R12
N12
P12
N10
L10
M10
QSPI_DOUT
I2C_SDA
O
UARTs
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
U1CTS
U1RTS
U1TXD
U1RXD
U0CTS
U0RTS
U0TXD
U0RXD
PUARTL7
PUARTL6
PUARTL5
PUARTL4
PUARTL3
PUARTL2
PUARTL1
PUARTL0
SSI_BCLK
SSI_FS
SSI_TXD2
SSI_RXD2
—
—
—
—
—
—
—
—
—
I
O
O
I
C9
D9
D11
E10
E11
E12
R15
T15
T14
R14
D11
E10
E11
E12
R15
T15
T14
R14
A9
A10
P13
N12
P12
P11
I
—
O
O
I
—
—
Note: The UART2 signals are multiplexed on the QSPI, SSI, DMA Timers, and I2C pins.
DMA Timers
EVDD
EVDD
EVDD
EVDD
DT3IN
DT2IN
DT1IN
DT0IN
PTIMER3
PTIMER2
PTIMER1
PTIMER0
DT3OUT
DT2OUT
DT1OUT
DT0OUT
U2RXD
U2TXD
DACK1
DREQ02
I
I
I
I
C1
B1
A1
C2
F1
E1
E2
E3
F1
E1
E2
E3
BDM/JTAG6
JTAG_EN7
DSCLK
PSTCLK
BKPT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
L12
N14
L7
M13
P15
T9
M13
P15
T9
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
TRST2
TCLK2
TMS2
TDI2
TDO
—
O
I
M12
K12
N9
R16
N14
N11
R16
N14
N11
DSI
I
DSO
O
O
DDATA[3:0]
N7, P7, L8, N9, P9, N10, N9, P9, N10,
M8 P10 P10
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
11
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
MCF53281
MCF5329
256
MCF5327
196
MAPBGA
MCF5328
256
MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
MAPBGA
EVDD
PST[3:0]
—
—
—
O
N8, P8, L9,
M9
R10, T10,
R11, T11
R10, T10,
R11, T11
Test
TEST7
—
—
—
—
—
—
I
I
E10
—
A16
N13
A16
N13
EVDD
EVDD
PLL_TEST8
Power Supplies
EVDD
—
—
—
—
—
E6, E7,
E8, F5–F8, E8, F5–F8,
F5–F7, H9, G5, G6, H5, G5, G6, H5,
J8, J9, K8,
K9, K11
H6, J11,
K11, K12,
H6, J11,
K11, K12,
L9–L11, M9, L9–L11, M9,
M10 M10
IVDD
—
—
—
—
—
E5, K5, K10, E5, G12,M5, E5,G12, M5,
J10
M11, M12
M11, M12
PLL_VDD
SD_VDD
—
—
—
—
—
—
—
—
—
—
H10
J12
J12
E8, E9,
F8–F10,
J5–J7, K7
E9, F9–F11, E9, F9–F11,
G11, H11,
J5, J6, K5,
G11, H11,
J5, J6, K5,
K6, L5–L8, K6, L5–L8,
M6, M7
M6, M7
USB_VDD
VSS
—
—
—
—
—
—
—
—
—
—
G10
L14
L14
G6–G9,
H6–H8, P9
G7–G10,
H7–H10,
J7–10,
G7–G10,
H7–H10,
J7–10,
K7–K10,
L12, L13
K7–K10,
L12, L13
PLL_VSS
USB_VSS
—
—
—
—
—
—
—
—
—
—
H11
H12
K13
M14
K13
M14
1
2
3
Refers to pin’s primary function.
Pull-up enabled internally on this signal for this mode.
The SDRAM functions of these signals are not programmable by the user. They are dynamically switched by the processor
when accessing SDRAM memory space and are included here for completeness.
4
5
6
Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating
the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.
GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate
functions.
If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for
assigning these pins.
7
8
Pull-down enabled internally on this signal for this mode.
Must be left floating for proper operation of the PLL.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
12
Freescale Semiconductor
Pin Assignments and Reset States
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
13
Pin Assignments and Reset States
NOTE
4.2
Pinout—256 MAPBGA
Figure 4 shows a pinout of the MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 devices.
NOTE
The pin at location N13 (PLL_TEST) must be left floating or improper operation of the
PLL module occurs.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FEC_
LCD_
D4
LCD_
D5
LCD_
D9
FEC_
RXD2
LCD_
D15
FEC_
COL
LCD_
CLS
LCD_
LCD_
PS
FB_CS3 FB_CS4
FB_CS2 FB_CS5
A
B
C
D
E
F
NC
A20
A17
TEST
A
B
C
D
E
F
TXCLK
LSCLK
FEC_
TXER
FEC_
TXEN
LCD_
D1
LCD_
D3
LCD_
D8
FEC_
RXD1
LCD_
D14
FEC_
CRS
LCD_
LCD_LP/
LCD_
REV
A19
A18
A15
A9
A16
A13
A11
A8
A14
A12
A10
A7
ACD/OE HSYNC
FEC_
MDC
FEC_
MDIO
LCD_
D0
LCD_
D2
LCD_
D7
FEC_
RXD0
LCD_
D13
FEC_
LCD_ LCD_FLM/
LCD_
FB_CS1
FB_CS0
U1RXD
NC
A23
A22
A21
A6
RXCLK
D17
VSYNC
SPL_SPR
FEC_
TXD1
FEC_
TXD2
FEC_
TXD3
FEC_
RXER
LCD_
D6
LCD_
D11
LCD_
D12
FEC_
RXDV
LCD_ LCD_CON
U1CTS
U1TXD
D16
TRAST
U1RTS
FEC_
TXD0
LCD_
D10
FEC_
RXD3
DT2IN
DT3IN
DT1IN
DT0IN
IVDD
EVDD
EVDD
EVDD
EVDD SD_VDD
I2C_
SDA
I2C_
SCL
SSI_
EVDD
EVDD
EVDD
EVDD
VSS
EVDD SD_VDD SD_VDD SD_VDD
A5
A4
A3
BCLK
SSI_
RXD
SSI_
SSI_
TXD
TA
G
H
SSI_FS
SD_WE
VSS
VSS
VSS
VSS
VSS
VSS
SD_VDD
SD_VDD
IVDD
A0
A1
A2
G
H
MCLK
DRAM
SEL
SD_
CS0
TS
SD_CKE
VSS
PWM7
IRQ7
PWM5
PWM3
IRQ5
PWM1
IRQ4
PLL_
VDD
D15
D11
SD_CS1
D12
IRQ6
IRQ3
J
K
L
D13
D9
D14
D10
D8
SD_VDD SD_VDD
SD_VDD SD_VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
EVDD
EVDD
EVDD
J
K
L
PLL_
VSS
IRQ2
USB
IRQ1
USB
EVDD
VSS
SD_
USB_
VSS
USBOTG
_VDD
BE/
BWE1
BE/
BWE3
SD_VDD SD_VDD SD_VDD SD_VDD EVDD
EVDD
DQS3
OTG_M OTG_P
JTAG_ USBHOST
USB
USB
RCON
R/W
D2
M
N
P
R
T
D31
D27
D30
D26
D29
D25
D28
D24
D22
D21
IVDD SD_VDD SD_VDD
BE/
EVDD
EVDD
IVDD
IVDD
M
N
P
R
T
EN
_VSS
HOST_M HOST_P
TDO/
DSO
QSPI_
DIN
PLL_
TEST
TDI/DSI
RESET
D19
D18
D17
D6
D5
D4
DDATA3 DDATA1
DDATA2 DDATA0
XTAL
BWE0
SD_DR
_DQS
QSPI_
CS0
QSPI_
DOUT
EXTAL
32K
BE/
BWE2
TRST/
DSCLK
SD_A10 SD_CAS
SD_CLK SD_RAS
RSTOUT
U0RXD
EXTAL
QSPI_
CLK
XTAL
32K
TMS/
BKPT
OE
PST3
U0CTS
SD_CLK
D7
D1
PST1
SD_
TCLK/
QSPI_
CS2
QSPI_
CS1
U0RTS
15
NC
1
FB_CLK
2
D23
3
D20
4
D16
5
D3
7
D0
8
PST2
10
PST0
11
U0TXD
14
NC
16
DQS2
PSTCLK
6
9
12
13
Figure 4. MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 Pinout Top View (256 MAPBGA)
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
14
Freescale Semiconductor
Electrical Characteristics
4.3
Pinout—196 MAPBGA
The pinout for the MCF5327CVM240 package is shown below.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
F
A
B
C
D
E
F
LCD_
D4
LCD_
D5
LCD_
D9
LCD_
D13
LCD_ LCD_FLM/ LCD_LP/
D17 VSYNC HSYNC
DT1IN
U1TXD
U1RXD FB_CS3
A20
A16
A15
LCD_
D0
LCD_
D6
LCD_
D8
LCD_
D12
LCD_ LCD_CON LCD_
LCD_
D2TIN
DT3IN
FB_CS0
FB_CS1
FB_CS2
TEST
A23
A22
A19
A8
A21
A18
A11
A7
A17
A13
A10
A6
A14
A12
D16
TRAST
LSCLK SPL_SPR
LCD_
D2
LCD_
D7
LCD_
D11
LCD_
D15
LCD_
CLS
LCD_
U1CTS
PS
DT0IN
TS
LCD_
D1
LCD_
D3
LCD_
D10
LCD_
D14
LCD_
ACD/OE
LCD_
U1RTS
REV
SD_WE
A9
SD_CKE SD_CS0 I2C_SCL I2C_SDA
IVDD
EVDD
D11
EVDD
EVDD
VSS
EVDD
EVDD
VSS
SD_VDD SD_VDD
A5
D12
D13
D8
D14
D9
D15
D10
SD_VDD SD_VDD SD_VDD
USB
A4
A3
A2
A1
G
H
J
G
H
J
BE/
BWE1
DRAM
SEL
USB
OTG_M
VSS
VSS
EVDD
EVDD
EVDD
PST1
PST0
TA
A0
OTG_VDD
BE/
BWE3
SD_
DQS3
PLL_
VDD
PLL_ USBHOST
VSS
USB
OTG_P
D29
D25
D24
D30
D26
D31
D27
VSS
VSS
VSS
PWM3
PWM1
XTAL
EXTAL
IRQ3
_VSS
USB
HOST_P
D28
SD_VDD SD_VDD SD_VDD
EVDD
EVDD
DDATA1
DDATA0
PST3
IVDD
IVDD
RESET
IRQ7
K
L
K
L
SD_DR_
DQS
SD_
USB
HOST_M
SD_CLK SD_CLK
IVDD
D7
SD_VDD
EVDD
TDI/DSI
DQS2
D1
TCLK/
PSTCLK
QSPI_
DIN
QSPI_
CS1
JTAG_
EN
FB_CLK SD_A10 SD_CAS
D23
IRQ4
IRQ2
IRQ1
M
N
P
M
N
P
BE/
BWE0
QSPI_
DOUT
EXTAL
32K
TMS/
BKPT
SD_RAS
D20
D22
D19
D21
D16
D4
D0
RCON
TDO/
DSO
QSPI_
CLK
XTAL
32K
TRST/
DSCLK
D6
D3
R/W
DDATA3
U0RTS
BE/
BWE2
QSPI_
CS2
D18
1
D17
2
D5
4
D2
5
OE
6
DDATA2
7
PST2
8
VSS
9
U0RXD
11
U0TXD
12
U0CTS RSTOUT
3
10
13
14
Figure 5. MCF5327CVM240 Pinout Top View (196 MAPBGA)
5
Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF5329 microcontroller unit.
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications of MCF5329.
The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not
be fully tested or guaranteed at this early stage of the product life cycle. However, for production silicon, these specifications
will be met. Finalized specifications will be published after complete characterization and device qualifications have been
completed.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
15
Electrical Characteristics
NOTE
The parameters specified in this MCU document supersede any values found in the module
specifications.
5.1
Maximum Ratings
1, 2
Table 4. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Core Supply Voltage
IVDD
EVDD
SDVDD
PLLVDD
VIN
– 0.5 to +2.0
– 0.3 to +4.0
– 0.3 to +4.0
– 0.3 to +2.0
– 0.3 to +3.6
V
V
V
V
V
CMOS Pad Supply Voltage
DDR/Memory Pad Supply Voltage
PLL Supply Voltage
Digital Input Voltage 3
Instantaneous Maximum Current
ID
25
mA
Single pin limit (applies to all pins) 3, 4, 5
Operating Temperature Range (Packaged)
TA
(TL - TH)
– 40 to +85
°C
°C
Storage Temperature Range
Tstg
– 55 to +150
1
2
Functional operating conditions are given in Section 5.4, “DC Electrical Specifications.”
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is
not guaranteed. Continued operation at these levels may affect device reliability or cause
permanent damage to the device.
This device contains circuitry protecting against damage due to high static voltage or electrical
fields; however, it is advised that normal precautions be taken to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate logic voltage level (VSS or
EVDD).
3
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages,
and then use the larger of the two values.
4
5
All functional non-supply pins are internally clamped to VSS and EVDD
.
Power supply must maintain regulation within operating EVDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > EVDD) is greater than
IDD, the injection current may flow out of EVDD and could result in external power supply going
out of regulation. Ensure external EVDD load shunts current greater than maximum injection
current. This is the greatest risk when the MCU is not consuming power (ex; no clock). Power
supply must maintain regulation within operating EVDD range during instantaneous and
operating maximum current conditions.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
16
Freescale Semiconductor
Electrical Characteristics
5.2
Thermal Characteristics
Table 5. Thermal Characteristics
Characteristic
Symbol
256MBGA 196MBGA Unit
Junction to ambient, natural convection
Four layer board
(2s2p)
θJMA
371,2
421,2
°C/W
°C/W
Junction to ambient (@200 ft/min)
Four layer board
(2s2p)
θJMA
341,2
381,2
Junction to board
—
—
—
—
θJB
θJC
Ψjt
Tj
273
164
41,5
105
323
194
51,5
105
°C/W
°C/W
°C/W
oC
Junction to case
Junction to top of package
Maximum operating junction temperature
1
θ
JMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.
Freescale recommends the use of θJmA and power dissipation specifications in the system design to prevent
device junction temperatures from exceeding the rated specification. System designers should be aware that
device junction temperatures can be significantly influenced by board layout and surrounding devices.
Conformance to the device junction temperature specification can be verified by physical measurement in the
customer’s system using the Ψjt parameter, the device power dissipation, and the method described in
EIA/JESD Standard 51-2.
2
3
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8.
Board temperature is measured on the top surface of the board near the package.
4
5
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written in conformance with Psi-JT.
The average chip-junction temperature (T ) in °C can be obtained from:
J
TJ = TA + (PD × ΘJMA
)
Eqn. 1
Where:
TA
= Ambient Temperature, °C
QJMA
PD
= Package Thermal Resistance, Junction-to-Ambient, °C/W
= PINT + PI/O
PINT
PI/O
= IDD × IVDD, Watts - Chip Internal Power
= Power Dissipation on Input and Output Pins — User Determined
For most applications P < P
and can be ignored. An approximate relationship between P and T (if P is neglected) is:
D J I/O
I/O
INT
K
--------------------------------
PD
=
Eqn. 2
(TJ + 273°C)
Solving equations 1 and 2 for K gives:
K = PD × (TA × 273°C) + QJMA × P2D
Eqn. 3
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
17
Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively
A
D
J
for any value of T .
A
5.3
ESD Protection
1, 2
Table 6. ESD Protection Characteristics
Characteristics
Symbol
Value
Units
ESD Target for Human Body Model
HBM
2000
V
1
2
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive
Grade Integrated Circuits.
A device is defined as a failure if after exposure to ESD pulses the device no longer meets
the device specification requirements. Complete DC parametric and functional testing is
performed per applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
5.4
DC Electrical Specifications
Table 7. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Unit
Core Supply Voltage
IVDD
PLLVDD
EVDD
1.4
1.4
3.0
1.6
1.6
3.6
V
V
V
V
PLL Supply Voltage
CMOS Pad Supply Voltage
SDRAM and FlexBus Supply Voltage
SDVDD
Mobile DDR/Bus Pad Supply Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
1.70
2.25
3.0
1.95
2.75
3.6
USB Supply Voltage
USBVDD
EVIH
3.0
2
3.6
EVDD + 0.3
0.8
V
V
V
V
CMOS Input High Voltage
CMOS Input Low Voltage
EVIL
VSS – 0.3
EVDD – 0.4
CMOS Output High Voltage
IOH = –5.0 mA
EVOH
—
CMOS Output Low Voltage
EVOL
—
0.4
V
V
IOL = 5.0 mA
SDRAM and FlexBus Input High Voltage
SDVIH
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
1.35
1.7
2
SDVDD + 0.3
SDVDD + 0.3
SDVDD + 0.3
SDRAM and FlexBus Input Low Voltage
SDVIL
V
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
VSS – 0.3
VSS – 0.3
VSS – 0.3
0.45
0.8
0.8
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
18
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
SDRAM and FlexBus Output High Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
IOH = –5.0 mA for all modes
SDVOH
V
SDVDD – 0.35
—
—
—
2.1
2.4
SDRAM and FlexBus Output Low Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
IOL = 5.0 mA for all modes
SDVOL
V
—
—
—
0.3
0.3
0.5
Input Leakage Current
Iin
−1.0
−10
1.0
μA
Vin = VDD or VSS, Input-only pins
Weak Internal Pull-Up Device Current, tested at VIL Max.1
IAPU
Cin
−130
μA
Input Capacitance 2
pF
All input-only pins
All input/output (three-state) pins
—
—
7
7
1
Refer to the signals section for pins having weak internal pull-up devices.
This parameter is characterized before qualification rather than 100% tested.
2
5.5
Oscillator and PLL Electrical Characteristics
Table 8. PLL Electrical Characteristics
Min.
Value
Max.
Value
Num
Characteristic
Symbol
Unit
PLL Reference Frequency Range
Crystal reference
1
fref_crystal
fref_ext
12
12
251
401
MHz
MHz
External reference
Core frequency
fsys
fsys/3
488 x 10−6
163 x 10−6
240
80
MHz
MHz
2
3
CLKOUT Frequency2
Crystal Start-up Time3, 4
tcst
—
10
ms
EXTAL Input High Voltage
Crystal Mode5
4
5
VIHEXT
VIHEXT
VXTAL + 0.4
EVDD/2 + 0.4
—
—
V
V
All other modes (External, Limp)
EXTAL Input Low Voltage
Crystal Mode5
VILEXT
VILEXT
—
—
VXTAL – 0.4
EVDD/2 – 0.4
V
V
All other modes (External, Limp)
7
8
PLL Lock Time 3, 6
tlpll
tdc
—
40
1
50000
60
CLKIN
%
Duty Cycle of reference 3
9
XTAL Current
IXTAL
3
mA
pF
10
11
Total on-chip stray capacitance on XTAL
Total on-chip stray capacitance on EXTAL
CS_XTAL
CS_EXTAL
1.5
1.5
pF
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
19
Electrical Characteristics
Table 8. PLL Electrical Characteristics (continued)
Min.
Max.
Value
Num
Characteristic
Symbol
Unit
Value
Crystal capacitive load
CL
See crystal
spec
12
13
Discrete load capacitance for XTAL
Discrete load capacitance for EXTAL
CL_XTAL
CL_EXTAL
Cjitter
2*CL –
pF
pF
CS_XTAL
CPCB_XTAL
–
7
2*CL–-
14
17
CS_EXTAL –
7
CPCB_EXTAL
CLKOUT Period Jitter, 3, 4, 7, 8, 9 Measured at fSYS Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
—
—
10
TBD
% fsys/3
% fsys/3
Frequency Modulation Range Limit 3, 10, 11
(fsysMax must not be exceeded)
Cmod
fvco
0.8
2.2
%fsys/3
18
19
VCO Frequency. fvco = (fref * PFD)/4
350
540
MHz
1
The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock
frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.
2
3
4
5
6
7
8
All internal registers retain data at 0 Hz.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
This parameter is guaranteed by design rather than 100% tested.
This specification is the PLL lock time only and does not include oscillator start-up time.
CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
.
Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
9
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.
10 Modulation percentage applies over an interval of 10 μs, or equivalently the modulation rate is 100 KHz.
11
Modulation range determined by hardware design.
5.6
External Interface Timing Characteristics
Table 9 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and output delay with
respect to the rising edge of a reference clock. The reference clock is the FB_CLK output.
All other timing relationships can be derived from these values. Timings listed in Table 9
are shown in Figure 7 and Figure 8.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
20
Freescale Semiconductor
Electrical Characteristics
* The timings are also valid for inputs sampled on the negative clock edge.
1.5V
FB_CLK (80MHz)
TSETUP
THOLD
Invalid
1.5V Valid 1.5V
Invalid
Input Setup And Hold
Input Rise Time
trise
Vh = VIH
Vl = VIL
tfall
Vh = VIH
Vl = VIL
Input Fall Time
FB_CLK
Inputs
B4
B5
Figure 6. General Input Timing Requirements
5.6.1
FlexBus
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up
to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external
boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose
chip-selects (FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces.
Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or
longword (32 bits) wide. Control signal timing is compatible with common ROM/flash memories.
5.6.1.1
FlexBus AC Timing Characteristics
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock.
Table 9. FlexBus AC Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
—
Frequency of Operation
fsys/3
—
80
—
Mhz
ns
FB1 Clock Period (FB_CLK)
tFBCK ( cyc)
tFBCHDCV
tFBCHDCI
t
12.5
Address, Data, and Control Output Valid (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)1
FB2
FB3
—
1
7.0
—
ns
ns
Address, Data, and Control Output Hold (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)1, 2
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
21
Electrical Characteristics
Num
Table 9. FlexBus AC Timing Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
FB4 Data Input Setup
FB5 Data Input Hold
tDVFBCH
tDIFBCH
tCVFBCH
tCIFBCH
3.5
0
—
—
—
—
ns
ns
ns
ns
FB6 Transfer Acknowledge (TA) Input Setup
FB7 Transfer Acknowledge (TA) Input Hold
4
0
1
2
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2, “DDR SDRAM AC
Timing Characteristics” for SD_CS[3:0] timing.
The FlexBus supports programming an extension of the address hold. Please consult the Reference Manual
for more information.
NOTE
The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM
controller. At the end of the read and write bus cycles the address signals are
indeterminate.
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[23:0]
FB_A[23:0]
FB2
FB5
FB_D[31:X]
ADDR[31:X]
DATA
FB4
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB6
FB7
FB_TA
Figure 7. FlexBus Read Timing
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
22
Freescale Semiconductor
Electrical Characteristics
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[23:0]
FB_A[23:0]
FB2
ADDR[31:X]
FB_D[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB6
FB7
FB_TA
Figure 8. FlexBus Write Timing
5.7
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or
double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.1
SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock,
when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller is a
DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must remain supplied to the device
for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during read
cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.
Table 10. SDR Timing Specifications
Symbol
Characteristic
Frequency of Operation1
Symbol
Min
Max
Unit
•
•
60
80
MHz
ns
SD1 Clock Period2
tSDCK
tSDCKH
tSDCKH
12.5
0.45
0.45
16.67
0.55
0.55
SD3 Pulse Width High3
SD4 Pulse Width Low4
SD_CLK
SD_CLK
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Valid
0.5 × SD_CLK
SD5
tSDCHACV
—
ns
+ 1.0
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Hold
SD6
tSDCHACI
tDQSOV
2.0
—
—
ns
ns
ns
SD7 SD_SDR_DQS Output Valid5
Self timed
SD_DQS[3:0] input setup relative to SD_CLK6
SD8
0.25 ×
SD_CLK
tDQVSDCH
0.40 × SD_CLK
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
23
Electrical Characteristics
Symbol
Table 10. SDR Timing Specifications (continued)
Characteristic Symbol Min
Max
Unit
SD9 SD_DQS[3:2] input hold relative to SD_CLK7
tDQISDCH Does not apply. 0.5×SD_CLK fixed width.
0.25 ×
Data (D[31:0]) Input Setup relative to SD_CLK (reference
SD10
only)8
tDVSDCH
tDISDCH
tSDCHDMV
tSDCHDMI
—
ns
ns
ns
ns
SD_CLK
SD11 Data Input Hold relative to SD_CLK (reference only)
1.0
—
Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid
SD12
0.75 × SD_CLK
+ 0.5
—
SD13 Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold
1.5
—
1
The FlexBus and SDRAM clock operates at the same frequency of the internal bus clock. See the PLL chapter of the MCF5329
Reference Manual for more information on setting the SDRAM clock rate.
2
3
4
5
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation
from this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat.
6
7
8
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge
does not affect the memory controller.
Because a read cycle in SDR mode uses the DQS circuit within the device, it is most critical that the data valid window be
centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup
spec is provided as guidance.
SD2
SD1
SD_CLK
SD3
SD5
SD_CSn
SD_RAS
SD_CAS
SD_WE
CMD
ROW
SD4
A[23:0]
SD_BA[1:0]
COL
SD11
SDDM
D[31:0]
SD12
WD1
WD2
WD3
WD4
Figure 9. SDR Write Timing
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
24
Freescale Semiconductor
Electrical Characteristics
SD2
SD1
SD_CLK
SD5
SD_CSn,
SD_RAS,
SD_CAS,
SD_WE
SD3
CMD
ROW
3/4 MCLK
Reference
SD4
A[23:0],
SD_BA[1:0]
COL
tDQS
SDDM
SD6
SD_SDR_DQS (Measured at Output Pin)
SD_DQS[3:2] (Measured at Input Pin)
Board Delay
SD8
Board Delay
SD7
Delayed
SD_CLK
SD9
D[31:0]
from
WD1
WD2
WD3
WD4
Memories
NOTE: Data driven from memories relative
to delayed memory clock.
SD10
Figure 10. SDR Read Timing
5.7.2
DDR SDRAM AC Timing Characteristics
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive
data onto the memory bus. All timing numbers are relative to the four DQS byte lanes.
Table 11. DDR Timing Specifications
Num
Characteristic
Frequency of Operation
Symbol
Min
Max
Unit
•
tDDCK
tDDSK
tDDCKH
tDDCKL
60
80
Mhz
ns
DD1 Clock Period1
12.5
0.45
0.45
16.67
0.55
0.55
DD2 Pulse Width High2
DD3 Pulse Width Low3
SD_CLK
SD_CLK
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid3
0.5 × SD_CLK
DD4
DD5
tSDCHACV
—
ns
+ 1.0
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
tSDCHACI
tCMDVDQ
tDQDMV
2.0
—
—
1.25
—
ns
SD_CLK
ns
DD6 Write Command to first DQS Latching Transition
Data and Data Mask Output Setup (DQ-->DQS) Relative
DD7
1.5
to DQS (DDR Write Mode)4, 5
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
25
Electrical Characteristics
Num
Table 11. DDR Timing Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
Data and Data Mask Output Hold (DQS-->DQ) Relative to
DQS (DDR Write Mode)6
tDQDMI
1.0
—
ns
DD8
DD9 Input Data Skew Relative to DQS (Input Setup)7
tDVDQ
tDIDQ
—
1
ns
ns
Input Data Hold Relative to DQS8
DD10
0.25 × SD_CLK
—
+ 0.5ns
DD11 DQS falling edge from SDCLK rising (output hold time)
DD12 DQS input read preamble width
tDQLSDCH
tDQRPRE
tDQRPST
tDQWPRE
tDQWPST
0.5
0.9
—
ns
1.1
0.6
SD_CLK
SD_CLK
SD_CLK
SD_CLK
DD13 DQS input read postamble width
DD14 DQS output write preamble width
DD15 DQS output write postamble width
SD_CLK is one SDRAM clock in (ns).
0.4
0.25
0.4
0.6
1
2
3
Pulse width high plus pulse width low cannot exceed min and max clock period.
Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature,
and voltage variations.
4
This specification relates to the required input setup time of today’s DDR memories. The processor’s output setup should be
larger than the input setup of the DDR memories. If it is not larger, the input setup on the memory is in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].
5
6
The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are
valid for each subsequent DQS edge.
This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative
MEM_DQS[0].
7
8
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other
factors).
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line
becomes invalid.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
26
Freescale Semiconductor
Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
ROW
DD4
DD6
A[13:0]
COL
DD7
DM3/DM2
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
DD8
DD7
WD1 WD2 WD3 WD4
DD8
Figure 11. DDR Write Timing
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
27
Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
CL=2
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
ROW
DD4
CL=2.5
A[13:0]
COL
DD9
DQS Read
Postamble
DQS Read
Preamble
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
DD10
WD1 WD2 WD3 WD4
DQS Read
Preamble
DQS Read
Postamble
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
Figure 12. DDR Read Timing
5.8
General Purpose I/O Timing
1
Table 12. GPIO Timing
Num
Characteristic
Symbol
Min
Max
Unit
G1
G2
G3
G4
FB_CLK High to GPIO Output Valid
FB_CLK High to GPIO Output Invalid
GPIO Input Valid to FB_CLK High
FB_CLK High to GPIO Input Invalid
tCHPOV
tCHPOI
tPVCH
tCHPI
—
1.5
9
10
—
—
—
ns
ns
ns
ns
1.5
1
GPIO pins include: IRQn, PWM, UART, FlexCAN, and Timer pins.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
28
Freescale Semiconductor
Electrical Characteristics
FB_CLK
G2
G1
GPIO Outputs
G3
G4
GPIO Inputs
Figure 13. GPIO Timing
5.9
Reset and Configuration Override Timing
Table 13. Reset and Configuration Override Timing
Num
Characteristic
Symbol
Min
Max
Unit
R1 RESET Input valid to FB_CLK High
tRVCH
tCHRI
9
1.5
5
—
—
—
10
—
—
—
1
ns
ns
R2 FB_CLK High to RESET Input invalid
R3 RESET Input valid Time 1
tRIVT
tCYC
ns
R4 FB_CLK High to RSTOUT Valid
tCHROV
tROVCV
tCOS
—
0
R5 RSTOUT valid to Config. Overrides valid
R6 Configuration Override Setup Time to RSTOUT invalid
R7 Configuration Override Hold Time after RSTOUT invalid
R8 RSTOUT invalid to Configuration Override High Impedance
ns
20
0
tCYC
ns
tCOH
tROICZ
—
tCYC
1
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to
the system. Thus, RESET must be held a minimum of 100 ns.
FB_CLK
R1
R2
R3
RESET
R4
R4
RSTOUT
R8
R5
R6
R7
Configuration Overrides*:
(RCON, Override pins])
Figure 14. RESET and Configuration Override Timing
NOTE
Refer to the CCM chapter of the MCF5329 Reference Manual for more information.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
29
Electrical Characteristics
5.10 LCD Controller Timing Specifications
This sections lists the timing specifications for the LCD Controller.
Table 14. LCD_LSCLK Timing
Num
Parameter
Minimum Maximum
Unit
T1
T2
T3
LCD_LSCLK Period
Pixel data setup time
Pixel data up time
25
11
11
2000
—
ns
ns
ns
—
Note: The pixel clock is equal to LCD_LSCLK / (PCD + 1). When it is in CSTN, TFT or monochrome mode with
bus width is set and LCD_LSCLK is equal to the pixel clock. When it is in monochrome with other bus
width settings, LCD_LSCLK is equal to the pixel clock divided by bus width. The polarity of LCD_LSCLK
and LCD_LD signals can also be programmed.
T1
LCD_LSCLK
LCD_LD[17:0]
T2
T3
Figure 15. LCD_LSCLK to LCD_LD[17:0] timing diagram
Non-display region
Display region
T3
T1
T4
LCD_VSYNC
LCD_HSYNC
LCD_OE
T2
Line Y
Line 1
Line Y
LCD_LD[17:0]
T5
T6
XMAX
T7
LCD_HSYNC
LCD_LSCLK
LCD_OE
(1,1)
(1,2)
LCD_LD[15:0]
(1,X)
Figure 16. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
30
Freescale Semiconductor
Electrical Characteristics
Table 15. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
Number
Description
Minimum
Value
Unit
T1
T2
T3
T4
T5
T6
T7
End of LCD_OE to beginning of LCD_VSYNC
LCD_HSYNC period
T5+T6+T7-1
(VWAIT1·T2)+T5+T6+T7-1
XMAX+T5+T6+T7
VWIDTH·T2
Ts
Ts
Ts
Ts
Ts
Ts
Ts
—
T2
1
LCD_VSYNC pulse width
End of LCD_VSYNC to beginning of LCD_OE
LCD_HSYNC pulse width
(VWAIT2·T2)+1
HWIDTH+1
1
End of LCD_HSYNC to beginning to LCD_OE
End of LCD_OE to beginning of LCD_HSYNC
3
HWAIT2+3
1
HWAIT1+1
Note: Ts is the LCD_LSCLK period. LCD_VSYNC, LCD_HSYNC and LCD_OE can be programmed as active high or active
low. In Figure 16, all 3 signals are active low. LCD_LSCLK can be programmed to be deactivated during the
LCD_VSYNC pulse or the LCD_OE deasserted period. In Figure 16, LCD_LSCLK is always active.
Note: XMAX is defined in number of pixels in one line.
XMAX
LCD_LSCLK
LCD_LD
LCD_SPL_SPR
LCD_HSYNC
D1
D2
D320
D320
T1
T3
T2
T2
T4
T4
LCD_CLS
LCD_PS
T5
T6
T7
T7
LCD_REV
Figure 17. Sharp TFT Panel Timing
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
31
Electrical Characteristics
Num
Table 16. Sharp TFT Panel Timing
Description
Minimum
Value
Unit
T1
T2
T3
T4
T5
T6
T7
LCD_SPL/LCD_SPR pulse width
—
1
1
Ts
Ts
Ts
Ts
Ts
Ts
Ts
End of LCD_LD of line to beginning of LCD_HSYNC
End of LCD_HSYNC to beginning of LCD_LD of line
LCD_CLS rise delay from end of LCD_LD of line
LCD_CLS pulse width
HWAIT1+1
4
HWAIT2 + 4
3
CLS_RISE_DELAY+1
CLS_HI_WIDTH+1
PS_RISE_DELAY
REV_TOGGLE_DELAY+1
1
LCD_PS rise delay from LCD_CLS negation
LCD_REV toggle delay from last LCD_LD of line
0
1
Note: Falling of LCD_SPL/LCD_SPR aligns with first LCD_LD of line.
Note: Falling of LCD_PS aligns with rising edge of LCD_CLS.
Note: LCD_REV toggles in every LCD_HSYN period.
T1
T1
LCD_VSYNC
T3
T4
T2
T2
XMAX
LCD_HSYNC
LCD_LSCLK
Ts
LCD_LD[15:0]
Figure 18. Non-TFT Mode Panel Timing
Table 17. Non-TFT Mode Panel Timing
Num
Description
Minimum
Value
Unit
T1
T2
T3
T4
LCD_HSYNC to LCD_VSYNC delay
LCD_HSYNC pulse width
2
1
HWAIT2 + 2
HWIDTH + 1
0 ≤ T3 ≤ Ts
HWAIT1 + 1
Tpix
Tpix
—
LCD_VSYNC to LCD_LSCLK
LCD_LSCLK to LCD_HSYNC
—
1
Tpix
Note: Ts is the LCD_LSCLK period while Tpix is the pixel clock period. LCD_VSYNC, LCD_HSYNC and LCD_LSCLK
can be programmed as active high or active low. In Figure 18, all three signals are active high. When it is in CSTN
mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. When it is in monochrome mode with bus width
= 2, 4 and 8, T3 = 1, 2 and 4 Tpix respectively.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
32
Freescale Semiconductor
Electrical Characteristics
5.11 USB On-The-Go
The MCF5329 device is compliant with industry standard USB 2.0 specification.
5.12 ULPI Timing Specification
Control and data timing requirements for the ULPI pins are given in Table 18. These timings apply in synchronous mode only.
All timings are measured with either a 60 MHz input clock from the USB_CLKIN pin. The USB_CLKIN needs to maintain a
50% duty cycle. Control signals and 8-bit data are always clocked on the rising edge.
The ULPI interface on the MCF5329 processor is compliant with the industry standard definition.
THD
TSD
THC
TDD
TSC
TDC
ULPI_CLK
ULPI_STP
(Input)
ULPI_DATA
(Input-8bit)
ULPI_DIR/ULPI_NXT
(Output)
ULPI_DATA
(Output-8bit)
Figure 19. ULPI Timing Diagram
Table 18. ULPI Interface Timing
Parameter
Symbol
Min
Max
Units
Setup time (control in, 8-bit data in)
Hold time (control in, 8-bit data in)
Output delay (control out, 8-bit data out)
TSC, TSD
THC, THD
TDC, TDD
—
−1.5
—
3.0
—
ns
ns
ns
6.0
5.13 SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
1
Table 19. SSI Timing – Master Modes
Num
Description
SSI_MCLK cycle time2
Symbol
Min
Max
Units
S1
S2
S3
S4
S5
tMCLK 8 × tSYS
—
55%
—
ns
tMCLK
ns
SSI_MCLK pulse width high / low
SSI_BCLK cycle time3
45%
tBCLK 8 × tSYS
45%
SSI_BCLK pulse width
55%
15
tBCLK
ns
SSI_BCLK to SSI_FS output valid
—
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
33
Electrical Characteristics
Num
1
Table 19. SSI Timing – Master Modes (continued)
Description
Symbol
Min
Max
Units
S6
S7
S8
S9
SSI_BCLK to SSI_FS output invalid
-2
—
-4
15
0
—
15
—
—
—
ns
ns
ns
ns
ns
SSI_BCLK to SSI_TXD valid
SSI_BCLK to SSI_TXD invalid / high impedence
SSI_RXD / SSI_FS input setup before SSI_BCLK
S10 SSI_RXD / SSI_FS input hold after SSI_BCLK
1
2
All timings specified with a capactive load of 25pF.
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock
(SYSCLK).
3
SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the
minimum divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure
that SSI_BCLK does not exceed 4 x fSYS
Table 20. SSI Timing – Slave Modes
Description Symbol
.
1
Num
S11 SSI_BCLK cycle time
Min
Max
Units
tBCLK 8 × tSYS
—
55%
—
ns
tBCLK
ns
S12 SSI_BCLK pulse width high/low
45%
10
3
S13 SSI_FS input setup before SSI_BCLK
S14 SSI_FS input hold after SSI_BCLK
S15 SSI_BCLK to SSI_TXD/SSI_FS output valid
—
ns
—
15
ns
S16 SSI_BCLK to SSI_TXD/SSI_FS output invalid/high
impedence
-2
—
ns
S17 SSI_RXD setup before SSI_BCLK
S18 SSI_RXD hold after SSI_BCLK
10
3
—
—
ns
ns
1
All timings specified with a capactive load of 25pF.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
34
Freescale Semiconductor
Electrical Characteristics
S1
S2
S2
SSI_MCLK
(Output)
S3
SSI_BCLK
(Output)
S4
S4
S5
S6
SSI_FS
(Output)
S9
S10
SSI_FS
(Input)
S7
S8
S7
S8
SSI_TXD
SSI_RXD
S9
S10
Figure 20. SSI Timing – Master Modes
S11
SSI_BCLK
(Input)
S12
S12
S15
S16
SSI_FS
(Output)
S13
S14
SSI_FS
(Input)
S15
S16
S16
S15
SSI_TXD
SSI_RXD
S17
S18
Figure 21. SSI Timing – Slave Modes
2
5.14 I C Input/Output Timing Specifications
2
Table 21 lists specifications for the I C input timing parameters shown in Figure 22.
2
Table 21. I C Input Timing Specifications between SCL and SDA
Num
Characteristic
Start condition hold time
Min
Max
Units
I1
I2
I3
I4
2
8
—
—
1
tcyc
tcyc
ms
ns
Clock low period
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
Data hold time
—
0
—
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
35
Electrical Characteristics
Table 21. I C Input Timing Specifications between SCL and SDA (continued)
2
Num
Characteristic
Min
Max
Units
I5
I6
I7
I8
I9
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
Clock high time
—
4
1
ms
tcyc
ns
—
—
—
—
Data setup time
0
Start condition setup time (for repeated start condition only)
Stop condition setup time
2
tcyc
tcyc
2
2
Table 22 lists specifications for the I C output timing parameters shown in Figure 22.
2
Table 22. I C Output Timing Specifications between SCL and SDA
Num
I11 Start condition hold time
I2 1 Clock low period
Characteristic
Min
Max
Units
6
10
—
7
—
—
—
—
3
tcyc
tcyc
µs
I3 2 I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
I4 1 Data hold time
tcyc
ns
I5 3 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
I6 1 Clock high time
—
10
2
—
—
—
—
tcyc
tcyc
tcyc
tcyc
I7 1 Data setup time
I8 1 Start condition setup time (for repeated start condition only)
I9 1 Stop condition setup time
20
10
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 22. The I2C interface is
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR; however, the numbers
given in Table 22 are minimum values.
2
3
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and
pull-up resistor values.
Specified at a nominal 50-pF load.
Figure 22 shows timing for the values in Table 22 and Table 21.
I5
I6
I2
I2C_SCL
I2C_SDA
I7
I8
I1
I9
I4
I3
2
Figure 22. I C Input/Output Timings
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
36
Freescale Semiconductor
Electrical Characteristics
5.15 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V.
5.15.1 MII Receive Signal Timing
The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. The processor clock frequency
must exceed twice the FEC_RXCLK frequency.
Table 23 lists MII receive channel timings.
Table 23. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
M2
M3
M4
FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup
FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold
FEC_RXCLK pulse width high
5
—
—
ns
5
ns
35%
35%
65%
65%
FEC_RXCLK period
FEC_RXCLK period
FEC_RXCLK pulse width low
Figure 23 shows MII receive signal timings listed in Table 23.
M3
FEC_RXCLK (input)
M4
FEC_RXD[3:0] (inputs)
FEC_RXDV
FEC_RXER
M1
M2
Figure 23. MII Receive Signal Timing Diagram
5.15.2 MII Transmit Signal Timing
Table 24 lists MII transmit channel timings.
The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. The processor clock frequency
must exceed twice the FEC_TXCLK frequency.
Table 24. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
M6
M7
M8
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid
FEC_TXCLK pulse width high
5
—
ns
—
25
ns
35%
35%
65%
65%
FEC_TXCLK period
FEC_TXCLK period
FEC_TXCLK pulse width low
Figure 24 shows MII transmit signal timings listed in Table 24.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
37
Electrical Characteristics
M7
FEC_TXCLK (input)
M5
M8
FEC_TXD[3:0] (outputs)
FEC_TXEN
FEC_TXER
M6
Figure 24. MII Transmit Signal Timing Diagram
5.15.3 MII Async Inputs Signal Timing
Table 25 lists MII asynchronous inputs signal timing.
Table 25. MII Async Inputs Signal Timing
Num
Characteristic
Min
Max
Unit
M9
FEC_CRS, FEC_COL minimum pulse width
1.5
—
FEC_TXCLK period
FEC_CRS
FEC_COL
M9
Figure 25. MII Async Inputs Timing Diagram
5.15.4 MII Serial Management Channel Timing
Table 26 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5
MHz.
Table 26. MII Serial Management Channel Timing
Num
Characteristic
Min Max
Unit
M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum
propagation delay)
0
—
ns
M11 FEC_MDC falling edge to FEC_MDIO output valid (max prop delay)
M12 FEC_MDIO (input) to FEC_MDC rising edge setup
M13 FEC_MDIO (input) to FEC_MDC rising edge hold
M14 FEC_MDC pulse width high
—
10
0
25
—
—
ns
ns
ns
40% 60% FEC_MDC period
40% 60% FEC_MDC period
M15 FEC_MDC pulse width low
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
38
Freescale Semiconductor
Electrical Characteristics
M14
M15
FEC_MDC (output)
FEC_MDIO (output)
M10
M11
FEC_MDIO (input)
M12
M13
Figure 26. MII Serial Management Channel Timing Diagram
5.16 32-Bit Timer Module Timing Specifications
Table 27 lists timer module AC timings.
Table 27. Timer Module AC Timing Specifications
Name
Characteristic
Min
Max
Unit
T1
T2
DT0IN / DT1IN / DT2IN / DT3IN cycle time
DT0IN / DT1IN / DT2IN / DT3IN pulse width
3
1
—
—
tCYC
tCYC
5.17 QSPI Electrical Specifications
Table 28 lists QSPI timings.
Table 28. QSPI Modules AC Timing Specifications
Characteristic
Name
Min
Max
Unit
QS1
QS2
QS3
QS4
QS5
QSPI_CS[3:0] to QSPI_CLK
1
—
2
510
10
—
tCYC
ns
QSPI_CLK high to QSPI_DOUT valid.
QSPI_CLK high to QSPI_DOUT invalid. (Output hold)
QSPI_DIN to QSPI_CLK (Input setup)
QSPI_DIN to QSPI_CLK (Input hold)
ns
9
—
ns
9
—
ns
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
39
Electrical Characteristics
QS1
QSPI_CS[3:0]
QSPI_CLK
QS2
QSPI_DOUT
QSPI_DIN
QS3
QS4
QS5
Figure 27. QSPI Timing
5.18 JTAG and Boundary Scan Timing
Table 29. JTAG and Boundary Scan Timing
Num
Characteristics1
TCLK Frequency of Operation
Symbol
Min
Max
Unit
J1
J2
J3
J4
J5
J6
J7
J8
J9
fJCYC
tJCYC
DC
4
1/4
—
—
3
fsys/3
tCYC
ns
TCLK Cycle Period
TCLK Clock Pulse Width
tJCW
26
0
TCLK Rise and Fall Times
tJCRF
ns
Boundary Scan Input Data Setup Time to TCLK Rise
Boundary Scan Input Data Hold Time after TCLK Rise
TCLK Low to Boundary Scan Output Data Valid
TCLK Low to Boundary Scan Output High Z
TMS, TDI Input Data Setup Time to TCLK Rise
tBSDST
tBSDHT
tBSDV
4
—
—
33
33
—
—
26
8
ns
26
0
ns
ns
tBSDZ
0
ns
tTAPBST
tTAPBHT
tTDODV
tTDODZ
tTRSTAT
tTRSTST
4
ns
J10 TMS, TDI Input Data Hold Time after TCLK Rise
J11 TCLK Low to TDO Data Valid
10
0
ns
ns
J12 TCLK Low to TDO High Z
0
ns
J13 TRST Assert Time
100
10
—
—
ns
J14 TRST Setup Time (Negation) to TCLK High
ns
1
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
40
Freescale Semiconductor
Electrical Characteristics
J2
J3
J3
VIH
TCLK
(input)
VIL
J4
J4
Figure 28. Test Clock Input Timing
TCLK
VIL
VIH
J5
J6
Data Inputs
Input Data Valid
J7
J8
Data Outputs
Output Data Valid
Data Outputs
Data Outputs
J7
Output Data Valid
Figure 29. Boundary Scan (JTAG) Timing
TCLK
VIL
VIH
J9
Input Data Valid
J10
TDI
TMS
J11
TDO
Output Data Valid
J12
J11
TDO
TDO
Output Data Valid
Figure 30. Test Access Port Timing
TCLK
TRST
J14
J13
Figure 31. TRST Timing
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
41
Current Consumption
5.19 Debug AC Timing Specifications
Table 30 lists specifications for the debug AC timing parameters shown in Figure 32.
Table 30. Debug AC Timing Specification
Num
Characteristic
PSTCLK cycle time
Min
Max
Units
D0
D1
D2
D3
D41
D5
D6
2
—
1.5
1
2
3.0
—
—
—
—
—
t
SYS = 1/fSYS
ns
PSTCLK rising to PSTDDATA valid
PSTCLK rising to PSTDDATA invalid
DSI-to-DSCLK setup
ns
PSTCLK
PSTCLK
PSTCLK
PSTCLK
DSCLK-to-DSO hold
4
DSCLK cycle time
5
BKPT assertion time
1
1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized
DSCLK input relative to the rising edge of PSTCLK.
D0
PSTCLK
D2
D1
PSTDDATA[7:0]
Figure 32. Real-Time Trace AC Timing
D5
DSCLK
DSI
D3
Current
D4
Next
DSO
Past
Current
Figure 33. BDM Serial Port AC Timing
6
Current Consumption
All current consumption data is lab data measured on a single device using an evaluation board. Table 31 shows the typical
power consumption in low-power modes. These current measurements are taken after executing a STOP instruction.
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
42
Freescale Semiconductor
Current Consumption
1,2
Table 31. Current Consumption in Low-Power Modes
58 MHz
(Typ)3
64 MHz
(Typ)3
72 MHz
(Typ)3
80 MHz
(Typ)3
80 MHz
Units
Mode
Voltage
(Peak)4
3.3 V
1.5 V
3.3 V
1.5 V
3.3 V
1.5 V
3.3 V
1.5 V
3.3 V
1.5 V
3.3 V
1.5 V
3.9
3.92
1.04
4.0
1.04
4.8
4.0
1.04
4.8
4.0
1.08
4.8
Stop Mode 3 (Stop 11)5
Stop Mode 2 (Stop 10)4
Stop Mode 1(Stop 01)4
Stop Mode 0 (Stop 00)4
Wait/Doze
1.04
4.69
4.72
2.69
2.69
2.70
4.81
17.85
24.33
18.06
25.21
30.81
42.3
65.4
2.70
4.81
19.91
26.13
20.12
27.03
34.47
50.5
73.4
2.75
4.81
4.72
4.73
15.28
21.65
15.47
22.49
26.79
33.61
56.3
16.44
21.68
16.63
22.52
28.85
33.61
60.7
20.42
mA
26.16
20.67
39.8
97.4
62.6
Run
132.3
1
2
3
All values are measured with a 3.30V EVDD, 3.30V SDVDD and 1.5V IVDD power supplies. Tests performed at room
temperature with pins configured for high drive strength.
Refer to the Power Management chapter in the MCF532x Reference Manual for more information on low-power
modes.
All peripheral clocks except UART0, FlexBus, INTC0, reset controller, PLL, and edge port off before entering low
power mode. All code executed from flash.
4
5
All peripheral clocks on before entering low power mode. All code is executed from flash.
See the description of the low-power control register (LCPR) in the MCF532x Reference Manual for more
information on stop modes 0–3.
450
400
350
300
250
200
150
100
50
Stop 0 - Flash
Stop 1 - Flash
Stop 2 - Flash
Stop 3 - Flash
Wait/Doze - Flash
Run - Flash
0
58
64
72
80
80(peak)
fsys/3 (MHz)
Figure 34. Current Consumption in Low-Power Modes
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
43
Current Consumption
1
Table 32. Typical Active Current Consumption Specifications
Typical2 Active
fsys/3 Frequency
1.333 MHz
2.666 MHz
58 MHz
Voltage
Peak3
Unit
(Flash)
3.3V
1.5V
3.3V
1.5V
3.3V
1.5V
3.3V
1.5V
3.3V
1.5V
3.3V
1.5V
7.73
2.87
7.74
3.56
8.60
5.52
49.3
91.70
54.0
97.0
63.7
104.7
73.7
112.9
8.57
4.37
40.10
65.90
44.40
69.50
53.6
mA
64 MHz
72 MHz
74.6
63.0
80 MHz
79.6
1
All values are measured with a 3.30 V EVDD, 3.30 V SDVDD and 1.5 V IVDD power
supplies. Tests performed at room temperature with pins configured for high drive
strength.
2
3
CPU polling a status register. All peripheral clocks except UART0, FlexBus,
INTC0, reset controller, PLL, and edge port disabled.
Peak current measured while running a while(1) loop with all modules active.
Figure 35 shows the estimated maximum power consumption.
Estimated Power Consumption vs. Core Frequency
300
250
200
150
100
50
0
0
40
80
120
160
200
240
Core Frequency (MHz)
Figure 35. Estimated Maximum Power Consumption
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
44
Freescale Semiconductor
Package Information
7
Package Information
This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF532x devices.
NOTE
The mechanical drawings are the latest revisions at the time of publication of this
document. The most up-to-date mechanical drawings can be found at the product summary
page located at http://www.freescale.com/coldfire.
7.1
Package Dimensions—256 MAPBGA
Figure 36 shows MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 package dimensions.
X
D
M
Laser mark for pin A1
identification in
this area
5
Y
0.30 Z
A2
K
A
A1
256X
4
0.15 Z
Z
E
Detail K
Rotated 90° Clockwise
Notes:
1.
2.
Dimensions are in millimeters.
Interpret dimensions and tolerances
per ASME Y14.5M, 1994.
Top View
M
0.20
15X e
3.
4.
5.
Dimension b is measured at the
maximum solder ball diameter, parallel
to datum plane Z.
Datum Z (seating plane) is defined by
the spherical crowns of the solder
balls.
Parallelism measurement shall exclude
any effect of mark on top surface of
package.
Metalized mark for
pin A1 identification
in this area
S
15 13 11
16 14 12 10
7 6 5 4 3 2 1
A
B
C
D
E
F
S
15X e
3
G
H
J
256X
b
M
M
0.25
0.10
Z X Y
Millimeters
K
L
M
N
P
R
T
Dim Min
1.25
A1 0.27
Max
1.60
0.47
Z
A
1.16 REF
A2
b
D
E
e
0.40
17.00 BSC
17.00 BSC
0.60
Bottom View
1.00 BSC
0.50 BSC
View M-M
S
Figure 36. 256 MAPBGA Package Outline
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
45
Package Information
7.2
Package Dimensions—196 MAPBGA
Figure 37 shows the MCF5327CVM240 package dimensions.
NOTES:
D
X
Y
1. Dimensions are in millimeters.
2. Interpretdimensionsandtolerances
per ASME Y14.5M, 1994.
3. Dimension B is measured at the
maximum solder ball diameter,
parallel to datum plane Z.
4. Datum Z (seating plane) is defined
bythesphericalcrownsofthesolder
balls.
Laser mark for pin 1
identification in
this area
M
K
5. Parallelism measurement shall
exclude any effect of mark on top
surface of package.
Millimeters
DIM Min Max
A 1.32 1.75
A1 0.27 0.47
A2 1.18 REF
E
b
D
E
e
0.35 0.65
15.00 BSC
15.00 BSC
1.00 BSC
0.50 BSC
S
M
Top View
0.20
13X e
S
Metalized mark for
pin 1 identification
in this area
14 13 12 11 10
9
6
5
4
3
2
1
A
B
C
D
E
F
5
S
0.30 Z
13X e
A2
A
G
H
J
A1
0.15 Z
4
Z
K
L
Detail K
Rotated 90 Clockwise
°
M
N
P
3
196X
b
Bottom View
0.30 Z X Y
0.10 Z
View M-M
Figure 37. 196 MAPBGA Package Dimensions (Case No. 1128A-01)
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
46
Freescale Semiconductor
Revision History
8
Revision History
Table 33. MCF5329DS Document Revision History
Rev. No.
Substantive Changes
Date of Release
0
• Initial release.
11/2005
3/2006
0.1
• Added not to Section 7, “Package Information.”
• Added top view and bottom view where appropriate in mechanical
drawings and pinout figures.
• Figure 6: Corrected “FB_CLK (75MHz)” label to “FB_CLK (80MHz)”
1
• Corrected MCF5327 196MAPBGA ball map locations in Table 5 for
the following signals: RCON, D1, D0, OE, R/W, SD_DQS2, PSTCLK,
DDATA[3:0], PST[3:0], EVDD, IVDD, and SD_VDD. Figure 5 was
correct.
7/2007
• Updated thermal characteristic values in Table 5.
• Updated DC electricals values in Table 7.
• Updated Section 3.3, “Supply Voltage Sequencing and Separation
Cautions” and subsections.
• Updated and added Oscillator/PLL characteristics in Table 8.
• Table 9: Swapped min/max for FB1; Removed FB8 & FB9.
• Updated SDRAM write timing diagram, Figure 9.
• Table 11: Added values for frequency of operation and DD1.
• Reworded first paragraph in Section 5.12, “ULPI Timing
Specification.”
• Updated Figure 19.
• Replaced figure & table Section 5.13, “SSI Timing Specifications,”
with slave & master mode versions.
• Removed second sentence from Section 5.15.2, “MII Transmit Signal
Timing,” regarding no minimum frequency requirement for TXCLK.
• Removed third and fourth paragraphs from Section 5.15.2, “MII
Transmit Signal Timing,” as this feature is not supported on this
device.
• Updated figure & table Section 5.19, “Debug AC Timing
Specifications.”
• Renamed & moved previous version’s Section 5.5 “Power
Consumption” to Section 6, “Current Consumption.” Added additional
real-world data to this section as well.
2
3
• Added MCF53281 device information throughout: features list, family
configuration table, ordering information table, signals description
table, and relevant package diagram titles
• Remove Footnote 1 from Table 11.
• Changed document type from Advance Information to Technical Data.
8/2007
• Corrected MCF53281 in features list table. This device contains CAN,
but does not feature the cryptography accelerators.
• In pin-multiplexing table, moved MCF53281 label from the MCF5328
column to the MCF5329 column, because this device contains CAN
output signals.
10/2007
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
47
Revision History
Table 33. MCF5329DS Document Revision History (continued)
Substantive Changes
Rev. No.
4
Date of Release
• Corrected pinouts in Signal Information and Pin-Muxing table for
196 MAPBGA device:
4/2008
Changed D[15:1] entry from “F4–F1, G4–G2...” to “F4–F1, G5–G2...”
Changed DSO/TDO entry from “P9” to “N9”
• Corrected D0 spec in Table 30 from 1.5 x tsys to 2 x tsys for min and
max balues.
• Updated FlexBus read and write timing diagrams in Figure 7 and
Figure 8.
• Removed footnote 2 from the IRQ[7:1] alternate functions USBHOST
VBUS_EN, USBHOST VBUS_OC, SSI_MCLK, USB_CLKIN, and
SSI_CLKIN signals in Signal Information and Pin-Muxing table.
• Updated pinouts for 196 MAPBGA device, MCF5327CVM240 in both
Figure 5 and Table 2.
The following locations are affected: G10–12, H12–14, J11–14,
K12–13, L12–13, M12–14, N13.
The following signals are affected: USBOTG_VDD, USBHOST_VSS,
USBOTG_M, USBOTG_P, USBHOST_M, USBHOST_P, DRAMSEL,
PWM3, PWM1, IRQ[7,4,3,2,1], RESET, TDI/DSI, JTAG_EN,
TMS/BKPT.
5
Changed the following specs in Table 10 and Table 11:
• Minimum frequency of operation from TBD to 60MHz
• Maximum clock period from TBD to 16.67 ns
11/2008
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
48
Freescale Semiconductor
Revision History
MCF532x ColdFire® Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
49
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Document Number: MCF5329DS
Rev. 5
11/2008
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