MCZ34652EF_技术文档

Archived by Freescale Semiconductor, Inc., 2008

Document Number: MC34652

Rev. 8.0, 2/2007

Freescale Semiconductor

Advance Information

2.0 A Negative Voltage Hot

Swap Controller with Enhanced

Programmability

34652

The 34652 is a highly integrated -48 V hot swap controller with an

internal Power MOSFET. It provides the means to safely install and

remove boards from live -48 V backplanes without having to power

down the entire system. It regulates the inrush current, from the

supply to the load’s filter capacitor, to a user-programmable limit,

allowing the system to safely stabilize. A disable function allows the

user to disable the 34652 manually or through a microprocessor and

safely disconnect the load from the main power line.

HOT SWAP

The 34652 has active high and active low power good output

signals that can be used to directly enable a power module load.

Programmable under- and overvoltage detection circuitry monitors

the input voltage to check that it is within its operating range.

A programmable start-up delay timer ensures that it is safe to turn on

the Power MOSFET and charge the load capacitor.

A two-level current limit approach to controlling the inrush current

and switching on the load limits the peak power dissipation in the

Power MOSFET. Both current limits are user programmable.

SCALE 2:1

EF SUFFIX (PB-Free)

98ASB42566B

16-PIN SOICN

Features

ORDERING INFORMATION

Temperature

• Integrated Power MOSFET and Control IC in a Small Outline

Package

• Input Voltage Operation Range from -15 V to -80 V

• Programmable Overcurrent Limit with Auto Retry

• Programmable Charging Current Limit Independent of Load

Capacitor

• Programmable Start-Up and Retry Delay Timer

• Programmable Overvoltage and Undervoltage Detection

• Active High and Low Power Good Output Signals

• Thermal Shutdown

Device

Package

Range (T )

A

MC34652EF/R2

MCZ34652EF/R2

-40°C to 85°C

16 SOICN

• Pb-Free Packaging Designated by Suffix Code EF

34652

DISABLE

Application

Dependent

PG

GND

System

Power

Supply

VPWR

UV

PG

VOUT

Load

OV

(Backplane)

-48 V

VIN

ICHG

Optional

External

Components

TIMER

Optional

External

Components

ILIM

Figure 1. 34652 Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

Archived by Freescale Semiconductor, Inc., 2008

INTERNAL BLOCK DIAGRAM

Timer

and

External

Resistors

Detection

Referenced VPWR

Logic

Adjustable Oscillator

and

Startup Delay Timer

DISABLE

VPWR

Fixed

Oscillator

TIMER

PG

-

UVLO

UV

1.3 V

+

Logic

-

UV

OV

+

-

OV

VIN

Thermal

Shutdown

3.1 V

ILIM

External

Resistors

Detection

Programmable

Current Limit

8.0 µA

Gate Control

Driver

ICHG

Sensor MOSFET

Power MOSFET

VOUT

VIN

Figure 2. 34652 Simplified Internal Block Diagram

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

Archived by Freescale Semiconductor, Inc., 2008

PIN CONNECTIONS

1

2

VIN

PG

16

15

VIN

ICHG

3

4

5

6

14

13

ILIM

PG

VOUT

DISABLE

VPWR

UV

12

11

10

9

TIMER

7

8

NC

OV

VIN

Figure 3. 16-SOICN Pin Connections

Table 1. 16-SOICN Pin Definitions

A functional description of each pin can be found in the FUNCTIONAL PIN DESCRIPTION section beginning on page 10.

Pin Name

Formal Name

Definition

This is the most negative power supply input. All pins except DISABLE are referenced

to this input.

1, 8, 9, 16

VIN

Negative Supply

Input Voltage

This is an active high power good output signal. This pin is referenced to VIN.

2

3

PG

Power Good Output

(Active High)

This is an active low power good output signal. This pin is referenced to VIN.

Power Good Output

(Active Low)

PG

This pin is the drain of the internal Power MOSFET and supplies a current limited voltage

to the load.

4, 5

6

VOUT

TIMER

Output Voltage

This input is used to control the time base used to generate the timing sequences at

start-up and the retry delay when the device experiences any fault.

Start-Up and Retry

Delay Timer

Not connected.

7

NC

OV

No Connect

This pin is used to set the upper limit of the input voltage operation range.

This pin is used to set the lower limit of the input voltage operation range.

10

11

12

Overvoltage Control

Undervoltage Control

UV

This is the most-positive power supply input. The load connects between this pin and the

VOUT pin.

VPWR

Positive Supply

Input Voltage

This pin is used to easily disconnect or connect the load from the main power line by

disabling or enabling the 34652. It can also be used to reset the fault conditions that

cause a “Power No Good” signal. This pin is referenced to VPWR.

13

DISABLE

Disable Input Control

This pin is used to set the overcurrent limit during normal operation.

14

15

ILIM

Current Limit Control

This pin is used to set the load’s input capacitor charging current limit, hence limiting the

inrush current to a known constant value.

ICHG

Charging Current

Limit Control

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

3

Archived by Freescale Semiconductor, Inc., 2008

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

Power Supply Voltage

V

85

Varies ⁽¹⁾

2.0

V

mJ

A

PWR

Power MOSFET Energy Capability

Continuous Output Current ⁽²⁾

E_MOSFET

I

O(CONT)

Maximum Voltage

DISABLE Pin

UV Pin

V

—

V

- 0.3 to V

+ 5.5

PWR

IN

7.0

5.0

85

OV, ILIM, ICHG, and TIMER Pins

PG Pin (V

- V )

IN

PG

85

PG Pin (V

- V )

IN

All Pins Minimum Voltage

PG, PG Maximum Current

—

-0.3

V

A

V

Internally Limited

ESD Voltage, All Pins ⁽³⁾

Human Body Model

Machine Model

V

±2000

±200

ESD3

V

ESD4

THERMAL RATINGS

Storage Temperature

Operating Temperature

T

-65 to 150

°C

STG

T

Ambient ⁽⁴⁾

Junction

A

-40 to 85

T

J

-40 to 160

Notes

1. Refer to the section titled Power MOSFET Energy Capability on page 23 for a detailed explanation on this parameter.

2. Continuous output current capability so long as T is ≤ 160°C.

J

3. ESD1 testing is performed in accordance with the Human Body Model (C

=100pF, R

=1500 Ω), ESD2 testing is performed in

ZAP

accordance with the Machine Model (C

=200 pF, R

=0 Ω).

ZAP

4. The limiting factor is junction temperature, taking into account power dissipation, thermal resistance, and heatsinking.

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

4

Archived by Freescale Semiconductor, Inc., 2008

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

Peak Package Reflow Temperature During Reflow ^{(5), (6)}

°C

T_PPRT

Note 6

,

(8)

Thermal Resistance ⁽⁷⁾

°C/W

Junction-to-Ambient, Single-Layer Board ⁽⁹⁾

Junction-to-Ambient, Four-Layer Board ⁽¹⁰⁾

R

103

65

θJA

R

θJMA

Notes

5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL),

Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.

MC33xxxD enter 33xxx), and review parametrics.

7. Refer to the section titled Thermal Shutdown on page 16 for more thermal resistance values under various conditions.

8. The VOUT and VIN pins comprise the main heat conduction paths.

9. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.

10. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. There are no thermal vias connecting the package to the two planes in the

board.

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

5

Archived by Freescale Semiconductor, Inc., 2008

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 15 V ≤ V_PWR≤ 80 V and -40°C ≤ T_A≤ 85°C. All voltages are referenced to VIN unless

otherwise noted.

Characteristic

POWER SUPPLY PIN (VPWR)

Symbol

Min

Typ

Max

Unit

Supply Voltage

V

15

—

80

V

μA

V

PWR

Supply Current, Device Enabled, Default Mode, Normal Operation ⁽¹¹⁾

I

900

1400

IN

Undervoltage Lockout Threshold (UVLO)

V

Rising

7.0

6.0

—

8.0

7.0

1.0

9.0

8.0

—

UVLOR

V

Falling

UVLOF

V

Hysteresis

UVLOHY

UNDERVOLTAGE CONTROL

UV Threshold (Default)

Rising

V

—

38

37

—

UV(ON)

Falling

V

UV(OFF)

V

Hysteresis

UVHY

1.0

UV Comparator Threshold

Rising

V

—

1.3

34

—

V

UVC

Hysteresis

V

UVCHY

mV

UV Input Leakage Current

I

—

1.0

μA

kΩ

UVLG

—

Maximum Value of the Series Resistance Between UV and VPWR Pins

OVERVOLTAGE CONTROL

500

OV Threshold (Default)

Rising

V

—

78

76

—

OV(OFF)

Falling

V

OV(ON)

V

Hysteresis

OVHY

2.0

OV Comparator Threshold

Rising

V

—

1.3

34

—

V

OVC

Hysteresis

V

mV

OVCHY

OV Input Leakage Current

I

—

1.0

μA

kΩ

OVLG

—

Maximum Value of the Series Resistance Between UV and VPWR Pins

Notes

500

11. The supply current depends on operation mode and can be calculated as follows:

•Start-Up Mode: I_IN= 539 μA + 548 μ * I (A) + 216 μ * I (A) + V_PWR(V) / 460(kΩ)

CHG

LIM

•Normal Mode: I_IN= 539 μA + 240 μ * I (A) + 288 μ * I

(A) + V_PWR(V) / 460(kΩ)

LOAD

LIM

•Overcurrent Mode: I_IN= 539 μA + 612 μ * I (A) + V_PWR(V) / 460(kΩ)

LIM

•Disable Mode: I_IN= 539 μA + 240 μ * I (A) + I (μA) + V_PWR(V) / 460(kΩ)

LIM

DIS

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

6

Archived by Freescale Semiconductor, Inc., 2008

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 15 V ≤ V_PWR≤ 80 V and -40°C ≤ T_A≤ 85°C. All voltages are referenced to VIN unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

DISABLE INPUT CONTROL PIN (DISABLE) ⁽¹²⁾

DISABLE Input Voltage

Inactive State

V

-1.2

—

V

+ 1.2

PWR

DISL

PWR

Active State, Positive Signal

Active State, Negative Signal

V

+2.0

—

DISHP

PWR

V

—

V

-2.0

DISHN

PWR

DISABLE Input Current

I

μA

DIS

V

= V

+ 3.3 V

- 3.3 V

20

-20

-50

60

-60

180

-180

-250

DIS

PWR

IN

-150

CURRENT LIMIT CONTROL PINS (ILIM, ICHG)

Overcurrent Limit in Steady State

Default

I

A

LIM

—

1.0

—

Maximum with External Resistor

Minimum with External Resistor

2.25

0.35

Current Limit During Start-Up

Default

I

CHG

—

0.1

0.5

—

Maximum with External Resistor

Minimum with External Resistor

0.05

Short Circuit Current Limit

I

—

5.0

12

—

20

35

—

A

%

V

SHORT

I

Current Limit Hysteresis

Current Limit Accuracy

I

LIM

LIMHY

-20

-35

—

LIMCLA

I

—

CHG

CHGCLA

ILIM Pin Voltage

V

3.1

129

-8.0

335

ILIM

I

to R

Setting Constant

ILIM

I_LIMCNS

—

A

kΩ

LIM

*

Reference Current

I

—

μA

CHG

CHGOUT

CHGCNS

to R

Setting Constant

I

—

kΩ/A

ICHG

POWER GOOD OUTPUT PINS (PG, PG) ⁽¹³⁾

Power Good Output Low Voltage

V

PGL

I

or I

= 1.6 mA

—

0.5

10

PG

Power Good Leakage Current

Power Good Current Limit

I

μA

PGLG

I

mA

PGCL

V

or V

= 3.0 V

PG

—

7.0

PG

Notes

12. Referenced to VPWR.

13. Referenced to VIN.

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

Archived by Freescale Semiconductor, Inc., 2008

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 15 V ≤ V_PWR≤ 80 V and -40°C ≤ T_A≤ 85°C. All voltages are referenced to VIN unless

otherwise noted.

Characteristic

START-UP AND RETRY DELAY TIMER (TIMER)

TIMER Pin Voltage

Symbol

Min

—

Typ

1.3

—

Max

—

Unit

V

I

TIMER

OUTPUT VOLTAGE PIN (VOUT)

VOUT Leakage Current

—

50

μA

mΩ

OUTLG

POWER MOSFET

ON Resistance @ 25°C

R

—

144

—

DS(ON)

THERMAL SHUTDOWN

Thermal Shutdown Temperature

Thermal Shutdown Temperature Hysteresis

T

—

160

25

—

°C

SD

T

SDHY

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

8

Archived by Freescale Semiconductor, Inc., 2008

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 15 V ≤ V_PWR≤ 80 V and -40°C ≤ T_A≤ 85°C. All voltages are referenced to VIN unless

otherwise noted.

Characteristic

Symbol

Min

—

Typ

1.0

Max

—

Unit

ms

UNDERVOLTAGE CONTROL

UV Active to Gate Low Filter Time

OVERVOLTAGE CONTROL

t

UVAL

OVAL

OV Active to Gate Low Filter Time

DISABLE INPUT CONTROL PIN (DISABLE) ⁽¹⁴⁾

DISABLE Active to Gate Low Filter Time

CURRENT LIMIT CONTROL PINS (ILIM, ICHG)

Short Circuit Protection Delay

—

ms

t

—

ms

DISAL

t

—

10

—

μs

SCPD

OCFT

Overcurrent Limit Filter Time

100

3.0

Overcurrent Limit Regulation Time

t

ms

OC

I

Rise Time

t

CHG

ICHGR

Default

Adjustable with an External Capacitor

—

1.0

—

1.0

POWER GOOD OUTPUT PINS (PG, PG) ⁽¹⁵⁾

Power Good Output Delay Time, from Power MOSFET Enhancement to PG

and PG Asserted

t

ms

PG

10

28

46

START-UP AND RETRY DELAY TIMER (TIMER)

Start-Up and Retry Delay Timer

Default

t

TIMER

130

—

200

1000

100

270

—

Maximum with External Resistor

Minimum with External Resistor

—

Notes

14. Referenced to VPWR.

15. Referenced to VIN.

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

Archived by Freescale Semiconductor, Inc., 2008

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

Most telecom and data transfer networks require that

circuit boards be inserted and removed from the system

without powering down the entire system. When a circuit

board is inserted into or removed from a live backplane, the

filter or bypass capacitors at the input of the board’s power

module or switching power supply can cause large transient

currents when being charged or discharged. These currents

can cause severe and permanent damage to the boards, thus

making the system unstable. Figure 4 displays the inrush

current to the filter capacitor if a hot swap device is absent.

The inrush current reached an unsafe value of more than

55 A.

voltages in a controlled manner and regulating the inrush

current to a user-programmable limit, thus allowing the

system to safely stabilize (see Figure 5). The 34652 provides

protection against overcurrent, undervoltage, overvoltage,

and overtemperature. Furthermore, it protects the system

from short circuits.

Figure 5. Circuit Board Insertion With the Hot Swap

Device, Inrush Current Limited

By integrating the control circuitry and the Power MOSFET

switch into a space-efficient package, the 34652 offers a

complete, cost-effective, and simple solution that takes much

less board space than a similar part with an external Power

MOSFET requires.

Figure 4. Circuit Board Insertion Without a

Hot Swap Device, Inrush Current Not Limited

The 34652 can be used in -48 V telecom and networking

systems, servers, electronic circuit breakers, -48 V

distributed power systems, negative power supply control,

and central office switching.

The 34652 is an integrated negative voltage hot swap

controller with an internal Power MOSFET. The 34652

resides on the plug-in boards and allows the boards to be

safely inserted or removed by powering up the supply

FUNCTIONAL PIN DESCRIPTION

The signal is deactivated under the following conditions:

NEGATIVE SUPPLY INPUT VOLTAGE (VIN)

The VIN pin is the most negative power supply input. All

pins except the DISABLE pin are referenced to this input.

• Power is turned off.

• The device is disabled for more than 1.0 ms.

• The device exceeded its thermal shutdown threshold for

more than 12 μs.

POWER GOOD OUTPUT (ACTIVE HIGH) (PG)

The PG pin is the active high power good output signal that

is used to enable or disable a load. This signal goes active

after a successful power-up sequence and stays active as

long as the device is in normal operation and is not

experiencing any faults.

• The device is in overvoltage or undervoltage mode for

more than 1.0 ms.

• Load current exceeded the overcurrent limit for more than

3.0 ms.

This pin is referenced to VIN.

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

10

Archived by Freescale Semiconductor, Inc., 2008

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

POWER GOOD OUTPUT (ACTIVE LOW) (PG)

UNDERVOLTAGE CONTROL (UV)

The PG pin is the active low power good output signal that

is used to enable or disable a load. This signal goes active

after a successful power-up sequence and stays active as

long as the device is in normal operation and is not

experiencing any faults.

The UV pin is used to set the lower limit of the input voltage

operation range. If the UV pin voltage goes below the

undervoltage threshold value, the device turns off the internal

Power MOSFET and deactivates the two power good

outputs, PG and PG. The Power MOSFET stays off until the

UV rises above the threshold value. The undervoltage

detection circuit has a 1.0 ms filter timer.

The signal is deactivated under the following conditions:

• Power is turned off.

The UV pin can be left unconnected for the typical default

threshold value of 37 V or the user can set the threshold

value externally with a simple voltage divider using resistors

between the VPWR and VIN pins.

• The device is disabled for more than 1.0 ms.

• The device exceeded its thermal shutdown threshold for

more than 12 μs.

• The device is in overvoltage or undervoltage mode for

more than 1.0 ms.

• Load current exceeded the overcurrent limit for more than

3.0 ms.

POSITIVE SUPPLY VOLTAGE INPUT (VPWR)

The VPWR pin is the most-positive power supply input.

The load connects between the VPWR and VOUT pins.

This pin is referenced to VIN.

DISABLE INPUT CONTROL (DISABLE)

OUTPUT VOLTAGE (VOUT)

The DISABLE pin is used to easily disconnect or connect

the load from the main power line by disabling or enabling the

34652. It can also be used to reset the fault conditions that

cause a “Power No Good” signal.

The VOUT pin is the drain of the internal Power MOSFET

and supplies a current-limited voltage to the load. The load

connects between the VOUT and VPWR pins.

If left open or connected to VPWR, the DISABLE pin is

inactive and the device is enabled. If a positive voltage

(above V_PWR) or a negative voltage (below V_PWR) is applied

to DISABLE, it is active and the device is disabled. The

disable function has a 1.0 ms filter timer.

START-UP AND RETRY DELAY TIMER (TIMER)

This input is used to control the time-base used to

generate the timing sequences at start-up and the retry delay

when the device experiences any fault. The TIMER pin can

be left unconnected for a default timer value of 200 ms or the

user can connect a resistor between this pin and the VIN pin

to set the timer value externally. The timer value can vary

between 100 ms and 1000 ms.

This pin is referenced to VPWR.

CURRENT LIMIT CONTROL (ILIM)

The ILIM pin is used to set the overcurrent limit during

normal operation. This pin can be left unconnected for a

default overcurrent limit value of 1.0 A or the user can

connect an external resistor between the ILIM and VIN pins

to set the overcurrent limit value. This value can vary

between 0.35 A and 2.25 A. The overcurrent detection circuit

has a 100 μs filter timer.

OVERVOLTAGE CONTROL (OV)

The OV pin is used to set the upper limit of the input

voltage operation range. If the OV pin voltage goes above the

overvoltage threshold value, the device turns off the internal

Power MOSFET and deactivates the two power good

outputs, PG and PG. The Power MOSFET stays off until the

OV drops below the threshold value. The overvoltage

detection circuit has a 1.0 ms filter timer.

CHARGING CURRENT LIMIT CONTROL (ICHG)

The ICHG pin is used to set the current limit that is used to

charge the load’s input capacitor, hence limiting the inrush

current to a known constant value. This pin can be left

unconnected for a default charging current limit value of 0.1 A

and a default I_CHGrise time of 1.0 ms. Or the user can

connect an external resistor between the ICHG and VIN pins

to set the current limit value between 0.05 A and 0.5 A and an

The OV pin can be left unconnected for the typical default

threshold value of 78 V or the user can set the threshold

value externally with a simple voltage divider using resistors

between the VPWR and VIN pins.

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

Archived by Freescale Semiconductor, Inc., 2008

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

START-UP SEQUENCE

When power is first applied to the 34652 by connecting the

VIN pin to the negative voltage rail and the VPWR pin to the

positive voltage rail, the 34652 keeps the Power MOSFET

turned off, deactivates the power good output signals, and

resets the retry counter. If the device is disabled, no further

activities will occur and power-up would not start. If the device

is enabled, it starts to establish an internally regulated supply

voltage required for the internal circuitry. The Power

MOSFET will stay off until the start of the charging process.

After Power-ON Reset (POR) and once the Undervoltage

Lockout (UVLO) threshold is cleared, the 34652 checks for

external components on four pins—the UV, the ILIM, the

ICHG, and 128 μs later the OV—to set the levels of the

Undervoltage Threshold, the Overcurrent Limit, the Charging

Current Limit, and the Overvoltage Threshold, respectively.

The device also checks for external components on the

TIMER pin to decide on the Start-Up and Retry Delay Timer

value, and the device keeps checking the TIMER pin

continuously throughout the operation.

Figure 6. Start-Up Sequence

Start-Up Conditions

The device then initiates the start-up timer (Point A in

Figure 6) and checks for the start-up conditions (see next

paragraph). The duration of the timer is either a default or a

user-programmable value. For undervoltage and overvoltage

faults during power up the 34652 retries infinitely until normal

input voltage is attained. If the die temperature ever

increased beyond the thermal shutdown threshold or the

device is disabled, then the start-up timer resets and the retry

counter increments. If after 10 retries the die temperature is

still high and the device is still disabled, the 34652 will not

retry again and the power in the device must be recycled or

the device must be disabled to reset the retry counter.

The start-up conditions are as follows:

• Input voltage is below the overvoltage turn-off threshold.

This threshold is either a default or user-programmable

value.

• Input voltage is above the undervoltage turn-off threshold.

This threshold is either a default or user-programmable

value.

• Die temperature is less than thermal shutdown

temperature.

• Device is enabled.

If the start-up conditions are satisfied for a time equal to

the length of the start-up timer and the retry counter is less

than or equal to 10, the device starts to turn on the Power

MOSFET gradually to control the inrush current that charges

up the load capacitor to eventually switch on the load (Point B

in Figure 6).

Charging Process

When charging a capacitor from a fixed voltage source, a

definite amount of energy will be dissipated in the control

circuit, no matter what the control algorithm is. This energy is

equal to the energy transferred to the capacitor—½CV².

With this in mind, the Power MOSFET in the 34652 cannot

absorb this pulse of energy instantaneously, so the pulse

must be dissipated over time. To limit the peak power

dissipation in the Power MOSFET and to spread out the

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

Archived by Freescale Semiconductor, Inc., 2008

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

NORMAL MODE

If one of the start-up conditions (list on page 12) is violated

any time from the start of the Power MOSFET enhancement

process and thereafter during normal operation, the Power

MOSFET turns off and the power good output signals

deactivate, disabling the load, and a new timer cycle starts as

explained previously. The 34652 also monitors the load

current to prevent any overload or short circuit conditions

from happening in order to protect the load from damage.

LOAD CURRENT CONTROL

When in normal operation mode, the 34652 monitors the

load and provides two modes of current control as explained

in the paragraphs below.

Overcurrent Mode

The 34652 monitors the load for overcurrent conditions. If

the current going through the load becomes larger than the

overcurrent limit for longer than the overcurrent limit filter

timer of 100 μs, the overcurrent signal is asserted and the

gate of the Power MOSFET is discharged to try to regulate

the current at the I_LIMvalue (Point A in Figure 9). The 34652

is in overcurrent mode for 3.0 ms. If after a 3.0 ms filter timer

the device is still in overcurrent mode, the device turns off the

Power MOSFET and deactivates the power good output

signals (Point B in Figure 9). The 34652 then initiates another

start-up timer and goes back through the enhancement

process. If during the 3.0 ms timer the fault was cleared, then

the 34652 goes back to the normal operation mode and the

power good output signals stay activated as shown in

Figure 10, page 14. This way the device overcomes

Figure 7. Power MOSFET Turn-On and the Gradual

Increase in the Charging Current from 0 A to I_CHG

(2.0 ms in Example)

The I_CHGcurrent charges up the load capacitor relatively

slowly. When the load capacitor is fully charged, the Power

MOSFET reaches its full enhancement, which triggers the

current limit detection to change from I_CHGto I_LIMand the load

current to decrease (Point C in Figure 6, page 12). The

current spike at Point C in Figure 6 is better displayed in

Figure 8. We can see that when the ⎜V_OUT- V_IN⎜< 0.5 V, the

Power MOSFET fully turns on to reach its full enhancement,

charging the capacitor an additional 0.5 V with a higher

current value that quickly ramps down. This eliminates the

need for a current slew rate control because the hazard for a

voltage change is less than 0.5 V. The power good output

signals activate after a 20 ms delay (Point D in Figure 6),

which in turn enables the load. The 34652 is now in normal

operation mode and the retry counter resets.

temporary overcurrent situations and at the same time

protects the load from a more severe overcurrent situation.

Figure 9. Overcurrent Mode for More Than 3.0 ms

Figure 8. Full Power MOSFET Turn-On and Current

Spike Associated with It. End of Charging Process

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

Archived by Freescale Semiconductor, Inc., 2008

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Figure 11. Disabling and Enabling the 34652

Figure 10. Overcurrent Mode for Less Than 3.0 ms

Short Circuit Mode

Figure 12 demonstrates that the 34652 must be enabled

for the length of the start-up timer to start turning on the

Power MOSFET. After the fourth disable signal, the 34652

was enabled for the length of the start-up timer. And because

the retry counter is less than 10, the 34652 turns on the

Power MOSFET and starts the charging process (refer to the

Charging Process section, pages 12–13).

If the current going through the load becomes > 5.0 A, the

Power MOSFET is discharged very fast (in less than 10 μs)

to try to regulate the current at the I_LIMvalue, and the 34652

is in the overcurrent mode for 3.0 ms. Then it follows the

pattern outlined in the Overcurrent Mode paragraph above.

DISABLING AND ENABLING THE 34652

When a negative voltage (< 1.8 V below V_PWR) is applied

to the DISABLE pin for more than 1.0 ms (Point A in

Figure 11), the 34652 is disabled, the Power MOSFET turns

off, and the power good output signals deactivate. The 34652

stays in this state until the voltage on the DISABLE pin is

brought to within ±1.2 V of V_PWRfor more than 1.0 ms to

enable the device (Point B in Figure 11). Then a new start-up

sequence initiates as described on page 12. Applying a

positive voltage (>1.8 V above V_PWR) would also disable the

34652 in the same manner.

Figure 12. Start-Up Timer Versus Disable

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

Archived by Freescale Semiconductor, Inc., 2008

FUNCTIONAL DEVICE OPERATION

PROTECTION FEATURES

BOARD REMOVAL

34652 STATE MACHINE DIAGRAM

When the board is removed, its power ramps down. As

soon as the 34652’s input voltage reaches the undervoltage

turn-off threshold, the undervoltage detection circuit activates

and the Power MOSFET turns off for having violated one of

the start-up conditions (list on page 12).

Figure 13 is a representation of the 34652 behavior in

different modes of operation.

Temp

> 160°C

Temp < 135°C

Filter = 12

μs

Turn Off

μs

MOSFET

→ OFF

Thermal

Shutdown

Start-Up Conditions

• Thermal Shutdown < 160°C

• DISABLE = 0

PG = 0

V

< 500 mV

N

≤ 10

DS

Charging Mode

MOSFET

→

OFF

PG = 0

N = N + 1

Power

Fail PG

Check

Good Check

• V_PWR< V_OV(OFF)

• V_PWR> V_UV(OFF)

If I

< I

V_PWR

> V_OV(OFF)

LOAD

LIM

V

< V

OV(ON)

Filter = t_TIMER

Filter = 1.0 ms

PWR

and V < 500 mV

DS

Filter = 1.0 ms

for 20 ms

Retry Fault

STOP

Pass PG

Check

Overvoltage

N

> 10

Overcurrent

for > 3.0 ms

MOSFET

→ OFF

Toggle DISABLE

or cycle Power Off

then On to clear fault

PG = 0

I

> I

LIM

LOAD

for 100 μs

V_PWR

< V_UV(OFF)

V

> V

UV(ON)

PWR

Normal Operation

PG = 1

Filter = 1.0 ms

Ext. Resistor Check

Overcurrent Mode

Filter = 3.0 ms

Filter = 1.0 ms

Undervoltage

MOSFET OFF

PG = 0

A signal “set” is generated to check

resistors on UV, ILIM, ICHG, and

N = 0

I

< I

- I

LOAD

LIM LIMHY

→

TIMER pins and 128

the OV pin

μs later

I

> I

SHORT

LOAD

V

> V

UVLOR

PWR

DISABLE = 0

Filter = 1.0 ms

Short Circuit

Detection

Fast Gate Discharge

< 10

DISABLE

Power Off

MOSFET

→ OFF

MOSFET

→ OFF

PG = 0

N = 0

μs

PG = 0

N = 0

POR is generated

V_PWR< V

Filter = 1.0 ms

DISABLE = 1

Filter = 1.0 ms

UVLOF

Figure 13. State Diagram

PROTECTION FEATURES

UNDERVOLTAGE

When the voltage on the UV pin drops below the

undervoltage falling threshold for more than 1.0 ms, an

undervoltage fault is detected and one of the start-up

conditions (list on page 12) is violated. The 34652 turns off

the Power MOSFET and deactivates the power good output

signals, disabling the load (Point A in Figure 14). The 34652

stays in this state until the voltage on the UV pin rises above

the undervoltage rising threshold for more than 1.0 ms,

signaling that the supply voltage is in the normal operation

range (Point B in Figure 14). Then a new start-up sequence

initiates as described on page 12. The undervoltage

detection circuit is also equipped with a 1.0 V hysteresis

when in default mode. The hysteresis value depends on the

undervoltage detection threshold and can be calculated as

follows:

V

= V

[1 - (1.3 V - V

) / 1.3 V]

UVCHY

UVHY

UV(RISING)

*

Figure 14. Undervoltage Fault Followed by a

New Start-Up Sequence

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

Archived by Freescale Semiconductor, Inc., 2008

FUNCTIONAL DEVICE OPERATION

PROTECTION FEATURES

Figure 15 shows how the 34652 uses the start-up timer to

make sure that the input voltage is above the undervoltage

falling threshold. The 34652 was in normal operation before

Point A. At Point A an undervoltage fault occurs. Then the

fault is cleared at Point B, and the 34652 initiates a start-up

sequence. Before the end of the start-up timer another

undervoltage fault occurs at Point C, so the 34652 does not

turn on the Power MOSFET. At Point D the fault is cleared

again for the length of the start-up timer. The 34652 turns on

the Power MOSFET and starts the charging process (refer to

Charging Process, pages 12–13).

Figure 16. Overvoltage Fault

THERMAL SHUTDOWN

The thermal shutdown feature helps protect the internal

Power MOSFET and circuitry from excessive temperatures.

During start-up and thereafter during normal operation, the

34652 monitors the temperature of the internal circuitry for

excessive heat. If the temperature of the device exceeds the

thermal shutdown temperature of 160°C, one of the start-up

conditions (list on page 12) is violated, and the device turns

off the Power MOSFET and deactivates the power good

output signals. Until the temperature of the device goes

below 135°C, a new start-up sequence will not be initiated.

This feature is an advantage over solutions with an external

Power MOSFET, because it is not easy for a device with an

external MOSFET to sense the temperature quickly and

accurately. The thermal shutdown circuit is equipped with a

12 μs filter.

Figure 15. Start-Up Timer Protection Against

Undervoltage Faults

OVERVOLTAGE

When the voltage on the OV pin exceeds the overvoltage

rising threshold for more than 1.0 ms, an overvoltage fault is

detected and one of the start-up conditions (list on page 12)

is violated. The 34652 turns off the Power MOSFET and

deactivates the power good output signals, thus disabling the

load. The 34652 stays in this state until the voltage on the OV

pin falls below the overvoltage falling threshold for more than

1.0 ms, signaling that the supply voltage is in the normal

operation range. Then a new start-up sequence initiates as

described on page 12.

Thermal design is critical to proper operation of the 34652.

The typical R_DS(ON)of the internal Power MOSFET is

0.144 Ω at room ambient temperature and can reach up to

0.251 Ω at high temperatures. The thermal performance of

the 34652 can vary depending on many factors, among them:

• The ambient operating temperature (T_A).

• The type of PC board—whether it is single layer or multi-

layer, has heat sinks or not, etc.—all of which affects the

value of the junction-to-ambient thermal resistance (R_θJA).

• The value of the desired load current (I_LOAD).

The overvoltage detection circuit is also equipped with a

2.0 V hysteresis when in default mode. The hysteresis value

depends on the overvoltage detection threshold and can be

calculated as follows:

When choosing an overcurrent limit, certain guidelines

need to be followed to make sure that if the load current is

running close to the overcurrent limit the 34652 does not go

into thermal shutdown. It is good practice to set the

parameters so that the resulting maximum junction

temperature is below the thermal shutdown temperature by a

safe margin.

V

= V

[1 - (1.3 V - V

) / 1.3 V]

OVCHY

OVHY

OV(RISING)

*

The waveforms for an overvoltage fault are shown in

Figure 16, page 16.

Equation 1, on the following page can be used to calculate

the maximum allowable overcurrent limit based on the

maximum desired junction temperature or vice versa.

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

Archived by Freescale Semiconductor, Inc., 2008

FUNCTIONAL DEVICE OPERATION

PROTECTION FEATURES

The power dissipation in the device can be calculated as

follows:

For example:

I_CHG= 100 mA, the default value

P = I²

R_DS(ON)

(LOAD)

*

C_LOAD= 400 μF, a very large capacitor

V_PWR= 80 V, worst case

OR

P = [T_J(max) - T_A(max)] / R_θJA

Then:

Combining the two equations:

The power pulse magnitude = I_CHGV_PWR= 8.0 W

*

I²_(LOAD)= [T_J(max) - T_A(max)] / [R_θJAR_DS(ON)] Eq 1

The power pulse duration = C_LOADV_PWR/I_CHG= 320 ms

*

For example:

Figure 17 displays the temperature profile of the device

under the instantaneous power pulse during the charging

process. Table 5 depicts thermal resistance values for

different board configurations.

T_A(max) = 55°C

R_θJA= 51°C/W for a four-layer board

R_DS(ON)= 0.251 Ω at high temperatures

Then:

60.0

50.0

40.0

30.0

20.0

10.0

0.0

I²_(LOAD)= [T_J(max) - 55°C] / [51°C/W 0.251 Ω]

I²_(LOAD)= [T_J(max) - 55°C] / 12.80°C/A²

*

So if the overcurrent limit is 2.0 A, then the maximum

junction temperature is 106.2°C, which is well below the

thermal shutdown temperature that is allowed.

The previous explanation applies to steady state power

when the device is in normal operation. During the charging

process, the power is dominated by the I* V across the Power

MOSFET. When charging starts, the power in the Power

MOSFET rises up and reaches a maximum value of I* V, then

quickly ramps back down to the steady state level in a period

governed by the size of the load’s input capacitor that is being

0

100

200

im

lli

Figure 17. Instantaneous Temperature Rise of an 8.0 W

300

400

charged and by the value of the charging current limit I_CHG

In this case the instantaneous power dissipation is much

higher than the steady state case, but it is on for a very short

time.

.

T e (ms)

Time (mi sec)

Table 5. Thermal Resistance Data

Type

Condition

Symbol Value

Unit

°C/W

Single-layer board (1s), per JEDEC JESD51-2 with board (JESD51-3) horizontal

Four-layer board (2s2p), per JEDEC JESD51-2 with board (JESD51-3) horizontal

Single-layer board with a 300 mm²radiator pad on its top surface, not standard JEDEC

Single-layer board with a 600 mm²radiator pad on its top surface, not standard JEDEC

Four-layer board with a via for each thermal lead, not standard JEDEC

Junction to Ambient

R

103

65

69

65

51

47

θJA

R

θJMA

—

Four-layer board with a 300 mm²radiator pad on its top surface and a full array of vias

between radiator pad and top surface, not standard JEDEC

Four-layer board with a 600 mm²radiator pad on its top surface and a full array of vias

between radiator pad and top surface, not standard JEDEC

Junction to Ambient

—

47

°C/W

Thermal resistance between die and board per JEDEC JESD51-8

Thermal resistance between die and case top

Junction to Board

Junction to Case

R

29

33

12

°C/W

JB

θ

R

θJC

Temperature difference between package top and junction per JEDEC JESD51-2

Junction to Package

Top

Ψ

JT

Thermal resistance between junction and thermal lead, not standard JEDEC

Junction to Lead

R

33

°C/W

θJL

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

Archived by Freescale Semiconductor, Inc., 2008

TYPICAL APPLICATIONS

The 34652 resides on the plug-in board (see Figures 18

and 19), allowing the board to be safely inserted or removed

without damaging electrical equipment. The 34652 can be

operated with no external components other than the power

good output signal pull-up resistor if the default mode was

selected for all the programmable features. This is one of the

great advantages of the 34652: it operates with minimal user

interface and minimal external component count and still

offers complete hot swapping functionality with all the

necessary protection features, from undervoltage/

overvoltage detection, to current limiting, to short circuit

protection and power good output signaling. The default

values were chosen to be sufficient for many standard

applications.

PLUG-IN CARD

GND

R

44 kΩ

33652

VPWR

1

Application

Dependent

UV

PG

R

2

3

DISABLE

OV

Enable/Enable

C

LOAD

VOUT (2)

ILIM

(4)

VIN

DC/DC

Converter

TIMER ICHG

-48 V

Figure 18 is a typical application diagram depicting the

default mode and using the power good output signal pull-up

resistor. Refer to the static and dynamic electrical

characteristics tables on pages 6 through 9 for the various

default values.

Figure 19. Typical Application Diagram with External

Components Necessary to Program the Device

UNDERVOLTAGE AND OVERVOLTAGE

DETECTION

PLUG-IN CARD

GND

The UV and OV pins are used to monitor the input voltage

to ensure that it is within the operating range and that there

are no overvoltage or undervoltage conditions, and to quickly

turn off the Power MOSFET if there are. The pins are

connected to internal comparators that compare the voltages

at the UV and OV pins with a reference voltage. The UV and

OV pins can be left unconnected for the default threshold

values of their trip point or the user can set the threshold

values externally with a simple voltage divider using resistors

between VPWR and VIN (resistors R₁, R₂, and R₃in

Figure 19). For the default mode, the 34652 is equipped with

an internal resistor divider that acts the same as the external

one. The typical default values of 37 V for the UV turn-off

threshold (falling threshold) and 78 V for the OV turn-off

threshold (rising threshold) will give a typical operating range

of 38 V to 76 V. This range is suitable for telecom industry

standards.

44 k

Ω

33652

VPWR

Application

Dependent

UV

PG

DISABLE

OV

Enable/Enable

C

LOAD

VOUT (2)

ILIM

(4)

VIN

DC/DC

Converter

TIMER ICHG

-48 V

Figure 18. Typical Application Diagram with Default

Settings and Minimal External Components

When the device passes the UVLO threshold, it checks if

there is any external resistor divider connected to the OV and

UV pins. If there is, it determines the value of the UV/OV

thresholds accordingly. If there is not, it defaults to the

internal resistor divider. It then uses the UV/OV detection

circuits to check the input supply levels before turning on the

Power MOSFET during the Start-Up Timer delay and

thereafter. As long as the voltage on the UV pin is above its

falling threshold and the voltage on the OV pin is below its

rising threshold, the supply is within operating range and the

Power MOSFET is allowed to turn on and stay on. If the UV

pin drops below its falling threshold or the OV pin rises above

its rising threshold, then one of the start-up conditions (refer

to page 12 for list) is violated and the Power MOSFET turns

off, the power good signals deactivate, and a new start-up

The 34652 can be also programmed for different values of

the Overcurrent Limit, the Charging Current Limit, the Start-

Up and Retry Delay Timer, and the UV/OV detection

thresholds using external components connected to the

device. Figure 19 shows the 34652 with the required external

components that allow access to all programmable features

in the device.

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

Archived by Freescale Semiconductor, Inc., 2008

TYPICAL APPLICATIONS

timer initiates. The UV and OV detection circuits are

equipped with a 1.0 ms filter to filter out momentary input

supply dips. Filter capacitors between the UV and VIN pins

and between the OV and VIN pins could also be added to

adjust the UV/OV filter time and prevent more transients from

affecting the device’s operation, especially if the input supply

has a lot of noise.

If the three-resistor divider, which is the recommended

approach, could not produce acceptable resistor values, the

user can consider two separate resistor dividers, one divider

for each pin from VPWR to VIN. An advantage of the two-

resistor dividers approach is that the user can set the trip

points of the UV and OV thresholds independently.

TIMER

Guidelines for Choosing Resistor Divider Values

The TIMER pin on the 34652 gives the user control over

the time base used to generate the timing sequences at start-

up. The same timer controls the retry delay when the device

experiences any fault. The TIMER pin can be left

unconnected for a default timer value of 200 ms or the user

can connect an external resistor (R_TIMER) between the

TIMER and VIN pins, as shown in Figure 19, page 18, to set

the timer value externally.

The total current flowing in the resistors is equal to the

supply voltage divided by the total series resistance. The

supply voltage can reach up to 80 V and the device will still

be in normal operation, the resistors connected and drawing

current. So the resistor values should be chosen high enough

to allow for a reasonable current to pass through them and

not dissipate a lot of power or cause input noise that would

trip the UV/OV detection circuit.

After the device passes the UVLO threshold and

continuously after that, the 34652 checks the TIMER pin for

any external components to determine the value of the timer.

During start-up and if any fault occurred, this timer value is

used when initiating a start-up sequence.

Another consideration is whether or not the values of the

resistors are readily available. The tolerance of the resistors

should be 1% or better to get an accurate reading.

Note Accuracy requirements are application dependent.

To demonstrate the importance of the accuracy of the

resistors, let’s look at a system with an operating range of

40 V for UV falling to 75 V for OV rising as an example. This

operating range will be scaled down for the device’s internal

circuitry to operate the UV/OV detection circuits. The scale

factor is 31.6 for UV and 57.1 for the OV. Taking overvoltage

as an example, this means that every 5.0 mV change on the

OV pin represents a 0.29 V change for the OV trip point on

the supply. Which says that an error of 5.0 mV due to the

resistors not being accurate will result in an error of 0.29 V for

the trip point, and depending on how close we are operating

to the OV rising threshold the device might detect an OV

condition and turn off the Power MOSFET prematurely. The

same argument applies to the UV pin.

Choosing the External Resistor R_TIMERValue

The user can change the value of the Start-Up Delay

Timer (t_TIMER) by adding a resistor (R_TIMER) between the

TIMER and VIN pins, as shown in Figure 19, page 18. The

timer value ranges between 100 ms and 1000 ms, with a

default value of 200 ms. Table 6 lists examples of R_TIMERfor

different values of the t_TIMERand Figure 20, page 20, shows

a plot of R_TIMERversus t_TIMER. It is recommended that the

closest 1% standard resistor value to the actual value be

chosen.

Note Accuracy requirements are application dependent.

To calculate the value of the R_TIMERresistor we use the

following equations:

t_TIMER(ms) = 20(ms) + 2.0 [R_TIMER(kΩ) + 1.0 kΩ]

Example of Calculations for Resistor Values

*

R_TIMER(kΩ) = [t_TIMER(ms) - 20(ms)] / 2.0 - 1.0 kΩ

The following equations are examples of calculating

resistor values using the same operating range as in the

previous paragraph:

Table 6. R_TIMERValues for Some Desired t_TIMERValues

R₃= 1.3 R₁V_UV(RISING)/ (V_OV(RISING)(V_UV(RISING)- 1.3))

t

(ms)

R

(kΩ)

t

(ms)

R

(kΩ)

*

TIMER

R₂= R₃(V_OV(RISING)/ V_UV(RISING)- 1)

100

150

200

250

300

350

400

450

500

39

600

650

700

750

800

850

900

950

1000

—

289

314

339

364

389

414

439

464

489

—

Where V_OV(RISING)= 75 V and V_UV(RISING)= 41 V

64

89

Note Some iteration may be required to get the right

values and also standard resistor values. The recommended

maximum value of the series resistance between the UV/OV

pins and VPWR pin is 500 kΩ.

Here we have two equations and three unknowns. If we

select a value for R₁of 487 kΩ, then from the first equation:

114

139

164

189

214

239

264

R₃= 8.72 kΩ

and the closest 1% standard resistor value is 8.66 kΩ.

Now, from the second equations we can solve for R₂:

R₂= 7.18 kΩ

and the closest 1% standard resistor value is 7.15 kΩ.

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

Archived by Freescale Semiconductor, Inc., 2008

TYPICAL APPLICATIONS

DISABLING AND ENABLING THE 34652

550

500

450

400

350

300

250

200

150

100

50

The Disable control input (DISABLE) provides two

functions:

• External enable/disable control.

• Manual resetting of the device and the retry counter after

a fault has occurred.

Using the DISABLE pin, a user can enable/disable the 34652

device, which facilitates easy access to connect the load to or

disconnect it from the main power rail.

When power is first applied, the DISABLE pin must be

inactive in order for the 34652 to initiate a start-up sequence.

If the DISABLE pin is active, the device makes no further

steps until the pin is inactive. If the DISABLE pin is activated

at any point during the start-up and thereafter during normal

operation, then the retry counter resets, the Power MOSFET

turns off, and the power good output signals deactivate. The

DISABLE circuit is equipped with a 1.0 ms filter to filter out

any glitches or transients on the DISABLE input and prevent

the Power MOSFET from turning off prematurely.

0

200

400

600

800

(ms)

1000 1200

t

TIMER

ttimer (ms)

Figure 20. External Resistor (R_TIMER) Value Versus

Start-Up and Retry Delay Timer Value (t_TIMER

)

The DISABLE pin is referenced to VPWR. If left open or

connected to VPWR, meaning the voltage at the DISABLE

pin is between V_PWR+ 1.2 V and V_PWR- 1.2 V, it is inactive

and the device is enabled. If a positive voltage (1.8 V above

V_PWR) or a negative voltage (1.8 V below V_PWR) is applied to

DISABLE, it is active and the device is disabled.

POWER GOOD OUTPUT SIGNALS

The power good pins PG and PG are output pins that are

used to directly enable a power module load. The device has

active high and active low power good output signals.

Choosing which power good active signal depends on the

Enable signal requirement of the load. This feature allows the

34652 to adapt to different applications and a wide variety of

loads.

CHARGING CURRENT LIMIT

When the device passes the UVLO threshold, it checks if

there is any external resistor or external capacitor connected

to the ICHG pin. If there is, then it determines the value of the

charging current limit value and the charging current limit rise

time accordingly. If there is not, it uses the default charging

current limit value of 100 mA and rise time of 1.0 ms.

The power good output signal is active if the Power

MOSFET is fully enhanced and the device is in normal

operation. The signal goes active after a typical 20 ms delay.

The signal deactivates if one of the following occurs:

Note Users are allowed to connect an external capacitor

to the ICHG pin only if an external resistor is also connected.

During the external components’ check, a capacitor produces

an impulse of current and an external resistor will be

detected, even it the external resistor is absent.

• Power is turned off.

• The device is disabled for more than 1.0 ms.

• The device exceeded its thermal shutdown threshold for

more than 12 μs.

• The device is in overvoltage or undervoltage mode for

When the Power MOSFET is turned on, the current limit is

set gradually from 0 A to I_CHG. This current charges up the

load capacitor relatively slowly. When the load capacitor is

fully charged, the Power MOSFET reaches its full

more than 1.0 ms.

• Load current exceeded the overcurrent limit for more than

3.0 ms.

When the power good output signal becomes inactive, it

disables the load, protecting it from any faults or damage.

These loads are usually DC/DC converters, depicted in

Figure 19, page 18. An LED can also be connected to PG to

indicate that the power is good.

enhancement, which triggers the current limit to change from

I_CHGto I_LIMand the load current to decrease. The power good

output signals activate after a 20 ms delay, which in turn

enables the load. The 34652 is now in normal operation

mode and the retry counter resets.

The PG and PG pins are referenced to VIN and require a

pull-up resistor connected to VPWR (Figures 18 and 19,

page 18).

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

Archived by Freescale Semiconductor, Inc., 2008

TYPICAL APPLICATIONS

The low charging current value of I_CHGis intended to limit

the temperature increase during the load capacitor charging

process, and the gradual rise to I_CHGis to prevent transient

dips in the input voltage due to sharp increases in the limit

current. This prevents the input voltage from drooping due to

current steps acting on the input line inductance, and that in

turn prevents a premature activation of the UV detection

circuit.

180

160

140

120

100

80

Choosing the External Resistor R_ICHGValue

The user can change the value of the charging current limit

by adding a resistor (R_ICHG) between the ICHG and VIN pins,

as shown in Figure 19, page 18. The charging current value

ranges between 50 mA and 500 mA, with a default value of

100 mA. Table 7 lists examples of R_ICHGfor different values

of I_CHGand Figure 21 shows a plot of R_ICHGversus I_CHG. It is

recommended that the closest 1% standard resistor value to

the actual value be chosen.

60

40

20

0

0.1

0.2

0.3

(A)

0.4

0.5

0.6

I

ICHG (A)

CHG

Note Accuracy requirements are application dependent.

Figure 21. External Resistor (R_ICHG) Value Versus

To calculate the value of the R_ICHGresistor we use the

following equations:

Charging Current Limit Value (I_CHG

)

I_CHG(A) = [R_ICHG(kΩ) + 1.4 kΩ] / 335

Choosing the External Capacitor C_ICHGValue

R_ICHG(kΩ) = 335 I_CHG(A) - 1.4 kΩ

*

The user can also change the charging current rise time by

adding a capacitor (C_ICHG) between the ICHG and VIN pins,

as shown in Figure 19, page 18. The charging current rise

time ranges between 1.0 ms (default value) and a

Table 7. R_ICHGValues for Some Desired I_CHGValues

I

(A)

R

(kΩ)

CHG

ICHG

recommended maximum of 10 ms. Table 8 lists examples of

C_ICHGfor different values of t_ICHGRand Figure 22 shows a

0.05

15.35

32.10

48.85

65.60

82.35

99.10

115.85

135.60

149.35

166.10

plot of C_ICHGversus t_ICHGR

.

0.1

0.15

0.2

To calculate the value of the C_ICHGcapacitor we use the

following equation:

C_ICHG(nF) = 1000 t_ICHGR(ms) / [3 R_ICHG(kΩ)]

*

0.25

0.3

Table 8. C_ICHGValues for Some Desired t_ICHGRValues

at a Specific I_CHGValue

0.35

0.4

C

(nF)

C

(nF)

C

(nF)

ICHG

t

(ms)

ICHGR

I

= 0.05 A

I

= 0.1 A

I

= 0.5 A

CHG

0.45

0.5

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10

21.72

43.43

10.38

2.01

20.77

31.15

41.54

51.92

62.31

72.69

83.07

93.46

103.84

4.01

6.02

65.15

86.86

8.03

108.58

130.29

152.01

173.72

195.44

217.16

10.03

12.04

14.05

16.05

18.06

20.07

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

Archived by Freescale Semiconductor, Inc., 2008

TYPICAL APPLICATIONS

to different requirements and operating environments. The

overcurrent value ranges between 0.35 A and 2.25 A, with a

default value of 1.0 A. Table 9 lists examples of R_ILIMfor

different values of I_LIMand Figure 23 shows a plot of R_ILIM

versus I_LIM. It is recommended that the closest 1% standard

resistor value to the actual value be chosen.

220

200

180

160

140

120

100

80

ICHG = 0.05 A

I

CHG

Note Accuracy requirements are application dependent.

To calculate the value of the R_ILIMresistor we use the

following equations:

ICHG = 0.1 A

I

I_LIM(A) = 129 / [R_ILIM(kΩ) + 1.4 kΩ]

R_ILIM(kΩ) = [129 / I_LIM(A)] - 1.4 kΩ

CHG

60

40

ICHG = 0.5 A

Table 9. R_ILIMValues for Some Desired I_LIMValues

I

CHG

20

I

(A)

R

(kΩ)

I

(A)

R

(kΩ)

LIM

ILIM

LIM

ILIM

0

0.35

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

367.65

321.52

256.93

213.88

183.12

160.06

142.12

127.77

116.02

106.24

97.96

1.5

84.71

79.33

74.58

70.36

66.58

63.18

60.11

57.31

56.01

—

0

1

2

3

4

5

6

7

8

9

10 11

t

(ms)

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.25

—

TIICCHHGGRR (ms)

Figure 22. Charging Current External Capacitor (C_ICHG

)

Versus Charging Current Rise Time (t_ICHGR

)

OVERCURRENT LIMIT

When in normal operation mode, the 34652 monitors the

load and compares (with a hysteresis) the current going

through a Sensor MOSFET with a reference current value

generated in reference to the current limit value I_LIM. If the

current going through the Sensor MOSFET becomes larger

than the reference current for more than 100 μs, the

overcurrent signal is asserted, the gate of the Power

MOSFET is discharged fast (in less than 10 μs) to try to

regulate the current, and the 34652 is in overcurrent mode for

3.0 ms. If after a 3.0 ms filter time the device is still in

overcurrent mode, the device turns off the Power MOSFET

and deactivates the power good output signals. The 34652

then initiates another start-up timer and goes back through

the enhancement process. If during the 3.0 ms timer the fault

was cleared where the load current was less than I_LIMminus

the hysteresis value, which is 12% of I_LIMvalue, then the

34652 goes back to the normal operation mode and the

power good output signals stay activated. This way the

device overcomes temporary overcurrent situations and at

the same time protects the load from more severe

—

90.86

—

400

350

300

250

200

150

100

50

overcurrent situations.

When the device passes the UVLO threshold, it checks if

there is any external resistor connected to the ILIM pin. If

there is, it determines the value of the overcurrent limit. If

there is not, it uses the default overcurrent limit value of 1.0 A.

It then uses the Sensor MOSFET to monitor the load for any

overcurrent conditions during operation as explained in the

previous paragraph.

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

ILIM (A)

Choosing the External Resistor R_ILIMValue

Figure 23. External Resistor (R_ILIM) Value Versus

Current Limit Value (I_LIM

The user can change the current limit by adding a resistor

(R_ILIM) between the ILIM and VIN pins, as shown in

)

Figure 19, page 18. This way the 34652 device is adaptable

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

Archived by Freescale Semiconductor, Inc., 2008

TYPICAL APPLICATIONS

SHORT CIRCUIT DETECTION

3500

3000

2500

If the current going through the load becomes >5.0 A, the

Power MOSFET is discharged very fast (in less than 10 μs)

to try to regulate the current, and the 34652 is in the

overcurrent mode for 3.0 ms. Then it follows the pattern

outlined in the Overcurrent Limit paragraph above.

Estimated for Area=1.7mm²

400 μF

200 μF

100 μF

POWER MOSFET ENERGY CAPABILITY

2000

1500

1000

Figure 24 shows a projected energy capability of the

device’s internal Power MOSFET under a drain to source

voltage of 82 V and an ambient temperature of 90°C. It is

compared to the energy levels required for the capacitive

loads of 100 μF, 200 μF, and 400 μF at 80 V for the

discharge periods of 16 ms, 32 ms, and 64 ms, respectively.

It is clear that the Power MOSFET well exceeds the required

energy capability for all three cases with a sufficient margin.

For example, the 400 μF capacitor load with a 64 ms

discharge time requires an energy capability of about

1540 mJ, which is well below the Power MOSFET capability

of about 3500 mJ. As a result of this analysis, the 33652 is

expected to more than meet all energy capability

500

0

20

40

60

Time (ms)

Figure 24. Projected Energy Capability of the Power

MOSFET Compared to the Required Energy Levels of

requirements for the possible capacitive loads.

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

23

Archived by Freescale Semiconductor, Inc., 2008

PACKAGING

PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

Important For the most current revision of the package, visit www.freescale.com and perform a keyword search on the “98A”

drawing number below:

EF SUFFIX (Pb-Free)

16-PIN SOIC NARROW BODY

PLASTIC PACKAGE

98ASB42566B

ISSUE M

34652

Analog Integrated Circuit Device Data

24

Freescale Semiconductor

Archived by Freescale Semiconductor, Inc., 2008

REVISION HISTORY

REVISION

6.0

DATE

2/2006

6/2006

DESCRIPTION OF CHANGES

•

Changed Document Order No.

•

Changed Max on DISABLE Input Current

Changed Overcurrent Limit in Steady State and in the text on page 11 and page 22

Updated PACKAGE DIMENSIONS on page 24

7.0

•

Updated to the current Freescale format and style

Added Part Number MCZ34652 in the Ordering Information

Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from

Maximum Ratings on page 5.

2/2007

8.0

•

Added Note Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC

standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels

(MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter

the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. on

page 5

34652

Analog Integrated Circuit Device Data

Freescale Semiconductor

25

Archived by Freescale Semiconductor, Inc., 2008

How to Reach Us:

Home Page:

www.freescale.com

Web Support:

http://www.freescale.com/support

USA/Europe or Locations Not Listed:

Freescale Semiconductor, Inc.

Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284

+1-800-521-6274 or +1-480-768-2130

www.freescale.com/support

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

www.freescale.com/support

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale Semiconductor assume any liability arising out of the application or use of any

product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters that may be

provided in Freescale Semiconductor data sheets and/or specifications can and do vary

in different applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer application by

customer’s technical experts. Freescale Semiconductor does not convey any license

under its patent rights nor the rights of others. Freescale Semiconductor products are

not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any other application in which the failure of the Freescale Semiconductor product

could create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs, damages, and expenses, and reasonable attorney fees arising out of,

directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Freescale

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064

Japan

0120 191014 or +81 3 5437 9125

support.japan@freescale.com

Asia/Pacific:

Freescale Semiconductor Hong Kong Ltd.

Technical Information Center

2 Dai King Street

Tai Po Industrial Estate

Tai Po, N.T., Hong Kong

+800 2666 8080

support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center

P.O. Box 5405

Semiconductor was negligent regarding the design or manufacture of the part.

Denver, Colorado 80217

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

All other product or service names are the property of their respective owners.

1-800-441-2447 or 303-675-2140

Fax: 303-675-2150

LDCForFreescaleSemiconductor@hibbertgroup.com

MC34652

Rev. 8.0

2/2007


型号：	MCZ34652EF
厂家：	NXP
描述：	1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-012AC, SOIC-16 光电二极管
文件：	总26页 (文件大小：1117K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCZ34652EF [NXP]

相关型号：

MCZ34652EF/R2

MCZ34652EFR2

MCZ34652EFR2SCALE

MCZ34653EF/R2

MCZ34670EG

MCZ34670EG/R2

MCZ34701EW

MCZ34701EW/R2

MCZ34701EWR2

MCZ34701EWR2

MCZ34702EW

MCZ34702EW/R2