MM908E624AYEW_技术文档

Document Number: MM908E624

Rev. 8.0, 3/2007

Freescale Semiconductor

Advance Information

Integrated Triple High-Side

Switch with Embedded MCU

and LIN Serial Communication

for Relay Drivers

908E624

HIGH-SIDE SWITCH

The 908E624 is an integrated single-package solution that

includes a high-performance HC08 microcontroller with a

SMARTMOS^TManalog control IC. The HC08 includes flash memory,

a timer, enhanced serial communications interface (ESCI), an

analog-to-digital converter (ADC), serial peripheral interface (SPI)

(only internal), and an internal clock generator module. The analog

control die provides three high-side outputs with diagnostic functions,

voltage regulator, watchdog, current sense operational amplifier, and

local interconnect network (LIN) physical layer.

The single-package solution, together with LIN, provides optimal

application performance adjustments and space-saving PCB design.

It is well suited for the control of automotive high-current motors

applications using relays (e.g., window lifts, fans, and sun roofs).

DWB SUFFIX

EW (Pb-FREE) SUFFIX

98ASA99294D

54-TERMINAL SOICW

Features

• High-Performance M68HC908EY16 Core

• 16 K Bytes of On-Chip Flash Memory, 512 Bytes of RAM

• Internal Clock Generator Module

• Two 16-Bit, 2-Channel Timers

• 10-Bit Analog-to-Digital Converter (ADC)

• LIN Physical Layer Interface

• Low Dropout Voltage Regulator

• Three High-Side Outputs

• Two Wake-Up Inputs

ORDERING INFORMATION

Temperature

Device

Package

Range (T_A)

MM908E624ACDWB/R2

*MM908E624ACEW/R2

*MM908E624AYEW/R2

-40°C to 85°C

-40°C to 125°C

54 SOICW

Notes* Recommended for new designs

• 16 Microcontroller I/Os

• Pb-Free Packaging Designated by Suffix Code EW

VBAT

908E624

VSUP1

VSUP2 HS3

LIN

Interface

VREFH

VDDA

EVDD

VCC

+5.0 V

L1

L2

VDD

VREFL

VSSA

EVSS

AGND

GND

HS1

RXD

M

PTE1/RXD

RST

RST_A

HS2

+E

IRQ

IRQ_A

PTD0/TACH0

PWMIN

To Microcontroller A/D Channel

PTA0-4

OUT

-E

PTB1; 3-7

PTC2-4

Microcontroller

Ports

PTD1/TACH1

WDCONF

Figure 1. 908E624 Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

INTERNAL BLOCK DIAGRAM

AGND

GND

VSUP2

VSUP1

PWMIN

RST_A

IRQ_A

WDCONF

LIN

RXD

PTE1/RXD

PTD0/TACH0

RST

IRQ

C R T P O

D D R C

D T R P O

D D R D

E R T P O

D D R

E

s

B u

a n r e I n t

l

VREFL

D D R A

A T R P O

D D R B

B R T P O

VSSA

EVSS

EVDD

VDDA

VREFH

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

TERMINAL CONNECTIONS

1

PTB7/AD7/TBCH1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

PTA0/KBD0

PTA1/KBD1

PTA2/KBD2

FLSVPP

PTA3/KBD3

PTA4/KBD4

VREFH

VDDA

EVDD

EVSS

VSSA

VREFL

PTE1/RXD

NC

RXD

WDCONF

+E

-E

OUT

VCC

AGND

VDD

NC

VSUP1

GND

LIN

VSUP2

2

PTB6/AD6/TBCH0

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

PTB5/AD5

PTB4/AD4

PTB3/AD3

IRQ

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

RST

PTB1/AD1

PTD0/TACH0

PTD1/TACH1

NC

PWMIN

RST_A

IRQ_A

NC

L1

L2

HS3

HS2

HS1

Figure 3. Terminal Connections

Table 1. Terminal Definitions

A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 18.

Die

Terminal

Terminal Name

Formal Name

Definition

These terminals are special-function, bidirectional I/O port terminals

that are shared with other functional modules in the MCU.

MCU

1

2

6

PTB7/AD7/TBCH1

PTB6/AD6/TBCH0

PTB5/AD5

Port B I/Os

7

PTB4/AD4

8

PTB3/AD3

11

PTB1/AD1

These terminals are special-function, bidirectional I/O port terminals

that are shared with other functional modules in the MCU.

MCU

3

4

5

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

Port C I/Os

This terminal is an asynchronous external interrupt input terminal.

MCU

—

9

IRQ

External Interrupt

Input

This terminal is bidirectional, allowing a reset of the entire system. It is

driven low when any internal reset source is asserted.

10

RST

External Reset

These terminals are special-function, bidirectional I/O port terminals

that are shared with other functional modules in the MCU.

12

13

PTD0/TACH0

PTD1/TACH1

Port D I/Os

Not connected.

14, 15, 16,

20, 21, 22,

32, 41

NC

No Connect

This terminal is a special-function, bidirectional I/O port terminal that

can is shared with other functional modules in the MCU.

MCU

42

PTE1/RXD

Port E I/O

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

3

TERMINAL CONNECTIONS

Table 1. Terminal Definitions (continued)

A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 18.

Die

Terminal

Terminal Name

Formal Name

Definition

These terminals are the reference voltage terminals for the analog-to-

digital converter (ADC).

MCU

43

48

VREFL

VREFH

ADC References

These terminals are the power supply terminals for the analog-to-digital

converter.

MCU

44

47

VSSA

VDDA

ADC Supply

Terminals

These terminals are the ground and power supply terminals,

respectively. The MCU operates from a single-power supply.

45

46

EVSS

EVDD

MCU Power Supply

Terminals

These terminals are special-function, bidirectional I/O port terminals

that are shared with other functional modules in the MCU.

49

50

52

53

54

PTA4/KBD4

PTA3/KBD3

PTA2/KBD2

PTA1/KBD1

PTA0/KBD0

Port A I/Os

For test purposes only. Do not connect in the application.

MCU

51

17

FLSVPP

PWMIN

Test Terminal

This terminal allows the enabling and PWM control of the high-side HS1

and HS2 terminals.

Analog

Direct High-Side

Control Input

This terminal is the reset output terminal of the analog die.

Analog

18

19

RST_A

IRQ_A

Internal Reset Output

This terminal is the interrupt output terminal of the analog die indicating

errors or wake-up events.

Internal Interrupt

Output

These terminals are the wake-up inputs of the analog chip.

Analog

23

24

L1

L2

Wake-Up Inputs

These output terminals are low R

high-side switches.

25

26

27

HS3

HS2

HS1

High-Side Output

DS(ON)

These terminals are device power supply terminals.

Analog

31

28

VSUP1

VSUP2

Power Supply

Terminals

This terminal represents the single-wire bus transmitter and receiver.

These terminals are device power ground connections.

Analog

29

LIN

LIN Bus

30

34

GND

AGND

Power Ground

Terminals

The +5.0 V voltage regulator output terminal is intended to supply the

embedded microcontroller.

Analog

33

35

36

VDD

VCC

OUT

Voltage Regulator

Output

This terminal is the single +5.0 V power supply for the current sense

operational amplifier.

Amplifier Power

Supply

This terminal is the output of the current sense operational amplifier.

Analog

Amplifier Output

Amplifier Inputs

These terminals are the current sense operational amplifier inverted

and non-inverted inputs.

37

38

-E

+E

This input terminal is for configuration of the watchdog period and

allows the disabling of the watchdog.

Analog

39

40

WDCONF

RXD

Window

Watchdog

Configuration

Terminal

This terminal is the output of LIN transceiver.

Analog

LIN Transceiver

Output

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

4

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent

damage to the device.

Rating

Symbol

Value

Unit

ELECTRICAL RATINGS

Supply Voltage

V

Analog Chip Supply Voltage under Normal Operation (Steady-State)

Analog Chip Supply Voltage under Transient Conditions

MCU Chip Supply Voltage

V

-0.3 to 27

-0.3 to 40

-0.3 to 5.5

SUP(SS)

V

SUP(PK)

V_DD

Input Terminal Voltage

Analog Chip

V

-0.3 to V +0.3

DD

IN(ANALOG)

Microcontroller Chip

V

-0.3 to V +0.3

SS DD

IN(MCU)

Maximum Microcontroller Current per Terminal

All Terminals except VDD, VSS, PTA0:PTA6, PTC0:PTC1

PTA0:PTA6, PTC0:PTC1 Terminals

mA

I

±15

±25

PIN(1)

PIN(2)

Maximum Microcontroller VSS Output Current

Maximum Microcontroller VDD Input Current

I

100

mA

MVSS

MVDD

I

Current Sense Operational Amplifier

Maximum Input Voltage, +E, -E Terminals

Maximum Input Current, +E, -E Terminals

Maximum Output Voltage, OUT Terminal

Maximum Output Current, OUT Terminal

V

-0.3 to 7.0

±20

V

mA

V

+E-E

I

+E-E

V

-0.3 to V +0.3

CC

OUT

I

±20

mA

OUT

LIN Supply Voltage

V

Normal Operation (Steady-State)

V

-18 to 40

BUS(SS)

Transient Input Voltage (per ISO7637 Specification) and with

External Components (Figure 4, page 15)

V

-150 to 100

BUS(PK)

L1 and L2 Terminal Voltage

Normal Operation with a 33 kΩ resistor (Steady-State)

V

-18 to 40

WAKE(SS)

WAKE(PK)

Transient Input Voltage (per ISO7637 Specification) and with

External Components (Figure 4, page 15)

V

-100 to 100

ESD Voltage

Human Body Model ⁽¹⁾

Machine Model ⁽¹⁾

Charge Device Model ⁽¹⁾

V

±2000

±100

ESD1

V

ESD2

ESD3

±500

Notes

1. ESD1 testing is performed in accordance with the Human Body Model (C_ZAP=100 pF, R_ZAP= 1500 Ω), the Machine Model (C_ZAP

=

200 pF, R_ZAP= 0 Ω), and the Charge Device Model, Robotic (C

=4.0 pF).

ZAP

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

5

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent

damage to the device.

Rating

Symbol

Value

Unit

THERMAL RATINGS

Package Operating Ambient Temperature ⁽⁴⁾

T

°C

A

MM908E624ACDWB and MM908E624ACEW

MM908E624AYEW

-40 to 85

-40 to 125

Operating Junction Temperature ⁽²⁾⁽⁴⁾

T

°C

J

-40 to 125

MM908E624ACDWB and MM908E624ACEW

MM908E624AYEW

Storage Temperature

T

-40 to 150

°C

STG

Peak Package Reflow Temperature During Solder Mounting ⁽³⁾

T

SOLDER

DWB Suffix

245

260

EW (Pb-Free) Suffix

Notes

2. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because

of higher power dissipation of the analog die. The analog die junction temperature must not exceed 150°C under these conditions.

3. Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

4. Independent of T_A,device parametrics are only guaranteed for -40 < T_J< 125°C . Please see note 2. T_Jis a factor of power dissipation,

package thermal resistance, and available heat sinking.

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

6

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values

noted reflect the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SUPPLY VOLTAGE RANGE

Nominal Operating Voltage

V

5.5

—

18

27

V

SUP

Functional Operating Voltage ⁽⁵⁾

SUPPLY CURRENT RANGE

Normal Mode ⁽⁶⁾

V

SUPOP

V

= 13.5 V, Analog Chip in Normal Mode, MCU Operating Using

SUP

Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC

Enabled

I

—

20

60

35

—

75

45

mA

µA

RUN

,

(7)

Stop Mode ⁽⁶⁾

V

= 13.5 V, LIN in recessive state

I

SUP

STOP

,

(7)

Sleep Mode ⁽⁶⁾

V

= 13.5 V, LIN in recessive state

I

SUP

SLEEP

DIGITAL INTERFACE RATINGS (ANALOG DIE)

Output Terminal RST_A

Low-State Output Voltage (I_OUT= -1.5 mA)

High-State Output Current (V_OUT> 3.5 V)

Pulldown Current Limitation

V_OL

I_OH

—

250

—

0.4

—

V

µA

mA

I_{OL_MAX}

-1.5

-8.0

Output Terminal IRQ_A

V

Low-State Output Voltage (I_OUT= -1.5 mA)

High-State Output Voltage (I_OUT= 250 µA)

V_OL

V_OH

—

0.4

—

3.85

Output Terminal RXD

Low-State Output Voltage (I_OUT= -1.5 mA)

High-State Output Voltage (I_OUT= 250 µA)

V_OL

V_OH

C_IN

—

3.85

—

0.4

—

V

Capacitance ⁽⁸⁾

4.0

—

pF

Input Terminal PWMIN

Input Logic Low Voltage

Input Logic High Voltage

Input Current

V_IL

V_IH

I_IN

—

3.5

-10

—

1.5

—

V

—

10

—

µA

pF

Capacitance ⁽⁸⁾

Terminal TXD, SS–Pullup Current

Notes

C_IN

4.0

I

—

40

—

µA

PU

5. Device is fully functional. All functions are operating. Overtemperature may occur.

6. Total current (I + I ) measured at GND terminal.

VSUP1

VSUP2

7. Stop and Sleep mode current will increase if V_SUPexceeds 15 V.

8. This parameter is guaranteed by process monitoring but is not production tested.

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values

noted reflect the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

SYSTEM RESETS AND INTERRUPTS

Symbol

Min

Typ

Max

Unit

Low-Voltage Reset (LVR)

Threshold

V

LVRON

3.6

4.0

4.4

Low-Voltage Interrupt (LVI)

Threshold

V

5.7

—

6.0

1.0

6.6

—

LVI

Hysteresis

V

LVI_HYS

High-Voltage Interrupt (HVI)

Threshold

V

18

—

19.25

220

20.5

—

V

HVI

Hysteresis

mV

HVI_HYS

VOLTAGE REGULATOR ⁽⁹⁾

Normal Mode Output Voltage

V

DDRUN

2.0 mA < I

< 50 mA, 5.5 V < V

< 27 V

SUP

4.75

50

5.0

5.25

200

DD

Normal Mode Output Current Limitation ⁽¹⁰⁾

I

110

mA

V

DDRUN

Dropout Voltage

V

DDDROP

V

_SUP= 4.9 V, I

= 50 mA

—

0.1

0.2

DD

Stop Mode Output Voltage ⁽¹¹⁾

Stop Mode Regulator Current Limitation

Line Regulation

V

4.75

4.0

5.0

8.0

5.25

14

V

DDSTOP

I

mA

mV

Normal Mode, 5.5 V < V

< 27 V, I = 10 mA

DD

V

—

20

10

150

100

SUP

LRRUN

Stop Mode, 5.5 V < V

< 27 V, I

= 2.0 mA

DD

V

SUP

LRSTOP

Load Regulation

Normal Mode, 1.0 mA < I < 50 mA, V_SUP= 18 V

mV

V

—

40

150

DD

LRRUN

Stop Mode, 1.0 mA < I

< 5.0 mA, V_SUP= 18 V

V

DD

LDSTOP

Overtemperature Pre-Warning (Junction) ⁽¹²⁾

Thermal Shutdown Temperature (Junction) ⁽¹²⁾

Temperature Threshold Difference

T

120

155

135

170

160

—

°C

PRE

T

SD

∆T

T

SD- PRE

T

-T

20

30

45

SD PRE

Notes

9. Specification with external capacitor 2.0 µF< C < 10 µF and 200 mΩ ≤ ESR ≤ 10 Ω. Capacitor value up to 47 µF can be used.

10. Total V_DDregulator current. A 5.0 mA current for current sense operational amplifier is included. Digital output supplied from VDD.

11. When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage

specification.

12. This parameter is guaranteed by process monitoring but not production tested

908E624

Analog Integrated Circuit Device Data

8

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values

noted reflect the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

WINDOW WATCHDOG CONFIGURATION TERMINAL (WDCONF)

External Resistor Range

Symbol

Min

Typ

Max

Unit

R

10

—

100

15

kΩ

EXT

Watchdog Period Accuracy with External Resistor

(Excluding Resistor Accuracy) ⁽¹³⁾

WD

%

CACC

-15

LIN PHYSICAL LAYER

LIN Transceiver Output Voltage

V

Recessive State, TXD HIGH, I

= 1.0 µA

V

V_SUP-1

—

OUT

LIN_REC

Dominant State, TXD LOW, 500 Ω External Pullup Resistor

Normal Mode Pullup Resistor to VSUP

Stop, Sleep Mode Pullup Current Source

Output Current Shutdown Threshold

V

1.4

LIN_DOM

R

20

—

50

30

2.0

75

60

—

kΩ

µA

mA

µA

PU

I

PU

I

150

OV-CUR

Leakage Current to GND

I

BUS

VSUP Disconnected, V

at 18 V

—

0.0

-1.0

1.0

3.0

—

10

20

BUS

Recessive State, 8.0 V ≤ V

≤ 18 V, 8.0 V≤ V

≤ 18 V, V

≥ V

BUS SUP

SUP

BUS

1.0

GND Disconnected, V

= V

, V

at -18 V

GND

SUP BUS

LIN Receiver

V

SUP

Receiver Threshold Dominant

Receiver Threshold Recessive

Receiver Threshold Center

Receiver Threshold Hysteresis

V_{BUS_DOM}

V_{BUS_REC}

V_{BUS_CNT}

V_{BUS_HYS}

—

0.6

—

0.4

—

0.475

—

0.5

—

0.525

0.175

Notes

13. Watchdog timing period calculation formula: P_WD= 0.991 R_EXT+0.648 (R_EXTin kΩ and P_WDin ms).

*

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values

noted reflect the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

HIGH-SIDE OUTPUTS HS1 AND HS2

Symbol

Min

Typ

Max

Unit

Switch On Resistance

R

Ω

DS(ON)

T_J= 25°C, I_LOAD= 150 mA, V

> 9.0 V

—

2.0

—

2.5

4.5

—

SUP

T_J= 125°C, I_LOAD= 150 mA, V

SUP

3.0

T_J= 125°C, I_LOAD= 120 mA, 5.5 V < V

> 9.0 V

SUP

Output Current Limit

I

300

155

—

600

190

10

LIM

mA

°C

,

Overtemperature Shutdown ⁽¹⁴⁾

(15)

T_HSSD

Leakage Current

I

µA

LEAK

Output Clamp Voltage

V

CL

I

= -100 mA

-6.0

—

OUT

HIGH-SIDE OUTPUT HS3

Switch On Resistance

R

Ω

DS(ON)

T_J= 25°C, I_LOAD= 50 m A, V

> 9.0 V

—

7.0

10

14

SUP

T_J= 125°C, I_LOAD= 50 mA, V

> 9.0 V

SUP

T_J= 125°C, I_LOAD= 30 mA, 5.5 V < V

> 9.0 V

SUP

Output Current Limitation

I

60

155

—

100

—

200

190

10

LIM

mA

°C

,

Overtemperature Shutdown ⁽¹⁴⁾

Leakage Current

Notes

(15)

T

HSSD

LEAK

I

—

µA

14. This parameter is guaranteed by process monitoring but it is not production tested

15. When overtemperature occurs, switch is turned off and latched off. Flag is set in SPI.

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

10

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values

noted reflect the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

CURRENT SENSE OPERATIONAL AMPLIFIER

Rail-to-Rail Input Voltage

Symbol

Min

Typ

Max

Unit

V

-0.1

—

V

+0.1

CC

V

IMC

Output Voltage Range

Output Current ±1.0 mA

Output Current ±5.0 mA

V

0.1

0.3

—

V

-0.1

-0.3

OUT1

OUT2

CC

Input Bias Current

Input Offset Current

Input Offset Voltage

L1 AND L2 INPUTS

Low Detection Threshold

I

—

250

nA

B

I

-100

-25

100

25

O

V

mV

IO

V

THL

THH

HYS

5.5 V < V

6.0 V < V

< 6.0 V

< 18 V

< 27 V

2.0

2.5

2.7

2.5

3.0

3.2

3.0

3.5

3.7

SUP

18 V < V

High Detection Threshold

V

5.5 V < V

< 6.0 V

< 18 V

< 27 V

2.7

3.0

3.5

3.3

4.0

4.2

3.8

4.5

4.7

SUP

6.0 V < V

18 V < V

Hysteresis

V

5.5 V < V

< 27 V

0.5

-10

—

1.3

10

SUP

Input Current

I

µA

IN

-0.2 V < V < 40 V

IN

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the

microcontroller chip. Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

LIN PHYSICAL LAYER

,

(17)

Driver Characteristics for Normal Slew Rate ⁽¹⁶⁾

Dominant Propagation Delay TXD to LIN

Recessive Propagation Delay TXD to LIN

t

—

50

—

11

µs

DOM-MIN

t

DOM-MAX

t

—

REC-MIN

REC-MAX

dt1

t

—

Propagation Delay Symmetry: t

- t

-10.44

—

DOM-MIN REC-MAX

Propagation Delay Symmetry: t

- t

DOM-MAX REC-MIN

dt2

,

(18)

Driver Characteristics for Slow Slew Rate ⁽¹⁶⁾

Dominant Propagation Delay TXD to LIN

Recessive Propagation Delay TXD to LIN

t

—

100

—

µs

DOM-MIN

t

DOM-MAX

t

—

REC-MIN

REC-MAX

dt1s

t

—

Propagation Delay Symmetry: t

- t

-22

—

DOM-MIN REC-MAX

- t

23

DOM-MAX REC-MIN

dt2s

Driver Characteristics for Fast Slew Rate

LIN High Slew Rate (Programming Mode)

Receiver Characteristics and Wake-Up Timings

Receiver Dominant Propagation Delay ⁽¹⁹⁾

Receiver Recessive Propagation Delay ⁽¹⁹⁾

Receiver Propagation Delay Symmetry

Bus Wake-Up Deglitcher

SR

t

—

15

—

V/µs

FAST

—

3.5

—

6.0

2.0

150

—

µs

RL

t

RH

t

-2.0

35

R-SYM

WL

t

—

PROP

Bus Wake-Up Event Reported ⁽²⁰⁾

t

—

20

WAKE

Notes

16.

V

from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 kΩ, 6.8 nF/660 Ω, 10 nF/500 Ω. Measurement thresholds: 50% of TXD signal

SUP

to LIN signal threshold defined at each parameter.

17. See Figure 6, page 15.

18. See Figure 7, page 16.

19. Measured between LIN signal threshold V or V and 50% of RXD signal.

IL

IH

20.

t

is typically 2 internal clock cycles after LIN rising edge detected. See Figure 8 and Figure 9, page 16. In Sleep mode the V

DD

WAKE

rise time is strongly dependent upon the decoupling capacitor at VDD terminal.

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the

microcontroller chip. Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

LIN PHYSICAL LAYER (CONTINUED)

Symbol

Min

Typ

Max

Unit

Output Current Shutdown Delay

SPI INTERFACE TIMING

t

—

10

—

µs

OV-DELAY

SPI Operating Recommended Frequency

L1 AND L2 INPUTS

f

0.25

8.0

—

4.0

38

MHz

µs

SPIOP

Wake-Up Filter Time ⁽²¹⁾

t

20

WUF

PWD

WINDOW WATCHDOG CONFIGURATION TERMINAL (WDCONF)

Watchdog Period

ms

External Resistor R_EXT= 10 kΩ (1%)

External Resistor R_EXT= 100 kΩ (1%)

Without External Resistor R_EXT(WDCONF Terminal Open)

—

97

10.558

99.748

150

—

205

STATE MACHINE TIMING

Reset Low-Level Duration after V_DDHigh ⁽²⁵⁾

Interrupt Low-Level Duration

t

0.65

7.0

97

1.0

10

1.35

13

ms

µs

ms

µs

RST

t

INT

NRTOUT

Normal Request Mode Timeout ⁽²⁵⁾

t

150

3.0

35

205

10

,

Delay Between SPI Command and HS1/HS2/HS3 Turn On ⁽²²⁾

Delay Between SPI Command and HS1/HS2/HS3 Turn Off ⁽²²⁾

(23)

t_S-HSON

t_S-HSOFF

t_S-NR2N

—

10

Delay Between Normal Request and Normal Mode After W/D Trigger

Command ⁽²⁴⁾

6.0

70

Delay Between SS Wake-Up (SS LOW to HIGH) and Normal Request Mode

(VDD On and Reset High)

t_W-SS

µs

15

40

80

Delay Between SS Wake-Up (SS LOW to HIGH) and First Accepted SPI

Command

t_W-SPI

90

30

15

—

N/A

—

Delay Between Interrupt Pulse and First SPI Command Accepted

Minimum Time Between Two Rising Edges on SS

Notes

t_S-1STSPI

t_2SS

µs

21. This parameter is guaranteed by process monitoring but is not production tested.

22. Delay between turn-on or turn-off command and high-side on or high-side off, excluding rise or fall time due to external load.

23. Delay between the end of the SPI command (rising edge of the SS) and start of device activation/deactivation.

24. This parameter is guaranteed by process monitoring but it is not production tested.

25. Also see Figure 10 on page 17

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

ELECTRICAL CHARACTERISTICS

MICROCONTROLLER PARAMETRICS

Table 4. Dynamic Electrical Characteristics (continued)

All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the

microcontroller chip. Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

CURRENT SENSE OPERATIONAL AMPLIFIER

Supply Voltage Rejection Ratio ⁽²⁶⁾

Common Mode Rejection Ratio ⁽²⁶⁾

Gain Bandwidth ⁽²⁶⁾

Symbol

Min

Typ

Max

Unit

SVR

CMR

GBP

SR

60

70

1.0

0.5

40

—

85

—

dB

MHz

V/µs

°

Slew Rate

Phase Margin (for Gain = 1, Load 100 pF/ 5.0 kΩ ⁽²⁶⁾

Open Loop Gain

PHMO

OLG

dB

Notes

26. This parameter is guaranteed by process monitoring but it is not production tested.

MICROCONTROLLER PARAMETRICS

Table 5. Microcontroller

For a detailed microcontroller description, refer to the MC68HC908EY16 data sheet.

Module

Description

Core

Timer

Flash

RAM

ADC

SPI

High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz

Two 16-Bit Timers with 2 Channels (TIM A and TIM B)

16 K Bytes

512 Bytes

10-Bit Analog-to-Digital Converter

SPI Module

ESCI

Standard Serial Communication Interface (SCI) Module

Bit-Time Measurement

Arbitration

Prescaler with Fine Baud-Rate Adjustment

ICG

Internal Clock Generation Module

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

Transient Pulse

Generator

LIN, L1, and L2

10 kΩ

10k

1.0 nF

1nF

Note Waveform in accordance with ISO7637 Part 1, Test Pulses 1, 2, 3a, and 3b.

Figure 4. Test Circuit for Transient Test Pulses

V_SUP

VSUP

R0

TXD

R0 and C0 Combinations:

R0 and C0 combinations:

LIN

• 1.0 kΩ and 1.0 nF

RXD

- 1k Ohm and 1nF

• 600 Ω and 6.8 nF

- 660 Ohm and 6.8nF

• 500 Ω and 10 nF

C0

- 500 Ohm and 10nF

Figure 5. Test Circuit for LIN Timing Measurements

TXD

LIN

t_REC-MAX

t_DOM-MIN

58.1% V_SUP

40% V_SUP

74.4% V_SUP

VLIN_REC

60% V_SUP

28.4% V_SUP

42.2% V_SUP

t_DOM-MAX

t_REC-MIN

RXD

t_RL

t_RH

Figure 6. LIN Timing Measurements for Normal Slew Rate

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

TXD

LIN

t_REC-MAX

t_DOM-MIN

61.6% V_SUP

40% V_sup

25.1% V_SUP

VLIN_REC

77.8% V_SUP

60% V_SUP

38.9% V_SUP

t_DOM-MAX

t_REC-MIN

RXD

t_RL

t_RH

Figure 7. LIN Timing Measurements for Slow Slew Rate

LIN

VLIN_REC

0.4VSUP

0.4 V_SUP

Dominant level

Dominant Level

VDD

t

WAKE

Twake

PROPWL

TpropWL

Figure 8. Wake-Up Sleep Mode Timing

LIN

VLIN_REC

0.4VSUP

0.4 V_SUP

Dominant level

Dominant Level

IRQ_A

t

WAKE

Twake

PROPWL

TpropWL

Figure 9. Wake-Up Stop Mode Timing

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

V_SUP

V_DD

RST_A

t_RST

t_NRTOUT

Figure 10. Power On Reset and Normal Request Time-out Timing

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 908E624 was designed and developed as a highly

integrated and cost-effective solution for automotive and

industrial applications. For automotive body electronics, the

908E624 is well suited to perform relay control in applications

like window lift, sunroof, etc., via a three-wire LIN bus.

high-side outputs. Other ports are also provided, which

include a current sense operational amplifier port and two

wake-up terminals. An internal voltage regulator provides

power to the MCU chip.

Also included in this device is a LIN physical layer, which

communicates using a single wire. This enables this device

to be compatible with three-wire bus systems, where one wire

is used for communication, one for battery, and one for

ground.

The device combines an HC908EY16 MCU core with flash

memory together with a SmartMOS IC chip. The SmartMOS

IC chip combines power and control in one chip. Power

switches are provided on the SmartMOS IC configured as

FUNCTIONAL TERMINAL DESCRIPTION

See Figure 1, 908E624 Simplified Application Diagram,

page 1, for a graphic representation of the various terminals

referred to in the following paragraphs. Also, see the terminal

diagram on page 3 for a depiction of the terminal locations on

the package.

PORT D I/O TERMINALS (PTD:0:1)

PTD1/TACH1 and PTD0/TACH0/BEMF are special-

function, bidirectional I/O port terminals that can also be

programmed to be timer terminals.

For details, refer to the 68HC908EY16 data sheet.

PORT A I/O TERMINALS (PTA0:4)

PORT E I/O TERMINAL (PTE1)

These terminals are special-function, bidirectional I/O port

terminals that are shared with other functional modules in the

MCU. PTA0:PTA4 are shared with the keyboard interrupt

terminals KBD0:KBD4.

PTE1/RXD and PTE0/TXD are special-function,

bidirectional I/O port terminals that can also be programmed

to be enhanced serial communication.

PTE0/TXD is internally connected to the TXD terminal of

the analog die. The connection for the receiver must be done

externally.

The PTA5/SPSCK terminal is not accessible in this device

and is internally connected to the SPI clock terminal of the

analog die. The PTA6/SS terminal is likewise not accessible.

For details, refer to the 68HC908EY16 data sheet.

EXTERNAL INTERRUPT TERMINAL (IRQ)

PORT B I/O TERMINALS (PTB1:7)

The IRQ terminal is an asynchronous external interrupt

terminal. This terminal contains an internal pullup resistor that

is always activated, even when the IRQ terminal is pulled

LOW.

These terminals are special-function, bidirectional I/O port

terminals that are shared with other functional modules in the

MCU. All terminals are shared with the ADC module. The

PTB6:PTB7 terminals are also shared with the Timer B

module.

For details, refer to the 68HC908EY16 data sheet.

The PTB0/AD0 and PTB2/AD2 terminals are not

accessible in this device.

EXTERNAL RESET TERMINAL (RST)

For details, refer to the 68HC908EY16 data sheet.

A logic [0] on the RST terminal forces the MCU to a known

startup state. It is driven LOW when any internal reset source

is asserted.

PORT C I/O TERMINALS (PTC2:4)

This terminal contains an internal pullup resistor that is

always activated, even when the reset terminal is pulled

LOW.

These terminals are special-function, bidirectional I/O port

terminals that are shared with other functional modules in the

MCU. For example, PTC2:PTC4 are shared with the ICG

module.

Important To ensure proper operation, do not add any

external pullup resistor.

PTC0/MISO and PTC1/MOSI are not accessible in this

device and are internally connected to the MISO and MOSI

SPI terminals of the analog die.

For details, refer to the 68HC908EY16 data sheet.

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

FUNCTIONAL DESCRIPTION

FUNCTIONAL TERMINAL DESCRIPTION

MCU POWER SUPPLY TERMINALS

(EVDD AND EVSS)

INTERRUPT TERMINAL (IRQ_A)

EVDD and EVSS are the power supply and ground

terminals, respectively. The MCU operates from a single-

power supply.

IRQ_A is the interrupt output terminal of the analog die

indicating errors or wake-up events. This terminal must be

connected to the IRQ terminal of the MCU.

Fast signal transitions on MCU terminals place high, short-

duration current demands on the power supply. To prevent

noise problems, take special care to provide power supply

bypassing at the MCU.

WINDOW WATCHDOG CONFIGURATION

TERMINAL (WDCONF)

This terminal is the configuration terminal for the internal

watchdog. A resistor is connected to this terminal. The

resistor value defines the watchdog period. If the terminal is

open, the watchdog period is fixed to its default value.

For details, refer to the 68HC908EY16 data sheet.

ADC SUPPLY TERMINALS (VDDA AND VSSA)

VDDA and VSSA are the power supply terminals for the

analog-to-digital converter (ADC). It is recommended that a

high-quality ceramic decoupling capacitor be placed between

these terminals.

The watchdog can be disabled (e.g., for flash

programming or software debugging) by connecting this

terminal to GND.

POWER SUPPLY TERMINALS

(VSUP1AND VSUP2)

Important VDDA is the supply for the ADC and should be

tied to the same potential as EVDD via separate traces.

VSSA is the ground terminal for the ADC and should be tied

to the same potential as EVSS via separate traces.

This VSUP1 power supply terminal supplies the voltage

regulator, the internal logic, and LIN transceiver.

For details, refer to the 68HC908EY16 data sheet.

This VSUP2 power supply terminal is the positive supply

for the high-side switches.

ADC REFERENCE TERMINALS

(VREFL AND VREFH)

POWER GROUND TERMINAL (GND)

VREFL and VREFH are the reference voltage terminals for

the ADC. It is recommended that a high-quality ceramic

decoupling capacitor be placed between these terminals.

This terminal is the device ground connection.

HIGH-SIDE OUTPUT TERMINALS (HS1 AND HS2)

Important VREFH is the high reference supply for the

ADC and should be tied to the same potential as VDDA via

separate traces. VREFL is the low reference supply for the

ADC and should be tied to the same potential as VSSA via

separate traces.

These terminals are high-side switch outputs to drive loads

such as relays or lamps. Each switch is protected with

overtemperature and current limit (overcurrent). The output

has an internal clamp circuitry for inductive load. The HS1

and HS2 outputs are controlled by SPI and have a direct

enabled input (PWMIN) for PWM capability.

For details, refer to the 68HC908EY16 data sheet.

TEST TERMINAL (FLSVPP)

HIGH-SIDE OUTPUT TERMINAL (HS3)

This terminal is for test purposes only. Do not connect in

the application or connect to GND.

This high-side switch can be used to drive small lamps,

Hall-effect sensors, or switch pullup resistors. The switch is

protected with overtemperature and current limit

PWMIN TERMINAL (PWMIN)

(overcurrent). The output is controlled only by SPI.

This terminal is the direct PWM input for high-side

outputs 1 and 2 (HS1 and HS2). If no PWM control is

required, PWMIN must be connected to VDD to enable the

HS1 and HS2 outputs.

LIN BUS TERMINAL (LIN)

The LIN terminal represents the single-wire bus

transmitter and receiver. It is suited for automotive bus

systems and is based on the LIN bus specification.

LIN TRANSCEIVER OUTPUT TERMINAL (RXD)

This terminal is the output of LIN transceiver. The terminal

must be connected to the microcontroller’s Enhanced Serial

Communications Interface (ESCI) module (RXD terminal).

WAKE-UP TERMINALS (L1 AND L2)

These terminals are high-voltage capable inputs used to

sense external switches and to wake up the device from

Sleep or Stop mode. During Normal mode the state of these

terminals can be read through SPI.

RESET TERMINAL (RST_A)

RST_A is the reset output terminal of the analog die and

must be connected to the RST terminal of the MCU.

Important If unused these terminals should be connected

to VSUP or GND to avoid parasitic transitions. In Low Power

Mode this could lead to random wakeup events.

Important To ensure proper operation, do not add any

external pullup resistor.

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

FUNCTIONAL DESCRIPTION

FUNCTIONAL TERMINAL DESCRIPTION

intended to supply the embedded microcontroller. The

terminal is protected against shorts to GND with an integrated

current limit (temperature shutdown could occur).

CURRENT SENSE OPERATIONAL AMPLIFIER

TERMINALS (E+, E-, OUT, VCC)

These are the terminals of the single-supply current sense

operational amplifier.

Important The VDD, EVDD, VDDA, and VREFH terminals

must be connected together.

• The E+ and E- input terminals are the non-inverting and

inverting inputs of the current sense operational

amplifier, respectively.

• The OUT terminal is the output terminal of the current

sense operational amplifier.

VOLTAGE REGULATOR AND CURRENT SENSE

AMPLIFIER GROUND TERMINAL (AGND)

The AGND terminal is the ground terminal of the voltage

regulator and the current sense operational amplifier.

• The VCC terminal is the +5.0 V single-supply

connection.

Important GND, AGND, VSS, EVSS, VSSA, and VREFL

terminals must be connected together.

Note If the operational amplifier is not used, it is possible

to connect all terminals (E+, E-, OUT and VCC) to GND - in

this case all of the four terminals must be grounded.

NO CONNECT TERMINALS (NC)

The NC terminals are not connected internally.

+5.0 V VOLTAGE REGULATOR OUTPUT

TERMINAL (VDD)

Note Each of the NC terminals can be left open or

connected to ground (recommended).

The VDD terminal is needed to place an external capacitor

to stabilize the regulated output voltage. The VDD terminal is

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Wake-up from Stop mode is initiated by a wake-up

interrupt. Wakeup from Sleep mode is done by a reset and

the voltage regulator is turned back on.

908E624 ANALOG DIE MODES OF OPERATION

The 908E624 offers three operating modes: Normal (Run),

Stop, and Sleep. In Normal mode the device is active and is

operating under normal application conditions. The Stop and

Sleep modes are low-power modes with wake-up

capabilities.

The selection of the different modes is controlled by the

MODE1:2 bits in the SPI Control register.

Figure 11 describes how transitions are done between the

different operating modes and Table 6, page 22, gives an

overview of the operating mode.

In Stop mode the voltage regulator still supplies the MCU

with V (limited current capability) and in Sleep mode the

DD

voltage regulator is turned off (V = 0 V).

DD

Normal Request Timeout Expired (t_NRTOUT

)

Normal Request timeout expired (NR_TOUT

)

V

Low

V

DD

V_DDHigh and

Power Up

Reset Delay (t

) Expired

V_DDHigh and Reset Delay (t_RST) expired

RST

Power

Normal

Reset

Down

Request

V_DDLow

Normal

WD Failed

WD failed

V_DDLL_owO₍W_>NR(>t_N

_reT) Expired

d

V_DD

)

_TOUTR

e

T

x

O

pi

U

^anda^VSn^Ud^VL⁼V⁰F = 0

Sleep Command

SLEEP Command

Wake-Up (Reset)

Sleep

Stop

V_VLow

_DDLow

DD

Legend

WD: Watchdog

Notes:

WD Disabled: Watchdog disabled (WDCONF terminal connected to GND)

WD - means Watchdog

WD Trigger: Watchdog is triggered by SPI command

WD disabled - means Watchdog disabled (WDCONF terminal connected to GND)

WD Failed: No watchdog trigger or trigger occurs in closed window

WD trigger – means Watchdog is triggered by SPI command

Stop Command: Stop command sent via SPI

WD failed – means no Watchdog trigger or trigger occurs in closed window

Sleep Command: Sleep command sent via SPI

STOP Command - means STOP command sent via SPI

Wake-Up: L1 or L2 state change or LIN bus wake-up or SS rising edge

SLEEP Command - means SLEEP command send via SPI

Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge

Figure 11. Operating Modes and Transitions

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Table 6. Operating Modes Overview

Device

Mode

Wake-Up

Capabilities

Watchdog

Function

HS1, HS2,

and HS3

Sense

Amplifier

RST_A

Output

Voltage Regulator

_DDON

LIN Interface

Reset

V

N/A

LOW

HIGH

Disabled

Enabled

Recessive only

Not active

Normal

Request

V_DDON

N/A

150 ms time out if

WD enabled

Transmit and

receive

Normal

(Run)

V_DDON

N/A

HIGH

Window WD if

enabled

Enabled

Disabled

Transmit and

receive

Active

Stop

V_DDON with limited

current capability

LIN wake-up,

L1, L2 state change,

SS rising edge

Disabled

Recessive state with Not active

wake-up capability

Sleep

V

_DDOFF

LIN wake-up

L1, L2 state change

LOW

Disabled

Recessive state with Not active

wake-up capability

INTERRUPTS

Wake-Up Interrupts

In Normal (Run) mode the 908E624 has four different

interrupt sources. An interrupt pulse on the IRQ_A terminal is

generated to report a fault to the MCU. All interrupts are not

maskable and cannot be disabled.

In Stop mode the IRQ_A terminal reports wake-up events

on the L1, L2, or the LIN bus to the MCU. All wake-up

interrupts are not maskable and cannot be disabled.

After a wake-up interrupt, the INTSRC bit in the Serial

Peripheral Interface (SPI) Status register is set, indicating the

source of the event. This wake-up source information is only

transferred once, and the INTSRC bit is cleared

automatically.

After an Interrupt the INTSRC bit in the SPI Status register

is set, indicating the source of the event. This interrupt source

information is only transferred once, and the INTSRC bit is

cleared automatically.

Figure 12, page 23, describes the Stop/Wake-Up

procedure.

Low-Voltage Interrupt

Low-voltage interrupt (LVI) is related to external supply

voltage VSUP1. If this voltage falls below the LVI threshold,

it will set the LVF bit in the SPI Status register and an interrupt

will be initiated. The LVF bit remains set as long as the Low-

voltage condition is present.

Voltage Regulator Temperature Prewarning (VDDT)

Voltage regulator temperature prewarning (VDDT) is

generated if the voltage regulator temperature is above the

T

threshold. It will set the VDDT bit in the SPI Status

PRE

During Sleep and Stop mode the low-voltage interrupt

circuitry is disabled.

register and an interrupt will be initiated. The VDDT bit

remains set as long as the error condition is present.

During Sleep and Stop mode the voltage regulator

temperature prewarning circuitry is disabled.

High-Voltage Interrupt

High-voltage interrupt (HVI) is related to external supply

voltage VSUP1. If this voltage rises above the HVI threshold,

it will set the HVF bit in the SPI Status register and an

interrupt will be initiated. The HVF bit remains set as long as

the high-voltage condition is present.

High-Side Switch Thermal Shutdown (HSST)

The high-side switch thermal shutdown HSST is

generated if one of the high-side switches HS1:HS3 is above

the HSST threshold, it will shutdown all high-side switches,

set the HSST flag in the SPI Status register and an interrupt

will be initiated. The HSST bit remains set as long as the error

condition is present.

During Sleep and Stop mode the high-voltage interrupt

circuitry is disabled.

During Sleep and Stop mode the high-side switch thermal

shutdown circuitry is disabled.

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

MCU

Power Die

From Reset

initialize

operate

SPI:

2x STOP

Command

Switch to VREG

low current mode

STOP

Wake Up on

LIN or L1, L2?

IRQ

interrupt

?

Assert IRQ

SPI: reason for

interrupt

Switch to VREG

high current mode

operate

Figure 12. Stop Mode/Wake-Up Procedure

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

23

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

HS3) are turned off and latched off. The failure is reported by

the HSST bit in the SPI Control register.

ANALOG DIE INPUTS/OUTPUTS

High-Side Output Terminals HS1 and HS2

Sleep and Stop Mode

These are two high-side switches used to drive loads such

as relays or lamps. They are protected with overtemperature

and current limit (overcurrent) and include an active internal

clamp circuitry for inductive load drive. Control is done using

the SPI Control register. PWM capability is offered through

the PWMIN input terminal.

In Sleep and Stop modes the high-sides are disabled.

High-Side Output HS3

This high-side switch can be used to drive small lamps,

Hall-effect sensors, or switch pullup resistors. Control is done

using the SPI Control register. No direct PWM control is

possible on this terminal (refer to Figure 14, page 25).

The high-side switch is turned on if both the HSxON bit in

the SPI Control register is set and the PWMIN input is HIGH

(refer to Figure 13, page 24). In order to have HS1 on, the

PWMIN must be HIGH and bit HS1ON must be set. The

same applies to the HS2 output.

Current Limit (Overcurrent) Protection

This high-side feature switch feature current limit to protect

it against overcurrent and short circuit conditions.

If no PWM control is required, PWMIN must be connected

to the VDD terminal.

Overtemperature Protection

Current Limit (Overcurrent) Protection

If an overtemperature condition occurs on any of the three

high-side switches, all high-side switches (HS1, HS2 and

HS3) are turned off and latched off. The failure is reported by

the HSST bit in the SPI Control register.

These high-side switches feature current limit to protect

them against overcurrent and short circuit conditions.

Overtemperature Protection

If an overtemperature condition occurs on any of the three

high-side switches, all high-side switches (HS1, HS2 and

Sleep and Stop Mode

In Sleep and Stop mode the high-side is disabled.

.

PWMIN

VSUP2

MODE1:2

On/Off

High-Side Driver

Charge Pump,

HSxON

HSx

Control

Status

Current Limit Protection,

Overtemperature Protection

Figure 13. High-Side HS1 and HS2 Circuitry

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

24

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

.

MODE1:2

VSUP2

On/Off

Status

High-Side Driver

Charge Pump,

Current Limit Protection,

Overtemperature Protection

HS3ON

Control

HS3

Figure 14. High-Side HS3 Circuitry

The LIN terminal offers high susceptibility immunity level

from external disturbance, guaranteeing communication

during external disturbance.

LIN PHYSICAL LAYER

The LIN bus terminal provides a physical layer for single-

wire communication in automotive applications. The LIN

physical layer is designed to meet the LIN physical layer

specification.

The LIN transmitter circuitry is enabled in Normal and

Normal Request mode.

An over current condition (e.g. LIN bus short to Vbat) or a

over temperature in the output low-side FET will shutdown

the transmitter and set the LINFAIL flag in the SPI Status

Register.

The LIN driver is a low-side MOSFET with over current

protection and thermal shutdown. An internal pullup resistor

with a serial diode structure is integrated, so no external

pullup components are required for the application in a slave

node. The fall time from dominant to recessive and the rise

time from recessive to dominant is controlled. The symmetry

between both slew rate controls is guaranteed.

For improved performance and safe behavior in case of

LIN bus short to Ground or LIN bus leakage during low power

mode the internal pull-up resistor on the LIN terminal can be

disconnected, with the LIN-PU bit in the SPI Control Register,

and a small current source keeps the LIN bus at recessive

level. In case of a LIN bus short to GND, this feature will

reduce the current consumption in STOP and SLEEP modes.

The slew rate can be selected for optimized operation at

10 and 20kBit/s as well as a fast baud rate for test and

programming. The slew rate can be adapted with the bits

LINSL2:1 in the SPI Control Register. The initial slew rate is

optimized for 20kBit/s.

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

25

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

MODE2:1

LINSL2:1

Control

LIN-PU

VSUP1

LINWU

2µA

LINFAIL

30k

LIN bus

TXD

Slope

Control

WakeUp

Filter

GND

RXD

Figure 15. LIN Interface

TXD Terminal

the Stop mode sequence the internal pull-up resistor is

disconnected from VSUP and a small current source keeps

the LIN terminal in recessive state. The receiver is still active

and able to detect wake-up events on the LIN bus line.

The TXD terminal is the MCU interface to control the state

of the LIN transmitter (see Figure 2, page 2). When TXD is

LOW, the LIN terminal is low (dominant state). When TXD is

HIGH, the LIN output MOSFET is turned off (recessive state).

The TXD terminal has an internal pullup current source in

order to set the LIN bus to recessive state in the event, for

instance, the microcontroller could not control it during

system power-up or power-down.

A dominant level longer than T

followed by an rising

propWL

edge will generate a wake-up interrupt and set the LINWF

flag in the SPI Status Register. Also see Figure 9, page 16.

SLEEP Mode and Wake-up Feature

During SLEEP mode operation the transmitter of the

physical layer is disabled. In case the bit LIN-PU was set in

the Sleep mode sequence the internal pull-up resistor is

disconnected from VSUP and a small current source keeps

the LIN terminal in recessive state. The receiver is still active

to be able to detect wake-up events on the LIN bus line.

RXD Terminal

The RXD transceiver terminal is the MCU interface, which

reports the state of the LIN bus voltage. LIN HIGH (recessive

state) is reported by a high level on RXD, LIN LOW (dominant

state) by a low level on RXD.

A dominant level longer than T

followed by an rising

propWL

edge will generate a system wake-up (reset) and set the

LINWF flag in the SPI Status Register . Also see Figure 8,

page 16).

STOP Mode and Wake-up Feature

During STOP mode operation the transmitter of the

physical layer is disabled. In case the bit LIN-PU was set in

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

26

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Overtemperature Protection

WINDOW WATCHDOG

The voltage regulator also features an overtemperature

protection having an overtemperature warning (Interrupt -

VDDT) and an overtemperature shutdown.

The window watchdog is configurable using an external

resistor at the WDCONF terminal. The watchdog is cleared

through by the MODE1:2 bits in the SPI Control register (refer

to Table 8, page 29).

Stop Mode

A watchdog clear is only allowed in the open window. If the

watchdog is cleared in the closed window or has not been

cleared at the end of the open window, the watchdog will

generate a reset on the RST_A terminal and reset the whole

device.

During Stop mode, the Stop mode regulator supplies a

regulated output voltage. The Stop mode regulator has a

limited output current capability.

Sleep Mode

Note The watchdog clear in Normal request mode

In Sleep mode the voltage regulator external V is turned

(150 ms) (first watchdog clear) has no window.

DD

off.

FACTORY TRIMMING AND CALIBRATION

Window closed

no watchdog clear allowed

Window open

for watchdog clear

To enhance the ease-of-use of the 908E624, various

parameters (e.g., ICG trim value) are stored in the flash

memory of the device. The following flash memory locations

are reserved for this purpose and might have a value different

from the “empty” (0xFF) state:

WD timing x 50%

• 0xFD80:0xFDDF Trim and Calibration Values

• 0xFFFE:0xFFFF Reset Vector

In the event the application uses these parameters, one

has to take care not to erase or override these values. If these

parameters are not used, these flash locations can be erased

and otherwise used.

(t

WD period (P_WD

WD timing selected by resistor on WDCONF terminal.

)

PWD

Figure 16. Window Watchdog Operation

Trim Values

Watchdog Configuration

The usage of the trim values, located in the flash memory,

is explained in the following.

If the WDCONF terminal is left open, the default watchdog

period is selected (typ. 150 ms). If no watchdog function is

required, the WDCONF terminal must be connected to GND.

Internal Clock Generator (ICG) Trim Value

The watchdog period is calculated using the following

formula:

The internal clock generator (ICG) module is used to

create a stable clock source for the microcontroller without

using any external components. The untrimmed frequency of

the low-frequency base clock (IBASE), will vary as much as

±25 percent due to process, temperature, and voltage

dependencies. To compensate for these dependencies, an

ICG trim value is located at address $FDC2. After trimming

the ICG, a range of typ. ±2% (±3% max.) at nominal

t

[ms] = 0.991

R

[kΩ] + 0.648

PWD

EXT

*

VOLTAGE REGULATOR

The 908E624 chip contains a low-power, low dropout

voltage regulator to provide internal power and external

power for the MCU. The on-chip regulator consist of two

elements, the main voltage regulator and the low-voltage

reset circuit.

conditions (filtered (100nF) and stabilized (4,7uF) V = 5V,

DD

T

~23°C) and will vary over temperature and voltage

Ambient

(VDD) as indicated in the 68HC908EY16 data sheet.

The V regulator accepts an unregulated input supply

To trim the ICG, these values have to be copied to the ICG

Trim Register ICGTR at address $38 of the MCU.

DD

and provides a regulated V_DDsupply to all digital sections of

the device. The output of the regulator is also connected to

the VDD terminal to provide the 5.0 V to the microcontroller.

Important The value has to be copied after every reset.

Current Limit (Overcurrent) Protection

OPERATING MODES OF THE MCU

The voltage regulator has current limit to protect the device

against overcurrent and short circuit conditions.

For a detailed description of the operating modes of

the MCU, refer to the MC68HC908EY16 data sheet.

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

27

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

• MOSI—Master-Out Slave-In

• MISO—Master-In Slave-Out

• SPSCK—Serial Clock

908E624 SPI INTERFACE AND CONFIGURATION

The serial peripheral interface creates the communication

link between the microcontroller and the analog die of the

908E624.

A complete data transfer via the SPI consists of 1 byte.

The master sends 8 bits of control information and the slave

replies with 8 bits of status data.

The interface consists of four terminals (see Figure 17):

•

SS—Slave Select

SS

Register write data

D4 D3

D7

D6

D5

D2

D1

D0

MOSI

MISO

Register read data

D4 D3

D7

D6

D5

D2

D1

D0

SPSCK

Read data latch

Write data latch

Rising edge of SPSCK

Falling edge of SPSCK

Change MISO/MOSI Output

Sample MISO/MOSI Input

Figure 17. SPI Protocol

During the inactive phase of the SS (HIGH), the new data

transfer is prepared.

The data transfer is only valid if exactly 8 sample clock

edges are present in the active (low) phase of SS.

The falling edge of the SS indicates the start of a new data

transfer and puts the MISO in the low-impedance state and

latches the analog status data (Register read data).

The rising edge of the slave select SS indicates the end of

the transfer and latches the write data (MOSI) into the

register The SS high forces MISO to the high impedance

state.

With the rising edge of the SPI clock, SPSCK the data is

moved to MISO/MOSI terminals. With the falling edge of the

SPI clock SPSCK the data is sampled by the Receiver.

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

28

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

SPI REGISTER OVERVIEW

Table 7 summarizes the SPI Register bit meaning, reset value, and bit reset condition.

.

Table 7. SPI Register Overview

Bit

Read/Write

Information

D7

D6

D5

D4

D3

D2

D1

MODE2

L2

D0

MODE1

L1

Write

Read

LINSL2

LINSL1

LIN-PU

HVF

HS3ON

HS2ON

VDDT

HS1ON

HSST

(27)

INTSRC

LINWU

or

LINFAIL

LVF

or

BATFAIL

(28)

Write Reset Value

0

—

Write Reset Condition

POR,

POR

POR, RESET

POR,

RESET

Notes

27. D7 signals interrupts and wake-up interrupts, D6:D0 indicated the source.

28. The first SPI read after reset returns the BATFAIL flag state on bit D4.

SPI Control Register (Write)

an erroneous short of the LIN bus to ground this will

significantly reduce the power consumption, e.g. in

combination with STOP/SLEEP mode.

Table 8 shows the SPI Control register bits by name.

Table 8. Control Bits Function (Write Operation)

HS3ON:HS1ON—High-Side H3:HS1 Enable Bits

D7

D6

D5

D4

D3

D2

D1

D0

These bits enable the HSx. Reset clears the HSxON bit.

LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1

• 1 = HSx switched on (refer to Note below).

• 0 = HSx switched off.

LINSL2:1—LIN Baud Rate and Low-Power Mode

Selection Bits

Note If no PWM on HS1 and HS2 is required, the PWMIN

terminal must be connected to the VDD terminal.

These bits select the LIN slew rate and requested low-

power mode in accordance with Table 9. Reset clears the

LINSL2:1 bits.

MODE2:1—Mode Section Bits

The MODE2:1 bits control the operating modes and the

watchdog in accordance with Table 10.

Table 9. LIN Baud Rate and Low-Power Mode Selection

Bits

Table 10. Mode Selection Bits

LINSL2

LINSL1

Description

MODE2

MODE1

Description

(29)

0

1

0

1

0

1

Sleep Mode

Stop Mode

0

1

0

1

0

Baud Rate up to 20 kbps (normal)

Baud Rate up to 10 kbps (slow)

(29)

(30)

Watchdog Clear

Run (Normal) Mode

Fast Program Download

Baud Rate up to 100 kbps

1

Low-Power Mode (Sleep or Stop) Request

Notes

29. To enter Sleep and Stop mode, a special sequence of SPI

commands is implemented.

LIN-PU—LIN Pullup Enable Bit

30. The device stays in Run (Normal) mode.

This bit controls the LIN pullup resistor during Sleep and

Stop modes.

To safely enter Sleep or Stop mode and to ensure that

these modes are not affected by noise issue during SPI

transmission, the Sleep/Stop commands require two SPI

transmissions.

• 1 = Pullup disconnected in Sleep and Stop modes.

• 0 = Pullup connected in Sleep and Stop modes.

In case the Pullup is disconnected a small current source

is used to pull the LIN terminal in recessive state. In case of

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

29

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Sleep Mode Sequence

The Sleep command, as shown in Table 11, must be sent twice.

Table 11. Sleep Command Bits

LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1

0/1

1

0

Stop Mode Sequence

The Stop command, as shown in Table 12, must be sent twice.

Table 12. Stop Command Bits

LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1

0/1

1

0

1

SPI Status Register (Read)

Table 13 shows the SPI Status register bits by name.

Table 13. Control Bits Function (Read Operation)

D7

D6

D5

D4

D3

D2

D1

L2

D0

L1

INTSRC LINWU

HVF

LVF

or

VDDT

HSST

or

LINFAIL

BATFAIL

INTSCR —Register Content Flags or Interrupt Source

• 1 = Low-voltage condition has occurred.

• 0 = No low-voltage condition.

This bit indicates if the register contents reflect the flags or

an interrupt/wake-up interrupt source.

VDDT—Voltage Regulator Status Flag Bit

• 1 = D6:D0 reflects the interrupt or wake-up source.

• 0 = No interrupt occurred. Other SPI bits report real time

status.

This flag is set as pre-warning in case of an over-

temperature condition on the voltage regulator.

• 1 = Voltage regulator overtemperature condition, pre-

warning.

LINWU/LINFAIL—LIN Status Flag Bit

• 0 = No overtemperature detected.

This bit indicates a LIN wake-up condition.

• 1 = LIN bus wake-up occurred or LIN overcurrent/

overtemperature occurred.

• 0 = No LIN bus wake-up occurred.

HSST—High-Side Status Flag Bit

This flag is set on overtemperature conditions on one of

the high-side outputs.

In case of a LIN overcurrent/overtemperature condition the

LIN transmitter is disabled. To reenable the LIN transmitter,

the error condition must be GONE and the LINWU/LINFAIL

flag must be cleared.

• 1 = HSx off due to overtemperature.

• 0 = No overtemperature.

In case one of the high-sides has an overtemperature

condition all high-side switches are disabled.

The flag is cleared by reading the flag when it is set (SPI

command).

To reenable the high-side switches, the flags have to be

cleared, by reading the flag when it is set and by writing a one

to high-side HSxON bit (two SPI commands are necessary).

HVF —High-Voltage Flag Bit

This flag is set on an overvoltage (VSUP1) condition.

L2:L1— Wake-Up Inputs L1, L2 Status Flag Bit

• 1 = High-voltage condition has occurred.

• 0 = no High-voltage condition.

These flags reflect the status of the L2 and L1 input

terminals and indicate the wake-up source.

LVF/BATFAIL—Low-Voltage Flag Bit

• 1 = L2:L1 input high or wake-up by L2:L1 (first register

read after wake-up indicated with INTSRC = 1).

• 0 = L2:L1 input low.

This flag is set on an undervoltage (VSUP1) condition.

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

30

TYPICAL APPLICATIONS

The programming is principally possible at two stages in

the manufacturing process — first on chip level, before the IC

is soldered onto a PCB board and second after the IC is

soldered onto the PCB board.

DEVELOPMENT SUPPORT

As the 908E624 has the MC68HC908EY16 MCU

embedded typically all the development tools available for

the MCU also apply for this device, however due to the fact

of the additional analog die circuitry and the nominal +12 V

supply voltage some additional items have to be considered:

Chip Level Programming

On Chip level the easiest way is to only power the MCU

with +5.0 V (see Figure 18) and not to provide the analog chip

with VSUP, in this setup all the analog terminal should be left

open (e.g. VSUP[1:2]) and interconnections between MCU

and analog die have to be separated (e.g. IRQ - IRQ_A).

• nominal 12 V rather than 5.0 V or 3.0 V supply

• high voltage V

might be applied not only to IRQ

TST

terminal, but IRQ_A terminal

• MCU monitoring (Normal request timeout) has to be

disabled

This mode is well described in the MC68HC908EY16 data

sheet - section development support.

For a detailed information on the MCU related

development support see the MC68HC908EY16 data sheet -

section development support.

VSUP[1:2]

GND

VDD

AGND

+5V

VREFH

VDDA

EVDD

RST

RST_A

V_DD

100nF

4.7µF

1

16

C1+

V_CC

V_TST

IRQ

VREFL

VSSA

EVSS

MM908E624

+

1µF

3

4

15

2

C1-

GND

V+

1µF

+

IRQ_A

C2+

6

V-

V_DD

10k

9.8304MHz CLOCK

PTB4/AD4

+5V

MAX232

5

C2-

CLK

RS232

DB-9

+

PTC4/OSC1

PTA0/KBD0

10k

74HC125

PTA1/KBD1

PTB3/AD3

WDCONF

2

3

5

7

8

10

9

6

5

DATA

T2_OUT

R2_IN

T2_IN

74HC125

4

R2_OUT

3

2

1

Figure 18. Normal Monitor Mode Circuit (MCU only)

Of course it is also possible to supply the whole system

with VSUP (12 V) instead as described in Figure 19, page 32.

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

31

TYPICAL APPLICATIONS

PCB Level Programming

system has to be powered up providing V

(see

SUP

Figure 19).

If the IC is soldered onto the PCB board it is typically not

possible to separately power the MCU with +5.0 V, the whole

V_DD

V_SUP

VSUP[1:2]

GND

VDD

+

100nF

AGND

47µF

VREFH

VDDA

EVDD

RST

RST_A

V_DD

100nF

4.7µF

1

16

C1+

V_CC

V_TST

IRQ

VREFL

VSSA

EVSS

MM908E624

+

1µF

2.2k

3

4

15

2

C1-

GND

V+

1µF

+

IRQ_A

C2+

6

V-

V_DD

10k

9.8304MHz CLOCK

PTB4/AD4

V_DD

MAX232

5

C2-

CLK

RS232

DB-9

+

PTC4/OSC1

PTA0/KBD0

10k

74HC125

PTA1/KBD1

PTB3/AD3

WDCONF

2

3

5

7

8

10

9

6

5

DATA

T2_OUT

R2_IN

T2_IN

74HC125

4

R2_OUT

3

2

1

Figure 19. Normal Monitor Mode Circuit

Table 14 summarizes the possible configurations and the

necessary setups.

Table 14. Monitor Mode Signal Requirements and Options

Serial

Communication

Mode

Selection

Communication Speed

Bus

Normal

Request

Timeout

Reset

Vector

Mode IRQ RST WDCONF

ICG

COP

External

Baud

Rate

PTA0

PTA1 PTB3 PTB4

Frequenc

y

Clock

Normal

Monitor

9.8304

MHz

2.4576

MHz

V

GND

X

1

0

X

1

X

OFF

ON

disabled

enabled

disabled

enabled

9600

TST

DD

9.8304

MHz

2.4576

MHz

V

DD

Forced

Monitor

$FFFF

(blank)

1

Nominal

1.6MHz

Nominal

6300

GND

—

not $FFFF

(not blank)

Nominal

1.6MHz

Nominal

6300

User

V

R

EXT

X

ON

DD

Notes

31. PTA0 must have a pullup resistor to V in monitor mode.

DD

32. External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1.

33. Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256.

34. X = don’t care.

35.

V

is a high voltage V + 3.5 V ≤ V_TST≤ V + 4.5 V.

TST DD DD

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

32

TYPICAL APPLICATIONS

MCU Digital Supply Terminals (EVDD and EVSS)

EMC/EMI RECOMMENDATIONS

This paragraph gives some device specific

Fast signal transitions on MCU terminals place high, short-

duration current demands on the power supply. To prevent

noise problems, take special care to provide power supply

bypassing at the MCU. It is recommended that a high-quality

ceramic decoupling capacitor be placed between these

terminals.

recommendations to improve EMC/EMI performance.

Further generic design recommendations can be e.g. found

on the Freescale website www.freescale.com.

VSUP Terminals (VSUP1 and VSUP2)

Its recommended to place a high-quality ceramic

decoupling capacitor close to the VSUP terminals to improve

EMC/EMI behavior.

MCU Analog Supply Terminals (VREFH, VDDA and

VREFL, VSSA)

To avoid noise on the analog supply terminals it is

important to take special care on the layout. The MCU digital

and analog supplies should be tied to the same potential via

separate traces and connected to the voltage regulator

output.

LIN Terminal

For DPI (Direct Power Injection) and ESD (Electro Static

Discharge) it is recommended to place a high-quality ceramic

decoupling capacitor near the LIN terminal. An additional

varistor will further increase the immunity against ESD. A

ferrite in the LIN line will suppress some of the noise induced.

Figure 20 and Figure 21 show the recommendations on

schematics and layout level and Table 15 indicates

recommended external components and layout

considerations.

Voltage Regulator Output Terminals (VDD and AGND)

Use a high-quality ceramic decoupling capacitor to

stabilize the regulated voltage.

D1

V_SUP

VSUP1

VSUP2

VDD

+

C2

AGND

C1

VREFH

VDDA

EVDD

L1

LIN

V1

C5

C3

C4

VREFL

VSSA

EVSS

MM908E624

GND

Figure 20. EMC/EMI recommendations

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

33

TYPICAL APPLICATIONS

1

54

53

2

3

52

4

51

5

50

6

49

7

VREFH 48

VDDA 47

EVDD 46

EVSS 45

VSSA 44

VREFL 43

42

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

41

908E624

40

39

38

37

Comment:

Terminal 32 NC - used for signal routing

36

35

C4

AGND 34

VDD 33

NC

32

VSUP1 31

GND 30

LIN

29

D1

VBAT

LIN

VSUP2 28

C5

L1

Figure 21. PCB Layout Recommendations

.

Table 15. Component Value Recommendation

Component

Recommended Value⁽³⁶⁾

Comments / Signal routing

D1

C1

C2

C3

Reverse battery protection

Bulk Capacitor

100 nF, SMD Ceramic

Close (<5 mm) to VSUP1, VSUP2 terminals with good ground return

Close (<3 mm) to digital supply terminals (EVDD, EVSS) with good

ground return.

The positive analog (VREFH, VDDA) and the digital (EVDD) supply

should be connected right at the C3.

C4

C5

4.7 µF, SMD Ceramic or Low ESR

Bulk Capacitor

180 pF, SMD Ceramic

Close (<5 mm) to LIN terminal.

Total Capacitance per LIN node has to be below 220 pF.

(C

= C

+ C5 + C

~ 10 pF + 180 pF + 15 pF)

Varistor

total

LIN-Terminal

(37)

V1

Varistor Type TDK AVR-M1608C270MBAAB

SMD Ferrite Bead Type TDK MMZ2012Y202B

Optional (close to LIN connector)

Optional, (close to LIN connector)

(37)

L1

Notes

36. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings

or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their

application.

37. Components are recommended to improve EMC and ESD performance.

908E624

Analog Integrated Circuit Device Data

34

Freescale Semiconductor

PACKAGING

PACKAGING DIMENSIONS

PACKAGING

PACKAGING DIMENSIONS

Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A

drawing number below.

10.3

5

9

7.6

7.4

C

2.65

2.35

B

52X

NOTES:

1

54

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

0.65

3. DATUMS B AND C TO BE DETERMINED AT THE PLANE

WHERE THE BOTTOM OF THE LEADS EXIT THE

PLASTIC BODY.

PIN 1 INDEX

4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,

PROTRUSION OR GATE BURRS. MOLD FLASH,

PROTRUSION OR GATE BURRS SHALL NOT EXCEED

0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED

AT THE PLANE WHERE THE BOTTOM OF THE LEADS

EXIT THE PLASTIC BODY.

5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSIONS. INTERLEAD FLASH AND

PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER

SIDE. THIS DIMENSION IS DETERMINED AT THE

PLANEWHERETHEBOTTOMOFTHELEADSEXITTHE

PLASTIC BODY.

4

9

18.0

17.8

C

L

6. THIS DIMENSION DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALLNOTCAUSETHELEADWIDTHTOEXCEED0.46

MM. DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN

PROTRUSIONANDADJACENTLEADSHALLNOTLESS

THAN 0.07 MM.

B

7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.

8. THESE DIMENSIONS APPLY TO THE FLAT SECTION

OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM

THE LEAD TIP.

9. THE PACKAGE TOP MAY BE SMALLER THAN THE

PACKAGE BOTTOM. THIS DIMENSION IS

27

28

SEATING

A

PLANE

DETERMINED AT THE OUTERMOST EXTREMES OF

THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE

BAR BURRS, GATE BURRS AND INTER-LEAD FLASH,

BUT INCLUDING ANY MISMATCH BETWEEN THE TOP

AND BOTTOM OF THE PLASTIC BODY.

5.15

2X 27 TIPS

54X

0.10

A

0.3

A B C

(0.29)

BASE METAL

R0.08 MIN

°

MIN

0

A

0.30

0.25

(0.25)

0.25

GAUGE PLANE

0.29

0.13

0.38

0.22

PLATING

6

M

0.9

0.5

0.13

A B C

8

°

8

0

SECTION A-A

SECTION B-B

ROTATED 90 CLOCKWISE

°

DWB SUFFIX

EW SUFFIX (Pb-FREE)

CASE 1365-01

54-TERMINAL SOIC WIDE BODY

ISSUE O

PLASTIC PACKAGE

98ASA99294D

ISSUE O

DATE 09/19/01

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

35

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 3.0)

ADDITIONAL DOCUMENTATION

908E624

THERMAL ADDENDUM (REV 3.0)

INTRODUCTION

This thermal addendum is provided as a supplement to the MM908E624

technical datasheet. The addendum provides thermal performance information

that may be critical in the design and development of system applications. All

electrical, application, and packaging information is provided in the datasheet.

54-TERMINAL

SOICW

Packaging and Thermal Considerations

The MM908E624 is a dual die package. There are two heat sources in the

package independently heating with P and P . This results in two junction

1

2

temperatures, T and T , and a thermal resistance matrix with R_θJAmn

.

J1

J2

For m, n = 1, R_θJA11is the thermal resistance from Junction 1 to the reference

temperature while only heat source 1 is heating with P .

1

DWB SUFFIX

EW (Pb-FREE) SUFFIX

98ASA99294D

For m = 1, n = 2, R_θJA12is the thermal resistance from Junction 1 to the

reference temperature while heat source 2 is heating with P . This applies to

R_θJ21and R_θJ22, respectively.

2

54-TERMINAL SOICW

R_θJA11R_θJA12

R_θJA21R_θJA22

T

P

Note For package dimensions, refer to the

MM908E624 datasheet.

J1

J2

1

2

.

=

The stated values are solely for a thermal performance comparison of one

package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a

package in an application-specific environment. Stated values were obtained by measurement and simulation according to the

standards listed below

Standards

Table 16. Thermal Performance Comparison

1 = Power Chip, 2 = Logic Chip [°C/W]

Thermal

m = 1,

n = 1

m = 1, n = 2

m = 2, n = 1

m = 2,

n = 2

Resistance

(1)(2)

R

40

25

57

21

31

16

47

12

36

21

52

16

θJAmn

θJBmn

θJAmn

θJCmn

(2)(3)

(1)(4)

(5)

R

Notes:

1. Per JEDEC JESD51-2 at natural convection, still air

condition.

2. 2s2p thermal test board per JEDEC JESD51-7and

JESD51-5.

54 Terminal SOIC

0.65 mm Pitch

17.9 mm x 7.5 mm Body

3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

4. Single layer thermal test board per JEDEC JESD51-3 and

JESD51-5.

5. Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

36

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 3.0)

A

PTB7/AD7/TBCH1

PTB6/AD6/TBCH0

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

PTB5/AD5

PTB4/AD4

PTB3/AD3

IRQ

1

2

3

4

5

6

7

8

PTA0/KBD0

PTA1/KBD1

PTA2/KBD2

FLSVPP

PTA3/KBD3

PTA4/KBD4

VREFH

VDDA

EVDD

EVSS

VSSA

VREFL

PTE1/RXD

NC

RXD

WDCONF

+E

-E

OUT

VCC

AGND

VDD

NC

VSUP1

GND

LIN

VSUP2

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

9

RST

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

PTB1/AD1

PTD0/TACH0

PTD1/TACH1

NC

PWMIN

RST_A

IRQ_A

NC

L1

L2

HS3

HS2

HS1

908E624 Terminal Connections

54-Terminal SOICW

0.65 mm Pitch

17.9 mm x 7.5 mm Body

Figure 22. Surface Mount for SOIC Wide Body

non-Exposed Pad

Device on Thermal Test Board

Table 17. Thermal Resistance Performance

Material:

Single layer printed circuit board

1 = Power Chip, 2 = Logic Chip (°C/W)

FR4, 1.6 mm thickness

Terminal

Resistance

Area A

(mm²)

Cu traces, 0.07 mm thickness

m = 1,

n = 1

m = 1, n = 2

m = 2, n = 1

m = 2,

n = 2

Outline:

80 mm x 100 mm board area,

including edge connector for thermal

testing

R

0

58

56

54

48

46

45

53

51

50

mn

θJA

300

600

Area A:

Cu heat-spreading areas on board

surface

Ambient Conditions: Natural convection, still air

R_θJAmnis the thermal resistance between die junction and

ambient air.

This device is a dual die package. Index m indicates the

die that is heated. Index n refers to the number of the die

where the junction temperature is sensed.

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

37

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 3.0)

70

60

50

40

30

20

10

0

RθJA11

R

θ

JA11

RRθJA22

x

θJA22

R

_JA12= R

θJA21

θ

RθJA12=RθJA21

0

300

600

Heat spreading area [mm²]

A

Figure 23. Device on Thermal Test Board

100

10

1

R

x

θ

JA11

JA22

R

θ

R

_JA12= R

θJA21

θ

0.1

1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04

Time[s]

Figure 24. Transient Thermal Resistance R_θJA(1.0 W Step Response)

Device on Thermal Test Board Area A = 600 (mm²)

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

38

REVISION HISTORY

REVISION

DATE

DESCRIPTION OF CHANGES

•

Implemented Revision History page

Added Pb-Free package option (Suffix EW) and higher Soldering temperature

5/2006

7.0

Added “Y” temperature (T -40°C to 125°C) code option (MM908E624AYEW) and updated condi-

J

tion statement for Static and Dynamic Electrical Characteristics

•

Corrected Figure 11, Operating Modes and Transitions (“STOP command” for transition from Nor-

mal to Stop state)

•

Updated Figure 21, PCB Layout Recommendations, comment NC Terminal used for signal routing

Updated Table 15, Component Value Recommendation

Corrected Figure 23, Device on Thermal Test Board

Removed reference to Note 11, Voltage Regulator - Dropout Voltage

Added comment “LIN in recessive state” to Supply Current Range in Stop Mode and Sleep Mode

Updated format to match current data sheet standard.

Added Figure 10, Power On Reset and Normal Request Time-out Timing

Added LIN P/L details

Made clarifications on Max Ratings Table for T and T Thermal Ratings and the accompanying

A

J

Note

Removed “Advance Information” watermark from first page.

3/2007

•

8.0

908E624

Analog Integrated Circuit Device Data

Freescale Semiconductor

39

RoHS-compliant and/or Pb-free versions of Freescale products have the functionality

and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free

counterparts. For further information, see http://www.freescale.com or contact your

Freescale sales representative.

How to Reach Us:

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Information in this document is provided solely to enable system and software

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LDCForFreescaleSemiconductor@hibbertgroup.com

MM908E624

Rev. 8.0

3/2007


型号：	MM908E624AYEW
厂家：	NXP
描述：	8-BIT, FLASH, 32MHz, MICROCONTROLLER, PDSO54, 0.65 MM PITCH, ROHS COMPLIANT, SOIC-54 时钟光电二极管外围集成电路
文件：	总40页 (文件大小：538K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MM908E624AYEW [NXP]

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