MPC9456ACR2 [NXP]
9456 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32;
| 型号： | MPC9456ACR2 |
| 厂家： | 
NXP |
| 描述： | 9456 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32 驱动 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC9456
Rev 3, 08/2005
Freescale Semiconductor
Technical Data
2.5 V and 3.3 V LVCMOS Clock
Fanout Buffer
MPC9456
The MPC9456 is a 2.5 V and 3.3 V compatible 1:10 clock distribution buffer
designed for low-voltage mid-range to high-performance telecom, networking
and computing applications. Both 3.3 V, 2.5 V and dual supply voltages are
supported for mixed-voltage applications. The MPC9456 offers 10 low-skew
outputs and a differential LVPECL clock input. The outputs are configurable and
support 1:1 and 1:2 output to input frequency ratios. The MPC9456 is specified
for the extended temperature range of –40 to 85°C.
LOW VOLTAGE SINGLE OR DUAL
SUPPLY 2.5 V AND 3.3 V LVCMOS
CLOCK DISTRIBUTION BUFFER
Features
•
•
•
•
Configurable 10 outputs LVCMOS clock distribution buffer
Compatible to single, dual and mixed 3.3 V/2.5 V voltage supply
Wide range output clock frequency up to 250 MHz
Designed for mid-range to high-performance telecom, networking and
computer applications
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-04
•
•
•
•
•
•
•
Supports high-performance differential clocking applications
Maximum output skew of 200 ps (150 ps within one bank)
Selectable output configurations per output bank
Tristable outputs
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
32-lead LQFP package
Ambient operating temperature range of –40 to 85°C
32-lead Pb-free package available
Functional Description
The MPC9456 is a full static design supporting clock frequencies up to
250 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks.
Each of the three output banks can be individually supplied by 2.5 V or 3.3 V supporting mixed voltage applications. The FSELx
pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for
each of the three output banks. The MPC9456 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic
high state). Asserting MR/OE will enable the outputs.
All control inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive
terminated 50 Ω transmission lines. The clock input is low voltage PECL compatible for differential clock distribution support.
Please consult the MPC9446 specification for a full CMOS compatible device. For series terminated transmission lines, each of
the MPC9456 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a
7×7 mm2 32-lead LQFP package.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Bank A
Bank B
QA0
QA1
QA2
CLK
0
1
PCLK
PCLK
25k
25k
CLK ÷ 2
VCC/2
QB0
QB1
QB2
0
1
QC0
Bank C
FSELA
0
1
QC1
QC2
25k
FSELB
FSELC
MR/OE
25k
25k
25k
QC3
Figure 1. MPC9456 Logic Diagram
VCCB is internally connected to VCC
24 23 22 21 20 19 18 17
25
16
15
14
13
12
11
10
9
QC3
GND
QC2
VCCC
QC1
GND
QC0
VCCC
VCCA
26
27
28
29
30
31
32
QA2
GND
QA1
MPC9456
VCCA
QA0
GND
MR/OE
1
2
3
4
5
6
7
8
Figure 2. Pinout: 32-Lead Package Pinout (Top View)
MPC9456
Advanced Clock Drivers Devices
Freescale Semiconductor
2
Table 1. Pin Configuration
Pin
I/O
Type
LVPECL
Function
PECL_CLK,
PECL_CLK
Input
Differential clock reference
Low voltage positive ECL input
FSELA, FSELB, FSELC
MR/OE
Input
Input
LVCMOS
LVCMOS
Supply
Output bank divide select input
Internal reset and output tristate control
Negative voltage supply output bank (GND)
Positive voltage supply for output banks
Positive voltage supply core (VCC)
Bank A outputs
GND
VCCA, VCCB(1), VCCC
Supply
VCC
Supply
QA0 – QA2
QB0 – QB2
QC0 – QC3
Output
Output
Output
LVCMOS
LVCMOS
LVCMOS
Bank B outputs
Bank C outputs
1. VCCB is internally connected to VCC
.
Table 2. Supported Single and Dual Supply Configurations
(1)
(2)
(3)
(4)
Supply Voltage Configuration
3.3 V
GND
VCC
VCCA
VCCB
VCCC
3.3 V
3.3 V
2.5 V
3.3 V
3.3 V or 2.5 V
2.5 V
3.3 V
3.3 V
2.5 V
3.3 V
3.3 V or 2.5 V
2.5 V
0 V
0 V
0 V
Mixed Voltage Supply
2.5 V
1. VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels.
2. VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels.
3. VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to VCC
4. VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels.
.
Table 3. Function Table (Controls)
Control
FSELA
Default
0
1
0
0
0
0
fQA0:2 = fREF
fQB0:2 = fREF
fQC0:3 = fREF
Outputs enabled
fQA0:2 = fREF ÷ 2
fQB0:2 = fREF ÷ 2
fQC0:3 = fREF ÷ 2
Internal reset
FSELB
FSELC
MR/OE
Outputs disabled (tristate)
MPC9456
Advanced Clock Drivers Devices
Freescale Semiconductor
3
Table 4. Absolute Maximum Ratings(1)
Symbol
VCC
VIN
Characteristics
Min
–0.3
–0.3
–0.3
Max
4.6
Unit
V
Condition
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
VCC+0.3
VCC+0.3
±20
V
VOUT
IIN
IOUT
TS
V
mA
mA
°C
±50
Storage Temperature
–65
125
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
Table 5. General Specifications
Symbol
VTT
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
Min
Typ
Max
Unit
V
Condition
VCC ÷ 2
MM
200
2000
200
V
HBM
LU
V
mA
pF
pF
CPD
CIN
Power Dissipation Capacitance
Input Capacitance
10
Per output
4.0
Table 6. DC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3 V ± 5%, TA = –40 to + 85°C)
Symbol
VIH
Characteristics
Min
2.0
Typ
Max
VCC+0.3
0.8
Unit
V
Condition
LVCMOS
LVCMOS
Input High Voltage
Input Low Voltage
VIL
–0.3
250
1.1
V
VPP
Peak-to-Peak Input Voltage
Common Mode Range
Input Current(2)
PCLK
PCLK
mV LVPECL
(1)
VCMR
V
CC–0.6
200
V
µA
V
LVPECL
IIN
VIN = GND or VIN = VCC
IOH = –24 mA(3)
VOH
VOL
Output High Voltage
Output Low Voltage
2.4
0.55
0.30
V
V
IOL = 24 mA(2)
IOL = 12 mA
ZOUT
Output Impedance
14–17
Ω
(4)
ICCQ
Maximum Quiescent Supply Current
2.0
mA All VCC Pins
1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
2. Input pull-up / pull-down resistors influence input current.
3. The MPC9456 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines.
4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
MPC9456
Advanced Clock Drivers Devices
4
Freescale Semiconductor
Table 7. AC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3 V ± 5%, TA = –40 to + 85°C)(1)
Symbol
fref
Characteristics
Min
Typ
Max
Unit
Condition
Input Frequency
0
250(2)
MHz
fMAX
Maximum Output Frequency
÷1 output
÷2output
0
0
250(2)
125
MHz FSELx = 0
MHz FSELx = 1
VPP
Peak-to-Peak Input Voltage
Common Mode Range
Reference Input Pulse Width
PCLK Input Rise/Fall Time
Propagation Delay
PCLK
PCLK
500
1.3
1.4
1000
mV LVPECL
(3)
VCMR
VCC–0.8
V
LVPECL
tP, REF
tr, tf
tPLH
tPHL
ns
ns
1.0(4)
0.8 to 2.0 V
CCLK to any Q
CCLK to any Q
2.2
2.2
2.8
2.8
4.45
4.2
ns
ns
tPLZ, HZ Output Disable Time
tPZL, LZ Output Enable Time
10
10
ns
ns
tsk(O)
Output-to-Output Skew
Within one bank
150
200
350
ps
ps
ps
Any output bank, same output divider
Any output, Any output divider
tsk(PP)
tSK(P)
Device-to-Device Skew
2.25
200
ns
ps
Output Pulse Skew(5)
DCQ
Output Duty Cycle
÷1 output
÷2 output
47
45
50
50
53
55
%
%
DCREF = 50%
DCREF = 25%–75%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
1. AC characteristics apply for parallel output termination of 50 Ω to VTT
.
2. The MPC9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification.
4. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
5. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency
dependent: DCQ = (0.5 ± tSK(P) • fOUT). For example at fOUT = 125 MHz the output duty cycle limit is 50% ± 2.5%.
Table 8. DC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5 V ± 5%, TA = –40 to +85°C)
Symbol
VIH
Characteristics
Min
1.7
Typ
Max
VCC+0.3
0.7
Unit
V
Condition
LVCMOS
LVCMOS
Input high voltage
Input low voltage
VIL
–0.3
250
1.1
V
VPP
Peak-to-peak input voltage
Common Mode Range
Output High Voltage
PCLK
PCLK
mV LVPECL
(1)
VCMR
VCC–0.7
0.6
V
V
LVPECL
VOH
VOL
ZOUT
IIN
1.8
IOH = –15 mA(2)
Output Low Voltage
V
IOL = 15 mA
Output impedance
17–20(2)
Ω
Input current(3)
±200
µA
VIN = GND or VIN = VCC
(4)
ICCQ
Maximum Quiescent Supply Current
2.0
mA All VCC Pins
1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
2. The MPC9456 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines per
output.
3. Input pull-up / pull-down resistors influence input current.
4. CCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
MPC9456
Advanced Clock Drivers Devices
Freescale Semiconductor
5
Table 9. AC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5 V ± 5%, TA = –40 to +85°C)(1)
Symbol
fref
Characteristics
Min
Typ
Max
Unit
Condition
Input Frequency
0
250(2)
MHz
fMAX
Maximum Output Frequency
÷1 output
÷2output
0
0
250(2)
125
MHz FSELx = 0
MHz FSELx = 1
VPP
Peak-to-Peak Input Voltage
Common Mode Range
Reference Input Pulse Width
PCLK Input Rise/Fall Time
Propagation Delay
PCLK
PCLK
500
1.1
1.4
1000
mV LVPECL
(3)
VCMR
V
CC–0.7
V
LVPECL
tP, REF
tr, tf
tPLH
tPHL
ns
ns
1.0(4)
0.7 to 1.7 V
PCLK to any Q
PCLK to any Q
2.6
2.6
5.6
5.5
ns
ns
tPLZ, HZ
tPZL, LZ
tsk(O)
Output Disable Time
Output Enable Time
Output-to-Output Skew
10
10
ns
ns
Within one bank
150
200
350
ps
ps
ps
Any output bank, same output divider
Any output, Any output divider
tsk(PP)
tSK(P)
Device-to-Device Skew
3.0
ns
ps
Output Pulse Skew(5)
200
DCQ
tr, tf
Output Duty Cycle
÷1 or ÷2 output
45
50
55
%
DCREF = 50%
0.6 to 1.8 V
Output Rise/Fall Time
0.1
1.0
ns
1. AC characteristics apply for parallel output termination of 50 Ω to VTT
.
2. The MPC9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification.
4. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
5. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency
dependent: DCQ = (0.5 ± tSK(P) • fOUT). For example at fOUT = 125 MHz the output duty cycle limit is 50% ± 2.5%.
Table 10. AC Characteristics (VCC = 3.3 V ± 5%, VCCA = VCCB = VCCC = 2.5 V ± 5% or 3.3 V ± 5%, TA = –40 to +85°C)(1), (2)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
tsk(O)
Output-to-Output Skew
Within one bank
150
250
350
ps
ps
ps
Any output bank, same output divider
Any output, Any output divider
tsk(PP)
tPLH,HL
tSK(P)
Device-to-Device Skew
2.5
ns
Propagation Delay
PCLK to any Q
See 3.3 V Table
50
Output Pulse Skew(3)
250
55
ps
%
DCQ
Output Duty Cycle
÷1 or ÷2 output
45
DCREF = 50%
1. AC characteristics apply for parallel output termination of 50 Ω to VTT
.
2. For all other AC specifications, refer to 2.5 V or 3.3 V tables according to the supply voltage of the output bank.
3. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency
dependent: DCQ = (0.5 ± tSK(P) • fOUT).
MPC9456
Advanced Clock Drivers Devices
Freescale Semiconductor
6
APPLICATIONS INFORMATION
the line impedances. The voltage wave launched down the
Driving Transmission Lines
two lines will equal:
The MPC9456 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091. In
most high performance clock networks point-to-point
distribution of signals is the method of choice. In a
point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 Ω resistance to VCC÷2.
VL = VS (Z0 ÷ (RS + R0+ Z0))
Z0 = 50 Ω || 50 Ω
RS = 36 Ω || 36 Ω
R0 = 14 Ω
VL = 3.0 (25 ÷ (18 + 14 + 25)
= 1.31 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.5 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
3.0
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9456 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 3 illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme
the fanout of the MPC9456 clock driver is effectively doubled
due to its capability to drive multiple lines.
OutA
tD = 3.8956
OutB
tD = 3.9386
2.5
2.0
In
1.5
1.0
0.5
0
MPC9456
Output
Buffer
ZO = 50Ω
RS = 36Ω
14Ω
IN
IN
OutA
2
4
6
8
10
12
14
MPC9456
Output
Buffer
TIME (ns)
ZO = 50Ω
ZO = 50Ω
RS = 36Ω
RS = 36Ω
Figure 4. Single versus Dual Waveforms
OutB0
OutB1
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 5 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
14Ω
Figure 3. Single versus Dual Transmission Lines
The waveform plots in Figure 4 show the simulation results
of an output driving a single line versus two lines. In both
cases the drive capability of the MPC9456 output buffer is
more than sufficient to drive 50 Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9456. The output waveform
in Figure 4 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36 Ω series resistor plus the
output impedance does not match the parallel combination of
MPC9456
Output
Buffer
ZO = 50Ω
RS = 22Ω
14Ω
ZO = 50Ω
RS = 22Ω
14Ω + 22Ω || 22Ω = 50Ω || 50Ω
25Ω = 25Ω
Figure 5. Optimized Dual Line Termination
MPC9456
Advanced Clock Drivers Devices
Freescale Semiconductor
7
MPC9456 DUT
ZO = 50Ω
Differential Pulse
Generator
ZO = 50Ω
Z = 50Ω
RT = 50Ω
RT = 50Ω
VCC–2V
VTT
Figure 6. PCLK MPC9456 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
PCLK
VCMR
VCC=3.3 V VCC=2.5VV
VPP
PCLK
2.4
1.8 V
VCC
0.55
0.6 V
VCC÷2
QX
GND
tF
tR
t(LH)
t(HL)
Figure 7. Output Transition Time Test Reference
Figure 8. Propagation Delay (tPD) Test Reference
VCC
VCC
VCC÷2
VCC÷2
GND
GND
VOH
tP
VCC÷2
T0
GND
tSK(LH)
tSK(HL)
DC = tP/T0 x 100%
The time from the PLL controlled edge to the non controlled edge, divided by
the time between PLL controlled edges,
expressed as a percentage
The pin-to-pin skew is defined as the worst case difference in
propagation delay between any similar delay path within a single
device
Figure 9. Output Duty Cycle (DC)
Figure 10. Output-to-Output Skew tSK(O)
VCC=3.3 V VCC=2.5 V
2.4
1.8 V
0.55
0.6 V
tF
tR
Figure 11. Output Transition Time Test Reference
MPC9456
Advanced Clock Drivers Devices
Freescale Semiconductor
8
PACKAGE DIMENSIONS
PAGE 1 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
MPC9456
Advanced Clock Drivers Devices
Freescale Semiconductor
9
PACKAGE DIMENSIONS
PAGE 2 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
MPC9456
Advanced Clock Drivers Devices
Freescale Semiconductor
10
PACKAGE DIMENSIONS
PAGE 3 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
MPC9456
11
Advanced Clock Drivers Devices
Freescale Semiconductor
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MPC9456
Rev. 3
08/2005
相关型号：
MPC9456FA
LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC, LQFP-32
MOTOROLA
MPC9456FAR2
9456 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC, LQFP-32
NXP
MPC9456FAR2
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, PLASTIC, LQFP-32
MOTOROLA
MPC9456FAR2
Low Skew Clock Driver, 9456 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, PLASTIC, LQFP-32
IDT
MPC946FA
Low Skew Clock Driver, 946 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 0.80 MM PITCH, LQFP-32
IDT
MPC946FA
Low Skew Clock Driver, MPC900 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, LQFP-32
MOTOROLA
MPC946FAR2
MPC900 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32
MOTOROLA
MPC946FAR2
946 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
NXP
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