MPC946FAR2 [NXP]
946 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32;
| 型号： | MPC946FAR2 |
| 厂家： | 
NXP |
| 描述： | 946 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32 驱动 输出元件 |
| 文件： | 总4页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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Order this document
by MPC946/D
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ꢑ ꢉꢆꢓ ꢔ ꢕꢖꢗ ꢘꢍ ꢖ
ꢀꢙ ꢑꢚ ꢛꢜ
See Upgrade Product – MPC9446
The MPC946 is a low voltage CMOS, 1:10 clock buffer. The 10 outputs
can be configured into a standard fanout buffer or into 1X and 1/2X com-
binations. The ten outputs were designed and optimized to drive 50Ω
series or parallel terminated transmission lines. With output to output
skews of 350ps the MPC946 is an ideal clock distribution chip for syn-
chronous systems which need a tight level of skew from a large number of
outputs. For a similar product with more outputs consult the MPC949 data
sheet.
LOW VOLTAGE
1:10 CMOS CLOCK DRIVER
• 2 Selectable LVCMOS/LVTTL Clock Inputs
• 350ps Output to Output Skew
• Drives up to 20 Series Terminated Independent Clock Lines
• Maximum Input/Output Frequency of 150MHz
• Tristatable Outputs
• 32–Lead LQFP Packaging
• 3.3V VCC Supply
With an output impedance of approximately 7Ω, in both the HIGH and
the LOW logic states, the output buffers of the MPC946 are ideal for driv-
ing series terminated transmission lines. More specifically each of the 10
MPC946 outputs can drive two series terminated transmission lines. With
this capability, the MPC946 has an effective fanout of 1:20 in applications
using point–to–point distribution schemes.
FA SUFFIX
LQFP PACKAGE
CASE 873A
The MPC946 has the capability of generating 1X and 1/2X signals from
a 1X source. The design is fully static, the signals are generated and
retimed inside the chip to ensure minimal skew between the 1X and 1/2X
signals. The device features selectability to allow the user to select the
ratio of 1X outputs to 1/2X outputs.
6
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to
provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the
TCLK1 input is selected.
All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the
Dsel pins will select the 1X output. The MR/Tristate input will reset the internal flip flops and tristate the outputs when it is forced
HIGH.
The MPC946 is fully 3.3V compatible. The 32–lead LQFP package was chosen to optimize performance, board space and
cost of the device. The 32–lead LQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
Rev 2
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
607
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC946
LOGIC DIAGRAM
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Pinout: 32–Lead TQFP (Top View)
6
FUNCTION TABLES
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ꢃ ꢊꢋ
TCLK_Sel
Input
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0
1
TCLK0
TCLK1
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Dselx
Outputs
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ꢊ
MPC946
0
1
1x
1/2x
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MR/OE
Outputs
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0
1
Enabled
Hi–Z
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608
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC946
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
–0.3
–0.3
Max
Unit
V
V
V
Supply Voltage
Input Voltage
Input Current
4.6
CC
I
V
+ 0.3
V
DD
I
IN
(CMOS Inputs)
20
mA
°C
T
Stor
Storage Temperature Range
–40
125
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or condi-
tions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not im-
plied.
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V 0.3V)
Symbol
Characteristic
Input HIGH Voltage
Min
Typ
Max
3.6
Unit
V
Condition
V
V
V
V
I
2.0
IH
Input LOW Voltage
0.8
V
IL
1
Output HIGH Voltage
Output LOW Voltage
2.5
V
I
I
= –20mA
OH
OL
OH
1
0.4
120
85
4
V
= 20mA
OL
Input Current
µA
mA
pF
pF
Note 2.
IN
I
Maximum Quiescent Supply Current
Input Capacitance
70
25
CC
C
C
IN
Power Dissipation Capacitance
Per Output
pd
1. The MPC946 can drive 50Ω transmission lines on the incident edge. Each output can drive one 50Ω parallel terminated transmission line to
the termination voltage of V = V /2. Alternately, the device drives up to two 50Ω series terminated transmission lines.
TT
CC
2. I current is a result of internal pull–up/pull–down resistors.
IN
AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V 0.3V)
6
Symbol
Characteristic
Maximum Input Frequency
Propagation Delay
Min
Typ
Max
Unit
MHz
ns
Condition
Note 1.
F
150
max
t
t
,
TCLK to Q
5.0
4.5
8.0
7.5
12.0
11.5
Note 1., 3.
PLH
PHL
t
Output–to–Output Skew
ps
Note 1., 3.
sk(o)
Same Frequency Outputs
Different Frequency Outputs
Same Frequency Outputs
Different Frequency Outputs
350
350
350
450
F
max
F
max
F
max
F
max
< 100MHz
< 100MHz
> 100MHz
> 100MHz
t
t
t
Part–to–Part Skew
2.0
3
4.5
11
ns
ns
ns
ns
Note 2.
sk(pp)
, t
Output Enable Time
Output Disable Time
Output Rise/Fall Time
Note 3.
PZL PZH
, t
3
11
Note 3.
PLZ PHZ
t , t
r
0.1
0.5
1.0
0.8V to 2.0V, Note 3.
f
1. Driving 50Ω transmission lines.
2. Part–to–part skew at a given temperature and voltage.
3. Termination is 50Ω to V /2.
CC
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
609
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC946
APPLICATIONS INFORMATION
Driving Transmission Lines
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
The MPC946 clock driver was designed to drive high speed
signals in a terminated transmission line environment. To pro-
vide the optimum flexibility to the user the output drivers were
designed to exhibit the lowest impedance possible. With an
output impedance of approximately 10Ω the drivers can drive
either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred to
application note AN1091 in the Timing Solutions data book
(DL207/D).
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.8V. It will then increment towards the
quiescent 3.0V in steps separated by one round trip delay (in
this case 4.0ns).
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In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a point–to–
point scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique termi-
nates the signal at the end of the line with a 50Ω resistance to
VCC/2. This technique draws a fairly high level of DC current
and thus only a single terminated line can be driven by each
output of the MPC946 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 1 illustrates
an output driving a single series terminated line vs two series
terminated lines in parallel. When taken to its extreme the fan-
out of the MPC946 clock driver is effectively doubled due to its
capability to drive multiple lines.
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ꢞꢥꢁ ꢚꢛ ꢗ
ꢠ ꢧꢍ ꢥꢧ ꢍ
Figure 2. Single versus Dual Waveforms
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ꢉΩ
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ꢋ
Ω
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 3 should be used. In this case the series terminating
resistors are reduced such that when the parallel combination
is added to the output buffer impedance the line impedance is
perfectly matched.
ꢑ
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Ω
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ꢰ
6
ꢞꢥꢁ ꢚꢛ ꢗ
ꢠ ꢧꢍ ꢥꢧ ꢍ
ꢬꢧ ꢭꢭ ꢡꢝ
ꢯ
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ꢮ
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ꢖ
ꢉΩ
ꢉΩ
ꢠ
ꢠ
ꢝ
ꢝ
ꢮ
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ꢛ
ꢋ Ω
ꢋ Ω
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ꢤ
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ꢉ
ꢈ
ꢘΩ
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ꢠ ꢧꢍꢥ ꢧꢍ
ꢬ ꢧꢭꢭꢡ ꢝ
ꢯ
ꢯ
ꢮ
ꢮ
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ꢉΩ
ꢉΩ
ꢠ
ꢠ
ꢝ
ꢑ
ꢝ
ꢑ
ꢮ
ꢮ
ꢋ
ꢋ
ꢗΩ
ꢗΩ
Figure 1. Single versus Dual Transmission Lines
The waveform plots of Figure 2 show the simulation results
ꢘΩ
of an output driving a single line vs two lines. In both cases the
drive capability of the MPC946 output buffers is more than suf-
ficient to drive 50Ω transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used exclu-
sively to maintain the tight output–to–output skew of the
MPC946. The output waveform in Figure 2 shows a step in the
waveform, this step is caused by the impedance mismatch
7Ω + 36Ω ꢀ 36Ω = 50Ω ꢀ 50Ω
25Ω = 25Ω
Figure 3. Optimized Dual Line Termination
SPICE level output buffer models are available for engi-
seen looking into the driver. The parallel combination of the neers who want to simulate their specific interconnect
43Ω series resistor plus the output impedance does not match schemes. In addition IV characteristics are in the process of
the parallel combination of the line impedances. The voltage being generated to support the other board level simulators in
wave launched down the two lines will equal:
general use.
610
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
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