MPC9456FA [NXP]
IC,1:10 OUTPUT,LV-CMOS,QFP,32PIN,PLASTIC;
| 型号： | MPC9456FA |
| 厂家： | 
NXP |
| 描述： | IC,1:10 OUTPUT,LV-CMOS,QFP,32PIN,PLASTIC 驱动 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9456/D
Rev 1, 03/2002
The MPC9456 is a 2.5V and 3.3V compatible 1:10 clock distribution
buffer designed for low-voltage mid-range to high-performance telecom,
networking and computing applications. Both 3.3V, 2.5V and dual supply
voltages are supported for mixed-voltage applications. The MPC9456
offers 10 low-skew outputs and a differential LVPECL clock input. The
outputs are configurable and support 1:1 and 1:2 output to input
frequency ratios. The MPC9456 is specified for the extended temperature
range of –40 to 85°C.
LOW VOLTAGE SINGLE OR
DUAL SUPPLY 2.5V AND 3.3V
LVCMOS CLOCK
DISTRIBUTION BUFFER
Features
• Configurable 10 outputs LVCMOS clock distribution buffer
• Compatible to single, dual and mixed 3.3V/2.5V voltage supply
• Wide range output clock frequency up to 250 MHz
• Designed for mid-range to high-performance telecom, networking and
computer applications
• Supports high-performance differential clocking applications
• Max. output skew of 200 ps (150 ps within one bank)
• Selectable output configurations per output bank
• Tristable outputs
FA SUFFIX
LQFP PACKAGE
CASE 873A–02
• 32 ld LQFP package
• Ambient operating temperature range of –40 to 85°C
Functional Description
The MPC9456 is a full static design supporting clock frequencies up to
250 MHz. The signals are generated and retimed on-chip to ensure
minimal skew between the three output banks.
Each of the three output banks can be individually supplied by 2.5V or 3.3V supporting mixed voltage applications. The FSELx
pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for
each of the three output banks. The MPC9456 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic
high state). Asserting MR/OE will enable the outputs.
All control inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive
terminated 50 Ω transmission lines. The clock input is low voltage PECL compatible for differential clock distribution support.
Please consult the MPC9446 specification for a full CMOS compatible device. For series terminated transmission lines, each of
the MPC9456 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7
2
mm 32-lead LQFP package.
For More Information On This Product,
Motorola, Inc. 2002
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC9456
Bank A
QA0
QA1
QA2
0
PCLK
PCLK
CLK
25k
1
CLK ÷ 2
V
/2
CC
25k
Bank B
Bank C
QB0
QB1
QB2
0
1
QC0
FSELA
0
1
QC1
QC2
25k
FSELB
FSELC
MR/OE
25k
25k
25k
QC3
Figure 1. MPC9456 Logic Diagram
V
CCB
is internally connected to V
CC
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
QC3
VCCA
QA2
GND
QC2
GND
QA1
VCCC
QC1
MPC9456
VCCA
QA0
GND
QC0
GND
MR/OE
VCCC
1
2
3
4
5
6
7
8
Figure 2. Pinout: 32–Lead Package Pinout (Top View)
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MPC9456
Table 1: Pin Configuration
Pin
I/O
Type
Function
PECL_CLK,
PECL_CLK
Input
LVPECL
Differential clock reference
Low voltage positive ECL input
FSEL , FSEL , FSEL
Input
Input
LVCMOS
LVCMOS
Supply
Output bank divide select input
A
B
C
MR/OE
Internal reset and output tristate control
Negative voltage supply output bank (GND)
Positive voltage supply for output banks
Positive voltage supply core (VCC)
Bank A outputs
GND
V
V
, V
*, V
Supply
CCA CCB
CCC
Supply
CC
QA0 - QA2
QB0 - QB2
QC0 - QC3
Output
Output
Output
LVCMOS
LVCMOS
LVCMOS
Bank B outputs
Bank C outputs
* V
CCB
is internally connected to V .
CC
Table 2: Supported Single and Dual Supply Configurations
a
b
c
d
Supply voltage configuration
3.3V
V
V
V
V
GND
0V
CC
CCA
CCB
CCC
3.3V
3.3V
2.5V
3.3V
3.3V
3.3V
Mixed voltage supply
2.5V
3.3V or 2.5V
2.5V
3.3V
2.5V
3.3V or 2.5V
2.5V
0 V
0 V
a.
b.
c.
d.
V
V
V
V
is the positive power supply of the device core and input circuitry. V
voltage defines the input threshold and levels
voltage defines bank A output levels
CC
CC
is the positive power supply of the bank A outputs. V
CCA
CCB
CCC
CCA
voltage defines bank B output levels. V
is the positive power supply of the bank B outputs. V
CCB
is internally connected to V
.
CCB
CC
is the positive power supply of the bank C outputs. V
voltage defines bank C output levels
CCC
Table 3: Function Table (Controls)
Control
FSELA
Default
0
1
0
0
0
0
f
f
f
= f
f
f
f
= f
÷ 2
÷ 2
÷ 2
QA0:2 REF
QA0:2 REF
FSELB
FSELC
MR/OE
= f
QB0:2 REF
= f
QB0:2 REF
= f
QC0:3 REF
= f
QC0:3 REF
Outputs enabled
Internal reset
Outputs disabled (tristate)
a
Table 4: Absolute Maximum Ratings
Symbol
Characteristics
Min
-0.3
-0.3
-0.3
Max
Unit
V
Condition
V
CC
Supply Voltage
4.6
V
IN
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
V
V
+0.3
V
CC
V
OUT
+0.3
V
CC
I
IN
±20
mA
mA
°C
I
±50
OUT
T
S
Storage temperature
-40
125
a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
orconditionsbeyondthoseindicatedmayadverselyaffectdevicereliability.Functionaloperationunderabsolute-maximum-ratedconditionsisnot
implied.
Table 5: General Specifications
Symbol
Characteristics
Output Termination Voltage
Min
Typ
÷ 2
Max
Unit
V
Condition
V
TT
V
CC
MM
HBM
LU
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch–Up Immunity
200
2000
200
V
V
mA
pF
pF
C
Power Dissipation Capacitance
Input Capacitance
10
Per output
PD
C
4.0
IN
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MPC9456
Table 6: DC Characteristics (V
= V
= V
= V
= 3.3V ± 5%, T = –40 to +85°C)
A
CC
CCA
CCB
CCC
Min
2.0
Symbol
Characteristics
Input high voltage
Typ
Max
Unit
Condition
LVCMOS
V
IH
V + 0.3
CC
0.8
V
V
IL
Input low voltage
-0.3
250
1.1
V
LVCMOS
LVPECL
LVPECL
V
Peak-to-peak input voltage
Common Mode Range
PCLK
PCLK
mV
V
PP
V
a
V
CC
-0.6
CMR
b
I
Input current
200
µA
V
V
=GND or V =V
IN CC
IN
IN
c
I =-24 mA
OH
V
OH
Output High Voltage
Output Low Voltage
2.4
b
V
0.55
0.30
V
V
I
I
= 24mA
OL
OL
OL
= 12mA
Z
OUT
Output impedance
14 - 17
I
d
Maximum Quiescent Supply Current
2.0
mA
All V
Pins
CC
CCQ
a.
V
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V range
CMR
CMR
and the input swing lies within the V
(DC) specification.
PP
b. Input pull-up / pull-down resistors influence input current.
c. The MPC9456 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of V . Alternatively, the device drives up to two 50Ω series terminated transmission lines.
TT
d.
I
is the DC current consumption of the device with all outputs open and the input in its default state or open.
CCQ
a
Table 7: AC Characteristics (V
CC
= V
= V
= V
= 3.3V ± 5%, T = –40 to +85°C)
A
CCA
CCB
CCC
Min
0
Symbol
Characteristics
Input Frequency
Typ
Max
Unit
Condition
b
b
f
250
MHz
ref
f
Maximum Output Frequency
÷1 output
÷2 output
0
0
250
MHz
MHz
FSELx=0
MAX
125
FSELx=1
LVPECL
LVPECL
V
Peak-to-peak input voltage
Common Mode Range
Reference Input Pulse Width
PCLK Input Rise/Fall Time
Propagation delay
PCLK
PCLK
500
1.3
1.4
1000
mV
V
PP
V
c
V
-0.8
CMR
CC
t
ns
ns
P, REF
d
1.0
t , t
r f
0.8 to 2.0V
t
t
CCLK to any Q
CCLK to any Q
2.2
2.2
2.8
2.8
4.45
4.2
ns
ns
PLH
PHL
t
Output Disable Time
Output Enable Time
Output-to-output Skew
10
10
ns
ns
PLZ, HZ
t
PZL, LZ
t
Within one bank
150
200
ps
ps
ps
sk(O)
Any output bank, same output divider
Any output, Any output divider
350
2.25
t
Device-to-device Skew
ns
ps
sk(PP)
e
t
Output pulse skew
200
SK(P)
DC
Output Duty Cycle
÷1 output
÷2 output
47
45
50
50
53
55
%
%
DC
DC
= 50%
= 25%-75%
Q
REF
REF
t , t
r f
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4V
a. AC characteristics apply for parallel output termination of 50Ω to V
.
TT
b. The MPC9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
c. (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
V
range
CMR
CMR
and the input swing lies within the V
(AC) specification.
PP
d. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
e. Output pulse skew is the absolute difference of the propagation delay times: | t
- t |.
pLH pHL
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MPC9456
Table 8: DC Characteristics (V
CC
= V
= V
= V
= 2.5V ± 5%, T = –40 to +85°C)
A
CCA
CCB
CCC
Min
1.7
Symbol
Characteristics
Input high voltage
Typ
Max
Unit
Condition
LVCMOS
V
IH
V + 0.3
CC
0.7
V
V
IL
Input low voltage
-0.3
250
1.1
V
LVCMOS
LVPECL
LVPECL
V
Peak-to-peak input voltage
Common Mode Range
Output High Voltage
Output Low Voltage
Output impedance
PCLK
PCLK
mV
V
PP
V
a
V
CC
-0.7
CMR
b
=-15 mA
V
OH
1.8
V
I
OH
= 15 mA
OL
V
OL
0.6
V
I
b
Z
OUT
17 - 20
c
I
Input current
±200
µA
V
IN
All V
=GND or V =V
IN CC
IN
I
d
Maximum Quiescent Supply Current
2.0
mA
Pins
CC
CCQ
a.
V
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V range
CMR
CMR
and the input swing lies within the V
(DC) specification.
PP
b. The MPC9456 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of V . Alternatively, the device drives up to two 50Ω series terminated transmission lines per
TT
output.
c. Input pull-up / pull-down resistors influence input current.
d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
a
Table 9: AC Characteristics (V
CC
= V
= V
= V
= 2.5V ± 5%, T = –40 to +85°C)
CCC A
CCA
CCB
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
b
b
f
Input Frequency
0
250
MHz
ref
f
Maximum Output Frequency
÷1 output
÷2 output
0
0
250
MHz
MHz
FSELx=0
FSELx=1
MAX
125
V
Peak-to-peak input voltage
Common Mode Range
Reference Input Pulse Width
PCLK Input Rise/Fall Time
Propagation delay
PCLK
PCLK
500
1.1
1.4
1000
mV
V
LVPECL
LVPECL
PP
V
c
V
-0.7
CMR
CC
t
ns
ns
P, REF
d
1.0
t , t
r f
0.7 to 1.7V
t
t
PCLK to any Q
PCLK to any Q
2.6
2.6
5.6
5.5
ns
ns
PLH
PHL
t
Output Disable Time
Output Enable Time
Output-to-output Skew
10
10
ns
ns
PLZ, HZ
t
PZL, LZ
t
Within one bank
150
200
ps
ps
ps
sk(O)
Any output bank, same output divider
Any output, Any output divider
350
3.0
t
Device-to-device Skew
ns
ps
sk(PP)
e
t
Output pulse skew
200
SK(P)
DC
Output Duty Cycle
÷1 or ÷2 output
45
50
55
%
DC
= 50%
Q
REF
0.6 to 1.8V
t , t
Output Rise/Fall Time
a. AC characteristics apply for parallel output termination of 50Ω to V
0.1
1.0
ns
r f
.
TT
b. The MPC9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
c. (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
V
range
CMR
CMR
and the input swing lies within the V
(AC) specification.
PP
d. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
e. Output pulse skew is the absolute difference of the propagation delay times: | t
- t |.
pLH pHL
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Freescale Semiconductor, Inc.
MPC9456
Table 10: AC Characteristics (V
= 3.3V ± 5%, V
= V
= V
= 2.5V ± 5% or 3.3V ± 5%,
CCC
CC
CCA
CCB
Min
a b
T
A
= –40 to +85°C)
Symbol
Characteristics
Output-to-output Skew
Typ
Max
Unit
Condition
t
Within one bank
150
250
ps
ps
ps
sk(O)
Any output bank, same output divider
Any output, Any output divider
350
2.5
t
Device-to-device Skew
ns
sk(PP)
t
Propagation delay
Output pulse skew
PCLK to any Q
See 3.3V table
50
PLH,HL
c
t
250
55
ps
%
SK(P)
DC
Output Duty Cycle
÷1 or ÷2 output
45
DC
= 50%
REF
Q
a. AC characteristics apply for parallel output termination of 50Ω to V
.
TT
b. For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.
c. Output pulse skew is the absolute difference of the propagation delay times: | t - t |.
pLH pHL
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MPC9456
APPLICATIONS INFORMATION
Driving Transmission Lines
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
The MPC9456 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091. In
most high performance clock networks point-to-point
distribution of signals is the method of choice. In a
point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
V
Z
R
R
V
= V ( Z ÷ (R +R +Z ))
S 0 S 0 0
L
0
S
0
= 50Ω || 50Ω
= 36Ω || 36Ω
= 14Ω
= 3.0 ( 25 ÷ (18+14+25)
= 1.31V
L
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
50Ω resistance to V ÷2.
3.0
CC
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9456 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 3. “Single
versus Dual Transmission Lines” illustrates an output driving
a single series terminated line versus two series terminated
lines in parallel. When taken to its extreme the fanout of the
MPC9456 clock driver is effectively doubled due to its
capability to drive multiple lines.
OutA
= 3.8956
OutB
= 3.9386
t
D
2.5
2.0
1.5
1.0
0.5
0
t
D
In
MPC9456
OUTPUT
BUFFER
Z
O
= 50Ω
R = 36Ω
S
14Ω
IN
IN
OutA
2
4
6
8
10
12
14
TIME (nS)
Figure 4. Single versus Dual Waveforms
MPC9456
OUTPUT
BUFFER
Z
= 50Ω
= 50Ω
O
R = 36Ω
S
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 5. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
OutB0
OutB1
14Ω
Z
O
R = 36Ω
S
Figure 3. Single versus Dual Transmission Lines
The waveform plots in Figure 4. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9456 output buffer is more than
sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9456. The output waveform in Figure 4. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36Ω series resistor plus the output
MPC9456
OUTPUT
BUFFER
Z
= 50Ω
= 50Ω
O
R = 22Ω
S
14Ω
Z
O
R = 22Ω
S
14Ω + 22Ω 22Ω = 50Ω 50Ω
25Ω = 25Ω
Figure 5. Optimized Dual Line Termination
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MPC9456 DUT
Z
O
= 50Ω
Differential
Pulse Generator
Z = 50
Z
O
= 50Ω
R = 50Ω
T
R = 50Ω
T
V
CC
– 2V
V
TT
Figure 6. PCLK MPC9456 AC test reference for V = 3.3V and V = 2.5V
cc cc
PCLK
PCLK
V
CMR
V
PP
V =3.3V
CC
V =2.5V
CC
2.4
0.55
1.8V
0.6V
V
CC
V
2
CC
GND
Q
X
t
F
t
R
t
t
(HL)
(LH)
Figure 7. Output Transition Time Test Reference
Figure 8. Propagation delay (t ) test reference
PD
V
CC
V
CC
V
CC
GND
2
2
V
CC
GND
2
V
OH
t
P
V
CC
GND
T
0
DC = t /T x 100%
P 0
t
t
SK(HL)
SK(LH)
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
The pin–to–pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
Figure 9. Output Duty Cycle (DC)
Figure 10. Output–to–output Skew t
SK(O)
V =3.3V
CC
V =2.5V
CC
2.4
0.55
1.8V
0.6V
t
F
t
R
Figure 11. Output Transition Time test reference
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OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 873A-02
ISSUE A
4X
A
A1
0.20 (0.008) AB T–U
Z
32
25
1
–U–
V
–T–
B
AE
AE
P
B1
DETAIL Y
–Z–
V1
17
8
DETAIL Y
9
4X
0.20 (0.008) AC T–U
Z
9
NOTES:
S1
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
DETAIL AD
G
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
–AB–
–AC–
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
SEATING
PLANE
0.10 (0.004) AC
BASE
METAL
N
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
F
D
8X M
MILLIMETERS
DIM MIN MAX
7.000 BSC
INCHES
MIN MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
R
J
A
A1
B
3.500 BSC
7.000 BSC
3.500 BSC
1.400 1.600 0.055 0.063
0.300 0.450 0.012 0.018
1.350 1.450 0.053 0.057
0.300 0.400 0.012 0.016
SECTION AE–AE
E
C
B1
C
D
E
F
W
G
H
J
K
M
N
P
0.800 BSC
0.031 BSC
Q
H
K
X
0.050 0.150 0.002 0.006
0.090 0.200 0.004 0.008
0.500 0.700 0.020 0.028
12 REF
0.090 0.160 0.004 0.006
0.400 BSC 0.016 BSC
12 REF
DETAIL AD
Q
R
1
5
1
5
0.150 0.250 0.006 0.010
S
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
S1
V
V1
W
X
For More Information On This Product,
TIMING SOLUTIONS
9
MOTOROLA
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Freescale Semiconductor, Inc.
MPC9456
NOTES
For More Information On This Product,
MOTOROLA
10
TIMING SOLUTIONS
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC9456
NOTES
For More Information On This Product,
TIMING SOLUTIONS
11
MOTOROLA
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC9456
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specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
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MPC9456/D
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