MPC947FAR2 [NXP]

947 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32;


型号：	MPC947FAR2
厂家：	NXP
描述：	947 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32 PC 驱动输出元件逻辑集成电路
文件：	总4页 (文件大小：261K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SEMICONDUCTOR TECHNICAL DATA

Order this document

by MPC947/D

Freescale Semiconductor, Inc.

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The MPC947 is a 1:9 low voltage clock distribution chip. The device

features the capability to select between two LVTTL compatible inputs

and fans the signal out to 9 LVCMOS or LVTTL compatible outputs.

These 9 outputs were designed and optimized to drive 50Ω series termi-

nated transmission lines. With output–to–output skews of 500ps, the

MPC947 is ideal as a clock distribution chip for synchronous systems

which need a tight level of skew at a relatively low cost. For a similar

product targeted at a higher price/performance point, consult the

MPC948 data sheet.

LOW VOLTAGE

1:9 CLOCK

DISTRIBUTION CHIP

• 2 Selectable LVCMOS/LVTTL Clock Inputs

• 500ps Maximum Output–to–Output Skew

• Drives Up to 18 Independent Clock Lines

• Maximum Output Frequency of 110MHz

• Synchronous Output Enable

• Tristatable Outputs

• 32–Lead LQFP Packaging

• 3.3V V_CCSupply Voltage

FA SUFFIX

32–LEAD LQFP PACKAGE

CASE 873A

With an output impedance of approximately 7Ω, in both the HIGH and

LOW logic states, the output buffers of the MPC947 are ideal for driving

series terminated transmission lines. More specifically, each of the 9

MPC947 outputs can drive two series terminated 50Ω transmission lines.

With this capability, the MPC947 has an effective fanout of 1:18 in ap-

plications using point–to–point distribution schemes. With this level of

fanout, the MPC947 provides enough copies of low skew clocks for high

performance synchronous systems, including use as a clock distribution

chip for the L2 cache of a PowerPC 620 based system.

Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to

provide redundant clock sources or the addition of a test clock into the system design. With the select input pulled HIGH, the

TTL_CLK1 input will be selected.

All of the control inputs are LVCMOS/LVTTL compatible. The MPC947 provides a synchronous output enable control to allow

for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control

is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test,

the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate input will force all of the outputs into

high impedance. Note that all of the MPC947 inputs have internal pullup resistors.

The MPC947 is fully 3.3V compatible. The 32–lead LQFP package was chosen to optimize performance, board space and

cost of the device. The 32–lead LQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

611

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC947

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Figure 1. Logic Diagram

FUNCTION TABLES

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TTL_CLK1_Sel

Input

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TTL_CLK0

TTL_CLK1

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Sync_OE

Outputs

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Disabled

Enabled

MPC947

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Tristate

Outputs

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Enabled

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Figure 2. 32–Lead Pinout (Top View)

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Figure 3. Sync_OE Timing Diagram

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MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

For More Information On This Product,

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Freescale Semiconductor, Inc.

MPC947

ABSOLUTE MAXIMUM RATINGS*

Symbol

Parameter

Min

–0.3

Max

Unit

Supply Voltage

Input Voltage

Input Current

4.6

+ 0.3

(CMOS Inputs)

°C

Stor

Storage Temperature Range

–40

125

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or condi-

tions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not im-

plied.

DC CHARACTERISTICS (T_A= 0° to 70°C, V_CC= 3.3V 0.3V)

Symbol

Characteristic

Input HIGH Voltage

Min

Typ

Max

3.6

Unit

Condition

2.0

Input LOW Voltage

0.8

Output HIGH Voltage

Output LOW Voltage

2.5

= –20mA (Note 1.)

= 20mA (Note 1.)

0.4

–100

Input Current

µA

Note 2.

Maximum Quiescent Supply Current

Input Capacitance

Power Dissipation Capacitance

Per Output

1. The MPC947 can drive 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to

= V /2. Alternately, the device drives up to two 50Ω series terminated transmission lines per output.

2. I current is a result of internal pull–up resistors.

AC CHARACTERISTICS (T_A= 0° to 70°C, V_CC= 3.3V 0.3V)

Symbol

Characteristic

Maximum Input Frequency

Propagation Delay

Min

110

Typ

Max

Unit

MHz

Condition

Note 3.

max

TCLK to Q

4.75

9.25

500

2.0

Note 3.

Output–to–Output Skew

Part–to–Part Skew

Note 3.

sk(o)

sk(pr)

pwo

Notes 3., 4.

Note 3.,

Output Pulse Width

CYCLE

– 800

+ 800

Measured at V /2

Setup Time

Sync_OE to Input Clk

Input Clk to Sync_OE

0.0

Notes 3., 5.

Hold Time

1.0

, t

Output Enable Time

Output Disable Time

Output Rise/Fall Time

PZL PZH

, t

PLZ PHZ

t , t

0.2

1.0

0.8V to 2.0V

3. Driving 50Ω terminated to V /2.

4. Part–to–part skew at a given temperature and voltage.

5. Setup and Hold times are relative to the falling edge of the input clock.

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

613

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Freescale Semiconductor, Inc.

MPC947

APPLICATIONS INFORMATION

Driving Transmission Lines

VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V

The MPC947 clock driver was designed to drive high speed

signals in a terminated transmission line environment. To pro-

vide the optimum flexibility to the user the output drivers were

designed to exhibit the lowest impedance possible. With an

output impedance of approximately 10Ω the drivers can drive

either parallel or series terminated transmission lines. For

more information on transmission lines the reader is referred to

application note AN1091 in the Timing Solutions data book

(DL207/D).

At the load end the voltage will double, due to the near unity

reflection coefficient, to 2.8V. It will then increment towards the

quiescent 3.0V in steps separated by one round trip delay (in

this case 4.0ns).

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In most high performance clock networks point–to–point

distribution of signals is the method of choice. In a point–to–

point scheme either series terminated or parallel terminated

transmission lines can be used. The parallel technique termi-

nates the signal at the end of the line with a 50Ω resistance to

VCC/2. This technique draws a fairly high level of DC current

and thus only a single terminated line can be driven by each

output of the MPC947 clock driver. For the series terminated

case however there is no DC current draw, thus the outputs

can drive multiple series terminated lines. Figure 4 illustrates

an output driving a single series terminated line vs two series

terminated lines in parallel. When taken to its extreme the fan-

out of the MPC947 clock driver is effectively doubled due to its

capability to drive multiple lines.

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Figure 5. Single versus Dual Waveforms

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Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the situation

in Figure 6 should be used. In this case the series terminating

resistors are reduced such that when the parallel combination

is added to the output buffer impedance the line impedance is

perfectly matched.

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Figure 4. Single versus Dual Transmission Lines

The waveform plots of Figure 5 show the simulation results

ꢋΩ

of an output driving a single line vs two lines. In both cases the

drive capability of the MPC947 output buffers is more than suf-

ficient to drive 50Ω transmission lines on the incident edge.

Note from the delay measurements in the simulations a delta

of only 43ps exists between the two differently loaded outputs.

This suggests that the dual line driving need not be used exclu-

sively to maintain the tight output–to–output skew of the

MPC947. The output waveform in Figure 5 shows a step in the

waveform, this step is caused by the impedance mismatch

7Ω + 36Ω ꢀ 36Ω = 50Ω ꢀ 50Ω

25Ω = 25Ω

Figure 6. Optimized Dual Line Termination

SPICE level output buffer models are available for engi-

seen looking into the driver. The parallel combination of the neers who want to simulate their specific interconnect

43Ω series resistor plus the output impedance does not match schemes. In addition IV characteristics are in the process of

the parallel combination of the line impedances. The voltage being generated to support the other board level simulators in

wave launched down the two lines will equal:

general use.

614

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

For More Information On This Product,

Go to: www.freescale.com

MPC947FAR2 [NXP]

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