MPC961CFAR2 [NXP]

961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32;


型号：	MPC961CFAR2
厂家：	NXP
描述：	961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32 驱动输出元件
文件：	总9页 (文件大小：343K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

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Order this document

by MPC961C/D

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The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay

buffer. With output frequencies of up to 200MHz, output skews of 150ps

the device meets the needs of the most demanding clock tree applica-

tions.

LOW VOLTAGE

• Fully Integrated PLL

• Up to 200MHz I/O Frequency

• LVCMOS Outputs

ZERO DELAY BUFFER

• Outputs Disable in High Impedance

• LVCMOS Reference Clock Options

• LQFP Packaging

•

50ps Cycle–Cycle Jitter

• 150ps Output Skews

The MPC961 is offered with two different input configurations. The

MPC961C offers an LVCMOS reference clock while the MPC961P offers

an LVPECL reference clock.

When pulled high the OE pin will force all of the outputs (except QFB)

into a high impedance state. Because the OE pin does not affect the QFB

output, down stream clocks can be disabled without the internal PLL los-

ing lock.

FA SUFFIX

32–LEAD LQFP PACKAGE

CASE 873A

The MPC961 is fully 2.5V or 3.3V compatible and requires no external

loop filter components. All control inputs accept LVCMOS compatible lev-

els and the outputs provide low impedance LVCMOS outputs capable of

driving terminated 50W transmission lines. For series terminated lines the

MPC961 can drive two lines per output giving the device an effective

fanout of 1:36. The device is packaged in a 32 lead LQFP.

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Figure 1. MPC961C Logic Diagram

Rev 1

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

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MPC961C

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MPC961C

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Figure 2. 32–Lead Pinout (Top View)

Table 1: PIN CONFIGURATIONS

I/O

Input

Type

LVCMOS

Ground

Function

CCLK

FB_IN

PLL reference clock signal

Input

PLL feedback signal input, connect to a QFB output

PLL frequency range select

F_RANGE

Input

Output enable/disable

Q0 - Q16

QFB

Output

Supply

Clock outputs

PLL feedback signal output, connect to a FB_IN

Negative power supply

GND

VCCA

VCC

PLL positive power supply (analog power supply). The MPC961C requires

an external RC filter for the analog power supply pin V

plications section for details.

. Please see ap-

CCA

VCC

Supply

VCC

Positive power supply for I/O and core

Not connected

Table 2: FUNCTION TABLE

Control

Default

F_RANGE

PLL high frequency range. MPC961C input reference

and output clock frequency range is 100 – 200 MHz

PLL low frequency range. MPC961C input reference

and output clock frequency range is 50 – 100 MHz

Outputs enabled

Outputs disabled (high–impedance state)

478

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MPC961C

Table 3: ABSOLUTE MAXIMUM RATINGS*

Symbol

Parameter

Min

–0.3

Max

Unit

Supply Voltage

3.6

DC Input Voltage

DC Output Voltage

DC Input Current

DC Output Current

+ 0.3

OUT

°C

OUT

Storage Temperature Range

–40

125

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or condi-

tions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not im-

plied.

Table 4: DC CHARACTERISTICS (V_CC= 3.3V 5%, T_A= –40° to 85°C)

Symbol

Characteristic

Input HIGH Voltage

Min

2.0

Typ

Max

V + 0.3

Unit

Condition

LVCMOS

Input LOW Voltage

–0.3

2.4

0.8

Output HIGH Voltage

= –20mA

OUT

Output LOW Voltage

0.55

= 20mA

Output Impedance

Input Current

120

µA

Input Capacitance

4.0

8.0

2.0

Power Dissipation Capacitance

Maximum PLL Supply Current

Maximum Quiescent Supply Current

Output Termination Voltage

Per Output

V Pin

CCA

5.0

CCA

All VCC Pins

B 2

a. The MPC961C is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmis-

sion line to a termination voltage of V . Alternatively, the device drives up two 50Ω series terminated transmission lines.

Table 5: AC CHARACTERISTICS (V_CC= 3.3V 5%, T_A= –40° to 85°C)^a

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

ref

Input Frequency

F_RANGE = 0

F_RANGE = 1

100

200

100

MHz

Maximum Output Frequency

F_RANGE = 0

F_RANGE = 1

100

200

100

MHz

max

Reference Input Duty Cycle

TCLK Input Rise/Fall Time

3.0

120

refDC

t , t

0.8 to 2.0V

PLL locked

(

Propagation Delay

(static phase offset)

CCLK to FB_IN

–80

∅

)

Output–to–Output Skew

150

sk(O)

Output Duty Cycle

F_RANGE = 0

F_RANGE = 1

t , t

Output Rise/Fall Time

Output Disable Time

Output Enable Time

Cycle–to–Cycle Jitter

Period Jitter

0.1

1.0

0.55 to 2.4V

PLZ HZ

PZL LZ

RMS (1 s)

JIT(CC)

RMS (1 s)

7.0

JIT(PER)

I/O Phase Jitter

∅

JIT(

lock

)

Maximum PLL Lock Time

a. AC characteristics apply for parallel output termination of 50W to V

b. See applications section for part–to–part skew calculation

c. See applications section for calculation for other confidence factors than 1 s

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MPC961C

Table 6: DC CHARACTERISTICS (V_CC= 2.5V 5%, T_A= –40° to 85°C)

Symbol

Characteristic

Input HIGH Voltage

Min

1.7

Typ

Max

V + 0.3

Unit

Condition

LVCMOS

Input LOW Voltage

–0.3

1.8

0.7

Output HIGH Voltage

= –15mA

OUT

Output LOW Voltage

0.6

= 15mA

Output Impedance

Input Current

120

µA

Input Capacitance

4.0

8.0

2.0

Power Dissipation Capacitance

Maximum PLL Supply Current

Maximum Quiescent Supply Current

Output Termination Voltage

Per Output

V Pin

CCA

5.0

CCA

All VCC Pins

B 2

a. The MPC961C is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmis-

sion line to a termination voltage of V . Alternatively, the device drives up two 50Ω series terminated transmission lines.

Table 7: AC CHARACTERISTICS (V_CC= 2.5V 5%, T_A= –40° to 85°C)^a

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

ref

Input Frequency

F_RANGE = 0

F_RANGE = 1

100

200

100

MHz

Maximum Output Frequency

F_RANGE = 0

F_RANGE = 1

100

200

100

MHz

max

Reference Input Duty Cycle

TCLK Input Rise/Fall Time

3.0

120

refDC

t , t

0.7 to 1.7V

PLL locked

(

Propagation Delay

(static phase offset)

CCLK to FB_IN

–80

∅

)

Output–to–Output Skew

150

sk(O)

Output Duty Cycle

F_RANGE = 0

F_RANGE = 1

t , t

Output Rise/Fall Time

Output Disable Time

Output Enable Time

Cycle–to–Cycle Jitter

Period Jitter

0.1

1.0

0.6 to 1.8V

PLZ HZ

PZL LZ

RMS (1 s)

JIT(CC)

RMS (1 s)

7.0

JIT(PER)

I/O Phase Jitter

∅

JIT(

)

Maximum PLL Lock Time

lock

a. AC characteristics apply for parallel output termination of 50W to V

b. See applications section for part–to–part skew calculation

c. See applications section for calculation for other confidence factors than 1 s

480

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

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MPC961C

Power Supply Filtering

Driving Transmission Lines

The MPC961C clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output drivers

were designed to exhibit the lowest impedance possible. With

an output impedance of less than 15Ω the drivers can drive

either parallel or series terminated transmission lines. For

more information on transmission lines the reader is referred to

application note AN1091.

The MPC961C is a mixed analog/digital product and as

such it exhibits some sensitivities that would not necessarily be

seen on a fully digital product. Analog circuitry is naturally sus-

ceptible to random noise, especially if this noise is seen on the

power supply pins. The MPC961C provides separate power

supplies for the output buffers (V_CC) and the phase–locked

loop (V_CCA) of the device. The purpose of this design tech-

nique is to isolate the high switching noise digital outputs from

the relatively sensitive internal analog phase–locked loop. In a

controlled environment such as an evaluation board this level

of isolation is sufficient. However, in a digital system environ-

ment where it is more difficult to minimize noise on the power

supplies a second level of isolation may be required. The sim-

plest form of isolation is a power supply filter on the V_CCApin

for the MPC961C.

In most high performance clock networks point–to–point

distribution of signals is the method of choice. In a point–to–

point scheme either series terminated or parallel terminated

transmission lines can be used. The parallel technique termi-

nates the signal at the end of the line with a 50Ω resistance to

VCC/2. This technique draws a fairly high level of DC current

and thus only a single terminated line can be driven by each

output of the MPC961C clock driver. For the series terminated

case however there is no DC current draw, thus the outputs

can drive multiple series terminated lines. Figure 4 illustrates

an output driving a single series terminated line vs two series

terminated lines in parallel. When taken to its extreme the fan-

out of the MPC961C clock driver is effectively doubled due to

its capability to drive multiple lines.

Figure 3 illustrates a typical power supply filter scheme. The

MPC961C is most susceptible to noise with spectral content in

the 10kHz to 10MHz range. Therefore the filter should be de-

signed to target this range. The key parameter that needs to be

met in the final filter design is the DC voltage drop that will be

seen between the V_CCsupply and the V_CCApin of the

MPC961C. From the data sheet the I_CCAcurrent (the current

sourced through the V_CCApin) is typically 2mA (5mA maxi-

mum), assuming that a minimum of 2.375V (V_CC= 3.3V or V_CC

= 2.5V) must be maintained on the V_CCApin. The resistor R_F

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shown in Figure 3 must have a resistance of 270Ω (V_CC

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3.3V) or 5 to 15Ω (V_CC= 2.5V) to meet the voltage drop crite-

ria. The RC filter pictured will provide a broadband filter with

approximately 100:1 attenuation for noise whose spectral con-

tent is above 20kHz. As the noise frequency crosses the series

resonant point of an individual capacitor it’s overall impedance

begins to look inductive and thus increases with increasing

frequency. The parallel capacitor combination shown ensures

that a low impedance path to ground exists for frequencies well

above the bandwidth of the PLL.

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Figure 4. Single versus Dual Transmission Lines

The waveform plots of Figure 5 show the simulation results

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of an output driving a single line vs two lines. In both cases the

drive capability of the MPC961C output buffer is more than

sufficient to drive 50Ω transmission lines on the incident edge.

Note from the delay measurements in the simulations a delta

of only 43ps exists between the two differently loaded outputs.

This suggests that the dual line driving need not be used exclu-

sively to maintain the tight output–to–output skew of the

MPC961C. The output waveform in Figure 5 shows a step in

the waveform, this step is caused by the impedance mismatch

seen looking into the driver. The parallel combination of the

36Ω series resistor plus the output impedance does not match

the parallel combination of the line impedances. The voltage

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Figure 3. Power Supply Filter

Although the MPC961C has several design features to mini- wave launched down the two lines will equal:

mize the susceptibility to power supply noise (isolated power

and grounds and fully differential PLL) there still may be ap-

plications in which overall performance is being degraded due

to system power supply noise. The power supply filter

schemes discussed in this section should be adequate to elim-

inate power supply noise related problems in most designs.

VL = VS ( Zo / (Rs + Ro +Zo))

Zo = 50Ω || 50Ω

Rs = 36Ω || 36Ω

Ro = 14Ω

VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)

= 1.31V

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MPC961C

At the load end the voltage will double, due to the near unity Using the MPC961C in zero-delay applications

reflection coefficient, to 2.62V. It will then increment towards

the quiescent 3.0V in steps separated by one round trip delay

(in this case 4.0ns).

Nested clock trees are typical applications for the

MPC961C. Designs using the MPC961C as LVCMOS PLL

fanout buffer with zero insertion delay will show significantly

lower clock skew than clock distributions developed from

CMOS fanout buffers. The external feedback option of the

MPC961C clock driver allows for its use as a zero delay buffer.

By using the QFB output as a feedback to the PLL the propa-

gation delay through the device is virtually eliminated. The PLL

aligns the feedback clock output edge with the clock input ref-

erence edge resulting a near zero delay through the device.

The maximum insertion delay of the device in zero-delay ap-

plications is measured between the reference clock input and

any output. This effective delay consists of the static phase

offset, I/O jitter (phase or long-term jitter), feedback path delay

and the output-to-output skew error relative to the feedback

output.

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Calculation of part-to-part skew

The MPC961C zero delay buffer supports applications

where critical clock signal timing can be maintained across

several devices. If the reference clock inputs of two or more

MPC961C are connected together, the maximum overall tim-

ing uncertainty from the common CCLK input to any output is:

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Figure 5. Single versus Dual Waveforms

t_SK(PP)= t _∅+ t_SK(O)+ t_{PD, LINE(FB)}+ t_JIT(ꢁ CF

∅

)

(

)

This maximum timing uncertainty consist of 4 components:

static phase offset, output skew, feedback board trace delay

and I/O (phase) jitter:

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the situation

in Figure 6 should be used. In this case the series terminating

resistors are reduced such that when the parallel combination

is added to the output buffer impedance the line impedance is

perfectly matched.

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14Ω + 22Ω ꢀ 22Ω = 50Ω ꢀ 50Ω

25Ω = 25Ω

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Figure 6. Optimized Dual Line Termination

Figure 7. MPC961C max. device-to-device skew

Due to the statistical nature of I/O jitter a rms value (1 s) is

SPICE level and IBIS output buffer models are available for

engineers who want to simulate their specific interconnect specified. I/O jitter numbers for other confidence factors (CF)

schemes. can be derived from Table 8.

482

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MPC961C

output loading, ambient temperature, vertical convection and

thermal conductivity of package and board. This section de-

scribes the impact of these parameters on the junction temper-

ature and gives a guideline to estimate the MPC961C die junc-

tion temperature and the associated device reliability. For a

complete analysis of power consumption as a function of oper-

ating conditions and associated long term device reliability

please refer to the application note AN1545. According the

AN1545, the long-term device reliability is a function of the die

junction temperature:

Table 8: Confidence Facter CF

Probability of clock edge within the distribution

0.68268948

0.95449988

0.99730007

0.99993663

0.99999943

0.99999999

The feedback trace delay is determined by the board layout

and can be used to fine-tune the effective delay through each

device. In the following example calculation a I/O jitter confi-

dence factor of 99.7% ( 3s) is assumed, resulting in a worst

case timing uncertainty from input to any output of -275 ps to

315 ps relative to CCLK:

Table 9: Die junction temperature and MTBF

Junction temperature (°C)

MTBF (Years)

100

110

120

130

20.4

9.1

4.2

2.0

t_SK(PP)

[–80ps...120ps] + [–150ps...150ps] +

[(15ps @ –3)...(15ps @ 3)] + t_{PD, LINE(FB)}

Increased power consumption will increase the die junction

temperature and impact the device reliability (MTBF). Accord-

ing to the system-defined tolerable MTBF, the die junction tem-

perature of the MPC961C needs to be controlled and the ther-

mal impedance of the board/package should be optimized.

The power dissipated in the MPC961C is represented in equa-

tion 1.

t_SK(PP)

[–275ps...315ps] + t_{PD, LINE(FB)}

Due to the frequency dependence of the I/O jitter, Figure 8

“Max. I/O Jitter versus frequency” can be used for a more pre-

cise timing performance analysis.

Where I_CCQis the static current consumption of the

MPC961C, C_PDis the power dissipation capacitance per out-

put, (Μ)ΣC_Lrepresents the external capacitive output load, N

is the number of active outputs (N is always 27 in case of the

MPC961C). The MPC961C supports driving transmission

lines to maintain high signal integrity and tight timing parame-

ters. Any transmission line will hide the lumped capacitive load

at the end of the board trace, therefore, ΣC_Lis zero for con-

trolled transmission line systems and can be eliminated from

equation 1. Using parallel termination output termination re-

sults in equation 2 for power dissipation.

In equation 2, P stands for the number of outputs with a

parallel or thevenin termination, V_OL, I_OL, V_OHand I_OHare a

function of the output termination technique and DC_Qis the

clock signal duty cyle. If transmission lines are used ΣC_Lis

zero in equation 2 and can be eliminated. In general, the use of

Figure 8. Max. I/O Jitter versus frequency

Power Consumption of the MPC961C and Thermal Man-

agement

The MPC961C AC specification is guaranteed for the entire controlled transmission line techniques eliminates the impact

operating frequency range up to 200 MHz. The MPC961C of the lumped capacitive loads at the end lines and greatly

power consumption and the associated long-term reliability reduces the power dissipation of the device. Equation 3 de-

may decrease the maximum frequency limit, depending on op- scribes the die junction temperature T_Jas a function of the

erating conditions such as clock frequency, supply voltage, power consumption.

₎ȍ

P_TOT

_CCQ) V_CC@ f_CLOCK

N @ C_PD

C_L

@ V

Equation 1

ǒ Ǔ

DC_Q@ I_OH@ V_CC* V_OH) 1 * DC_Q@ I_OL@ V_OL

₎ȍ

P_TOT+ V_CC

_CCQ) V_CC@ f_CLOCK

N @ C_PD

C_L

Equation 2

T_J+ T_A) P_TOT@ R_thja

Equation 3

Equation 4

T_J,MAX* T_A

_@ƪ

f_CLOCK,MAX

* I_CCQ@ V_CC

C_PD@ N @ V_C²_C

R_thja

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

483

For More Information On This Product,

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Freescale Semiconductor, Inc.

MPC961C

Where R_thjais the thermal impedance of the package (junc-

T_J,MAXshould be selected according to the MTBF system

tion to ambient) and T_Ais the ambient temperature. According requirements and Table 9. R_thjacan be derived from Table 10.

to Table 9, the junction temperature can be used to estimate The R_thjarepresent data based on 1S2P boards, using 2S2P

the long-term device reliability. Further, combining equation 1 boards will result in a lower thermal impedance than indicated

and equation 2 results in a maximum operating frequency for below.

the MPC961C in a series terminated transmission line system.

If the calculated maximum frequency is below 200 MHz, it

becomes the upper clock speed limit for the given application

Table 10: Thermal package impedance of the 32ld

LQFP

conditions. The following two derating charts describe the safe

frequency operation range for the MPC961C. The charts were

calculated for a maximum tolerable die junction temperature of

110°C, corresponding to an estimated MTBF of 9.1 years, a

supply voltage of 3.3V and series terminated transmission line

or capacitive loading. Depending on a given set of these oper-

ating conditions and the available device convection a decision

on the maximum operating frequency can be made. There are

no operating frequency limitations if a 2.5V power supply or the

system specifications allow for a MTBF of 4 years (corre-

sponding to a max. junction temperature of 120°C.

Convection, LFPM

Still air

(1P2S board), K/W

thja

100 lfpm

200 lfpm

300 lfpm

400 lfpm

500 lfpm

ꢒ ꢉ

ꢊ ꢵ

ꢊ ꢕ

ꢊ ꢋ

ꢊ ꢒ

ꢊ ꢉ

ꢵ

ꢕ

ꢋ

ꢒ

ꢉ

ꢒ

ꢊ

ꢉ

ꢵ

ꢕ

ꢋ

ꢒ

ꢉ

ꢵ

ꢕ

ꢋ

ꢒ

ꢉ

ꢗ

ꢺ

ꢏ

ꢀ

ꢻ

ꢗ

ꢺꢏ ꢀꢻ

ꢏ ꣄

ꢙ

ꢏ

꣄

ꢙ

ꢜ

ꢏ

ꢶ

ꢵ

ꢔ

ꢀ

ꢜ ꢶ ꢴ ꢔ°ꢀ

ꢏ

ꢜ

ꢏ

ꢶ

ꢵ

ꢔ

ꢀ

Safe operation

ꢉ

ꢔ

ꢉ

ꢋ

ꢉ

ꢓ

ꢉ

ꢒ

ꢉ

ꢊ

ꢉ

ꢔ

ꢉ

ꢋ

ꢉ

ꢓ

ꢉ

ꢒ

ꢉ

ꢊ

ꢉ

ꢆ

ꢃ

ꢽ ꢀꢌ ꢇꢮ ꢑ ꢀꢜꢆ ꢌ ꢇ

ꢙ

ꢆ

ꢃ

ꢽ ꢀꢌ ꢇ ꢮꢑ ꢀꢜꢆ ꢌ ꢇ

ꢙ

ꢍ

Figure 9. Maximum MPC961C frequency, V_CC= 3.3V, MTBF

9.1 years, driving series terminated transmission lines

Figure 10. Maximum MPC961C frequency,

_CC= 3.3V, MTBF 9.1 years, 4 pF load per line

ꢙ

ꢍ

ꢀ

ꢞ

ꢕ

ꢊ

ꢀ

ꢳ

ꢷ

ꢜ

ꢍ ꢡꢨꢣꢖ

ꢐ ꢖꢥꢖ ꢟꢤꢧ ꢩ ꢟ

ꢹ

ꢶ

ꢔ

ꢉ

Ω

ꢹ ꢶ ꢔ ꢉ Ω

ꢌ

ꢹ

ꢶ

ꢔ

ꢉ

ꢎ

ꢜ

ꢶ

ꢔ

ꢉ

Ω

ꢎ ꢶ ꢔ ꢉΩ

ꢜ

ꢮ

ꢜ

ꢮ

ꢜ ꢜ

ꢜ

Figure 11. TCLK MPC961C AC test reference for V_cc= 3.3V and V_cc= 2.5V

484

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC961C

ꢮ

ꢀ

ꢮ

ꢀ

Bꢒ

ꢀ

ꢁ

ꢂ

ꢒ

ꢀ

ꢐ ꢇꢳ

ꢐ

ꢮ

ꢇ

ꢳ

ꢮ

ꢌ

ꢚ

ꢀ

ꢒ

ꢀ

ꢮ

ꢀ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢐ

ꢇ

ꢳ

ꢐ

ꢇ

ꢳ

ꢧ

ꢸ ꢂ ꢺ ꢌ ꢻ

ꢧ

∅

ꢺ

ꢻ

ꢜ

ꢝ

ꢤ

ꢖ

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ꢫ

ꢢ

ꢥ

ꢘ

ꢱ

ꢧ

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ꢘ

ꢤ

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ꢭ

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꣆

ꢣ

ꢲ

ꢬ

ꢖ

ꢬ

ꢖ

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ꢧ

ꢱ

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ꢖ

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ꢭ

ꢩ

ꢫ

ꢟ

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ꢣ

ꢧ

ꢰ

ꢝ

ꢤ

ꢬ

ꢣ

ꢖ

ꢝ

ꢱ

ꢢ

ꢗ

ꢤ

ꢗ

ꢖ

ꢣ

ꢟ

ꢖ

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ꢪ

ꢰ

ꢨ

ꢖ

ꢢ

ꢱ

ꢥ

ꢖ

ꢫ

ꣂ

ꢟ

ꢩ

ꢖ

ꢫ

ꣅ

ꢤ

ꢪ

ꢢ

ꢩ

ꢖꢧ

ꢤ

ꢥ

ꢢ

ꣁ

ꢢ

ꢨ

ꢤ

ꢨ

ꢤ

ꢢ

ꢧ

ꢢ

ꢥ

ꢢ

ꢥ

ꢢꢰ

Figure 12. Output–to–output Skew t_SK(O)

Figure 13. Propagation delay (t_PD, static phase

offset) test reference

ꢮ

ꢀ

Bꢒ

ꢀꢀ ꢁꢂ

ꢀ

ꢐ

ꢇ

ꢳ

ꢧ

ꢍ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢜ

ꢉ

ꢀ

ꢁ

ꢂ

ꢃ

ꢅ

ꢆ

ꢦ

ꢈ

ꢇ

ꢉ

ꢄ

ꢇ

ꢆ

ꢊ ꢋꢆ

ꢂ ꣇ꢆ ꢍ ꢆ ꢎꢏ ꢐ ꢑ꣇

ꢇ ꢈ

〈∅

ꢌ

ꢜ

ꢝ

ꣂ

ꢖ

ꢧ

ꢖ

ꢢ

ꣁ

ꢱ

ꢖ

꣆

ꢗ

ꢭ

ꢟ

ꢩ

ꣁ

ꢖ

ꢧ

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ꢖ

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꣆

ꢁ

ꢖ

ꢁ

ꢧ

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ꢩ

ꢖ

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ꢖ

ꢧ

ꢥ

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ꢍ

ꢨ

ꢁ

ꢖ

ꢁ

ꢱ

ꢖ

ꢱ

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ꢪ

ꢧ

ꢖ

ꢧ

ꢨ

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ꢧ

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ꢩ

ꢖ

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ꢣ

ꢰ

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ꢩ

ꢖ

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ꢦ

ꢧ

ꢫ

ꢟ

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ꢨ

ꢣ

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ꢣ

ꢱ

ꢖ

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ꢤ

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ꢖ

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ꢖ

ꣁ

ꣂ

ꢢ

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ꢤ

ꢧ

ꢢ

ꣁ

ꢩ

ꢥ

ꢫ

ꢢ

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ꢧ

ꢩ

ꢗ

ꢰ

ꢩ

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ꢟ

ꢰ

ꢤ

ꢰ

ꢣ

ꢩ

ꢥ

ꢧ

ꢟ

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ꢨ

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ꢖ

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ꢢ

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ꢫ

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ꢢ

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ꢨ

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ꢨ

ꢖ

ꢫ

ꢖ

ꢟ

ꢰ

ꢖ

ꢥ

ꢧ

ꢤ

ꢪ

ꢖ

Figure 14. Output Duty Cycle (DC)

Figure 15. I/O Jitter

ꢆ

ꢂ

꣇ꢆ ꢍ ꢆ

꣇

ꢆ

ꢂ

꣇ꢆ ꢍ ꢈ ꣉ꢗ

ꢓ ꢇ

꣇

ꢊ

ꢋ

ꢆ

ꢒ

ꢁ

ꢌ

ꢓ

ꢔ

ꢈ

ꢊ

ꢋ

ꢆ

ꢒ

ꢄ

ꢕ

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ꢜ

ꢇ ꢿ ꢊ

ꢜ

ꢇ

ꢉ

ꢜ

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ꢥ

ꢖ

ꢱ

ꣂ

ꢩ

ꢤ

ꣁ

ꢟ

ꢢ

ꢤ

ꢣ

ꢧ

ꢤ

ꢢ

ꢩ

ꣁ

ꢥ

ꢫ

ꢢ

ꢨ

ꢥ

ꢖ

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ꢩ

ꢭ

ꢗ

ꢰ

ꢤ

ꢨ

ꢱ

ꢖ

꣈

ꢧ

ꢤ

ꢢ

ꣁ

ꢖ

ꢥ

ꢩ

ꢗ

ꢤ

ꢣ

ꢢ

ꢪ

ꢫ

ꢥ

ꢤ

ꢢ

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ꢟ

꣆

ꢣ

ꢖ

ꢧ

ꢬ

ꢖ

ꢥ

ꢤ

ꢱ

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ꢤ

ꢰ

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ꢰ

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ꢰ

ꢨ

ꢖ

ꢣ

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ꢩ

ꣂ

ꢖ

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ꢤ

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ꢤ

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ꣂ

ꣁ

ꢢ

ꢤ

ꢧ

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ꣁ

ꢢ

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ꢰ

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ꢢ

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ꢣ

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ꢗ

ꢤ

ꢣ

ꢢ

ꢪ

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ꢤ

ꢨ

ꢬ

ꢢ

ꢧ

ꢝ

ꢟ

ꢖ

ꢣ

ꢫ

ꢖ

ꢰ

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ꢧ

ꢝ

ꢖ

ꢢ

ꢱ

ꢖ

ꢤ

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ꢫ

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ꢱ

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ꣂ

ꢖ

ꢟ

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ꢰ

ꢖ

ꢧ

ꢰ

ꢭ

ꢰ

ꢨ

ꢖ

ꢥ

ꢱ

ꢭ

ꢰ

ꢨ

ꢖ

Figure 16. Cycle–to–cycle Jitter

Figure 17. Period Jitter

ꢮ

ꢀ

ꢶ

ꢓ

ꢯ

ꢓ

ꢮ

ꢀ

ꢶ

ꢒ

ꢯ

ꢔ

ꢮ

ꢀ

ꢒ

ꢯ

ꢋ

ꢊ

ꢯ

ꢵ

ꢮ

ꢉ

ꢯ

ꢔ

ꢉ

ꢯ

ꢕ

ꢮ

ꢧ

ꢃ

ꢧ

ꢎ

Figure 18. Output Transition Time Test

Reference

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

485

For More Information On This Product,

Go to: www.freescale.com

MPC961CFAR2 [NXP]

相关型号：

MPC961PAC

MPC961PACR2

MPC961PFA

MPC961PFAR2

MPC961PFAR2

MPC962305

MPC962305D-1

MPC962305D-1

MPC962305D-1

MPC962305D-1H

MPC962305D-1H

MPC962305D-1H