MPC9774AE_技术文档

Freescale Semiconductor, Inc.

TECHNICAL DATA

Order number: MPC9774

Rev 3, 08/2004

3.3 V 1:14 LVCMOS PLL Clock

Generator

MPC9774

The MPC9774 is a 3.3V compatible, 1:14 PLL based clock generator

targeted for high performance low-skew clock distribution in mid-range to

high-performance networking, computing and telecom applications. With

output frequencies up to 125 MHz and output skews less than 175 ps the device

meets the needs of the most demanding clock applications.

3.3 V 1:14 LVCMOS

PLL CLOCK GENERATOR

Features

•

1:14 PLL based low-voltage clock generator

3.3 V power supply

Internal power-on reset

FA SUFFIX

52-LEAD LQFP PACKAGE

CASE 848D-03

Generates clock signals up to 125 MHz

Maximum output skew of 175 ps

Two LVCMOS PLL reference clock inputs

External PLL feedback supports zero-delay capability

Various feedback and output dividers (see APPLICATIONS

INFORMATION)

•

Supports up to three individual generated output clock frequencies

Drives up to 28 clock lines

Ambient temperature range 0°C to +70°C

Pin and function compatible to the MPC974

52-lead Pb-free Package Available

Functional Description

The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The

reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the

VCO frequency range.

The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input relation-

ships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate configurable

feedback output which allows for a wide variety of input/output frequency multiplication alternatives. The VCO_SEL pin provides an

extended PLL input reference frequency range.

The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alter-

native LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass con-

figuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers

bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do

not apply.

The MPC9774 has an internal power-on reset.

The MPC9774 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS

signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series

terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the devices an effective fanout of 1:12.

The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package.

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FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

MPC9774

All input resistors have a value of 25 kΩ

QA0

QA1

QA2

QA3

QA4

V_CC

BANK A

÷ 2

÷ 4

0

1

0

1

CCLK0

CLK

STOP

0

1

÷ 2, ÷ 4

Ref

VCO

CCLK1

CCLK_SEL

PLL

200–500 MHz

÷ 4, ÷ 6

÷ 4, ÷ 6, ÷ 8, ÷ 12

BANK B

QB0

QB1

QB2

QB3

QB4

V_CC

CLK

STOP

FB

FB_IN

PLL_EN

VCO_SEL

FSEL_A

FSEL_B

FSEL_C

FSEL_FB[1:0]

2

QC0

QC1

QC2

QC3

BANK C

CLK

STOP

V_CC

CLK_STOP

MR/OE

V_CC

POWER-ON RESET

QFB

Figure 1. MPC9774 Logic Diagram

39 38 37 36 35 34 33 32 31 30 29 28 27

QB0

V_CC

NC

V_CC

40

26

25

24

23

22

21

20

19

18

17

16

15

14

QA0

41

42

43

44

45

46

47

48

49

50

51

52

GND

QC3

QA1

V_CC

QA2

QC2

FSEL_FB1

GND

MPC9774

GND

QC1

QA3

V_CC

QC0

QA4

GND

VCO_SEL

FSEL_FB0

1

2

3

4

5

6

7

8

9 10 11 12 13

Figure 2. MPC9774 52-Lead Package Pinout (Top View)

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

225

MPC9774

Table 1. Pin Configuration

I/O

Type

Function

CCLK0

CCLK1

FB_IN

Input

LVCMOS

Ground

PLL reference clock

Input

Alternative PLL reference clock

PLL feedback signal input, connect to QFB

LVCMOS clock reference select

VCO operating frequency select

PLL enable/PLL bypass mode select

Input

CCLK_SEL

VCO_SEL

PLL_EN

MR/OE

Input

Output enable/disable (high-impedance tristate) and device reset

Output enable/clock stop (logic low state)

Frequency divider select for bank A outputs

Frequency divider select for bank B outputs

Frequency divider select for bank C outputs

Frequency divider select for the QFB output

Clock outputs (Bank A)

CLK_STOP

FSEL_A

FSEL_B

FSEL_C

FSEL_FB[1:0]

QA[4:0]

Input

Output

Supply

QB[4:0]

Clock outputs (Bank B)

QC[3:0]

Clock outputs (Bank C)

QFB

PLL feedback output. Connect to FB_IN.

Negative power supply

GND

V_{CC_PLL}

V_CC

PLL positive power supply (analog power supply). It is recommended to use an external RC filter

for the analog power supply pin V_{CC_PLL.}Please see applications section for details.

V_CC

Supply

V_CC

Positive power supply for I/O and core. All V_CCpins must be connected to the positive power

supply for correct operation

Table 2. Function Table (Configuration Controls)

Control

CCLK_SEL

VCO_SEL

Default

0

1

0

Selects CCLK0 as PLL references signal input

Selects CCKL1 as PLL reference signal input

Selects VCO ÷ 2. The VCO frequency is scaled by a factor of 2 (high input Selects VCO ÷ 4. The VCO frequency is

frequency range)

scaled by a factor of 4 (low input frequency

range).

PLL_EN

CLK_STOP

MR/OE

1

Test mode with the PLL bypassed. The reference clock is substituted for the Normal operation mode with PLL enabled.

internal VCO output. MPC9774 is fully static and no minimum frequency limit

applies. All PLL related AC characteristics are not applicable.

QA, QB an QC outputs disabled in logic low state. QFB is not affected by

CLK_STOP. CLK_STOP deassertion may cause the initial output clock pulse

to be distorted.

Outputs enabled (active)

Outputs disabled (high-impedance state) and reset of the device. During

reset/output disable the PLL feedback loop is open and the internal VCO is

tied to its lowest frequency. The MPC9774 requires reset after any loss of

PLL lock. Loss of PLL lock may occur when the external feedback path is

interrupted. The length of the reset pulse should be greater than one

reference clock cycle (CCLKx). The device is reset by the internal power-on

reset (POR) circuitry during power-up.

VCO_SEL, FSEL_A, FSEL_B, FSEL_C and FSEL_FB[1:0] control the operating PLL frequency range and input/output frequency ratios.

See Table 3 and Table 4 for the device frequency configuration.

Table 3. Function Table (Output Dividers Bank A, B, and C)

VCO_SEL

FSEL_A

QA[4:0]

VCO ÷ 4

VCO ÷ 8

VCO ÷ 16

VCO_SEL

FSEL_B

QB[4:0]

VCO ÷ 4

VCO ÷ 8

VCO ÷ 16

VCO_SEL

FSEL_C

QC[3:0]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VCO ÷ 8

VCO ÷ 12

VCO ÷ 16

VCO ÷ 24

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FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

MPC9774

Table 4. Function Table (QFB)

VCO_SEL

FSEL_B1

FSEL_B0

QFB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VCO ÷ 8

VCO ÷ 16

VCO ÷ 12

VCO ÷ 24

VCO ÷ 16

VCO ÷ 32

VCO ÷ 24

VCO ÷ 48

Table 5. General Specifications

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

V_TT

Output Termination Voltage

V

_CC÷ 2

V

MM

HBM

LU

ESD protection (Machine Model)

ESD protection (Human Body Model)

Latch-Up Immunity

200

2000

200

V

mA

C_PD

Power Dissipation Capacitance

12

pF Per output

pF Inputs

C_IN

Input Capacitance

4.0

Table 6. Absolute Maximum Ratings¹

Symbol

Characteristics

Min

Max

Unit

Condition

V_CC

Supply Voltage

–0.3

3.9

V

V_IN

V_OUT

I_IN

DC Input Voltage

DC Output Voltage

DC Input Current

DC Output Current

Storage Temperature

–0.3

V_CC+ 0.3

±20

V

mA

°C

I_OUT

T_S

±50

–65

125

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions

or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not

implied.

Table 7. DC Characteristics (V_CC= 3.3 V ± 5%, T_A= 0°C to +70°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

LVCMOS

V_{CC_PLL}PLL Supply Voltage

3.02

V_CC

V

V_IH

V_IL

Input High Voltage

Input Low Voltage

Output High Voltage

2.0

2.4

V_CC+ 0.3

0.8

V

LVCMOS

I_OH= –24 mA¹

V_OH

V_OL

Output Low Voltage

0.55

0.30

V

I_OL= 24 mA

I

_OL= 12 mA

Z_OUT

I_IN

I_{CC_PLL}

I_CCQ

Output Impedance

14 – 17

5.0

Ω

Input Current²

±200

7.5

µA V_IN= V_CCor GND

mA V_{CC_PLL}Pin

Maximum PLL Supply Current

Maximum Quiescent Supply Current

8.0

mA All V_CCPins

1. The MPC9774 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission

line to a termination voltage of V_TT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines.

2. Inputs have pull-down or pull-up resistors affecting the input current.

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

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MPC9774

Table 8. AC Characteristics (V_CC= 3.3 V ± 5%, T_A= 0°C to +70°C)¹

Symbol

f_REF

Characteristics

Input Reference Frequency

Min

Typ

Max

Unit

Condition

÷ 8 feedback

÷ 12 feedback

÷ 16 feedback

÷ 24 feedback

÷ 32 feedback

÷ 48 feedback

25.0

16.6

12.5

8.33

6.25

4.16

62.5

41.6

31.25

20.83

15.625

10.41

MHz PLL locked

MHz

MHz PLL bypass

MHz

Input Reference Frequency in PLL Bypass Mode²

VCO Frequency Range³

250

500

MHz

f_VCO

f_MAX

200

Output Frequency

÷ 4 output

÷ 8 output

50.0

25.0

16.6

12.5

8.33

125.0

62.5

41.6

31.25

20.83

MHz PLL locked

MHz

÷ 12 output

÷ 16 output

÷ 24 output

Input Reference Pulse Width⁴

CCLKx Input Rise/Fall Time

t_PW,MIN

t_R, t_F

t_(∅)

2.0

ns

1.0

ns

0.8 to 2.0V

PLL locked

Propagation Delay (static phase offset)⁵

–250

+100

ps

CCLKx to FB_IN (FB = ÷ 8 and f_REF= 50 MHz)

Output-to-Output Skew⁶

within QA bank

within QB bank

within QC bank

any output

t_SK(O)

100

125

100

175

ps

DC

Output Duty Cycle

47

50

53

%

t_R, t_F

Output Rise/Fall Time

0.1

1.0

ns

0.55 to 2.4V

t_{PLZ, HZ}

t_PZL

Output Disable Time

Output Enable Time

10

90

ns

ps

Cycle-to-Cycle Jitter⁷

Period Jitter⁶

t_JIT(CC)

t_JIT(PER)

t_JIT(∅)

I/O Phase Jitter RMS (1 σ)⁸

FB = ÷ 8

FB = ÷ 12

FB = ÷ 16

FB = ÷ 24

FB = ÷ 32

FB = ÷ 48

15

49

18

22

26

34

ps

PLL Closed Loop Bandwidth⁹

FB = ÷ 8

FB = ÷ 12

FB = ÷ 16

FB = ÷ 24

FB = ÷ 32

FB = ÷ 48

BW

0.50 – 1.80

0.30 – 1.00

0.25 – 0.70

0.17 – 0.40

0.12 – 0.30

0.07 – 0.20

MHz

MHZ

MHz

t_LOCK

Maximum PLL Lock Time

10

ms

1. AC characteristics apply for parallel output termination of 50 Ω to V_TT

.

2. In bypass mode, the MPC9774 divides the input reference clock.

3. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio (FB): f_REF= f_VCO÷ (M ⋅ VCO_SEL).

4. Calculation of reference duty cycle limits: DC_REF,MIN= t_PW,MIN⋅ f_REF⋅ 100% and DC_REF,MAX= 100% – DC_REF,MIN.E.g. at f_REF= 62.5 MHz the

input duty cycle range is 12.5% < DC < 87.5%.

5. Static phase offset depends on the reference frequency: t_(∅)= +50 ps ± (1÷(120 ⋅ f_REF)) for any reference frequency.

6. Refer to Application section for part-to-part skew calculation.

7. Valid for all outputs at the same frequency.

8. I/O jitter for f_VCO= 400 MHz. Refer to APPLICATIONS INFORMATION for I/O jitter at other frequencies and for a jitter calculation for confidence

factors other than 1 σ.

9. –3 dB point of PLL transfer characteristics.

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MPC9774

APPLICATIONS INFORMATION

MPC9774 Configurations

VCO_SEL pin. VCO_SEL effectively extends the usable input

frequency range while it has no effect on the output to reference

frequency ratio. The output frequency for each bank can be

derived from the VCO frequency and output divider:

f_QA[4:0]= f_VCO÷ (VCO_SEL ⋅ N_A)

Configuring the MPC9774 amounts to properly configuring

the internal dividers to produce the desired output frequencies.

The output frequency can be represented by this formula:

f_OUT= f_REF⋅ M ÷ N

f_QB[4:0]= f_VCO÷ (VCO_SEL ⋅ N_B)

f_QC[3:0]= f_VCO÷ (VCO_SEL ⋅ N_C)

f_OUT

f_REF

÷ VCO_SEL

PLL

÷ N

Table 9. MPC9774 Divider

Divider

Function

VCO_SEL

÷ 2

Values

8, 12, 16, 24

16, 24, 32, 48

4, 8

÷ M

M

PLL Feedback

FSEL_FB[0:1]

÷ 4

where f_REFis the reference frequency of the selected input

clock source (CCLK0 or CCLK1), M is the PLL feedback divider

and N is a output divider. M is configured by the FSEL_FB[0:1]

and N is individually configured for each output bank by the

FSEL_A, FSEL_B and FSEL_C inputs.

The reference frequency f_REFand the selection of the

feedback-divider M is limited by the specified VCO frequency

range. f_REFand M must be configured to match the VCO

frequency range of 200 to 500 MHz in order to achieve stable

PLL operation:

N_A

N_B

N_C

Bank A Output

Divider FSEL_A

÷ 2

÷ 4

8, 16

Bank B Output

Divider FSEL_B

÷ 2

4, 8

÷ 4

8, 16

Bank C Output

Divider FSEL_C

÷ 2

8, 12

÷ 4

16, 24

Table 9 shows the various PLL feedback and output dividers.

The output dividers for the three output banks allow the user to

configure the outputs into 1:1, 2:1, 3:2, and 3:2:1 frequency

ratios. Figure 3 and Figure 4 display example configurations for

the MPC9774.

f

_VCO,MIN≤ (f_REF⋅ VCO_SEL ⋅ M) ≤ f_VCO,MAX

The PLL post-divider VCO_SEL is either a divide-by-two or

a divide-by-four and can be used to situate the VCO into the

specified frequency range. This divider is controlled by the

Figure 3. Example Configuration

Figure 4. Example Configuration

f_REF= 20.83 MHz

CCLK0

f_REF= 25 MHz

QA[4:0]

QB[4:0]

QC[3:0]

QFB

125 MHz

62.5 MHz

QA[4:0]

QB[4:0]

QC[3:0]

QFB

100 MHz

50 MHz

CCLK1

CCLK_SEL

0

CCLK_SEL

VCO_SEL

FB_IN

VCO_SEL

FB_IN

FSEL_A

FSEL_B

FSEL_C

FSEL_FB[1:0]

0

1

0

62.5 MHz

FSEL_A

FSEL_B

FSEL_C

FSEL_FB[1:0]

0

1

33.3 MHz

11

01

MPC9774

20.83 MHz (Feedback)

25 MHz (Feedback)

MPC9774 example configuration (feedback of

QFB = 20.83 MHz, VCO_SEL = ÷ 2, M = 12,

N_A= 2, N_B= 4, N_C= 4, f_VCO= 500 MHz).

MPC9774 example configuration (feedback of

QFB = 25 MHz, VCO_SEL = ÷ 2, M = 8, N_A= 2,

N_B= 4, N_C= 6, f_VCO= 400 MHz).

Frequency Range

Input

Min

Max

Frequency Range

Input

Min

Max

8.33 MHz

50 MHz

25 MHz

20.83 MHz

125 MHz

62.5 MHz

20 MHz

50 MHz

100 MHz

48 MHz

120 MHz

200 MHz

QA outputs

QB outputs

QC outputs

QA outputs

QB outputs

QC outputs

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

229

MPC9774

Using the MPC9774 in Zero-Delay Applications

Table 10. Confidence Factor CF

Nested clock trees are typical applications for the MPC9774.

Designs using the MPC9774 as LVCMOS PLL fanout buffer

with zero insertion delay will show significantly lower clock skew

than clock distributions developed from CMOS fanout buffers.

The external feedback of the MPC9774 clock driver allows for

its use as a zero delay buffer. The PLL aligns the feedback clock

output edge with the clock input reference edge resulting a near

zero delay through the device (the propagation delay through

the device is virtually eliminated). The maximum insertion delay

of the device in zero-delay applications is measured between

the reference clock input and any output. This effective delay

consists of the static phase offset, I/O jitter (phase or long-term

jitter), feedback path delay and the output-to-output skew error

relative to the feedback output.

CF

Probability of Clock Edge within the Distribution

± 1σ

± 2σ

± 3σ

± 4σ

± 5σ

± 6σ

0.68268948

0.95449988

0.99730007

0.99993663

0.99999943

0.99999999

Due to the frequency dependence of the static phase offset

and I/O jitter, using Figure 6 and Figure 7 to predict a maximum

I/O jitter and the specified t₍_∅₎parameter relative to the input

reference frequency results in a precise timing performance

analysis.

In the following example calculation a I/O jitter confidence

factor of 99.7% (± 3σ) is assumed, resulting in a worst case

timing uncertainty from the common input reference clock to

any output of –470 ps to +320 ps relative to CCLK (PLL

feedback = ÷ 8, reference frequency = 50 MHz, VCO

frequency = 400 MHz, I/O jitter = 15 ps RMS max., static phase

offset t₍_∅₎= –250 ps to +100 ps):

Calculation of Part-to-Part Skew

The MPC9774 zero delay buffer supports applications where

critical clock signal timing can be maintained across several

devices. If the reference clock inputs of two or more MPC9774

are connected together, the maximum overall timing uncertainty

from the common CCLK input to any output is:

t_SK(PP)= t_(∅)+ t_SK(O)+ t_{PD, LINE(FB)}+ t_JIT(∅)⋅ CF

t_SK(PP)= [–250 ps...+100 ps] + [-175 ps...175 ps] +

[(15 ps • –3)...(15 ps • 3)] + t_{PD, LINE(FB)}

This maximum timing uncertainty consist of 4 components:

static phase offset, output skew, feedback board trace delay

and I/O (phase) jitter:

t_SK(PP)= [–470 ps...+320 ps] + t_{PD, LINE(FB)}

Maximum I/O Phase Jitter (RMS) versus Frequency Parameter:

PLL Feedback Divider FB

100

CCLK_Common

t_PD,LINE(FB)

–t_(∅)

80

FB = ÷ 32

60

FB = ÷ 16

QFB_{Device 1}

40

t_JIT(∅)

FB = ÷ 8

20

Any Q_{Device 1}

±t_SK(O)

0

200

250

300

350

400

450

500

VCO Frequency [MHz]

+t_(∅)

Figure 6. MPC9774 I/O Jitter

QFB_Device2

t_JIT(∅)

Maximum I/O Phase Jitter (RMS) versus Frequency Parameter:

PLL Feedback Divider FB

Any Q_{Device 2}

160

140

120

100

80

±t_SK(O)

FB = ÷ 12

Max. skew

t_SK(PP)

FB = ÷ 48

FB = ÷ 24

Figure 5. MPC9774 Maximum Device-to-Device Skew

60

40

Due to the statistical nature of I/O jitter a RMS value (1 σ) is

specified. I/O jitter numbers for other confidence factors (CF)

can be derived from Table 10.

The feedback trace delay is determined by the board layout

and can be used to fine-tune the effective delay through each

device.

20

0

200

250

300

350

400

450

500

VCO Frequency [MHz]

Figure 7. MPC9774 I/O Jitter

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FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

MPC9774

Driving Transmission Lines

the parallel combination of the line impedances. The voltage

wave launched down the two lines will equal:

V_L= V_S(Z₀÷ (R_S+ R₀+ Z₀))

The MPC9774 clock driver was designed to drive high speed

signals in a terminated transmission line environment. To

provide the optimum flexibility to the user the output drivers

were designed to exhibit the lowest impedance possible. With

an output impedance of less than 20 Ω the drivers can drive

either parallel or series terminated transmission lines. For more

information on transmission lines the reader is referred to

Motorola application note AN1091. In most high performance

clock networks point-to-point distribution of signals is the

method of choice. In a point-to-point scheme either series

terminated or parallel terminated transmission lines can be

used. The parallel technique terminates the signal at the end of

the line with a 50 Ω resistance to V_CC÷ 2.

Z₀= 50 Ω || 50 Ω

R_S= 36 Ω || 36 Ω

R₀= 14 Ω

V_L= 3.0 (25 ÷ (18 + 17 + 25)

= 1.31 V

At the load end the voltage will double, due to the near unity

reflection coefficient, to 2.6 V. It will then increment towards the

quiescent 3.0 V in steps separated by one round trip delay (in

this case 4.0 ns).

3.0

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each output

of the MPC9774 clock driver. For the series terminated case

however there is no DC current draw, thus the outputs can drive

multiple series terminated lines. Figure 8 illustrates an output

driving a single series terminated line versus two series

terminated lines in parallel. When taken to its extreme the

fanout of the MPC9774 clock driver is effectively doubled due to

its capability to drive multiple lines.

OutA

t_D= 3.8956

OutB

t_D= 3.9386

2.5

2.0

1.5

1.0

0.5

0

In

MPC9774

OUTPUT

BUFFER

Z_O= 50 Ω

R_S= 36 Ω

14 Ω

IN

OutA

2

4

6

8

10

12

14

TIME (ns)

Figure 9. Single versus Dual Waveforms

MPC9774

OUTPUT

BUFFER

Z_O= 50 Ω

R_S= 36 Ω

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the situation

in Figure 10 should be used. In this case the series terminating

resistors are reduced such that when the parallel combination

is added to the output buffer impedance the line impedance is

perfectly matched.

OutB0

OutB1

14 Ω

Figure 8. Single versus Dual Transmission Lines

MPC9774

OUTPUT

BUFFER

The waveform plots in Figure 9 show the simulation results

of an output driving a single line versus two lines. In both cases

the drive capability of the MPC9774 output buffer is more than

sufficient to drive 50 Ω transmission lines on the incident edge.

Note from the delay measurements in the simulations a delta of

only 43 ps exists between the two differently loaded outputs.

This suggests that the dual line driving need not be used

exclusively to maintain the tight output-to-output skew of the

MPC9774. The output waveform in Figure 9 shows a step in the

waveform, this step is caused by the impedance mismatch seen

looking into the driver. The parallel combination of the 36 Ω

series resistor plus the output impedance does not match

Z

_O= 50 Ω

R_S= 22 Ω

14 Ω

Z_O= 50 Ω

14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω

25 Ω = 25 Ω

Figure 10. Optimized Dual Line Termination

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231

MPC9774

Power Supply Filtering

filter shown in Figure 11, the filter cut-off frequency is around

3–5 kHz and the noise attenuation at 100 kHz is better than

42 dB.

The MPC9774 is a mixed analog/digital product. Its analog

circuitry is naturally susceptible to random noise, especially if

this noise is seen on the power supply pins. Random noise on

the V_{CC_PLL}power supply impacts the device characteristics,

for instance I/O jitter. The MPC9774 provides separate power

supplies for the output buffers (V_CC) and the phase-locked loop

(V_{CC_PLL}) of the device.The purpose of this design technique is

to isolate the high switching noise digital outputs from the

relatively sensitive internal analog phase-locked loop. In a

digital system environment where it is more difficult to minimize

noise on the power supplies a second level of isolation may be

required. The simple but effective form of isolation is a power

supply filter on the V_{CC_PLL}pin for the MPC9774. Figure 11

illustrates a typical power supply filter scheme. The MPC9774

frequency and phase stability is most susceptible to noise with

spectral content in the 100 kHz to 20 MHz range. Therefore, the

filter should be designed to target this range. The key

parameter that needs to be met in the final filter design is the DC

voltage drop across the series filter resistor R_F. From the data

sheet the I_{CC_PLL}current (the current sourced through the

V_{CC_PLL}pin) is typically 5 mA (7.5 mA maximum), assuming

that a minimum of 3.02 V (V_{CC_PLL}, min) must be maintained on

the V_{CC_PLL}pin. The resistor R_Fshown in Figure 11 must have

a resistance of 5–15 Ω to meet the voltage drop criteria.

The minimum values for RF and the filter capacitor C_Fare

defined by the required filter characteristics: the RC filter

should provide an attenuation greater than 40 dB for noise

whose spectral content is above 100 kHz. In the example, RC

R_F= 5–15 Ω

C_F= 22 µF

R_F

V_{CC_PLL}

V_CC

C_F

10 nF

MPC9774

V_CC

33...100 nF

Figure 11. V_{CC_PLL}Power Supply Filter

As the noise frequency crosses the series resonant point of

an individual capacitor its overall impedance begins to look

inductive and thus increases with increasing frequency. The

parallel capacitor combination shown ensures that a low

impedance path to ground exists for frequencies well above the

bandwidth of the PLL. Although the MPC9774 has several

design features to minimize the susceptibility to power supply

noise (isolated power and grounds and fully differential PLL)

there still may be applications in which overall performance is

being degraded due to system power supply noise. The power

supply filter schemes discussed in this section should be

adequate to eliminate power supply noise related problems in

most designs.

MPC9774 DUT

Pulse

Z = 50 Ω

Generator

Z = 50 Ω

R_T= 50 Ω

V_TT

Figure 12. CCLK MPC9774 AC Test Reference

232

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

MPC9774

V_CC

V

_CC÷ 2

V_CC

V_CC÷ 2

GND

V_CC

CCLKx

FB_IN

GND

V_CC

V

_CC÷ 2

GND

V_CC÷ 2

t_SK(O)

GND

The pin-to-pin skew is defined as the worst case difference in propagation

delay between any similar delay path within a single device

t_(∅)

Figure 13. Output-to-Output Skew t_SK(O)

Figure 14. Propagation Delay (t_(∅), Static Phase

Offset) Test Reference

V_CC

CCLKx

V

_CC÷ 2

GND

t_P

FB_IN

T₀

DC = t_P/T₀x 100%

T_JIT(∅)= |T₀–T₁mean|

The time from the PLL controlled edge to the non controlled edge,

divided by the time between PLL controlled edges, expressed as

a percentage

The deviation in t₀for a controlled edge with respect to a t₀mean in a random

sample of cycles

Figure 15. Output Duty Cycle (DC)

Figure 16. I/O Jitter

T_JIT(CC)= |T_N–T_N+1

|

T_JIT(PER)= |T_N–1/f₀|

T_N

T_N+1

T₀

The variation in cycle time of a signal between adjacent cycles, over a random

sample of adjacent cycle pairs

The deviation in cycle time of a signal with respect to the ideal period over a

random sample of cycles

Figure 17. Cycle-to-Cycle Jitter

Figure 18. Period Jitter

V_CC= 3.3 V

2.4

0.55

t_F

t_R

Figure 19. Output Transition Time Test Reference

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

233


型号：	MPC9774AE
厂家：	NXP
描述：	9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLASTIC, LQFP-52 驱动输出元件逻辑集成电路
文件：	总10页 (文件大小：186K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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